2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Native 64-bit page table operations for running without a hypervisor.
100 #include <sys/param.h>
101 #include <sys/kernel.h>
103 #include <sys/lock.h>
104 #include <sys/mutex.h>
105 #include <sys/proc.h>
106 #include <sys/sched.h>
107 #include <sys/sysctl.h>
108 #include <sys/systm.h>
113 #include <vm/vm_param.h>
114 #include <vm/vm_kern.h>
115 #include <vm/vm_page.h>
116 #include <vm/vm_map.h>
117 #include <vm/vm_object.h>
118 #include <vm/vm_extern.h>
119 #include <vm/vm_pageout.h>
120 #include <vm/vm_pager.h>
122 #include <machine/md_var.h>
123 #include <machine/mmuvar.h>
125 #include "mmu_oea64.h"
127 #include "moea64_if.h"
129 #define PTESYNC() __asm __volatile("ptesync");
130 #define TLBSYNC() __asm __volatile("tlbsync; ptesync");
131 #define SYNC() __asm __volatile("sync");
132 #define EIEIO() __asm __volatile("eieio");
134 #define VSID_HASH_MASK 0x0000007fffffffffULL
137 * The tlbie instruction must be executed in 64-bit mode
138 * so we have to twiddle MSR[SF] around every invocation.
139 * Just to add to the fun, exceptions must be off as well
140 * so that we can't trap in 64-bit mode. What a pain.
142 static struct mtx tlbie_mutex;
145 TLBIE(uint64_t vpn) {
146 #ifndef __powerpc64__
147 register_t vpn_hi, vpn_lo;
152 vpn <<= ADDR_PIDX_SHFT;
153 vpn &= ~(0xffffULL << 48);
156 mtx_lock(&tlbie_mutex);
157 __asm __volatile("tlbie %0" :: "r"(vpn) : "memory");
158 mtx_unlock(&tlbie_mutex);
159 __asm __volatile("eieio; tlbsync; ptesync");
161 vpn_hi = (uint32_t)(vpn >> 32);
162 vpn_lo = (uint32_t)vpn;
164 /* Note: spin mutex is to disable exceptions while fiddling MSR */
165 mtx_lock_spin(&tlbie_mutex);
180 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1)
182 mtx_unlock_spin(&tlbie_mutex);
186 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
187 #define ENABLE_TRANS(msr) mtmsr(msr)
192 static struct lpteg *moea64_pteg_table;
197 static int moea64_pte_insert_native(mmu_t, u_int, struct lpte *);
198 static uintptr_t moea64_pvo_to_pte_native(mmu_t, const struct pvo_entry *);
199 static void moea64_pte_synch_native(mmu_t, uintptr_t pt,
200 struct lpte *pvo_pt);
201 static void moea64_pte_clear_native(mmu_t, uintptr_t pt,
202 struct lpte *pvo_pt, uint64_t vpn, uint64_t ptebit);
203 static void moea64_pte_change_native(mmu_t, uintptr_t pt,
204 struct lpte *pvo_pt, uint64_t vpn);
205 static void moea64_pte_unset_native(mmu_t mmu, uintptr_t pt,
206 struct lpte *pvo_pt, uint64_t vpn);
211 static void moea64_bootstrap_native(mmu_t mmup,
212 vm_offset_t kernelstart, vm_offset_t kernelend);
213 static void moea64_cpu_bootstrap_native(mmu_t, int ap);
214 static void tlbia(void);
216 static mmu_method_t moea64_native_methods[] = {
217 /* Internal interfaces */
218 MMUMETHOD(mmu_bootstrap, moea64_bootstrap_native),
219 MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap_native),
221 MMUMETHOD(moea64_pte_synch, moea64_pte_synch_native),
222 MMUMETHOD(moea64_pte_clear, moea64_pte_clear_native),
223 MMUMETHOD(moea64_pte_unset, moea64_pte_unset_native),
224 MMUMETHOD(moea64_pte_change, moea64_pte_change_native),
225 MMUMETHOD(moea64_pte_insert, moea64_pte_insert_native),
226 MMUMETHOD(moea64_pvo_to_pte, moea64_pvo_to_pte_native),
231 MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods,
234 static __inline u_int
235 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
240 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
241 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
243 return (hash & moea64_pteg_mask);
247 moea64_pte_synch_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt)
249 struct lpte *pt = (struct lpte *)pt_cookie;
251 pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG);
255 moea64_pte_clear_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt,
256 uint64_t vpn, uint64_t ptebit)
258 struct lpte *pt = (struct lpte *)pt_cookie;
261 * As shown in Section 7.6.3.2.3
263 pt->pte_lo &= ~ptebit;
270 moea64_pte_set_native(struct lpte *pt, struct lpte *pvo_pt)
273 pvo_pt->pte_hi |= LPTE_VALID;
276 * Update the PTE as defined in section 7.6.3.1.
277 * Note that the REF/CHG bits are from pvo_pt and thus should have
278 * been saved so this routine can restore them (if desired).
280 pt->pte_lo = pvo_pt->pte_lo;
282 pt->pte_hi = pvo_pt->pte_hi;
285 /* Keep statistics for unlocked pages */
286 if (!(pvo_pt->pte_hi & LPTE_LOCKED))
291 moea64_pte_unset_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt,
294 struct lpte *pt = (struct lpte *)pt_cookie;
297 * Invalidate the pte.
301 pvo_pt->pte_hi &= ~LPTE_VALID;
302 pt->pte_hi &= ~LPTE_VALID;
308 * Save the reg & chg bits.
310 moea64_pte_synch_native(mmu, pt_cookie, pvo_pt);
312 /* Keep statistics for unlocked pages */
313 if (!(pvo_pt->pte_hi & LPTE_LOCKED))
318 moea64_pte_change_native(mmu_t mmu, uintptr_t pt, struct lpte *pvo_pt,
325 moea64_pte_unset_native(mmu, pt, pvo_pt, vpn);
326 moea64_pte_set_native((struct lpte *)pt, pvo_pt);
330 moea64_cpu_bootstrap_native(mmu_t mmup, int ap)
334 struct slb *slb = PCPU_GET(slb);
339 * Initialize segment registers and MMU
342 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR);
345 * Install kernel SLB entries
349 __asm __volatile ("slbia");
350 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) :
353 for (i = 0; i < 64; i++) {
354 if (!(slb[i].slbe & SLBE_VALID))
357 __asm __volatile ("slbmte %0, %1" ::
358 "r"(slb[i].slbv), "r"(slb[i].slbe));
361 for (i = 0; i < 16; i++)
362 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
369 __asm __volatile ("ptesync; mtsdr1 %0; isync"
370 :: "r"((uintptr_t)moea64_pteg_table
371 | (uintptr_t)(flsl(moea64_pteg_mask >> 11))));
376 moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart,
377 vm_offset_t kernelend)
384 moea64_early_bootstrap(mmup, kernelstart, kernelend);
387 * Allocate PTEG table.
390 size = moea64_pteg_count * sizeof(struct lpteg);
391 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes",
392 moea64_pteg_count, size);
395 * We now need to allocate memory. This memory, to be allocated,
396 * has to reside in a page table. The page table we are about to
397 * allocate. We don't have BAT. So drop to data real mode for a minute
398 * as a measure of last resort. We do this a couple times.
401 moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size);
403 bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg));
406 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table);
409 * Initialize the TLBIE lock. TLBIE can only be executed by one CPU.
412 mtx_init(&tlbie_mutex, "tlbie", NULL, MTX_DEF);
414 mtx_init(&tlbie_mutex, "tlbie", NULL, MTX_SPIN);
417 moea64_mid_bootstrap(mmup, kernelstart, kernelend);
420 * Add a mapping for the page table itself if there is no direct map.
422 if (!hw_direct_map) {
423 size = moea64_pteg_count * sizeof(struct lpteg);
424 off = (vm_offset_t)(moea64_pteg_table);
426 for (pa = off; pa < off + size; pa += PAGE_SIZE)
431 /* Bring up virtual memory */
432 moea64_late_bootstrap(mmup, kernelstart, kernelend);
439 #ifndef __powerpc64__
440 register_t msr, scratch;
445 for (i = 0; i < 0xFF000; i += 0x00001000) {
447 __asm __volatile("tlbiel %0" :: "r"(i));
460 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1));
469 moea64_pvo_to_pte_native(mmu_t mmu, const struct pvo_entry *pvo)
475 /* If the PTEG index is not set, then there is no page table entry */
476 if (!PVO_PTEGIDX_ISSET(pvo))
480 * Calculate the ptegidx
482 vsid = PVO_VSID(pvo);
483 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
484 pvo->pvo_vaddr & PVO_LARGE);
487 * We can find the actual pte entry without searching by grabbing
488 * the PTEG index from 3 unused bits in pvo_vaddr and by
489 * noticing the HID bit.
491 if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID)
492 ptegidx ^= moea64_pteg_mask;
494 pteidx = (ptegidx << 3) | PVO_PTEGIDX_GET(pvo);
496 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
497 !PVO_PTEGIDX_ISSET(pvo)) {
498 panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no "
499 "valid pte index", pvo);
502 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 &&
503 PVO_PTEGIDX_ISSET(pvo)) {
504 panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo "
505 "pvo but no valid pte", pvo);
508 pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7];
509 if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) ==
511 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) {
512 panic("moea64_pvo_to_pte: pvo %p has valid pte in "
513 "moea64_pteg_table %p but invalid in pvo", pvo, pt);
516 if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) &
517 ~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) {
518 panic("moea64_pvo_to_pte: pvo %p pte does not match "
519 "pte %p in moea64_pteg_table difference is %#x",
521 (uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo));
524 return ((uintptr_t)pt);
527 if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) {
528 panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in "
529 "moea64_pteg_table but valid in pvo", pvo, pt);
536 moea64_pte_spillable_ident(u_int ptegidx)
541 /* Start at a random slot */
544 for (j = 0; j < 8; j++) {
545 pt = &moea64_pteg_table[ptegidx].pt[(i + j) % 8];
546 if (pt->pte_hi & (LPTE_LOCKED | LPTE_WIRED))
549 /* This is a candidate, so remember it */
552 /* Try to get a page that has not been used lately */
553 if (!(pt->pte_lo & LPTE_REF))
561 moea64_pte_insert_native(mmu_t mmu, u_int ptegidx, struct lpte *pvo_pt)
564 struct pvo_entry *pvo;
569 * First try primary hash.
571 pteg_bktidx = ptegidx;
572 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) {
573 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) {
574 pvo_pt->pte_hi &= ~LPTE_HID;
575 moea64_pte_set_native(pt, pvo_pt);
581 * Now try secondary hash.
583 pteg_bktidx ^= moea64_pteg_mask;
584 for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) {
585 if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) {
586 pvo_pt->pte_hi |= LPTE_HID;
587 moea64_pte_set_native(pt, pvo_pt);
593 * Out of luck. Find a PTE to sacrifice.
595 pteg_bktidx = ptegidx;
596 i = moea64_pte_spillable_ident(pteg_bktidx);
598 pteg_bktidx ^= moea64_pteg_mask;
599 i = moea64_pte_spillable_ident(pteg_bktidx);
603 /* No freeable slots in either PTEG? We're hosed. */
604 panic("moea64_pte_insert: overflow");
608 if (pteg_bktidx == ptegidx)
609 pvo_pt->pte_hi &= ~LPTE_HID;
611 pvo_pt->pte_hi |= LPTE_HID;
614 * Synchronize the sacrifice PTE with its PVO, then mark both
615 * invalid. The PVO will be reused when/if the VM system comes
616 * here after a fault.
618 pt = &moea64_pteg_table[pteg_bktidx].pt[i];
620 if (pt->pte_hi & LPTE_HID)
621 pteg_bktidx ^= moea64_pteg_mask; /* PTEs indexed by primary */
623 LIST_FOREACH(pvo, &moea64_pvo_table[pteg_bktidx], pvo_olink) {
624 if (pvo->pvo_pte.lpte.pte_hi == pt->pte_hi) {
625 KASSERT(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID,
626 ("Invalid PVO for valid PTE!"));
627 moea64_pte_unset_native(mmu, (uintptr_t)pt,
628 &pvo->pvo_pte.lpte, pvo->pvo_vpn);
629 PVO_PTEGIDX_CLR(pvo);
630 moea64_pte_overflow++;
635 KASSERT(pvo->pvo_pte.lpte.pte_hi == pt->pte_hi,
636 ("Unable to find PVO for spilled PTE"));
641 moea64_pte_set_native(pt, pvo_pt);