2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
38 #include <machine/bus.h>
39 #include <machine/cpu.h>
40 #include <machine/hid.h>
41 #include <machine/platform.h>
42 #include <machine/platformvar.h>
43 #include <machine/smp.h>
44 #include <machine/spr.h>
45 #include <machine/vmparam.h>
47 #include <dev/fdt/fdt_common.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50 #include <dev/ofw/openfirm.h>
52 #include <powerpc/mpc85xx/mpc85xx.h>
54 #include "platform_if.h"
58 extern uint8_t __boot_page[]; /* Boot page body */
59 extern uint32_t kernload_ap; /* Kernel physical load address */
62 extern uint32_t *bootinfo;
64 static int cpu, maxcpu;
66 static int bare_probe(platform_t);
67 static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz,
68 struct mem_region **avail, int *availsz);
69 static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref);
70 static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref);
71 static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref);
72 static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref);
73 static int bare_smp_start_cpu(platform_t, struct pcpu *cpu);
75 static void e500_reset(platform_t);
77 static platform_method_t bare_methods[] = {
78 PLATFORMMETHOD(platform_probe, bare_probe),
79 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions),
80 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq),
82 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu),
83 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu),
84 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp),
85 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu),
87 PLATFORMMETHOD(platform_reset, e500_reset),
92 static platform_def_t bare_platform = {
98 PLATFORM_DEF(bare_platform);
101 bare_probe(platform_t plat)
106 ver = SVR_VER(mfspr(SPR_SVR));
107 switch (ver & ~0x0008) { /* Mask Security Enabled bit */
125 * Clear local access windows. Skip DRAM entries, so we don't shoot
126 * ourselves in the foot.
128 law_max = law_getmax();
129 for (i = 0; i < law_max; i++) {
130 sr = ccsr_read4(OCP85XX_LAWSR(i));
131 if ((sr & 0x80000000) == 0)
133 tgt = (sr & 0x01f00000) >> 20;
134 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
135 tgt == OCP85XX_TGTIF_RAM_INTL)
138 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
141 return (BUS_PROBE_GENERIC);
144 #define MEM_REGIONS 8
145 static struct mem_region avail_regions[MEM_REGIONS];
148 bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz,
149 struct mem_region **avail, int *availsz)
154 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize);
159 for (i = 0; i < *availsz; i++) {
160 if (avail_regions[i].mr_start < 1048576) {
161 avail_regions[i].mr_size =
162 avail_regions[i].mr_size -
163 (1048576 - avail_regions[i].mr_start);
164 avail_regions[i].mr_start = 1048576;
167 *avail = avail_regions;
169 /* On the bare metal platform phys == avail memory */
175 bare_timebase_freq(platform_t plat, struct cpuref *cpuref)
178 phandle_t cpus, child;
181 if (bootinfo != NULL) {
182 if (bootinfo[0] == 1) {
183 /* Backward compatibility. See 8-STABLE. */
184 ticks = bootinfo[3] >> 3;
186 /* Compatibility with Juniper's loader. */
187 ticks = bootinfo[5] >> 3;
192 if ((cpus = OF_finddevice("/cpus")) == 0)
195 if ((child = OF_child(cpus)) == 0)
199 if (OF_getprop(child, "bus-frequency", (void *)&freq,
204 * Time Base and Decrementer are updated every 8 CCB bus clocks.
205 * HID0[SEL_TBCLK] = 0
212 panic("Unable to determine timebase frequency!");
218 bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
222 cpuref->cr_cpuid = cpu;
223 cpuref->cr_hwref = cpuref->cr_cpuid;
225 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
232 bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
238 cpuref->cr_cpuid = cpu++;
239 cpuref->cr_hwref = cpuref->cr_cpuid;
241 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
247 bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
250 cpuref->cr_cpuid = mfspr(SPR_PIR);
251 cpuref->cr_hwref = cpuref->cr_cpuid;
257 bare_smp_start_cpu(platform_t plat, struct pcpu *pc)
260 uint32_t bptr, eebpcr;
263 eebpcr = ccsr_read4(OCP85XX_EEBPCR);
264 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
265 printf("%s: CPU=%d already out of hold-off state!\n",
266 __func__, pc->pc_cpuid);
271 __asm __volatile("msync; isync");
274 * Set BPTR to the physical address of the boot page
276 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload_ap;
277 ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000);
280 * Release AP from hold-off state
282 eebpcr |= (1 << (pc->pc_cpuid + 24));
283 ccsr_write4(OCP85XX_EEBPCR, eebpcr);
284 __asm __volatile("isync; msync");
287 while (!pc->pc_awake && timeout--)
288 DELAY(1000); /* wait 1ms */
290 return ((pc->pc_awake) ? 0 : EBUSY);
298 e500_reset(platform_t plat)
302 * Try the dedicated reset register first.
303 * If the SoC doesn't have one, we'll fall
304 * back to using the debug control register.
306 ccsr_write4(OCP85XX_RSTCR, 2);
308 /* Clear DBCR0, disables debug interrupts and events. */
310 __asm __volatile("isync");
312 /* Enable Debug Interrupts in MSR. */
313 mtmsr(mfmsr() | PSL_DE);
315 /* Enable debug interrupts and issue reset. */
316 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
318 printf("Reset failed...\n");