2 * Written by: yen_cw@myson.com.tw
3 * Copyright (c) 2002 Myson Technology Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/types.h>
42 #include <sys/module.h>
44 #include <sys/mutex.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_media.h>
52 #include <net/if_types.h>
53 #include <net/if_dl.h>
56 #include <vm/vm.h> /* for vtophys */
57 #include <vm/pmap.h> /* for vtophys */
58 #include <machine/bus.h>
59 #include <machine/resource.h>
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
67 * #define MY_USEIOSPACE
70 static int MY_USEIOSPACE = 1;
73 #define MY_RES SYS_RES_IOPORT
74 #define MY_RID MY_PCI_LOIO
76 #define MY_RES SYS_RES_MEMORY
77 #define MY_RID MY_PCI_LOMEM
81 #include <dev/my/if_myreg.h>
84 * Various supported device vendors/types and their names.
86 struct my_type *my_info_tmp;
87 static struct my_type my_devs[] = {
88 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
89 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
90 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
95 * Various supported PHY vendors/types and their names. Note that this driver
96 * will work with pretty much any MII-compliant PHY, so failure to positively
97 * identify the chip is not a fatal error.
99 static struct my_type my_phys[] = {
100 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
101 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
102 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
103 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
104 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
105 {0, 0, "<MII-compliant physical interface>"}
108 static int my_probe(device_t);
109 static int my_attach(device_t);
110 static int my_detach(device_t);
111 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
112 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
113 static void my_rxeof(struct my_softc *);
114 static void my_txeof(struct my_softc *);
115 static void my_txeoc(struct my_softc *);
116 static void my_intr(void *);
117 static void my_start(struct ifnet *);
118 static void my_start_locked(struct ifnet *);
119 static int my_ioctl(struct ifnet *, u_long, caddr_t);
120 static void my_init(void *);
121 static void my_init_locked(struct my_softc *);
122 static void my_stop(struct my_softc *);
123 static void my_autoneg_timeout(void *);
124 static void my_watchdog(void *);
125 static int my_shutdown(device_t);
126 static int my_ifmedia_upd(struct ifnet *);
127 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
128 static u_int16_t my_phy_readreg(struct my_softc *, int);
129 static void my_phy_writereg(struct my_softc *, int, int);
130 static void my_autoneg_xmit(struct my_softc *);
131 static void my_autoneg_mii(struct my_softc *, int, int);
132 static void my_setmode_mii(struct my_softc *, int);
133 static void my_getmode_mii(struct my_softc *);
134 static void my_setcfg(struct my_softc *, int);
135 static void my_setmulti(struct my_softc *);
136 static void my_reset(struct my_softc *);
137 static int my_list_rx_init(struct my_softc *);
138 static int my_list_tx_init(struct my_softc *);
139 static long my_send_cmd_to_phy(struct my_softc *, int, int);
141 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
142 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
144 static device_method_t my_methods[] = {
145 /* Device interface */
146 DEVMETHOD(device_probe, my_probe),
147 DEVMETHOD(device_attach, my_attach),
148 DEVMETHOD(device_detach, my_detach),
149 DEVMETHOD(device_shutdown, my_shutdown),
154 static driver_t my_driver = {
157 sizeof(struct my_softc)
160 static devclass_t my_devclass;
162 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
163 MODULE_DEPEND(my, pci, 1, 1, 1);
164 MODULE_DEPEND(my, ether, 1, 1, 1);
167 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
175 /* enable MII output */
176 miir = CSR_READ_4(sc, MY_MANAGEMENT);
179 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
181 /* send 32 1's preamble */
182 for (i = 0; i < 32; i++) {
183 /* low MDC; MDO is already high (miir) */
184 miir &= ~MY_MASK_MIIR_MII_MDC;
185 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
188 miir |= MY_MASK_MIIR_MII_MDC;
189 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
192 /* calculate ST+OP+PHYAD+REGAD+TA */
193 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
198 /* low MDC, prepare MDO */
199 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
201 miir |= MY_MASK_MIIR_MII_MDO;
203 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
205 miir |= MY_MASK_MIIR_MII_MDC;
206 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
211 if (mask == 0x2 && opcode == MY_OP_READ)
212 miir &= ~MY_MASK_MIIR_MII_WRITE;
220 my_phy_readreg(struct my_softc * sc, int reg)
227 if (sc->my_info->my_did == MTD803ID)
228 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
230 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
237 miir &= ~MY_MASK_MIIR_MII_MDC;
238 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
241 miir = CSR_READ_4(sc, MY_MANAGEMENT);
242 if (miir & MY_MASK_MIIR_MII_MDI)
245 /* high MDC, and wait */
246 miir |= MY_MASK_MIIR_MII_MDC;
247 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
255 miir &= ~MY_MASK_MIIR_MII_MDC;
256 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
259 return (u_int16_t) data;
264 my_phy_writereg(struct my_softc * sc, int reg, int data)
271 if (sc->my_info->my_did == MTD803ID)
272 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
274 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
279 /* low MDC, prepare MDO */
280 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
282 miir |= MY_MASK_MIIR_MII_MDO;
283 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
287 miir |= MY_MASK_MIIR_MII_MDC;
288 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
296 miir &= ~MY_MASK_MIIR_MII_MDC;
297 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
304 * Program the 64-bit multicast hash filter.
307 my_setmulti(struct my_softc * sc)
311 u_int32_t hashes[2] = {0, 0};
312 struct ifmultiaddr *ifma;
320 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
322 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
324 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
325 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
326 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
330 /* first, zot all the existing hash bits */
331 CSR_WRITE_4(sc, MY_MAR0, 0);
332 CSR_WRITE_4(sc, MY_MAR1, 0);
334 /* now program new ones */
336 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
337 if (ifma->ifma_addr->sa_family != AF_LINK)
339 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
340 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
342 hashes[0] |= (1 << h);
344 hashes[1] |= (1 << (h - 32));
347 if_maddr_runlock(ifp);
353 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
354 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
355 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
360 * Initiate an autonegotiation session.
363 my_autoneg_xmit(struct my_softc * sc)
365 u_int16_t phy_sts = 0;
369 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
371 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
373 phy_sts = my_phy_readreg(sc, PHY_BMCR);
374 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
375 my_phy_writereg(sc, PHY_BMCR, phy_sts);
381 my_autoneg_timeout(void *arg)
387 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
391 * Invoke autonegotiation on a PHY.
394 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
396 u_int16_t phy_sts = 0, media, advert, ability;
397 u_int16_t ability2 = 0;
406 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
408 #ifndef FORCE_AUTONEG_TFOUR
410 * First, see if autoneg is supported. If not, there's no point in
413 phy_sts = my_phy_readreg(sc, PHY_BMSR);
414 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
416 device_printf(sc->my_dev,
417 "autonegotiation not supported\n");
418 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
423 case MY_FLAG_FORCEDELAY:
425 * XXX Never use this option anywhere but in the probe
426 * routine: making the kernel stop dead in its tracks for
427 * three whole seconds after we've gone multi-user is really
433 case MY_FLAG_SCHEDDELAY:
435 * Wait for the transmitter to go idle before starting an
436 * autoneg session, otherwise my_start() may clobber our
437 * timeout, and we don't want to allow transmission during an
438 * autoneg session since that can screw it up.
440 if (sc->my_cdata.my_tx_head != NULL) {
441 sc->my_want_auto = 1;
446 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout,
449 sc->my_want_auto = 0;
451 case MY_FLAG_DELAYTIMEO:
452 callout_stop(&sc->my_autoneg_timer);
456 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
460 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
462 device_printf(sc->my_dev, "autoneg complete, ");
463 phy_sts = my_phy_readreg(sc, PHY_BMSR);
466 device_printf(sc->my_dev, "autoneg not complete, ");
469 media = my_phy_readreg(sc, PHY_BMCR);
471 /* Link is good. Report modes and set duplex mode. */
472 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
474 device_printf(sc->my_dev, "link status good. ");
475 advert = my_phy_readreg(sc, PHY_ANAR);
476 ability = my_phy_readreg(sc, PHY_LPAR);
477 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
478 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
479 ability2 = my_phy_readreg(sc, PHY_1000SR);
480 if (ability2 & PHY_1000SR_1000BTXFULL) {
484 * this version did not support 1000M,
486 * IFM_ETHER|IFM_1000_T|IFM_FDX;
489 IFM_ETHER | IFM_100_TX | IFM_FDX;
490 media &= ~PHY_BMCR_SPEEDSEL;
491 media |= PHY_BMCR_1000;
492 media |= PHY_BMCR_DUPLEX;
493 printf("(full-duplex, 1000Mbps)\n");
494 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
498 * this version did not support 1000M,
499 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
501 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
502 media &= ~PHY_BMCR_SPEEDSEL;
503 media &= ~PHY_BMCR_DUPLEX;
504 media |= PHY_BMCR_1000;
505 printf("(half-duplex, 1000Mbps)\n");
508 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
509 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
510 media |= PHY_BMCR_SPEEDSEL;
511 media &= ~PHY_BMCR_DUPLEX;
512 printf("(100baseT4)\n");
513 } else if (advert & PHY_ANAR_100BTXFULL &&
514 ability & PHY_ANAR_100BTXFULL) {
515 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
516 media |= PHY_BMCR_SPEEDSEL;
517 media |= PHY_BMCR_DUPLEX;
518 printf("(full-duplex, 100Mbps)\n");
519 } else if (advert & PHY_ANAR_100BTXHALF &&
520 ability & PHY_ANAR_100BTXHALF) {
521 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
522 media |= PHY_BMCR_SPEEDSEL;
523 media &= ~PHY_BMCR_DUPLEX;
524 printf("(half-duplex, 100Mbps)\n");
525 } else if (advert & PHY_ANAR_10BTFULL &&
526 ability & PHY_ANAR_10BTFULL) {
527 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
528 media &= ~PHY_BMCR_SPEEDSEL;
529 media |= PHY_BMCR_DUPLEX;
530 printf("(full-duplex, 10Mbps)\n");
532 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
533 media &= ~PHY_BMCR_SPEEDSEL;
534 media &= ~PHY_BMCR_DUPLEX;
535 printf("(half-duplex, 10Mbps)\n");
537 media &= ~PHY_BMCR_AUTONEGENBL;
539 /* Set ASIC's duplex mode to match the PHY. */
540 my_phy_writereg(sc, PHY_BMCR, media);
541 my_setcfg(sc, media);
544 device_printf(sc->my_dev, "no carrier\n");
548 if (sc->my_tx_pend) {
551 my_start_locked(ifp);
557 * To get PHY ability.
560 my_getmode_mii(struct my_softc * sc)
567 bmsr = my_phy_readreg(sc, PHY_BMSR);
569 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
572 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
574 if (bmsr & PHY_BMSR_10BTHALF) {
576 device_printf(sc->my_dev,
577 "10Mbps half-duplex mode supported\n");
578 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
580 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
582 if (bmsr & PHY_BMSR_10BTFULL) {
584 device_printf(sc->my_dev,
585 "10Mbps full-duplex mode supported\n");
587 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
589 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
591 if (bmsr & PHY_BMSR_100BTXHALF) {
593 device_printf(sc->my_dev,
594 "100Mbps half-duplex mode supported\n");
595 ifp->if_baudrate = 100000000;
596 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
597 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
599 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
601 if (bmsr & PHY_BMSR_100BTXFULL) {
603 device_printf(sc->my_dev,
604 "100Mbps full-duplex mode supported\n");
605 ifp->if_baudrate = 100000000;
606 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
608 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
610 /* Some also support 100BaseT4. */
611 if (bmsr & PHY_BMSR_100BT4) {
613 device_printf(sc->my_dev, "100baseT4 mode supported\n");
614 ifp->if_baudrate = 100000000;
615 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
616 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
617 #ifdef FORCE_AUTONEG_TFOUR
619 device_printf(sc->my_dev,
620 "forcing on autoneg support for BT4\n");
621 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
622 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
625 #if 0 /* this version did not support 1000M, */
626 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
628 device_printf(sc->my_dev,
629 "1000Mbps half-duplex mode supported\n");
631 ifp->if_baudrate = 1000000000;
632 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
633 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
636 device_printf(sc->my_dev,
637 "1000Mbps full-duplex mode supported\n");
638 ifp->if_baudrate = 1000000000;
639 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
641 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
644 if (bmsr & PHY_BMSR_CANAUTONEG) {
646 device_printf(sc->my_dev, "autoneg supported\n");
647 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
648 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
654 * Set speed and duplex mode.
657 my_setmode_mii(struct my_softc * sc, int media)
665 * If an autoneg session is in progress, stop it.
667 if (sc->my_autoneg) {
668 device_printf(sc->my_dev, "canceling autoneg session\n");
669 callout_stop(&sc->my_autoneg_timer);
670 sc->my_autoneg = sc->my_want_auto = 0;
671 bmcr = my_phy_readreg(sc, PHY_BMCR);
672 bmcr &= ~PHY_BMCR_AUTONEGENBL;
673 my_phy_writereg(sc, PHY_BMCR, bmcr);
675 device_printf(sc->my_dev, "selecting MII, ");
676 bmcr = my_phy_readreg(sc, PHY_BMCR);
677 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
678 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
680 #if 0 /* this version did not support 1000M, */
681 if (IFM_SUBTYPE(media) == IFM_1000_T) {
682 printf("1000Mbps/T4, half-duplex\n");
683 bmcr &= ~PHY_BMCR_SPEEDSEL;
684 bmcr &= ~PHY_BMCR_DUPLEX;
685 bmcr |= PHY_BMCR_1000;
688 if (IFM_SUBTYPE(media) == IFM_100_T4) {
689 printf("100Mbps/T4, half-duplex\n");
690 bmcr |= PHY_BMCR_SPEEDSEL;
691 bmcr &= ~PHY_BMCR_DUPLEX;
693 if (IFM_SUBTYPE(media) == IFM_100_TX) {
695 bmcr |= PHY_BMCR_SPEEDSEL;
697 if (IFM_SUBTYPE(media) == IFM_10_T) {
699 bmcr &= ~PHY_BMCR_SPEEDSEL;
701 if ((media & IFM_GMASK) == IFM_FDX) {
702 printf("full duplex\n");
703 bmcr |= PHY_BMCR_DUPLEX;
705 printf("half duplex\n");
706 bmcr &= ~PHY_BMCR_DUPLEX;
708 my_phy_writereg(sc, PHY_BMCR, bmcr);
714 * The Myson manual states that in order to fiddle with the 'full-duplex' and
715 * '100Mbps' bits in the netconfig register, we first have to put the
716 * transmit and/or receive logic in the idle state.
719 my_setcfg(struct my_softc * sc, int bmcr)
724 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
726 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
727 for (i = 0; i < MY_TIMEOUT; i++) {
729 if (!(CSR_READ_4(sc, MY_TCRRCR) &
730 (MY_TXRUN | MY_RXRUN)))
734 device_printf(sc->my_dev,
735 "failed to force tx and rx to idle \n");
737 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
738 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
739 if (bmcr & PHY_BMCR_1000)
740 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
741 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
742 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
743 if (bmcr & PHY_BMCR_DUPLEX)
744 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
746 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
748 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
753 my_reset(struct my_softc * sc)
758 MY_SETBIT(sc, MY_BCR, MY_SWR);
759 for (i = 0; i < MY_TIMEOUT; i++) {
761 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
765 device_printf(sc->my_dev, "reset never completed!\n");
767 /* Wait a little while for the chip to get its brains in order. */
773 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
774 * list and return a device name if we find a match.
777 my_probe(device_t dev)
782 while (t->my_name != NULL) {
783 if ((pci_get_vendor(dev) == t->my_vid) &&
784 (pci_get_device(dev) == t->my_did)) {
785 device_set_desc(dev, t->my_name);
787 return (BUS_PROBE_DEFAULT);
795 * Attach the interface. Allocate softc structures, do ifmedia setup and
796 * ethernet/BPF attach.
799 my_attach(device_t dev)
802 u_char eaddr[ETHER_ADDR_LEN];
806 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
810 u_int16_t phy_vid, phy_did, phy_sts = 0;
813 sc = device_get_softc(dev);
815 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
817 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0);
818 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0);
821 * Map control/status registers.
823 pci_enable_busmaster(dev);
825 if (my_info_tmp->my_did == MTD800ID) {
826 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
832 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
834 if (sc->my_res == NULL) {
835 device_printf(dev, "couldn't map ports/memory\n");
839 sc->my_btag = rman_get_bustag(sc->my_res);
840 sc->my_bhandle = rman_get_bushandle(sc->my_res);
843 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
844 RF_SHAREABLE | RF_ACTIVE);
846 if (sc->my_irq == NULL) {
847 device_printf(dev, "couldn't map interrupt\n");
852 sc->my_info = my_info_tmp;
854 /* Reset the adapter. */
860 * Get station address
862 for (i = 0; i < ETHER_ADDR_LEN; ++i)
863 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
865 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
867 if (sc->my_ldata_ptr == NULL) {
868 device_printf(dev, "no memory for list buffers!\n");
872 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
873 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
874 roundptr = sc->my_ldata_ptr;
875 for (i = 0; i < 8; i++) {
882 sc->my_ldata = (struct my_list_data *) roundptr;
883 bzero(sc->my_ldata, sizeof(struct my_list_data));
885 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
887 device_printf(dev, "can not if_alloc()\n");
892 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
893 ifp->if_mtu = ETHERMTU;
894 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
895 ifp->if_ioctl = my_ioctl;
896 ifp->if_start = my_start;
897 ifp->if_init = my_init;
898 ifp->if_baudrate = 10000000;
899 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
900 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
901 IFQ_SET_READY(&ifp->if_snd);
903 if (sc->my_info->my_did == MTD803ID)
904 sc->my_pinfo = my_phys;
907 device_printf(dev, "probing for a PHY\n");
909 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
911 device_printf(dev, "checking address: %d\n", i);
913 phy_sts = my_phy_readreg(sc, PHY_BMSR);
914 if ((phy_sts != 0) && (phy_sts != 0xffff))
920 phy_vid = my_phy_readreg(sc, PHY_VENID);
921 phy_did = my_phy_readreg(sc, PHY_DEVID);
923 device_printf(dev, "found PHY at address %d, ",
925 printf("vendor id: %x device id: %x\n",
930 if (phy_vid == p->my_vid) {
936 if (sc->my_pinfo == NULL)
937 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
939 device_printf(dev, "PHY type: %s\n",
940 sc->my_pinfo->my_name);
943 device_printf(dev, "MII without any phy!\n");
950 /* Do ifmedia setup. */
951 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
954 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
955 media = sc->ifmedia.ifm_media;
958 ifmedia_set(&sc->ifmedia, media);
960 ether_ifattach(ifp, eaddr);
962 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
963 NULL, my_intr, sc, &sc->my_intrhand);
966 device_printf(dev, "couldn't set up irq\n");
977 free(sc->my_ldata_ptr, M_DEVBUF);
979 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
981 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
983 mtx_destroy(&sc->my_mtx);
988 my_detach(device_t dev)
993 sc = device_get_softc(dev);
999 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1000 callout_drain(&sc->my_watchdog);
1001 callout_drain(&sc->my_autoneg_timer);
1004 free(sc->my_ldata_ptr, M_DEVBUF);
1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1007 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1008 mtx_destroy(&sc->my_mtx);
1014 * Initialize the transmit descriptors.
1017 my_list_tx_init(struct my_softc * sc)
1019 struct my_chain_data *cd;
1020 struct my_list_data *ld;
1026 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1027 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1028 if (i == (MY_TX_LIST_CNT - 1))
1029 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1031 cd->my_tx_chain[i].my_nextdesc =
1032 &cd->my_tx_chain[i + 1];
1034 cd->my_tx_free = &cd->my_tx_chain[0];
1035 cd->my_tx_tail = cd->my_tx_head = NULL;
1040 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1041 * arrange the descriptors in a closed ring, so that the last descriptor
1042 * points back to the first.
1045 my_list_rx_init(struct my_softc * sc)
1047 struct my_chain_data *cd;
1048 struct my_list_data *ld;
1054 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1055 cd->my_rx_chain[i].my_ptr =
1056 (struct my_desc *) & ld->my_rx_list[i];
1057 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1061 if (i == (MY_RX_LIST_CNT - 1)) {
1062 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1063 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1065 cd->my_rx_chain[i].my_nextdesc =
1066 &cd->my_rx_chain[i + 1];
1067 ld->my_rx_list[i].my_next =
1068 vtophys(&ld->my_rx_list[i + 1]);
1071 cd->my_rx_head = &cd->my_rx_chain[0];
1076 * Initialize an RX descriptor and attach an MBUF cluster.
1079 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1081 struct mbuf *m_new = NULL;
1084 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1085 if (m_new == NULL) {
1086 device_printf(sc->my_dev,
1087 "no memory for rx list -- packet dropped!\n");
1090 MCLGET(m_new, M_NOWAIT);
1091 if (!(m_new->m_flags & M_EXT)) {
1092 device_printf(sc->my_dev,
1093 "no memory for rx list -- packet dropped!\n");
1098 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1099 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1100 c->my_ptr->my_status = MY_OWNByNIC;
1105 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1109 my_rxeof(struct my_softc * sc)
1111 struct ether_header *eh;
1114 struct my_chain_onefrag *cur_rx;
1120 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1122 cur_rx = sc->my_cdata.my_rx_head;
1123 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1125 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1127 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1130 /* No errors; receive the packet. */
1131 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1132 total_len -= ETHER_CRC_LEN;
1134 if (total_len < MINCLSIZE) {
1135 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1136 total_len, 0, ifp, NULL);
1137 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1143 m = cur_rx->my_mbuf;
1145 * Try to conjure up a new mbuf cluster. If that
1146 * fails, it means we have an out of memory condition
1147 * and should leave the buffer in place and continue.
1148 * This will result in a lost packet, but there's
1149 * little else we can do in this situation.
1151 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1153 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1156 m->m_pkthdr.rcvif = ifp;
1157 m->m_pkthdr.len = m->m_len = total_len;
1160 eh = mtod(m, struct ether_header *);
1163 * Handle BPF listeners. Let the BPF user see the packet, but
1164 * don't pass it up to the ether_input() layer unless it's a
1165 * broadcast packet, multicast packet, matches our ethernet
1166 * address or the interface is in promiscuous mode.
1168 if (bpf_peers_present(ifp->if_bpf)) {
1169 bpf_mtap(ifp->if_bpf, m);
1170 if (ifp->if_flags & IFF_PROMISC &&
1171 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp),
1173 (eh->ether_dhost[0] & 1) == 0)) {
1180 (*ifp->if_input)(ifp, m);
1188 * A frame was downloaded to the chip. It's safe for us to clean up the list
1192 my_txeof(struct my_softc * sc)
1194 struct my_chain *cur_tx;
1199 /* Clear the timeout timer. */
1201 if (sc->my_cdata.my_tx_head == NULL) {
1205 * Go through our tx list and free mbufs for those frames that have
1208 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1211 cur_tx = sc->my_cdata.my_tx_head;
1212 txstat = MY_TXSTATUS(cur_tx);
1213 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1215 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1216 if (txstat & MY_TXERR) {
1218 if (txstat & MY_EC) /* excessive collision */
1219 ifp->if_collisions++;
1220 if (txstat & MY_LC) /* late collision */
1221 ifp->if_collisions++;
1223 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1227 m_freem(cur_tx->my_mbuf);
1228 cur_tx->my_mbuf = NULL;
1229 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1230 sc->my_cdata.my_tx_head = NULL;
1231 sc->my_cdata.my_tx_tail = NULL;
1234 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1236 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1237 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1243 * TX 'end of channel' interrupt handler.
1246 my_txeoc(struct my_softc * sc)
1253 if (sc->my_cdata.my_tx_head == NULL) {
1254 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1255 sc->my_cdata.my_tx_tail = NULL;
1256 if (sc->my_want_auto)
1257 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1259 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1260 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1262 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1271 struct my_softc *sc;
1278 if (!(ifp->if_flags & IFF_UP)) {
1282 /* Disable interrupts. */
1283 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1286 status = CSR_READ_4(sc, MY_ISR);
1289 CSR_WRITE_4(sc, MY_ISR, status);
1293 if (status & MY_RI) /* receive interrupt */
1296 if ((status & MY_RBU) || (status & MY_RxErr)) {
1297 /* rx buffer unavailable or rx error */
1305 if (status & MY_TI) /* tx interrupt */
1307 if (status & MY_ETI) /* tx early interrupt */
1309 if (status & MY_TBU) /* tx buffer unavailable */
1312 #if 0 /* 90/1/18 delete */
1313 if (status & MY_FBE) {
1321 /* Re-enable interrupts. */
1322 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1323 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1324 my_start_locked(ifp);
1330 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1331 * pointers to the fragment pointers.
1334 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1336 struct my_desc *f = NULL;
1338 struct mbuf *m, *m_new = NULL;
1341 /* calculate the total tx pkt length */
1343 for (m = m_head; m != NULL; m = m->m_next)
1344 total_len += m->m_len;
1346 * Start packing the mbufs in this chain into the fragment pointers.
1347 * Stop when we run out of fragments or hit the end of the mbuf
1351 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1352 if (m_new == NULL) {
1353 device_printf(sc->my_dev, "no memory for tx list");
1356 if (m_head->m_pkthdr.len > MHLEN) {
1357 MCLGET(m_new, M_NOWAIT);
1358 if (!(m_new->m_flags & M_EXT)) {
1360 device_printf(sc->my_dev, "no memory for tx list");
1364 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1365 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1368 f = &c->my_ptr->my_frag[0];
1370 f->my_data = vtophys(mtod(m_new, caddr_t));
1371 total_len = m_new->m_len;
1372 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1373 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1374 f->my_ctl |= total_len; /* buffer size */
1375 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1376 if (sc->my_info->my_did == MTD891ID)
1377 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1378 c->my_mbuf = m_head;
1380 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1385 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1386 * to the mbuf data regions directly in the transmit lists. We also save a
1387 * copy of the pointers since the transmit list fragment pointers are
1388 * physical addresses.
1391 my_start(struct ifnet * ifp)
1393 struct my_softc *sc;
1397 my_start_locked(ifp);
1402 my_start_locked(struct ifnet * ifp)
1404 struct my_softc *sc;
1405 struct mbuf *m_head = NULL;
1406 struct my_chain *cur_tx = NULL, *start_tx;
1410 if (sc->my_autoneg) {
1415 * Check for an available queue slot. If there are none, punt.
1417 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1418 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1421 start_tx = sc->my_cdata.my_tx_free;
1422 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1423 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1427 /* Pick a descriptor off the free list. */
1428 cur_tx = sc->my_cdata.my_tx_free;
1429 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1431 /* Pack the data into the descriptor. */
1432 my_encap(sc, cur_tx, m_head);
1434 if (cur_tx != start_tx)
1435 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1438 * If there's a BPF listener, bounce a copy of this frame to
1441 BPF_MTAP(ifp, cur_tx->my_mbuf);
1445 * If there are no packets queued, bail.
1447 if (cur_tx == NULL) {
1451 * Place the request for the upload interrupt in the last descriptor
1452 * in the chain. This way, if we're chaining several packets at once,
1453 * we'll only get an interrupt once for the whole chain rather than
1454 * once for each packet.
1456 MY_TXCTL(cur_tx) |= MY_TXIC;
1457 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1458 sc->my_cdata.my_tx_tail = cur_tx;
1459 if (sc->my_cdata.my_tx_head == NULL)
1460 sc->my_cdata.my_tx_head = start_tx;
1461 MY_TXOWN(start_tx) = MY_OWNByNIC;
1462 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1465 * Set a timeout in case the chip goes out to lunch.
1474 struct my_softc *sc = xsc;
1482 my_init_locked(struct my_softc *sc)
1484 struct ifnet *ifp = sc->my_ifp;
1485 u_int16_t phy_bmcr = 0;
1488 if (sc->my_autoneg) {
1491 if (sc->my_pinfo != NULL)
1492 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1494 * Cancel pending I/O and free all RX/TX buffers.
1500 * Set cache alignment and burst length.
1502 #if 0 /* 89/9/1 modify, */
1503 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1504 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1506 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1507 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1509 * 89/12/29 add, for mtd891,
1511 if (sc->my_info->my_did == MTD891ID) {
1512 MY_SETBIT(sc, MY_BCR, MY_PROG);
1513 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1515 my_setcfg(sc, phy_bmcr);
1516 /* Init circular RX list. */
1517 if (my_list_rx_init(sc) == ENOBUFS) {
1518 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1522 /* Init TX descriptors. */
1523 my_list_tx_init(sc);
1525 /* If we want promiscuous mode, set the allframes bit. */
1526 if (ifp->if_flags & IFF_PROMISC)
1527 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1529 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1532 * Set capture broadcast bit to capture broadcast frames.
1534 if (ifp->if_flags & IFF_BROADCAST)
1535 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1537 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1540 * Program the multicast filter, if necessary.
1545 * Load the address of the RX list.
1547 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1548 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1551 * Enable interrupts.
1553 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1554 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1556 /* Enable receiver and transmitter. */
1557 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1558 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1559 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1560 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1562 /* Restore state of BMCR */
1563 if (sc->my_pinfo != NULL)
1564 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1565 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1566 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1568 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1573 * Set media options.
1577 my_ifmedia_upd(struct ifnet * ifp)
1579 struct my_softc *sc;
1580 struct ifmedia *ifm;
1585 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1589 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1590 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1592 my_setmode_mii(sc, ifm->ifm_media);
1598 * Report current media status.
1602 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1604 struct my_softc *sc;
1605 u_int16_t advert = 0, ability = 0;
1609 ifmr->ifm_active = IFM_ETHER;
1610 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1611 #if 0 /* this version did not support 1000M, */
1612 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1613 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1615 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1616 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1618 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1619 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1620 ifmr->ifm_active |= IFM_FDX;
1622 ifmr->ifm_active |= IFM_HDX;
1627 ability = my_phy_readreg(sc, PHY_LPAR);
1628 advert = my_phy_readreg(sc, PHY_ANAR);
1630 #if 0 /* this version did not support 1000M, */
1631 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1632 ability2 = my_phy_readreg(sc, PHY_1000SR);
1633 if (ability2 & PHY_1000SR_1000BTXFULL) {
1636 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1637 } else if (ability & PHY_1000SR_1000BTXHALF) {
1640 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1644 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1645 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1646 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1647 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1648 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1649 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1650 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1651 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1652 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1653 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1659 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1661 struct my_softc *sc = ifp->if_softc;
1662 struct ifreq *ifr = (struct ifreq *) data;
1668 if (ifp->if_flags & IFF_UP)
1670 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1684 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1687 error = ether_ioctl(ifp, command, data);
1694 my_watchdog(void *arg)
1696 struct my_softc *sc;
1701 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1702 if (sc->my_timer == 0 || --sc->my_timer > 0)
1707 if_printf(ifp, "watchdog timeout\n");
1708 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1709 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1713 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1714 my_start_locked(ifp);
1719 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1722 my_stop(struct my_softc * sc)
1730 callout_stop(&sc->my_autoneg_timer);
1731 callout_stop(&sc->my_watchdog);
1733 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1734 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1735 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1736 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1739 * Free data in the RX lists.
1741 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1742 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1743 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1744 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1747 bzero((char *)&sc->my_ldata->my_rx_list,
1748 sizeof(sc->my_ldata->my_rx_list));
1750 * Free the TX list buffers.
1752 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1753 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1754 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1755 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1758 bzero((char *)&sc->my_ldata->my_tx_list,
1759 sizeof(sc->my_ldata->my_tx_list));
1760 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1765 * Stop all chip I/O so that the kernel's probe routines don't get confused
1766 * by errant DMAs when rebooting.
1769 my_shutdown(device_t dev)
1771 struct my_softc *sc;
1773 sc = device_get_softc(dev);