1 /* $OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $ */
4 * Copyright (c) 2006 Shigeaki Tagashira <shigeaki@se.hiroshima-u.ac.jp>
5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
23 #include <sys/cdefs.h>
24 __FBSDID("$FreeBSD$");
26 #ifdef HAVE_KERNEL_OPTION_HEADERS
27 #include "opt_device_polling.h"
30 #include <sys/param.h>
31 #include <sys/endian.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/kernel.h>
38 #include <sys/queue.h>
39 #include <sys/socket.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
44 #include <net/if_arp.h>
45 #include <net/ethernet.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
48 #include <net/if_types.h>
49 #include <net/if_vlan_var.h>
53 #include <machine/bus.h>
54 #include <machine/resource.h>
58 #include <dev/mii/mii.h>
59 #include <dev/mii/miivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
64 #include <dev/nfe/if_nfereg.h>
65 #include <dev/nfe/if_nfevar.h>
67 MODULE_DEPEND(nfe, pci, 1, 1, 1);
68 MODULE_DEPEND(nfe, ether, 1, 1, 1);
69 MODULE_DEPEND(nfe, miibus, 1, 1, 1);
71 /* "device miibus" required. See GENERIC if you get errors here. */
72 #include "miibus_if.h"
74 static int nfe_probe(device_t);
75 static int nfe_attach(device_t);
76 static int nfe_detach(device_t);
77 static int nfe_suspend(device_t);
78 static int nfe_resume(device_t);
79 static int nfe_shutdown(device_t);
80 static int nfe_can_use_msix(struct nfe_softc *);
81 static int nfe_detect_msik9(struct nfe_softc *);
82 static void nfe_power(struct nfe_softc *);
83 static int nfe_miibus_readreg(device_t, int, int);
84 static int nfe_miibus_writereg(device_t, int, int, int);
85 static void nfe_miibus_statchg(device_t);
86 static void nfe_mac_config(struct nfe_softc *, struct mii_data *);
87 static void nfe_set_intr(struct nfe_softc *);
88 static __inline void nfe_enable_intr(struct nfe_softc *);
89 static __inline void nfe_disable_intr(struct nfe_softc *);
90 static int nfe_ioctl(struct ifnet *, u_long, caddr_t);
91 static void nfe_alloc_msix(struct nfe_softc *, int);
92 static int nfe_intr(void *);
93 static void nfe_int_task(void *, int);
94 static __inline void nfe_discard_rxbuf(struct nfe_softc *, int);
95 static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int);
96 static int nfe_newbuf(struct nfe_softc *, int);
97 static int nfe_jnewbuf(struct nfe_softc *, int);
98 static int nfe_rxeof(struct nfe_softc *, int, int *);
99 static int nfe_jrxeof(struct nfe_softc *, int, int *);
100 static void nfe_txeof(struct nfe_softc *);
101 static int nfe_encap(struct nfe_softc *, struct mbuf **);
102 static void nfe_setmulti(struct nfe_softc *);
103 static void nfe_start(struct ifnet *);
104 static void nfe_start_locked(struct ifnet *);
105 static void nfe_watchdog(struct ifnet *);
106 static void nfe_init(void *);
107 static void nfe_init_locked(void *);
108 static void nfe_stop(struct ifnet *);
109 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
110 static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *);
111 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
112 static int nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *);
113 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
114 static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *);
115 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
116 static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
117 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
118 static int nfe_ifmedia_upd(struct ifnet *);
119 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
120 static void nfe_tick(void *);
121 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
122 static void nfe_set_macaddr(struct nfe_softc *, uint8_t *);
123 static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int);
125 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
126 static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS);
127 static void nfe_sysctl_node(struct nfe_softc *);
128 static void nfe_stats_clear(struct nfe_softc *);
129 static void nfe_stats_update(struct nfe_softc *);
130 static void nfe_set_linkspeed(struct nfe_softc *);
131 static void nfe_set_wol(struct nfe_softc *);
134 static int nfedebug = 0;
135 #define DPRINTF(sc, ...) do { \
137 device_printf((sc)->nfe_dev, __VA_ARGS__); \
139 #define DPRINTFN(sc, n, ...) do { \
140 if (nfedebug >= (n)) \
141 device_printf((sc)->nfe_dev, __VA_ARGS__); \
144 #define DPRINTF(sc, ...)
145 #define DPRINTFN(sc, n, ...)
148 #define NFE_LOCK(_sc) mtx_lock(&(_sc)->nfe_mtx)
149 #define NFE_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_mtx)
150 #define NFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nfe_mtx, MA_OWNED)
153 static int msi_disable = 0;
154 static int msix_disable = 0;
155 static int jumbo_disable = 0;
156 TUNABLE_INT("hw.nfe.msi_disable", &msi_disable);
157 TUNABLE_INT("hw.nfe.msix_disable", &msix_disable);
158 TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable);
160 static device_method_t nfe_methods[] = {
161 /* Device interface */
162 DEVMETHOD(device_probe, nfe_probe),
163 DEVMETHOD(device_attach, nfe_attach),
164 DEVMETHOD(device_detach, nfe_detach),
165 DEVMETHOD(device_suspend, nfe_suspend),
166 DEVMETHOD(device_resume, nfe_resume),
167 DEVMETHOD(device_shutdown, nfe_shutdown),
170 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
171 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
172 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
177 static driver_t nfe_driver = {
180 sizeof(struct nfe_softc)
183 static devclass_t nfe_devclass;
185 DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0);
186 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
188 static struct nfe_type nfe_devs[] = {
189 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
190 "NVIDIA nForce MCP Networking Adapter"},
191 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
192 "NVIDIA nForce2 MCP2 Networking Adapter"},
193 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1,
194 "NVIDIA nForce2 400 MCP4 Networking Adapter"},
195 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2,
196 "NVIDIA nForce2 400 MCP5 Networking Adapter"},
197 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
198 "NVIDIA nForce3 MCP3 Networking Adapter"},
199 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN,
200 "NVIDIA nForce3 250 MCP6 Networking Adapter"},
201 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
202 "NVIDIA nForce3 MCP7 Networking Adapter"},
203 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1,
204 "NVIDIA nForce4 CK804 MCP8 Networking Adapter"},
205 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2,
206 "NVIDIA nForce4 CK804 MCP9 Networking Adapter"},
207 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
208 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP10 */
209 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
210 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP11 */
211 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1,
212 "NVIDIA nForce 430 MCP12 Networking Adapter"},
213 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2,
214 "NVIDIA nForce 430 MCP13 Networking Adapter"},
215 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
216 "NVIDIA nForce MCP55 Networking Adapter"},
217 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
218 "NVIDIA nForce MCP55 Networking Adapter"},
219 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
220 "NVIDIA nForce MCP61 Networking Adapter"},
221 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
222 "NVIDIA nForce MCP61 Networking Adapter"},
223 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
224 "NVIDIA nForce MCP61 Networking Adapter"},
225 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
226 "NVIDIA nForce MCP61 Networking Adapter"},
227 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
228 "NVIDIA nForce MCP65 Networking Adapter"},
229 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
230 "NVIDIA nForce MCP65 Networking Adapter"},
231 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
232 "NVIDIA nForce MCP65 Networking Adapter"},
233 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
234 "NVIDIA nForce MCP65 Networking Adapter"},
235 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
236 "NVIDIA nForce MCP67 Networking Adapter"},
237 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
238 "NVIDIA nForce MCP67 Networking Adapter"},
239 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
240 "NVIDIA nForce MCP67 Networking Adapter"},
241 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
242 "NVIDIA nForce MCP67 Networking Adapter"},
243 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
244 "NVIDIA nForce MCP73 Networking Adapter"},
245 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
246 "NVIDIA nForce MCP73 Networking Adapter"},
247 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
248 "NVIDIA nForce MCP73 Networking Adapter"},
249 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
250 "NVIDIA nForce MCP73 Networking Adapter"},
251 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
252 "NVIDIA nForce MCP77 Networking Adapter"},
253 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
254 "NVIDIA nForce MCP77 Networking Adapter"},
255 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
256 "NVIDIA nForce MCP77 Networking Adapter"},
257 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
258 "NVIDIA nForce MCP77 Networking Adapter"},
259 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
260 "NVIDIA nForce MCP79 Networking Adapter"},
261 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
262 "NVIDIA nForce MCP79 Networking Adapter"},
263 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
264 "NVIDIA nForce MCP79 Networking Adapter"},
265 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
266 "NVIDIA nForce MCP79 Networking Adapter"},
271 /* Probe for supported hardware ID's */
273 nfe_probe(device_t dev)
278 /* Check for matching PCI DEVICE ID's */
279 while (t->name != NULL) {
280 if ((pci_get_vendor(dev) == t->vid_id) &&
281 (pci_get_device(dev) == t->dev_id)) {
282 device_set_desc(dev, t->name);
283 return (BUS_PROBE_DEFAULT);
292 nfe_alloc_msix(struct nfe_softc *sc, int count)
297 sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY,
299 if (sc->nfe_msix_res == NULL) {
300 device_printf(sc->nfe_dev,
301 "couldn't allocate MSIX table resource\n");
305 sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev,
306 SYS_RES_MEMORY, &rid, RF_ACTIVE);
307 if (sc->nfe_msix_pba_res == NULL) {
308 device_printf(sc->nfe_dev,
309 "couldn't allocate MSIX PBA resource\n");
310 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2),
312 sc->nfe_msix_res = NULL;
316 if (pci_alloc_msix(sc->nfe_dev, &count) == 0) {
317 if (count == NFE_MSI_MESSAGES) {
319 device_printf(sc->nfe_dev,
320 "Using %d MSIX messages\n", count);
324 device_printf(sc->nfe_dev,
325 "couldn't allocate MSIX\n");
326 pci_release_msi(sc->nfe_dev);
327 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY,
328 PCIR_BAR(3), sc->nfe_msix_pba_res);
329 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY,
330 PCIR_BAR(2), sc->nfe_msix_res);
331 sc->nfe_msix_pba_res = NULL;
332 sc->nfe_msix_res = NULL;
339 nfe_detect_msik9(struct nfe_softc *sc)
341 static const char *maker = "MSI";
342 static const char *product = "K9N6PGM2-V2 (MS-7309)";
347 m = getenv("smbios.planar.maker");
348 p = getenv("smbios.planar.product");
349 if (m != NULL && p != NULL) {
350 if (strcmp(m, maker) == 0 && strcmp(p, product) == 0)
363 nfe_attach(device_t dev)
365 struct nfe_softc *sc;
367 bus_addr_t dma_addr_max;
368 int error = 0, i, msic, phyloc, reg, rid;
370 sc = device_get_softc(dev);
373 mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
375 callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0);
377 pci_enable_busmaster(dev);
380 sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
382 if (sc->nfe_res[0] == NULL) {
383 device_printf(dev, "couldn't map memory resources\n");
384 mtx_destroy(&sc->nfe_mtx);
388 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
391 v = pci_read_config(dev, reg + 0x08, 2);
392 /* Change max. read request size to 4096. */
395 pci_write_config(dev, reg + 0x08, v, 2);
397 v = pci_read_config(dev, reg + 0x0c, 2);
398 /* link capability */
400 width = pci_read_config(dev, reg + 0x12, 2);
401 /* negotiated link width */
402 width = (width >> 4) & 0x3f;
404 device_printf(sc->nfe_dev,
405 "warning, negotiated width of link(x%d) != "
406 "max. width of link(x%d)\n", width, v);
409 if (nfe_can_use_msix(sc) == 0) {
410 device_printf(sc->nfe_dev,
411 "MSI/MSI-X capability black-listed, will use INTx\n");
416 /* Allocate interrupt */
417 if (msix_disable == 0 || msi_disable == 0) {
418 if (msix_disable == 0 &&
419 (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES)
420 nfe_alloc_msix(sc, msic);
421 if (msi_disable == 0 && sc->nfe_msix == 0 &&
422 (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES &&
423 pci_alloc_msi(dev, &msic) == 0) {
424 if (msic == NFE_MSI_MESSAGES) {
427 "Using %d MSI messages\n", msic);
430 pci_release_msi(dev);
434 if (sc->nfe_msix == 0 && sc->nfe_msi == 0) {
436 sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
437 RF_SHAREABLE | RF_ACTIVE);
438 if (sc->nfe_irq[0] == NULL) {
439 device_printf(dev, "couldn't allocate IRQ resources\n");
444 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) {
445 sc->nfe_irq[i] = bus_alloc_resource_any(dev,
446 SYS_RES_IRQ, &rid, RF_ACTIVE);
447 if (sc->nfe_irq[i] == NULL) {
449 "couldn't allocate IRQ resources for "
450 "message %d\n", rid);
455 /* Map interrupts to vector 0. */
456 if (sc->nfe_msix != 0) {
457 NFE_WRITE(sc, NFE_MSIX_MAP0, 0);
458 NFE_WRITE(sc, NFE_MSIX_MAP1, 0);
459 } else if (sc->nfe_msi != 0) {
460 NFE_WRITE(sc, NFE_MSI_MAP0, 0);
461 NFE_WRITE(sc, NFE_MSI_MAP1, 0);
465 /* Set IRQ status/mask register. */
466 sc->nfe_irq_status = NFE_IRQ_STATUS;
467 sc->nfe_irq_mask = NFE_IRQ_MASK;
468 sc->nfe_intrs = NFE_IRQ_WANTED;
470 if (sc->nfe_msix != 0) {
471 sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS;
472 sc->nfe_nointrs = NFE_IRQ_WANTED;
473 } else if (sc->nfe_msi != 0) {
474 sc->nfe_irq_mask = NFE_MSI_IRQ_MASK;
475 sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED;
478 sc->nfe_devid = pci_get_device(dev);
479 sc->nfe_revid = pci_get_revid(dev);
482 switch (sc->nfe_devid) {
483 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
484 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
485 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
486 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
487 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM;
489 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
490 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
491 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | NFE_MIB_V1;
493 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
494 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
495 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
496 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
497 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM |
500 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
501 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
502 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM |
503 NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL | NFE_MIB_V2;
506 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
507 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
508 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
509 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
510 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
511 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
512 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
513 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
514 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
515 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
516 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
517 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
518 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT |
519 NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | NFE_MIB_V2;
521 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
522 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
523 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
524 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
525 /* XXX flow control */
526 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | NFE_PWR_MGMT |
527 NFE_CORRECT_MACADDR | NFE_MIB_V3;
529 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
530 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
531 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
532 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
533 /* XXX flow control */
534 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM |
535 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_MIB_V3;
537 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
538 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
539 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
540 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
541 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR |
542 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL |
548 /* Check for reversed ethernet address */
549 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0)
550 sc->nfe_flags |= NFE_CORRECT_MACADDR;
551 nfe_get_macaddr(sc, sc->eaddr);
553 * Allocate the parent bus DMA tag appropriate for PCI.
555 dma_addr_max = BUS_SPACE_MAXADDR_32BIT;
556 if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0)
557 dma_addr_max = NFE_DMA_MAXADDR;
558 error = bus_dma_tag_create(
559 bus_get_dma_tag(sc->nfe_dev), /* parent */
560 1, 0, /* alignment, boundary */
561 dma_addr_max, /* lowaddr */
562 BUS_SPACE_MAXADDR, /* highaddr */
563 NULL, NULL, /* filter, filterarg */
564 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
565 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
567 NULL, NULL, /* lockfunc, lockarg */
568 &sc->nfe_parent_tag);
572 ifp = sc->nfe_ifp = if_alloc(IFT_ETHER);
574 device_printf(dev, "can not if_alloc()\n");
580 * Allocate Tx and Rx rings.
582 if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0)
585 if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0)
588 nfe_alloc_jrx_ring(sc, &sc->jrxq);
589 /* Create sysctl node. */
593 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
594 ifp->if_mtu = ETHERMTU;
595 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
596 ifp->if_ioctl = nfe_ioctl;
597 ifp->if_start = nfe_start;
598 ifp->if_hwassist = 0;
599 ifp->if_capabilities = 0;
600 ifp->if_init = nfe_init;
601 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_TX_RING_COUNT - 1);
602 ifp->if_snd.ifq_drv_maxlen = NFE_TX_RING_COUNT - 1;
603 IFQ_SET_READY(&ifp->if_snd);
605 if (sc->nfe_flags & NFE_HW_CSUM) {
606 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4;
607 ifp->if_hwassist |= NFE_CSUM_FEATURES | CSUM_TSO;
609 ifp->if_capenable = ifp->if_capabilities;
611 sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS;
612 /* VLAN capability setup. */
613 ifp->if_capabilities |= IFCAP_VLAN_MTU;
614 if ((sc->nfe_flags & NFE_HW_VLAN) != 0) {
615 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
616 if ((ifp->if_capabilities & IFCAP_HWCSUM) != 0)
617 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM |
621 if (pci_find_cap(dev, PCIY_PMG, ®) == 0)
622 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
623 ifp->if_capenable = ifp->if_capabilities;
626 * Tell the upper layer(s) we support long frames.
627 * Must appear after the call to ether_ifattach() because
628 * ether_ifattach() sets ifi_hdrlen to the default value.
630 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
632 #ifdef DEVICE_POLLING
633 ifp->if_capabilities |= IFCAP_POLLING;
637 phyloc = MII_PHY_ANY;
638 if (sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN1 ||
639 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN2 ||
640 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN3 ||
641 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN4) {
642 if (nfe_detect_msik9(sc) != 0)
645 error = mii_attach(dev, &sc->nfe_miibus, ifp, nfe_ifmedia_upd,
646 nfe_ifmedia_sts, BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY,
649 device_printf(dev, "attaching PHYs failed\n");
652 ether_ifattach(ifp, sc->eaddr);
654 TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc);
655 sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK,
656 taskqueue_thread_enqueue, &sc->nfe_tq);
657 taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq",
658 device_get_nameunit(sc->nfe_dev));
660 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) {
661 error = bus_setup_intr(dev, sc->nfe_irq[0],
662 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc,
663 &sc->nfe_intrhand[0]);
665 for (i = 0; i < NFE_MSI_MESSAGES; i++) {
666 error = bus_setup_intr(dev, sc->nfe_irq[i],
667 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc,
668 &sc->nfe_intrhand[i]);
674 device_printf(dev, "couldn't set up irq\n");
675 taskqueue_free(sc->nfe_tq);
690 nfe_detach(device_t dev)
692 struct nfe_softc *sc;
694 uint8_t eaddr[ETHER_ADDR_LEN];
697 sc = device_get_softc(dev);
698 KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized"));
701 #ifdef DEVICE_POLLING
702 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
703 ether_poll_deregister(ifp);
705 if (device_is_attached(dev)) {
708 ifp->if_flags &= ~IFF_UP;
710 callout_drain(&sc->nfe_stat_ch);
715 /* restore ethernet address */
716 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) {
717 for (i = 0; i < ETHER_ADDR_LEN; i++) {
718 eaddr[i] = sc->eaddr[5 - i];
721 bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN);
722 nfe_set_macaddr(sc, eaddr);
726 device_delete_child(dev, sc->nfe_miibus);
727 bus_generic_detach(dev);
728 if (sc->nfe_tq != NULL) {
729 taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task);
730 taskqueue_free(sc->nfe_tq);
734 for (i = 0; i < NFE_MSI_MESSAGES; i++) {
735 if (sc->nfe_intrhand[i] != NULL) {
736 bus_teardown_intr(dev, sc->nfe_irq[i],
737 sc->nfe_intrhand[i]);
738 sc->nfe_intrhand[i] = NULL;
742 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) {
743 if (sc->nfe_irq[0] != NULL)
744 bus_release_resource(dev, SYS_RES_IRQ, 0,
747 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) {
748 if (sc->nfe_irq[i] != NULL) {
749 bus_release_resource(dev, SYS_RES_IRQ, rid,
751 sc->nfe_irq[i] = NULL;
754 pci_release_msi(dev);
756 if (sc->nfe_msix_pba_res != NULL) {
757 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3),
758 sc->nfe_msix_pba_res);
759 sc->nfe_msix_pba_res = NULL;
761 if (sc->nfe_msix_res != NULL) {
762 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2),
764 sc->nfe_msix_res = NULL;
766 if (sc->nfe_res[0] != NULL) {
767 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
769 sc->nfe_res[0] = NULL;
772 nfe_free_tx_ring(sc, &sc->txq);
773 nfe_free_rx_ring(sc, &sc->rxq);
774 nfe_free_jrx_ring(sc, &sc->jrxq);
776 if (sc->nfe_parent_tag) {
777 bus_dma_tag_destroy(sc->nfe_parent_tag);
778 sc->nfe_parent_tag = NULL;
781 mtx_destroy(&sc->nfe_mtx);
788 nfe_suspend(device_t dev)
790 struct nfe_softc *sc;
792 sc = device_get_softc(dev);
795 nfe_stop(sc->nfe_ifp);
797 sc->nfe_suspended = 1;
805 nfe_resume(device_t dev)
807 struct nfe_softc *sc;
810 sc = device_get_softc(dev);
815 if (ifp->if_flags & IFF_UP)
817 sc->nfe_suspended = 0;
825 nfe_can_use_msix(struct nfe_softc *sc)
827 static struct msix_blacklist {
830 } msix_blacklists[] = {
831 { "ASUSTeK Computer INC.", "P5N32-SLI PREMIUM" }
834 struct msix_blacklist *mblp;
835 char *maker, *product;
836 int count, n, use_msix;
839 * Search base board manufacturer and product name table
840 * to see this system has a known MSI/MSI-X issue.
842 maker = getenv("smbios.planar.maker");
843 product = getenv("smbios.planar.product");
845 if (maker != NULL && product != NULL) {
846 count = sizeof(msix_blacklists) / sizeof(msix_blacklists[0]);
847 mblp = msix_blacklists;
848 for (n = 0; n < count; n++) {
849 if (strcmp(maker, mblp->maker) == 0 &&
850 strcmp(product, mblp->product) == 0) {
866 /* Take PHY/NIC out of powerdown, from Linux */
868 nfe_power(struct nfe_softc *sc)
872 if ((sc->nfe_flags & NFE_PWR_MGMT) == 0)
874 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2);
875 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC);
877 NFE_WRITE(sc, NFE_MAC_RESET, 0);
879 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2);
880 pwr = NFE_READ(sc, NFE_PWR2_CTL);
881 pwr &= ~NFE_PWR2_WAKEUP_MASK;
882 if (sc->nfe_revid >= 0xa3 &&
883 (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 ||
884 sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2))
885 pwr |= NFE_PWR2_REVA3;
886 NFE_WRITE(sc, NFE_PWR2_CTL, pwr);
891 nfe_miibus_statchg(device_t dev)
893 struct nfe_softc *sc;
894 struct mii_data *mii;
896 uint32_t rxctl, txctl;
898 sc = device_get_softc(dev);
900 mii = device_get_softc(sc->nfe_miibus);
904 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
905 (IFM_ACTIVE | IFM_AVALID)) {
906 switch (IFM_SUBTYPE(mii->mii_media_active)) {
917 nfe_mac_config(sc, mii);
918 txctl = NFE_READ(sc, NFE_TX_CTL);
919 rxctl = NFE_READ(sc, NFE_RX_CTL);
920 if (sc->nfe_link != 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
921 txctl |= NFE_TX_START;
922 rxctl |= NFE_RX_START;
924 txctl &= ~NFE_TX_START;
925 rxctl &= ~NFE_RX_START;
927 NFE_WRITE(sc, NFE_TX_CTL, txctl);
928 NFE_WRITE(sc, NFE_RX_CTL, rxctl);
933 nfe_mac_config(struct nfe_softc *sc, struct mii_data *mii)
935 uint32_t link, misc, phy, seed;
940 phy = NFE_READ(sc, NFE_PHY_IFACE);
941 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
943 seed = NFE_READ(sc, NFE_RNDSEED);
944 seed &= ~NFE_SEED_MASK;
946 misc = NFE_MISC1_MAGIC;
947 link = NFE_MEDIA_SET;
949 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) {
950 phy |= NFE_PHY_HDX; /* half-duplex */
951 misc |= NFE_MISC1_HDX;
954 switch (IFM_SUBTYPE(mii->mii_media_active)) {
955 case IFM_1000_T: /* full-duplex only */
956 link |= NFE_MEDIA_1000T;
957 seed |= NFE_SEED_1000T;
958 phy |= NFE_PHY_1000T;
961 link |= NFE_MEDIA_100TX;
962 seed |= NFE_SEED_100TX;
963 phy |= NFE_PHY_100TX;
966 link |= NFE_MEDIA_10T;
967 seed |= NFE_SEED_10T;
971 if ((phy & 0x10000000) != 0) {
972 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
973 val = NFE_R1_MAGIC_1000;
975 val = NFE_R1_MAGIC_10_100;
977 val = NFE_R1_MAGIC_DEFAULT;
978 NFE_WRITE(sc, NFE_SETUP_R1, val);
980 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
982 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
983 NFE_WRITE(sc, NFE_MISC1, misc);
984 NFE_WRITE(sc, NFE_LINKSPEED, link);
986 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
987 /* It seems all hardwares supports Rx pause frames. */
988 val = NFE_READ(sc, NFE_RXFILTER);
989 if ((IFM_OPTIONS(mii->mii_media_active) &
990 IFM_ETH_RXPAUSE) != 0)
991 val |= NFE_PFF_RX_PAUSE;
993 val &= ~NFE_PFF_RX_PAUSE;
994 NFE_WRITE(sc, NFE_RXFILTER, val);
995 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) {
996 val = NFE_READ(sc, NFE_MISC1);
997 if ((IFM_OPTIONS(mii->mii_media_active) &
998 IFM_ETH_TXPAUSE) != 0) {
999 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
1000 NFE_TX_PAUSE_FRAME_ENABLE);
1001 val |= NFE_MISC1_TX_PAUSE;
1003 val &= ~NFE_MISC1_TX_PAUSE;
1004 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
1005 NFE_TX_PAUSE_FRAME_DISABLE);
1007 NFE_WRITE(sc, NFE_MISC1, val);
1010 /* disable rx/tx pause frames */
1011 val = NFE_READ(sc, NFE_RXFILTER);
1012 val &= ~NFE_PFF_RX_PAUSE;
1013 NFE_WRITE(sc, NFE_RXFILTER, val);
1014 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) {
1015 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
1016 NFE_TX_PAUSE_FRAME_DISABLE);
1017 val = NFE_READ(sc, NFE_MISC1);
1018 val &= ~NFE_MISC1_TX_PAUSE;
1019 NFE_WRITE(sc, NFE_MISC1, val);
1026 nfe_miibus_readreg(device_t dev, int phy, int reg)
1028 struct nfe_softc *sc = device_get_softc(dev);
1032 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1034 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
1035 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
1039 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
1041 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) {
1043 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
1046 if (ntries == NFE_TIMEOUT) {
1047 DPRINTFN(sc, 2, "timeout waiting for PHY\n");
1051 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
1052 DPRINTFN(sc, 2, "could not read PHY\n");
1056 val = NFE_READ(sc, NFE_PHY_DATA);
1057 if (val != 0xffffffff && val != 0)
1058 sc->mii_phyaddr = phy;
1060 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
1067 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
1069 struct nfe_softc *sc = device_get_softc(dev);
1073 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1075 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
1076 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
1080 NFE_WRITE(sc, NFE_PHY_DATA, val);
1081 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
1082 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
1084 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) {
1086 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
1090 if (nfedebug >= 2 && ntries == NFE_TIMEOUT)
1091 device_printf(sc->nfe_dev, "could not write to PHY\n");
1096 struct nfe_dmamap_arg {
1097 bus_addr_t nfe_busaddr;
1101 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1103 struct nfe_dmamap_arg ctx;
1104 struct nfe_rx_data *data;
1106 int i, error, descsize;
1108 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1109 desc = ring->desc64;
1110 descsize = sizeof (struct nfe_desc64);
1112 desc = ring->desc32;
1113 descsize = sizeof (struct nfe_desc32);
1116 ring->cur = ring->next = 0;
1118 error = bus_dma_tag_create(sc->nfe_parent_tag,
1119 NFE_RING_ALIGN, 0, /* alignment, boundary */
1120 BUS_SPACE_MAXADDR, /* lowaddr */
1121 BUS_SPACE_MAXADDR, /* highaddr */
1122 NULL, NULL, /* filter, filterarg */
1123 NFE_RX_RING_COUNT * descsize, 1, /* maxsize, nsegments */
1124 NFE_RX_RING_COUNT * descsize, /* maxsegsize */
1126 NULL, NULL, /* lockfunc, lockarg */
1127 &ring->rx_desc_tag);
1129 device_printf(sc->nfe_dev, "could not create desc DMA tag\n");
1133 /* allocate memory to desc */
1134 error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK |
1135 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map);
1137 device_printf(sc->nfe_dev, "could not create desc DMA map\n");
1140 if (sc->nfe_flags & NFE_40BIT_ADDR)
1141 ring->desc64 = desc;
1143 ring->desc32 = desc;
1145 /* map desc to device visible address space */
1146 ctx.nfe_busaddr = 0;
1147 error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc,
1148 NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0);
1150 device_printf(sc->nfe_dev, "could not load desc DMA map\n");
1153 ring->physaddr = ctx.nfe_busaddr;
1155 error = bus_dma_tag_create(sc->nfe_parent_tag,
1156 1, 0, /* alignment, boundary */
1157 BUS_SPACE_MAXADDR, /* lowaddr */
1158 BUS_SPACE_MAXADDR, /* highaddr */
1159 NULL, NULL, /* filter, filterarg */
1160 MCLBYTES, 1, /* maxsize, nsegments */
1161 MCLBYTES, /* maxsegsize */
1163 NULL, NULL, /* lockfunc, lockarg */
1164 &ring->rx_data_tag);
1166 device_printf(sc->nfe_dev, "could not create Rx DMA tag\n");
1170 error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map);
1172 device_printf(sc->nfe_dev,
1173 "could not create Rx DMA spare map\n");
1178 * Pre-allocate Rx buffers and populate Rx ring.
1180 for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1181 data = &sc->rxq.data[i];
1182 data->rx_data_map = NULL;
1184 error = bus_dmamap_create(ring->rx_data_tag, 0,
1185 &data->rx_data_map);
1187 device_printf(sc->nfe_dev,
1188 "could not create Rx DMA map\n");
1199 nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring)
1201 struct nfe_dmamap_arg ctx;
1202 struct nfe_rx_data *data;
1204 int i, error, descsize;
1206 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0)
1208 if (jumbo_disable != 0) {
1209 device_printf(sc->nfe_dev, "disabling jumbo frame support\n");
1210 sc->nfe_jumbo_disable = 1;
1214 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1215 desc = ring->jdesc64;
1216 descsize = sizeof (struct nfe_desc64);
1218 desc = ring->jdesc32;
1219 descsize = sizeof (struct nfe_desc32);
1222 ring->jcur = ring->jnext = 0;
1224 /* Create DMA tag for jumbo Rx ring. */
1225 error = bus_dma_tag_create(sc->nfe_parent_tag,
1226 NFE_RING_ALIGN, 0, /* alignment, boundary */
1227 BUS_SPACE_MAXADDR, /* lowaddr */
1228 BUS_SPACE_MAXADDR, /* highaddr */
1229 NULL, NULL, /* filter, filterarg */
1230 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsize */
1232 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsegsize */
1234 NULL, NULL, /* lockfunc, lockarg */
1235 &ring->jrx_desc_tag);
1237 device_printf(sc->nfe_dev,
1238 "could not create jumbo ring DMA tag\n");
1242 /* Create DMA tag for jumbo Rx buffers. */
1243 error = bus_dma_tag_create(sc->nfe_parent_tag,
1244 1, 0, /* alignment, boundary */
1245 BUS_SPACE_MAXADDR, /* lowaddr */
1246 BUS_SPACE_MAXADDR, /* highaddr */
1247 NULL, NULL, /* filter, filterarg */
1248 MJUM9BYTES, /* maxsize */
1250 MJUM9BYTES, /* maxsegsize */
1252 NULL, NULL, /* lockfunc, lockarg */
1253 &ring->jrx_data_tag);
1255 device_printf(sc->nfe_dev,
1256 "could not create jumbo Rx buffer DMA tag\n");
1260 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
1261 error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK |
1262 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map);
1264 device_printf(sc->nfe_dev,
1265 "could not allocate DMA'able memory for jumbo Rx ring\n");
1268 if (sc->nfe_flags & NFE_40BIT_ADDR)
1269 ring->jdesc64 = desc;
1271 ring->jdesc32 = desc;
1273 ctx.nfe_busaddr = 0;
1274 error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc,
1275 NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0);
1277 device_printf(sc->nfe_dev,
1278 "could not load DMA'able memory for jumbo Rx ring\n");
1281 ring->jphysaddr = ctx.nfe_busaddr;
1283 /* Create DMA maps for jumbo Rx buffers. */
1284 error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map);
1286 device_printf(sc->nfe_dev,
1287 "could not create jumbo Rx DMA spare map\n");
1291 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) {
1292 data = &sc->jrxq.jdata[i];
1293 data->rx_data_map = NULL;
1295 error = bus_dmamap_create(ring->jrx_data_tag, 0,
1296 &data->rx_data_map);
1298 device_printf(sc->nfe_dev,
1299 "could not create jumbo Rx DMA map\n");
1308 * Running without jumbo frame support is ok for most cases
1309 * so don't fail on creating dma tag/map for jumbo frame.
1311 nfe_free_jrx_ring(sc, ring);
1312 device_printf(sc->nfe_dev, "disabling jumbo frame support due to "
1313 "resource shortage\n");
1314 sc->nfe_jumbo_disable = 1;
1319 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1325 ring->cur = ring->next = 0;
1326 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1327 desc = ring->desc64;
1328 descsize = sizeof (struct nfe_desc64);
1330 desc = ring->desc32;
1331 descsize = sizeof (struct nfe_desc32);
1333 bzero(desc, descsize * NFE_RX_RING_COUNT);
1334 for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1335 if (nfe_newbuf(sc, i) != 0)
1339 bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map,
1340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1347 nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring)
1353 ring->jcur = ring->jnext = 0;
1354 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1355 desc = ring->jdesc64;
1356 descsize = sizeof (struct nfe_desc64);
1358 desc = ring->jdesc32;
1359 descsize = sizeof (struct nfe_desc32);
1361 bzero(desc, descsize * NFE_JUMBO_RX_RING_COUNT);
1362 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) {
1363 if (nfe_jnewbuf(sc, i) != 0)
1367 bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map,
1368 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1375 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1377 struct nfe_rx_data *data;
1381 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1382 desc = ring->desc64;
1383 descsize = sizeof (struct nfe_desc64);
1385 desc = ring->desc32;
1386 descsize = sizeof (struct nfe_desc32);
1389 for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1390 data = &ring->data[i];
1391 if (data->rx_data_map != NULL) {
1392 bus_dmamap_destroy(ring->rx_data_tag,
1394 data->rx_data_map = NULL;
1396 if (data->m != NULL) {
1401 if (ring->rx_data_tag != NULL) {
1402 if (ring->rx_spare_map != NULL) {
1403 bus_dmamap_destroy(ring->rx_data_tag,
1404 ring->rx_spare_map);
1405 ring->rx_spare_map = NULL;
1407 bus_dma_tag_destroy(ring->rx_data_tag);
1408 ring->rx_data_tag = NULL;
1412 bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map);
1413 bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map);
1414 ring->desc64 = NULL;
1415 ring->desc32 = NULL;
1416 ring->rx_desc_map = NULL;
1418 if (ring->rx_desc_tag != NULL) {
1419 bus_dma_tag_destroy(ring->rx_desc_tag);
1420 ring->rx_desc_tag = NULL;
1426 nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring)
1428 struct nfe_rx_data *data;
1432 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0)
1435 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1436 desc = ring->jdesc64;
1437 descsize = sizeof (struct nfe_desc64);
1439 desc = ring->jdesc32;
1440 descsize = sizeof (struct nfe_desc32);
1443 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) {
1444 data = &ring->jdata[i];
1445 if (data->rx_data_map != NULL) {
1446 bus_dmamap_destroy(ring->jrx_data_tag,
1448 data->rx_data_map = NULL;
1450 if (data->m != NULL) {
1455 if (ring->jrx_data_tag != NULL) {
1456 if (ring->jrx_spare_map != NULL) {
1457 bus_dmamap_destroy(ring->jrx_data_tag,
1458 ring->jrx_spare_map);
1459 ring->jrx_spare_map = NULL;
1461 bus_dma_tag_destroy(ring->jrx_data_tag);
1462 ring->jrx_data_tag = NULL;
1466 bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map);
1467 bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map);
1468 ring->jdesc64 = NULL;
1469 ring->jdesc32 = NULL;
1470 ring->jrx_desc_map = NULL;
1473 if (ring->jrx_desc_tag != NULL) {
1474 bus_dma_tag_destroy(ring->jrx_desc_tag);
1475 ring->jrx_desc_tag = NULL;
1481 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1483 struct nfe_dmamap_arg ctx;
1488 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1489 desc = ring->desc64;
1490 descsize = sizeof (struct nfe_desc64);
1492 desc = ring->desc32;
1493 descsize = sizeof (struct nfe_desc32);
1497 ring->cur = ring->next = 0;
1499 error = bus_dma_tag_create(sc->nfe_parent_tag,
1500 NFE_RING_ALIGN, 0, /* alignment, boundary */
1501 BUS_SPACE_MAXADDR, /* lowaddr */
1502 BUS_SPACE_MAXADDR, /* highaddr */
1503 NULL, NULL, /* filter, filterarg */
1504 NFE_TX_RING_COUNT * descsize, 1, /* maxsize, nsegments */
1505 NFE_TX_RING_COUNT * descsize, /* maxsegsize */
1507 NULL, NULL, /* lockfunc, lockarg */
1508 &ring->tx_desc_tag);
1510 device_printf(sc->nfe_dev, "could not create desc DMA tag\n");
1514 error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK |
1515 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map);
1517 device_printf(sc->nfe_dev, "could not create desc DMA map\n");
1520 if (sc->nfe_flags & NFE_40BIT_ADDR)
1521 ring->desc64 = desc;
1523 ring->desc32 = desc;
1525 ctx.nfe_busaddr = 0;
1526 error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc,
1527 NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0);
1529 device_printf(sc->nfe_dev, "could not load desc DMA map\n");
1532 ring->physaddr = ctx.nfe_busaddr;
1534 error = bus_dma_tag_create(sc->nfe_parent_tag,
1544 &ring->tx_data_tag);
1546 device_printf(sc->nfe_dev, "could not create Tx DMA tag\n");
1550 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1551 error = bus_dmamap_create(ring->tx_data_tag, 0,
1552 &ring->data[i].tx_data_map);
1554 device_printf(sc->nfe_dev,
1555 "could not create Tx DMA map\n");
1566 nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1571 sc->nfe_force_tx = 0;
1573 ring->cur = ring->next = 0;
1574 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1575 desc = ring->desc64;
1576 descsize = sizeof (struct nfe_desc64);
1578 desc = ring->desc32;
1579 descsize = sizeof (struct nfe_desc32);
1581 bzero(desc, descsize * NFE_TX_RING_COUNT);
1583 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map,
1584 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1589 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1591 struct nfe_tx_data *data;
1595 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1596 desc = ring->desc64;
1597 descsize = sizeof (struct nfe_desc64);
1599 desc = ring->desc32;
1600 descsize = sizeof (struct nfe_desc32);
1603 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1604 data = &ring->data[i];
1606 if (data->m != NULL) {
1607 bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map,
1608 BUS_DMASYNC_POSTWRITE);
1609 bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map);
1613 if (data->tx_data_map != NULL) {
1614 bus_dmamap_destroy(ring->tx_data_tag,
1616 data->tx_data_map = NULL;
1620 if (ring->tx_data_tag != NULL) {
1621 bus_dma_tag_destroy(ring->tx_data_tag);
1622 ring->tx_data_tag = NULL;
1626 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map,
1627 BUS_DMASYNC_POSTWRITE);
1628 bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map);
1629 bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map);
1630 ring->desc64 = NULL;
1631 ring->desc32 = NULL;
1632 ring->tx_desc_map = NULL;
1633 bus_dma_tag_destroy(ring->tx_desc_tag);
1634 ring->tx_desc_tag = NULL;
1638 #ifdef DEVICE_POLLING
1639 static poll_handler_t nfe_poll;
1643 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1645 struct nfe_softc *sc = ifp->if_softc;
1651 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1656 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN)
1657 rx_npkts = nfe_jrxeof(sc, count, &rx_npkts);
1659 rx_npkts = nfe_rxeof(sc, count, &rx_npkts);
1661 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1662 nfe_start_locked(ifp);
1664 if (cmd == POLL_AND_CHECK_STATUS) {
1665 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) {
1669 NFE_WRITE(sc, sc->nfe_irq_status, r);
1671 if (r & NFE_IRQ_LINK) {
1672 NFE_READ(sc, NFE_PHY_STATUS);
1673 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1674 DPRINTF(sc, "link state changed\n");
1680 #endif /* DEVICE_POLLING */
1683 nfe_set_intr(struct nfe_softc *sc)
1686 if (sc->nfe_msi != 0)
1687 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED);
1691 /* In MSIX, a write to mask reegisters behaves as XOR. */
1692 static __inline void
1693 nfe_enable_intr(struct nfe_softc *sc)
1696 if (sc->nfe_msix != 0) {
1697 /* XXX Should have a better way to enable interrupts! */
1698 if (NFE_READ(sc, sc->nfe_irq_mask) == 0)
1699 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs);
1701 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs);
1705 static __inline void
1706 nfe_disable_intr(struct nfe_softc *sc)
1709 if (sc->nfe_msix != 0) {
1710 /* XXX Should have a better way to disable interrupts! */
1711 if (NFE_READ(sc, sc->nfe_irq_mask) != 0)
1712 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs);
1714 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs);
1719 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1721 struct nfe_softc *sc;
1723 struct mii_data *mii;
1724 int error, init, mask;
1727 ifr = (struct ifreq *) data;
1732 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU)
1734 else if (ifp->if_mtu != ifr->ifr_mtu) {
1735 if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) ||
1736 (sc->nfe_jumbo_disable != 0)) &&
1737 ifr->ifr_mtu > ETHERMTU)
1741 ifp->if_mtu = ifr->ifr_mtu;
1742 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1743 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1744 nfe_init_locked(sc);
1752 if (ifp->if_flags & IFF_UP) {
1754 * If only the PROMISC or ALLMULTI flag changes, then
1755 * don't do a full re-init of the chip, just update
1758 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
1759 ((ifp->if_flags ^ sc->nfe_if_flags) &
1760 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
1763 nfe_init_locked(sc);
1765 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1768 sc->nfe_if_flags = ifp->if_flags;
1774 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1783 mii = device_get_softc(sc->nfe_miibus);
1784 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1787 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1788 #ifdef DEVICE_POLLING
1789 if ((mask & IFCAP_POLLING) != 0) {
1790 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1791 error = ether_poll_register(nfe_poll, ifp);
1795 nfe_disable_intr(sc);
1796 ifp->if_capenable |= IFCAP_POLLING;
1799 error = ether_poll_deregister(ifp);
1800 /* Enable interrupt even in error case */
1802 nfe_enable_intr(sc);
1803 ifp->if_capenable &= ~IFCAP_POLLING;
1807 #endif /* DEVICE_POLLING */
1808 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1809 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1810 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1811 if ((mask & IFCAP_TXCSUM) != 0 &&
1812 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1813 ifp->if_capenable ^= IFCAP_TXCSUM;
1814 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1815 ifp->if_hwassist |= NFE_CSUM_FEATURES;
1817 ifp->if_hwassist &= ~NFE_CSUM_FEATURES;
1819 if ((mask & IFCAP_RXCSUM) != 0 &&
1820 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1821 ifp->if_capenable ^= IFCAP_RXCSUM;
1824 if ((mask & IFCAP_TSO4) != 0 &&
1825 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1826 ifp->if_capenable ^= IFCAP_TSO4;
1827 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
1828 ifp->if_hwassist |= CSUM_TSO;
1830 ifp->if_hwassist &= ~CSUM_TSO;
1832 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1833 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1834 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1835 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1836 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1837 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1838 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1839 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
1844 * It seems that VLAN stripping requires Rx checksum offload.
1845 * Unfortunately FreeBSD has no way to disable only Rx side
1846 * VLAN stripping. So when we know Rx checksum offload is
1847 * disabled turn entire hardware VLAN assist off.
1849 if ((ifp->if_capenable & IFCAP_RXCSUM) == 0) {
1850 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
1852 ifp->if_capenable &= ~(IFCAP_VLAN_HWTAGGING |
1855 if (init > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1856 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1859 VLAN_CAPABILITIES(ifp);
1862 error = ether_ioctl(ifp, cmd, data);
1873 struct nfe_softc *sc;
1876 sc = (struct nfe_softc *)arg;
1878 status = NFE_READ(sc, sc->nfe_irq_status);
1879 if (status == 0 || status == 0xffffffff)
1880 return (FILTER_STRAY);
1881 nfe_disable_intr(sc);
1882 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task);
1884 return (FILTER_HANDLED);
1889 nfe_int_task(void *arg, int pending)
1891 struct nfe_softc *sc = arg;
1892 struct ifnet *ifp = sc->nfe_ifp;
1898 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) {
1899 nfe_enable_intr(sc);
1901 return; /* not for us */
1903 NFE_WRITE(sc, sc->nfe_irq_status, r);
1905 DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r);
1907 #ifdef DEVICE_POLLING
1908 if (ifp->if_capenable & IFCAP_POLLING) {
1914 if (r & NFE_IRQ_LINK) {
1915 NFE_READ(sc, NFE_PHY_STATUS);
1916 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1917 DPRINTF(sc, "link state changed\n");
1920 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1922 nfe_disable_intr(sc);
1928 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN)
1929 domore = nfe_jrxeof(sc, sc->nfe_process_limit, NULL);
1931 domore = nfe_rxeof(sc, sc->nfe_process_limit, NULL);
1935 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1936 nfe_start_locked(ifp);
1940 if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) {
1941 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task);
1945 /* Reenable interrupts. */
1946 nfe_enable_intr(sc);
1950 static __inline void
1951 nfe_discard_rxbuf(struct nfe_softc *sc, int idx)
1953 struct nfe_desc32 *desc32;
1954 struct nfe_desc64 *desc64;
1955 struct nfe_rx_data *data;
1958 data = &sc->rxq.data[idx];
1961 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1962 desc64 = &sc->rxq.desc64[idx];
1963 /* VLAN packet may have overwritten it. */
1964 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr));
1965 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr));
1966 desc64->length = htole16(m->m_len);
1967 desc64->flags = htole16(NFE_RX_READY);
1969 desc32 = &sc->rxq.desc32[idx];
1970 desc32->length = htole16(m->m_len);
1971 desc32->flags = htole16(NFE_RX_READY);
1976 static __inline void
1977 nfe_discard_jrxbuf(struct nfe_softc *sc, int idx)
1979 struct nfe_desc32 *desc32;
1980 struct nfe_desc64 *desc64;
1981 struct nfe_rx_data *data;
1984 data = &sc->jrxq.jdata[idx];
1987 if (sc->nfe_flags & NFE_40BIT_ADDR) {
1988 desc64 = &sc->jrxq.jdesc64[idx];
1989 /* VLAN packet may have overwritten it. */
1990 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr));
1991 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr));
1992 desc64->length = htole16(m->m_len);
1993 desc64->flags = htole16(NFE_RX_READY);
1995 desc32 = &sc->jrxq.jdesc32[idx];
1996 desc32->length = htole16(m->m_len);
1997 desc32->flags = htole16(NFE_RX_READY);
2003 nfe_newbuf(struct nfe_softc *sc, int idx)
2005 struct nfe_rx_data *data;
2006 struct nfe_desc32 *desc32;
2007 struct nfe_desc64 *desc64;
2009 bus_dma_segment_t segs[1];
2013 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2017 m->m_len = m->m_pkthdr.len = MCLBYTES;
2018 m_adj(m, ETHER_ALIGN);
2020 if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map,
2021 m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) {
2025 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2027 data = &sc->rxq.data[idx];
2028 if (data->m != NULL) {
2029 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map,
2030 BUS_DMASYNC_POSTREAD);
2031 bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map);
2033 map = data->rx_data_map;
2034 data->rx_data_map = sc->rxq.rx_spare_map;
2035 sc->rxq.rx_spare_map = map;
2036 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map,
2037 BUS_DMASYNC_PREREAD);
2038 data->paddr = segs[0].ds_addr;
2040 /* update mapping address in h/w descriptor */
2041 if (sc->nfe_flags & NFE_40BIT_ADDR) {
2042 desc64 = &sc->rxq.desc64[idx];
2043 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr));
2044 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr));
2045 desc64->length = htole16(segs[0].ds_len);
2046 desc64->flags = htole16(NFE_RX_READY);
2048 desc32 = &sc->rxq.desc32[idx];
2049 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr));
2050 desc32->length = htole16(segs[0].ds_len);
2051 desc32->flags = htole16(NFE_RX_READY);
2059 nfe_jnewbuf(struct nfe_softc *sc, int idx)
2061 struct nfe_rx_data *data;
2062 struct nfe_desc32 *desc32;
2063 struct nfe_desc64 *desc64;
2065 bus_dma_segment_t segs[1];
2069 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
2072 if ((m->m_flags & M_EXT) == 0) {
2076 m->m_pkthdr.len = m->m_len = MJUM9BYTES;
2077 m_adj(m, ETHER_ALIGN);
2079 if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag,
2080 sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) {
2084 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2086 data = &sc->jrxq.jdata[idx];
2087 if (data->m != NULL) {
2088 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map,
2089 BUS_DMASYNC_POSTREAD);
2090 bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map);
2092 map = data->rx_data_map;
2093 data->rx_data_map = sc->jrxq.jrx_spare_map;
2094 sc->jrxq.jrx_spare_map = map;
2095 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map,
2096 BUS_DMASYNC_PREREAD);
2097 data->paddr = segs[0].ds_addr;
2099 /* update mapping address in h/w descriptor */
2100 if (sc->nfe_flags & NFE_40BIT_ADDR) {
2101 desc64 = &sc->jrxq.jdesc64[idx];
2102 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr));
2103 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr));
2104 desc64->length = htole16(segs[0].ds_len);
2105 desc64->flags = htole16(NFE_RX_READY);
2107 desc32 = &sc->jrxq.jdesc32[idx];
2108 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr));
2109 desc32->length = htole16(segs[0].ds_len);
2110 desc32->flags = htole16(NFE_RX_READY);
2118 nfe_rxeof(struct nfe_softc *sc, int count, int *rx_npktsp)
2120 struct ifnet *ifp = sc->nfe_ifp;
2121 struct nfe_desc32 *desc32;
2122 struct nfe_desc64 *desc64;
2123 struct nfe_rx_data *data;
2126 int len, prog, rx_npkts;
2130 NFE_LOCK_ASSERT(sc);
2132 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map,
2133 BUS_DMASYNC_POSTREAD);
2135 for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) {
2140 data = &sc->rxq.data[sc->rxq.cur];
2142 if (sc->nfe_flags & NFE_40BIT_ADDR) {
2143 desc64 = &sc->rxq.desc64[sc->rxq.cur];
2144 vtag = le32toh(desc64->physaddr[1]);
2145 flags = le16toh(desc64->flags);
2146 len = le16toh(desc64->length) & NFE_RX_LEN_MASK;
2148 desc32 = &sc->rxq.desc32[sc->rxq.cur];
2149 flags = le16toh(desc32->flags);
2150 len = le16toh(desc32->length) & NFE_RX_LEN_MASK;
2153 if (flags & NFE_RX_READY)
2156 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
2157 if (!(flags & NFE_RX_VALID_V1)) {
2159 nfe_discard_rxbuf(sc, sc->rxq.cur);
2162 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
2163 flags &= ~NFE_RX_ERROR;
2164 len--; /* fix buffer length */
2167 if (!(flags & NFE_RX_VALID_V2)) {
2169 nfe_discard_rxbuf(sc, sc->rxq.cur);
2173 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
2174 flags &= ~NFE_RX_ERROR;
2175 len--; /* fix buffer length */
2179 if (flags & NFE_RX_ERROR) {
2181 nfe_discard_rxbuf(sc, sc->rxq.cur);
2186 if (nfe_newbuf(sc, sc->rxq.cur) != 0) {
2188 nfe_discard_rxbuf(sc, sc->rxq.cur);
2192 if ((vtag & NFE_RX_VTAG) != 0 &&
2193 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
2194 m->m_pkthdr.ether_vtag = vtag & 0xffff;
2195 m->m_flags |= M_VLANTAG;
2198 m->m_pkthdr.len = m->m_len = len;
2199 m->m_pkthdr.rcvif = ifp;
2201 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
2202 if ((flags & NFE_RX_IP_CSUMOK) != 0) {
2203 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2204 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2205 if ((flags & NFE_RX_TCP_CSUMOK) != 0 ||
2206 (flags & NFE_RX_UDP_CSUMOK) != 0) {
2207 m->m_pkthdr.csum_flags |=
2208 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2209 m->m_pkthdr.csum_data = 0xffff;
2217 (*ifp->if_input)(ifp, m);
2223 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map,
2224 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2226 if (rx_npktsp != NULL)
2227 *rx_npktsp = rx_npkts;
2228 return (count > 0 ? 0 : EAGAIN);
2233 nfe_jrxeof(struct nfe_softc *sc, int count, int *rx_npktsp)
2235 struct ifnet *ifp = sc->nfe_ifp;
2236 struct nfe_desc32 *desc32;
2237 struct nfe_desc64 *desc64;
2238 struct nfe_rx_data *data;
2241 int len, prog, rx_npkts;
2245 NFE_LOCK_ASSERT(sc);
2247 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map,
2248 BUS_DMASYNC_POSTREAD);
2250 for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT),
2256 data = &sc->jrxq.jdata[sc->jrxq.jcur];
2258 if (sc->nfe_flags & NFE_40BIT_ADDR) {
2259 desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur];
2260 vtag = le32toh(desc64->physaddr[1]);
2261 flags = le16toh(desc64->flags);
2262 len = le16toh(desc64->length) & NFE_RX_LEN_MASK;
2264 desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur];
2265 flags = le16toh(desc32->flags);
2266 len = le16toh(desc32->length) & NFE_RX_LEN_MASK;
2269 if (flags & NFE_RX_READY)
2272 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
2273 if (!(flags & NFE_RX_VALID_V1)) {
2275 nfe_discard_jrxbuf(sc, sc->jrxq.jcur);
2278 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
2279 flags &= ~NFE_RX_ERROR;
2280 len--; /* fix buffer length */
2283 if (!(flags & NFE_RX_VALID_V2)) {
2285 nfe_discard_jrxbuf(sc, sc->jrxq.jcur);
2289 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
2290 flags &= ~NFE_RX_ERROR;
2291 len--; /* fix buffer length */
2295 if (flags & NFE_RX_ERROR) {
2297 nfe_discard_jrxbuf(sc, sc->jrxq.jcur);
2302 if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) {
2304 nfe_discard_jrxbuf(sc, sc->jrxq.jcur);
2308 if ((vtag & NFE_RX_VTAG) != 0 &&
2309 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
2310 m->m_pkthdr.ether_vtag = vtag & 0xffff;
2311 m->m_flags |= M_VLANTAG;
2314 m->m_pkthdr.len = m->m_len = len;
2315 m->m_pkthdr.rcvif = ifp;
2317 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
2318 if ((flags & NFE_RX_IP_CSUMOK) != 0) {
2319 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2320 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2321 if ((flags & NFE_RX_TCP_CSUMOK) != 0 ||
2322 (flags & NFE_RX_UDP_CSUMOK) != 0) {
2323 m->m_pkthdr.csum_flags |=
2324 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2325 m->m_pkthdr.csum_data = 0xffff;
2333 (*ifp->if_input)(ifp, m);
2339 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map,
2340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2342 if (rx_npktsp != NULL)
2343 *rx_npktsp = rx_npkts;
2344 return (count > 0 ? 0 : EAGAIN);
2349 nfe_txeof(struct nfe_softc *sc)
2351 struct ifnet *ifp = sc->nfe_ifp;
2352 struct nfe_desc32 *desc32;
2353 struct nfe_desc64 *desc64;
2354 struct nfe_tx_data *data = NULL;
2358 NFE_LOCK_ASSERT(sc);
2360 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map,
2361 BUS_DMASYNC_POSTREAD);
2364 for (cons = sc->txq.next; cons != sc->txq.cur;
2365 NFE_INC(cons, NFE_TX_RING_COUNT)) {
2366 if (sc->nfe_flags & NFE_40BIT_ADDR) {
2367 desc64 = &sc->txq.desc64[cons];
2368 flags = le16toh(desc64->flags);
2370 desc32 = &sc->txq.desc32[cons];
2371 flags = le16toh(desc32->flags);
2374 if (flags & NFE_TX_VALID)
2379 data = &sc->txq.data[cons];
2381 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
2382 if ((flags & NFE_TX_LASTFRAG_V1) == 0)
2384 if ((flags & NFE_TX_ERROR_V1) != 0) {
2385 device_printf(sc->nfe_dev,
2386 "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR);
2392 if ((flags & NFE_TX_LASTFRAG_V2) == 0)
2394 if ((flags & NFE_TX_ERROR_V2) != 0) {
2395 device_printf(sc->nfe_dev,
2396 "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR);
2402 /* last fragment of the mbuf chain transmitted */
2403 KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__));
2404 bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map,
2405 BUS_DMASYNC_POSTWRITE);
2406 bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map);
2412 sc->nfe_force_tx = 0;
2413 sc->txq.next = cons;
2414 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2415 if (sc->txq.queued == 0)
2416 sc->nfe_watchdog_timer = 0;
2421 nfe_encap(struct nfe_softc *sc, struct mbuf **m_head)
2423 struct nfe_desc32 *desc32 = NULL;
2424 struct nfe_desc64 *desc64 = NULL;
2426 bus_dma_segment_t segs[NFE_MAX_SCATTER];
2427 int error, i, nsegs, prod, si;
2429 uint16_t cflags, flags;
2432 prod = si = sc->txq.cur;
2433 map = sc->txq.data[prod].tx_data_map;
2435 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs,
2436 &nsegs, BUS_DMA_NOWAIT);
2437 if (error == EFBIG) {
2438 m = m_collapse(*m_head, M_NOWAIT, NFE_MAX_SCATTER);
2445 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map,
2446 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2452 } else if (error != 0)
2460 if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) {
2461 bus_dmamap_unload(sc->txq.tx_data_tag, map);
2468 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2469 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz <<
2471 cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM);
2472 cflags |= NFE_TX_TSO;
2473 } else if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) {
2474 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2475 cflags |= NFE_TX_IP_CSUM;
2476 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2477 cflags |= NFE_TX_TCP_UDP_CSUM;
2478 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2479 cflags |= NFE_TX_TCP_UDP_CSUM;
2482 for (i = 0; i < nsegs; i++) {
2483 if (sc->nfe_flags & NFE_40BIT_ADDR) {
2484 desc64 = &sc->txq.desc64[prod];
2485 desc64->physaddr[0] =
2486 htole32(NFE_ADDR_HI(segs[i].ds_addr));
2487 desc64->physaddr[1] =
2488 htole32(NFE_ADDR_LO(segs[i].ds_addr));
2490 desc64->length = htole16(segs[i].ds_len - 1);
2491 desc64->flags = htole16(flags);
2493 desc32 = &sc->txq.desc32[prod];
2495 htole32(NFE_ADDR_LO(segs[i].ds_addr));
2496 desc32->length = htole16(segs[i].ds_len - 1);
2497 desc32->flags = htole16(flags);
2501 * Setting of the valid bit in the first descriptor is
2502 * deferred until the whole chain is fully setup.
2504 flags |= NFE_TX_VALID;
2507 NFE_INC(prod, NFE_TX_RING_COUNT);
2511 * the whole mbuf chain has been DMA mapped, fix last/first descriptor.
2512 * csum flags, vtag and TSO belong to the first fragment only.
2514 if (sc->nfe_flags & NFE_40BIT_ADDR) {
2515 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
2516 desc64 = &sc->txq.desc64[si];
2517 if ((m->m_flags & M_VLANTAG) != 0)
2518 desc64->vtag = htole32(NFE_TX_VTAG |
2519 m->m_pkthdr.ether_vtag);
2520 if (tso_segsz != 0) {
2523 * The following indicates the descriptor element
2524 * is a 32bit quantity.
2526 desc64->length |= htole16((uint16_t)tso_segsz);
2527 desc64->flags |= htole16(tso_segsz >> 16);
2530 * finally, set the valid/checksum/TSO bit in the first
2533 desc64->flags |= htole16(NFE_TX_VALID | cflags);
2535 if (sc->nfe_flags & NFE_JUMBO_SUP)
2536 desc32->flags |= htole16(NFE_TX_LASTFRAG_V2);
2538 desc32->flags |= htole16(NFE_TX_LASTFRAG_V1);
2539 desc32 = &sc->txq.desc32[si];
2540 if (tso_segsz != 0) {
2543 * The following indicates the descriptor element
2544 * is a 32bit quantity.
2546 desc32->length |= htole16((uint16_t)tso_segsz);
2547 desc32->flags |= htole16(tso_segsz >> 16);
2550 * finally, set the valid/checksum/TSO bit in the first
2553 desc32->flags |= htole16(NFE_TX_VALID | cflags);
2557 prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT;
2558 sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map;
2559 sc->txq.data[prod].tx_data_map = map;
2560 sc->txq.data[prod].m = m;
2562 bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE);
2569 nfe_setmulti(struct nfe_softc *sc)
2571 struct ifnet *ifp = sc->nfe_ifp;
2572 struct ifmultiaddr *ifma;
2575 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2576 uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = {
2577 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2580 NFE_LOCK_ASSERT(sc);
2582 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2583 bzero(addr, ETHER_ADDR_LEN);
2584 bzero(mask, ETHER_ADDR_LEN);
2588 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2589 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2591 if_maddr_rlock(ifp);
2592 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2595 if (ifma->ifma_addr->sa_family != AF_LINK)
2598 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2599 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2600 u_int8_t mcaddr = addrp[i];
2605 if_maddr_runlock(ifp);
2607 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2612 addr[0] |= 0x01; /* make sure multicast bit is set */
2614 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2615 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2616 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2617 addr[5] << 8 | addr[4]);
2618 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2619 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2620 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2621 mask[5] << 8 | mask[4]);
2623 filter = NFE_READ(sc, NFE_RXFILTER);
2624 filter &= NFE_PFF_RX_PAUSE;
2625 filter |= NFE_RXFILTER_MAGIC;
2626 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M;
2627 NFE_WRITE(sc, NFE_RXFILTER, filter);
2632 nfe_start(struct ifnet *ifp)
2634 struct nfe_softc *sc = ifp->if_softc;
2637 nfe_start_locked(ifp);
2642 nfe_start_locked(struct ifnet *ifp)
2644 struct nfe_softc *sc = ifp->if_softc;
2648 NFE_LOCK_ASSERT(sc);
2650 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2651 IFF_DRV_RUNNING || sc->nfe_link == 0)
2654 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
2655 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
2659 if (nfe_encap(sc, &m0) != 0) {
2662 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
2663 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2667 ETHER_BPF_MTAP(ifp, m0);
2671 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map,
2672 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2675 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
2678 * Set a timeout in case the chip goes out to lunch.
2680 sc->nfe_watchdog_timer = 5;
2686 nfe_watchdog(struct ifnet *ifp)
2688 struct nfe_softc *sc = ifp->if_softc;
2690 if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer)
2693 /* Check if we've lost Tx completion interrupt. */
2695 if (sc->txq.queued == 0) {
2696 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
2698 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2699 nfe_start_locked(ifp);
2702 /* Check if we've lost start Tx command. */
2704 if (sc->nfe_force_tx <= 3) {
2706 * If this is the case for watchdog timeout, the following
2707 * code should go to nfe_txeof().
2709 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
2712 sc->nfe_force_tx = 0;
2714 if_printf(ifp, "watchdog timeout\n");
2716 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2718 nfe_init_locked(sc);
2725 struct nfe_softc *sc = xsc;
2728 nfe_init_locked(sc);
2734 nfe_init_locked(void *xsc)
2736 struct nfe_softc *sc = xsc;
2737 struct ifnet *ifp = sc->nfe_ifp;
2738 struct mii_data *mii;
2742 NFE_LOCK_ASSERT(sc);
2744 mii = device_get_softc(sc->nfe_miibus);
2746 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2751 sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS;
2753 nfe_init_tx_ring(sc, &sc->txq);
2754 if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN))
2755 error = nfe_init_jrx_ring(sc, &sc->jrxq);
2757 error = nfe_init_rx_ring(sc, &sc->rxq);
2759 device_printf(sc->nfe_dev,
2760 "initialization failed: no memory for rx buffers\n");
2766 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0)
2767 val |= NFE_MAC_ADDR_INORDER;
2768 NFE_WRITE(sc, NFE_TX_UNK, val);
2769 NFE_WRITE(sc, NFE_STATUS, 0);
2771 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0)
2772 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE);
2774 sc->rxtxctl = NFE_RXTX_BIT2;
2775 if (sc->nfe_flags & NFE_40BIT_ADDR)
2776 sc->rxtxctl |= NFE_RXTX_V3MAGIC;
2777 else if (sc->nfe_flags & NFE_JUMBO_SUP)
2778 sc->rxtxctl |= NFE_RXTX_V2MAGIC;
2780 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2781 sc->rxtxctl |= NFE_RXTX_RXCSUM;
2782 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2783 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP;
2785 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
2787 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
2789 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2790 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
2792 NFE_WRITE(sc, NFE_VTAG_CTL, 0);
2794 NFE_WRITE(sc, NFE_SETUP_R6, 0);
2796 /* set MAC address */
2797 nfe_set_macaddr(sc, IF_LLADDR(ifp));
2799 /* tell MAC where rings are in memory */
2800 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) {
2801 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
2802 NFE_ADDR_HI(sc->jrxq.jphysaddr));
2803 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO,
2804 NFE_ADDR_LO(sc->jrxq.jphysaddr));
2806 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
2807 NFE_ADDR_HI(sc->rxq.physaddr));
2808 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO,
2809 NFE_ADDR_LO(sc->rxq.physaddr));
2811 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr));
2812 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr));
2814 NFE_WRITE(sc, NFE_RING_SIZE,
2815 (NFE_RX_RING_COUNT - 1) << 16 |
2816 (NFE_TX_RING_COUNT - 1));
2818 NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize);
2820 /* force MAC to wakeup */
2821 val = NFE_READ(sc, NFE_PWR_STATE);
2822 if ((val & NFE_PWR_WAKEUP) == 0)
2823 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP);
2825 val = NFE_READ(sc, NFE_PWR_STATE);
2826 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID);
2829 /* configure interrupts coalescing/mitigation */
2830 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT);
2832 /* no interrupt mitigation: one interrupt per packet */
2833 NFE_WRITE(sc, NFE_IMTIMER, 970);
2836 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100);
2837 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
2838 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
2840 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
2841 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
2843 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
2845 NFE_WRITE(sc, NFE_WOL_CTL, 0);
2847 sc->rxtxctl &= ~NFE_RXTX_BIT2;
2848 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
2850 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
2856 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
2859 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
2861 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
2863 /* Clear hardware stats. */
2864 nfe_stats_clear(sc);
2866 #ifdef DEVICE_POLLING
2867 if (ifp->if_capenable & IFCAP_POLLING)
2868 nfe_disable_intr(sc);
2872 nfe_enable_intr(sc); /* enable interrupts */
2874 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2875 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2880 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc);
2885 nfe_stop(struct ifnet *ifp)
2887 struct nfe_softc *sc = ifp->if_softc;
2888 struct nfe_rx_ring *rx_ring;
2889 struct nfe_jrx_ring *jrx_ring;
2890 struct nfe_tx_ring *tx_ring;
2891 struct nfe_rx_data *rdata;
2892 struct nfe_tx_data *tdata;
2895 NFE_LOCK_ASSERT(sc);
2897 sc->nfe_watchdog_timer = 0;
2898 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2900 callout_stop(&sc->nfe_stat_ch);
2903 NFE_WRITE(sc, NFE_TX_CTL, 0);
2906 NFE_WRITE(sc, NFE_RX_CTL, 0);
2908 /* disable interrupts */
2909 nfe_disable_intr(sc);
2913 /* free Rx and Tx mbufs still in the queues. */
2915 for (i = 0; i < NFE_RX_RING_COUNT; i++) {
2916 rdata = &rx_ring->data[i];
2917 if (rdata->m != NULL) {
2918 bus_dmamap_sync(rx_ring->rx_data_tag,
2919 rdata->rx_data_map, BUS_DMASYNC_POSTREAD);
2920 bus_dmamap_unload(rx_ring->rx_data_tag,
2921 rdata->rx_data_map);
2927 if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) {
2928 jrx_ring = &sc->jrxq;
2929 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) {
2930 rdata = &jrx_ring->jdata[i];
2931 if (rdata->m != NULL) {
2932 bus_dmamap_sync(jrx_ring->jrx_data_tag,
2933 rdata->rx_data_map, BUS_DMASYNC_POSTREAD);
2934 bus_dmamap_unload(jrx_ring->jrx_data_tag,
2935 rdata->rx_data_map);
2943 for (i = 0; i < NFE_RX_RING_COUNT; i++) {
2944 tdata = &tx_ring->data[i];
2945 if (tdata->m != NULL) {
2946 bus_dmamap_sync(tx_ring->tx_data_tag,
2947 tdata->tx_data_map, BUS_DMASYNC_POSTWRITE);
2948 bus_dmamap_unload(tx_ring->tx_data_tag,
2949 tdata->tx_data_map);
2954 /* Update hardware stats. */
2955 nfe_stats_update(sc);
2960 nfe_ifmedia_upd(struct ifnet *ifp)
2962 struct nfe_softc *sc = ifp->if_softc;
2963 struct mii_data *mii;
2966 mii = device_get_softc(sc->nfe_miibus);
2975 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2977 struct nfe_softc *sc;
2978 struct mii_data *mii;
2983 mii = device_get_softc(sc->nfe_miibus);
2986 ifmr->ifm_active = mii->mii_media_active;
2987 ifmr->ifm_status = mii->mii_media_status;
2995 struct nfe_softc *sc;
2996 struct mii_data *mii;
2999 sc = (struct nfe_softc *)xsc;
3001 NFE_LOCK_ASSERT(sc);
3005 mii = device_get_softc(sc->nfe_miibus);
3007 nfe_stats_update(sc);
3009 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc);
3014 nfe_shutdown(device_t dev)
3017 return (nfe_suspend(dev));
3022 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
3026 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) {
3027 val = NFE_READ(sc, NFE_MACADDR_LO);
3028 addr[0] = (val >> 8) & 0xff;
3029 addr[1] = (val & 0xff);
3031 val = NFE_READ(sc, NFE_MACADDR_HI);
3032 addr[2] = (val >> 24) & 0xff;
3033 addr[3] = (val >> 16) & 0xff;
3034 addr[4] = (val >> 8) & 0xff;
3035 addr[5] = (val & 0xff);
3037 val = NFE_READ(sc, NFE_MACADDR_LO);
3038 addr[5] = (val >> 8) & 0xff;
3039 addr[4] = (val & 0xff);
3041 val = NFE_READ(sc, NFE_MACADDR_HI);
3042 addr[3] = (val >> 24) & 0xff;
3043 addr[2] = (val >> 16) & 0xff;
3044 addr[1] = (val >> 8) & 0xff;
3045 addr[0] = (val & 0xff);
3051 nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr)
3054 NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]);
3055 NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 |
3056 addr[1] << 8 | addr[0]);
3061 * Map a single buffer address.
3065 nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3067 struct nfe_dmamap_arg *ctx;
3072 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
3074 ctx = (struct nfe_dmamap_arg *)arg;
3075 ctx->nfe_busaddr = segs[0].ds_addr;
3080 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3086 value = *(int *)arg1;
3087 error = sysctl_handle_int(oidp, &value, 0, req);
3088 if (error || !req->newptr)
3090 if (value < low || value > high)
3092 *(int *)arg1 = value;
3099 sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS)
3102 return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN,
3107 #define NFE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
3108 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3109 #define NFE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
3110 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
3113 nfe_sysctl_node(struct nfe_softc *sc)
3115 struct sysctl_ctx_list *ctx;
3116 struct sysctl_oid_list *child, *parent;
3117 struct sysctl_oid *tree;
3118 struct nfe_hw_stats *stats;
3121 stats = &sc->nfe_stats;
3122 ctx = device_get_sysctl_ctx(sc->nfe_dev);
3123 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nfe_dev));
3124 SYSCTL_ADD_PROC(ctx, child,
3125 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
3126 &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I",
3127 "max number of Rx events to process");
3129 sc->nfe_process_limit = NFE_PROC_DEFAULT;
3130 error = resource_int_value(device_get_name(sc->nfe_dev),
3131 device_get_unit(sc->nfe_dev), "process_limit",
3132 &sc->nfe_process_limit);
3134 if (sc->nfe_process_limit < NFE_PROC_MIN ||
3135 sc->nfe_process_limit > NFE_PROC_MAX) {
3136 device_printf(sc->nfe_dev,
3137 "process_limit value out of range; "
3138 "using default: %d\n", NFE_PROC_DEFAULT);
3139 sc->nfe_process_limit = NFE_PROC_DEFAULT;
3143 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0)
3146 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3147 NULL, "NFE statistics");
3148 parent = SYSCTL_CHILDREN(tree);
3150 /* Rx statistics. */
3151 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3152 NULL, "Rx MAC statistics");
3153 child = SYSCTL_CHILDREN(tree);
3155 NFE_SYSCTL_STAT_ADD32(ctx, child, "frame_errors",
3156 &stats->rx_frame_errors, "Framing Errors");
3157 NFE_SYSCTL_STAT_ADD32(ctx, child, "extra_bytes",
3158 &stats->rx_extra_bytes, "Extra Bytes");
3159 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols",
3160 &stats->rx_late_cols, "Late Collisions");
3161 NFE_SYSCTL_STAT_ADD32(ctx, child, "runts",
3162 &stats->rx_runts, "Runts");
3163 NFE_SYSCTL_STAT_ADD32(ctx, child, "jumbos",
3164 &stats->rx_jumbos, "Jumbos");
3165 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_overuns",
3166 &stats->rx_fifo_overuns, "FIFO Overruns");
3167 NFE_SYSCTL_STAT_ADD32(ctx, child, "crc_errors",
3168 &stats->rx_crc_errors, "CRC Errors");
3169 NFE_SYSCTL_STAT_ADD32(ctx, child, "fae",
3170 &stats->rx_fae, "Frame Alignment Errors");
3171 NFE_SYSCTL_STAT_ADD32(ctx, child, "len_errors",
3172 &stats->rx_len_errors, "Length Errors");
3173 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast",
3174 &stats->rx_unicast, "Unicast Frames");
3175 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast",
3176 &stats->rx_multicast, "Multicast Frames");
3177 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast",
3178 &stats->rx_broadcast, "Broadcast Frames");
3179 if ((sc->nfe_flags & NFE_MIB_V2) != 0) {
3180 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets",
3181 &stats->rx_octets, "Octets");
3182 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause",
3183 &stats->rx_pause, "Pause frames");
3184 NFE_SYSCTL_STAT_ADD32(ctx, child, "drops",
3185 &stats->rx_drops, "Drop frames");
3188 /* Tx statistics. */
3189 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3190 NULL, "Tx MAC statistics");
3191 child = SYSCTL_CHILDREN(tree);
3192 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets",
3193 &stats->tx_octets, "Octets");
3194 NFE_SYSCTL_STAT_ADD32(ctx, child, "zero_rexmits",
3195 &stats->tx_zero_rexmits, "Zero Retransmits");
3196 NFE_SYSCTL_STAT_ADD32(ctx, child, "one_rexmits",
3197 &stats->tx_one_rexmits, "One Retransmits");
3198 NFE_SYSCTL_STAT_ADD32(ctx, child, "multi_rexmits",
3199 &stats->tx_multi_rexmits, "Multiple Retransmits");
3200 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols",
3201 &stats->tx_late_cols, "Late Collisions");
3202 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_underuns",
3203 &stats->tx_fifo_underuns, "FIFO Underruns");
3204 NFE_SYSCTL_STAT_ADD32(ctx, child, "carrier_losts",
3205 &stats->tx_carrier_losts, "Carrier Losts");
3206 NFE_SYSCTL_STAT_ADD32(ctx, child, "excess_deferrals",
3207 &stats->tx_excess_deferals, "Excess Deferrals");
3208 NFE_SYSCTL_STAT_ADD32(ctx, child, "retry_errors",
3209 &stats->tx_retry_errors, "Retry Errors");
3210 if ((sc->nfe_flags & NFE_MIB_V2) != 0) {
3211 NFE_SYSCTL_STAT_ADD32(ctx, child, "deferrals",
3212 &stats->tx_deferals, "Deferrals");
3213 NFE_SYSCTL_STAT_ADD32(ctx, child, "frames",
3214 &stats->tx_frames, "Frames");
3215 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause",
3216 &stats->tx_pause, "Pause Frames");
3218 if ((sc->nfe_flags & NFE_MIB_V3) != 0) {
3219 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast",
3220 &stats->tx_deferals, "Unicast Frames");
3221 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast",
3222 &stats->tx_frames, "Multicast Frames");
3223 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast",
3224 &stats->tx_pause, "Broadcast Frames");
3228 #undef NFE_SYSCTL_STAT_ADD32
3229 #undef NFE_SYSCTL_STAT_ADD64
3232 nfe_stats_clear(struct nfe_softc *sc)
3236 if ((sc->nfe_flags & NFE_MIB_V1) != 0)
3237 mib_cnt = NFE_NUM_MIB_STATV1;
3238 else if ((sc->nfe_flags & (NFE_MIB_V2 | NFE_MIB_V3)) != 0)
3239 mib_cnt = NFE_NUM_MIB_STATV2;
3243 for (i = 0; i < mib_cnt; i++)
3244 NFE_READ(sc, NFE_TX_OCTET + i * sizeof(uint32_t));
3246 if ((sc->nfe_flags & NFE_MIB_V3) != 0) {
3247 NFE_READ(sc, NFE_TX_UNICAST);
3248 NFE_READ(sc, NFE_TX_MULTICAST);
3249 NFE_READ(sc, NFE_TX_BROADCAST);
3254 nfe_stats_update(struct nfe_softc *sc)
3256 struct nfe_hw_stats *stats;
3258 NFE_LOCK_ASSERT(sc);
3260 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0)
3263 stats = &sc->nfe_stats;
3264 stats->tx_octets += NFE_READ(sc, NFE_TX_OCTET);
3265 stats->tx_zero_rexmits += NFE_READ(sc, NFE_TX_ZERO_REXMIT);
3266 stats->tx_one_rexmits += NFE_READ(sc, NFE_TX_ONE_REXMIT);
3267 stats->tx_multi_rexmits += NFE_READ(sc, NFE_TX_MULTI_REXMIT);
3268 stats->tx_late_cols += NFE_READ(sc, NFE_TX_LATE_COL);
3269 stats->tx_fifo_underuns += NFE_READ(sc, NFE_TX_FIFO_UNDERUN);
3270 stats->tx_carrier_losts += NFE_READ(sc, NFE_TX_CARRIER_LOST);
3271 stats->tx_excess_deferals += NFE_READ(sc, NFE_TX_EXCESS_DEFERRAL);
3272 stats->tx_retry_errors += NFE_READ(sc, NFE_TX_RETRY_ERROR);
3273 stats->rx_frame_errors += NFE_READ(sc, NFE_RX_FRAME_ERROR);
3274 stats->rx_extra_bytes += NFE_READ(sc, NFE_RX_EXTRA_BYTES);
3275 stats->rx_late_cols += NFE_READ(sc, NFE_RX_LATE_COL);
3276 stats->rx_runts += NFE_READ(sc, NFE_RX_RUNT);
3277 stats->rx_jumbos += NFE_READ(sc, NFE_RX_JUMBO);
3278 stats->rx_fifo_overuns += NFE_READ(sc, NFE_RX_FIFO_OVERUN);
3279 stats->rx_crc_errors += NFE_READ(sc, NFE_RX_CRC_ERROR);
3280 stats->rx_fae += NFE_READ(sc, NFE_RX_FAE);
3281 stats->rx_len_errors += NFE_READ(sc, NFE_RX_LEN_ERROR);
3282 stats->rx_unicast += NFE_READ(sc, NFE_RX_UNICAST);
3283 stats->rx_multicast += NFE_READ(sc, NFE_RX_MULTICAST);
3284 stats->rx_broadcast += NFE_READ(sc, NFE_RX_BROADCAST);
3286 if ((sc->nfe_flags & NFE_MIB_V2) != 0) {
3287 stats->tx_deferals += NFE_READ(sc, NFE_TX_DEFERAL);
3288 stats->tx_frames += NFE_READ(sc, NFE_TX_FRAME);
3289 stats->rx_octets += NFE_READ(sc, NFE_RX_OCTET);
3290 stats->tx_pause += NFE_READ(sc, NFE_TX_PAUSE);
3291 stats->rx_pause += NFE_READ(sc, NFE_RX_PAUSE);
3292 stats->rx_drops += NFE_READ(sc, NFE_RX_DROP);
3295 if ((sc->nfe_flags & NFE_MIB_V3) != 0) {
3296 stats->tx_unicast += NFE_READ(sc, NFE_TX_UNICAST);
3297 stats->tx_multicast += NFE_READ(sc, NFE_TX_MULTICAST);
3298 stats->tx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST);
3304 nfe_set_linkspeed(struct nfe_softc *sc)
3306 struct mii_softc *miisc;
3307 struct mii_data *mii;
3310 NFE_LOCK_ASSERT(sc);
3312 mii = device_get_softc(sc->nfe_miibus);
3315 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3316 (IFM_ACTIVE | IFM_AVALID)) {
3317 switch IFM_SUBTYPE(mii->mii_media_active) {
3328 miisc = LIST_FIRST(&mii->mii_phys);
3329 phyno = miisc->mii_phy;
3330 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3332 nfe_miibus_writereg(sc->nfe_dev, phyno, MII_100T2CR, 0);
3333 nfe_miibus_writereg(sc->nfe_dev, phyno,
3334 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3335 nfe_miibus_writereg(sc->nfe_dev, phyno,
3336 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
3340 * Poll link state until nfe(4) get a 10/100Mbps link.
3342 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3344 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3345 == (IFM_ACTIVE | IFM_AVALID)) {
3346 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3349 nfe_mac_config(sc, mii);
3356 pause("nfelnk", hz);
3359 if (i == MII_ANEGTICKS_GIGE)
3360 device_printf(sc->nfe_dev,
3361 "establishing a link failed, WOL may not work!");
3364 * No link, force MAC to have 100Mbps, full-duplex link.
3365 * This is the last resort and may/may not work.
3367 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3368 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3369 nfe_mac_config(sc, mii);
3374 nfe_set_wol(struct nfe_softc *sc)
3381 NFE_LOCK_ASSERT(sc);
3383 if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0)
3386 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3387 wolctl = NFE_WOL_MAGIC;
3390 NFE_WRITE(sc, NFE_WOL_CTL, wolctl);
3391 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
3392 nfe_set_linkspeed(sc);
3393 if ((sc->nfe_flags & NFE_PWR_MGMT) != 0)
3394 NFE_WRITE(sc, NFE_PWR2_CTL,
3395 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_GATE_CLOCKS);
3397 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0);
3398 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0);
3399 NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) |
3402 /* Request PME if WOL is requested. */
3403 pmstat = pci_read_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, 2);
3404 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3405 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3406 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3407 pci_write_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);