sys/dev/oce/oce_if.h

   1 /*-
   2  * Copyright (C) 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  *
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * 3. Neither the name of the Emulex Corporation nor the names of its
  16  *    contributors may be used to endorse or promote products derived from
  17  *    this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * Contact Information:
  32  * freebsd-drivers@emulex.com
  33  *
  34  * Emulex
  35  * 3333 Susan Street
  36  * Costa Mesa, CA 92626
  37  */
  38
  39 /* $FreeBSD$ */
  40
  41 #include <sys/param.h>
  42 #include <sys/endian.h>
  43 #include <sys/module.h>
  44 #include <sys/kernel.h>
  45 #include <sys/bus.h>
  46 #include <sys/mbuf.h>
  47 #include <sys/rman.h>
  48 #include <sys/socket.h>
  49 #include <sys/sockio.h>
  50 #include <sys/sockopt.h>
  51 #include <sys/queue.h>
  52 #include <sys/taskqueue.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/sysctl.h>
  56 #include <sys/random.h>
  57 #include <sys/firmware.h>
  58 #include <sys/systm.h>
  59 #include <sys/proc.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include <net/bpf.h>
  65 #include <net/ethernet.h>
  66 #include <net/if.h>
  67 #include <net/if_types.h>
  68 #include <net/if_media.h>
  69 #include <net/if_vlan_var.h>
  70 #include <net/if_dl.h>
  71
  72 #include <netinet/in.h>
  73 #include <netinet/in_systm.h>
  74 #include <netinet/in_var.h>
  75 #include <netinet/if_ether.h>
  76 #include <netinet/ip.h>
  77 #include <netinet/ip6.h>
  78 #include <netinet6/in6_var.h>
  79 #include <netinet6/ip6_mroute.h>
  80
  81 #include <netinet/udp.h>
  82 #include <netinet/tcp.h>
  83 #include <netinet/sctp.h>
  84 #include <netinet/tcp_lro.h>
  85
  86 #include <machine/bus.h>
  87
  88 #include "oce_hw.h"
  89
  90 /* OCE device driver module component revision informaiton */
  91 #define COMPONENT_REVISION "10.0.664.0"
  92
  93 /* OCE devices supported by this driver */
  94 #define PCI_VENDOR_EMULEX               0x10df  /* Emulex */
  95 #define PCI_VENDOR_SERVERENGINES        0x19a2  /* ServerEngines (BE) */
  96 #define PCI_PRODUCT_BE2                 0x0700  /* BE2 network adapter */
  97 #define PCI_PRODUCT_BE3                 0x0710  /* BE3 network adapter */
  98 #define PCI_PRODUCT_XE201               0xe220  /* XE201 network adapter */
  99 #define PCI_PRODUCT_XE201_VF            0xe228  /* XE201 with VF in Lancer */
 100 #define PCI_PRODUCT_SH                  0x0720  /* Skyhawk network adapter */
 101
 102 #define IS_BE(sc)       (((sc->flags & OCE_FLAGS_BE3) | \
 103                          (sc->flags & OCE_FLAGS_BE2))? 1:0)
 104 #define IS_BE3(sc)      (sc->flags & OCE_FLAGS_BE3)
 105 #define IS_BE2(sc)      (sc->flags & OCE_FLAGS_BE2)
 106 #define IS_XE201(sc)    ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
 107 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
 108 #define IS_SH(sc)       ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
 109
 110 #define is_be_mode_mc(sc)       ((sc->function_mode & FNM_FLEX10_MODE) ||       \
 111                                 (sc->function_mode & FNM_UMC_MODE)    ||        \
 112                                 (sc->function_mode & FNM_VNIC_MODE))
 113 #define OCE_FUNCTION_CAPS_SUPER_NIC     0x40
 114 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
 115
 116
 117 /* proportion Service Level Interface queues */
 118 #define OCE_MAX_UNITS                   2
 119 #define OCE_MAX_PPORT                   OCE_MAX_UNITS
 120 #define OCE_MAX_VPORT                   OCE_MAX_UNITS
 121
 122 extern int mp_ncpus;                    /* system's total active cpu cores */
 123 #define OCE_NCPUS                       mp_ncpus
 124
 125 /* This should be powers of 2. Like 2,4,8 & 16 */
 126 #define OCE_MAX_RSS                     8
 127 #define OCE_LEGACY_MODE_RSS             4 /* For BE3 Legacy mode*/
 128 #define is_rss_enabled(sc)              ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
 129
 130 #define OCE_MIN_RQ                      1
 131 #define OCE_MIN_WQ                      1
 132
 133 #define OCE_MAX_RQ                      OCE_MAX_RSS + 1 /* one default queue */
 134 #define OCE_MAX_WQ                      8
 135
 136 #define OCE_MAX_EQ                      32
 137 #define OCE_MAX_CQ                      OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
 138 #define OCE_MAX_CQ_EQ                   8 /* Max CQ that can attached to an EQ */
 139
 140 #define OCE_DEFAULT_WQ_EQD              16
 141 #define OCE_MAX_PACKET_Q                16
 142 #define OCE_RQ_BUF_SIZE                 2048
 143 #define OCE_LSO_MAX_SIZE                (64 * 1024)
 144 #define LONG_TIMEOUT                    30
 145 #define OCE_MAX_JUMBO_FRAME_SIZE        9018
 146 #define OCE_MAX_MTU                     (OCE_MAX_JUMBO_FRAME_SIZE - \
 147                                                 ETHER_VLAN_ENCAP_LEN - \
 148                                                 ETHER_HDR_LEN)
 149
 150 #define OCE_MAX_TX_ELEMENTS             29
 151 #define OCE_MAX_TX_DESC                 1024
 152 #define OCE_MAX_TX_SIZE                 65535
 153 #define OCE_MAX_TSO_SIZE                (65535 - ETHER_HDR_LEN)
 154 #define OCE_MAX_RX_SIZE                 4096
 155 #define OCE_MAX_RQ_POSTS                255
 156 #define OCE_DEFAULT_PROMISCUOUS         0
 157
 158
 159 #define RSS_ENABLE_IPV4                 0x1
 160 #define RSS_ENABLE_TCP_IPV4             0x2
 161 #define RSS_ENABLE_IPV6                 0x4
 162 #define RSS_ENABLE_TCP_IPV6             0x8
 163
 164 #define INDIRECTION_TABLE_ENTRIES       128
 165
 166 /* flow control definitions */
 167 #define OCE_FC_NONE                     0x00000000
 168 #define OCE_FC_TX                       0x00000001
 169 #define OCE_FC_RX                       0x00000002
 170 #define OCE_DEFAULT_FLOW_CONTROL        (OCE_FC_TX | OCE_FC_RX)
 171
 172
 173 /* Interface capabilities to give device when creating interface */
 174 #define  OCE_CAPAB_FLAGS                (MBX_RX_IFACE_FLAGS_BROADCAST    | \
 175                                         MBX_RX_IFACE_FLAGS_UNTAGGED      | \
 176                                         MBX_RX_IFACE_FLAGS_PROMISCUOUS      | \
 177                                         MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS |   \
 178                                         MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS   | \
 179                                         MBX_RX_IFACE_FLAGS_RSS | \
 180                                         MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
 181
 182 /* Interface capabilities to enable by default (others set dynamically) */
 183 #define  OCE_CAPAB_ENABLE               (MBX_RX_IFACE_FLAGS_BROADCAST | \
 184                                         MBX_RX_IFACE_FLAGS_UNTAGGED   | \
 185                                         MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
 186
 187 #define OCE_IF_HWASSIST                 (CSUM_IP | CSUM_TCP | CSUM_UDP)
 188 #define OCE_IF_CAPABILITIES             (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
 189                                         IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
 190                                         IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
 191 #define OCE_IF_HWASSIST_NONE            0
 192 #define OCE_IF_CAPABILITIES_NONE        0
 193
 194
 195 #define ETH_ADDR_LEN                    6
 196 #define MAX_VLANFILTER_SIZE             64
 197 #define MAX_VLANS                       4096
 198
 199 #define upper_32_bits(n)                ((uint32_t)(((n) >> 16) >> 16))
 200 #define BSWAP_8(x)                      ((x) & 0xff)
 201 #define BSWAP_16(x)                     ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
 202 #define BSWAP_32(x)                     ((BSWAP_16(x) << 16) | \
 203                                          BSWAP_16((x) >> 16))
 204 #define BSWAP_64(x)                     ((BSWAP_32(x) << 32) | \
 205                                         BSWAP_32((x) >> 32))
 206
 207 #define for_all_wq_queues(sc, wq, i)    \
 208                 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
 209 #define for_all_rq_queues(sc, rq, i)    \
 210                 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
 211 #define for_all_rss_queues(sc, rq, i)   \
 212                 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
 213                      i++, rq = sc->rq[i + 1])
 214 #define for_all_evnt_queues(sc, eq, i)  \
 215                 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
 216 #define for_all_cq_queues(sc, cq, i)    \
 217                 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
 218
 219
 220 /* Flash specific */
 221 #define IOCTL_COOKIE                    "SERVERENGINES CORP"
 222 #define MAX_FLASH_COMP                  32
 223
 224 #define IMG_ISCSI                       160
 225 #define IMG_REDBOOT                     224
 226 #define IMG_BIOS                        34
 227 #define IMG_PXEBIOS                     32
 228 #define IMG_FCOEBIOS                    33
 229 #define IMG_ISCSI_BAK                   176
 230 #define IMG_FCOE                        162
 231 #define IMG_FCOE_BAK                    178
 232 #define IMG_NCSI                        16
 233 #define IMG_PHY                         192
 234 #define FLASHROM_OPER_FLASH             1
 235 #define FLASHROM_OPER_SAVE              2
 236 #define FLASHROM_OPER_REPORT            4
 237 #define FLASHROM_OPER_FLASH_PHY         9
 238 #define FLASHROM_OPER_SAVE_PHY          10
 239 #define TN_8022                         13
 240
 241 enum {
 242         PHY_TYPE_CX4_10GB = 0,
 243         PHY_TYPE_XFP_10GB,
 244         PHY_TYPE_SFP_1GB,
 245         PHY_TYPE_SFP_PLUS_10GB,
 246         PHY_TYPE_KR_10GB,
 247         PHY_TYPE_KX4_10GB,
 248         PHY_TYPE_BASET_10GB,
 249         PHY_TYPE_BASET_1GB,
 250         PHY_TYPE_BASEX_1GB,
 251         PHY_TYPE_SGMII,
 252         PHY_TYPE_DISABLED = 255
 253 };
 254
 255 /**
 256  * @brief Define and hold all necessary info for a single interrupt
 257  */
 258 #define OCE_MAX_MSI                     32 /* Message Signaled Interrupts */
 259 #define OCE_MAX_MSIX                    2048 /* PCI Express MSI Interrrupts */
 260
 261 typedef struct oce_intr_info {
 262         void *tag;              /* cookie returned by bus_setup_intr */
 263         struct resource *intr_res;      /* PCI resource container */
 264         int irq_rr;             /* resource id for the interrupt */
 265         struct oce_softc *sc;   /* pointer to the parent soft c */
 266         struct oce_eq *eq;      /* pointer to the connected EQ */
 267         struct taskqueue *tq;   /* Associated task queue */
 268         struct task task;       /* task queue task */
 269         char task_name[32];     /* task name */
 270         int vector;             /* interrupt vector number */
 271 } OCE_INTR_INFO, *POCE_INTR_INFO;
 272
 273
 274 /* Ring related */
 275 #define GET_Q_NEXT(_START, _STEP, _END) \
 276         (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
 277         : (((_START) + (_STEP)) - (_END)))
 278
 279 #define DBUF_PA(obj)                    ((obj)->addr)
 280 #define DBUF_VA(obj)                    ((obj)->ptr)
 281 #define DBUF_TAG(obj)                   ((obj)->tag)
 282 #define DBUF_MAP(obj)                   ((obj)->map)
 283 #define DBUF_SYNC(obj, flags)           \
 284                 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
 285
 286 #define RING_NUM_PENDING(ring)          ring->num_used
 287 #define RING_FULL(ring)                 (ring->num_used == ring->num_items)
 288 #define RING_EMPTY(ring)                (ring->num_used == 0)
 289 #define RING_NUM_FREE(ring)             \
 290                 (uint32_t)(ring->num_items - ring->num_used)
 291 #define RING_GET(ring, n)               \
 292                 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
 293 #define RING_PUT(ring, n)               \
 294                 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
 295
 296 #define RING_GET_CONSUMER_ITEM_VA(ring, type)   \
 297         (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
 298 #define RING_GET_CONSUMER_ITEM_PA(ring, type)           \
 299         (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
 300 #define RING_GET_PRODUCER_ITEM_VA(ring, type)           \
 301         (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
 302 #define RING_GET_PRODUCER_ITEM_PA(ring, type)           \
 303         (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
 304
 305 #define OCE_DMAPTR(o, c)                ((c *)(o)->ptr)
 306
 307 struct oce_packet_desc {
 308         struct mbuf *mbuf;
 309         bus_dmamap_t map;
 310         int nsegs;
 311         uint32_t wqe_idx;
 312 };
 313
 314 typedef struct oce_dma_mem {
 315         bus_dma_tag_t tag;
 316         bus_dmamap_t map;
 317         void *ptr;
 318         bus_addr_t paddr;
 319 } OCE_DMA_MEM, *POCE_DMA_MEM;
 320
 321 typedef struct oce_ring_buffer_s {
 322         uint16_t cidx;  /* Get ptr */
 323         uint16_t pidx;  /* Put Ptr */
 324         size_t item_size;
 325         size_t num_items;
 326         uint32_t num_used;
 327         OCE_DMA_MEM dma;
 328 } oce_ring_buffer_t;
 329
 330 /* Stats */
 331 #define OCE_UNICAST_PACKET      0
 332 #define OCE_MULTICAST_PACKET    1
 333 #define OCE_BROADCAST_PACKET    2
 334 #define OCE_RSVD_PACKET         3
 335
 336 struct oce_rx_stats {
 337         /* Total Receive Stats*/
 338         uint64_t t_rx_pkts;
 339         uint64_t t_rx_bytes;
 340         uint32_t t_rx_frags;
 341         uint32_t t_rx_mcast_pkts;
 342         uint32_t t_rx_ucast_pkts;
 343         uint32_t t_rxcp_errs;
 344 };
 345 struct oce_tx_stats {
 346         /*Total Transmit Stats */
 347         uint64_t t_tx_pkts;
 348         uint64_t t_tx_bytes;
 349         uint32_t t_tx_reqs;
 350         uint32_t t_tx_stops;
 351         uint32_t t_tx_wrbs;
 352         uint32_t t_tx_compl;
 353         uint32_t t_ipv6_ext_hdr_tx_drop;
 354 };
 355
 356 struct oce_be_stats {
 357         uint8_t  be_on_die_temperature;
 358         uint32_t be_tx_events;
 359         uint32_t eth_red_drops;
 360         uint32_t rx_drops_no_pbuf;
 361         uint32_t rx_drops_no_txpb;
 362         uint32_t rx_drops_no_erx_descr;
 363         uint32_t rx_drops_no_tpre_descr;
 364         uint32_t rx_drops_too_many_frags;
 365         uint32_t rx_drops_invalid_ring;
 366         uint32_t forwarded_packets;
 367         uint32_t rx_drops_mtu;
 368         uint32_t rx_crc_errors;
 369         uint32_t rx_alignment_symbol_errors;
 370         uint32_t rx_pause_frames;
 371         uint32_t rx_priority_pause_frames;
 372         uint32_t rx_control_frames;
 373         uint32_t rx_in_range_errors;
 374         uint32_t rx_out_range_errors;
 375         uint32_t rx_frame_too_long;
 376         uint32_t rx_address_match_errors;
 377         uint32_t rx_dropped_too_small;
 378         uint32_t rx_dropped_too_short;
 379         uint32_t rx_dropped_header_too_small;
 380         uint32_t rx_dropped_tcp_length;
 381         uint32_t rx_dropped_runt;
 382         uint32_t rx_ip_checksum_errs;
 383         uint32_t rx_tcp_checksum_errs;
 384         uint32_t rx_udp_checksum_errs;
 385         uint32_t rx_switched_unicast_packets;
 386         uint32_t rx_switched_multicast_packets;
 387         uint32_t rx_switched_broadcast_packets;
 388         uint32_t tx_pauseframes;
 389         uint32_t tx_priority_pauseframes;
 390         uint32_t tx_controlframes;
 391         uint32_t rxpp_fifo_overflow_drop;
 392         uint32_t rx_input_fifo_overflow_drop;
 393         uint32_t pmem_fifo_overflow_drop;
 394         uint32_t jabber_events;
 395 };
 396
 397 struct oce_xe201_stats {
 398         uint64_t tx_pkts;
 399         uint64_t tx_unicast_pkts;
 400         uint64_t tx_multicast_pkts;
 401         uint64_t tx_broadcast_pkts;
 402         uint64_t tx_bytes;
 403         uint64_t tx_unicast_bytes;
 404         uint64_t tx_multicast_bytes;
 405         uint64_t tx_broadcast_bytes;
 406         uint64_t tx_discards;
 407         uint64_t tx_errors;
 408         uint64_t tx_pause_frames;
 409         uint64_t tx_pause_on_frames;
 410         uint64_t tx_pause_off_frames;
 411         uint64_t tx_internal_mac_errors;
 412         uint64_t tx_control_frames;
 413         uint64_t tx_pkts_64_bytes;
 414         uint64_t tx_pkts_65_to_127_bytes;
 415         uint64_t tx_pkts_128_to_255_bytes;
 416         uint64_t tx_pkts_256_to_511_bytes;
 417         uint64_t tx_pkts_512_to_1023_bytes;
 418         uint64_t tx_pkts_1024_to_1518_bytes;
 419         uint64_t tx_pkts_1519_to_2047_bytes;
 420         uint64_t tx_pkts_2048_to_4095_bytes;
 421         uint64_t tx_pkts_4096_to_8191_bytes;
 422         uint64_t tx_pkts_8192_to_9216_bytes;
 423         uint64_t tx_lso_pkts;
 424         uint64_t rx_pkts;
 425         uint64_t rx_unicast_pkts;
 426         uint64_t rx_multicast_pkts;
 427         uint64_t rx_broadcast_pkts;
 428         uint64_t rx_bytes;
 429         uint64_t rx_unicast_bytes;
 430         uint64_t rx_multicast_bytes;
 431         uint64_t rx_broadcast_bytes;
 432         uint32_t rx_unknown_protos;
 433         uint64_t rx_discards;
 434         uint64_t rx_errors;
 435         uint64_t rx_crc_errors;
 436         uint64_t rx_alignment_errors;
 437         uint64_t rx_symbol_errors;
 438         uint64_t rx_pause_frames;
 439         uint64_t rx_pause_on_frames;
 440         uint64_t rx_pause_off_frames;
 441         uint64_t rx_frames_too_long;
 442         uint64_t rx_internal_mac_errors;
 443         uint32_t rx_undersize_pkts;
 444         uint32_t rx_oversize_pkts;
 445         uint32_t rx_fragment_pkts;
 446         uint32_t rx_jabbers;
 447         uint64_t rx_control_frames;
 448         uint64_t rx_control_frames_unknown_opcode;
 449         uint32_t rx_in_range_errors;
 450         uint32_t rx_out_of_range_errors;
 451         uint32_t rx_address_match_errors;
 452         uint32_t rx_vlan_mismatch_errors;
 453         uint32_t rx_dropped_too_small;
 454         uint32_t rx_dropped_too_short;
 455         uint32_t rx_dropped_header_too_small;
 456         uint32_t rx_dropped_invalid_tcp_length;
 457         uint32_t rx_dropped_runt;
 458         uint32_t rx_ip_checksum_errors;
 459         uint32_t rx_tcp_checksum_errors;
 460         uint32_t rx_udp_checksum_errors;
 461         uint32_t rx_non_rss_pkts;
 462         uint64_t rx_ipv4_pkts;
 463         uint64_t rx_ipv6_pkts;
 464         uint64_t rx_ipv4_bytes;
 465         uint64_t rx_ipv6_bytes;
 466         uint64_t rx_nic_pkts;
 467         uint64_t rx_tcp_pkts;
 468         uint64_t rx_iscsi_pkts;
 469         uint64_t rx_management_pkts;
 470         uint64_t rx_switched_unicast_pkts;
 471         uint64_t rx_switched_multicast_pkts;
 472         uint64_t rx_switched_broadcast_pkts;
 473         uint64_t num_forwards;
 474         uint32_t rx_fifo_overflow;
 475         uint32_t rx_input_fifo_overflow;
 476         uint64_t rx_drops_too_many_frags;
 477         uint32_t rx_drops_invalid_queue;
 478         uint64_t rx_drops_mtu;
 479         uint64_t rx_pkts_64_bytes;
 480         uint64_t rx_pkts_65_to_127_bytes;
 481         uint64_t rx_pkts_128_to_255_bytes;
 482         uint64_t rx_pkts_256_to_511_bytes;
 483         uint64_t rx_pkts_512_to_1023_bytes;
 484         uint64_t rx_pkts_1024_to_1518_bytes;
 485         uint64_t rx_pkts_1519_to_2047_bytes;
 486         uint64_t rx_pkts_2048_to_4095_bytes;
 487         uint64_t rx_pkts_4096_to_8191_bytes;
 488         uint64_t rx_pkts_8192_to_9216_bytes;
 489 };
 490
 491 struct oce_drv_stats {
 492         struct oce_rx_stats rx;
 493         struct oce_tx_stats tx;
 494         union {
 495                 struct oce_be_stats be;
 496                 struct oce_xe201_stats xe201;
 497         } u0;
 498 };
 499
 500 #define INTR_RATE_HWM                   15000
 501 #define INTR_RATE_LWM                   10000
 502
 503 #define OCE_MAX_EQD 128u
 504 #define OCE_MIN_EQD 50u
 505
 506 struct oce_set_eqd {
 507         uint32_t eq_id;
 508         uint32_t phase;
 509         uint32_t delay_multiplier;
 510 };
 511
 512 struct oce_aic_obj {             /* Adaptive interrupt coalescing (AIC) info */
 513         boolean_t enable;
 514         uint32_t  min_eqd;            /* in usecs */
 515         uint32_t  max_eqd;            /* in usecs */
 516         uint32_t  cur_eqd;            /* in usecs */
 517         uint32_t  et_eqd;             /* configured value when aic is off */
 518         uint64_t  ticks;
 519         uint64_t  intr_prev;
 520 };
 521
 522 #define MAX_LOCK_DESC_LEN                       32
 523 struct oce_lock {
 524         struct mtx mutex;
 525         char name[MAX_LOCK_DESC_LEN+1];
 526 };
 527 #define OCE_LOCK                                struct oce_lock
 528
 529 #define LOCK_CREATE(lock, desc)                 { \
 530         strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \
 531         (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
 532         mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \
 533 }
 534 #define LOCK_DESTROY(lock)                      \
 535                 if (mtx_initialized(&(lock)->mutex))\
 536                         mtx_destroy(&(lock)->mutex)
 537 #define TRY_LOCK(lock)                          mtx_trylock(&(lock)->mutex)
 538 #define LOCK(lock)                              mtx_lock(&(lock)->mutex)
 539 #define LOCKED(lock)                            mtx_owned(&(lock)->mutex)
 540 #define UNLOCK(lock)                            mtx_unlock(&(lock)->mutex)
 541
 542 #define DEFAULT_MQ_MBOX_TIMEOUT                 (5 * 1000 * 1000)
 543 #define MBX_READY_TIMEOUT                       (1 * 1000 * 1000)
 544 #define DEFAULT_DRAIN_TIME                      200
 545 #define MBX_TIMEOUT_SEC                         5
 546 #define STAT_TIMEOUT                            2000000
 547
 548 /* size of the packet descriptor array in a transmit queue */
 549 #define OCE_TX_RING_SIZE                        2048
 550 #define OCE_RX_RING_SIZE                        1024
 551 #define OCE_WQ_PACKET_ARRAY_SIZE                (OCE_TX_RING_SIZE/2)
 552 #define OCE_RQ_PACKET_ARRAY_SIZE                (OCE_RX_RING_SIZE)
 553
 554 struct oce_dev;
 555
 556 enum eq_len {
 557         EQ_LEN_256  = 256,
 558         EQ_LEN_512  = 512,
 559         EQ_LEN_1024 = 1024,
 560         EQ_LEN_2048 = 2048,
 561         EQ_LEN_4096 = 4096
 562 };
 563
 564 enum eqe_size {
 565         EQE_SIZE_4  = 4,
 566         EQE_SIZE_16 = 16
 567 };
 568
 569 enum qtype {
 570         QTYPE_EQ,
 571         QTYPE_MQ,
 572         QTYPE_WQ,
 573         QTYPE_RQ,
 574         QTYPE_CQ,
 575         QTYPE_RSS
 576 };
 577
 578 typedef enum qstate_e {
 579         QDELETED = 0x0,
 580         QCREATED = 0x1
 581 } qstate_t;
 582
 583 struct eq_config {
 584         enum eq_len q_len;
 585         enum eqe_size item_size;
 586         uint32_t q_vector_num;
 587         uint8_t min_eqd;
 588         uint8_t max_eqd;
 589         uint8_t cur_eqd;
 590         uint8_t pad;
 591 };
 592
 593 struct oce_eq {
 594         uint32_t eq_id;
 595         void *parent;
 596         void *cb_context;
 597         oce_ring_buffer_t *ring;
 598         uint32_t ref_count;
 599         qstate_t qstate;
 600         struct oce_cq *cq[OCE_MAX_CQ_EQ];
 601         int cq_valid;
 602         struct eq_config eq_cfg;
 603         int vector;
 604         uint64_t intr;
 605 };
 606
 607 enum cq_len {
 608         CQ_LEN_256  = 256,
 609         CQ_LEN_512  = 512,
 610         CQ_LEN_1024 = 1024
 611 };
 612
 613 struct cq_config {
 614         enum cq_len q_len;
 615         uint32_t item_size;
 616         boolean_t is_eventable;
 617         boolean_t sol_eventable;
 618         boolean_t nodelay;
 619         uint16_t dma_coalescing;
 620 };
 621
 622 typedef uint16_t(*cq_handler_t) (void *arg1);
 623
 624 struct oce_cq {
 625         uint32_t cq_id;
 626         void *parent;
 627         struct oce_eq *eq;
 628         cq_handler_t cq_handler;
 629         void *cb_arg;
 630         oce_ring_buffer_t *ring;
 631         qstate_t qstate;
 632         struct cq_config cq_cfg;
 633         uint32_t ref_count;
 634 };
 635
 636
 637 struct mq_config {
 638         uint32_t eqd;
 639         uint8_t q_len;
 640         uint8_t pad[3];
 641 };
 642
 643
 644 struct oce_mq {
 645         void *parent;
 646         oce_ring_buffer_t *ring;
 647         uint32_t mq_id;
 648         struct oce_cq *cq;
 649         struct oce_cq *async_cq;
 650         uint32_t mq_free;
 651         qstate_t qstate;
 652         struct mq_config cfg;
 653 };
 654
 655 struct oce_mbx_ctx {
 656         struct oce_mbx *mbx;
 657         void (*cb) (void *ctx);
 658         void *cb_ctx;
 659 };
 660
 661 struct wq_config {
 662         uint8_t wq_type;
 663         uint16_t buf_size;
 664         uint8_t pad[1];
 665         uint32_t q_len;
 666         uint16_t pd_id;
 667         uint16_t pci_fn_num;
 668         uint32_t eqd;   /* interrupt delay */
 669         uint32_t nbufs;
 670         uint32_t nhdl;
 671 };
 672
 673 struct oce_tx_queue_stats {
 674         uint64_t tx_pkts;
 675         uint64_t tx_bytes;
 676         uint32_t tx_reqs;
 677         uint32_t tx_stops; /* number of times TX Q was stopped */
 678         uint32_t tx_wrbs;
 679         uint32_t tx_compl;
 680         uint32_t tx_rate;
 681         uint32_t ipv6_ext_hdr_tx_drop;
 682 };
 683
 684 struct oce_wq {
 685         OCE_LOCK tx_lock;
 686         void *parent;
 687         oce_ring_buffer_t *ring;
 688         struct oce_cq *cq;
 689         bus_dma_tag_t tag;
 690         struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
 691         uint32_t pkt_desc_tail;
 692         uint32_t pkt_desc_head;
 693         uint32_t wqm_used;
 694         boolean_t resched;
 695         uint32_t wq_free;
 696         uint32_t tx_deferd;
 697         uint32_t pkt_drops;
 698         qstate_t qstate;
 699         uint16_t wq_id;
 700         struct wq_config cfg;
 701         int queue_index;
 702         struct oce_tx_queue_stats tx_stats;
 703         struct buf_ring *br;
 704         struct task txtask;
 705         uint32_t db_offset;
 706 };
 707
 708 struct rq_config {
 709         uint32_t q_len;
 710         uint32_t frag_size;
 711         uint32_t mtu;
 712         uint32_t if_id;
 713         uint32_t is_rss_queue;
 714         uint32_t eqd;
 715         uint32_t nbufs;
 716 };
 717
 718 struct oce_rx_queue_stats {
 719         uint32_t rx_post_fail;
 720         uint32_t rx_ucast_pkts;
 721         uint32_t rx_compl;
 722         uint64_t rx_bytes;
 723         uint64_t rx_bytes_prev;
 724         uint64_t rx_pkts;
 725         uint32_t rx_rate;
 726         uint32_t rx_mcast_pkts;
 727         uint32_t rxcp_err;
 728         uint32_t rx_frags;
 729         uint32_t prev_rx_frags;
 730         uint32_t rx_fps;
 731 };
 732
 733
 734 struct oce_rq {
 735         struct rq_config cfg;
 736         uint32_t rq_id;
 737         int queue_index;
 738         uint32_t rss_cpuid;
 739         void *parent;
 740         oce_ring_buffer_t *ring;
 741         struct oce_cq *cq;
 742         void *pad1;
 743         bus_dma_tag_t tag;
 744         struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
 745         uint32_t packets_in;
 746         uint32_t packets_out;
 747         uint32_t pending;
 748 #ifdef notdef
 749         struct mbuf *head;
 750         struct mbuf *tail;
 751         int fragsleft;
 752 #endif
 753         qstate_t qstate;
 754         OCE_LOCK rx_lock;
 755         struct oce_rx_queue_stats rx_stats;
 756         struct lro_ctrl lro;
 757         int lro_pkts_queued;
 758
 759 };
 760
 761 struct link_status {
 762         uint8_t phys_port_speed;
 763         uint8_t logical_link_status;
 764         uint16_t qos_link_speed;
 765 };
 766
 767
 768
 769 #define OCE_FLAGS_PCIX                  0x00000001
 770 #define OCE_FLAGS_PCIE                  0x00000002
 771 #define OCE_FLAGS_MSI_CAPABLE           0x00000004
 772 #define OCE_FLAGS_MSIX_CAPABLE          0x00000008
 773 #define OCE_FLAGS_USING_MSI             0x00000010
 774 #define OCE_FLAGS_USING_MSIX            0x00000020
 775 #define OCE_FLAGS_FUNCRESET_RQD         0x00000040
 776 #define OCE_FLAGS_VIRTUAL_PORT          0x00000080
 777 #define OCE_FLAGS_MBOX_ENDIAN_RQD       0x00000100
 778 #define OCE_FLAGS_BE3                   0x00000200
 779 #define OCE_FLAGS_XE201                 0x00000400
 780 #define OCE_FLAGS_BE2                   0x00000800
 781 #define OCE_FLAGS_SH                    0x00001000
 782
 783 #define OCE_DEV_BE2_CFG_BAR             1
 784 #define OCE_DEV_CFG_BAR                 0
 785 #define OCE_PCI_CSR_BAR                 2
 786 #define OCE_PCI_DB_BAR                  4
 787
 788 typedef struct oce_softc {
 789         device_t dev;
 790         OCE_LOCK dev_lock;
 791
 792         uint32_t flags;
 793
 794         uint32_t pcie_link_speed;
 795         uint32_t pcie_link_width;
 796
 797         uint8_t fn; /* PCI function number */
 798
 799         struct resource *devcfg_res;
 800         bus_space_tag_t devcfg_btag;
 801         bus_space_handle_t devcfg_bhandle;
 802         void *devcfg_vhandle;
 803
 804         struct resource *csr_res;
 805         bus_space_tag_t csr_btag;
 806         bus_space_handle_t csr_bhandle;
 807         void *csr_vhandle;
 808
 809         struct resource *db_res;
 810         bus_space_tag_t db_btag;
 811         bus_space_handle_t db_bhandle;
 812         void *db_vhandle;
 813
 814         OCE_INTR_INFO intrs[OCE_MAX_EQ];
 815         int intr_count;
 816
 817         struct ifnet *ifp;
 818
 819         struct ifmedia media;
 820         uint8_t link_status;
 821         uint8_t link_speed;
 822         uint8_t duplex;
 823         uint32_t qos_link_speed;
 824         uint32_t speed;
 825
 826         char fw_version[32];
 827         struct mac_address_format macaddr;
 828
 829         OCE_DMA_MEM bsmbx;
 830         OCE_LOCK bmbx_lock;
 831
 832         uint32_t config_number;
 833         uint32_t asic_revision;
 834         uint32_t port_id;
 835         uint32_t function_mode;
 836         uint32_t function_caps;
 837         uint32_t max_tx_rings;
 838         uint32_t max_rx_rings;
 839
 840         struct oce_wq *wq[OCE_MAX_WQ];  /* TX work queues */
 841         struct oce_rq *rq[OCE_MAX_RQ];  /* RX work queues */
 842         struct oce_cq *cq[OCE_MAX_CQ];  /* Completion queues */
 843         struct oce_eq *eq[OCE_MAX_EQ];  /* Event queues */
 844         struct oce_mq *mq;              /* Mailbox queue */
 845
 846         uint32_t neqs;
 847         uint32_t ncqs;
 848         uint32_t nrqs;
 849         uint32_t nwqs;
 850         uint32_t nrssqs;
 851
 852         uint32_t tx_ring_size;
 853         uint32_t rx_ring_size;
 854         uint32_t rq_frag_size;
 855
 856         uint32_t if_id;         /* interface ID */
 857         uint32_t nifs;          /* number of adapter interfaces, 0 or 1 */
 858         uint32_t pmac_id;       /* PMAC id */
 859
 860         uint32_t if_cap_flags;
 861
 862         uint32_t flow_control;
 863         uint8_t  promisc;
 864
 865         struct oce_aic_obj aic_obj[OCE_MAX_EQ];
 866
 867         /*Vlan Filtering related */
 868         eventhandler_tag vlan_attach;
 869         eventhandler_tag vlan_detach;
 870         uint16_t vlans_added;
 871         uint8_t vlan_tag[MAX_VLANS];
 872         /*stats */
 873         OCE_DMA_MEM stats_mem;
 874         struct oce_drv_stats oce_stats_info;
 875         struct callout  timer;
 876         int8_t be3_native;
 877         uint8_t hw_error;
 878         uint16_t qnq_debug_event;
 879         uint16_t qnqid;
 880         uint32_t pvid;
 881         uint32_t max_vlans;
 882
 883 } OCE_SOFTC, *POCE_SOFTC;
 884
 885
 886
 887 /**************************************************
 888  * BUS memory read/write macros
 889  * BE3: accesses three BAR spaces (CFG, CSR, DB)
 890  * Lancer: accesses one BAR space (CFG)
 891  **************************************************/
 892 #define OCE_READ_CSR_MPU(sc, space, o) \
 893         ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
 894                                         (sc)->space##_bhandle,o)) \
 895                                 : (bus_space_read_4((sc)->devcfg_btag, \
 896                                         (sc)->devcfg_bhandle,o)))
 897 #define OCE_READ_REG32(sc, space, o) \
 898         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
 899                                         (sc)->space##_bhandle,o)) \
 900                                 : (bus_space_read_4((sc)->devcfg_btag, \
 901                                         (sc)->devcfg_bhandle,o)))
 902 #define OCE_READ_REG16(sc, space, o) \
 903         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
 904                                         (sc)->space##_bhandle,o)) \
 905                                 : (bus_space_read_2((sc)->devcfg_btag, \
 906                                         (sc)->devcfg_bhandle,o)))
 907 #define OCE_READ_REG8(sc, space, o) \
 908         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
 909                                         (sc)->space##_bhandle,o)) \
 910                                 : (bus_space_read_1((sc)->devcfg_btag, \
 911                                         (sc)->devcfg_bhandle,o)))
 912
 913 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
 914         ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
 915                                        (sc)->space##_bhandle,o,v)) \
 916                                 : (bus_space_write_4((sc)->devcfg_btag, \
 917                                         (sc)->devcfg_bhandle,o,v)))
 918 #define OCE_WRITE_REG32(sc, space, o, v) \
 919         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
 920                                        (sc)->space##_bhandle,o,v)) \
 921                                 : (bus_space_write_4((sc)->devcfg_btag, \
 922                                         (sc)->devcfg_bhandle,o,v)))
 923 #define OCE_WRITE_REG16(sc, space, o, v) \
 924         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
 925                                        (sc)->space##_bhandle,o,v)) \
 926                                 : (bus_space_write_2((sc)->devcfg_btag, \
 927                                         (sc)->devcfg_bhandle,o,v)))
 928 #define OCE_WRITE_REG8(sc, space, o, v) \
 929         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
 930                                        (sc)->space##_bhandle,o,v)) \
 931                                 : (bus_space_write_1((sc)->devcfg_btag, \
 932                                         (sc)->devcfg_bhandle,o,v)))
 933
 934
 935 /***********************************************************
 936  * DMA memory functions
 937  ***********************************************************/
 938 #define oce_dma_sync(d, f)              bus_dmamap_sync((d)->tag, (d)->map, f)
 939 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
 940 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
 941 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
 942 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
 943 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
 944                                           uint32_t q_len, uint32_t num_entries);
 945 /************************************************************
 946  * oce_hw_xxx functions
 947  ************************************************************/
 948 int oce_clear_rx_buf(struct oce_rq *rq);
 949 int oce_hw_pci_alloc(POCE_SOFTC sc);
 950 int oce_hw_init(POCE_SOFTC sc);
 951 int oce_hw_start(POCE_SOFTC sc);
 952 int oce_create_nw_interface(POCE_SOFTC sc);
 953 int oce_pci_soft_reset(POCE_SOFTC sc);
 954 int oce_hw_update_multicast(POCE_SOFTC sc);
 955 void oce_delete_nw_interface(POCE_SOFTC sc);
 956 void oce_hw_shutdown(POCE_SOFTC sc);
 957 void oce_hw_intr_enable(POCE_SOFTC sc);
 958 void oce_hw_intr_disable(POCE_SOFTC sc);
 959 void oce_hw_pci_free(POCE_SOFTC sc);
 960
 961 /***********************************************************
 962  * oce_queue_xxx functions
 963  ***********************************************************/
 964 int oce_queue_init_all(POCE_SOFTC sc);
 965 int oce_start_rq(struct oce_rq *rq);
 966 int oce_start_wq(struct oce_wq *wq);
 967 int oce_start_mq(struct oce_mq *mq);
 968 int oce_start_rx(POCE_SOFTC sc);
 969 void oce_arm_eq(POCE_SOFTC sc,
 970                 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
 971 void oce_queue_release_all(POCE_SOFTC sc);
 972 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
 973 void oce_drain_eq(struct oce_eq *eq);
 974 void oce_drain_mq_cq(void *arg);
 975 void oce_drain_rq_cq(struct oce_rq *rq);
 976 void oce_drain_wq_cq(struct oce_wq *wq);
 977
 978 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
 979
 980 /***********************************************************
 981  * cleanup  functions
 982  ***********************************************************/
 983 void oce_stop_rx(POCE_SOFTC sc);
 984 void oce_intr_free(POCE_SOFTC sc);
 985 void oce_free_posted_rxbuf(struct oce_rq *rq);
 986 #if defined(INET6) || defined(INET)
 987 void oce_free_lro(POCE_SOFTC sc);
 988 #endif
 989
 990
 991 /************************************************************
 992  * Mailbox functions
 993  ************************************************************/
 994 int oce_fw_clean(POCE_SOFTC sc);
 995 int oce_reset_fun(POCE_SOFTC sc);
 996 int oce_mbox_init(POCE_SOFTC sc);
 997 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
 998 int oce_get_fw_version(POCE_SOFTC sc);
 999 int oce_first_mcc_cmd(POCE_SOFTC sc);
1000
1001 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1002                         uint8_t type, struct mac_address_format *mac);
1003 int oce_get_fw_config(POCE_SOFTC sc);
1004 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1005                 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1006 int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1007 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1008                 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1009                 uint32_t untagged, uint32_t enable_promisc);
1010 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1011 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1012 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable);
1013 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1014 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1015 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1016 int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1017 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1018                                 uint32_t reset_stats);
1019 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1020                                 uint32_t req_size, uint32_t reset_stats);
1021 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1022 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1023 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1024 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1025                 uint32_t if_id, uint32_t *pmac_id);
1026 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1027         uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1028         uint64_t pattern);
1029
1030 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1031         uint8_t loopback_type, uint8_t enable);
1032
1033 int oce_mbox_check_native_mode(POCE_SOFTC sc);
1034 int oce_mbox_post(POCE_SOFTC sc,
1035                   struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1036 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1037                                 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1038 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1039                         uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1040                         uint32_t *written_data, uint32_t *additional_status);
1041
1042 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1043                                 uint32_t offset, uint32_t optype);
1044 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1045 int oce_mbox_create_rq(struct oce_rq *rq);
1046 int oce_mbox_create_wq(struct oce_wq *wq);
1047 int oce_mbox_create_eq(struct oce_eq *eq);
1048 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1049                          uint32_t is_eventable);
1050 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1051 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1052                                         int num);
1053 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss);
1054 int oce_get_func_config(POCE_SOFTC sc);
1055 void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1056                              uint8_t dom,
1057                              uint8_t port,
1058                              uint8_t subsys,
1059                              uint8_t opcode,
1060                              uint32_t timeout, uint32_t pyld_len,
1061                              uint8_t version);
1062
1063
1064 uint16_t oce_mq_handler(void *arg);
1065
1066 /************************************************************
1067  * Transmit functions
1068  ************************************************************/
1069 uint16_t oce_wq_handler(void *arg);
1070 void     oce_start(struct ifnet *ifp);
1071 void     oce_tx_task(void *arg, int npending);
1072
1073 /************************************************************
1074  * Receive functions
1075  ************************************************************/
1076 int      oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1077 uint16_t oce_rq_handler(void *arg);
1078
1079
1080 /* Sysctl functions */
1081 void oce_add_sysctls(POCE_SOFTC sc);
1082 void oce_refresh_queue_stats(POCE_SOFTC sc);
1083 int  oce_refresh_nic_stats(POCE_SOFTC sc);
1084 int  oce_stats_init(POCE_SOFTC sc);
1085 void oce_stats_free(POCE_SOFTC sc);
1086
1087 /* Capabilities */
1088 #define OCE_MODCAP_RSS                  1
1089 #define OCE_MAX_RSP_HANDLED             64
1090 extern uint32_t oce_max_rsp_handled;    /* max responses */
1091
1092 #define OCE_MAC_LOOPBACK                0x0
1093 #define OCE_PHY_LOOPBACK                0x1
1094 #define OCE_ONE_PORT_EXT_LOOPBACK       0x2
1095 #define OCE_NO_LOOPBACK                 0xff
1096
1097 #undef IFM_40G_SR4
1098 #define IFM_40G_SR4                     28
1099
1100 #define atomic_inc_32(x)                atomic_add_32(x, 1)
1101 #define atomic_dec_32(x)                atomic_subtract_32(x, 1)
1102
1103 #define LE_64(x)                        htole64(x)
1104 #define LE_32(x)                        htole32(x)
1105 #define LE_16(x)                        htole16(x)
1106 #define HOST_64(x)                      le64toh(x)
1107 #define HOST_32(x)                      le32toh(x)
1108 #define HOST_16(x)                      le16toh(x)
1109 #define DW_SWAP(x, l)
1110 #define IS_ALIGNED(x,a)                 ((x % a) == 0)
1111 #define ADDR_HI(x)                      ((uint32_t)((uint64_t)(x) >> 32))
1112 #define ADDR_LO(x)                      ((uint32_t)((uint64_t)(x) & 0xffffffff));
1113
1114 #define IF_LRO_ENABLED(sc)  (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0)
1115 #define IF_LSO_ENABLED(sc)  (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0)
1116 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0)
1117
1118 #define OCE_LOG2(x)                     (oce_highbit(x))
1119 static inline uint32_t oce_highbit(uint32_t x)
1120 {
1121         int i;
1122         int c;
1123         int b;
1124
1125         c = 0;
1126         b = 0;
1127
1128         for (i = 0; i < 32; i++) {
1129                 if ((1 << i) & x) {
1130                         c++;
1131                         b = i;
1132                 }
1133         }
1134
1135         if (c == 1)
1136                 return b;
1137
1138         return 0;
1139 }
1140
1141 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1142 {
1143         if (IS_BE(sc))
1144                 return MPU_EP_SEMAPHORE_BE3;
1145         else if (IS_SH(sc))
1146                 return MPU_EP_SEMAPHORE_SH;
1147         else
1148                 return MPU_EP_SEMAPHORE_XE201;
1149 }
1150
1151 #define TRANSCEIVER_DATA_NUM_ELE 64
1152 #define TRANSCEIVER_DATA_SIZE 256
1153 #define TRANSCEIVER_A0_SIZE 128
1154 #define TRANSCEIVER_A2_SIZE 128
1155 #define PAGE_NUM_A0 0xa0
1156 #define PAGE_NUM_A2 0xa2
1157 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1158                      || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1159