sys/dev/siba/siba_core.c

   1 /*-
   2  * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 /*
  34  * the Sonics Silicon Backplane driver.
  35  */
  36
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/module.h>
  40 #include <sys/kernel.h>
  41 #include <sys/endian.h>
  42 #include <sys/errno.h>
  43 #include <sys/lock.h>
  44 #include <sys/mutex.h>
  45 #include <machine/bus.h>
  46 #include <machine/resource.h>
  47 #include <sys/bus.h>
  48 #include <sys/rman.h>
  49 #include <sys/socket.h>
  50
  51 #include <net/if.h>
  52 #include <net/if_media.h>
  53 #include <net/if_arp.h>
  54
  55 #include <dev/pci/pcivar.h>
  56 #include <dev/pci/pcireg.h>
  57
  58 #include <dev/siba/siba_ids.h>
  59 #include <dev/siba/sibareg.h>
  60 #include <dev/siba/sibavar.h>
  61
  62 #ifdef SIBA_DEBUG
  63 enum {
  64         SIBA_DEBUG_SCAN         = 0x00000001,   /* scan */
  65         SIBA_DEBUG_PMU          = 0x00000002,   /* PMU */
  66         SIBA_DEBUG_PLL          = 0x00000004,   /* PLL */
  67         SIBA_DEBUG_SWITCHCORE   = 0x00000008,   /* switching core */
  68         SIBA_DEBUG_SPROM        = 0x00000010,   /* SPROM */
  69         SIBA_DEBUG_CORE         = 0x00000020,   /* handling cores */
  70         SIBA_DEBUG_ANY          = 0xffffffff
  71 };
  72 #define DPRINTF(siba, m, fmt, ...) do {                 \
  73         if (siba->siba_debug & (m))                     \
  74                 printf(fmt, __VA_ARGS__);               \
  75 } while (0)
  76 #else
  77 #define DPRINTF(siba, m, fmt, ...) do { (void) siba; } while (0)
  78 #endif
  79 #define N(a)                    (sizeof(a) / sizeof(a[0]))
  80
  81 static void     siba_pci_gpio(struct siba_softc *, uint32_t, int);
  82 static void     siba_scan(struct siba_softc *);
  83 static int      siba_switchcore(struct siba_softc *, uint8_t);
  84 static int      siba_pci_switchcore_sub(struct siba_softc *, uint8_t);
  85 static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t);
  86 static uint16_t siba_dev2chipid(struct siba_softc *);
  87 static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t);
  88 static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t);
  89 static void     siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t);
  90 static void     siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t);
  91 static void     siba_cc_clock(struct siba_cc *,
  92                     enum siba_clock);
  93 static void     siba_cc_pmu_init(struct siba_cc *);
  94 static void     siba_cc_power_init(struct siba_cc *);
  95 static void     siba_cc_powerup_delay(struct siba_cc *);
  96 static int      siba_cc_clockfreq(struct siba_cc *, int);
  97 static void     siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t);
  98 static void     siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t);
  99 static enum siba_clksrc siba_cc_clksrc(struct siba_cc *);
 100 static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t);
 101 static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t);
 102 static void     siba_cc_pll_write(struct siba_cc *, uint32_t,
 103                     uint32_t);
 104 static const struct siba_cc_pmu0_plltab *
 105                 siba_cc_pmu0_plltab_findentry(uint32_t);
 106 static int      siba_pci_sprom(struct siba_softc *, struct siba_sprom *);
 107 static int      siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t);
 108 static int      sprom_check_crc(const uint16_t *, size_t);
 109 static uint8_t  siba_crc8(uint8_t, uint8_t);
 110 static void     siba_sprom_r123(struct siba_sprom *, const uint16_t *);
 111 static void     siba_sprom_r45(struct siba_sprom *, const uint16_t *);
 112 static void     siba_sprom_r8(struct siba_sprom *, const uint16_t *);
 113 static int8_t   siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t,
 114                     uint16_t);
 115 static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *);
 116 static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t);
 117 static void     siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t);
 118 static uint32_t siba_pcie_read(struct siba_pci *, uint32_t);
 119 static void     siba_pcie_write(struct siba_pci *, uint32_t, uint32_t);
 120 static void     siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t,
 121                     uint16_t);
 122 static void     siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t,
 123                     uint16_t);
 124 static void     siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t,
 125                     uint16_t);
 126 static void     siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t,
 127                     uint16_t);
 128 static void     siba_pci_write_multi_1(struct siba_dev_softc *, const void *,
 129                     size_t, uint16_t);
 130 static void     siba_pci_write_multi_2(struct siba_dev_softc *, const void *,
 131                     size_t, uint16_t);
 132 static void     siba_pci_write_multi_4(struct siba_dev_softc *, const void *,
 133                     size_t, uint16_t);
 134 static const char *siba_core_name(uint16_t);
 135 static void     siba_pcicore_init(struct siba_pci *);
 136 static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t);
 137 static void     siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t);
 138 static void     siba_powerup_sub(struct siba_softc *, int);
 139 static int      siba_powerdown_sub(struct siba_softc *);
 140 static int      siba_dev_isup_sub(struct siba_dev_softc *);
 141 static void     siba_dev_up_sub(struct siba_dev_softc *, uint32_t);
 142 static void     siba_dev_down_sub(struct siba_dev_softc *, uint32_t);
 143 int             siba_core_attach(struct siba_softc *);
 144 int             siba_core_detach(struct siba_softc *);
 145 int             siba_core_suspend(struct siba_softc *);
 146 int             siba_core_resume(struct siba_softc *);
 147 uint8_t         siba_getncores(device_t, uint16_t);
 148
 149 static const struct siba_bus_ops siba_pci_ops = {
 150         .read_2         = siba_pci_read_2,
 151         .read_4         = siba_pci_read_4,
 152         .write_2        = siba_pci_write_2,
 153         .write_4        = siba_pci_write_4,
 154         .read_multi_1   = siba_pci_read_multi_1,
 155         .read_multi_2   = siba_pci_read_multi_2,
 156         .read_multi_4   = siba_pci_read_multi_4,
 157         .write_multi_1  = siba_pci_write_multi_1,
 158         .write_multi_2  = siba_pci_write_multi_2,
 159         .write_multi_4  = siba_pci_write_multi_4,
 160 };
 161
 162 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] =
 163     SIBA_CC_PMU_4325_RES_UPDOWN;
 164 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] =
 165     SIBA_CC_PMU_4325_RES_DEPEND;
 166 static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] =
 167     SIBA_CC_PMU_4328_RES_UPDOWN;
 168 static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] =
 169     SIBA_CC_PMU_4328_RES_DEPEND;
 170 static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] =
 171     SIBA_CC_PMU0_PLLTAB_ENTRY;
 172 static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] =
 173     SIBA_CC_PMU1_PLLTAB_ENTRY;
 174
 175 int
 176 siba_core_attach(struct siba_softc *siba)
 177 {
 178         struct siba_cc *scc;
 179         int error;
 180
 181         KASSERT(siba->siba_type == SIBA_TYPE_PCI,
 182             ("unsupported BUS type (%#x)", siba->siba_type));
 183
 184         siba->siba_ops = &siba_pci_ops;
 185
 186         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
 187         siba_scan(siba);
 188
 189         /* XXX init PCI or PCMCIA host devices */
 190
 191         siba_powerup_sub(siba, 0);
 192
 193         /* init ChipCommon */
 194         scc = &siba->siba_cc;
 195         if (scc->scc_dev != NULL) {
 196                 siba_cc_pmu_init(scc);
 197                 siba_cc_power_init(scc);
 198                 siba_cc_clock(scc, SIBA_CLOCK_FAST);
 199                 siba_cc_powerup_delay(scc);
 200         }
 201
 202         error = siba_pci_sprom(siba, &siba->siba_sprom);
 203         if (error) {
 204                 siba_powerdown_sub(siba);
 205                 return (error);
 206         }
 207
 208         siba_pcicore_init(&siba->siba_pci);
 209         siba_powerdown_sub(siba);
 210
 211         return (bus_generic_attach(siba->siba_dev));
 212 }
 213
 214 int
 215 siba_core_detach(struct siba_softc *siba)
 216 {
 217         /* detach & delete all children */
 218         device_delete_children(siba->siba_dev);
 219         return (0);
 220 }
 221
 222 static void
 223 siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on)
 224 {
 225         uint32_t in, out;
 226         uint16_t status;
 227
 228         if (siba->siba_type != SIBA_TYPE_PCI)
 229                 return;
 230
 231         out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4);
 232         if (on == 0) {
 233                 if (what & SIBA_GPIO_PLL)
 234                         out |= SIBA_GPIO_PLL;
 235                 if (what & SIBA_GPIO_CRYSTAL)
 236                         out &= ~SIBA_GPIO_CRYSTAL;
 237                 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
 238                 pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN,
 239                     pci_read_config(siba->siba_dev,
 240                         SIBA_GPIO_OUT_EN, 4) | what, 4);
 241                 return;
 242         }
 243
 244         in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4);
 245         if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) {
 246                 if (what & SIBA_GPIO_CRYSTAL) {
 247                         out |= SIBA_GPIO_CRYSTAL;
 248                         if (what & SIBA_GPIO_PLL)
 249                                 out |= SIBA_GPIO_PLL;
 250                         pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
 251                         pci_write_config(siba->siba_dev,
 252                             SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev,
 253                                 SIBA_GPIO_OUT_EN, 4) | what, 4);
 254                         DELAY(1000);
 255                 }
 256                 if (what & SIBA_GPIO_PLL) {
 257                         out &= ~SIBA_GPIO_PLL;
 258                         pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4);
 259                         DELAY(5000);
 260                 }
 261         }
 262
 263         status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2);
 264         status &= ~PCIM_STATUS_STABORT;
 265         pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2);
 266 }
 267
 268 static void
 269 siba_scan(struct siba_softc *siba)
 270 {
 271         struct siba_dev_softc *sd;
 272         uint32_t idhi, tmp;
 273         device_t child;
 274         int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0,
 275             n_pci = 0;
 276
 277         KASSERT(siba->siba_type == SIBA_TYPE_PCI,
 278             ("unsupported BUS type (%#x)", siba->siba_type));
 279
 280         siba->siba_ndevs = 0;
 281         error = siba_switchcore(siba, 0); /* need the first core */
 282         if (error)
 283                 return;
 284
 285         idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH);
 286         if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) {
 287                 tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID);
 288                 siba->siba_chipid = SIBA_CC_ID(tmp);
 289                 siba->siba_chiprev = SIBA_CC_REV(tmp);
 290                 siba->siba_chippkg = SIBA_CC_PKG(tmp);
 291                 if (SIBA_IDHIGH_REV(idhi) >= 4)
 292                         siba->siba_ndevs = SIBA_CC_NCORES(tmp);
 293                 siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0,
 294                     SIBA_CC_CAPS);
 295         } else {
 296                 if (siba->siba_type == SIBA_TYPE_PCI) {
 297                         siba->siba_chipid = siba_dev2chipid(siba);
 298                         siba->siba_chiprev = pci_read_config(siba->siba_dev,
 299                             PCIR_REVID, 2);
 300                         siba->siba_chippkg = 0;
 301                 } else {
 302                         siba->siba_chipid = 0x4710;
 303                         siba->siba_chiprev = 0;
 304                         siba->siba_chippkg = 0;
 305                 }
 306         }
 307         if (siba->siba_ndevs == 0)
 308                 siba->siba_ndevs = siba_getncores(siba->siba_dev,
 309                     siba->siba_chipid);
 310         if (siba->siba_ndevs > SIBA_MAX_CORES) {
 311                 device_printf(siba->siba_dev,
 312                     "too many siba cores (max %d %d)\n",
 313                     SIBA_MAX_CORES, siba->siba_ndevs);
 314                 return;
 315         }
 316
 317         /* looking basic information about each cores/devices */
 318         for (i = 0; i < siba->siba_ndevs; i++) {
 319                 error = siba_switchcore(siba, i);
 320                 if (error)
 321                         return;
 322                 sd = &(siba->siba_devs[dev_i]);
 323                 idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH);
 324                 sd->sd_bus = siba;
 325                 sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi);
 326                 sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi);
 327                 sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi);
 328                 sd->sd_ops = siba->siba_ops;
 329                 sd->sd_coreidx = i;
 330
 331                 DPRINTF(siba, SIBA_DEBUG_SCAN,
 332                     "core %d (%s) found (cc %#xrev %#x vendor %#x)\n",
 333                     i, siba_core_name(sd->sd_id.sd_device),
 334                     sd->sd_id.sd_device, sd->sd_id.sd_rev, sd->sd_id.vendor);
 335
 336                 switch (sd->sd_id.sd_device) {
 337                 case SIBA_DEVID_CHIPCOMMON:
 338                         n_cc++;
 339                         if (n_cc > 1) {
 340                                 device_printf(siba->siba_dev,
 341                                     "warn: multiple ChipCommon\n");
 342                                 break;
 343                         }
 344                         siba->siba_cc.scc_dev = sd;
 345                         break;
 346                 case SIBA_DEVID_80211:
 347                         n_80211++;
 348                         if (n_80211 > 1) {
 349                                 device_printf(siba->siba_dev,
 350                                     "warn: multiple 802.11 core\n");
 351                                 continue;
 352                         }
 353                         break;
 354                 case SIBA_DEVID_PCI:
 355                 case SIBA_DEVID_PCIE:
 356                         n_pci++;
 357                         error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS,
 358                             &base);
 359                         is_pcie = (error == 0) ? 1 : 0;
 360
 361                         if (n_pci > 1) {
 362                                 device_printf(siba->siba_dev,
 363                                     "warn: multiple PCI(E) cores\n");
 364                                 break;
 365                         }
 366                         if (sd->sd_id.sd_device == SIBA_DEVID_PCI &&
 367                             is_pcie == 1)
 368                                 continue;
 369                         if (sd->sd_id.sd_device == SIBA_DEVID_PCIE &&
 370                             is_pcie == 0)
 371                                 continue;
 372                         siba->siba_pci.spc_dev = sd;
 373                         break;
 374                 case SIBA_DEVID_MODEM:
 375                 case SIBA_DEVID_PCMCIA:
 376                         break;
 377                 default:
 378                         device_printf(siba->siba_dev,
 379                             "unsupported coreid (%s)\n",
 380                             siba_core_name(sd->sd_id.sd_device));
 381                         break;
 382                 }
 383                 dev_i++;
 384
 385                 child = device_add_child(siba->siba_dev, NULL, -1);
 386                 if (child == NULL) {
 387                         device_printf(siba->siba_dev, "child attach failed\n");
 388                         continue;
 389                 }
 390
 391                 device_set_ivars(child, sd);
 392         }
 393         siba->siba_ndevs = dev_i;
 394 }
 395
 396 static int
 397 siba_switchcore(struct siba_softc *siba, uint8_t idx)
 398 {
 399
 400         switch (siba->siba_type) {
 401         case SIBA_TYPE_PCI:
 402                 return (siba_pci_switchcore_sub(siba, idx));
 403         default:
 404                 KASSERT(0 == 1,
 405                     ("%s: unsupported bustype %#x", __func__,
 406                     siba->siba_type));
 407         }
 408         return (0);
 409 }
 410
 411 static int
 412 siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx)
 413 {
 414 #define RETRY_MAX       50
 415         int i;
 416         uint32_t dir;
 417
 418         dir = SIBA_REGWIN(idx);
 419
 420         for (i = 0; i < RETRY_MAX; i++) {
 421                 pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4);
 422                 if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir)
 423                         return (0);
 424                 DELAY(10);
 425         }
 426         return (ENODEV);
 427 #undef RETRY_MAX
 428 }
 429
 430 static int
 431 siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd)
 432 {
 433         int error;
 434
 435         DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n",
 436             siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx);
 437
 438         error = siba_pci_switchcore_sub(siba, sd->sd_coreidx);
 439         if (error == 0)
 440                 siba->siba_curdev = sd;
 441
 442         return (error);
 443 }
 444
 445 static uint32_t
 446 siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx,
 447     uint16_t offset)
 448 {
 449
 450         (void)coreidx;
 451         KASSERT(siba->siba_type == SIBA_TYPE_PCI,
 452             ("unsupported BUS type (%#x)", siba->siba_type));
 453
 454         return (SIBA_READ_4(siba, offset));
 455 }
 456
 457 static uint16_t
 458 siba_dev2chipid(struct siba_softc *siba)
 459 {
 460         uint16_t chipid = 0;
 461
 462         switch (siba->siba_pci_did) {
 463         case 0x4301:
 464                 chipid = 0x4301;
 465                 break;
 466         case 0x4305:
 467         case 0x4306:
 468         case 0x4307:
 469                 chipid = 0x4307;
 470                 break;
 471         case 0x4403:
 472                 chipid = 0x4402;
 473                 break;
 474         case 0x4610:
 475         case 0x4611:
 476         case 0x4612:
 477         case 0x4613:
 478         case 0x4614:
 479         case 0x4615:
 480                 chipid = 0x4610;
 481                 break;
 482         case 0x4710:
 483         case 0x4711:
 484         case 0x4712:
 485         case 0x4713:
 486         case 0x4714:
 487         case 0x4715:
 488                 chipid = 0x4710;
 489                 break;
 490         case 0x4320:
 491         case 0x4321:
 492         case 0x4322:
 493         case 0x4323:
 494         case 0x4324:
 495         case 0x4325:
 496                 chipid = 0x4309;
 497                 break;
 498         case PCI_DEVICE_ID_BCM4401:
 499         case PCI_DEVICE_ID_BCM4401B0:
 500         case PCI_DEVICE_ID_BCM4401B1:
 501                 chipid = 0x4401;
 502                 break;
 503         default:
 504                 device_printf(siba->siba_dev, "unknown PCI did (%d)\n",
 505                     siba->siba_pci_did);
 506         }
 507
 508         return (chipid);
 509 }
 510
 511 /*
 512  * Earlier ChipCommon revisions have hardcoded number of cores
 513  * present dependent on the ChipCommon ID.
 514  */
 515 uint8_t
 516 siba_getncores(device_t dev, uint16_t chipid)
 517 {
 518         switch (chipid) {
 519         case 0x4401:
 520         case 0x4402:
 521                 return (3);
 522         case 0x4301:
 523         case 0x4307:
 524                 return (5);
 525         case 0x4306:
 526                 return (6);
 527         case SIBA_CCID_SENTRY5:
 528                 return (7);
 529         case 0x4310:
 530                 return (8);
 531         case SIBA_CCID_BCM4710:
 532         case 0x4610:
 533         case SIBA_CCID_BCM4704:
 534                 return (9);
 535         default:
 536                 device_printf(dev, "unknown the chipset ID %#x\n", chipid);
 537         }
 538
 539         return (1);
 540 }
 541
 542 static const char *
 543 siba_core_name(uint16_t coreid)
 544 {
 545
 546         switch (coreid) {
 547         case SIBA_DEVID_CHIPCOMMON:
 548                 return ("ChipCommon");
 549         case SIBA_DEVID_ILINE20:
 550                 return ("ILine 20");
 551         case SIBA_DEVID_SDRAM:
 552                 return ("SDRAM");
 553         case SIBA_DEVID_PCI:
 554                 return ("PCI");
 555         case SIBA_DEVID_MIPS:
 556                 return ("MIPS");
 557         case SIBA_DEVID_ETHERNET:
 558                 return ("Fast Ethernet");
 559         case SIBA_DEVID_MODEM:
 560                 return ("Modem");
 561         case SIBA_DEVID_USB11_HOSTDEV:
 562                 return ("USB 1.1 Hostdev");
 563         case SIBA_DEVID_ADSL:
 564                 return ("ADSL");
 565         case SIBA_DEVID_ILINE100:
 566                 return ("ILine 100");
 567         case SIBA_DEVID_IPSEC:
 568                 return ("IPSEC");
 569         case SIBA_DEVID_PCMCIA:
 570                 return ("PCMCIA");
 571         case SIBA_DEVID_INTERNAL_MEM:
 572                 return ("Internal Memory");
 573         case SIBA_DEVID_SDRAMDDR:
 574                 return ("MEMC SDRAM");
 575         case SIBA_DEVID_EXTIF:
 576                 return ("EXTIF");
 577         case SIBA_DEVID_80211:
 578                 return ("IEEE 802.11");
 579         case SIBA_DEVID_MIPS_3302:
 580                 return ("MIPS 3302");
 581         case SIBA_DEVID_USB11_HOST:
 582                 return ("USB 1.1 Host");
 583         case SIBA_DEVID_USB11_DEV:
 584                 return ("USB 1.1 Device");
 585         case SIBA_DEVID_USB20_HOST:
 586                 return ("USB 2.0 Host");
 587         case SIBA_DEVID_USB20_DEV:
 588                 return ("USB 2.0 Device");
 589         case SIBA_DEVID_SDIO_HOST:
 590                 return ("SDIO Host");
 591         case SIBA_DEVID_ROBOSWITCH:
 592                 return ("Roboswitch");
 593         case SIBA_DEVID_PARA_ATA:
 594                 return ("PATA");
 595         case SIBA_DEVID_SATA_XORDMA:
 596                 return ("SATA XOR-DMA");
 597         case SIBA_DEVID_ETHERNET_GBIT:
 598                 return ("GBit Ethernet");
 599         case SIBA_DEVID_PCIE:
 600                 return ("PCI-Express");
 601         case SIBA_DEVID_MIMO_PHY:
 602                 return ("MIMO PHY");
 603         case SIBA_DEVID_SRAM_CTRLR:
 604                 return ("SRAM Controller");
 605         case SIBA_DEVID_MINI_MACPHY:
 606                 return ("Mini MACPHY");
 607         case SIBA_DEVID_ARM_1176:
 608                 return ("ARM 1176");
 609         case SIBA_DEVID_ARM_7TDMI:
 610                 return ("ARM 7TDMI");
 611         }
 612         return ("unknown");
 613 }
 614
 615 static uint16_t
 616 siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset)
 617 {
 618         struct siba_softc *siba = sd->sd_bus;
 619
 620         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 621                 return (0xffff);
 622
 623         return (SIBA_READ_2(siba, offset));
 624 }
 625
 626 static uint32_t
 627 siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset)
 628 {
 629         struct siba_softc *siba = sd->sd_bus;
 630
 631         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 632                 return (0xffff);
 633
 634         return (SIBA_READ_4(siba, offset));
 635 }
 636
 637 static void
 638 siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value)
 639 {
 640         struct siba_softc *siba = sd->sd_bus;
 641
 642         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 643                 return;
 644
 645         SIBA_WRITE_2(siba, offset, value);
 646 }
 647
 648 static void
 649 siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
 650 {
 651         struct siba_softc *siba = sd->sd_bus;
 652
 653         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 654                 return;
 655
 656         SIBA_WRITE_4(siba, offset, value);
 657 }
 658
 659 static void
 660 siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count,
 661     uint16_t offset)
 662 {
 663         struct siba_softc *siba = sd->sd_bus;
 664
 665         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
 666                 memset(buffer, 0xff, count);
 667                 return;
 668         }
 669
 670         SIBA_READ_MULTI_1(siba, offset, buffer, count);
 671 }
 672
 673 static void
 674 siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count,
 675     uint16_t offset)
 676 {
 677         struct siba_softc *siba = sd->sd_bus;
 678
 679         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
 680                 memset(buffer, 0xff, count);
 681                 return;
 682         }
 683
 684         KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
 685         SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1);
 686 }
 687
 688 static void
 689 siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count,
 690     uint16_t offset)
 691 {
 692         struct siba_softc *siba = sd->sd_bus;
 693
 694         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) {
 695                 memset(buffer, 0xff, count);
 696                 return;
 697         }
 698
 699         KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
 700         SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2);
 701 }
 702
 703 static void
 704 siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer,
 705     size_t count, uint16_t offset)
 706 {
 707         struct siba_softc *siba = sd->sd_bus;
 708
 709         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 710                 return;
 711
 712         SIBA_WRITE_MULTI_1(siba, offset, buffer, count);
 713 }
 714
 715 static void
 716 siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer,
 717     size_t count, uint16_t offset)
 718 {
 719         struct siba_softc *siba = sd->sd_bus;
 720
 721         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 722                 return;
 723
 724         KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__));
 725         SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1);
 726 }
 727
 728 static void
 729 siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer,
 730     size_t count, uint16_t offset)
 731 {
 732         struct siba_softc *siba = sd->sd_bus;
 733
 734         if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0)
 735                 return;
 736
 737         KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__));
 738         SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2);
 739 }
 740
 741 void
 742 siba_powerup(device_t dev, int dynamic)
 743 {
 744         struct siba_dev_softc *sd = device_get_ivars(dev);
 745         struct siba_softc *siba = sd->sd_bus;
 746
 747         siba_powerup_sub(siba, dynamic);
 748 }
 749
 750 static void
 751 siba_powerup_sub(struct siba_softc *siba, int dynamic)
 752 {
 753
 754         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1);
 755         siba_cc_clock(&siba->siba_cc,
 756             (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST);
 757 }
 758
 759 static void
 760 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock)
 761 {
 762         struct siba_dev_softc *sd = scc->scc_dev;
 763         struct siba_softc *siba;
 764         uint32_t tmp;
 765
 766         if (sd == NULL)
 767                 return;
 768         siba = sd->sd_bus;
 769         /*
 770          * chipcommon < r6 (no dynamic clock control)
 771          * chipcommon >= r10 (unknown)
 772          */
 773         if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 ||
 774             (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
 775                 return;
 776
 777         switch (clock) {
 778         case SIBA_CLOCK_DYNAMIC:
 779                 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) &
 780                     ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW |
 781                     SIBA_CC_CLKSLOW_IPLL);
 782                 if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL)
 783                         tmp |= SIBA_CC_CLKSLOW_ENXTAL;
 784                 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp);
 785                 if (tmp & SIBA_CC_CLKSLOW_ENXTAL)
 786                         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0);
 787                 break;
 788         case SIBA_CLOCK_SLOW:
 789                 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
 790                     SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
 791                     SIBA_CC_CLKSLOW_FSLOW);
 792                 break;
 793         case SIBA_CLOCK_FAST:
 794                 /* crystal on */
 795                 siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1);
 796                 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
 797                     (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
 798                         SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW);
 799                 break;
 800         default:
 801                 KASSERT(0 == 1,
 802                     ("%s: unsupported clock %#x", __func__, clock));
 803         }
 804 }
 805
 806 uint16_t
 807 siba_read_2(device_t dev, uint16_t offset)
 808 {
 809         struct siba_dev_softc *sd = device_get_ivars(dev);
 810
 811         return (sd->sd_ops->read_2(sd, offset));
 812 }
 813
 814 uint32_t
 815 siba_read_4(device_t dev, uint16_t offset)
 816 {
 817         struct siba_dev_softc *sd = device_get_ivars(dev);
 818
 819         return (siba_read_4_sub(sd, offset));
 820 }
 821
 822 static uint32_t
 823 siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset)
 824 {
 825
 826         return (sd->sd_ops->read_4(sd, offset));
 827 }
 828
 829 void
 830 siba_write_2(device_t dev, uint16_t offset, uint16_t value)
 831 {
 832         struct siba_dev_softc *sd = device_get_ivars(dev);
 833
 834         sd->sd_ops->write_2(sd, offset, value);
 835 }
 836
 837 void
 838 siba_write_4(device_t dev, uint16_t offset, uint32_t value)
 839 {
 840         struct siba_dev_softc *sd = device_get_ivars(dev);
 841
 842         return (siba_write_4_sub(sd, offset, value));
 843 }
 844
 845 static void
 846 siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value)
 847 {
 848
 849         sd->sd_ops->write_4(sd, offset, value);
 850 }
 851
 852 void
 853 siba_read_multi_1(device_t dev, void *buffer, size_t count,
 854     uint16_t offset)
 855 {
 856         struct siba_dev_softc *sd = device_get_ivars(dev);
 857
 858         sd->sd_ops->read_multi_1(sd, buffer, count, offset);
 859 }
 860
 861 void
 862 siba_read_multi_2(device_t dev, void *buffer, size_t count,
 863     uint16_t offset)
 864 {
 865         struct siba_dev_softc *sd = device_get_ivars(dev);
 866
 867         sd->sd_ops->read_multi_2(sd, buffer, count, offset);
 868 }
 869
 870 void
 871 siba_read_multi_4(device_t dev, void *buffer, size_t count,
 872     uint16_t offset)
 873 {
 874         struct siba_dev_softc *sd = device_get_ivars(dev);
 875
 876         sd->sd_ops->read_multi_4(sd, buffer, count, offset);
 877 }
 878
 879 void
 880 siba_write_multi_1(device_t dev, const void *buffer, size_t count,
 881     uint16_t offset)
 882 {
 883         struct siba_dev_softc *sd = device_get_ivars(dev);
 884
 885         sd->sd_ops->write_multi_1(sd, buffer, count, offset);
 886 }
 887
 888 void
 889 siba_write_multi_2(device_t dev, const void *buffer, size_t count,
 890     uint16_t offset)
 891 {
 892         struct siba_dev_softc *sd = device_get_ivars(dev);
 893
 894         sd->sd_ops->write_multi_2(sd, buffer, count, offset);
 895 }
 896
 897 void
 898 siba_write_multi_4(device_t dev, const void *buffer, size_t count,
 899     uint16_t offset)
 900 {
 901         struct siba_dev_softc *sd = device_get_ivars(dev);
 902
 903         sd->sd_ops->write_multi_4(sd, buffer, count, offset);
 904 }
 905
 906 static void
 907 siba_cc_pmu_init(struct siba_cc *scc)
 908 {
 909         const struct siba_cc_pmu_res_updown *updown = NULL;
 910         const struct siba_cc_pmu_res_depend *depend = NULL;
 911         struct siba_dev_softc *sd = scc->scc_dev;
 912         struct siba_softc *siba = sd->sd_bus;
 913         uint32_t min = 0, max = 0, pmucap;
 914         unsigned int i, updown_size, depend_size;
 915
 916         if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0)
 917                 return;
 918
 919         pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS);
 920         scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV);
 921
 922         DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n",
 923             scc->scc_pmu.rev, pmucap);
 924
 925         if (scc->scc_pmu.rev >= 1) {
 926                 if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325)
 927                         SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL,
 928                             ~SIBA_CC_PMUCTL_NOILP);
 929                 else
 930                         SIBA_CC_SET32(scc, SIBA_CC_PMUCTL,
 931                             SIBA_CC_PMUCTL_NOILP);
 932         }
 933
 934         /* initialize PLL & PMU resources */
 935         switch (siba->siba_chipid) {
 936         case 0x4312:
 937                 siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
 938                 /* use the default: min = 0xcbb max = 0x7ffff */
 939                 break;
 940         case 0x4325:
 941                 siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
 942
 943                 updown = siba_cc_pmu_4325_updown;
 944                 updown_size = N(siba_cc_pmu_4325_updown);
 945                 depend = siba_cc_pmu_4325_depend;
 946                 depend_size = N(siba_cc_pmu_4325_depend);
 947
 948                 min = (1 << SIBA_CC_PMU_4325_BURST) |
 949                     (1 << SIBA_CC_PMU_4325_LN);
 950                 if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) &
 951                     SIBA_CC_CHST_4325_PMUTOP_2B)
 952                         min |= (1 << SIBA_CC_PMU_4325_CLBURST);
 953                 max = 0xfffff;
 954                 break;
 955         case 0x4328:
 956                 siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
 957
 958                 updown = siba_cc_pmu_4328_updown;
 959                 updown_size = N(siba_cc_pmu_4328_updown);
 960                 depend = siba_cc_pmu_4328_depend;
 961                 depend_size = N(siba_cc_pmu_4328_depend);
 962
 963                 min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) |
 964                           (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) |
 965                           (1 << SIBA_CC_PMU_4328_CRYSTAL_EN);
 966
 967                 max = 0xfffff;
 968                 break;
 969         case 0x5354:
 970                 siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
 971
 972                 max = 0xfffff;
 973                 break;
 974         default:
 975                 device_printf(siba->siba_dev,
 976                     "unknown chipid %#x for PLL & PMU init\n",
 977                     siba->siba_chipid);
 978         }
 979
 980         if (updown) {
 981                 for (i = 0; i < updown_size; i++) {
 982                         SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
 983                             updown[i].res);
 984                         SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM,
 985                             updown[i].updown);
 986                 }
 987         }
 988         if (depend) {
 989                 for (i = 0; i < depend_size; i++) {
 990                         SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
 991                             depend[i].res);
 992                         switch (depend[i].task) {
 993                         case SIBA_CC_PMU_DEP_SET:
 994                                 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK,
 995                                     depend[i].depend);
 996                                 break;
 997                         case SIBA_CC_PMU_DEP_ADD:
 998                                 SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK,
 999                                     depend[i].depend);
1000                                 break;
1001                         case SIBA_CC_PMU_DEP_REMOVE:
1002                                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK,
1003                                     ~(depend[i].depend));
1004                                 break;
1005                         default:
1006                                 KASSERT(0 == 1,
1007                                     ("%s:%d: assertion failed",
1008                                         __func__, __LINE__));
1009                         }
1010                 }
1011         }
1012
1013         if (min)
1014                 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min);
1015         if (max)
1016                 SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max);
1017 }
1018
1019 static void
1020 siba_cc_power_init(struct siba_cc *scc)
1021 {
1022         struct siba_softc *siba = scc->scc_dev->sd_bus;
1023         int maxfreq;
1024
1025         if (siba->siba_chipid == 0x4321) {
1026                 if (siba->siba_chiprev == 0)
1027                         SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4);
1028                 else if (siba->siba_chiprev == 1)
1029                         SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4);
1030         }
1031
1032         if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
1033                 return;
1034
1035         if (scc->scc_dev->sd_id.sd_rev >= 10)
1036                 SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL,
1037                     (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) &
1038                     0xffff) | 0x40000);
1039         else {
1040                 maxfreq = siba_cc_clockfreq(scc, 1);
1041                 SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY,
1042                     (maxfreq * 150 + 999999) / 1000000);
1043                 SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY,
1044                     (maxfreq * 15 + 999999) / 1000000);
1045         }
1046 }
1047
1048 static void
1049 siba_cc_powerup_delay(struct siba_cc *scc)
1050 {
1051         struct siba_softc *siba = scc->scc_dev->sd_bus;
1052         int min;
1053
1054         if (siba->siba_type != SIBA_TYPE_PCI ||
1055             !(scc->scc_caps & SIBA_CC_CAPS_PWCTL))
1056                 return;
1057
1058         min = siba_cc_clockfreq(scc, 0);
1059         scc->scc_powerup_delay =
1060             (((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000) +
1061             (min - 1)) / min;
1062 }
1063
1064 static int
1065 siba_cc_clockfreq(struct siba_cc *scc, int max)
1066 {
1067         enum siba_clksrc src;
1068         int div = 1, limit = 0;
1069
1070         src = siba_cc_clksrc(scc);
1071         if (scc->scc_dev->sd_id.sd_rev < 6) {
1072                 div = (src == SIBA_CC_CLKSRC_PCI) ? 64 :
1073                     (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1;
1074                 KASSERT(div != 1,
1075                     ("%s: unknown clock %d", __func__, src));
1076         } else if (scc->scc_dev->sd_id.sd_rev < 10) {
1077                 switch (src) {
1078                 case SIBA_CC_CLKSRC_CRYSTAL:
1079                 case SIBA_CC_CLKSRC_PCI:
1080                         div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) +
1081                             1) * 4;
1082                         break;
1083                 case SIBA_CC_CLKSRC_LOWPW:
1084                         break;
1085                 }
1086         } else
1087                 div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4;
1088
1089         switch (src) {
1090         case SIBA_CC_CLKSRC_CRYSTAL:
1091                 limit = (max) ? 20200000 : 19800000;
1092                 break;
1093         case SIBA_CC_CLKSRC_LOWPW:
1094                 limit = (max) ? 43000 : 25000;
1095                 break;
1096         case SIBA_CC_CLKSRC_PCI:
1097                 limit = (max) ? 34000000 : 25000000;
1098                 break;
1099         }
1100
1101         return (limit / div);
1102 }
1103
1104 static void
1105 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq)
1106 {
1107         struct siba_dev_softc *sd = scc->scc_dev;
1108         struct siba_softc *siba = sd->sd_bus;
1109         const struct siba_cc_pmu1_plltab *e = NULL;
1110         uint32_t bufsth = 0, pll, pmu;
1111         unsigned int i;
1112
1113         KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__));
1114         if (siba->siba_chipid == 0x4312) {
1115                 scc->scc_pmu.freq = 20000;
1116                 return;
1117         }
1118
1119         e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ);
1120         KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__));
1121         scc->scc_pmu.freq = e->freq;
1122
1123         pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1124         if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf)
1125                 return;
1126
1127         DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
1128             (e->freq / 1000), (e->freq % 1000));
1129
1130         /* turn PLL off */
1131         switch (siba->siba_chipid) {
1132         case 0x4325:
1133                 bufsth = 0x222222;
1134                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1135                     ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
1136                       (1 << SIBA_CC_PMU_4325_HT)));
1137                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1138                     ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) |
1139                       (1 << SIBA_CC_PMU_4325_HT)));
1140                 break;
1141         default:
1142                 KASSERT(0 == 1,
1143                     ("%s:%d: assertion failed", __func__, __LINE__));
1144         }
1145         for (i = 0; i < 1500; i++) {
1146                 if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) &
1147                       SIBA_CC_CLKCTLSTATUS_HT))
1148                         break;
1149                 DELAY(10);
1150         }
1151         if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT)
1152                 device_printf(siba->siba_dev, "failed to turn PLL off!\n");
1153
1154         pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0);
1155         pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV);
1156         pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV;
1157         pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV;
1158         siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll);
1159
1160         pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2);
1161         pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE);
1162         pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT;
1163         pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE;
1164         siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll);
1165
1166         pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3);
1167         pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC;
1168         pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC;
1169         siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll);
1170
1171         if (bufsth) {
1172                 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5);
1173                 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV;
1174                 pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV;
1175                 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll);
1176         }
1177
1178         pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1179         pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF);
1180         pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) &
1181             SIBA_CC_PMUCTL_ILP;
1182         pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
1183         SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1184 }
1185
1186 static void
1187 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq)
1188 {
1189         struct siba_dev_softc *sd = scc->scc_dev;
1190         struct siba_softc *siba = sd->sd_bus;
1191         const struct siba_cc_pmu0_plltab *e = NULL;
1192         uint32_t pmu, tmp, pll;
1193         unsigned int i;
1194
1195         if ((siba->siba_chipid == 0x5354) && !xtalfreq)
1196                 xtalfreq = 25000;
1197         if (xtalfreq)
1198                 e = siba_cc_pmu0_plltab_findentry(xtalfreq);
1199         if (!e)
1200                 e = siba_cc_pmu0_plltab_findentry(
1201                     SIBA_CC_PMU0_DEFAULT_XTALFREQ);
1202         KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__));
1203         xtalfreq = e->freq;
1204         scc->scc_pmu.freq = e->freq;
1205
1206         pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1207         if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf)
1208                 return;
1209
1210         DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
1211             (xtalfreq / 1000), (xtalfreq % 1000));
1212
1213         KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354,
1214             ("%s:%d: fail", __func__, __LINE__));
1215
1216         switch (siba->siba_chipid) {
1217         case 0x4328:
1218                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1219                     ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
1220                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1221                     ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU));
1222                 break;
1223         case 0x5354:
1224                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1225                     ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
1226                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1227                     ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU));
1228                 break;
1229         }
1230         for (i = 1500; i; i--) {
1231                 tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1232                 if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT))
1233                         break;
1234                 DELAY(10);
1235         }
1236         tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1237         if (tmp & SIBA_CC_CLKCTLSTATUS_HT)
1238                 device_printf(siba->siba_dev, "failed to turn PLL off!\n");
1239
1240         /* set PDIV */
1241         pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0);
1242         if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ)
1243                 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK;
1244         else
1245                 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK;
1246         siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll);
1247
1248         /* set WILD */
1249         pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1);
1250         pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK |
1251             SIBA_CC_PMU0_PLL1_FMSK);
1252         pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK;
1253         pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK;
1254         if (e->wb_frac == 0)
1255                 pll |= SIBA_CC_PMU0_PLL1_STOPMOD;
1256         siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll);
1257
1258         /* set WILD */
1259         pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2);
1260         pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI;
1261         pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI;
1262         siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll);
1263
1264         /* set freq and divisor. */
1265         pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1266         pmu &= ~SIBA_CC_PMUCTL_ILP;
1267         pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP;
1268         pmu &= ~SIBA_CC_PMUCTL_XF;
1269         pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
1270         SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1271 }
1272
1273 static enum siba_clksrc
1274 siba_cc_clksrc(struct siba_cc *scc)
1275 {
1276         struct siba_dev_softc *sd = scc->scc_dev;
1277         struct siba_softc *siba = sd->sd_bus;
1278
1279         if (sd->sd_id.sd_rev < 6) {
1280                 if (siba->siba_type == SIBA_TYPE_PCI) {
1281                         if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) &
1282                             0x10)
1283                                 return (SIBA_CC_CLKSRC_PCI);
1284                         return (SIBA_CC_CLKSRC_CRYSTAL);
1285                 }
1286                 if (siba->siba_type == SIBA_TYPE_SSB ||
1287                     siba->siba_type == SIBA_TYPE_PCMCIA)
1288                         return (SIBA_CC_CLKSRC_CRYSTAL);
1289         }
1290         if (sd->sd_id.sd_rev < 10) {
1291                 switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) {
1292                 case 0:
1293                         return (SIBA_CC_CLKSRC_LOWPW);
1294                 case 1:
1295                         return (SIBA_CC_CLKSRC_CRYSTAL);
1296                 case 2:
1297                         return (SIBA_CC_CLKSRC_PCI);
1298                 default:
1299                         break;
1300                 }
1301         }
1302
1303         return (SIBA_CC_CLKSRC_CRYSTAL);
1304 }
1305
1306 static const struct siba_cc_pmu1_plltab *
1307 siba_cc_pmu1_plltab_find(uint32_t crystalfreq)
1308 {
1309         const struct siba_cc_pmu1_plltab *e;
1310         unsigned int i;
1311
1312         for (i = 0; i < N(siba_cc_pmu1_plltab); i++) {
1313                 e = &siba_cc_pmu1_plltab[i];
1314                 if (crystalfreq == e->freq)
1315                         return (e);
1316         }
1317
1318         return (NULL);
1319 }
1320
1321 static uint32_t
1322 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset)
1323 {
1324
1325         SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1326         return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA));
1327 }
1328
1329 static void
1330 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value)
1331 {
1332
1333         SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1334         SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value);
1335 }
1336
1337 static const struct siba_cc_pmu0_plltab *
1338 siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq)
1339 {
1340         const struct siba_cc_pmu0_plltab *e;
1341         unsigned int i;
1342
1343         for (i = 0; i < N(siba_cc_pmu0_plltab); i++) {
1344                 e = &siba_cc_pmu0_plltab[i];
1345                 if (e->freq == crystalfreq)
1346                         return (e);
1347         }
1348
1349         return (NULL);
1350 }
1351
1352 static int
1353 siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom)
1354 {
1355         int error = ENOMEM;
1356         uint16_t *buf;
1357
1358         buf = malloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t),
1359             M_DEVBUF, M_NOWAIT | M_ZERO);
1360         if (buf == NULL)
1361                 return (ENOMEM);
1362         siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123);
1363         error = sprom_check_crc(buf, siba->siba_spromsize);
1364         if (error) {
1365                 free(buf, M_DEVBUF);
1366                 buf = malloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t),
1367                     M_DEVBUF, M_NOWAIT | M_ZERO);
1368                 if (buf == NULL)
1369                         return (ENOMEM);
1370                 siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4);
1371                 error = sprom_check_crc(buf, siba->siba_spromsize);
1372                 if (error)
1373                         device_printf(siba->siba_dev, "warn: bad SPROM CRC\n");
1374         }
1375
1376         bzero(sprom, sizeof(*sprom));
1377
1378         sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF;
1379         DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n",
1380             sprom->rev);
1381         memset(sprom->mac_eth, 0xff, 6);
1382         memset(sprom->mac_80211a, 0xff, 6);
1383         if ((siba->siba_chipid & 0xff00) == 0x4400) {
1384                 sprom->rev = 1;
1385                 siba_sprom_r123(sprom, buf);
1386         } else if (siba->siba_chipid == 0x4321) {
1387                 sprom->rev = 4;
1388                 siba_sprom_r45(sprom, buf);
1389         } else {
1390                 switch (sprom->rev) {
1391                 case 1:
1392                 case 2:
1393                 case 3:
1394                         siba_sprom_r123(sprom, buf);
1395                         break;
1396                 case 4:
1397                 case 5:
1398                         siba_sprom_r45(sprom, buf);
1399                         break;
1400                 case 8:
1401                         siba_sprom_r8(sprom, buf);
1402                         break;
1403                 default:
1404                         device_printf(siba->siba_dev,
1405                             "unknown SPROM revision %d.\n", sprom->rev);
1406                         siba_sprom_r123(sprom, buf);
1407                 }
1408         }
1409
1410         if (sprom->bf_lo == 0xffff)
1411                 sprom->bf_lo = 0;
1412         if (sprom->bf_hi == 0xffff)
1413                 sprom->bf_hi = 0;
1414
1415         free(buf, M_DEVBUF);
1416         return (error);
1417 }
1418
1419 static int
1420 siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len)
1421 {
1422         int i;
1423
1424         for (i = 0; i < len; i++)
1425                 sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2));
1426
1427         siba->siba_spromsize = len;
1428         return (0);
1429 }
1430
1431 static int
1432 sprom_check_crc(const uint16_t *sprom, size_t size)
1433 {
1434         int word;
1435         uint8_t crc0, crc1 = 0xff;
1436
1437         crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8;
1438         for (word = 0; word < size - 1; word++) {
1439                 crc1 = siba_crc8(crc1, sprom[word] & 0x00ff);
1440                 crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8);
1441         }
1442         crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff);
1443         crc1 ^= 0xff;
1444
1445         return ((crc0 != crc1) ? EPROTO : 0);
1446 }
1447
1448 static uint8_t
1449 siba_crc8(uint8_t crc, uint8_t data)
1450 {
1451         static const uint8_t ct[] = {
1452                 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b,
1453                 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21,
1454                 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff,
1455                 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5,
1456                 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14,
1457                 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e,
1458                 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80,
1459                 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca,
1460                 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95,
1461                 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf,
1462                 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01,
1463                 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b,
1464                 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea,
1465                 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0,
1466                 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e,
1467                 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34,
1468                 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0,
1469                 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a,
1470                 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54,
1471                 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e,
1472                 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf,
1473                 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5,
1474                 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b,
1475                 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61,
1476                 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e,
1477                 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74,
1478                 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa,
1479                 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0,
1480                 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41,
1481                 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b,
1482                 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5,
1483                 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f,
1484         };
1485         return (ct[crc ^ data]);
1486 }
1487
1488 #define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
1489 #define SIBA_OFFSET(offset)     \
1490         (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t))
1491 #define SIBA_SHIFTOUT_SUB(__x, __mask)                                  \
1492         (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask))
1493 #define SIBA_SHIFTOUT(_var, _offset, _mask)                             \
1494         out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask))
1495 #define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift)                   \
1496         out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 |   \
1497             in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift))
1498
1499 static void
1500 siba_sprom_r123(struct siba_sprom *out, const uint16_t *in)
1501 {
1502         int i;
1503         uint16_t v;
1504         int8_t gain;
1505         uint16_t loc[3];
1506
1507         if (out->rev == 3)
1508                 loc[0] = SIBA_SPROM3_MAC_80211BG;
1509         else {
1510                 loc[0] = SIBA_SPROM1_MAC_80211BG;
1511                 loc[1] = SIBA_SPROM1_MAC_ETH;
1512                 loc[2] = SIBA_SPROM1_MAC_80211A;
1513         }
1514         for (i = 0; i < 3; i++) {
1515                 v = in[SIBA_OFFSET(loc[0]) + i];
1516                 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1517         }
1518         if (out->rev < 3) {
1519                 for (i = 0; i < 3; i++) {
1520                         v = in[SIBA_OFFSET(loc[1]) + i];
1521                         *(((uint16_t *)out->mac_eth) + i) = htobe16(v);
1522                 }
1523                 for (i = 0; i < 3; i++) {
1524                         v = in[SIBA_OFFSET(loc[2]) + i];
1525                         *(((uint16_t *)out->mac_80211a) + i) = htobe16(v);
1526                 }
1527         }
1528         SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY,
1529             SIBA_SPROM1_ETHPHY_MII_ETH0);
1530         SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY,
1531             SIBA_SPROM1_ETHPHY_MII_ETH1);
1532         SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY,
1533             SIBA_SPROM1_ETHPHY_MDIO_ETH0);
1534         SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY,
1535             SIBA_SPROM1_ETHPHY_MDIO_ETH1);
1536         SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV);
1537         SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO,
1538             SIBA_SPROM1_BOARDINFO_CCODE);
1539         SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA);
1540         SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO,
1541             SIBA_SPROM1_BOARDINFO_ANTBG);
1542         SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff);
1543         SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff);
1544         SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff);
1545         SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff);
1546         SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff);
1547         SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff);
1548         SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0);
1549         SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1);
1550         SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2);
1551         SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3);
1552
1553         SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A);
1554         SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG);
1555         SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A);
1556         SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG);
1557         SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff);
1558         if (out->rev >= 2)
1559                 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff);
1560
1561         /* antenna gain */
1562         gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0);
1563         out->again.ghz24.a0 = out->again.ghz24.a1 = gain;
1564         out->again.ghz24.a2 = out->again.ghz24.a3 = gain;
1565         gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8);
1566         out->again.ghz5.a0 = out->again.ghz5.a1 = gain;
1567         out->again.ghz5.a2 = out->again.ghz5.a3 = gain;
1568 }
1569
1570 static void
1571 siba_sprom_r45(struct siba_sprom *out, const uint16_t *in)
1572 {
1573         int i;
1574         uint16_t v;
1575         uint16_t mac_80211bg_offset;
1576
1577         if (out->rev == 4)
1578                 mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG;
1579         else
1580                 mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG;
1581         for (i = 0; i < 3; i++) {
1582                 v = in[SIBA_OFFSET(mac_80211bg_offset) + i];
1583                 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1584         }
1585         SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A);
1586         SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A);
1587         if (out->rev == 4) {
1588                 SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff);
1589                 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff);
1590                 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff);
1591         } else {
1592                 SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff);
1593                 SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff);
1594                 SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff);
1595         }
1596         SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A);
1597         SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG);
1598         SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK);
1599         SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG);
1600         SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK);
1601         SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A);
1602         if (out->rev == 4) {
1603                 SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0);
1604                 SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1);
1605                 SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2);
1606                 SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3);
1607         } else {
1608                 SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0);
1609                 SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1);
1610                 SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2);
1611                 SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3);
1612         }
1613
1614         /* antenna gain */
1615         SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0);
1616         SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1);
1617         SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2);
1618         SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3);
1619         bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
1620 }
1621
1622 static void
1623 siba_sprom_r8(struct siba_sprom *out, const uint16_t *in)
1624 {
1625         int i;
1626         uint16_t v;
1627
1628         for (i = 0; i < 3; i++) {
1629                 v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i];
1630                 *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v);
1631         }
1632         SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff);
1633         SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff);
1634         SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff);
1635         SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff);
1636         SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff);
1637         SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A);
1638         SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG);
1639         SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK);
1640         SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG);
1641         SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK);
1642         SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A);
1643         SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL,
1644             SIBA_SPROM8_MAXP_AH_MASK);
1645         SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL,
1646             SIBA_SPROM8_MAXP_AL_MASK);
1647         SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0);
1648         SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1);
1649         SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2);
1650         SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3);
1651         SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G);
1652         SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G);
1653         SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL);
1654         SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH);
1655         SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G);
1656         SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G);
1657         SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G);
1658         SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G);
1659         SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G);
1660         SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G);
1661         SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G);
1662         SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G);
1663         SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G);
1664         SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G);
1665
1666         SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff);
1667         SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff);
1668         SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff);
1669         SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff);
1670         SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff);
1671         SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff);
1672         SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff);
1673         SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff);
1674         SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff);
1675         SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff);
1676         SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff);
1677         SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff);
1678         SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff);
1679
1680         SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0);
1681         SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0);
1682         SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0);
1683         SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0);
1684
1685         /* antenna gain */
1686         SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0);
1687         SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1);
1688         SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2);
1689         SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3);
1690         bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5));
1691 }
1692
1693 static int8_t
1694 siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in,
1695     uint16_t mask, uint16_t shift)
1696 {
1697         uint16_t v;
1698         uint8_t gain;
1699
1700         v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)];
1701         gain = (v & mask) >> shift;
1702         gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 :
1703             ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2);
1704
1705         return ((int8_t)gain);
1706 }
1707
1708 #undef SIBA_LOWEST_SET_BIT
1709 #undef SIBA_OFFSET
1710 #undef SIBA_SHIFTOUT_SUB
1711 #undef SIBA_SHIFTOUT
1712
1713 int
1714 siba_powerdown(device_t dev)
1715 {
1716         struct siba_dev_softc *sd = device_get_ivars(dev);
1717         struct siba_softc *siba = sd->sd_bus;
1718
1719         return (siba_powerdown_sub(siba));
1720 }
1721
1722 static int
1723 siba_powerdown_sub(struct siba_softc *siba)
1724 {
1725         struct siba_cc *scc;
1726
1727         if (siba->siba_type == SIBA_TYPE_SSB)
1728                 return (0);
1729
1730         scc = &siba->siba_cc;
1731         if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5)
1732                 return (0);
1733         siba_cc_clock(scc, SIBA_CLOCK_SLOW);
1734         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
1735         return (0);
1736 }
1737
1738 static void
1739 siba_pcicore_init(struct siba_pci *spc)
1740 {
1741         struct siba_dev_softc *sd = spc->spc_dev;
1742
1743         if (sd == NULL)
1744                 return;
1745
1746         if (!siba_dev_isup_sub(sd))
1747                 siba_dev_up_sub(sd, 0);
1748
1749         KASSERT(spc->spc_hostmode == 0,
1750             ("%s:%d: hostmode", __func__, __LINE__));
1751         /* disable PCI interrupt */
1752         siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0);
1753 }
1754
1755 int
1756 siba_dev_isup(device_t dev)
1757 {
1758         struct siba_dev_softc *sd = device_get_ivars(dev);
1759
1760         return (siba_dev_isup_sub(sd));
1761 }
1762
1763 static int
1764 siba_dev_isup_sub(struct siba_dev_softc *sd)
1765 {
1766         uint32_t reject, val;
1767
1768         reject = siba_tmslow_reject_bitmask(sd);
1769         val = siba_read_4_sub(sd, SIBA_TGSLOW);
1770         val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject;
1771
1772         return (val == SIBA_TGSLOW_CLOCK);
1773 }
1774
1775 void
1776 siba_dev_up(device_t dev, uint32_t flags)
1777 {
1778         struct siba_dev_softc *sd = device_get_ivars(dev);
1779
1780         siba_dev_up_sub(sd, flags);
1781 }
1782
1783 static void
1784 siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags)
1785 {
1786         uint32_t val;
1787
1788         siba_dev_down_sub(sd, flags);
1789         siba_write_4_sub(sd, SIBA_TGSLOW,
1790             SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
1791         siba_read_4_sub(sd, SIBA_TGSLOW);
1792         DELAY(1);
1793
1794         if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR)
1795                 siba_write_4_sub(sd, SIBA_TGSHIGH, 0);
1796
1797         val = siba_read_4_sub(sd, SIBA_IAS);
1798         if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) {
1799                 val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT);
1800                 siba_write_4_sub(sd, SIBA_IAS, val);
1801         }
1802
1803         siba_write_4_sub(sd, SIBA_TGSLOW,
1804             SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags);
1805         siba_read_4_sub(sd, SIBA_TGSLOW);
1806         DELAY(1);
1807
1808         siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags);
1809         siba_read_4_sub(sd, SIBA_TGSLOW);
1810         DELAY(1);
1811 }
1812
1813 static uint32_t
1814 siba_tmslow_reject_bitmask(struct siba_dev_softc *sd)
1815 {
1816         uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV;
1817
1818         switch (rev) {
1819         case SIBA_IDLOW_SSBREV_22:
1820                 return (SIBA_TGSLOW_REJECT_22);
1821         case SIBA_IDLOW_SSBREV_23:
1822                 return (SIBA_TGSLOW_REJECT_23);
1823         case SIBA_IDLOW_SSBREV_24:
1824         case SIBA_IDLOW_SSBREV_25:
1825         case SIBA_IDLOW_SSBREV_26:
1826         case SIBA_IDLOW_SSBREV_27:
1827                 return (SIBA_TGSLOW_REJECT_23);
1828         default:
1829                 KASSERT(0 == 1,
1830                     ("%s:%d: unknown backplane rev %#x\n",
1831                         __func__, __LINE__, rev));
1832         }
1833         return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23);
1834 }
1835
1836 void
1837 siba_dev_down(device_t dev, uint32_t flags)
1838 {
1839         struct siba_dev_softc *sd = device_get_ivars(dev);
1840
1841         siba_dev_down_sub(sd, flags);
1842 }
1843
1844 static void
1845 siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags)
1846 {
1847         struct siba_softc *siba = sd->sd_bus;
1848         uint32_t reject, val;
1849         int i;
1850
1851         if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET)
1852                 return;
1853
1854         reject = siba_tmslow_reject_bitmask(sd);
1855         siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK);
1856
1857         for (i = 0; i < 1000; i++) {
1858                 val = siba_read_4_sub(sd, SIBA_TGSLOW);
1859                 if (val & reject)
1860                         break;
1861                 DELAY(10);
1862         }
1863         if ((val & reject) == 0) {
1864                 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
1865                     reject, SIBA_TGSLOW);
1866         }
1867         for (i = 0; i < 1000; i++) {
1868                 val = siba_read_4_sub(sd, SIBA_TGSHIGH);
1869                 if (!(val & SIBA_TGSHIGH_BUSY))
1870                         break;
1871                 DELAY(10);
1872         }
1873         if ((val & SIBA_TGSHIGH_BUSY) != 0) {
1874                 device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n",
1875                     SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH);
1876         }
1877
1878         siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK |
1879             reject | SIBA_TGSLOW_RESET | flags);
1880         siba_read_4_sub(sd, SIBA_TGSLOW);
1881         DELAY(1);
1882         siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags);
1883         siba_read_4_sub(sd, SIBA_TGSLOW);
1884         DELAY(1);
1885 }
1886
1887 static void
1888 siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd)
1889 {
1890         struct siba_dev_softc *psd = spc->spc_dev;
1891         struct siba_softc *siba = psd->sd_bus;
1892         uint32_t tmp;
1893
1894         if (psd->sd_id.sd_device == SIBA_DEVID_PCI) {
1895                 siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2,
1896                     siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) |
1897                     SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST);
1898
1899                 if (psd->sd_id.sd_rev < 5) {
1900                         tmp = siba_read_4_sub(psd, SIBA_IMCFGLO);
1901                         tmp &= ~SIBA_IMCFGLO_SERTO;
1902                         tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO;
1903                         tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */;
1904                         siba_write_4_sub(psd, SIBA_IMCFGLO, tmp);
1905
1906                         /* broadcast value */
1907                         sd = (siba->siba_cc.scc_dev != NULL) ?
1908                             siba->siba_cc.scc_dev : siba->siba_pci.spc_dev;
1909                         if (sd != NULL) {
1910                                 siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR,
1911                                     0xfd8);
1912                                 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR);
1913                                 siba_write_4_sub(sd,
1914                                     SIBA_PCICORE_BCAST_DATA, 0);
1915                                 siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA);
1916                         }
1917                 } else if (psd->sd_id.sd_rev >= 11) {
1918                         tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2);
1919                         tmp |= SIBA_PCICORE_SBTOPCI_MRM;
1920                         siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp);
1921                 }
1922         } else {
1923                 KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE"));
1924                 if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1))
1925                         siba_pcie_write(spc, 0x4,
1926                             siba_pcie_read(spc, 0x4) | 0x8);
1927                 if (psd->sd_id.sd_rev == 0) {
1928                         siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */
1929                         siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */
1930                         siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */
1931                 } else if (psd->sd_id.sd_rev == 1)
1932                         siba_pcie_write(spc, 0x100,
1933                             siba_pcie_read(spc, 0x100) | 0x40);
1934         }
1935         spc->spc_inited = 1;
1936 }
1937
1938 void
1939 siba_pcicore_intr(device_t dev)
1940 {
1941         struct siba_dev_softc *sd = device_get_ivars(dev);
1942         struct siba_softc *siba = sd->sd_bus;
1943         struct siba_pci *spc = &siba->siba_pci;
1944         struct siba_dev_softc *psd = spc->spc_dev;
1945         uint32_t tmp;
1946
1947         if (siba->siba_type != SIBA_TYPE_PCI || !psd)
1948                 return;
1949
1950         KASSERT(siba == psd->sd_bus, ("different pointers"));
1951
1952         /* enable interrupts */
1953         if (siba->siba_dev != NULL &&
1954             (psd->sd_id.sd_rev >= 6 ||
1955              psd->sd_id.sd_device == SIBA_DEVID_PCIE)) {
1956                 tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4);
1957                 tmp |= (1 << sd->sd_coreidx) << 8;
1958                 pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4);
1959         } else {
1960                 tmp = siba_read_4_sub(sd, SIBA_TPS);
1961                 tmp &= SIBA_TPS_BPFLAG;
1962                 siba_write_4_sub(psd, SIBA_INTR_MASK,
1963                     siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp));
1964         }
1965
1966         /* setup PCIcore */
1967         if (spc->spc_inited == 0)
1968                 siba_pcicore_setup(spc, sd);
1969 }
1970
1971 static uint32_t
1972 siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset)
1973 {
1974
1975         return (siba_read_4_sub(spc->spc_dev, offset));
1976 }
1977
1978 static void
1979 siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value)
1980 {
1981
1982         siba_write_4_sub(spc->spc_dev, offset, value);
1983 }
1984
1985 static uint32_t
1986 siba_pcie_read(struct siba_pci *spc, uint32_t address)
1987 {
1988
1989         siba_pcicore_write_4(spc, 0x130, address);
1990         return (siba_pcicore_read_4(spc, 0x134));
1991 }
1992
1993 static void
1994 siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data)
1995 {
1996
1997         siba_pcicore_write_4(spc, 0x130, address);
1998         siba_pcicore_write_4(spc, 0x134, data);
1999 }
2000
2001 static void
2002 siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address,
2003     uint16_t data)
2004 {
2005         int i;
2006
2007         siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2);
2008         siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA,
2009             (1 << 30) | (1 << 28) |
2010             ((uint32_t)device << 22) | ((uint32_t)address << 18) |
2011             (1 << 17) | data);
2012         DELAY(10);
2013         for (i = 0; i < 10; i++) {
2014                 if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100)
2015                         break;
2016                 DELAY(1000);
2017         }
2018         siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0);
2019 }
2020
2021 uint32_t
2022 siba_dma_translation(device_t dev)
2023 {
2024 #ifdef INVARIANTS
2025         struct siba_dev_softc *sd = device_get_ivars(dev);
2026         struct siba_softc *siba = sd->sd_bus;
2027
2028         KASSERT(siba->siba_type == SIBA_TYPE_PCI,
2029             ("unsupported bustype %d\n", siba->siba_type));
2030 #endif
2031         return (SIBA_PCI_DMA);
2032 }
2033
2034 void
2035 siba_barrier(device_t dev, int flags)
2036 {
2037         struct siba_dev_softc *sd = device_get_ivars(dev);
2038         struct siba_softc *siba = sd->sd_bus;
2039
2040         SIBA_BARRIER(siba, flags);
2041 }
2042
2043 static void
2044 siba_cc_suspend(struct siba_cc *scc)
2045 {
2046
2047         siba_cc_clock(scc, SIBA_CLOCK_SLOW);
2048 }
2049
2050 static void
2051 siba_cc_resume(struct siba_cc *scc)
2052 {
2053
2054         siba_cc_power_init(scc);
2055         siba_cc_clock(scc, SIBA_CLOCK_FAST);
2056 }
2057
2058 int
2059 siba_core_suspend(struct siba_softc *siba)
2060 {
2061
2062         siba_cc_suspend(&siba->siba_cc);
2063         siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0);
2064         return (0);
2065 }
2066
2067 int
2068 siba_core_resume(struct siba_softc *siba)
2069 {
2070
2071         siba->siba_pci.spc_inited = 0;
2072         siba->siba_curdev = NULL;
2073
2074         siba_powerup_sub(siba, 0);
2075         /* XXX setup H/W for PCMCIA??? */
2076         siba_cc_resume(&siba->siba_cc);
2077         siba_powerdown_sub(siba);
2078
2079         return (0);
2080 }
2081
2082 static void
2083 siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask,
2084     uint32_t set)
2085 {
2086
2087         SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
2088         SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset);
2089         SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR);
2090         SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA,
2091             (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set);
2092         SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA);
2093 }
2094
2095 void
2096 siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt)
2097 {
2098         struct siba_dev_softc *sd = device_get_ivars(dev);
2099         struct siba_softc *siba = sd->sd_bus;
2100         struct siba_cc *scc = &siba->siba_cc;
2101         uint32_t *p = NULL, info[5][3] = {
2102                 { 2, 25,  0xf },
2103                 { 3,  1,  0xf },
2104                 { 3,  9,  0xf },
2105                 { 3, 17, 0x3f },
2106                 { 0, 21, 0x3f }
2107         };
2108
2109         if (siba->siba_chipid == 0x4312) {
2110                 if (id != SIBA_LDO_PAREF)
2111                         return;
2112                 p = info[4];
2113                 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2114                     (volt & p[2]) << p[1]);
2115                 return;
2116         }
2117         if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) {
2118                 switch (id) {
2119                 case SIBA_LDO_PAREF:
2120                         p = info[3];
2121                         break;
2122                 case SIBA_LDO_VOLT1:
2123                         p = info[0];
2124                         break;
2125                 case SIBA_LDO_VOLT2:
2126                         p = info[1];
2127                         break;
2128                 case SIBA_LDO_VOLT3:
2129                         p = info[2];
2130                         break;
2131                 default:
2132                         KASSERT(0 == 1,
2133                             ("%s: unsupported voltage ID %#x", __func__, id));
2134                         return;
2135                 }
2136                 siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2137                     (volt & p[2]) << p[1]);
2138         }
2139 }
2140
2141 void
2142 siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on)
2143 {
2144         struct siba_dev_softc *sd = device_get_ivars(dev);
2145         struct siba_softc *siba = sd->sd_bus;
2146         struct siba_cc *scc = &siba->siba_cc;
2147         int ldo;
2148
2149         ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF :
2150             ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF :
2151             ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1)));
2152         if (ldo == -1)
2153                 return;
2154
2155         if (on)
2156                 SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo);
2157         else
2158                 SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo));
2159         SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES);
2160 }
2161
2162 int
2163 siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result)
2164 {
2165         struct siba_dev_softc *sd = device_get_ivars(child);
2166         struct siba_softc *siba = sd->sd_bus;
2167
2168         switch (which) {
2169         case SIBA_SPROMVAR_REV:
2170                 *result = siba->siba_sprom.rev;
2171                 break;
2172         case SIBA_SPROMVAR_MAC_80211BG:
2173                 *((uint8_t **) result) = siba->siba_sprom.mac_80211bg;
2174                 break;
2175         case SIBA_SPROMVAR_MAC_ETH:
2176                 *((uint8_t **) result) = siba->siba_sprom.mac_eth;
2177                 break;
2178         case SIBA_SPROMVAR_MAC_80211A:
2179                 *((uint8_t **) result) = siba->siba_sprom.mac_80211a;
2180                 break;
2181         case SIBA_SPROMVAR_MII_ETH0:
2182                 *result = siba->siba_sprom.mii_eth0;
2183                 break;
2184         case SIBA_SPROMVAR_MII_ETH1:
2185                 *result = siba->siba_sprom.mii_eth1;
2186                 break;
2187         case SIBA_SPROMVAR_MDIO_ETH0:
2188                 *result = siba->siba_sprom.mdio_eth0;
2189                 break;
2190         case SIBA_SPROMVAR_MDIO_ETH1:
2191                 *result = siba->siba_sprom.mdio_eth1;
2192                 break;
2193         case SIBA_SPROMVAR_BREV:
2194                 *result = siba->siba_sprom.brev;
2195                 break;
2196         case SIBA_SPROMVAR_CCODE:
2197                 *result = siba->siba_sprom.ccode;
2198                 break;
2199         case SIBA_SPROMVAR_ANT_A:
2200                 *result = siba->siba_sprom.ant_a;
2201                 break;
2202         case SIBA_SPROMVAR_ANT_BG:
2203                 *result = siba->siba_sprom.ant_bg;
2204                 break;
2205         case SIBA_SPROMVAR_PA0B0:
2206                 *result = siba->siba_sprom.pa0b0;
2207                 break;
2208         case SIBA_SPROMVAR_PA0B1:
2209                 *result = siba->siba_sprom.pa0b1;
2210                 break;
2211         case SIBA_SPROMVAR_PA0B2:
2212                 *result = siba->siba_sprom.pa0b2;
2213                 break;
2214         case SIBA_SPROMVAR_PA1B0:
2215                 *result = siba->siba_sprom.pa1b0;
2216                 break;
2217         case SIBA_SPROMVAR_PA1B1:
2218                 *result = siba->siba_sprom.pa1b1;
2219                 break;
2220         case SIBA_SPROMVAR_PA1B2:
2221                 *result = siba->siba_sprom.pa1b2;
2222                 break;
2223         case SIBA_SPROMVAR_PA1LOB0:
2224                 *result = siba->siba_sprom.pa1lob0;
2225                 break;
2226         case SIBA_SPROMVAR_PA1LOB1:
2227                 *result = siba->siba_sprom.pa1lob1;
2228                 break;
2229         case SIBA_SPROMVAR_PA1LOB2:
2230                 *result = siba->siba_sprom.pa1lob2;
2231                 break;
2232         case SIBA_SPROMVAR_PA1HIB0:
2233                 *result = siba->siba_sprom.pa1hib0;
2234                 break;
2235         case SIBA_SPROMVAR_PA1HIB1:
2236                 *result = siba->siba_sprom.pa1hib1;
2237                 break;
2238         case SIBA_SPROMVAR_PA1HIB2:
2239                 *result = siba->siba_sprom.pa1hib2;
2240                 break;
2241         case SIBA_SPROMVAR_GPIO0:
2242                 *result = siba->siba_sprom.gpio0;
2243                 break;
2244         case SIBA_SPROMVAR_GPIO1:
2245                 *result = siba->siba_sprom.gpio1;
2246                 break;
2247         case SIBA_SPROMVAR_GPIO2:
2248                 *result = siba->siba_sprom.gpio2;
2249                 break;
2250         case SIBA_SPROMVAR_GPIO3:
2251                 *result = siba->siba_sprom.gpio3;
2252                 break;
2253         case SIBA_SPROMVAR_MAXPWR_AL:
2254                 *result = siba->siba_sprom.maxpwr_al;
2255                 break;
2256         case SIBA_SPROMVAR_MAXPWR_A:
2257                 *result = siba->siba_sprom.maxpwr_a;
2258                 break;
2259         case SIBA_SPROMVAR_MAXPWR_AH:
2260                 *result = siba->siba_sprom.maxpwr_ah;
2261                 break;
2262         case SIBA_SPROMVAR_MAXPWR_BG:
2263                 *result = siba->siba_sprom.maxpwr_bg;
2264                 break;
2265         case SIBA_SPROMVAR_RXPO2G:
2266                 *result = siba->siba_sprom.rxpo2g;
2267                 break;
2268         case SIBA_SPROMVAR_RXPO5G:
2269                 *result = siba->siba_sprom.rxpo5g;
2270                 break;
2271         case SIBA_SPROMVAR_TSSI_A:
2272                 *result = siba->siba_sprom.tssi_a;
2273                 break;
2274         case SIBA_SPROMVAR_TSSI_BG:
2275                 *result = siba->siba_sprom.tssi_bg;
2276                 break;
2277         case SIBA_SPROMVAR_TRI2G:
2278                 *result = siba->siba_sprom.tri2g;
2279                 break;
2280         case SIBA_SPROMVAR_TRI5GL:
2281                 *result = siba->siba_sprom.tri5gl;
2282                 break;
2283         case SIBA_SPROMVAR_TRI5G:
2284                 *result = siba->siba_sprom.tri5g;
2285                 break;
2286         case SIBA_SPROMVAR_TRI5GH:
2287                 *result = siba->siba_sprom.tri5gh;
2288                 break;
2289         case SIBA_SPROMVAR_RSSISAV2G:
2290                 *result = siba->siba_sprom.rssisav2g;
2291                 break;
2292         case SIBA_SPROMVAR_RSSISMC2G:
2293                 *result = siba->siba_sprom.rssismc2g;
2294                 break;
2295         case SIBA_SPROMVAR_RSSISMF2G:
2296                 *result = siba->siba_sprom.rssismf2g;
2297                 break;
2298         case SIBA_SPROMVAR_BXA2G:
2299                 *result = siba->siba_sprom.bxa2g;
2300                 break;
2301         case SIBA_SPROMVAR_RSSISAV5G:
2302                 *result = siba->siba_sprom.rssisav5g;
2303                 break;
2304         case SIBA_SPROMVAR_RSSISMC5G:
2305                 *result = siba->siba_sprom.rssismc5g;
2306                 break;
2307         case SIBA_SPROMVAR_RSSISMF5G:
2308                 *result = siba->siba_sprom.rssismf5g;
2309                 break;
2310         case SIBA_SPROMVAR_BXA5G:
2311                 *result = siba->siba_sprom.bxa5g;
2312                 break;
2313         case SIBA_SPROMVAR_CCK2GPO:
2314                 *result = siba->siba_sprom.cck2gpo;
2315                 break;
2316         case SIBA_SPROMVAR_OFDM2GPO:
2317                 *result = siba->siba_sprom.ofdm2gpo;
2318                 break;
2319         case SIBA_SPROMVAR_OFDM5GLPO:
2320                 *result = siba->siba_sprom.ofdm5glpo;
2321                 break;
2322         case SIBA_SPROMVAR_OFDM5GPO:
2323                 *result = siba->siba_sprom.ofdm5gpo;
2324                 break;
2325         case SIBA_SPROMVAR_OFDM5GHPO:
2326                 *result = siba->siba_sprom.ofdm5ghpo;
2327                 break;
2328         case SIBA_SPROMVAR_BF_LO:
2329                 *result = siba->siba_sprom.bf_lo;
2330                 break;
2331         case SIBA_SPROMVAR_BF_HI:
2332                 *result = siba->siba_sprom.bf_hi;
2333                 break;
2334         case SIBA_SPROMVAR_BF2_LO:
2335                 *result = siba->siba_sprom.bf2_lo;
2336                 break;
2337         case SIBA_SPROMVAR_BF2_HI:
2338                 *result = siba->siba_sprom.bf2_hi;
2339                 break;
2340         default:
2341                 return (ENOENT);
2342         }
2343         return (0);
2344 }
2345
2346 int
2347 siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value)
2348 {
2349         struct siba_dev_softc *sd = device_get_ivars(child);
2350         struct siba_softc *siba = sd->sd_bus;
2351
2352         switch (which) {
2353         case SIBA_SPROMVAR_REV:
2354                 siba->siba_sprom.rev = value;
2355                 break;
2356         case SIBA_SPROMVAR_MII_ETH0:
2357                 siba->siba_sprom.mii_eth0 = value;
2358                 break;
2359         case SIBA_SPROMVAR_MII_ETH1:
2360                 siba->siba_sprom.mii_eth1 = value;
2361                 break;
2362         case SIBA_SPROMVAR_MDIO_ETH0:
2363                 siba->siba_sprom.mdio_eth0 = value;
2364                 break;
2365         case SIBA_SPROMVAR_MDIO_ETH1:
2366                 siba->siba_sprom.mdio_eth1 = value;
2367                 break;
2368         case SIBA_SPROMVAR_BREV:
2369                 siba->siba_sprom.brev = value;
2370                 break;
2371         case SIBA_SPROMVAR_CCODE:
2372                 siba->siba_sprom.ccode = value;
2373                 break;
2374         case SIBA_SPROMVAR_ANT_A:
2375                 siba->siba_sprom.ant_a = value;
2376                 break;
2377         case SIBA_SPROMVAR_ANT_BG:
2378                 siba->siba_sprom.ant_bg = value;
2379                 break;
2380         case SIBA_SPROMVAR_PA0B0:
2381                 siba->siba_sprom.pa0b0 = value;
2382                 break;
2383         case SIBA_SPROMVAR_PA0B1:
2384                 siba->siba_sprom.pa0b1 = value;
2385                 break;
2386         case SIBA_SPROMVAR_PA0B2:
2387                 siba->siba_sprom.pa0b2 = value;
2388                 break;
2389         case SIBA_SPROMVAR_PA1B0:
2390                 siba->siba_sprom.pa1b0 = value;
2391                 break;
2392         case SIBA_SPROMVAR_PA1B1:
2393                 siba->siba_sprom.pa1b1 = value;
2394                 break;
2395         case SIBA_SPROMVAR_PA1B2:
2396                 siba->siba_sprom.pa1b2 = value;
2397                 break;
2398         case SIBA_SPROMVAR_PA1LOB0:
2399                 siba->siba_sprom.pa1lob0 = value;
2400                 break;
2401         case SIBA_SPROMVAR_PA1LOB1:
2402                 siba->siba_sprom.pa1lob1 = value;
2403                 break;
2404         case SIBA_SPROMVAR_PA1LOB2:
2405                 siba->siba_sprom.pa1lob2 = value;
2406                 break;
2407         case SIBA_SPROMVAR_PA1HIB0:
2408                 siba->siba_sprom.pa1hib0 = value;
2409                 break;
2410         case SIBA_SPROMVAR_PA1HIB1:
2411                 siba->siba_sprom.pa1hib1 = value;
2412                 break;
2413         case SIBA_SPROMVAR_PA1HIB2:
2414                 siba->siba_sprom.pa1hib2 = value;
2415                 break;
2416         case SIBA_SPROMVAR_GPIO0:
2417                 siba->siba_sprom.gpio0 = value;
2418                 break;
2419         case SIBA_SPROMVAR_GPIO1:
2420                 siba->siba_sprom.gpio1 = value;
2421                 break;
2422         case SIBA_SPROMVAR_GPIO2:
2423                 siba->siba_sprom.gpio2 = value;
2424                 break;
2425         case SIBA_SPROMVAR_GPIO3:
2426                 siba->siba_sprom.gpio3 = value;
2427                 break;
2428         case SIBA_SPROMVAR_MAXPWR_AL:
2429                 siba->siba_sprom.maxpwr_al = value;
2430                 break;
2431         case SIBA_SPROMVAR_MAXPWR_A:
2432                 siba->siba_sprom.maxpwr_a = value;
2433                 break;
2434         case SIBA_SPROMVAR_MAXPWR_AH:
2435                 siba->siba_sprom.maxpwr_ah = value;
2436                 break;
2437         case SIBA_SPROMVAR_MAXPWR_BG:
2438                 siba->siba_sprom.maxpwr_bg = value;
2439                 break;
2440         case SIBA_SPROMVAR_RXPO2G:
2441                 siba->siba_sprom.rxpo2g = value;
2442                 break;
2443         case SIBA_SPROMVAR_RXPO5G:
2444                 siba->siba_sprom.rxpo5g = value;
2445                 break;
2446         case SIBA_SPROMVAR_TSSI_A:
2447                 siba->siba_sprom.tssi_a = value;
2448                 break;
2449         case SIBA_SPROMVAR_TSSI_BG:
2450                 siba->siba_sprom.tssi_bg = value;
2451                 break;
2452         case SIBA_SPROMVAR_TRI2G:
2453                 siba->siba_sprom.tri2g = value;
2454                 break;
2455         case SIBA_SPROMVAR_TRI5GL:
2456                 siba->siba_sprom.tri5gl = value;
2457                 break;
2458         case SIBA_SPROMVAR_TRI5G:
2459                 siba->siba_sprom.tri5g = value;
2460                 break;
2461         case SIBA_SPROMVAR_TRI5GH:
2462                 siba->siba_sprom.tri5gh = value;
2463                 break;
2464         case SIBA_SPROMVAR_RSSISAV2G:
2465                 siba->siba_sprom.rssisav2g = value;
2466                 break;
2467         case SIBA_SPROMVAR_RSSISMC2G:
2468                 siba->siba_sprom.rssismc2g = value;
2469                 break;
2470         case SIBA_SPROMVAR_RSSISMF2G:
2471                 siba->siba_sprom.rssismf2g = value;
2472                 break;
2473         case SIBA_SPROMVAR_BXA2G:
2474                 siba->siba_sprom.bxa2g = value;
2475                 break;
2476         case SIBA_SPROMVAR_RSSISAV5G:
2477                 siba->siba_sprom.rssisav5g = value;
2478                 break;
2479         case SIBA_SPROMVAR_RSSISMC5G:
2480                 siba->siba_sprom.rssismc5g = value;
2481                 break;
2482         case SIBA_SPROMVAR_RSSISMF5G:
2483                 siba->siba_sprom.rssismf5g = value;
2484                 break;
2485         case SIBA_SPROMVAR_BXA5G:
2486                 siba->siba_sprom.bxa5g = value;
2487                 break;
2488         case SIBA_SPROMVAR_CCK2GPO:
2489                 siba->siba_sprom.cck2gpo = value;
2490                 break;
2491         case SIBA_SPROMVAR_OFDM2GPO:
2492                 siba->siba_sprom.ofdm2gpo = value;
2493                 break;
2494         case SIBA_SPROMVAR_OFDM5GLPO:
2495                 siba->siba_sprom.ofdm5glpo = value;
2496                 break;
2497         case SIBA_SPROMVAR_OFDM5GPO:
2498                 siba->siba_sprom.ofdm5gpo = value;
2499                 break;
2500         case SIBA_SPROMVAR_OFDM5GHPO:
2501                 siba->siba_sprom.ofdm5ghpo = value;
2502                 break;
2503         case SIBA_SPROMVAR_BF_LO:
2504                 siba->siba_sprom.bf_lo = value;
2505                 break;
2506         case SIBA_SPROMVAR_BF_HI:
2507                 siba->siba_sprom.bf_hi = value;
2508                 break;
2509         case SIBA_SPROMVAR_BF2_LO:
2510                 siba->siba_sprom.bf2_lo = value;
2511                 break;
2512         case SIBA_SPROMVAR_BF2_HI:
2513                 siba->siba_sprom.bf2_hi = value;
2514                 break;
2515         default:
2516                 return (ENOENT);
2517         }
2518         return (0);
2519 }
2520
2521 #define SIBA_GPIOCTL                    0x06c
2522
2523 uint32_t
2524 siba_gpio_get(device_t dev)
2525 {
2526         struct siba_dev_softc *sd = device_get_ivars(dev);
2527         struct siba_softc *siba = sd->sd_bus;
2528         struct siba_dev_softc *gpiodev, *pcidev = NULL;
2529
2530         pcidev = siba->siba_pci.spc_dev;
2531         gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
2532         if (!gpiodev)
2533                 return (-1);
2534         return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL));
2535 }
2536
2537 void
2538 siba_gpio_set(device_t dev, uint32_t value)
2539 {
2540         struct siba_dev_softc *sd = device_get_ivars(dev);
2541         struct siba_softc *siba = sd->sd_bus;
2542         struct siba_dev_softc *gpiodev, *pcidev = NULL;
2543
2544         pcidev = siba->siba_pci.spc_dev;
2545         gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev;
2546         if (!gpiodev)
2547                 return;
2548         siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value);
2549 }
2550
2551 void
2552 siba_fix_imcfglobug(device_t dev)
2553 {
2554         struct siba_dev_softc *sd = device_get_ivars(dev);
2555         struct siba_softc *siba = sd->sd_bus;
2556         uint32_t tmp;
2557
2558         if (siba->siba_pci.spc_dev == NULL)
2559                 return;
2560         if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI ||
2561             siba->siba_pci.spc_dev->sd_id.sd_rev > 5)
2562                 return;
2563
2564         tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) &
2565             ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO);
2566         switch (siba->siba_type) {
2567         case SIBA_TYPE_PCI:
2568         case SIBA_TYPE_PCMCIA:
2569                 tmp |= 0x32;
2570                 break;
2571         case SIBA_TYPE_SSB:
2572                 tmp |= 0x53;
2573                 break;
2574         }
2575         siba_write_4_sub(sd, SIBA_IMCFGLO, tmp);
2576 }