2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
3 * Copyright (c) 1997, 1998, 1999
4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
39 * available from http://www.sis.com.tw.
41 * This driver also supports the NatSemi DP83815. Datasheets are
42 * available from http://www.national.com.
44 * Written by Bill Paul <wpaul@ee.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #ifdef HAVE_KERNEL_OPTION_HEADERS
62 #include "opt_device_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
68 #include <sys/endian.h>
69 #include <sys/kernel.h>
71 #include <sys/malloc.h>
73 #include <sys/module.h>
74 #include <sys/socket.h>
75 #include <sys/sockio.h>
76 #include <sys/sysctl.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_dl.h>
82 #include <net/if_media.h>
83 #include <net/if_types.h>
84 #include <net/if_vlan_var.h>
88 #include <machine/bus.h>
89 #include <machine/resource.h>
92 #include <dev/mii/mii.h>
93 #include <dev/mii/mii_bitbang.h>
94 #include <dev/mii/miivar.h>
96 #include <dev/pci/pcireg.h>
97 #include <dev/pci/pcivar.h>
99 #define SIS_USEIOSPACE
101 #include <dev/sis/if_sisreg.h>
103 MODULE_DEPEND(sis, pci, 1, 1, 1);
104 MODULE_DEPEND(sis, ether, 1, 1, 1);
105 MODULE_DEPEND(sis, miibus, 1, 1, 1);
107 /* "device miibus" required. See GENERIC if you get errors here. */
108 #include "miibus_if.h"
110 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
111 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
112 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
115 * register space access macros
117 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
119 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
121 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
123 #define CSR_BARRIER(sc, reg, length, flags) \
124 bus_barrier(sc->sis_res[0], reg, length, flags)
127 * Various supported device vendors/types and their names.
129 static const struct sis_type sis_devs[] = {
130 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
131 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
132 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
136 static int sis_detach(device_t);
137 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
138 static int sis_dma_alloc(struct sis_softc *);
139 static void sis_dma_free(struct sis_softc *);
140 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
141 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
142 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
143 #ifndef __NO_STRICT_ALIGNMENT
144 static __inline void sis_fixup_rx(struct mbuf *);
146 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
147 static int sis_ifmedia_upd(struct ifnet *);
148 static void sis_init(void *);
149 static void sis_initl(struct sis_softc *);
150 static void sis_intr(void *);
151 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
152 static uint32_t sis_mii_bitbang_read(device_t);
153 static void sis_mii_bitbang_write(device_t, uint32_t);
154 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
155 static int sis_resume(device_t);
156 static int sis_rxeof(struct sis_softc *);
157 static void sis_rxfilter(struct sis_softc *);
158 static void sis_rxfilter_ns(struct sis_softc *);
159 static void sis_rxfilter_sis(struct sis_softc *);
160 static void sis_start(struct ifnet *);
161 static void sis_startl(struct ifnet *);
162 static void sis_stop(struct sis_softc *);
163 static int sis_suspend(device_t);
164 static void sis_add_sysctls(struct sis_softc *);
165 static void sis_watchdog(struct sis_softc *);
166 static void sis_wol(struct sis_softc *);
171 static const struct mii_bitbang_ops sis_mii_bitbang_ops = {
172 sis_mii_bitbang_read,
173 sis_mii_bitbang_write,
175 SIS_MII_DATA, /* MII_BIT_MDO */
176 SIS_MII_DATA, /* MII_BIT_MDI */
177 SIS_MII_CLK, /* MII_BIT_MDC */
178 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
179 0, /* MII_BIT_DIR_PHY_HOST */
183 static struct resource_spec sis_res_spec[] = {
184 #ifdef SIS_USEIOSPACE
185 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
187 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
193 #define SIS_SETBIT(sc, reg, x) \
194 CSR_WRITE_4(sc, reg, \
195 CSR_READ_4(sc, reg) | (x))
197 #define SIS_CLRBIT(sc, reg, x) \
198 CSR_WRITE_4(sc, reg, \
199 CSR_READ_4(sc, reg) & ~(x))
202 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
208 * Routine to reverse the bits in a word. Stolen almost
209 * verbatim from /usr/games/fortune.
212 sis_reverse(uint16_t n)
214 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
215 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
216 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
217 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
223 sis_delay(struct sis_softc *sc)
227 for (idx = (300 / 33) + 1; idx > 0; idx--)
228 CSR_READ_4(sc, SIS_CSR);
232 sis_eeprom_idle(struct sis_softc *sc)
236 SIO_SET(SIS_EECTL_CSEL);
238 SIO_SET(SIS_EECTL_CLK);
241 for (i = 0; i < 25; i++) {
242 SIO_CLR(SIS_EECTL_CLK);
244 SIO_SET(SIS_EECTL_CLK);
248 SIO_CLR(SIS_EECTL_CLK);
250 SIO_CLR(SIS_EECTL_CSEL);
252 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
256 * Send a read command and address to the EEPROM, check for ACK.
259 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
263 d = addr | SIS_EECMD_READ;
266 * Feed in each bit and stobe the clock.
268 for (i = 0x400; i; i >>= 1) {
270 SIO_SET(SIS_EECTL_DIN);
272 SIO_CLR(SIS_EECTL_DIN);
275 SIO_SET(SIS_EECTL_CLK);
277 SIO_CLR(SIS_EECTL_CLK);
283 * Read a word of data stored in the EEPROM at address 'addr.'
286 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
291 /* Force EEPROM to idle state. */
294 /* Enter EEPROM access mode. */
296 SIO_CLR(SIS_EECTL_CLK);
298 SIO_SET(SIS_EECTL_CSEL);
302 * Send address of word we want to read.
304 sis_eeprom_putbyte(sc, addr);
307 * Start reading bits from EEPROM.
309 for (i = 0x8000; i; i >>= 1) {
310 SIO_SET(SIS_EECTL_CLK);
312 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
315 SIO_CLR(SIS_EECTL_CLK);
319 /* Turn off EEPROM access mode. */
326 * Read a sequence of words from the EEPROM.
329 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
332 uint16_t word = 0, *ptr;
334 for (i = 0; i < cnt; i++) {
335 sis_eeprom_getword(sc, off + i, &word);
336 ptr = (uint16_t *)(dest + (i * 2));
344 #if defined(__i386__) || defined(__amd64__)
346 sis_find_bridge(device_t dev)
348 devclass_t pci_devclass;
349 device_t *pci_devices;
351 device_t *pci_children;
352 int pci_childcount = 0;
353 device_t *busp, *childp;
354 device_t child = NULL;
357 if ((pci_devclass = devclass_find("pci")) == NULL)
360 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
362 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
363 if (device_get_children(*busp, &pci_children, &pci_childcount))
365 for (j = 0, childp = pci_children;
366 j < pci_childcount; j++, childp++) {
367 if (pci_get_vendor(*childp) == SIS_VENDORID &&
368 pci_get_device(*childp) == 0x0008) {
370 free(pci_children, M_TEMP);
374 free(pci_children, M_TEMP);
378 free(pci_devices, M_TEMP);
383 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
388 bus_space_tag_t btag;
390 bridge = sis_find_bridge(dev);
393 reg = pci_read_config(bridge, 0x48, 1);
394 pci_write_config(bridge, 0x48, reg|0x40, 1);
397 #if defined(__amd64__) || defined(__i386__)
398 btag = X86_BUS_SPACE_IO;
401 for (i = 0; i < cnt; i++) {
402 bus_space_write_1(btag, 0x0, 0x70, i + off);
403 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
406 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
410 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
412 uint32_t filtsave, csrsave;
414 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
415 csrsave = CSR_READ_4(sc, SIS_CSR);
417 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
418 CSR_WRITE_4(sc, SIS_CSR, 0);
420 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
422 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
423 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
424 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
425 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
426 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
427 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
430 CSR_WRITE_4(sc, SIS_CSR, csrsave);
435 * Read the MII serial port for the MII bit-bang module.
438 sis_mii_bitbang_read(device_t dev)
440 struct sis_softc *sc;
443 sc = device_get_softc(dev);
445 val = CSR_READ_4(sc, SIS_EECTL);
446 CSR_BARRIER(sc, SIS_EECTL, 4,
447 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
452 * Write the MII serial port for the MII bit-bang module.
455 sis_mii_bitbang_write(device_t dev, uint32_t val)
457 struct sis_softc *sc;
459 sc = device_get_softc(dev);
461 CSR_WRITE_4(sc, SIS_EECTL, val);
462 CSR_BARRIER(sc, SIS_EECTL, 4,
463 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
467 sis_miibus_readreg(device_t dev, int phy, int reg)
469 struct sis_softc *sc;
471 sc = device_get_softc(dev);
473 if (sc->sis_type == SIS_TYPE_83815) {
477 * The NatSemi chip can take a while after
478 * a reset to come ready, during which the BMSR
479 * returns a value of 0. This is *never* supposed
480 * to happen: some of the BMSR bits are meant to
481 * be hardwired in the on position, and this can
482 * confuse the miibus code a bit during the probe
483 * and attach phase. So we make an effort to check
484 * for this condition and wait for it to clear.
486 if (!CSR_READ_4(sc, NS_BMSR))
488 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
492 * Chipsets < SIS_635 seem not to be able to read/write
493 * through mdio. Use the enhanced PHY access register
496 if (sc->sis_type == SIS_TYPE_900 &&
497 sc->sis_rev < SIS_REV_635) {
503 CSR_WRITE_4(sc, SIS_PHYCTL,
504 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
505 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
507 for (i = 0; i < SIS_TIMEOUT; i++) {
508 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
512 if (i == SIS_TIMEOUT) {
513 device_printf(sc->sis_dev,
514 "PHY failed to come ready\n");
518 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
525 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
530 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
532 struct sis_softc *sc;
534 sc = device_get_softc(dev);
536 if (sc->sis_type == SIS_TYPE_83815) {
539 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
544 * Chipsets < SIS_635 seem not to be able to read/write
545 * through mdio. Use the enhanced PHY access register
548 if (sc->sis_type == SIS_TYPE_900 &&
549 sc->sis_rev < SIS_REV_635) {
555 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
556 (reg << 6) | SIS_PHYOP_WRITE);
557 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
559 for (i = 0; i < SIS_TIMEOUT; i++) {
560 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
564 if (i == SIS_TIMEOUT)
565 device_printf(sc->sis_dev,
566 "PHY failed to come ready\n");
568 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,
574 sis_miibus_statchg(device_t dev)
576 struct sis_softc *sc;
577 struct mii_data *mii;
581 sc = device_get_softc(dev);
584 mii = device_get_softc(sc->sis_miibus);
586 if (mii == NULL || ifp == NULL ||
587 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
590 sc->sis_flags &= ~SIS_FLAG_LINK;
591 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
592 (IFM_ACTIVE | IFM_AVALID)) {
593 switch (IFM_SUBTYPE(mii->mii_media_active)) {
595 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
596 sc->sis_flags |= SIS_FLAG_LINK;
599 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
600 sc->sis_flags |= SIS_FLAG_LINK;
607 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
609 * Stopping MACs seem to reset SIS_TX_LISTPTR and
610 * SIS_RX_LISTPTR which in turn requires resetting
611 * TX/RX buffers. So just don't do anything for
617 /* Set full/half duplex mode. */
618 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
619 SIS_SETBIT(sc, SIS_TX_CFG,
620 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
621 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
623 SIS_CLRBIT(sc, SIS_TX_CFG,
624 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
625 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
628 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
630 * MPII03.D: Half Duplex Excessive Collisions.
631 * Also page 49 in 83816 manual
633 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
636 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
637 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
639 * Short Cable Receive Errors (MP21.E)
641 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
642 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
643 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
645 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
646 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
647 device_printf(sc->sis_dev,
648 "Applying short cable fix (reg=%x)\n", reg);
649 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
650 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
652 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
654 /* Enable TX/RX MACs. */
655 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
656 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
660 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
664 /* Compute CRC for the address value. */
665 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
668 * return the filter bit position
670 * The NatSemi chip has a 512-bit filter, which is
671 * different than the SiS, so we special-case it.
673 if (sc->sis_type == SIS_TYPE_83815)
675 else if (sc->sis_rev >= SIS_REV_635 ||
676 sc->sis_rev == SIS_REV_900B)
683 sis_rxfilter(struct sis_softc *sc)
688 if (sc->sis_type == SIS_TYPE_83815)
691 sis_rxfilter_sis(sc);
695 sis_rxfilter_ns(struct sis_softc *sc)
698 struct ifmultiaddr *ifma;
699 uint32_t h, i, filter;
703 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
704 if (filter & SIS_RXFILTCTL_ENABLE) {
706 * Filter should be disabled to program other bits.
708 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
709 CSR_READ_4(sc, SIS_RXFILT_CTL);
711 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
712 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
713 SIS_RXFILTCTL_ALLMULTI);
715 if (ifp->if_flags & IFF_BROADCAST)
716 filter |= SIS_RXFILTCTL_BROAD;
718 * For the NatSemi chip, we have to explicitly enable the
719 * reception of ARP frames, as well as turn on the 'perfect
720 * match' filter where we store the station address, otherwise
721 * we won't receive unicasts meant for this host.
723 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
725 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
726 filter |= SIS_RXFILTCTL_ALLMULTI;
727 if (ifp->if_flags & IFF_PROMISC)
728 filter |= SIS_RXFILTCTL_ALLPHYS;
731 * We have to explicitly enable the multicast hash table
732 * on the NatSemi chip if we want to use it, which we do.
734 filter |= NS_RXFILTCTL_MCHASH;
736 /* first, zot all the existing hash bits */
737 for (i = 0; i < 32; i++) {
738 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
740 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
744 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
745 if (ifma->ifma_addr->sa_family != AF_LINK)
748 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
751 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
755 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
757 if_maddr_runlock(ifp);
760 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
761 CSR_READ_4(sc, SIS_RXFILT_CTL);
765 sis_rxfilter_sis(struct sis_softc *sc)
768 struct ifmultiaddr *ifma;
769 uint32_t filter, h, i, n;
774 /* hash table size */
775 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
780 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
781 if (filter & SIS_RXFILTCTL_ENABLE) {
782 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL);
783 CSR_READ_4(sc, SIS_RXFILT_CTL);
785 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
786 SIS_RXFILTCTL_ALLMULTI);
787 if (ifp->if_flags & IFF_BROADCAST)
788 filter |= SIS_RXFILTCTL_BROAD;
790 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
791 filter |= SIS_RXFILTCTL_ALLMULTI;
792 if (ifp->if_flags & IFF_PROMISC)
793 filter |= SIS_RXFILTCTL_ALLPHYS;
794 for (i = 0; i < n; i++)
797 for (i = 0; i < n; i++)
801 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
802 if (ifma->ifma_addr->sa_family != AF_LINK)
805 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
806 hashes[h >> 4] |= 1 << (h & 0xf);
809 if_maddr_runlock(ifp);
811 filter |= SIS_RXFILTCTL_ALLMULTI;
812 for (i = 0; i < n; i++)
817 for (i = 0; i < n; i++) {
818 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
819 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
822 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
823 CSR_READ_4(sc, SIS_RXFILT_CTL);
827 sis_reset(struct sis_softc *sc)
831 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
833 for (i = 0; i < SIS_TIMEOUT; i++) {
834 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
838 if (i == SIS_TIMEOUT)
839 device_printf(sc->sis_dev, "reset never completed\n");
841 /* Wait a little while for the chip to get its brains in order. */
845 * If this is a NetSemi chip, make sure to clear
848 if (sc->sis_type == SIS_TYPE_83815) {
849 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
850 CSR_WRITE_4(sc, NS_CLKRUN, 0);
852 /* Disable WOL functions. */
853 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
858 * Probe for an SiS chip. Check the PCI vendor and device
859 * IDs against our list and return a device name if we find a match.
862 sis_probe(device_t dev)
864 const struct sis_type *t;
868 while (t->sis_name != NULL) {
869 if ((pci_get_vendor(dev) == t->sis_vid) &&
870 (pci_get_device(dev) == t->sis_did)) {
871 device_set_desc(dev, t->sis_name);
872 return (BUS_PROBE_DEFAULT);
881 * Attach the interface. Allocate softc structures, do ifmedia
882 * setup and ethernet/BPF attach.
885 sis_attach(device_t dev)
887 u_char eaddr[ETHER_ADDR_LEN];
888 struct sis_softc *sc;
890 int error = 0, pmc, waittime = 0;
893 sc = device_get_softc(dev);
897 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
899 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
901 if (pci_get_device(dev) == SIS_DEVICEID_900)
902 sc->sis_type = SIS_TYPE_900;
903 if (pci_get_device(dev) == SIS_DEVICEID_7016)
904 sc->sis_type = SIS_TYPE_7016;
905 if (pci_get_vendor(dev) == NS_VENDORID)
906 sc->sis_type = SIS_TYPE_83815;
908 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
910 * Map control/status registers.
912 pci_enable_busmaster(dev);
914 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
916 device_printf(dev, "couldn't allocate resources\n");
920 /* Reset the adapter. */
923 if (sc->sis_type == SIS_TYPE_900 &&
924 (sc->sis_rev == SIS_REV_635 ||
925 sc->sis_rev == SIS_REV_900B)) {
926 SIO_SET(SIS_CFG_RND_CNT);
927 SIO_SET(SIS_CFG_PERR_DETECT);
931 * Get station address from the EEPROM.
933 switch (pci_get_vendor(dev)) {
935 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
937 /* We can't update the device description, so spew */
938 if (sc->sis_srr == NS_SRR_15C)
939 device_printf(dev, "Silicon Revision: DP83815C\n");
940 else if (sc->sis_srr == NS_SRR_15D)
941 device_printf(dev, "Silicon Revision: DP83815D\n");
942 else if (sc->sis_srr == NS_SRR_16A)
943 device_printf(dev, "Silicon Revision: DP83816A\n");
945 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
948 * Reading the MAC address out of the EEPROM on
949 * the NatSemi chip takes a bit more work than
950 * you'd expect. The address spans 4 16-bit words,
951 * with the first word containing only a single bit.
952 * You have to shift everything over one bit to
953 * get it aligned properly. Also, the bits are
954 * stored backwards (the LSB is really the MSB,
955 * and so on) so you have to reverse them in order
956 * to get the MAC address into the form we want.
957 * Why? Who the hell knows.
962 sis_read_eeprom(sc, (caddr_t)&tmp,
963 NS_EE_NODEADDR, 4, 0);
965 /* Shift everything over one bit. */
966 tmp[3] = tmp[3] >> 1;
967 tmp[3] |= tmp[2] << 15;
968 tmp[2] = tmp[2] >> 1;
969 tmp[2] |= tmp[1] << 15;
970 tmp[1] = tmp[1] >> 1;
971 tmp[1] |= tmp[0] << 15;
973 /* Now reverse all the bits. */
974 tmp[3] = sis_reverse(tmp[3]);
975 tmp[2] = sis_reverse(tmp[2]);
976 tmp[1] = sis_reverse(tmp[1]);
978 eaddr[0] = (tmp[1] >> 0) & 0xFF;
979 eaddr[1] = (tmp[1] >> 8) & 0xFF;
980 eaddr[2] = (tmp[2] >> 0) & 0xFF;
981 eaddr[3] = (tmp[2] >> 8) & 0xFF;
982 eaddr[4] = (tmp[3] >> 0) & 0xFF;
983 eaddr[5] = (tmp[3] >> 8) & 0xFF;
988 #if defined(__i386__) || defined(__amd64__)
990 * If this is a SiS 630E chipset with an embedded
991 * SiS 900 controller, we have to read the MAC address
992 * from the APC CMOS RAM. Our method for doing this
993 * is very ugly since we have to reach out and grab
994 * ahold of hardware for which we cannot properly
995 * allocate resources. This code is only compiled on
996 * the i386 architecture since the SiS 630E chipset
997 * is for x86 motherboards only. Note that there are
998 * a lot of magic numbers in this hack. These are
999 * taken from SiS's Linux driver. I'd like to replace
1000 * them with proper symbolic definitions, but that
1001 * requires some datasheets that I don't have access
1004 if (sc->sis_rev == SIS_REV_630S ||
1005 sc->sis_rev == SIS_REV_630E ||
1006 sc->sis_rev == SIS_REV_630EA1)
1007 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1009 else if (sc->sis_rev == SIS_REV_635 ||
1010 sc->sis_rev == SIS_REV_630ET)
1011 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1012 else if (sc->sis_rev == SIS_REV_96x) {
1013 /* Allow to read EEPROM from LAN. It is shared
1014 * between a 1394 controller and the NIC and each
1015 * time we access it, we need to set SIS_EECMD_REQ.
1017 SIO_SET(SIS_EECMD_REQ);
1018 for (waittime = 0; waittime < SIS_TIMEOUT;
1020 /* Force EEPROM to idle state. */
1021 sis_eeprom_idle(sc);
1022 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1023 sis_read_eeprom(sc, (caddr_t)&eaddr,
1024 SIS_EE_NODEADDR, 3, 0);
1030 * Set SIS_EECTL_CLK to high, so a other master
1031 * can operate on the i2c bus.
1033 SIO_SET(SIS_EECTL_CLK);
1034 /* Refuse EEPROM access by LAN */
1035 SIO_SET(SIS_EECMD_DONE);
1038 sis_read_eeprom(sc, (caddr_t)&eaddr,
1039 SIS_EE_NODEADDR, 3, 0);
1043 sis_add_sysctls(sc);
1045 /* Allocate DMA'able memory. */
1046 if ((error = sis_dma_alloc(sc)) != 0)
1049 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1051 device_printf(dev, "can not if_alloc()\n");
1056 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1057 ifp->if_mtu = ETHERMTU;
1058 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1059 ifp->if_ioctl = sis_ioctl;
1060 ifp->if_start = sis_start;
1061 ifp->if_init = sis_init;
1062 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1063 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1064 IFQ_SET_READY(&ifp->if_snd);
1066 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
1067 if (sc->sis_type == SIS_TYPE_83815)
1068 ifp->if_capabilities |= IFCAP_WOL;
1070 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1071 ifp->if_capenable = ifp->if_capabilities;
1077 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
1078 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1080 device_printf(dev, "attaching PHYs failed\n");
1085 * Call MI attach routine.
1087 ether_ifattach(ifp, eaddr);
1090 * Tell the upper layer(s) we support long frames.
1092 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1093 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1094 ifp->if_capenable = ifp->if_capabilities;
1095 #ifdef DEVICE_POLLING
1096 ifp->if_capabilities |= IFCAP_POLLING;
1099 /* Hook interrupt last to avoid having to lock softc */
1100 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1101 NULL, sis_intr, sc, &sc->sis_intrhand);
1104 device_printf(dev, "couldn't set up irq\n");
1105 ether_ifdetach(ifp);
1117 * Shutdown hardware and free up resources. This can be called any
1118 * time after the mutex has been initialized. It is called in both
1119 * the error case in attach and the normal detach case so it needs
1120 * to be careful about only freeing resources that have actually been
1124 sis_detach(device_t dev)
1126 struct sis_softc *sc;
1129 sc = device_get_softc(dev);
1130 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1133 #ifdef DEVICE_POLLING
1134 if (ifp->if_capenable & IFCAP_POLLING)
1135 ether_poll_deregister(ifp);
1138 /* These should only be active if attach succeeded. */
1139 if (device_is_attached(dev)) {
1143 callout_drain(&sc->sis_stat_ch);
1144 ether_ifdetach(ifp);
1147 device_delete_child(dev, sc->sis_miibus);
1148 bus_generic_detach(dev);
1150 if (sc->sis_intrhand)
1151 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1152 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1159 mtx_destroy(&sc->sis_mtx);
1164 struct sis_dmamap_arg {
1165 bus_addr_t sis_busaddr;
1169 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1171 struct sis_dmamap_arg *ctx;
1176 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1178 ctx = (struct sis_dmamap_arg *)arg;
1179 ctx->sis_busaddr = segs[0].ds_addr;
1183 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
1184 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
1185 bus_addr_t *paddr, const char *msg)
1187 struct sis_dmamap_arg ctx;
1190 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
1191 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
1192 maxsize, 0, NULL, NULL, tag);
1194 device_printf(sc->sis_dev,
1195 "could not create %s dma tag\n", msg);
1198 /* Allocate DMA'able memory for ring. */
1199 error = bus_dmamem_alloc(*tag, (void **)ring,
1200 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1202 device_printf(sc->sis_dev,
1203 "could not allocate DMA'able memory for %s\n", msg);
1206 /* Load the address of the ring. */
1207 ctx.sis_busaddr = 0;
1208 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
1209 &ctx, BUS_DMA_NOWAIT);
1211 device_printf(sc->sis_dev,
1212 "could not load DMA'able memory for %s\n", msg);
1215 *paddr = ctx.sis_busaddr;
1220 sis_dma_alloc(struct sis_softc *sc)
1222 struct sis_rxdesc *rxd;
1223 struct sis_txdesc *txd;
1226 /* Allocate the parent bus DMA tag appropriate for PCI. */
1227 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1228 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1229 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
1230 0, NULL, NULL, &sc->sis_parent_tag);
1232 device_printf(sc->sis_dev,
1233 "could not allocate parent dma tag\n");
1237 /* Create RX ring. */
1238 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
1239 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
1240 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
1244 /* Create TX ring. */
1245 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
1246 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
1247 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
1251 /* Create tag for RX mbufs. */
1252 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
1253 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1254 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
1256 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
1260 /* Create tag for TX mbufs. */
1261 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
1262 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1263 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1266 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
1270 /* Create DMA maps for RX buffers. */
1271 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
1273 device_printf(sc->sis_dev,
1274 "can't create spare DMA map for RX\n");
1277 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1278 rxd = &sc->sis_rxdesc[i];
1280 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
1282 device_printf(sc->sis_dev,
1283 "can't create DMA map for RX\n");
1288 /* Create DMA maps for TX buffers. */
1289 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1290 txd = &sc->sis_txdesc[i];
1292 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
1294 device_printf(sc->sis_dev,
1295 "can't create DMA map for TX\n");
1304 sis_dma_free(struct sis_softc *sc)
1306 struct sis_rxdesc *rxd;
1307 struct sis_txdesc *txd;
1310 /* Destroy DMA maps for RX buffers. */
1311 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1312 rxd = &sc->sis_rxdesc[i];
1314 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
1316 if (sc->sis_rx_sparemap)
1317 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
1319 /* Destroy DMA maps for TX buffers. */
1320 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1321 txd = &sc->sis_txdesc[i];
1323 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
1327 bus_dma_tag_destroy(sc->sis_rx_tag);
1329 bus_dma_tag_destroy(sc->sis_tx_tag);
1331 /* Destroy RX ring. */
1332 if (sc->sis_rx_list_map)
1333 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
1334 if (sc->sis_rx_list_map && sc->sis_rx_list)
1335 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
1336 sc->sis_rx_list_map);
1338 if (sc->sis_rx_list_tag)
1339 bus_dma_tag_destroy(sc->sis_rx_list_tag);
1341 /* Destroy TX ring. */
1342 if (sc->sis_tx_list_map)
1343 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
1345 if (sc->sis_tx_list_map && sc->sis_tx_list)
1346 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
1347 sc->sis_tx_list_map);
1349 if (sc->sis_tx_list_tag)
1350 bus_dma_tag_destroy(sc->sis_tx_list_tag);
1352 /* Destroy the parent tag. */
1353 if (sc->sis_parent_tag)
1354 bus_dma_tag_destroy(sc->sis_parent_tag);
1358 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1359 * we arrange the descriptors in a closed ring, so that the last descriptor
1360 * points back to the first.
1363 sis_ring_init(struct sis_softc *sc)
1365 struct sis_rxdesc *rxd;
1366 struct sis_txdesc *txd;
1370 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
1371 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1372 txd = &sc->sis_txdesc[i];
1374 if (i == SIS_TX_LIST_CNT - 1)
1375 next = SIS_TX_RING_ADDR(sc, 0);
1377 next = SIS_TX_RING_ADDR(sc, i + 1);
1378 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
1380 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1381 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1384 sc->sis_rx_cons = 0;
1385 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
1386 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1387 rxd = &sc->sis_rxdesc[i];
1388 rxd->rx_desc = &sc->sis_rx_list[i];
1389 if (i == SIS_RX_LIST_CNT - 1)
1390 next = SIS_RX_RING_ADDR(sc, 0);
1392 next = SIS_RX_RING_ADDR(sc, i + 1);
1393 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
1394 error = sis_newbuf(sc, rxd);
1398 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1399 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1405 * Initialize an RX descriptor and attach an MBUF cluster.
1408 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
1411 bus_dma_segment_t segs[1];
1415 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1418 m->m_len = m->m_pkthdr.len = SIS_RXLEN;
1419 #ifndef __NO_STRICT_ALIGNMENT
1420 m_adj(m, SIS_RX_BUF_ALIGN);
1423 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
1424 segs, &nsegs, 0) != 0) {
1428 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1430 if (rxd->rx_m != NULL) {
1431 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
1432 BUS_DMASYNC_POSTREAD);
1433 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
1435 map = rxd->rx_dmamap;
1436 rxd->rx_dmamap = sc->sis_rx_sparemap;
1437 sc->sis_rx_sparemap = map;
1438 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
1440 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
1441 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1445 static __inline void
1446 sis_discard_rxbuf(struct sis_rxdesc *rxd)
1449 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1452 #ifndef __NO_STRICT_ALIGNMENT
1453 static __inline void
1454 sis_fixup_rx(struct mbuf *m)
1456 uint16_t *src, *dst;
1459 src = mtod(m, uint16_t *);
1460 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
1462 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1465 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
1470 * A frame has been uploaded: pass the resulting mbuf chain up to
1471 * the higher level protocols.
1474 sis_rxeof(struct sis_softc *sc)
1478 struct sis_rxdesc *rxd;
1479 struct sis_desc *cur_rx;
1480 int prog, rx_cons, rx_npkts = 0, total_len;
1483 SIS_LOCK_ASSERT(sc);
1485 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1488 rx_cons = sc->sis_rx_cons;
1491 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1492 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
1493 #ifdef DEVICE_POLLING
1494 if (ifp->if_capenable & IFCAP_POLLING) {
1495 if (sc->rxcycles <= 0)
1500 cur_rx = &sc->sis_rx_list[rx_cons];
1501 rxstat = le32toh(cur_rx->sis_cmdsts);
1502 if ((rxstat & SIS_CMDSTS_OWN) == 0)
1504 rxd = &sc->sis_rxdesc[rx_cons];
1506 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
1507 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
1508 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1510 rxstat &= ~SIS_RXSTAT_GIANT;
1511 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1513 if (rxstat & SIS_RXSTAT_COLL)
1514 ifp->if_collisions++;
1515 sis_discard_rxbuf(rxd);
1519 /* Add a new receive buffer to the ring. */
1521 if (sis_newbuf(sc, rxd) != 0) {
1523 sis_discard_rxbuf(rxd);
1527 /* No errors; receive the packet. */
1528 m->m_pkthdr.len = m->m_len = total_len;
1529 #ifndef __NO_STRICT_ALIGNMENT
1531 * On architectures without alignment problems we try to
1532 * allocate a new buffer for the receive ring, and pass up
1533 * the one where the packet is already, saving the expensive
1539 m->m_pkthdr.rcvif = ifp;
1542 (*ifp->if_input)(ifp, m);
1548 sc->sis_rx_cons = rx_cons;
1549 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1557 * A frame was downloaded to the chip. It's safe for us to clean up
1562 sis_txeof(struct sis_softc *sc)
1565 struct sis_desc *cur_tx;
1566 struct sis_txdesc *txd;
1567 uint32_t cons, txstat;
1569 SIS_LOCK_ASSERT(sc);
1571 cons = sc->sis_tx_cons;
1572 if (cons == sc->sis_tx_prod)
1576 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1577 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1580 * Go through our tx list and free mbufs for those
1581 * frames that have been transmitted.
1583 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
1584 cur_tx = &sc->sis_tx_list[cons];
1585 txstat = le32toh(cur_tx->sis_cmdsts);
1586 if ((txstat & SIS_CMDSTS_OWN) != 0)
1588 txd = &sc->sis_txdesc[cons];
1589 if (txd->tx_m != NULL) {
1590 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
1591 BUS_DMASYNC_POSTWRITE);
1592 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1595 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
1597 ifp->if_collisions +=
1598 (txstat & SIS_TXSTAT_COLLCNT) >> 16;
1601 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
1602 ifp->if_collisions++;
1603 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
1604 ifp->if_collisions++;
1608 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1610 sc->sis_tx_cons = cons;
1611 if (sc->sis_tx_cnt == 0)
1612 sc->sis_watchdog_timer = 0;
1618 struct sis_softc *sc;
1619 struct mii_data *mii;
1622 SIS_LOCK_ASSERT(sc);
1624 mii = device_get_softc(sc->sis_miibus);
1627 if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
1628 sis_miibus_statchg(sc->sis_dev);
1629 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1632 #ifdef DEVICE_POLLING
1633 static poll_handler_t sis_poll;
1636 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1638 struct sis_softc *sc = ifp->if_softc;
1642 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1648 * On the sis, reading the status register also clears it.
1649 * So before returning to intr mode we must make sure that all
1650 * possible pending sources of interrupts have been served.
1651 * In practice this means run to completion the *eof routines,
1652 * and then call the interrupt routine
1654 sc->rxcycles = count;
1655 rx_npkts = sis_rxeof(sc);
1657 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1660 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1663 /* Reading the ISR register clears all interrupts. */
1664 status = CSR_READ_4(sc, SIS_ISR);
1666 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1669 if (status & (SIS_ISR_RX_IDLE))
1670 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1672 if (status & SIS_ISR_SYSERR) {
1673 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1681 #endif /* DEVICE_POLLING */
1686 struct sis_softc *sc;
1694 #ifdef DEVICE_POLLING
1695 if (ifp->if_capenable & IFCAP_POLLING) {
1701 /* Reading the ISR register clears all interrupts. */
1702 status = CSR_READ_4(sc, SIS_ISR);
1703 if ((status & SIS_INTRS) == 0) {
1709 /* Disable interrupts. */
1710 CSR_WRITE_4(sc, SIS_IER, 0);
1712 for (;(status & SIS_INTRS) != 0;) {
1713 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1716 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1717 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1720 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1721 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1724 if (status & SIS_ISR_RX_OFLOW)
1727 if (status & (SIS_ISR_RX_IDLE))
1728 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1730 if (status & SIS_ISR_SYSERR) {
1731 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1736 status = CSR_READ_4(sc, SIS_ISR);
1739 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1740 /* Re-enable interrupts. */
1741 CSR_WRITE_4(sc, SIS_IER, 1);
1743 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1751 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1752 * pointers to the fragment pointers.
1755 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
1758 struct sis_txdesc *txd;
1760 bus_dma_segment_t segs[SIS_MAXTXSEGS];
1762 int error, i, frag, nsegs, prod;
1765 prod = sc->sis_tx_prod;
1766 txd = &sc->sis_txdesc[prod];
1767 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
1768 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
1770 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
1771 if (M_WRITABLE(m) == 0) {
1772 /* Get a writable copy. */
1773 m = m_dup(*m_head, M_NOWAIT);
1781 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1782 m = m_defrag(m, M_NOWAIT);
1790 * Manually pad short frames, and zero the pad space
1791 * to avoid leaking data.
1793 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1794 m->m_pkthdr.len += padlen;
1795 m->m_len = m->m_pkthdr.len;
1798 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1799 *m_head, segs, &nsegs, 0);
1800 if (error == EFBIG) {
1801 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS);
1808 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1809 *m_head, segs, &nsegs, 0);
1815 } else if (error != 0)
1818 /* Check for descriptor overruns. */
1819 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
1820 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1824 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
1827 for (i = 0; i < nsegs; i++) {
1828 f = &sc->sis_tx_list[prod];
1830 f->sis_cmdsts = htole32(segs[i].ds_len |
1833 f->sis_cmdsts = htole32(segs[i].ds_len |
1834 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
1835 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
1836 SIS_INC(prod, SIS_TX_LIST_CNT);
1840 /* Update producer index. */
1841 sc->sis_tx_prod = prod;
1843 /* Remove MORE flag on the last descriptor. */
1844 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
1845 f = &sc->sis_tx_list[prod];
1846 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
1848 /* Lastly transfer ownership of packet to the controller. */
1849 f = &sc->sis_tx_list[frag];
1850 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
1852 /* Swap the last and the first dmamaps. */
1853 map = txd->tx_dmamap;
1854 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
1855 sc->sis_txdesc[prod].tx_dmamap = map;
1856 sc->sis_txdesc[prod].tx_m = *m_head;
1862 sis_start(struct ifnet *ifp)
1864 struct sis_softc *sc;
1873 sis_startl(struct ifnet *ifp)
1875 struct sis_softc *sc;
1876 struct mbuf *m_head;
1881 SIS_LOCK_ASSERT(sc);
1883 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1884 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
1887 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1888 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
1889 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1893 if (sis_encap(sc, &m_head) != 0) {
1896 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1897 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1904 * If there's a BPF listener, bounce a copy of this frame
1907 BPF_MTAP(ifp, m_head);
1912 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1913 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1914 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1917 * Set a timeout in case the chip goes out to lunch.
1919 sc->sis_watchdog_timer = 5;
1926 struct sis_softc *sc = xsc;
1934 sis_initl(struct sis_softc *sc)
1936 struct ifnet *ifp = sc->sis_ifp;
1937 struct mii_data *mii;
1940 SIS_LOCK_ASSERT(sc);
1942 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1946 * Cancel pending I/O and free all RX/TX buffers.
1950 * Reset the chip to a known state.
1954 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1956 * Configure 400usec of interrupt holdoff. This is based
1957 * on emperical tests on a Soekris 4801.
1959 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1963 mii = device_get_softc(sc->sis_miibus);
1965 /* Set MAC address */
1966 eaddr = IF_LLADDR(sc->sis_ifp);
1967 if (sc->sis_type == SIS_TYPE_83815) {
1968 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1969 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1970 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1971 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1972 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1973 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1975 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1976 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1977 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1978 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1979 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1980 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1983 /* Init circular TX/RX lists. */
1984 if (sis_ring_init(sc) != 0) {
1985 device_printf(sc->sis_dev,
1986 "initialization failed: no memory for rx buffers\n");
1991 if (sc->sis_type == SIS_TYPE_83815) {
1992 if (sc->sis_manual_pad != 0)
1993 sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
1995 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
1999 * Short Cable Receive Errors (MP21.E)
2000 * also: Page 78 of the DP83815 data sheet (september 2002 version)
2001 * recommends the following register settings "for optimum
2002 * performance." for rev 15C. Set this also for 15D parts as
2003 * they require it in practice.
2005 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
2006 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2007 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2008 /* set val for c2 */
2009 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2011 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2012 /* rais SD off, from 4 to c */
2013 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2014 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2018 /* Turn the receive filter on */
2019 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
2022 * Load the address of the RX and TX lists.
2024 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
2025 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
2027 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2028 * the PCI bus. When this bit is set, the Max DMA Burst Size
2029 * for TX/RX DMA should be no larger than 16 double words.
2031 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2032 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2034 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2037 /* Accept Long Packets for VLAN support */
2038 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2041 * Assume 100Mbps link, actual MAC configuration is done
2042 * after getting a valid link.
2044 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2047 * Enable interrupts.
2049 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2050 #ifdef DEVICE_POLLING
2052 * ... only enable interrupts if we are not polling, make sure
2053 * they are off otherwise.
2055 if (ifp->if_capenable & IFCAP_POLLING)
2056 CSR_WRITE_4(sc, SIS_IER, 0);
2059 CSR_WRITE_4(sc, SIS_IER, 1);
2061 /* Clear MAC disable. */
2062 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
2064 sc->sis_flags &= ~SIS_FLAG_LINK;
2067 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2068 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2070 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2074 * Set media options.
2077 sis_ifmedia_upd(struct ifnet *ifp)
2079 struct sis_softc *sc;
2080 struct mii_data *mii;
2081 struct mii_softc *miisc;
2087 mii = device_get_softc(sc->sis_miibus);
2088 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2090 error = mii_mediachg(mii);
2097 * Report current media status.
2100 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2102 struct sis_softc *sc;
2103 struct mii_data *mii;
2108 mii = device_get_softc(sc->sis_miibus);
2110 ifmr->ifm_active = mii->mii_media_active;
2111 ifmr->ifm_status = mii->mii_media_status;
2116 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2118 struct sis_softc *sc = ifp->if_softc;
2119 struct ifreq *ifr = (struct ifreq *) data;
2120 struct mii_data *mii;
2121 int error = 0, mask;
2126 if (ifp->if_flags & IFF_UP) {
2127 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2128 ((ifp->if_flags ^ sc->sis_if_flags) &
2129 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2133 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2135 sc->sis_if_flags = ifp->if_flags;
2146 mii = device_get_softc(sc->sis_miibus);
2147 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2151 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2152 #ifdef DEVICE_POLLING
2153 if ((mask & IFCAP_POLLING) != 0 &&
2154 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
2155 ifp->if_capenable ^= IFCAP_POLLING;
2156 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
2157 error = ether_poll_register(sis_poll, ifp);
2162 /* Disable interrupts. */
2163 CSR_WRITE_4(sc, SIS_IER, 0);
2165 error = ether_poll_deregister(ifp);
2166 /* Enable interrupts. */
2167 CSR_WRITE_4(sc, SIS_IER, 1);
2170 #endif /* DEVICE_POLLING */
2171 if ((mask & IFCAP_WOL) != 0 &&
2172 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2173 if ((mask & IFCAP_WOL_UCAST) != 0)
2174 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2175 if ((mask & IFCAP_WOL_MCAST) != 0)
2176 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2177 if ((mask & IFCAP_WOL_MAGIC) != 0)
2178 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2183 error = ether_ioctl(ifp, command, data);
2191 sis_watchdog(struct sis_softc *sc)
2194 SIS_LOCK_ASSERT(sc);
2196 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2199 device_printf(sc->sis_dev, "watchdog timeout\n");
2200 sc->sis_ifp->if_oerrors++;
2202 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2205 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
2206 sis_startl(sc->sis_ifp);
2210 * Stop the adapter and free any mbufs allocated to the
2214 sis_stop(struct sis_softc *sc)
2217 struct sis_rxdesc *rxd;
2218 struct sis_txdesc *txd;
2221 SIS_LOCK_ASSERT(sc);
2224 sc->sis_watchdog_timer = 0;
2226 callout_stop(&sc->sis_stat_ch);
2228 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2229 CSR_WRITE_4(sc, SIS_IER, 0);
2230 CSR_WRITE_4(sc, SIS_IMR, 0);
2231 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2232 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2234 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2235 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2237 sc->sis_flags &= ~SIS_FLAG_LINK;
2240 * Free data in the RX lists.
2242 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2243 rxd = &sc->sis_rxdesc[i];
2244 if (rxd->rx_m != NULL) {
2245 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
2246 BUS_DMASYNC_POSTREAD);
2247 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
2254 * Free the TX list buffers.
2256 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2257 txd = &sc->sis_txdesc[i];
2258 if (txd->tx_m != NULL) {
2259 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
2260 BUS_DMASYNC_POSTWRITE);
2261 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
2269 * Stop all chip I/O so that the kernel's probe routines don't
2270 * get confused by errant DMAs when rebooting.
2273 sis_shutdown(device_t dev)
2276 return (sis_suspend(dev));
2280 sis_suspend(device_t dev)
2282 struct sis_softc *sc;
2284 sc = device_get_softc(dev);
2293 sis_resume(device_t dev)
2295 struct sis_softc *sc;
2298 sc = device_get_softc(dev);
2301 if ((ifp->if_flags & IFF_UP) != 0) {
2302 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2310 sis_wol(struct sis_softc *sc)
2318 if ((ifp->if_capenable & IFCAP_WOL) == 0)
2321 if (sc->sis_type == SIS_TYPE_83815) {
2323 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2325 /* Configure WOL events. */
2326 CSR_READ_4(sc, NS_WCSR);
2328 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2329 val |= NS_WCSR_WAKE_UCAST;
2330 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2331 val |= NS_WCSR_WAKE_MCAST;
2332 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2333 val |= NS_WCSR_WAKE_MAGIC;
2334 CSR_WRITE_4(sc, NS_WCSR, val);
2335 /* Enable PME and clear PMESTS. */
2336 val = CSR_READ_4(sc, NS_CLKRUN);
2337 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
2338 CSR_WRITE_4(sc, NS_CLKRUN, val);
2339 /* Enable silent RX mode. */
2340 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2342 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
2345 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2346 val |= SIS_PWRMAN_WOL_MAGIC;
2347 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
2349 pmstat = pci_read_config(sc->sis_dev,
2350 pmc + PCIR_POWER_STATUS, 2);
2351 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2352 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2353 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2354 pci_write_config(sc->sis_dev,
2355 pmc + PCIR_POWER_STATUS, pmstat, 2);
2360 sis_add_sysctls(struct sis_softc *sc)
2362 struct sysctl_ctx_list *ctx;
2363 struct sysctl_oid_list *children;
2367 ctx = device_get_sysctl_ctx(sc->sis_dev);
2368 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
2370 unit = device_get_unit(sc->sis_dev);
2372 * Unlike most other controllers, NS DP83815/DP83816 controllers
2373 * seem to pad with 0xFF when it encounter short frames. According
2374 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable
2375 * on will have driver pad manully but it's disabled by default
2376 * because it will consume extra CPU cycles for short frames.
2378 sc->sis_manual_pad = 0;
2379 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit);
2380 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad);
2381 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
2382 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames");
2385 static device_method_t sis_methods[] = {
2386 /* Device interface */
2387 DEVMETHOD(device_probe, sis_probe),
2388 DEVMETHOD(device_attach, sis_attach),
2389 DEVMETHOD(device_detach, sis_detach),
2390 DEVMETHOD(device_shutdown, sis_shutdown),
2391 DEVMETHOD(device_suspend, sis_suspend),
2392 DEVMETHOD(device_resume, sis_resume),
2395 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2396 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2397 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2402 static driver_t sis_driver = {
2405 sizeof(struct sis_softc)
2408 static devclass_t sis_devclass;
2410 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2411 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);