sys/dev/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34 /*-
  35  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  36  *
  37  * Permission to use, copy, modify, and distribute this software for any
  38  * purpose with or without fee is hereby granted, provided that the above
  39  * copyright notice and this permission notice appear in all copies.
  40  *
  41  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  42  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  43  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  44  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  45  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  46  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  47  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  48  */
  49
  50 #include <sys/cdefs.h>
  51 __FBSDID("$FreeBSD$");
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71 /*
  72  * The SysKonnect gigabit ethernet adapters consist of two main
  73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  75  * components and a PHY while the GEnesis controller provides a PCI
  76  * interface with DMA support. Each card may have between 512K and
  77  * 2MB of SRAM on board depending on the configuration.
  78  *
  79  * The SysKonnect GEnesis controller can have either one or two XMAC
  80  * chips connected to it, allowing single or dual port NIC configurations.
  81  * SysKonnect has the distinction of being the only vendor on the market
  82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  84  * XMAC registers. This driver takes advantage of these features to allow
  85  * both XMACs to operate as independent interfaces.
  86  */
  87
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/mbuf.h>
  93 #include <sys/malloc.h>
  94 #include <sys/kernel.h>
  95 #include <sys/module.h>
  96 #include <sys/socket.h>
  97 #include <sys/sockio.h>
  98 #include <sys/queue.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/bpf.h>
 102 #include <net/ethernet.h>
 103 #include <net/if.h>
 104 #include <net/if_arp.h>
 105 #include <net/if_dl.h>
 106 #include <net/if_media.h>
 107 #include <net/if_types.h>
 108 #include <net/if_vlan_var.h>
 109
 110 #include <netinet/in.h>
 111 #include <netinet/in_systm.h>
 112 #include <netinet/ip.h>
 113
 114 #include <machine/bus.h>
 115 #include <machine/in_cksum.h>
 116 #include <machine/resource.h>
 117 #include <sys/rman.h>
 118
 119 #include <dev/mii/mii.h>
 120 #include <dev/mii/miivar.h>
 121 #include <dev/mii/brgphyreg.h>
 122
 123 #include <dev/pci/pcireg.h>
 124 #include <dev/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include <dev/sk/if_skreg.h>
 131 #include <dev/sk/xmaciireg.h>
 132 #include <dev/sk/yukonreg.h>
 133
 134 MODULE_DEPEND(sk, pci, 1, 1, 1);
 135 MODULE_DEPEND(sk, ether, 1, 1, 1);
 136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
 137
 138 /* "device miibus" required.  See GENERIC if you get errors here. */
 139 #include "miibus_if.h"
 140
 141 static const struct sk_type sk_devs[] = {
 142         {
 143                 VENDORID_SK,
 144                 DEVICEID_SK_V1,
 145                 "SysKonnect Gigabit Ethernet (V1.0)"
 146         },
 147         {
 148                 VENDORID_SK,
 149                 DEVICEID_SK_V2,
 150                 "SysKonnect Gigabit Ethernet (V2.0)"
 151         },
 152         {
 153                 VENDORID_MARVELL,
 154                 DEVICEID_SK_V2,
 155                 "Marvell Gigabit Ethernet"
 156         },
 157         {
 158                 VENDORID_MARVELL,
 159                 DEVICEID_BELKIN_5005,
 160                 "Belkin F5D5005 Gigabit Ethernet"
 161         },
 162         {
 163                 VENDORID_3COM,
 164                 DEVICEID_3COM_3C940,
 165                 "3Com 3C940 Gigabit Ethernet"
 166         },
 167         {
 168                 VENDORID_LINKSYS,
 169                 DEVICEID_LINKSYS_EG1032,
 170                 "Linksys EG1032 Gigabit Ethernet"
 171         },
 172         {
 173                 VENDORID_DLINK,
 174                 DEVICEID_DLINK_DGE530T_A1,
 175                 "D-Link DGE-530T Gigabit Ethernet"
 176         },
 177         {
 178                 VENDORID_DLINK,
 179                 DEVICEID_DLINK_DGE530T_B1,
 180                 "D-Link DGE-530T Gigabit Ethernet"
 181         },
 182         { 0, 0, NULL }
 183 };
 184
 185 static int skc_probe(device_t);
 186 static int skc_attach(device_t);
 187 static int skc_detach(device_t);
 188 static int skc_shutdown(device_t);
 189 static int skc_suspend(device_t);
 190 static int skc_resume(device_t);
 191 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
 192 static int sk_detach(device_t);
 193 static int sk_probe(device_t);
 194 static int sk_attach(device_t);
 195 static void sk_tick(void *);
 196 static void sk_yukon_tick(void *);
 197 static void sk_intr(void *);
 198 static void sk_intr_xmac(struct sk_if_softc *);
 199 static void sk_intr_bcom(struct sk_if_softc *);
 200 static void sk_intr_yukon(struct sk_if_softc *);
 201 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
 202 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
 203 static void sk_rxeof(struct sk_if_softc *);
 204 static void sk_jumbo_rxeof(struct sk_if_softc *);
 205 static void sk_txeof(struct sk_if_softc *);
 206 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
 207 static int sk_encap(struct sk_if_softc *, struct mbuf **);
 208 static void sk_start(struct ifnet *);
 209 static void sk_start_locked(struct ifnet *);
 210 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
 211 static void sk_init(void *);
 212 static void sk_init_locked(struct sk_if_softc *);
 213 static void sk_init_xmac(struct sk_if_softc *);
 214 static void sk_init_yukon(struct sk_if_softc *);
 215 static void sk_stop(struct sk_if_softc *);
 216 static void sk_watchdog(void *);
 217 static int sk_ifmedia_upd(struct ifnet *);
 218 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 219 static void sk_reset(struct sk_softc *);
 220 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
 221 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
 222 static int sk_newbuf(struct sk_if_softc *, int);
 223 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
 224 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 225 static int sk_dma_alloc(struct sk_if_softc *);
 226 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
 227 static void sk_dma_free(struct sk_if_softc *);
 228 static void sk_dma_jumbo_free(struct sk_if_softc *);
 229 static int sk_init_rx_ring(struct sk_if_softc *);
 230 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
 231 static void sk_init_tx_ring(struct sk_if_softc *);
 232 static u_int32_t sk_win_read_4(struct sk_softc *, int);
 233 static u_int16_t sk_win_read_2(struct sk_softc *, int);
 234 static u_int8_t sk_win_read_1(struct sk_softc *, int);
 235 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
 236 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
 237 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
 238
 239 static int sk_miibus_readreg(device_t, int, int);
 240 static int sk_miibus_writereg(device_t, int, int, int);
 241 static void sk_miibus_statchg(device_t);
 242
 243 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 244 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
 245                                                 int);
 246 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
 247
 248 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 249 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
 250                                                 int);
 251 static void sk_marv_miibus_statchg(struct sk_if_softc *);
 252
 253 static uint32_t sk_xmchash(const uint8_t *);
 254 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
 255 static void sk_rxfilter(struct sk_if_softc *);
 256 static void sk_rxfilter_genesis(struct sk_if_softc *);
 257 static void sk_rxfilter_yukon(struct sk_if_softc *);
 258
 259 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
 260 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
 261
 262 /* Tunables. */
 263 static int jumbo_disable = 0;
 264 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
 265
 266 /*
 267  * It seems that SK-NET GENESIS supports very simple checksum offload
 268  * capability for Tx and I believe it can generate 0 checksum value for
 269  * UDP packets in Tx as the hardware can't differenciate UDP packets from
 270  * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
 271  * means sender didn't perforam checksum computation. For the safety I
 272  * disabled UDP checksum offload capability at the moment. Alternatively
 273  * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
 274  * offload routine.
 275  */
 276 #define SK_CSUM_FEATURES        (CSUM_TCP)
 277
 278 /*
 279  * Note that we have newbus methods for both the GEnesis controller
 280  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 281  * the miibus code is a child of the XMACs. We need to do it this way
 282  * so that the miibus drivers can access the PHY registers on the
 283  * right PHY. It's not quite what I had in mind, but it's the only
 284  * design that achieves the desired effect.
 285  */
 286 static device_method_t skc_methods[] = {
 287         /* Device interface */
 288         DEVMETHOD(device_probe,         skc_probe),
 289         DEVMETHOD(device_attach,        skc_attach),
 290         DEVMETHOD(device_detach,        skc_detach),
 291         DEVMETHOD(device_suspend,       skc_suspend),
 292         DEVMETHOD(device_resume,        skc_resume),
 293         DEVMETHOD(device_shutdown,      skc_shutdown),
 294
 295         DEVMETHOD(bus_get_dma_tag,      skc_get_dma_tag),
 296
 297         DEVMETHOD_END
 298 };
 299
 300 static driver_t skc_driver = {
 301         "skc",
 302         skc_methods,
 303         sizeof(struct sk_softc)
 304 };
 305
 306 static devclass_t skc_devclass;
 307
 308 static device_method_t sk_methods[] = {
 309         /* Device interface */
 310         DEVMETHOD(device_probe,         sk_probe),
 311         DEVMETHOD(device_attach,        sk_attach),
 312         DEVMETHOD(device_detach,        sk_detach),
 313         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 314
 315         /* MII interface */
 316         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 317         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 318         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 319
 320         DEVMETHOD_END
 321 };
 322
 323 static driver_t sk_driver = {
 324         "sk",
 325         sk_methods,
 326         sizeof(struct sk_if_softc)
 327 };
 328
 329 static devclass_t sk_devclass;
 330
 331 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL);
 332 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL);
 333 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
 334
 335 static struct resource_spec sk_res_spec_io[] = {
 336         { SYS_RES_IOPORT,       PCIR_BAR(1),    RF_ACTIVE },
 337         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 338         { -1,                   0,              0 }
 339 };
 340
 341 static struct resource_spec sk_res_spec_mem[] = {
 342         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 343         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 344         { -1,                   0,              0 }
 345 };
 346
 347 #define SK_SETBIT(sc, reg, x)           \
 348         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 349
 350 #define SK_CLRBIT(sc, reg, x)           \
 351         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 352
 353 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 354         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 355
 356 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 357         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 358
 359 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 360         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 361
 362 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 363         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 364
 365 static u_int32_t
 366 sk_win_read_4(sc, reg)
 367         struct sk_softc         *sc;
 368         int                     reg;
 369 {
 370 #ifdef SK_USEIOSPACE
 371         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 372         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 373 #else
 374         return(CSR_READ_4(sc, reg));
 375 #endif
 376 }
 377
 378 static u_int16_t
 379 sk_win_read_2(sc, reg)
 380         struct sk_softc         *sc;
 381         int                     reg;
 382 {
 383 #ifdef SK_USEIOSPACE
 384         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 385         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 386 #else
 387         return(CSR_READ_2(sc, reg));
 388 #endif
 389 }
 390
 391 static u_int8_t
 392 sk_win_read_1(sc, reg)
 393         struct sk_softc         *sc;
 394         int                     reg;
 395 {
 396 #ifdef SK_USEIOSPACE
 397         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 398         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 399 #else
 400         return(CSR_READ_1(sc, reg));
 401 #endif
 402 }
 403
 404 static void
 405 sk_win_write_4(sc, reg, val)
 406         struct sk_softc         *sc;
 407         int                     reg;
 408         u_int32_t               val;
 409 {
 410 #ifdef SK_USEIOSPACE
 411         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 412         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 413 #else
 414         CSR_WRITE_4(sc, reg, val);
 415 #endif
 416         return;
 417 }
 418
 419 static void
 420 sk_win_write_2(sc, reg, val)
 421         struct sk_softc         *sc;
 422         int                     reg;
 423         u_int32_t               val;
 424 {
 425 #ifdef SK_USEIOSPACE
 426         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 427         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 428 #else
 429         CSR_WRITE_2(sc, reg, val);
 430 #endif
 431         return;
 432 }
 433
 434 static void
 435 sk_win_write_1(sc, reg, val)
 436         struct sk_softc         *sc;
 437         int                     reg;
 438         u_int32_t               val;
 439 {
 440 #ifdef SK_USEIOSPACE
 441         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 442         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 443 #else
 444         CSR_WRITE_1(sc, reg, val);
 445 #endif
 446         return;
 447 }
 448
 449 static int
 450 sk_miibus_readreg(dev, phy, reg)
 451         device_t                dev;
 452         int                     phy, reg;
 453 {
 454         struct sk_if_softc      *sc_if;
 455         int                     v;
 456
 457         sc_if = device_get_softc(dev);
 458
 459         SK_IF_MII_LOCK(sc_if);
 460         switch(sc_if->sk_softc->sk_type) {
 461         case SK_GENESIS:
 462                 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
 463                 break;
 464         case SK_YUKON:
 465         case SK_YUKON_LITE:
 466         case SK_YUKON_LP:
 467                 v = sk_marv_miibus_readreg(sc_if, phy, reg);
 468                 break;
 469         default:
 470                 v = 0;
 471                 break;
 472         }
 473         SK_IF_MII_UNLOCK(sc_if);
 474
 475         return (v);
 476 }
 477
 478 static int
 479 sk_miibus_writereg(dev, phy, reg, val)
 480         device_t                dev;
 481         int                     phy, reg, val;
 482 {
 483         struct sk_if_softc      *sc_if;
 484         int                     v;
 485
 486         sc_if = device_get_softc(dev);
 487
 488         SK_IF_MII_LOCK(sc_if);
 489         switch(sc_if->sk_softc->sk_type) {
 490         case SK_GENESIS:
 491                 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 492                 break;
 493         case SK_YUKON:
 494         case SK_YUKON_LITE:
 495         case SK_YUKON_LP:
 496                 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
 497                 break;
 498         default:
 499                 v = 0;
 500                 break;
 501         }
 502         SK_IF_MII_UNLOCK(sc_if);
 503
 504         return (v);
 505 }
 506
 507 static void
 508 sk_miibus_statchg(dev)
 509         device_t                dev;
 510 {
 511         struct sk_if_softc      *sc_if;
 512
 513         sc_if = device_get_softc(dev);
 514
 515         SK_IF_MII_LOCK(sc_if);
 516         switch(sc_if->sk_softc->sk_type) {
 517         case SK_GENESIS:
 518                 sk_xmac_miibus_statchg(sc_if);
 519                 break;
 520         case SK_YUKON:
 521         case SK_YUKON_LITE:
 522         case SK_YUKON_LP:
 523                 sk_marv_miibus_statchg(sc_if);
 524                 break;
 525         }
 526         SK_IF_MII_UNLOCK(sc_if);
 527
 528         return;
 529 }
 530
 531 static int
 532 sk_xmac_miibus_readreg(sc_if, phy, reg)
 533         struct sk_if_softc      *sc_if;
 534         int                     phy, reg;
 535 {
 536         int                     i;
 537
 538         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 539         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 540         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 541                 for (i = 0; i < SK_TIMEOUT; i++) {
 542                         DELAY(1);
 543                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 544                             XM_MMUCMD_PHYDATARDY)
 545                                 break;
 546                 }
 547
 548                 if (i == SK_TIMEOUT) {
 549                         if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 550                         return(0);
 551                 }
 552         }
 553         DELAY(1);
 554         i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
 555
 556         return(i);
 557 }
 558
 559 static int
 560 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 561         struct sk_if_softc      *sc_if;
 562         int                     phy, reg, val;
 563 {
 564         int                     i;
 565
 566         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 567         for (i = 0; i < SK_TIMEOUT; i++) {
 568                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 569                         break;
 570         }
 571
 572         if (i == SK_TIMEOUT) {
 573                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 574                 return (ETIMEDOUT);
 575         }
 576
 577         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 578         for (i = 0; i < SK_TIMEOUT; i++) {
 579                 DELAY(1);
 580                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 581                         break;
 582         }
 583         if (i == SK_TIMEOUT)
 584                 if_printf(sc_if->sk_ifp, "phy write timed out\n");
 585
 586         return(0);
 587 }
 588
 589 static void
 590 sk_xmac_miibus_statchg(sc_if)
 591         struct sk_if_softc      *sc_if;
 592 {
 593         struct mii_data         *mii;
 594
 595         mii = device_get_softc(sc_if->sk_miibus);
 596
 597         /*
 598          * If this is a GMII PHY, manually set the XMAC's
 599          * duplex mode accordingly.
 600          */
 601         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 602                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 603                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 604                 } else {
 605                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 606                 }
 607         }
 608 }
 609
 610 static int
 611 sk_marv_miibus_readreg(sc_if, phy, reg)
 612         struct sk_if_softc      *sc_if;
 613         int                     phy, reg;
 614 {
 615         u_int16_t               val;
 616         int                     i;
 617
 618         if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 619             sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
 620                 return(0);
 621         }
 622
 623         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 624                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 625
 626         for (i = 0; i < SK_TIMEOUT; i++) {
 627                 DELAY(1);
 628                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 629                 if (val & YU_SMICR_READ_VALID)
 630                         break;
 631         }
 632
 633         if (i == SK_TIMEOUT) {
 634                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 635                 return(0);
 636         }
 637
 638         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 639
 640         return(val);
 641 }
 642
 643 static int
 644 sk_marv_miibus_writereg(sc_if, phy, reg, val)
 645         struct sk_if_softc      *sc_if;
 646         int                     phy, reg, val;
 647 {
 648         int                     i;
 649
 650         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 651         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 652                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 653
 654         for (i = 0; i < SK_TIMEOUT; i++) {
 655                 DELAY(1);
 656                 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
 657                         break;
 658         }
 659         if (i == SK_TIMEOUT)
 660                 if_printf(sc_if->sk_ifp, "phy write timeout\n");
 661
 662         return(0);
 663 }
 664
 665 static void
 666 sk_marv_miibus_statchg(sc_if)
 667         struct sk_if_softc      *sc_if;
 668 {
 669         return;
 670 }
 671
 672 #define HASH_BITS               6
 673
 674 static u_int32_t
 675 sk_xmchash(addr)
 676         const uint8_t *addr;
 677 {
 678         uint32_t crc;
 679
 680         /* Compute CRC for the address value. */
 681         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 682
 683         return (~crc & ((1 << HASH_BITS) - 1));
 684 }
 685
 686 static void
 687 sk_setfilt(sc_if, addr, slot)
 688         struct sk_if_softc      *sc_if;
 689         u_int16_t               *addr;
 690         int                     slot;
 691 {
 692         int                     base;
 693
 694         base = XM_RXFILT_ENTRY(slot);
 695
 696         SK_XM_WRITE_2(sc_if, base, addr[0]);
 697         SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
 698         SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
 699
 700         return;
 701 }
 702
 703 static void
 704 sk_rxfilter(sc_if)
 705         struct sk_if_softc      *sc_if;
 706 {
 707         struct sk_softc         *sc;
 708
 709         SK_IF_LOCK_ASSERT(sc_if);
 710
 711         sc = sc_if->sk_softc;
 712         if (sc->sk_type == SK_GENESIS)
 713                 sk_rxfilter_genesis(sc_if);
 714         else
 715                 sk_rxfilter_yukon(sc_if);
 716 }
 717
 718 static void
 719 sk_rxfilter_genesis(sc_if)
 720         struct sk_if_softc      *sc_if;
 721 {
 722         struct ifnet            *ifp = sc_if->sk_ifp;
 723         u_int32_t               hashes[2] = { 0, 0 }, mode;
 724         int                     h = 0, i;
 725         struct ifmultiaddr      *ifma;
 726         u_int16_t               dummy[] = { 0, 0, 0 };
 727         u_int16_t               maddr[(ETHER_ADDR_LEN+1)/2];
 728
 729         SK_IF_LOCK_ASSERT(sc_if);
 730
 731         mode = SK_XM_READ_4(sc_if, XM_MODE);
 732         mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
 733             XM_MODE_RX_USE_PERFECT);
 734         /* First, zot all the existing perfect filters. */
 735         for (i = 1; i < XM_RXFILT_MAX; i++)
 736                 sk_setfilt(sc_if, dummy, i);
 737
 738         /* Now program new ones. */
 739         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 740                 if (ifp->if_flags & IFF_ALLMULTI)
 741                         mode |= XM_MODE_RX_USE_HASH;
 742                 if (ifp->if_flags & IFF_PROMISC)
 743                         mode |= XM_MODE_RX_PROMISC;
 744                 hashes[0] = 0xFFFFFFFF;
 745                 hashes[1] = 0xFFFFFFFF;
 746         } else {
 747                 i = 1;
 748                 if_maddr_rlock(ifp);
 749                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
 750                     ifma_link) {
 751                         if (ifma->ifma_addr->sa_family != AF_LINK)
 752                                 continue;
 753                         /*
 754                          * Program the first XM_RXFILT_MAX multicast groups
 755                          * into the perfect filter.
 756                          */
 757                         bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 758                             maddr, ETHER_ADDR_LEN);
 759                         if (i < XM_RXFILT_MAX) {
 760                                 sk_setfilt(sc_if, maddr, i);
 761                                 mode |= XM_MODE_RX_USE_PERFECT;
 762                                 i++;
 763                                 continue;
 764                         }
 765                         h = sk_xmchash((const uint8_t *)maddr);
 766                         if (h < 32)
 767                                 hashes[0] |= (1 << h);
 768                         else
 769                                 hashes[1] |= (1 << (h - 32));
 770                         mode |= XM_MODE_RX_USE_HASH;
 771                 }
 772                 if_maddr_runlock(ifp);
 773         }
 774
 775         SK_XM_WRITE_4(sc_if, XM_MODE, mode);
 776         SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 777         SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 778 }
 779
 780 static void
 781 sk_rxfilter_yukon(sc_if)
 782         struct sk_if_softc      *sc_if;
 783 {
 784         struct ifnet            *ifp;
 785         u_int32_t               crc, hashes[2] = { 0, 0 }, mode;
 786         struct ifmultiaddr      *ifma;
 787
 788         SK_IF_LOCK_ASSERT(sc_if);
 789
 790         ifp = sc_if->sk_ifp;
 791         mode = SK_YU_READ_2(sc_if, YUKON_RCR);
 792         if (ifp->if_flags & IFF_PROMISC)
 793                 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
 794         else if (ifp->if_flags & IFF_ALLMULTI) {
 795                 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
 796                 hashes[0] = 0xFFFFFFFF;
 797                 hashes[1] = 0xFFFFFFFF;
 798         } else {
 799                 mode |= YU_RCR_UFLEN;
 800                 if_maddr_rlock(ifp);
 801                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 802                         if (ifma->ifma_addr->sa_family != AF_LINK)
 803                                 continue;
 804                         crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 805                             ifma->ifma_addr), ETHER_ADDR_LEN);
 806                         /* Just want the 6 least significant bits. */
 807                         crc &= 0x3f;
 808                         /* Set the corresponding bit in the hash table. */
 809                         hashes[crc >> 5] |= 1 << (crc & 0x1f);
 810                 }
 811                 if_maddr_runlock(ifp);
 812                 if (hashes[0] != 0 || hashes[1] != 0)
 813                         mode |= YU_RCR_MUFLEN;
 814         }
 815
 816         SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 817         SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 818         SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 819         SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 820         SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
 821 }
 822
 823 static int
 824 sk_init_rx_ring(sc_if)
 825         struct sk_if_softc      *sc_if;
 826 {
 827         struct sk_ring_data     *rd;
 828         bus_addr_t              addr;
 829         u_int32_t               csum_start;
 830         int                     i;
 831
 832         sc_if->sk_cdata.sk_rx_cons = 0;
 833
 834         csum_start = (ETHER_HDR_LEN + sizeof(struct ip))  << 16 |
 835             ETHER_HDR_LEN;
 836         rd = &sc_if->sk_rdata;
 837         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 838         for (i = 0; i < SK_RX_RING_CNT; i++) {
 839                 if (sk_newbuf(sc_if, i) != 0)
 840                         return (ENOBUFS);
 841                 if (i == (SK_RX_RING_CNT - 1))
 842                         addr = SK_RX_RING_ADDR(sc_if, 0);
 843                 else
 844                         addr = SK_RX_RING_ADDR(sc_if, i + 1);
 845                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 846                 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
 847         }
 848
 849         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
 850             sc_if->sk_cdata.sk_rx_ring_map,
 851             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 852
 853         return(0);
 854 }
 855
 856 static int
 857 sk_init_jumbo_rx_ring(sc_if)
 858         struct sk_if_softc      *sc_if;
 859 {
 860         struct sk_ring_data     *rd;
 861         bus_addr_t              addr;
 862         u_int32_t               csum_start;
 863         int                     i;
 864
 865         sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
 866
 867         csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
 868             ETHER_HDR_LEN;
 869         rd = &sc_if->sk_rdata;
 870         bzero(rd->sk_jumbo_rx_ring,
 871             sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
 872         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
 873                 if (sk_jumbo_newbuf(sc_if, i) != 0)
 874                         return (ENOBUFS);
 875                 if (i == (SK_JUMBO_RX_RING_CNT - 1))
 876                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
 877                 else
 878                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
 879                 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 880                 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
 881         }
 882
 883         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
 884             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
 885             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 886
 887         return (0);
 888 }
 889
 890 static void
 891 sk_init_tx_ring(sc_if)
 892         struct sk_if_softc      *sc_if;
 893 {
 894         struct sk_ring_data     *rd;
 895         struct sk_txdesc        *txd;
 896         bus_addr_t              addr;
 897         int                     i;
 898
 899         STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
 900         STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
 901
 902         sc_if->sk_cdata.sk_tx_prod = 0;
 903         sc_if->sk_cdata.sk_tx_cons = 0;
 904         sc_if->sk_cdata.sk_tx_cnt = 0;
 905
 906         rd = &sc_if->sk_rdata;
 907         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 908         for (i = 0; i < SK_TX_RING_CNT; i++) {
 909                 if (i == (SK_TX_RING_CNT - 1))
 910                         addr = SK_TX_RING_ADDR(sc_if, 0);
 911                 else
 912                         addr = SK_TX_RING_ADDR(sc_if, i + 1);
 913                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 914                 txd = &sc_if->sk_cdata.sk_txdesc[i];
 915                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
 916         }
 917
 918         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
 919             sc_if->sk_cdata.sk_tx_ring_map,
 920             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 921 }
 922
 923 static __inline void
 924 sk_discard_rxbuf(sc_if, idx)
 925         struct sk_if_softc      *sc_if;
 926         int                     idx;
 927 {
 928         struct sk_rx_desc       *r;
 929         struct sk_rxdesc        *rxd;
 930         struct mbuf             *m;
 931
 932
 933         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 934         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 935         m = rxd->rx_m;
 936         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 937 }
 938
 939 static __inline void
 940 sk_discard_jumbo_rxbuf(sc_if, idx)
 941         struct sk_if_softc      *sc_if;
 942         int                     idx;
 943 {
 944         struct sk_rx_desc       *r;
 945         struct sk_rxdesc        *rxd;
 946         struct mbuf             *m;
 947
 948         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
 949         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
 950         m = rxd->rx_m;
 951         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 952 }
 953
 954 static int
 955 sk_newbuf(sc_if, idx)
 956         struct sk_if_softc      *sc_if;
 957         int                     idx;
 958 {
 959         struct sk_rx_desc       *r;
 960         struct sk_rxdesc        *rxd;
 961         struct mbuf             *m;
 962         bus_dma_segment_t       segs[1];
 963         bus_dmamap_t            map;
 964         int                     nsegs;
 965
 966         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 967         if (m == NULL)
 968                 return (ENOBUFS);
 969         m->m_len = m->m_pkthdr.len = MCLBYTES;
 970         m_adj(m, ETHER_ALIGN);
 971
 972         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
 973             sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
 974                 m_freem(m);
 975                 return (ENOBUFS);
 976         }
 977         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 978
 979         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 980         if (rxd->rx_m != NULL) {
 981                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 982                     BUS_DMASYNC_POSTREAD);
 983                 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
 984         }
 985         map = rxd->rx_dmamap;
 986         rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
 987         sc_if->sk_cdata.sk_rx_sparemap = map;
 988         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 989             BUS_DMASYNC_PREREAD);
 990         rxd->rx_m = m;
 991         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 992         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
 993         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
 994         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
 995
 996         return (0);
 997 }
 998
 999 static int
1000 sk_jumbo_newbuf(sc_if, idx)
1001         struct sk_if_softc      *sc_if;
1002         int                     idx;
1003 {
1004         struct sk_rx_desc       *r;
1005         struct sk_rxdesc        *rxd;
1006         struct mbuf             *m;
1007         bus_dma_segment_t       segs[1];
1008         bus_dmamap_t            map;
1009         int                     nsegs;
1010
1011         m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1012         if (m == NULL)
1013                 return (ENOBUFS);
1014         if ((m->m_flags & M_EXT) == 0) {
1015                 m_freem(m);
1016                 return (ENOBUFS);
1017         }
1018         m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1019         /*
1020          * Adjust alignment so packet payload begins on a
1021          * longword boundary. Mandatory for Alpha, useful on
1022          * x86 too.
1023          */
1024         m_adj(m, ETHER_ALIGN);
1025
1026         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1027             sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1028                 m_freem(m);
1029                 return (ENOBUFS);
1030         }
1031         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1032
1033         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1034         if (rxd->rx_m != NULL) {
1035                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1036                     BUS_DMASYNC_POSTREAD);
1037                 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1038                     rxd->rx_dmamap);
1039         }
1040         map = rxd->rx_dmamap;
1041         rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1042         sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1043         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1044             BUS_DMASYNC_PREREAD);
1045         rxd->rx_m = m;
1046         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1047         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1048         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1049         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1050
1051         return (0);
1052 }
1053
1054 /*
1055  * Set media options.
1056  */
1057 static int
1058 sk_ifmedia_upd(ifp)
1059         struct ifnet            *ifp;
1060 {
1061         struct sk_if_softc      *sc_if = ifp->if_softc;
1062         struct mii_data         *mii;
1063
1064         mii = device_get_softc(sc_if->sk_miibus);
1065         sk_init(sc_if);
1066         mii_mediachg(mii);
1067
1068         return(0);
1069 }
1070
1071 /*
1072  * Report current media status.
1073  */
1074 static void
1075 sk_ifmedia_sts(ifp, ifmr)
1076         struct ifnet            *ifp;
1077         struct ifmediareq       *ifmr;
1078 {
1079         struct sk_if_softc      *sc_if;
1080         struct mii_data         *mii;
1081
1082         sc_if = ifp->if_softc;
1083         mii = device_get_softc(sc_if->sk_miibus);
1084
1085         mii_pollstat(mii);
1086         ifmr->ifm_active = mii->mii_media_active;
1087         ifmr->ifm_status = mii->mii_media_status;
1088
1089         return;
1090 }
1091
1092 static int
1093 sk_ioctl(ifp, command, data)
1094         struct ifnet            *ifp;
1095         u_long                  command;
1096         caddr_t                 data;
1097 {
1098         struct sk_if_softc      *sc_if = ifp->if_softc;
1099         struct ifreq            *ifr = (struct ifreq *) data;
1100         int                     error, mask;
1101         struct mii_data         *mii;
1102
1103         error = 0;
1104         switch(command) {
1105         case SIOCSIFMTU:
1106                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1107                         error = EINVAL;
1108                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1109                         if (sc_if->sk_jumbo_disable != 0 &&
1110                             ifr->ifr_mtu > SK_MAX_FRAMELEN)
1111                                 error = EINVAL;
1112                         else {
1113                                 SK_IF_LOCK(sc_if);
1114                                 ifp->if_mtu = ifr->ifr_mtu;
1115                                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1116                                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1117                                         sk_init_locked(sc_if);
1118                                 }
1119                                 SK_IF_UNLOCK(sc_if);
1120                         }
1121                 }
1122                 break;
1123         case SIOCSIFFLAGS:
1124                 SK_IF_LOCK(sc_if);
1125                 if (ifp->if_flags & IFF_UP) {
1126                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1127                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1128                                     & (IFF_PROMISC | IFF_ALLMULTI))
1129                                         sk_rxfilter(sc_if);
1130                         } else
1131                                 sk_init_locked(sc_if);
1132                 } else {
1133                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1134                                 sk_stop(sc_if);
1135                 }
1136                 sc_if->sk_if_flags = ifp->if_flags;
1137                 SK_IF_UNLOCK(sc_if);
1138                 break;
1139         case SIOCADDMULTI:
1140         case SIOCDELMULTI:
1141                 SK_IF_LOCK(sc_if);
1142                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1143                         sk_rxfilter(sc_if);
1144                 SK_IF_UNLOCK(sc_if);
1145                 break;
1146         case SIOCGIFMEDIA:
1147         case SIOCSIFMEDIA:
1148                 mii = device_get_softc(sc_if->sk_miibus);
1149                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1150                 break;
1151         case SIOCSIFCAP:
1152                 SK_IF_LOCK(sc_if);
1153                 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1154                         SK_IF_UNLOCK(sc_if);
1155                         break;
1156                 }
1157                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1158                 if ((mask & IFCAP_TXCSUM) != 0 &&
1159                     (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1160                         ifp->if_capenable ^= IFCAP_TXCSUM;
1161                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1162                                 ifp->if_hwassist |= SK_CSUM_FEATURES;
1163                         else
1164                                 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1165                 }
1166                 if ((mask & IFCAP_RXCSUM) != 0 &&
1167                     (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1168                         ifp->if_capenable ^= IFCAP_RXCSUM;
1169                 SK_IF_UNLOCK(sc_if);
1170                 break;
1171         default:
1172                 error = ether_ioctl(ifp, command, data);
1173                 break;
1174         }
1175
1176         return (error);
1177 }
1178
1179 /*
1180  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1181  * IDs against our list and return a device name if we find a match.
1182  */
1183 static int
1184 skc_probe(dev)
1185         device_t                dev;
1186 {
1187         const struct sk_type    *t = sk_devs;
1188
1189         while(t->sk_name != NULL) {
1190                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1191                     (pci_get_device(dev) == t->sk_did)) {
1192                         /*
1193                          * Only attach to rev. 2 of the Linksys EG1032 adapter.
1194                          * Rev. 3 is supported by re(4).
1195                          */
1196                         if ((t->sk_vid == VENDORID_LINKSYS) &&
1197                                 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1198                                 (pci_get_subdevice(dev) !=
1199                                  SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1200                                 t++;
1201                                 continue;
1202                         }
1203                         device_set_desc(dev, t->sk_name);
1204                         return (BUS_PROBE_DEFAULT);
1205                 }
1206                 t++;
1207         }
1208
1209         return(ENXIO);
1210 }
1211
1212 /*
1213  * Force the GEnesis into reset, then bring it out of reset.
1214  */
1215 static void
1216 sk_reset(sc)
1217         struct sk_softc         *sc;
1218 {
1219
1220         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1221         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1222         if (SK_YUKON_FAMILY(sc->sk_type))
1223                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1224
1225         DELAY(1000);
1226         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1227         DELAY(2);
1228         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1229         if (SK_YUKON_FAMILY(sc->sk_type))
1230                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1231
1232         if (sc->sk_type == SK_GENESIS) {
1233                 /* Configure packet arbiter */
1234                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1235                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1236                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1237                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1238                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1239         }
1240
1241         /* Enable RAM interface */
1242         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1243
1244         /*
1245          * Configure interrupt moderation. The moderation timer
1246          * defers interrupts specified in the interrupt moderation
1247          * timer mask based on the timeout specified in the interrupt
1248          * moderation timer init register. Each bit in the timer
1249          * register represents one tick, so to specify a timeout in
1250          * microseconds, we have to multiply by the correct number of
1251          * ticks-per-microsecond.
1252          */
1253         switch (sc->sk_type) {
1254         case SK_GENESIS:
1255                 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1256                 break;
1257         default:
1258                 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1259                 break;
1260         }
1261         if (bootverbose)
1262                 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1263                     sc->sk_int_mod);
1264         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1265             sc->sk_int_ticks));
1266         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1267             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1268         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1269
1270         return;
1271 }
1272
1273 static int
1274 sk_probe(dev)
1275         device_t                dev;
1276 {
1277         struct sk_softc         *sc;
1278
1279         sc = device_get_softc(device_get_parent(dev));
1280
1281         /*
1282          * Not much to do here. We always know there will be
1283          * at least one XMAC present, and if there are two,
1284          * skc_attach() will create a second device instance
1285          * for us.
1286          */
1287         switch (sc->sk_type) {
1288         case SK_GENESIS:
1289                 device_set_desc(dev, "XaQti Corp. XMAC II");
1290                 break;
1291         case SK_YUKON:
1292         case SK_YUKON_LITE:
1293         case SK_YUKON_LP:
1294                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1295                 break;
1296         }
1297
1298         return (BUS_PROBE_DEFAULT);
1299 }
1300
1301 /*
1302  * Each XMAC chip is attached as a separate logical IP interface.
1303  * Single port cards will have only one logical interface of course.
1304  */
1305 static int
1306 sk_attach(dev)
1307         device_t                dev;
1308 {
1309         struct sk_softc         *sc;
1310         struct sk_if_softc      *sc_if;
1311         struct ifnet            *ifp;
1312         u_int32_t               r;
1313         int                     error, i, phy, port;
1314         u_char                  eaddr[6];
1315         u_char                  inv_mac[] = {0, 0, 0, 0, 0, 0};
1316
1317         if (dev == NULL)
1318                 return(EINVAL);
1319
1320         error = 0;
1321         sc_if = device_get_softc(dev);
1322         sc = device_get_softc(device_get_parent(dev));
1323         port = *(int *)device_get_ivars(dev);
1324
1325         sc_if->sk_if_dev = dev;
1326         sc_if->sk_port = port;
1327         sc_if->sk_softc = sc;
1328         sc->sk_if[port] = sc_if;
1329         if (port == SK_PORT_A)
1330                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1331         if (port == SK_PORT_B)
1332                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1333
1334         callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1335         callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1336
1337         if (sk_dma_alloc(sc_if) != 0) {
1338                 error = ENOMEM;
1339                 goto fail;
1340         }
1341         sk_dma_jumbo_alloc(sc_if);
1342
1343         ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1344         if (ifp == NULL) {
1345                 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1346                 error = ENOSPC;
1347                 goto fail;
1348         }
1349         ifp->if_softc = sc_if;
1350         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1351         ifp->if_mtu = ETHERMTU;
1352         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1353         /*
1354          * SK_GENESIS has a bug in checksum offload - From linux.
1355          */
1356         if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1357                 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1358                 ifp->if_hwassist = 0;
1359         } else {
1360                 ifp->if_capabilities = 0;
1361                 ifp->if_hwassist = 0;
1362         }
1363         ifp->if_capenable = ifp->if_capabilities;
1364         /*
1365          * Some revision of Yukon controller generates corrupted
1366          * frame when TX checksum offloading is enabled.  The
1367          * frame has a valid checksum value so payload might be
1368          * modified during TX checksum calculation. Disable TX
1369          * checksum offloading but give users chance to enable it
1370          * when they know their controller works without problems
1371          * with TX checksum offloading.
1372          */
1373         ifp->if_capenable &= ~IFCAP_TXCSUM;
1374         ifp->if_ioctl = sk_ioctl;
1375         ifp->if_start = sk_start;
1376         ifp->if_init = sk_init;
1377         IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1378         ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1379         IFQ_SET_READY(&ifp->if_snd);
1380
1381         /*
1382          * Get station address for this interface. Note that
1383          * dual port cards actually come with three station
1384          * addresses: one for each port, plus an extra. The
1385          * extra one is used by the SysKonnect driver software
1386          * as a 'virtual' station address for when both ports
1387          * are operating in failover mode. Currently we don't
1388          * use this extra address.
1389          */
1390         SK_IF_LOCK(sc_if);
1391         for (i = 0; i < ETHER_ADDR_LEN; i++)
1392                 eaddr[i] =
1393                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1394
1395         /* Verify whether the station address is invalid or not. */
1396         if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1397                 device_printf(sc_if->sk_if_dev,
1398                     "Generating random ethernet address\n");
1399                 r = arc4random();
1400                 /*
1401                  * Set OUI to convenient locally assigned address.  'b'
1402                  * is 0x62, which has the locally assigned bit set, and
1403                  * the broadcast/multicast bit clear.
1404                  */
1405                 eaddr[0] = 'b';
1406                 eaddr[1] = 's';
1407                 eaddr[2] = 'd';
1408                 eaddr[3] = (r >> 16) & 0xff;
1409                 eaddr[4] = (r >>  8) & 0xff;
1410                 eaddr[5] = (r >>  0) & 0xff;
1411         }
1412         /*
1413          * Set up RAM buffer addresses. The NIC will have a certain
1414          * amount of SRAM on it, somewhere between 512K and 2MB. We
1415          * need to divide this up a) between the transmitter and
1416          * receiver and b) between the two XMACs, if this is a
1417          * dual port NIC. Our algotithm is to divide up the memory
1418          * evenly so that everyone gets a fair share.
1419          *
1420          * Just to be contrary, Yukon2 appears to have separate memory
1421          * for each MAC.
1422          */
1423         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1424                 u_int32_t               chunk, val;
1425
1426                 chunk = sc->sk_ramsize / 2;
1427                 val = sc->sk_rboff / sizeof(u_int64_t);
1428                 sc_if->sk_rx_ramstart = val;
1429                 val += (chunk / sizeof(u_int64_t));
1430                 sc_if->sk_rx_ramend = val - 1;
1431                 sc_if->sk_tx_ramstart = val;
1432                 val += (chunk / sizeof(u_int64_t));
1433                 sc_if->sk_tx_ramend = val - 1;
1434         } else {
1435                 u_int32_t               chunk, val;
1436
1437                 chunk = sc->sk_ramsize / 4;
1438                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1439                     sizeof(u_int64_t);
1440                 sc_if->sk_rx_ramstart = val;
1441                 val += (chunk / sizeof(u_int64_t));
1442                 sc_if->sk_rx_ramend = val - 1;
1443                 sc_if->sk_tx_ramstart = val;
1444                 val += (chunk / sizeof(u_int64_t));
1445                 sc_if->sk_tx_ramend = val - 1;
1446         }
1447
1448         /* Read and save PHY type and set PHY address */
1449         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1450         if (!SK_YUKON_FAMILY(sc->sk_type)) {
1451                 switch(sc_if->sk_phytype) {
1452                 case SK_PHYTYPE_XMAC:
1453                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1454                         break;
1455                 case SK_PHYTYPE_BCOM:
1456                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1457                         break;
1458                 default:
1459                         device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1460                             sc_if->sk_phytype);
1461                         error = ENODEV;
1462                         SK_IF_UNLOCK(sc_if);
1463                         goto fail;
1464                 }
1465         } else {
1466                 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1467                     sc->sk_pmd != 'S') {
1468                         /* not initialized, punt */
1469                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1470                         sc->sk_coppertype = 1;
1471                 }
1472
1473                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1474
1475                 if (!(sc->sk_coppertype))
1476                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1477         }
1478
1479         /*
1480          * Call MI attach routine.  Can't hold locks when calling into ether_*.
1481          */
1482         SK_IF_UNLOCK(sc_if);
1483         ether_ifattach(ifp, eaddr);
1484         SK_IF_LOCK(sc_if);
1485
1486         /*
1487          * The hardware should be ready for VLAN_MTU by default:
1488          * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1489          * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1490          *
1491          */
1492         ifp->if_capabilities |= IFCAP_VLAN_MTU;
1493         ifp->if_capenable |= IFCAP_VLAN_MTU;
1494         /*
1495          * Tell the upper layer(s) we support long frames.
1496          * Must appear after the call to ether_ifattach() because
1497          * ether_ifattach() sets ifi_hdrlen to the default value.
1498          */
1499         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1500
1501         /*
1502          * Do miibus setup.
1503          */
1504         phy = MII_PHY_ANY;
1505         switch (sc->sk_type) {
1506         case SK_GENESIS:
1507                 sk_init_xmac(sc_if);
1508                 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1509                         phy = 0;
1510                 break;
1511         case SK_YUKON:
1512         case SK_YUKON_LITE:
1513         case SK_YUKON_LP:
1514                 sk_init_yukon(sc_if);
1515                 phy = 0;
1516                 break;
1517         }
1518
1519         SK_IF_UNLOCK(sc_if);
1520         error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1521             sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1522         if (error != 0) {
1523                 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1524                 ether_ifdetach(ifp);
1525                 goto fail;
1526         }
1527
1528 fail:
1529         if (error) {
1530                 /* Access should be ok even though lock has been dropped */
1531                 sc->sk_if[port] = NULL;
1532                 sk_detach(dev);
1533         }
1534
1535         return(error);
1536 }
1537
1538 /*
1539  * Attach the interface. Allocate softc structures, do ifmedia
1540  * setup and ethernet/BPF attach.
1541  */
1542 static int
1543 skc_attach(dev)
1544         device_t                dev;
1545 {
1546         struct sk_softc         *sc;
1547         int                     error = 0, *port;
1548         uint8_t                 skrs;
1549         const char              *pname = NULL;
1550         char                    *revstr;
1551
1552         sc = device_get_softc(dev);
1553         sc->sk_dev = dev;
1554
1555         mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1556             MTX_DEF);
1557         mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1558         /*
1559          * Map control/status registers.
1560          */
1561         pci_enable_busmaster(dev);
1562
1563         /* Allocate resources */
1564 #ifdef SK_USEIOSPACE
1565         sc->sk_res_spec = sk_res_spec_io;
1566 #else
1567         sc->sk_res_spec = sk_res_spec_mem;
1568 #endif
1569         error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1570         if (error) {
1571                 if (sc->sk_res_spec == sk_res_spec_mem)
1572                         sc->sk_res_spec = sk_res_spec_io;
1573                 else
1574                         sc->sk_res_spec = sk_res_spec_mem;
1575                 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1576                 if (error) {
1577                         device_printf(dev, "couldn't allocate %s resources\n",
1578                             sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1579                             "I/O");
1580                         goto fail;
1581                 }
1582         }
1583
1584         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1585         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1586
1587         /* Bail out if chip is not recognized. */
1588         if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1589                 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1590                     sc->sk_type, sc->sk_rev);
1591                 error = ENXIO;
1592                 goto fail;
1593         }
1594
1595         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1596                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1597                 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1598                 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1599                 "SK interrupt moderation");
1600
1601         /* Pull in device tunables. */
1602         sc->sk_int_mod = SK_IM_DEFAULT;
1603         error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1604                 "int_mod", &sc->sk_int_mod);
1605         if (error == 0) {
1606                 if (sc->sk_int_mod < SK_IM_MIN ||
1607                     sc->sk_int_mod > SK_IM_MAX) {
1608                         device_printf(dev, "int_mod value out of range; "
1609                             "using default: %d\n", SK_IM_DEFAULT);
1610                         sc->sk_int_mod = SK_IM_DEFAULT;
1611                 }
1612         }
1613
1614         /* Reset the adapter. */
1615         sk_reset(sc);
1616
1617         skrs = sk_win_read_1(sc, SK_EPROM0);
1618         if (sc->sk_type == SK_GENESIS) {
1619                 /* Read and save RAM size and RAMbuffer offset */
1620                 switch(skrs) {
1621                 case SK_RAMSIZE_512K_64:
1622                         sc->sk_ramsize = 0x80000;
1623                         sc->sk_rboff = SK_RBOFF_0;
1624                         break;
1625                 case SK_RAMSIZE_1024K_64:
1626                         sc->sk_ramsize = 0x100000;
1627                         sc->sk_rboff = SK_RBOFF_80000;
1628                         break;
1629                 case SK_RAMSIZE_1024K_128:
1630                         sc->sk_ramsize = 0x100000;
1631                         sc->sk_rboff = SK_RBOFF_0;
1632                         break;
1633                 case SK_RAMSIZE_2048K_128:
1634                         sc->sk_ramsize = 0x200000;
1635                         sc->sk_rboff = SK_RBOFF_0;
1636                         break;
1637                 default:
1638                         device_printf(dev, "unknown ram size: %d\n", skrs);
1639                         error = ENXIO;
1640                         goto fail;
1641                 }
1642         } else { /* SK_YUKON_FAMILY */
1643                 if (skrs == 0x00)
1644                         sc->sk_ramsize = 0x20000;
1645                 else
1646                         sc->sk_ramsize = skrs * (1<<12);
1647                 sc->sk_rboff = SK_RBOFF_0;
1648         }
1649
1650         /* Read and save physical media type */
1651          sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1652
1653          if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1654                  sc->sk_coppertype = 1;
1655          else
1656                  sc->sk_coppertype = 0;
1657
1658         /* Determine whether to name it with VPD PN or just make it up.
1659          * Marvell Yukon VPD PN seems to freqently be bogus. */
1660         switch (pci_get_device(dev)) {
1661         case DEVICEID_SK_V1:
1662         case DEVICEID_BELKIN_5005:
1663         case DEVICEID_3COM_3C940:
1664         case DEVICEID_LINKSYS_EG1032:
1665         case DEVICEID_DLINK_DGE530T_A1:
1666         case DEVICEID_DLINK_DGE530T_B1:
1667                 /* Stay with VPD PN. */
1668                 (void) pci_get_vpd_ident(dev, &pname);
1669                 break;
1670         case DEVICEID_SK_V2:
1671                 /* YUKON VPD PN might bear no resemblance to reality. */
1672                 switch (sc->sk_type) {
1673                 case SK_GENESIS:
1674                         /* Stay with VPD PN. */
1675                         (void) pci_get_vpd_ident(dev, &pname);
1676                         break;
1677                 case SK_YUKON:
1678                         pname = "Marvell Yukon Gigabit Ethernet";
1679                         break;
1680                 case SK_YUKON_LITE:
1681                         pname = "Marvell Yukon Lite Gigabit Ethernet";
1682                         break;
1683                 case SK_YUKON_LP:
1684                         pname = "Marvell Yukon LP Gigabit Ethernet";
1685                         break;
1686                 default:
1687                         pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1688                         break;
1689                 }
1690
1691                 /* Yukon Lite Rev. A0 needs special test. */
1692                 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1693                         u_int32_t far;
1694                         u_int8_t testbyte;
1695
1696                         /* Save flash address register before testing. */
1697                         far = sk_win_read_4(sc, SK_EP_ADDR);
1698
1699                         sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1700                         testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1701
1702                         if (testbyte != 0x00) {
1703                                 /* Yukon Lite Rev. A0 detected. */
1704                                 sc->sk_type = SK_YUKON_LITE;
1705                                 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1706                                 /* Restore flash address register. */
1707                                 sk_win_write_4(sc, SK_EP_ADDR, far);
1708                         }
1709                 }
1710                 break;
1711         default:
1712                 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1713                         "chipver=%02x, rev=%x\n",
1714                         pci_get_vendor(dev), pci_get_device(dev),
1715                         sc->sk_type, sc->sk_rev);
1716                 error = ENXIO;
1717                 goto fail;
1718         }
1719
1720         if (sc->sk_type == SK_YUKON_LITE) {
1721                 switch (sc->sk_rev) {
1722                 case SK_YUKON_LITE_REV_A0:
1723                         revstr = "A0";
1724                         break;
1725                 case SK_YUKON_LITE_REV_A1:
1726                         revstr = "A1";
1727                         break;
1728                 case SK_YUKON_LITE_REV_A3:
1729                         revstr = "A3";
1730                         break;
1731                 default:
1732                         revstr = "";
1733                         break;
1734                 }
1735         } else {
1736                 revstr = "";
1737         }
1738
1739         /* Announce the product name and more VPD data if there. */
1740         if (pname != NULL)
1741                 device_printf(dev, "%s rev. %s(0x%x)\n",
1742                         pname, revstr, sc->sk_rev);
1743
1744         if (bootverbose) {
1745                 device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
1746                 device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
1747                 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1748                 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1749         }
1750
1751         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1752         if (sc->sk_devs[SK_PORT_A] == NULL) {
1753                 device_printf(dev, "failed to add child for PORT_A\n");
1754                 error = ENXIO;
1755                 goto fail;
1756         }
1757         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1758         if (port == NULL) {
1759                 device_printf(dev, "failed to allocate memory for "
1760                     "ivars of PORT_A\n");
1761                 error = ENXIO;
1762                 goto fail;
1763         }
1764         *port = SK_PORT_A;
1765         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1766
1767         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1768                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1769                 if (sc->sk_devs[SK_PORT_B] == NULL) {
1770                         device_printf(dev, "failed to add child for PORT_B\n");
1771                         error = ENXIO;
1772                         goto fail;
1773                 }
1774                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1775                 if (port == NULL) {
1776                         device_printf(dev, "failed to allocate memory for "
1777                             "ivars of PORT_B\n");
1778                         error = ENXIO;
1779                         goto fail;
1780                 }
1781                 *port = SK_PORT_B;
1782                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1783         }
1784
1785         /* Turn on the 'driver is loaded' LED. */
1786         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1787
1788         error = bus_generic_attach(dev);
1789         if (error) {
1790                 device_printf(dev, "failed to attach port(s)\n");
1791                 goto fail;
1792         }
1793
1794         /* Hook interrupt last to avoid having to lock softc */
1795         error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1796             NULL, sk_intr, sc, &sc->sk_intrhand);
1797
1798         if (error) {
1799                 device_printf(dev, "couldn't set up irq\n");
1800                 goto fail;
1801         }
1802
1803 fail:
1804         if (error)
1805                 skc_detach(dev);
1806
1807         return(error);
1808 }
1809
1810 /*
1811  * Shutdown hardware and free up resources. This can be called any
1812  * time after the mutex has been initialized. It is called in both
1813  * the error case in attach and the normal detach case so it needs
1814  * to be careful about only freeing resources that have actually been
1815  * allocated.
1816  */
1817 static int
1818 sk_detach(dev)
1819         device_t                dev;
1820 {
1821         struct sk_if_softc      *sc_if;
1822         struct ifnet            *ifp;
1823
1824         sc_if = device_get_softc(dev);
1825         KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1826             ("sk mutex not initialized in sk_detach"));
1827         SK_IF_LOCK(sc_if);
1828
1829         ifp = sc_if->sk_ifp;
1830         /* These should only be active if attach_xmac succeeded */
1831         if (device_is_attached(dev)) {
1832                 sk_stop(sc_if);
1833                 /* Can't hold locks while calling detach */
1834                 SK_IF_UNLOCK(sc_if);
1835                 callout_drain(&sc_if->sk_tick_ch);
1836                 callout_drain(&sc_if->sk_watchdog_ch);
1837                 ether_ifdetach(ifp);
1838                 SK_IF_LOCK(sc_if);
1839         }
1840         if (ifp)
1841                 if_free(ifp);
1842         /*
1843          * We're generally called from skc_detach() which is using
1844          * device_delete_child() to get to here. It's already trashed
1845          * miibus for us, so don't do it here or we'll panic.
1846          */
1847         /*
1848         if (sc_if->sk_miibus != NULL)
1849                 device_delete_child(dev, sc_if->sk_miibus);
1850         */
1851         bus_generic_detach(dev);
1852         sk_dma_jumbo_free(sc_if);
1853         sk_dma_free(sc_if);
1854         SK_IF_UNLOCK(sc_if);
1855
1856         return(0);
1857 }
1858
1859 static int
1860 skc_detach(dev)
1861         device_t                dev;
1862 {
1863         struct sk_softc         *sc;
1864
1865         sc = device_get_softc(dev);
1866         KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1867
1868         if (device_is_alive(dev)) {
1869                 if (sc->sk_devs[SK_PORT_A] != NULL) {
1870                         free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1871                         device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1872                 }
1873                 if (sc->sk_devs[SK_PORT_B] != NULL) {
1874                         free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1875                         device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1876                 }
1877                 bus_generic_detach(dev);
1878         }
1879
1880         if (sc->sk_intrhand)
1881                 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1882         bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1883
1884         mtx_destroy(&sc->sk_mii_mtx);
1885         mtx_destroy(&sc->sk_mtx);
1886
1887         return(0);
1888 }
1889
1890 static bus_dma_tag_t
1891 skc_get_dma_tag(device_t bus, device_t child __unused)
1892 {
1893
1894         return (bus_get_dma_tag(bus));
1895 }
1896
1897 struct sk_dmamap_arg {
1898         bus_addr_t      sk_busaddr;
1899 };
1900
1901 static void
1902 sk_dmamap_cb(arg, segs, nseg, error)
1903         void                    *arg;
1904         bus_dma_segment_t       *segs;
1905         int                     nseg;
1906         int                     error;
1907 {
1908         struct sk_dmamap_arg    *ctx;
1909
1910         if (error != 0)
1911                 return;
1912
1913         ctx = arg;
1914         ctx->sk_busaddr = segs[0].ds_addr;
1915 }
1916
1917 /*
1918  * Allocate jumbo buffer storage. The SysKonnect adapters support
1919  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1920  * use them in their drivers. In order for us to use them, we need
1921  * large 9K receive buffers, however standard mbuf clusters are only
1922  * 2048 bytes in size. Consequently, we need to allocate and manage
1923  * our own jumbo buffer pool. Fortunately, this does not require an
1924  * excessive amount of additional code.
1925  */
1926 static int
1927 sk_dma_alloc(sc_if)
1928         struct sk_if_softc      *sc_if;
1929 {
1930         struct sk_dmamap_arg    ctx;
1931         struct sk_txdesc        *txd;
1932         struct sk_rxdesc        *rxd;
1933         int                     error, i;
1934
1935         /* create parent tag */
1936         /*
1937          * XXX
1938          * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1939          * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1940          * However bz@ reported that it does not work on amd64 with > 4GB
1941          * RAM. Until we have more clues of the breakage, disable DAC mode
1942          * by limiting DMA address to be in 32bit address space.
1943          */
1944         error = bus_dma_tag_create(
1945                     bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1946                     1, 0,                       /* algnmnt, boundary */
1947                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1948                     BUS_SPACE_MAXADDR,          /* highaddr */
1949                     NULL, NULL,                 /* filter, filterarg */
1950                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1951                     0,                          /* nsegments */
1952                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1953                     0,                          /* flags */
1954                     NULL, NULL,                 /* lockfunc, lockarg */
1955                     &sc_if->sk_cdata.sk_parent_tag);
1956         if (error != 0) {
1957                 device_printf(sc_if->sk_if_dev,
1958                     "failed to create parent DMA tag\n");
1959                 goto fail;
1960         }
1961
1962         /* create tag for Tx ring */
1963         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1964                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1965                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1966                     BUS_SPACE_MAXADDR,          /* highaddr */
1967                     NULL, NULL,                 /* filter, filterarg */
1968                     SK_TX_RING_SZ,              /* maxsize */
1969                     1,                          /* nsegments */
1970                     SK_TX_RING_SZ,              /* maxsegsize */
1971                     0,                          /* flags */
1972                     NULL, NULL,                 /* lockfunc, lockarg */
1973                     &sc_if->sk_cdata.sk_tx_ring_tag);
1974         if (error != 0) {
1975                 device_printf(sc_if->sk_if_dev,
1976                     "failed to allocate Tx ring DMA tag\n");
1977                 goto fail;
1978         }
1979
1980         /* create tag for Rx ring */
1981         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1982                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1983                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1984                     BUS_SPACE_MAXADDR,          /* highaddr */
1985                     NULL, NULL,                 /* filter, filterarg */
1986                     SK_RX_RING_SZ,              /* maxsize */
1987                     1,                          /* nsegments */
1988                     SK_RX_RING_SZ,              /* maxsegsize */
1989                     0,                          /* flags */
1990                     NULL, NULL,                 /* lockfunc, lockarg */
1991                     &sc_if->sk_cdata.sk_rx_ring_tag);
1992         if (error != 0) {
1993                 device_printf(sc_if->sk_if_dev,
1994                     "failed to allocate Rx ring DMA tag\n");
1995                 goto fail;
1996         }
1997
1998         /* create tag for Tx buffers */
1999         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2000                     1, 0,                       /* algnmnt, boundary */
2001                     BUS_SPACE_MAXADDR,          /* lowaddr */
2002                     BUS_SPACE_MAXADDR,          /* highaddr */
2003                     NULL, NULL,                 /* filter, filterarg */
2004                     MCLBYTES * SK_MAXTXSEGS,    /* maxsize */
2005                     SK_MAXTXSEGS,               /* nsegments */
2006                     MCLBYTES,                   /* maxsegsize */
2007                     0,                          /* flags */
2008                     NULL, NULL,                 /* lockfunc, lockarg */
2009                     &sc_if->sk_cdata.sk_tx_tag);
2010         if (error != 0) {
2011                 device_printf(sc_if->sk_if_dev,
2012                     "failed to allocate Tx DMA tag\n");
2013                 goto fail;
2014         }
2015
2016         /* create tag for Rx buffers */
2017         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2018                     1, 0,                       /* algnmnt, boundary */
2019                     BUS_SPACE_MAXADDR,          /* lowaddr */
2020                     BUS_SPACE_MAXADDR,          /* highaddr */
2021                     NULL, NULL,                 /* filter, filterarg */
2022                     MCLBYTES,                   /* maxsize */
2023                     1,                          /* nsegments */
2024                     MCLBYTES,                   /* maxsegsize */
2025                     0,                          /* flags */
2026                     NULL, NULL,                 /* lockfunc, lockarg */
2027                     &sc_if->sk_cdata.sk_rx_tag);
2028         if (error != 0) {
2029                 device_printf(sc_if->sk_if_dev,
2030                     "failed to allocate Rx DMA tag\n");
2031                 goto fail;
2032         }
2033
2034         /* allocate DMA'able memory and load the DMA map for Tx ring */
2035         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2036             (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2037             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2038         if (error != 0) {
2039                 device_printf(sc_if->sk_if_dev,
2040                     "failed to allocate DMA'able memory for Tx ring\n");
2041                 goto fail;
2042         }
2043
2044         ctx.sk_busaddr = 0;
2045         error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2046             sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2047             SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2048         if (error != 0) {
2049                 device_printf(sc_if->sk_if_dev,
2050                     "failed to load DMA'able memory for Tx ring\n");
2051                 goto fail;
2052         }
2053         sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2054
2055         /* allocate DMA'able memory and load the DMA map for Rx ring */
2056         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2057             (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2058             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2059         if (error != 0) {
2060                 device_printf(sc_if->sk_if_dev,
2061                     "failed to allocate DMA'able memory for Rx ring\n");
2062                 goto fail;
2063         }
2064
2065         ctx.sk_busaddr = 0;
2066         error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2067             sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2068             SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2069         if (error != 0) {
2070                 device_printf(sc_if->sk_if_dev,
2071                     "failed to load DMA'able memory for Rx ring\n");
2072                 goto fail;
2073         }
2074         sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2075
2076         /* create DMA maps for Tx buffers */
2077         for (i = 0; i < SK_TX_RING_CNT; i++) {
2078                 txd = &sc_if->sk_cdata.sk_txdesc[i];
2079                 txd->tx_m = NULL;
2080                 txd->tx_dmamap = NULL;
2081                 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2082                     &txd->tx_dmamap);
2083                 if (error != 0) {
2084                         device_printf(sc_if->sk_if_dev,
2085                             "failed to create Tx dmamap\n");
2086                         goto fail;
2087                 }
2088         }
2089
2090         /* create DMA maps for Rx buffers */
2091         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2092             &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2093                 device_printf(sc_if->sk_if_dev,
2094                     "failed to create spare Rx dmamap\n");
2095                 goto fail;
2096         }
2097         for (i = 0; i < SK_RX_RING_CNT; i++) {
2098                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2099                 rxd->rx_m = NULL;
2100                 rxd->rx_dmamap = NULL;
2101                 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2102                     &rxd->rx_dmamap);
2103                 if (error != 0) {
2104                         device_printf(sc_if->sk_if_dev,
2105                             "failed to create Rx dmamap\n");
2106                         goto fail;
2107                 }
2108         }
2109
2110 fail:
2111         return (error);
2112 }
2113
2114 static int
2115 sk_dma_jumbo_alloc(sc_if)
2116         struct sk_if_softc      *sc_if;
2117 {
2118         struct sk_dmamap_arg    ctx;
2119         struct sk_rxdesc        *jrxd;
2120         int                     error, i;
2121
2122         if (jumbo_disable != 0) {
2123                 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2124                 sc_if->sk_jumbo_disable = 1;
2125                 return (0);
2126         }
2127         /* create tag for jumbo Rx ring */
2128         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2129                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2130                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2131                     BUS_SPACE_MAXADDR,          /* highaddr */
2132                     NULL, NULL,                 /* filter, filterarg */
2133                     SK_JUMBO_RX_RING_SZ,        /* maxsize */
2134                     1,                          /* nsegments */
2135                     SK_JUMBO_RX_RING_SZ,        /* maxsegsize */
2136                     0,                          /* flags */
2137                     NULL, NULL,                 /* lockfunc, lockarg */
2138                     &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2139         if (error != 0) {
2140                 device_printf(sc_if->sk_if_dev,
2141                     "failed to allocate jumbo Rx ring DMA tag\n");
2142                 goto jumbo_fail;
2143         }
2144
2145         /* create tag for jumbo Rx buffers */
2146         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2147                     1, 0,                       /* algnmnt, boundary */
2148                     BUS_SPACE_MAXADDR,          /* lowaddr */
2149                     BUS_SPACE_MAXADDR,          /* highaddr */
2150                     NULL, NULL,                 /* filter, filterarg */
2151                     MJUM9BYTES,                 /* maxsize */
2152                     1,                          /* nsegments */
2153                     MJUM9BYTES,                 /* maxsegsize */
2154                     0,                          /* flags */
2155                     NULL, NULL,                 /* lockfunc, lockarg */
2156                     &sc_if->sk_cdata.sk_jumbo_rx_tag);
2157         if (error != 0) {
2158                 device_printf(sc_if->sk_if_dev,
2159                     "failed to allocate jumbo Rx DMA tag\n");
2160                 goto jumbo_fail;
2161         }
2162
2163         /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2164         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2165             (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2166             BUS_DMA_COHERENT | BUS_DMA_ZERO,
2167             &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2168         if (error != 0) {
2169                 device_printf(sc_if->sk_if_dev,
2170                     "failed to allocate DMA'able memory for jumbo Rx ring\n");
2171                 goto jumbo_fail;
2172         }
2173
2174         ctx.sk_busaddr = 0;
2175         error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2176             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2177             sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2178             &ctx, BUS_DMA_NOWAIT);
2179         if (error != 0) {
2180                 device_printf(sc_if->sk_if_dev,
2181                     "failed to load DMA'able memory for jumbo Rx ring\n");
2182                 goto jumbo_fail;
2183         }
2184         sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2185
2186         /* create DMA maps for jumbo Rx buffers */
2187         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2188             &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2189                 device_printf(sc_if->sk_if_dev,
2190                     "failed to create spare jumbo Rx dmamap\n");
2191                 goto jumbo_fail;
2192         }
2193         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2194                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2195                 jrxd->rx_m = NULL;
2196                 jrxd->rx_dmamap = NULL;
2197                 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2198                     &jrxd->rx_dmamap);
2199                 if (error != 0) {
2200                         device_printf(sc_if->sk_if_dev,
2201                             "failed to create jumbo Rx dmamap\n");
2202                         goto jumbo_fail;
2203                 }
2204         }
2205
2206         return (0);
2207
2208 jumbo_fail:
2209         sk_dma_jumbo_free(sc_if);
2210         device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2211             "resource shortage\n");
2212         sc_if->sk_jumbo_disable = 1;
2213         return (0);
2214 }
2215
2216 static void
2217 sk_dma_free(sc_if)
2218         struct sk_if_softc      *sc_if;
2219 {
2220         struct sk_txdesc        *txd;
2221         struct sk_rxdesc        *rxd;
2222         int                     i;
2223
2224         /* Tx ring */
2225         if (sc_if->sk_cdata.sk_tx_ring_tag) {
2226                 if (sc_if->sk_cdata.sk_tx_ring_map)
2227                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2228                             sc_if->sk_cdata.sk_tx_ring_map);
2229                 if (sc_if->sk_cdata.sk_tx_ring_map &&
2230                     sc_if->sk_rdata.sk_tx_ring)
2231                         bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2232                             sc_if->sk_rdata.sk_tx_ring,
2233                             sc_if->sk_cdata.sk_tx_ring_map);
2234                 sc_if->sk_rdata.sk_tx_ring = NULL;
2235                 sc_if->sk_cdata.sk_tx_ring_map = NULL;
2236                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2237                 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2238         }
2239         /* Rx ring */
2240         if (sc_if->sk_cdata.sk_rx_ring_tag) {
2241                 if (sc_if->sk_cdata.sk_rx_ring_map)
2242                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2243                             sc_if->sk_cdata.sk_rx_ring_map);
2244                 if (sc_if->sk_cdata.sk_rx_ring_map &&
2245                     sc_if->sk_rdata.sk_rx_ring)
2246                         bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2247                             sc_if->sk_rdata.sk_rx_ring,
2248                             sc_if->sk_cdata.sk_rx_ring_map);
2249                 sc_if->sk_rdata.sk_rx_ring = NULL;
2250                 sc_if->sk_cdata.sk_rx_ring_map = NULL;
2251                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2252                 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2253         }
2254         /* Tx buffers */
2255         if (sc_if->sk_cdata.sk_tx_tag) {
2256                 for (i = 0; i < SK_TX_RING_CNT; i++) {
2257                         txd = &sc_if->sk_cdata.sk_txdesc[i];
2258                         if (txd->tx_dmamap) {
2259                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2260                                     txd->tx_dmamap);
2261                                 txd->tx_dmamap = NULL;
2262                         }
2263                 }
2264                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2265                 sc_if->sk_cdata.sk_tx_tag = NULL;
2266         }
2267         /* Rx buffers */
2268         if (sc_if->sk_cdata.sk_rx_tag) {
2269                 for (i = 0; i < SK_RX_RING_CNT; i++) {
2270                         rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2271                         if (rxd->rx_dmamap) {
2272                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2273                                     rxd->rx_dmamap);
2274                                 rxd->rx_dmamap = NULL;
2275                         }
2276                 }
2277                 if (sc_if->sk_cdata.sk_rx_sparemap) {
2278                         bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2279                             sc_if->sk_cdata.sk_rx_sparemap);
2280                         sc_if->sk_cdata.sk_rx_sparemap = NULL;
2281                 }
2282                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2283                 sc_if->sk_cdata.sk_rx_tag = NULL;
2284         }
2285
2286         if (sc_if->sk_cdata.sk_parent_tag) {
2287                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2288                 sc_if->sk_cdata.sk_parent_tag = NULL;
2289         }
2290 }
2291
2292 static void
2293 sk_dma_jumbo_free(sc_if)
2294         struct sk_if_softc      *sc_if;
2295 {
2296         struct sk_rxdesc        *jrxd;
2297         int                     i;
2298
2299         /* jumbo Rx ring */
2300         if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2301                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2302                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2303                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2304                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2305                     sc_if->sk_rdata.sk_jumbo_rx_ring)
2306                         bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2307                             sc_if->sk_rdata.sk_jumbo_rx_ring,
2308                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2309                 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2310                 sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2311                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2312                 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2313         }
2314
2315         /* jumbo Rx buffers */
2316         if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2317                 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2318                         jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2319                         if (jrxd->rx_dmamap) {
2320                                 bus_dmamap_destroy(
2321                                     sc_if->sk_cdata.sk_jumbo_rx_tag,
2322                                     jrxd->rx_dmamap);
2323                                 jrxd->rx_dmamap = NULL;
2324                         }
2325                 }
2326                 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2327                         bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2328                             sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2329                         sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2330                 }
2331                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2332                 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2333         }
2334 }
2335
2336 static void
2337 sk_txcksum(ifp, m, f)
2338         struct ifnet            *ifp;
2339         struct mbuf             *m;
2340         struct sk_tx_desc       *f;
2341 {
2342         struct ip               *ip;
2343         u_int16_t               offset;
2344         u_int8_t                *p;
2345
2346         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2347         for(; m && m->m_len == 0; m = m->m_next)
2348                 ;
2349         if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2350                 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2351                 /* checksum may be corrupted */
2352                 goto sendit;
2353         }
2354         if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2355                 if (m->m_len != ETHER_HDR_LEN) {
2356                         if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2357                             __func__);
2358                         /* checksum may be corrupted */
2359                         goto sendit;
2360                 }
2361                 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2362                         ;
2363                 if (m == NULL) {
2364                         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2365                         /* checksum may be corrupted */
2366                         goto sendit;
2367                 }
2368                 ip = mtod(m, struct ip *);
2369         } else {
2370                 p = mtod(m, u_int8_t *);
2371                 p += ETHER_HDR_LEN;
2372                 ip = (struct ip *)p;
2373         }
2374         offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2375
2376 sendit:
2377         f->sk_csum_startval = 0;
2378         f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2379             (offset << 16));
2380 }
2381
2382 static int
2383 sk_encap(sc_if, m_head)
2384         struct sk_if_softc      *sc_if;
2385         struct mbuf             **m_head;
2386 {
2387         struct sk_txdesc        *txd;
2388         struct sk_tx_desc       *f = NULL;
2389         struct mbuf             *m;
2390         bus_dma_segment_t       txsegs[SK_MAXTXSEGS];
2391         u_int32_t               cflags, frag, si, sk_ctl;
2392         int                     error, i, nseg;
2393
2394         SK_IF_LOCK_ASSERT(sc_if);
2395
2396         if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2397                 return (ENOBUFS);
2398
2399         error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2400             txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2401         if (error == EFBIG) {
2402                 m = m_defrag(*m_head, M_NOWAIT);
2403                 if (m == NULL) {
2404                         m_freem(*m_head);
2405                         *m_head = NULL;
2406                         return (ENOMEM);
2407                 }
2408                 *m_head = m;
2409                 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2410                     txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2411                 if (error != 0) {
2412                         m_freem(*m_head);
2413                         *m_head = NULL;
2414                         return (error);
2415                 }
2416         } else if (error != 0)
2417                 return (error);
2418         if (nseg == 0) {
2419                 m_freem(*m_head);
2420                 *m_head = NULL;
2421                 return (EIO);
2422         }
2423         if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2424                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2425                 return (ENOBUFS);
2426         }
2427
2428         m = *m_head;
2429         if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2430                 cflags = SK_OPCODE_CSUM;
2431         else
2432                 cflags = SK_OPCODE_DEFAULT;
2433         si = frag = sc_if->sk_cdata.sk_tx_prod;
2434         for (i = 0; i < nseg; i++) {
2435                 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2436                 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2437                 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2438                 sk_ctl = txsegs[i].ds_len | cflags;
2439                 if (i == 0) {
2440                         if (cflags == SK_OPCODE_CSUM)
2441                                 sk_txcksum(sc_if->sk_ifp, m, f);
2442                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
2443                 } else
2444                         sk_ctl |= SK_TXCTL_OWN;
2445                 f->sk_ctl = htole32(sk_ctl);
2446                 sc_if->sk_cdata.sk_tx_cnt++;
2447                 SK_INC(frag, SK_TX_RING_CNT);
2448         }
2449         sc_if->sk_cdata.sk_tx_prod = frag;
2450
2451         /* set EOF on the last desciptor */
2452         frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2453         f = &sc_if->sk_rdata.sk_tx_ring[frag];
2454         f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2455
2456         /* turn the first descriptor ownership to NIC */
2457         f = &sc_if->sk_rdata.sk_tx_ring[si];
2458         f->sk_ctl |= htole32(SK_TXCTL_OWN);
2459
2460         STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2461         STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2462         txd->tx_m = m;
2463
2464         /* sync descriptors */
2465         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2466             BUS_DMASYNC_PREWRITE);
2467         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2468             sc_if->sk_cdata.sk_tx_ring_map,
2469             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2470
2471         return (0);
2472 }
2473
2474 static void
2475 sk_start(ifp)
2476         struct ifnet            *ifp;
2477 {
2478         struct sk_if_softc *sc_if;
2479
2480         sc_if = ifp->if_softc;
2481
2482         SK_IF_LOCK(sc_if);
2483         sk_start_locked(ifp);
2484         SK_IF_UNLOCK(sc_if);
2485
2486         return;
2487 }
2488
2489 static void
2490 sk_start_locked(ifp)
2491         struct ifnet            *ifp;
2492 {
2493         struct sk_softc         *sc;
2494         struct sk_if_softc      *sc_if;
2495         struct mbuf             *m_head;
2496         int                     enq;
2497
2498         sc_if = ifp->if_softc;
2499         sc = sc_if->sk_softc;
2500
2501         SK_IF_LOCK_ASSERT(sc_if);
2502
2503         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2504             sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2505                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2506                 if (m_head == NULL)
2507                         break;
2508
2509                 /*
2510                  * Pack the data into the transmit ring. If we
2511                  * don't have room, set the OACTIVE flag and wait
2512                  * for the NIC to drain the ring.
2513                  */
2514                 if (sk_encap(sc_if, &m_head)) {
2515                         if (m_head == NULL)
2516                                 break;
2517                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2518                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2519                         break;
2520                 }
2521
2522                 enq++;
2523                 /*
2524                  * If there's a BPF listener, bounce a copy of this frame
2525                  * to him.
2526                  */
2527                 BPF_MTAP(ifp, m_head);
2528         }
2529
2530         if (enq > 0) {
2531                 /* Transmit */
2532                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2533
2534                 /* Set a timeout in case the chip goes out to lunch. */
2535                 sc_if->sk_watchdog_timer = 5;
2536         }
2537 }
2538
2539
2540 static void
2541 sk_watchdog(arg)
2542         void                    *arg;
2543 {
2544         struct sk_if_softc      *sc_if;
2545         struct ifnet            *ifp;
2546
2547         ifp = arg;
2548         sc_if = ifp->if_softc;
2549
2550         SK_IF_LOCK_ASSERT(sc_if);
2551
2552         if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2553                 goto done;
2554
2555         /*
2556          * Reclaim first as there is a possibility of losing Tx completion
2557          * interrupts.
2558          */
2559         sk_txeof(sc_if);
2560         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2561                 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2562                 ifp->if_oerrors++;
2563                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2564                 sk_init_locked(sc_if);
2565         }
2566
2567 done:
2568         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2569
2570         return;
2571 }
2572
2573 static int
2574 skc_shutdown(dev)
2575         device_t                dev;
2576 {
2577         struct sk_softc         *sc;
2578
2579         sc = device_get_softc(dev);
2580         SK_LOCK(sc);
2581
2582         /* Turn off the 'driver is loaded' LED. */
2583         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2584
2585         /*
2586          * Reset the GEnesis controller. Doing this should also
2587          * assert the resets on the attached XMAC(s).
2588          */
2589         sk_reset(sc);
2590         SK_UNLOCK(sc);
2591
2592         return (0);
2593 }
2594
2595 static int
2596 skc_suspend(dev)
2597         device_t                dev;
2598 {
2599         struct sk_softc         *sc;
2600         struct sk_if_softc      *sc_if0, *sc_if1;
2601         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2602
2603         sc = device_get_softc(dev);
2604
2605         SK_LOCK(sc);
2606
2607         sc_if0 = sc->sk_if[SK_PORT_A];
2608         sc_if1 = sc->sk_if[SK_PORT_B];
2609         if (sc_if0 != NULL)
2610                 ifp0 = sc_if0->sk_ifp;
2611         if (sc_if1 != NULL)
2612                 ifp1 = sc_if1->sk_ifp;
2613         if (ifp0 != NULL)
2614                 sk_stop(sc_if0);
2615         if (ifp1 != NULL)
2616                 sk_stop(sc_if1);
2617         sc->sk_suspended = 1;
2618
2619         SK_UNLOCK(sc);
2620
2621         return (0);
2622 }
2623
2624 static int
2625 skc_resume(dev)
2626         device_t                dev;
2627 {
2628         struct sk_softc         *sc;
2629         struct sk_if_softc      *sc_if0, *sc_if1;
2630         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2631
2632         sc = device_get_softc(dev);
2633
2634         SK_LOCK(sc);
2635
2636         sc_if0 = sc->sk_if[SK_PORT_A];
2637         sc_if1 = sc->sk_if[SK_PORT_B];
2638         if (sc_if0 != NULL)
2639                 ifp0 = sc_if0->sk_ifp;
2640         if (sc_if1 != NULL)
2641                 ifp1 = sc_if1->sk_ifp;
2642         if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2643                 sk_init_locked(sc_if0);
2644         if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2645                 sk_init_locked(sc_if1);
2646         sc->sk_suspended = 0;
2647
2648         SK_UNLOCK(sc);
2649
2650         return (0);
2651 }
2652
2653 /*
2654  * According to the data sheet from SK-NET GENESIS the hardware can compute
2655  * two Rx checksums at the same time(Each checksum start position is
2656  * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2657  * does not work at least on my Yukon hardware. I tried every possible ways
2658  * to get correct checksum value but couldn't get correct one. So TCP/UDP
2659  * checksum offload was disabled at the moment and only IP checksum offload
2660  * was enabled.
2661  * As nomral IP header size is 20 bytes I can't expect it would give an
2662  * increase in throughput. However it seems it doesn't hurt performance in
2663  * my testing. If there is a more detailed information for checksum secret
2664  * of the hardware in question please contact yongari@FreeBSD.org to add
2665  * TCP/UDP checksum offload support.
2666  */
2667 static __inline void
2668 sk_rxcksum(ifp, m, csum)
2669         struct ifnet            *ifp;
2670         struct mbuf             *m;
2671         u_int32_t               csum;
2672 {
2673         struct ether_header     *eh;
2674         struct ip               *ip;
2675         int32_t                 hlen, len, pktlen;
2676         u_int16_t               csum1, csum2, ipcsum;
2677
2678         pktlen = m->m_pkthdr.len;
2679         if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2680                 return;
2681         eh = mtod(m, struct ether_header *);
2682         if (eh->ether_type != htons(ETHERTYPE_IP))
2683                 return;
2684         ip = (struct ip *)(eh + 1);
2685         if (ip->ip_v != IPVERSION)
2686                 return;
2687         hlen = ip->ip_hl << 2;
2688         pktlen -= sizeof(struct ether_header);
2689         if (hlen < sizeof(struct ip))
2690                 return;
2691         if (ntohs(ip->ip_len) < hlen)
2692                 return;
2693         if (ntohs(ip->ip_len) != pktlen)
2694                 return;
2695
2696         csum1 = htons(csum & 0xffff);
2697         csum2 = htons((csum >> 16) & 0xffff);
2698         ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2699         /* checksum fixup for IP options */
2700         len = hlen - sizeof(struct ip);
2701         if (len > 0) {
2702                 /*
2703                  * If the second checksum value is correct we can compute IP
2704                  * checksum with simple math. Unfortunately the second checksum
2705                  * value is wrong so we can't verify the checksum from the
2706                  * value(It seems there is some magic here to get correct
2707                  * value). If the second checksum value is correct it also
2708                  * means we can get TCP/UDP checksum) here. However, it still
2709                  * needs pseudo header checksum calculation due to hardware
2710                  * limitations.
2711                  */
2712                 return;
2713         }
2714         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2715         if (ipcsum == 0xffff)
2716                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2717 }
2718
2719 static __inline int
2720 sk_rxvalid(sc, stat, len)
2721         struct sk_softc         *sc;
2722         u_int32_t               stat, len;
2723 {
2724
2725         if (sc->sk_type == SK_GENESIS) {
2726                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2727                     XM_RXSTAT_BYTES(stat) != len)
2728                         return (0);
2729         } else {
2730                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2731                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2732                     YU_RXSTAT_JABBER)) != 0 ||
2733                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2734                     YU_RXSTAT_BYTES(stat) != len)
2735                         return (0);
2736         }
2737
2738         return (1);
2739 }
2740
2741 static void
2742 sk_rxeof(sc_if)
2743         struct sk_if_softc      *sc_if;
2744 {
2745         struct sk_softc         *sc;
2746         struct mbuf             *m;
2747         struct ifnet            *ifp;
2748         struct sk_rx_desc       *cur_rx;
2749         struct sk_rxdesc        *rxd;
2750         int                     cons, prog;
2751         u_int32_t               csum, rxstat, sk_ctl;
2752
2753         sc = sc_if->sk_softc;
2754         ifp = sc_if->sk_ifp;
2755
2756         SK_IF_LOCK_ASSERT(sc_if);
2757
2758         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2759             sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2760
2761         prog = 0;
2762         for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2763             prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2764                 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2765                 sk_ctl = le32toh(cur_rx->sk_ctl);
2766                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2767                         break;
2768                 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2769                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2770
2771                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2772                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2773                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2774                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2775                     SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2776                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2777                         ifp->if_ierrors++;
2778                         sk_discard_rxbuf(sc_if, cons);
2779                         continue;
2780                 }
2781
2782                 m = rxd->rx_m;
2783                 csum = le32toh(cur_rx->sk_csum);
2784                 if (sk_newbuf(sc_if, cons) != 0) {
2785                         ifp->if_iqdrops++;
2786                         /* reuse old buffer */
2787                         sk_discard_rxbuf(sc_if, cons);
2788                         continue;
2789                 }
2790                 m->m_pkthdr.rcvif = ifp;
2791                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2792                 ifp->if_ipackets++;
2793                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2794                         sk_rxcksum(ifp, m, csum);
2795                 SK_IF_UNLOCK(sc_if);
2796                 (*ifp->if_input)(ifp, m);
2797                 SK_IF_LOCK(sc_if);
2798         }
2799
2800         if (prog > 0) {
2801                 sc_if->sk_cdata.sk_rx_cons = cons;
2802                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2803                     sc_if->sk_cdata.sk_rx_ring_map,
2804                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2805         }
2806 }
2807
2808 static void
2809 sk_jumbo_rxeof(sc_if)
2810         struct sk_if_softc      *sc_if;
2811 {
2812         struct sk_softc         *sc;
2813         struct mbuf             *m;
2814         struct ifnet            *ifp;
2815         struct sk_rx_desc       *cur_rx;
2816         struct sk_rxdesc        *jrxd;
2817         int                     cons, prog;
2818         u_int32_t               csum, rxstat, sk_ctl;
2819
2820         sc = sc_if->sk_softc;
2821         ifp = sc_if->sk_ifp;
2822
2823         SK_IF_LOCK_ASSERT(sc_if);
2824
2825         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2826             sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2827
2828         prog = 0;
2829         for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2830             prog < SK_JUMBO_RX_RING_CNT;
2831             prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2832                 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2833                 sk_ctl = le32toh(cur_rx->sk_ctl);
2834                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2835                         break;
2836                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2837                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2838
2839                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2840                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2841                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2842                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2843                     SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2844                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2845                         ifp->if_ierrors++;
2846                         sk_discard_jumbo_rxbuf(sc_if, cons);
2847                         continue;
2848                 }
2849
2850                 m = jrxd->rx_m;
2851                 csum = le32toh(cur_rx->sk_csum);
2852                 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2853                         ifp->if_iqdrops++;
2854                         /* reuse old buffer */
2855                         sk_discard_jumbo_rxbuf(sc_if, cons);
2856                         continue;
2857                 }
2858                 m->m_pkthdr.rcvif = ifp;
2859                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2860                 ifp->if_ipackets++;
2861                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2862                         sk_rxcksum(ifp, m, csum);
2863                 SK_IF_UNLOCK(sc_if);
2864                 (*ifp->if_input)(ifp, m);
2865                 SK_IF_LOCK(sc_if);
2866         }
2867
2868         if (prog > 0) {
2869                 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2870                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2871                     sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2872                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2873         }
2874 }
2875
2876 static void
2877 sk_txeof(sc_if)
2878         struct sk_if_softc      *sc_if;
2879 {
2880         struct sk_txdesc        *txd;
2881         struct sk_tx_desc       *cur_tx;
2882         struct ifnet            *ifp;
2883         u_int32_t               idx, sk_ctl;
2884
2885         ifp = sc_if->sk_ifp;
2886
2887         txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2888         if (txd == NULL)
2889                 return;
2890         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2891             sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2892         /*
2893          * Go through our tx ring and free mbufs for those
2894          * frames that have been sent.
2895          */
2896         for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2897                 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2898                         break;
2899                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2900                 sk_ctl = le32toh(cur_tx->sk_ctl);
2901                 if (sk_ctl & SK_TXCTL_OWN)
2902                         break;
2903                 sc_if->sk_cdata.sk_tx_cnt--;
2904                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2905                 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2906                         continue;
2907                 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2908                     BUS_DMASYNC_POSTWRITE);
2909                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2910
2911                 ifp->if_opackets++;
2912                 m_freem(txd->tx_m);
2913                 txd->tx_m = NULL;
2914                 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2915                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2916                 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2917         }
2918         sc_if->sk_cdata.sk_tx_cons = idx;
2919         sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2920
2921         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2922             sc_if->sk_cdata.sk_tx_ring_map,
2923             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2924 }
2925
2926 static void
2927 sk_tick(xsc_if)
2928         void                    *xsc_if;
2929 {
2930         struct sk_if_softc      *sc_if;
2931         struct mii_data         *mii;
2932         struct ifnet            *ifp;
2933         int                     i;
2934
2935         sc_if = xsc_if;
2936         ifp = sc_if->sk_ifp;
2937         mii = device_get_softc(sc_if->sk_miibus);
2938
2939         if (!(ifp->if_flags & IFF_UP))
2940                 return;
2941
2942         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2943                 sk_intr_bcom(sc_if);
2944                 return;
2945         }
2946
2947         /*
2948          * According to SysKonnect, the correct way to verify that
2949          * the link has come back up is to poll bit 0 of the GPIO
2950          * register three times. This pin has the signal from the
2951          * link_sync pin connected to it; if we read the same link
2952          * state 3 times in a row, we know the link is up.
2953          */
2954         for (i = 0; i < 3; i++) {
2955                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2956                         break;
2957         }
2958
2959         if (i != 3) {
2960                 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2961                 return;
2962         }
2963
2964         /* Turn the GP0 interrupt back on. */
2965         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2966         SK_XM_READ_2(sc_if, XM_ISR);
2967         mii_tick(mii);
2968         callout_stop(&sc_if->sk_tick_ch);
2969 }
2970
2971 static void
2972 sk_yukon_tick(xsc_if)
2973         void                    *xsc_if;
2974 {
2975         struct sk_if_softc      *sc_if;
2976         struct mii_data         *mii;
2977
2978         sc_if = xsc_if;
2979         mii = device_get_softc(sc_if->sk_miibus);
2980
2981         mii_tick(mii);
2982         callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2983 }
2984
2985 static void
2986 sk_intr_bcom(sc_if)
2987         struct sk_if_softc      *sc_if;
2988 {
2989         struct mii_data         *mii;
2990         struct ifnet            *ifp;
2991         int                     status;
2992         mii = device_get_softc(sc_if->sk_miibus);
2993         ifp = sc_if->sk_ifp;
2994
2995         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2996
2997         /*
2998          * Read the PHY interrupt register to make sure
2999          * we clear any pending interrupts.
3000          */
3001         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3002
3003         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3004                 sk_init_xmac(sc_if);
3005                 return;
3006         }
3007
3008         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3009                 int                     lstat;
3010                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3011                     BRGPHY_MII_AUXSTS);
3012
3013                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3014                         mii_mediachg(mii);
3015                         /* Turn off the link LED. */
3016                         SK_IF_WRITE_1(sc_if, 0,
3017                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
3018                         sc_if->sk_link = 0;
3019                 } else if (status & BRGPHY_ISR_LNK_CHG) {
3020                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3021                             BRGPHY_MII_IMR, 0xFF00);
3022                         mii_tick(mii);
3023                         sc_if->sk_link = 1;
3024                         /* Turn on the link LED. */
3025                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3026                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3027                             SK_LINKLED_BLINK_OFF);
3028                 } else {
3029                         mii_tick(mii);
3030                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3031                 }
3032         }
3033
3034         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3035
3036         return;
3037 }
3038
3039 static void
3040 sk_intr_xmac(sc_if)
3041         struct sk_if_softc      *sc_if;
3042 {
3043         struct sk_softc         *sc;
3044         u_int16_t               status;
3045
3046         sc = sc_if->sk_softc;
3047         status = SK_XM_READ_2(sc_if, XM_ISR);
3048
3049         /*
3050          * Link has gone down. Start MII tick timeout to
3051          * watch for link resync.
3052          */
3053         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3054                 if (status & XM_ISR_GP0_SET) {
3055                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3056                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3057                 }
3058
3059                 if (status & XM_ISR_AUTONEG_DONE) {
3060                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3061                 }
3062         }
3063
3064         if (status & XM_IMR_TX_UNDERRUN)
3065                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3066
3067         if (status & XM_IMR_RX_OVERRUN)
3068                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3069
3070         status = SK_XM_READ_2(sc_if, XM_ISR);
3071
3072         return;
3073 }
3074
3075 static void
3076 sk_intr_yukon(sc_if)
3077         struct sk_if_softc      *sc_if;
3078 {
3079         u_int8_t status;
3080
3081         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3082         /* RX overrun */
3083         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3084                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3085                     SK_RFCTL_RX_FIFO_OVER);
3086         }
3087         /* TX underrun */
3088         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3089                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3090                     SK_TFCTL_TX_FIFO_UNDER);
3091         }
3092 }
3093
3094 static void
3095 sk_intr(xsc)
3096         void                    *xsc;
3097 {
3098         struct sk_softc         *sc = xsc;
3099         struct sk_if_softc      *sc_if0, *sc_if1;
3100         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
3101         u_int32_t               status;
3102
3103         SK_LOCK(sc);
3104
3105         status = CSR_READ_4(sc, SK_ISSR);
3106         if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3107                 goto done_locked;
3108
3109         sc_if0 = sc->sk_if[SK_PORT_A];
3110         sc_if1 = sc->sk_if[SK_PORT_B];
3111
3112         if (sc_if0 != NULL)
3113                 ifp0 = sc_if0->sk_ifp;
3114         if (sc_if1 != NULL)
3115                 ifp1 = sc_if1->sk_ifp;
3116
3117         for (; (status &= sc->sk_intrmask) != 0;) {
3118                 /* Handle receive interrupts first. */
3119                 if (status & SK_ISR_RX1_EOF) {
3120                         if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3121                                 sk_jumbo_rxeof(sc_if0);
3122                         else
3123                                 sk_rxeof(sc_if0);
3124                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3125                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3126                 }
3127                 if (status & SK_ISR_RX2_EOF) {
3128                         if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3129                                 sk_jumbo_rxeof(sc_if1);
3130                         else
3131                                 sk_rxeof(sc_if1);
3132                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3133                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3134                 }
3135
3136                 /* Then transmit interrupts. */
3137                 if (status & SK_ISR_TX1_S_EOF) {
3138                         sk_txeof(sc_if0);
3139                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3140                 }
3141                 if (status & SK_ISR_TX2_S_EOF) {
3142                         sk_txeof(sc_if1);
3143                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3144                 }
3145
3146                 /* Then MAC interrupts. */
3147                 if (status & SK_ISR_MAC1 &&
3148                     ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3149                         if (sc->sk_type == SK_GENESIS)
3150                                 sk_intr_xmac(sc_if0);
3151                         else
3152                                 sk_intr_yukon(sc_if0);
3153                 }
3154
3155                 if (status & SK_ISR_MAC2 &&
3156                     ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3157                         if (sc->sk_type == SK_GENESIS)
3158                                 sk_intr_xmac(sc_if1);
3159                         else
3160                                 sk_intr_yukon(sc_if1);
3161                 }
3162
3163                 if (status & SK_ISR_EXTERNAL_REG) {
3164                         if (ifp0 != NULL &&
3165                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3166                                 sk_intr_bcom(sc_if0);
3167                         if (ifp1 != NULL &&
3168                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3169                                 sk_intr_bcom(sc_if1);
3170                 }
3171                 status = CSR_READ_4(sc, SK_ISSR);
3172         }
3173
3174         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3175
3176         if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3177                 sk_start_locked(ifp0);
3178         if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3179                 sk_start_locked(ifp1);
3180
3181 done_locked:
3182         SK_UNLOCK(sc);
3183 }
3184
3185 static void
3186 sk_init_xmac(sc_if)
3187         struct sk_if_softc      *sc_if;
3188 {
3189         struct sk_softc         *sc;
3190         struct ifnet            *ifp;
3191         u_int16_t               eaddr[(ETHER_ADDR_LEN+1)/2];
3192         static const struct sk_bcom_hack bhack[] = {
3193         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3194         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3195         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3196         { 0, 0 } };
3197
3198         SK_IF_LOCK_ASSERT(sc_if);
3199
3200         sc = sc_if->sk_softc;
3201         ifp = sc_if->sk_ifp;
3202
3203         /* Unreset the XMAC. */
3204         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3205         DELAY(1000);
3206
3207         /* Reset the XMAC's internal state. */
3208         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3209
3210         /* Save the XMAC II revision */
3211         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3212
3213         /*
3214          * Perform additional initialization for external PHYs,
3215          * namely for the 1000baseTX cards that use the XMAC's
3216          * GMII mode.
3217          */
3218         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3219                 int                     i = 0;
3220                 u_int32_t               val;
3221
3222                 /* Take PHY out of reset. */
3223                 val = sk_win_read_4(sc, SK_GPIO);
3224                 if (sc_if->sk_port == SK_PORT_A)
3225                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3226                 else
3227                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3228                 sk_win_write_4(sc, SK_GPIO, val);
3229
3230                 /* Enable GMII mode on the XMAC. */
3231                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3232
3233                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3234                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3235                 DELAY(10000);
3236                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3237                     BRGPHY_MII_IMR, 0xFFF0);
3238
3239                 /*
3240                  * Early versions of the BCM5400 apparently have
3241                  * a bug that requires them to have their reserved
3242                  * registers initialized to some magic values. I don't
3243                  * know what the numbers do, I'm just the messenger.
3244                  */
3245                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3246                     == 0x6041) {
3247                         while(bhack[i].reg) {
3248                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3249                                     bhack[i].reg, bhack[i].val);
3250                                 i++;
3251                         }
3252                 }
3253         }
3254
3255         /* Set station address */
3256         bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3257         SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3258         SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3259         SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3260         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3261
3262         if (ifp->if_flags & IFF_BROADCAST) {
3263                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3264         } else {
3265                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3266         }
3267
3268         /* We don't need the FCS appended to the packet. */
3269         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3270
3271         /* We want short frames padded to 60 bytes. */
3272         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3273
3274         /*
3275          * Enable the reception of all error frames. This is is
3276          * a necessary evil due to the design of the XMAC. The
3277          * XMAC's receive FIFO is only 8K in size, however jumbo
3278          * frames can be up to 9000 bytes in length. When bad
3279          * frame filtering is enabled, the XMAC's RX FIFO operates
3280          * in 'store and forward' mode. For this to work, the
3281          * entire frame has to fit into the FIFO, but that means
3282          * that jumbo frames larger than 8192 bytes will be
3283          * truncated. Disabling all bad frame filtering causes
3284          * the RX FIFO to operate in streaming mode, in which
3285          * case the XMAC will start transfering frames out of the
3286          * RX FIFO as soon as the FIFO threshold is reached.
3287          */
3288         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3289                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3290                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3291                     XM_MODE_RX_INRANGELEN);
3292                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3293         } else
3294                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3295
3296         /*
3297          * Bump up the transmit threshold. This helps hold off transmit
3298          * underruns when we're blasting traffic from both ports at once.
3299          */
3300         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3301
3302         /* Set Rx filter */
3303         sk_rxfilter_genesis(sc_if);
3304
3305         /* Clear and enable interrupts */
3306         SK_XM_READ_2(sc_if, XM_ISR);
3307         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3308                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3309         else
3310                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3311
3312         /* Configure MAC arbiter */
3313         switch(sc_if->sk_xmac_rev) {
3314         case XM_XMAC_REV_B2:
3315                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3316                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3317                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3318                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3319                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3320                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3321                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3322                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3323                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3324                 break;
3325         case XM_XMAC_REV_C1:
3326                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3327                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3328                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3329                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3330                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3331                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3332                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3333                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3334                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3335                 break;
3336         default:
3337                 break;
3338         }
3339         sk_win_write_2(sc, SK_MACARB_CTL,
3340             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3341
3342         sc_if->sk_link = 1;
3343
3344         return;
3345 }
3346
3347 static void
3348 sk_init_yukon(sc_if)
3349         struct sk_if_softc      *sc_if;
3350 {
3351         u_int32_t               phy, v;
3352         u_int16_t               reg;
3353         struct sk_softc         *sc;
3354         struct ifnet            *ifp;
3355         u_int8_t                *eaddr;
3356         int                     i;
3357
3358         SK_IF_LOCK_ASSERT(sc_if);
3359
3360         sc = sc_if->sk_softc;
3361         ifp = sc_if->sk_ifp;
3362
3363         if (sc->sk_type == SK_YUKON_LITE &&
3364             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3365                 /*
3366                  * Workaround code for COMA mode, set PHY reset.
3367                  * Otherwise it will not correctly take chip out of
3368                  * powerdown (coma)
3369                  */
3370                 v = sk_win_read_4(sc, SK_GPIO);
3371                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3372                 sk_win_write_4(sc, SK_GPIO, v);
3373         }
3374
3375         /* GMAC and GPHY Reset */
3376         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3377         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3378         DELAY(1000);
3379
3380         if (sc->sk_type == SK_YUKON_LITE &&
3381             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3382                 /*
3383                  * Workaround code for COMA mode, clear PHY reset
3384                  */
3385                 v = sk_win_read_4(sc, SK_GPIO);
3386                 v |= SK_GPIO_DIR9;
3387                 v &= ~SK_GPIO_DAT9;
3388                 sk_win_write_4(sc, SK_GPIO, v);
3389         }
3390
3391         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3392                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3393
3394         if (sc->sk_coppertype)
3395                 phy |= SK_GPHY_COPPER;
3396         else
3397                 phy |= SK_GPHY_FIBER;
3398
3399         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3400         DELAY(1000);
3401         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3402         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3403                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3404
3405         /* unused read of the interrupt source register */
3406         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3407
3408         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3409
3410         /* MIB Counter Clear Mode set */
3411         reg |= YU_PAR_MIB_CLR;
3412         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3413
3414         /* MIB Counter Clear Mode clear */
3415         reg &= ~YU_PAR_MIB_CLR;
3416         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3417
3418         /* receive control reg */
3419         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3420
3421         /* transmit parameter register */
3422         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3423                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3424
3425         /* serial mode register */
3426         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3427         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3428                 reg |= YU_SMR_MFL_JUMBO;
3429         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3430
3431         /* Setup Yukon's station address */
3432         eaddr = IF_LLADDR(sc_if->sk_ifp);
3433         for (i = 0; i < 3; i++)
3434                 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3435                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3436         /* Set GMAC source address of flow control. */
3437         for (i = 0; i < 3; i++)
3438                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3439                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3440         /* Set GMAC virtual address. */
3441         for (i = 0; i < 3; i++)
3442                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3443                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3444
3445         /* Set Rx filter */
3446         sk_rxfilter_yukon(sc_if);
3447
3448         /* enable interrupt mask for counter overflows */
3449         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3450         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3451         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3452
3453         /* Configure RX MAC FIFO Flush Mask */
3454         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3455             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3456             YU_RXSTAT_JABBER;
3457         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3458
3459         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3460         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3461                 v = SK_TFCTL_OPERATION_ON;
3462         else
3463                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3464         /* Configure RX MAC FIFO */
3465         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3466         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3467
3468         /* Increase flush threshould to 64 bytes */
3469         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3470             SK_RFCTL_FIFO_THRESHOLD + 1);
3471
3472         /* Configure TX MAC FIFO */
3473         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3474         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3475 }
3476
3477 /*
3478  * Note that to properly initialize any part of the GEnesis chip,
3479  * you first have to take it out of reset mode.
3480  */
3481 static void
3482 sk_init(xsc)
3483         void                    *xsc;
3484 {
3485         struct sk_if_softc      *sc_if = xsc;
3486
3487         SK_IF_LOCK(sc_if);
3488         sk_init_locked(sc_if);
3489         SK_IF_UNLOCK(sc_if);
3490
3491         return;
3492 }
3493
3494 static void
3495 sk_init_locked(sc_if)
3496         struct sk_if_softc      *sc_if;
3497 {
3498         struct sk_softc         *sc;
3499         struct ifnet            *ifp;
3500         struct mii_data         *mii;
3501         u_int16_t               reg;
3502         u_int32_t               imr;
3503         int                     error;
3504
3505         SK_IF_LOCK_ASSERT(sc_if);
3506
3507         ifp = sc_if->sk_ifp;
3508         sc = sc_if->sk_softc;
3509         mii = device_get_softc(sc_if->sk_miibus);
3510
3511         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3512                 return;
3513
3514         /* Cancel pending I/O and free all RX/TX buffers. */
3515         sk_stop(sc_if);
3516
3517         if (sc->sk_type == SK_GENESIS) {
3518                 /* Configure LINK_SYNC LED */
3519                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3520                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3521                         SK_LINKLED_LINKSYNC_ON);
3522
3523                 /* Configure RX LED */
3524                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3525                         SK_RXLEDCTL_COUNTER_START);
3526
3527                 /* Configure TX LED */
3528                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3529                         SK_TXLEDCTL_COUNTER_START);
3530         }
3531
3532         /*
3533          * Configure descriptor poll timer
3534          *
3535          * SK-NET GENESIS data sheet says that possibility of losing Start
3536          * transmit command due to CPU/cache related interim storage problems
3537          * under certain conditions. The document recommends a polling
3538          * mechanism to send a Start transmit command to initiate transfer
3539          * of ready descriptors regulary. To cope with this issue sk(4) now
3540          * enables descriptor poll timer to initiate descriptor processing
3541          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3542          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3543          * command instead of waiting for next descriptor polling time.
3544          * The same rule may apply to Rx side too but it seems that is not
3545          * needed at the moment.
3546          * Since sk(4) uses descriptor polling as a last resort there is no
3547          * need to set smaller polling time than maximum allowable one.
3548          */
3549         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3550
3551         /* Configure I2C registers */
3552
3553         /* Configure XMAC(s) */
3554         switch (sc->sk_type) {
3555         case SK_GENESIS:
3556                 sk_init_xmac(sc_if);
3557                 break;
3558         case SK_YUKON:
3559         case SK_YUKON_LITE:
3560         case SK_YUKON_LP:
3561                 sk_init_yukon(sc_if);
3562                 break;
3563         }
3564         mii_mediachg(mii);
3565
3566         if (sc->sk_type == SK_GENESIS) {
3567                 /* Configure MAC FIFOs */
3568                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3569                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3570                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3571
3572                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3573                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3574                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3575         }
3576
3577         /* Configure transmit arbiter(s) */
3578         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3579             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3580
3581         /* Configure RAMbuffers */
3582         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3583         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3584         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3585         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3586         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3587         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3588
3589         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3590         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3591         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3592         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3593         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3594         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3595         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3596
3597         /* Configure BMUs */
3598         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3599         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3600                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3601                     SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3602                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3603                     SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3604         } else {
3605                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3606                     SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3607                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3608                     SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3609         }
3610
3611         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3612         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3613             SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3614         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3615             SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3616
3617         /* Init descriptors */
3618         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3619                 error = sk_init_jumbo_rx_ring(sc_if);
3620         else
3621                 error = sk_init_rx_ring(sc_if);
3622         if (error != 0) {
3623                 device_printf(sc_if->sk_if_dev,
3624                     "initialization failed: no memory for rx buffers\n");
3625                 sk_stop(sc_if);
3626                 return;
3627         }
3628         sk_init_tx_ring(sc_if);
3629
3630         /* Set interrupt moderation if changed via sysctl. */
3631         imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3632         if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3633                 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3634                     sc->sk_int_ticks));
3635                 if (bootverbose)
3636                         device_printf(sc_if->sk_if_dev,
3637                             "interrupt moderation is %d us.\n",
3638                             sc->sk_int_mod);
3639         }
3640
3641         /* Configure interrupt handling */
3642         CSR_READ_4(sc, SK_ISSR);
3643         if (sc_if->sk_port == SK_PORT_A)
3644                 sc->sk_intrmask |= SK_INTRS1;
3645         else
3646                 sc->sk_intrmask |= SK_INTRS2;
3647
3648         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3649
3650         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3651
3652         /* Start BMUs. */
3653         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3654
3655         switch(sc->sk_type) {
3656         case SK_GENESIS:
3657                 /* Enable XMACs TX and RX state machines */
3658                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3659                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3660                 break;
3661         case SK_YUKON:
3662         case SK_YUKON_LITE:
3663         case SK_YUKON_LP:
3664                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3665                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3666 #if 0
3667                 /* XXX disable 100Mbps and full duplex mode? */
3668                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3669 #endif
3670                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3671         }
3672
3673         /* Activate descriptor polling timer */
3674         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3675         /* start transfer of Tx descriptors */
3676         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3677
3678         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3679         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3680
3681         switch (sc->sk_type) {
3682         case SK_YUKON:
3683         case SK_YUKON_LITE:
3684         case SK_YUKON_LP:
3685                 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3686                 break;
3687         }
3688
3689         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3690
3691         return;
3692 }
3693
3694 static void
3695 sk_stop(sc_if)
3696         struct sk_if_softc      *sc_if;
3697 {
3698         int                     i;
3699         struct sk_softc         *sc;
3700         struct sk_txdesc        *txd;
3701         struct sk_rxdesc        *rxd;
3702         struct sk_rxdesc        *jrxd;
3703         struct ifnet            *ifp;
3704         u_int32_t               val;
3705
3706         SK_IF_LOCK_ASSERT(sc_if);
3707         sc = sc_if->sk_softc;
3708         ifp = sc_if->sk_ifp;
3709
3710         callout_stop(&sc_if->sk_tick_ch);
3711         callout_stop(&sc_if->sk_watchdog_ch);
3712
3713         /* stop Tx descriptor polling timer */
3714         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3715         /* stop transfer of Tx descriptors */
3716         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3717         for (i = 0; i < SK_TIMEOUT; i++) {
3718                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3719                 if ((val & SK_TXBMU_TX_STOP) == 0)
3720                         break;
3721                 DELAY(1);
3722         }
3723         if (i == SK_TIMEOUT)
3724                 device_printf(sc_if->sk_if_dev,
3725                     "can not stop transfer of Tx descriptor\n");
3726         /* stop transfer of Rx descriptors */
3727         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3728         for (i = 0; i < SK_TIMEOUT; i++) {
3729                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3730                 if ((val & SK_RXBMU_RX_STOP) == 0)
3731                         break;
3732                 DELAY(1);
3733         }
3734         if (i == SK_TIMEOUT)
3735                 device_printf(sc_if->sk_if_dev,
3736                     "can not stop transfer of Rx descriptor\n");
3737
3738         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3739                 /* Put PHY back into reset. */
3740                 val = sk_win_read_4(sc, SK_GPIO);
3741                 if (sc_if->sk_port == SK_PORT_A) {
3742                         val |= SK_GPIO_DIR0;
3743                         val &= ~SK_GPIO_DAT0;
3744                 } else {
3745                         val |= SK_GPIO_DIR2;
3746                         val &= ~SK_GPIO_DAT2;
3747                 }
3748                 sk_win_write_4(sc, SK_GPIO, val);
3749         }
3750
3751         /* Turn off various components of this interface. */
3752         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3753         switch (sc->sk_type) {
3754         case SK_GENESIS:
3755                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3756                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3757                 break;
3758         case SK_YUKON:
3759         case SK_YUKON_LITE:
3760         case SK_YUKON_LP:
3761                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3762                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3763                 break;
3764         }
3765         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3766         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3767         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3768         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3769         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3770         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3771         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3772         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3773         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3774
3775         /* Disable interrupts */
3776         if (sc_if->sk_port == SK_PORT_A)
3777                 sc->sk_intrmask &= ~SK_INTRS1;
3778         else
3779                 sc->sk_intrmask &= ~SK_INTRS2;
3780         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3781
3782         SK_XM_READ_2(sc_if, XM_ISR);
3783         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3784
3785         /* Free RX and TX mbufs still in the queues. */
3786         for (i = 0; i < SK_RX_RING_CNT; i++) {
3787                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3788                 if (rxd->rx_m != NULL) {
3789                         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3790                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3791                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3792                             rxd->rx_dmamap);
3793                         m_freem(rxd->rx_m);
3794                         rxd->rx_m = NULL;
3795                 }
3796         }
3797         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3798                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3799                 if (jrxd->rx_m != NULL) {
3800                         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3801                             jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3802                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3803                             jrxd->rx_dmamap);
3804                         m_freem(jrxd->rx_m);
3805                         jrxd->rx_m = NULL;
3806                 }
3807         }
3808         for (i = 0; i < SK_TX_RING_CNT; i++) {
3809                 txd = &sc_if->sk_cdata.sk_txdesc[i];
3810                 if (txd->tx_m != NULL) {
3811                         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3812                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3813                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3814                             txd->tx_dmamap);
3815                         m_freem(txd->tx_m);
3816                         txd->tx_m = NULL;
3817                 }
3818         }
3819
3820         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3821
3822         return;
3823 }
3824
3825 static int
3826 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3827 {
3828         int error, value;
3829
3830         if (!arg1)
3831                 return (EINVAL);
3832         value = *(int *)arg1;
3833         error = sysctl_handle_int(oidp, &value, 0, req);
3834         if (error || !req->newptr)
3835                 return (error);
3836         if (value < low || value > high)
3837                 return (EINVAL);
3838         *(int *)arg1 = value;
3839         return (0);
3840 }
3841
3842 static int
3843 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3844 {
3845         return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3846 }