1 2007-08-08 Andrew Haley <aph@redhat.com> (r128087)
3 * config/arm/libunwind.S (UNWIND_WRAPPER _Unwind_Backtrace): New.
4 * config/arm/unwind-arm.h (__gnu_Unwind_Backtrace): New.
5 * config/arm/unwind-arm.c (__gnu_Unwind_Backtrace): New.
7 2007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346)
10 * doc/extend.texi: Document the 0b-prefixed binary integer
13 2007-05-24 Richard Sandiford <rsandifo@nildram.co.uk> (r125037)
15 * postreload-gcse.c (reg_changed_after_insn_p): New function.
16 (oprs_unchanged_p): Use it to check all registers in a REG.
17 (record_opr_changes): Look for clobbers in CALL_INSN_FUNCTION_USAGE.
18 (reg_set_between_after_reload_p): Delete.
19 (reg_used_between_after_reload_p): Likewise.
20 (reg_set_or_used_since_bb_start): Likewise.
21 (eliminate_partially_redundant_load): Use reg_changed_after_insn_p
22 and reg_used_between_p instead of reg_set_or_used_since_bb_start.
23 Use reg_set_between_p instead of reg_set_between_after_reload_p.
24 * rtlanal.c (reg_set_p): Check whether REG overlaps
25 regs_invalidated_by_call, rather than just checking the
26 membership of REGNO (REG).
28 2007-05-03 Ian Lance Taylor <iant@google.com> (r124381)
30 * config/rs6000/rs6000.c (rs6000_override_options): Don't set
31 MASK_PPC_GFXOPT for 8540 or 8548.
33 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341)
35 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
38 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
40 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
41 and athlon64-sse3 as improved versions of k8, opteron and athlon64
42 with SSE3 instruction set support.
43 * doc/invoke.texi: Likewise.
45 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330)
47 * config/i386/i386.c (override_options): Tuning 32-byte loop
48 alignment for amdfam10 architecture. Increasing the max loop
49 alignment to 24 bytes.
51 2007-04-16 Lawrence Crowl <crowl@google.com>
53 * doc/invoke.texi (Debugging Options): Add documentation for the
54 -femit-struct-debug options -femit-struct-debug-baseonly,
55 -femit-struct-debug-reduced, and
56 -femit-struct-debug-detailed[=...].
58 * c-opts.c (c_common_handle_option): Add
59 OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced,
60 and OPT_femit_struct_debug_detailed_.
61 * c.opt: Add specifications for
62 -femit-struct-debug-baseonly, -femit-struct-debug-reduced,
63 and -femit-struct-debug-detailed[=...].
64 * opts.c (set_struct_debug_option): Parse the
65 -femit-struct-debug-... options.
66 * opts.c (matches_main_base, main_input_basename,
67 main_input_baselength, base_of_path, matches_main_base): Add
68 variables and functions to compare header base name to compilation
70 * opts.c (should_emit_struct_debug): Add to determine to emit a
71 structure based on the option.
72 (dump_struct_debug) Also disabled function to debug this
74 * opts.c (handle_options): Save the base name of the
77 * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define.
78 (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add.
79 This hook indicates if a type is generic. Set it by default
81 * langhooks.h (struct lang_hooks_for_types): Add a new hook
82 to determine if a struct type is generic or not.
83 * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook.
84 * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook.
85 * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook
88 * flags.h (enum debug_info_usage): Add an enumeration to describe
89 a program's use of a structure type.
90 * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter
91 to indicate the program's usage of the type. Filter structs based
92 on the -femit-struct-debug-... specification.
93 (gen_type_die): Split into two routines, gen_type_die and
94 gen_type_die_with_usage. gen_type_die is now a wrapper
95 that assumes direct usage.
96 (gen_type_die_with_usage): Replace calls to gen_type_die
97 with gen_type_die_with_usage adding the program usage of
99 (dwarf2out_imported_module_or_decl): Suppress struct debug
100 information using should_emit_struct_debug when appropriate.
102 2007-04-12 Richard Guenther <rguenther@suse.de> (r123736)
104 PR tree-optimization/24689
105 PR tree-optimization/31307
106 * fold-const.c (operand_equal_p): Compare INTEGER_CST array
108 * gimplify.c (canonicalize_addr_expr): To be consistent with
109 gimplify_compound_lval only set operands two and three of
110 ARRAY_REFs if they are not gimple_min_invariant. This makes
111 it never at this place.
112 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
114 2007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639)
116 * config/i386/i386.c (ix86_handle_option): Handle SSSE3.
118 2007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313)
120 * config.gcc: Accept barcelona as a variant of amdfam10.
121 * config/i386/i386.c (override_options): Likewise.
122 * doc/invoke.texi: Likewise.
124 2007-03-12 Seongbae Park <seongbae.park@gmail.com>
126 * c-decl.c (warn_variable_length_array): New function.
127 Refactored from grokdeclarator to handle warn_vla
128 and handle unnamed array case.
129 (grokdeclarator): Refactored VLA warning case.
130 * c.opt (Wvla): New flag.
132 2007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial)
134 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and
135 the *_DIV_EXPR codes correctly with overflow infinities.
137 2007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763)
139 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10.
142 2007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726)
144 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h
145 conditional to __SSE2__.
146 (Entries below should have been added to first ChangeLog
147 entry for amdfam10 dated 2007-02-05)
148 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not
150 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
152 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
155 2007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687)
157 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
159 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
161 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8,
162 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov,
163 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul,
164 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn,
165 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8,
166 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load,
167 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8,
168 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10.
170 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
172 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse,
173 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387,
174 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse,
175 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse,
176 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed,
177 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse,
178 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1,
179 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn,
180 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn,
181 umuldi3_highpart_rex64, umulsi3_highpart_insn,
182 umulsi3_highpart_zext, smuldi3_highpart_rex64,
183 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld,
184 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse,
185 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387,
186 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387,
187 sqrtextenddfxf2_i387): Added amdfam10_decode.
189 * config/i386/athlon.md (athlon_idirect_amdfam10,
190 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10,
191 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10,
192 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10,
193 athlon_ivector_store_amdfam10): New define_insn_reservation.
194 (athlon_idirect_loadmov, athlon_idirect_movstore): Added
197 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
199 * config/i386/athlon.md (athlon_call_amdfam10,
200 athlon_pop_amdfam10, athlon_lea_amdfam10): New
201 define_insn_reservation.
202 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8,
203 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI,
204 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10.
206 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
208 * config/i386/athlon.md (athlon_sseld_amdfam10,
209 athlon_mmxld_amdfam10, athlon_ssest_amdfam10,
210 athlon_mmxssest_short_amdfam10): New define_insn_reservation.
212 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
214 * config/i386/athlon.md (athlon_sseins_amdfam10): New
215 define_insn_reservation.
216 * config/i386/i386.md (sseins): Added sseins to define_attr type
217 and define_attr unit.
218 * config/i386/sse.md: Set type attribute to sseins for insertq
221 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
223 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10,
224 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10,
225 ssecomi_load_amdfam10, ssecomi_amdfam10,
226 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New
227 define_insn_reservation.
228 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10.
230 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
232 * config/i386/athlon.md (cvtss2sd_load_amdfam10,
233 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10,
234 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10,
235 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10,
236 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10,
237 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New
238 define_insn_reservation.
240 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si,
241 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq,
242 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq,
243 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd,
244 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute.
246 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
248 * config/i386/athlon.md (athlon_ssedivvector_amdfam10,
249 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10,
250 athlon_ssemulvector_load_amdfam10): New define_insn_reservation.
251 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul,
252 athlon_ssemul_load_k8): Added amdfam10.
254 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
256 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro.
257 (x86_sse_unaligned_move_optimal): New variable.
259 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for
261 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups
262 for unaligned vector SSE double/single precision loads for AMDFAM10.
264 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
266 * config/i386/i386.h (TARGET_AMDFAM10): New macro.
267 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10.
268 Define TARGET_CPU_DEFAULT_amdfam10.
269 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10.
270 (processor_type): Add PROCESSOR_AMDFAM10.
272 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match
273 processor_type in config/i386/i386.h.
274 Enable imul peepholes for TARGET_AMDFAM10.
276 * config.gcc: Add support for --with-cpu option for amdfam10.
278 * config/i386/i386.c (amdfam10_cost): New variable.
279 (m_AMDFAM10): New macro.
280 (m_ATHLON_K8_AMDFAM10): New macro.
281 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
282 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop,
283 x86_promote_QImode, x86_integer_DFmode_moves,
284 x86_partial_reg_dependency, x86_memory_mismatch_stall,
285 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387,
286 x86_sse_partial_reg_dependency, x86_sse_typeless_stores,
287 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit,
288 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns):
289 Enable/disable for amdfam10.
290 (override_options): Add amdfam10_cost to processor_target_table.
291 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in
292 processor_alias_table.
293 (ix86_issue_rate): Add PROCESSOR_AMDFAM10.
294 (ix86_adjust_cost): Add code for amdfam10.
296 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
298 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm)
299 instruction set feature flag. Add new (-mpopcnt) flag for popcnt
300 instruction. Add new SSE4A (-msse4a) instruction set feature flag.
301 * config/i386/i386.h: Add builtin definition for SSE4A.
302 * config/i386/i386.md: Add support for ABM instructions
304 * config/i386/sse.md: Add support for SSE4A instructions
305 (movntss, movntsd, extrq, insertq).
306 * config/i386/i386.c: Add support for ABM and SSE4A builtins.
307 Add -march=amdfam10 flag.
308 * config/i386/ammintrin.h: Add support for SSE4A intrinsics.
309 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt
311 * doc/extend.texi: Add documentation for SSE4A builtins.
313 2007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140)
315 * config/i386/i386.h (x86_cmpxchg16b): Remove const.
316 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b.
317 * config/i386/i386.c (x86_cmpxchg16b): Remove const.
318 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b
319 for CPUs that have PTA_CX16 set.
321 2007-01-17 Eric Christopher <echristo@apple.com> (r120846)
323 * config.gcc: Support core2 processor.
325 2006-12-13 Ian Lance Taylor <iant@google.com> (r119855)
329 * c-typeck.c (parser_build_binary_op): Move parentheses warnings
330 to warn_about_parentheses in c-common.c.
331 * c-common.c (warn_about_parentheses): New function.
332 * c-common.h (warn_about_parentheses): Declare.
333 * doc/invoke.texi (Warning Options): Update -Wparentheses
336 2006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial)
339 * config/i386/driver-i386.c (bit_SSSE3): New.
341 2006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260)
343 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2
346 2006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973)
348 * doc/invoke.texi (core2): Add item.
350 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
352 (TARGET_CPU_CPP_BUILTINS): Add code for core2.
353 (TARGET_CPU_DEFAULT_generic): Change value.
354 (TARGET_CPU_DEFAULT_NAMES): Add core2.
355 (processor_type): Add new constant PROCESSOR_CORE2.
357 * config/i386/i386.md (cpu): Add core2.
359 * config/i386/i386.c (core2_cost): New initialized variable.
360 (m_CORE2): New macro.
361 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
362 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
363 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
364 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
365 x86_partial_reg_dependency, x86_memory_mismatch_stall,
366 x86_accumulate_outgoing_args, x86_prologue_using_move,
367 x86_epilogue_using_move, x86_arch_always_fancy_math_387,
368 x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
369 x86_use_incdec, x86_four_jump_limit, x86_schedule,
370 x86_pad_returns): Add m_CORE2.
371 (override_options): Add entries for Core2.
372 (ix86_issue_rate): Add case for Core2.
374 2006-10-31 Geoffrey Keating <geoffk@apple.com> (r118356)
376 * c-decl.c (grokdeclarator): Don't set DECL_EXTERNAL on
377 inline static functions in c99 mode.
380 * doc/extend.texi (Inline): Update.
381 * c-tree.h (struct language_function): Remove field 'extern_inline'.
382 * c-decl.c (current_extern_inline): Delete.
383 (pop_scope): Adjust test for an undefined nested function.
384 Add warning about undeclared inline function.
385 (diagnose_mismatched_decls): Update comments. Disallow overriding
386 of inline functions in a translation unit in C99. Allow inline
387 declarations in C99 at any time.
388 (merge_decls): Boolize variables. Handle C99 'extern inline'
390 (grokdeclarator): Set DECL_EXTERNAL here for functions. Handle
391 C99 inline semantics.
392 (start_function): Don't clear current_extern_inline. Don't set
394 (c_push_function_context): Don't push current_extern_inline.
395 (c_pop_function_context): Don't restore current_extern_inline.
398 * c-typeck.c (build_external_ref): Warn about static variables
399 used in extern inline functions.
400 * c-decl.c (start_decl): Warn about static variables declared
401 in extern inline functions.
403 2006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090)
405 * config/i386/i386.h (TARGET_GEODE):
406 (TARGET_CPU_CPP_BUILTINS): Add code for geode.
407 (TARGET_CPU_DEFAULT_geode): New macro.
408 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2,
409 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon,
410 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8,
411 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott,
412 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase
414 (TARGET_CPU_DEFAULT_NAMES): Add geode.
415 (processor_type): Add PROCESSOR_GEODE.
417 * config/i386/i386.md: Include geode.md.
420 * config/i386/i386.c (geode_cost): New initialized global
422 (m_GEODE, m_K6_GEODE): New macros.
423 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf,
424 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4,
425 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants,
426 x86_schedule): Use m_K6_GEODE instead of m_K6.
427 (x86_movx, x86_cmove): Set up m_GEODE.
428 (x86_integer_DFmode_moves): Clear m_GEODE.
429 (processor_target_table): Add entry for geode.
430 (processor_alias_table): Ditto.
432 * config/i386/geode.md: New file.
434 * doc/invoke.texi: Add entry about geode processor.
436 2006-10-24 Richard Guenther <rguenther@suse.de> (r118001)
439 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES
440 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS
441 for deciding optimizations in consistency with fold-const.c
442 (fold_builtin_unordered_cmp): Likewise.
444 2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958)
446 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
447 (x86_64-*-*): Likewise.
449 * config/i386/i386.c (pta_flags): Add PTA_SSSE3.
450 (override_options): Check SSSE3.
451 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
452 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
453 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
454 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
455 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
456 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
457 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
458 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
459 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
460 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
461 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
462 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
463 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
464 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
465 IX86_BUILTIN_PABSD128.
466 (bdesc_2arg): Add SSSE3.
467 (bdesc_1arg): Likewise.
468 (ix86_init_mmx_sse_builtins): Support SSSE3.
469 (ix86_expand_builtin): Likewise.
470 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.
472 * config/i386/i386.md (UNSPEC_PSHUFB): New.
473 (UNSPEC_PSIGN): Likewise.
474 (UNSPEC_PALIGNR): Likewise.
475 Include mmx.md before sse.md.
477 * config/i386/i386.opt: Add -mssse3.
479 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
480 (ssse3_phaddwv4hi3): Likewise.
481 (ssse3_phadddv4si3): Likewise.
482 (ssse3_phadddv2si3): Likewise.
483 (ssse3_phaddswv8hi3): Likewise.
484 (ssse3_phaddswv4hi3): Likewise.
485 (ssse3_phsubwv8hi3): Likewise.
486 (ssse3_phsubwv4hi3): Likewise.
487 (ssse3_phsubdv4si3): Likewise.
488 (ssse3_phsubdv2si3): Likewise.
489 (ssse3_phsubswv8hi3): Likewise.
490 (ssse3_phsubswv4hi3): Likewise.
491 (ssse3_pmaddubswv8hi3): Likewise.
492 (ssse3_pmaddubswv4hi3): Likewise.
493 (ssse3_pmulhrswv8hi3): Likewise.
494 (ssse3_pmulhrswv4hi3): Likewise.
495 (ssse3_pshufbv16qi3): Likewise.
496 (ssse3_pshufbv8qi3): Likewise.
497 (ssse3_psign<mode>3): Likewise.
498 (ssse3_psign<mode>3): Likewise.
499 (ssse3_palignrti): Likewise.
500 (ssse3_palignrdi): Likewise.
501 (abs<mode>2): Likewise.
502 (abs<mode>2): Likewise.
504 * config/i386/tmmintrin.h: New file.
506 * doc/extend.texi: Document SSSE3 built-in functions.
508 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
510 2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959)
512 * config/i386/tmmintrin.h: Remove the duplicated content.
514 2006-10-21 Richard Guenther <rguenther@suse.de> (r117932)
516 PR tree-optimization/3511
517 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
518 got new invariant arguments during PHI translation.
520 2006-10-21 Richard Guenther <rguenther@suse.de> (r117929)
522 * builtins.c (fold_builtin_classify): Fix typo.