1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
32 using namespace clang;
34 //===----------------------------------------------------------------------===//
35 // Common code shared among targets.
36 //===----------------------------------------------------------------------===//
38 /// DefineStd - Define a macro name and standard variants. For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42 const LangOptions &Opts) {
43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46 // in the user's namespace.
48 Builder.defineMacro(MacroName);
51 Builder.defineMacro("__" + MacroName);
54 Builder.defineMacro("__" + MacroName + "__");
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59 Builder.defineMacro("__" + CPUName);
60 Builder.defineMacro("__" + CPUName + "__");
62 Builder.defineMacro("__tune_" + CPUName + "__");
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74 MacroBuilder &Builder) const=0;
76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77 virtual void getTargetDefines(const LangOptions &Opts,
78 MacroBuilder &Builder) const {
79 TgtInfo::getTargetDefines(Opts, Builder);
80 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
84 } // end anonymous namespace
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88 const llvm::Triple &Triple,
89 StringRef &PlatformName,
90 VersionTuple &PlatformMinVersion) {
91 Builder.defineMacro("__APPLE_CC__", "5621");
92 Builder.defineMacro("__APPLE__");
93 Builder.defineMacro("__MACH__");
94 Builder.defineMacro("OBJC_NEW_PROPERTIES");
95 // AddressSanitizer doesn't play well with source fortification, which is on
96 // by default on Darwin.
97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 if (!Opts.ObjCAutoRefCount) {
100 // __weak is always defined, for use in blocks and with objc pointers.
101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 // Darwin defines __strong even in C mode (just to nothing).
104 if (Opts.getGC() != LangOptions::NonGC)
105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107 Builder.defineMacro("__strong", "");
109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110 // allow this in C, since one might have block pointers in structs that
111 // are used in pure C code and in Objective-C ARC.
112 Builder.defineMacro("__unsafe_unretained", "");
116 Builder.defineMacro("__STATIC__");
118 Builder.defineMacro("__DYNAMIC__");
120 if (Opts.POSIXThreads)
121 Builder.defineMacro("_REENTRANT");
123 // Get the platform type and version number from the triple.
124 unsigned Maj, Min, Rev;
125 if (Triple.isMacOSX()) {
126 Triple.getMacOSXVersion(Maj, Min, Rev);
127 PlatformName = "macosx";
129 Triple.getOSVersion(Maj, Min, Rev);
130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
133 // If -target arch-pc-win32-macho option specified, we're
134 // generating code for Win32 ABI. No need to emit
135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136 if (PlatformName == "win32") {
137 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
141 // Set the appropriate OS version define.
142 if (Triple.getOS() == llvm::Triple::IOS) {
143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
146 Str[1] = '0' + (Min / 10);
147 Str[2] = '0' + (Min % 10);
148 Str[3] = '0' + (Rev / 10);
149 Str[4] = '0' + (Rev % 10);
151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
153 // Note that the Driver allows versions which aren't representable in the
154 // define (because we only get a single digit for the minor and micro
155 // revision numbers). So, we limit them to the maximum representable
157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160 Str[0] = '0' + (Maj / 10);
161 Str[1] = '0' + (Maj % 10);
162 Str[2] = '0' + std::min(Min, 9U);
163 Str[3] = '0' + std::min(Rev, 9U);
165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
168 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
172 template<typename Target>
173 class DarwinTargetInfo : public OSTargetInfo<Target> {
175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176 MacroBuilder &Builder) const {
177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178 this->PlatformMinVersion);
182 DarwinTargetInfo(const std::string& triple) :
183 OSTargetInfo<Target>(triple) {
184 llvm::Triple T = llvm::Triple(triple);
185 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186 this->MCountName = "\01mcount";
189 virtual std::string isValidSectionSpecifier(StringRef SR) const {
190 // Let MCSectionMachO validate this.
191 StringRef Segment, Section;
192 unsigned TAA, StubSize;
194 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195 TAA, HasTAA, StubSize);
198 virtual const char *getStaticInitSectionSpecifier() const {
199 // FIXME: We should return 0 when building kexts.
200 return "__TEXT,__StaticInit,regular,pure_instructions";
203 /// Darwin does not support protected visibility. Darwin's "default"
204 /// is very similar to ELF's "protected"; Darwin requires a "weak"
205 /// attribute on declarations that can be dynamically replaced.
206 virtual bool hasProtectedVisibility() const {
212 // DragonFlyBSD Target
213 template<typename Target>
214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
216 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217 MacroBuilder &Builder) const {
218 // DragonFly defines; list based off of gcc output
219 Builder.defineMacro("__DragonFly__");
220 Builder.defineMacro("__DragonFly_cc_version", "100001");
221 Builder.defineMacro("__ELF__");
222 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223 Builder.defineMacro("__tune_i386__");
224 DefineStd(Builder, "unix", Opts);
227 DragonFlyBSDTargetInfo(const std::string &triple)
228 : OSTargetInfo<Target>(triple) {
229 this->UserLabelPrefix = "";
231 llvm::Triple Triple(triple);
232 switch (Triple.getArch()) {
234 case llvm::Triple::x86:
235 case llvm::Triple::x86_64:
236 this->MCountName = ".mcount";
243 template<typename Target>
244 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247 MacroBuilder &Builder) const {
248 // FreeBSD defines; list based off of gcc output
250 unsigned Release = Triple.getOSMajorVersion();
254 Builder.defineMacro("__FreeBSD__", Twine(Release));
255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257 DefineStd(Builder, "unix", Opts);
258 Builder.defineMacro("__ELF__");
261 FreeBSDTargetInfo(const std::string &triple)
262 : OSTargetInfo<Target>(triple) {
263 this->UserLabelPrefix = "";
265 llvm::Triple Triple(triple);
266 switch (Triple.getArch()) {
268 case llvm::Triple::x86:
269 case llvm::Triple::x86_64:
270 this->MCountName = ".mcount";
272 case llvm::Triple::mips:
273 case llvm::Triple::mipsel:
274 case llvm::Triple::ppc:
275 case llvm::Triple::ppc64:
276 this->MCountName = "_mcount";
278 case llvm::Triple::arm:
279 this->MCountName = "__mcount";
287 template<typename Target>
288 class MinixTargetInfo : public OSTargetInfo<Target> {
290 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291 MacroBuilder &Builder) const {
294 Builder.defineMacro("__minix", "3");
295 Builder.defineMacro("_EM_WSIZE", "4");
296 Builder.defineMacro("_EM_PSIZE", "4");
297 Builder.defineMacro("_EM_SSIZE", "2");
298 Builder.defineMacro("_EM_LSIZE", "4");
299 Builder.defineMacro("_EM_FSIZE", "4");
300 Builder.defineMacro("_EM_DSIZE", "8");
301 Builder.defineMacro("__ELF__");
302 DefineStd(Builder, "unix", Opts);
305 MinixTargetInfo(const std::string &triple)
306 : OSTargetInfo<Target>(triple) {
307 this->UserLabelPrefix = "";
312 template<typename Target>
313 class LinuxTargetInfo : public OSTargetInfo<Target> {
315 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316 MacroBuilder &Builder) const {
317 // Linux defines; list based off of gcc output
318 DefineStd(Builder, "unix", Opts);
319 DefineStd(Builder, "linux", Opts);
320 Builder.defineMacro("__gnu_linux__");
321 Builder.defineMacro("__ELF__");
322 if (Triple.getEnvironment() == llvm::Triple::Android)
323 Builder.defineMacro("__ANDROID__", "1");
324 if (Opts.POSIXThreads)
325 Builder.defineMacro("_REENTRANT");
327 Builder.defineMacro("_GNU_SOURCE");
330 LinuxTargetInfo(const std::string& triple)
331 : OSTargetInfo<Target>(triple) {
332 this->UserLabelPrefix = "";
333 this->WIntType = TargetInfo::UnsignedInt;
336 virtual const char *getStaticInitSectionSpecifier() const {
337 return ".text.startup";
342 template<typename Target>
343 class NetBSDTargetInfo : public OSTargetInfo<Target> {
345 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346 MacroBuilder &Builder) const {
347 // NetBSD defines; list based off of gcc output
348 Builder.defineMacro("__NetBSD__");
349 Builder.defineMacro("__unix__");
350 Builder.defineMacro("__ELF__");
351 if (Opts.POSIXThreads)
352 Builder.defineMacro("_POSIX_THREADS");
355 NetBSDTargetInfo(const std::string &triple)
356 : OSTargetInfo<Target>(triple) {
357 this->UserLabelPrefix = "";
362 template<typename Target>
363 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
365 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366 MacroBuilder &Builder) const {
367 // OpenBSD defines; list based off of gcc output
369 Builder.defineMacro("__OpenBSD__");
370 DefineStd(Builder, "unix", Opts);
371 Builder.defineMacro("__ELF__");
372 if (Opts.POSIXThreads)
373 Builder.defineMacro("_REENTRANT");
376 OpenBSDTargetInfo(const std::string &triple)
377 : OSTargetInfo<Target>(triple) {
378 this->UserLabelPrefix = "";
379 this->TLSSupported = false;
381 llvm::Triple Triple(triple);
382 switch (Triple.getArch()) {
384 case llvm::Triple::x86:
385 case llvm::Triple::x86_64:
386 case llvm::Triple::arm:
387 case llvm::Triple::sparc:
388 this->MCountName = "__mcount";
390 case llvm::Triple::mips64:
391 case llvm::Triple::mips64el:
392 case llvm::Triple::ppc:
393 case llvm::Triple::sparcv9:
394 this->MCountName = "_mcount";
401 template<typename Target>
402 class BitrigTargetInfo : public OSTargetInfo<Target> {
404 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405 MacroBuilder &Builder) const {
406 // Bitrig defines; list based off of gcc output
408 Builder.defineMacro("__Bitrig__");
409 DefineStd(Builder, "unix", Opts);
410 Builder.defineMacro("__ELF__");
411 if (Opts.POSIXThreads)
412 Builder.defineMacro("_REENTRANT");
415 BitrigTargetInfo(const std::string &triple)
416 : OSTargetInfo<Target>(triple) {
417 this->UserLabelPrefix = "";
418 this->TLSSupported = false;
419 this->MCountName = "__mcount";
424 template<typename Target>
425 class PSPTargetInfo : public OSTargetInfo<Target> {
427 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428 MacroBuilder &Builder) const {
429 // PSP defines; list based on the output of the pspdev gcc toolchain.
430 Builder.defineMacro("PSP");
431 Builder.defineMacro("_PSP");
432 Builder.defineMacro("__psp__");
433 Builder.defineMacro("__ELF__");
436 PSPTargetInfo(const std::string& triple)
437 : OSTargetInfo<Target>(triple) {
438 this->UserLabelPrefix = "";
443 template<typename Target>
444 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
446 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447 MacroBuilder &Builder) const {
449 Builder.defineMacro("__PPC__");
450 Builder.defineMacro("__PPU__");
451 Builder.defineMacro("__CELLOS_LV2__");
452 Builder.defineMacro("__ELF__");
453 Builder.defineMacro("__LP32__");
454 Builder.defineMacro("_ARCH_PPC64");
455 Builder.defineMacro("__powerpc64__");
458 PS3PPUTargetInfo(const std::string& triple)
459 : OSTargetInfo<Target>(triple) {
460 this->UserLabelPrefix = "";
461 this->LongWidth = this->LongAlign = 32;
462 this->PointerWidth = this->PointerAlign = 32;
463 this->IntMaxType = TargetInfo::SignedLongLong;
464 this->UIntMaxType = TargetInfo::UnsignedLongLong;
465 this->Int64Type = TargetInfo::SignedLongLong;
466 this->SizeType = TargetInfo::UnsignedInt;
467 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
472 // FIXME: Need a real SPU target.
474 template<typename Target>
475 class PS3SPUTargetInfo : public OSTargetInfo<Target> {
477 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478 MacroBuilder &Builder) const {
480 Builder.defineMacro("__SPU__");
481 Builder.defineMacro("__ELF__");
484 PS3SPUTargetInfo(const std::string& triple)
485 : OSTargetInfo<Target>(triple) {
486 this->UserLabelPrefix = "";
491 template<typename Target>
492 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
494 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495 MacroBuilder &Builder) const {
496 DefineStd(Builder, "sun", Opts);
497 DefineStd(Builder, "unix", Opts);
498 Builder.defineMacro("__ELF__");
499 Builder.defineMacro("__svr4__");
500 Builder.defineMacro("__SVR4");
503 AuroraUXTargetInfo(const std::string& triple)
504 : OSTargetInfo<Target>(triple) {
505 this->UserLabelPrefix = "";
506 this->WCharType = this->SignedLong;
507 // FIXME: WIntType should be SignedLong
512 template<typename Target>
513 class SolarisTargetInfo : public OSTargetInfo<Target> {
515 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516 MacroBuilder &Builder) const {
517 DefineStd(Builder, "sun", Opts);
518 DefineStd(Builder, "unix", Opts);
519 Builder.defineMacro("__ELF__");
520 Builder.defineMacro("__svr4__");
521 Builder.defineMacro("__SVR4");
522 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523 // newer, but to 500 for everything else. feature_test.h has a check to
524 // ensure that you are not using C99 with an old version of X/Open or C89
525 // with a new version.
526 if (Opts.C99 || Opts.C11)
527 Builder.defineMacro("_XOPEN_SOURCE", "600");
529 Builder.defineMacro("_XOPEN_SOURCE", "500");
531 Builder.defineMacro("__C99FEATURES__");
532 Builder.defineMacro("_LARGEFILE_SOURCE");
533 Builder.defineMacro("_LARGEFILE64_SOURCE");
534 Builder.defineMacro("__EXTENSIONS__");
535 Builder.defineMacro("_REENTRANT");
538 SolarisTargetInfo(const std::string& triple)
539 : OSTargetInfo<Target>(triple) {
540 this->UserLabelPrefix = "";
541 this->WCharType = this->SignedInt;
542 // FIXME: WIntType should be SignedLong
547 template<typename Target>
548 class WindowsTargetInfo : public OSTargetInfo<Target> {
550 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551 MacroBuilder &Builder) const {
552 Builder.defineMacro("_WIN32");
554 void getVisualStudioDefines(const LangOptions &Opts,
555 MacroBuilder &Builder) const {
556 if (Opts.CPlusPlus) {
558 Builder.defineMacro("_CPPRTTI");
561 Builder.defineMacro("_CPPUNWIND");
564 if (!Opts.CharIsSigned)
565 Builder.defineMacro("_CHAR_UNSIGNED");
567 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568 // but it works for now.
569 if (Opts.POSIXThreads)
570 Builder.defineMacro("_MT");
572 if (Opts.MSCVersion != 0)
573 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
575 if (Opts.MicrosoftExt) {
576 Builder.defineMacro("_MSC_EXTENSIONS");
578 if (Opts.CPlusPlus11) {
579 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
585 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
589 WindowsTargetInfo(const std::string &triple)
590 : OSTargetInfo<Target>(triple) {}
593 template <typename Target>
594 class NaClTargetInfo : public OSTargetInfo<Target> {
596 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597 MacroBuilder &Builder) const {
598 if (Opts.POSIXThreads)
599 Builder.defineMacro("_REENTRANT");
601 Builder.defineMacro("_GNU_SOURCE");
603 DefineStd(Builder, "unix", Opts);
604 Builder.defineMacro("__ELF__");
605 Builder.defineMacro("__native_client__");
608 NaClTargetInfo(const std::string &triple)
609 : OSTargetInfo<Target>(triple) {
610 this->UserLabelPrefix = "";
611 this->LongAlign = 32;
612 this->LongWidth = 32;
613 this->PointerAlign = 32;
614 this->PointerWidth = 32;
615 this->IntMaxType = TargetInfo::SignedLongLong;
616 this->UIntMaxType = TargetInfo::UnsignedLongLong;
617 this->Int64Type = TargetInfo::SignedLongLong;
618 this->DoubleAlign = 64;
619 this->LongDoubleWidth = 64;
620 this->LongDoubleAlign = 64;
621 this->SizeType = TargetInfo::UnsignedInt;
622 this->PtrDiffType = TargetInfo::SignedInt;
623 this->IntPtrType = TargetInfo::SignedInt;
624 // RegParmMax is inherited from the underlying architecture
625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
629 virtual typename Target::CallingConvCheckResult checkCallingConvention(
630 CallingConv CC) const {
631 return CC == CC_PnaclCall ? Target::CCCR_OK :
632 Target::checkCallingConvention(CC);
635 } // end anonymous namespace.
637 //===----------------------------------------------------------------------===//
638 // Specific target implementations.
639 //===----------------------------------------------------------------------===//
642 // PPC abstract base class
643 class PPCTargetInfo : public TargetInfo {
644 static const Builtin::Info BuiltinInfo[];
645 static const char * const GCCRegNames[];
646 static const TargetInfo::GCCRegAlias GCCRegAliases[];
649 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650 LongDoubleWidth = LongDoubleAlign = 128;
651 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
654 /// \brief Flags for architecture specific defines.
657 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
658 ArchDefinePpcgr = 1 << 1,
659 ArchDefinePpcsq = 1 << 2,
660 ArchDefine440 = 1 << 3,
661 ArchDefine603 = 1 << 4,
662 ArchDefine604 = 1 << 5,
663 ArchDefinePwr4 = 1 << 6,
664 ArchDefinePwr5 = 1 << 7,
665 ArchDefinePwr5x = 1 << 8,
666 ArchDefinePwr6 = 1 << 9,
667 ArchDefinePwr6x = 1 << 10,
668 ArchDefinePwr7 = 1 << 11,
669 ArchDefineA2 = 1 << 12,
670 ArchDefineA2q = 1 << 13
673 // Note: GCC recognizes the following additional cpus:
674 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
677 virtual bool setCPU(const std::string &Name) {
678 bool CPUKnown = llvm::StringSwitch<bool>(Name)
679 .Case("generic", true)
701 .Case("e500mc", true)
703 .Case("power3", true)
705 .Case("power4", true)
707 .Case("power5", true)
709 .Case("power5x", true)
711 .Case("power6", true)
713 .Case("power6x", true)
715 .Case("power7", true)
717 .Case("powerpc", true)
719 .Case("powerpc64", true)
729 virtual void getTargetBuiltins(const Builtin::Info *&Records,
730 unsigned &NumRecords) const {
731 Records = BuiltinInfo;
732 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
735 virtual bool isCLZForZeroUndef() const { return false; }
737 virtual void getTargetDefines(const LangOptions &Opts,
738 MacroBuilder &Builder) const;
740 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
742 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
746 virtual bool hasFeature(StringRef Feature) const;
748 virtual void getGCCRegNames(const char * const *&Names,
749 unsigned &NumNames) const;
750 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751 unsigned &NumAliases) const;
752 virtual bool validateAsmConstraint(const char *&Name,
753 TargetInfo::ConstraintInfo &Info) const {
755 default: return false;
758 case 'b': // Base register
759 case 'f': // Floating point register
760 Info.setAllowsRegister();
762 // FIXME: The following are added to allow parsing.
763 // I just took a guess at what the actions should be.
764 // Also, is more specific checking needed? I.e. specific registers?
765 case 'd': // Floating point register (containing 64-bit value)
766 case 'v': // Altivec vector register
767 Info.setAllowsRegister();
771 case 'd':// VSX vector register to hold vector double data
772 case 'f':// VSX vector register to hold vector float data
773 case 's':// VSX vector register to hold scalar float data
774 case 'a':// Any VSX register
779 Info.setAllowsRegister();
780 Name++; // Skip over 'w'.
782 case 'h': // `MQ', `CTR', or `LINK' register
783 case 'q': // `MQ' register
784 case 'c': // `CTR' register
785 case 'l': // `LINK' register
786 case 'x': // `CR' register (condition register) number 0
787 case 'y': // `CR' register (condition register)
788 case 'z': // `XER[CA]' carry bit (part of the XER register)
789 Info.setAllowsRegister();
791 case 'I': // Signed 16-bit constant
792 case 'J': // Unsigned 16-bit constant shifted left 16 bits
793 // (use `L' instead for SImode constants)
794 case 'K': // Unsigned 16-bit constant
795 case 'L': // Signed 16-bit constant shifted left 16 bits
796 case 'M': // Constant larger than 31
797 case 'N': // Exact power of 2
798 case 'P': // Constant whose negation is a signed 16-bit constant
799 case 'G': // Floating point constant that can be loaded into a
800 // register with one instruction per word
801 case 'H': // Integer/Floating point constant that can be loaded
802 // into a register using three instructions
804 case 'm': // Memory operand. Note that on PowerPC targets, m can
805 // include addresses that update the base register. It
806 // is therefore only safe to use `m' in an asm statement
807 // if that asm statement accesses the operand exactly once.
808 // The asm statement must also use `%U<opno>' as a
809 // placeholder for the "update" flag in the corresponding
810 // load or store instruction. For example:
811 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
813 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814 // is not. Use es rather than m if you don't want the base
815 // register to be updated.
819 // es: A "stable" memory operand; that is, one which does not
820 // include any automodification of the base register. Unlike
821 // `m', this constraint can be used in asm statements that
822 // might access the operand several times, or that might not
824 Info.setAllowsMemory();
825 Name++; // Skip over 'e'.
827 case 'Q': // Memory operand that is an offset from a register (it is
828 // usually better to use `m' or `es' in asm statements)
829 case 'Z': // Memory operand that is an indexed or indirect from a
830 // register (it is usually better to use `m' or `es' in
832 Info.setAllowsMemory();
833 Info.setAllowsRegister();
835 case 'R': // AIX TOC entry
836 case 'a': // Address operand that is an indexed or indirect from a
837 // register (`p' is preferable for asm statements)
838 case 'S': // Constant suitable as a 64-bit mask operand
839 case 'T': // Constant suitable as a 32-bit mask operand
840 case 'U': // System V Release 4 small data area reference
841 case 't': // AND masks that can be performed by two rldic{l, r}
843 case 'W': // Vector constant that does not require memory
844 case 'j': // Vector constant that is all zeros.
850 virtual const char *getClobbers() const {
853 int getEHDataRegisterNumber(unsigned RegNo) const {
854 if (RegNo == 0) return 3;
855 if (RegNo == 1) return 4;
860 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
864 #include "clang/Basic/BuiltinsPPC.def"
868 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869 /// #defines that are not tied to a specific subtarget.
870 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871 MacroBuilder &Builder) const {
872 // Target identification.
873 Builder.defineMacro("__ppc__");
874 Builder.defineMacro("_ARCH_PPC");
875 Builder.defineMacro("__powerpc__");
876 Builder.defineMacro("__POWERPC__");
877 if (PointerWidth == 64) {
878 Builder.defineMacro("_ARCH_PPC64");
879 Builder.defineMacro("__powerpc64__");
880 Builder.defineMacro("__ppc64__");
882 Builder.defineMacro("__ppc__");
885 // Target properties.
886 if (getTriple().getOS() != llvm::Triple::NetBSD &&
887 getTriple().getOS() != llvm::Triple::OpenBSD)
888 Builder.defineMacro("_BIG_ENDIAN");
889 Builder.defineMacro("__BIG_ENDIAN__");
891 // Subtarget options.
892 Builder.defineMacro("__NATURAL_ALIGNMENT__");
893 Builder.defineMacro("__REGISTER_PREFIX__", "");
895 // FIXME: Should be controlled by command line option.
896 Builder.defineMacro("__LONG_DOUBLE_128__");
899 Builder.defineMacro("__VEC__", "10206");
900 Builder.defineMacro("__ALTIVEC__");
903 // CPU identification.
904 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905 .Case("440", ArchDefineName)
906 .Case("450", ArchDefineName | ArchDefine440)
907 .Case("601", ArchDefineName)
908 .Case("602", ArchDefineName | ArchDefinePpcgr)
909 .Case("603", ArchDefineName | ArchDefinePpcgr)
910 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912 .Case("604", ArchDefineName | ArchDefinePpcgr)
913 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914 .Case("620", ArchDefineName | ArchDefinePpcgr)
915 .Case("630", ArchDefineName | ArchDefinePpcgr)
916 .Case("7400", ArchDefineName | ArchDefinePpcgr)
917 .Case("7450", ArchDefineName | ArchDefinePpcgr)
918 .Case("750", ArchDefineName | ArchDefinePpcgr)
919 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
921 .Case("a2", ArchDefineA2)
922 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923 .Case("pwr3", ArchDefinePpcgr)
924 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
927 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928 | ArchDefinePpcgr | ArchDefinePpcsq)
929 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
934 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937 .Case("power3", ArchDefinePpcgr)
938 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
941 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942 | ArchDefinePpcgr | ArchDefinePpcsq)
943 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
948 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951 .Default(ArchDefineNone);
953 if (defs & ArchDefineName)
954 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955 if (defs & ArchDefinePpcgr)
956 Builder.defineMacro("_ARCH_PPCGR");
957 if (defs & ArchDefinePpcsq)
958 Builder.defineMacro("_ARCH_PPCSQ");
959 if (defs & ArchDefine440)
960 Builder.defineMacro("_ARCH_440");
961 if (defs & ArchDefine603)
962 Builder.defineMacro("_ARCH_603");
963 if (defs & ArchDefine604)
964 Builder.defineMacro("_ARCH_604");
965 if (defs & ArchDefinePwr4)
966 Builder.defineMacro("_ARCH_PWR4");
967 if (defs & ArchDefinePwr5)
968 Builder.defineMacro("_ARCH_PWR5");
969 if (defs & ArchDefinePwr5x)
970 Builder.defineMacro("_ARCH_PWR5X");
971 if (defs & ArchDefinePwr6)
972 Builder.defineMacro("_ARCH_PWR6");
973 if (defs & ArchDefinePwr6x)
974 Builder.defineMacro("_ARCH_PWR6X");
975 if (defs & ArchDefinePwr7)
976 Builder.defineMacro("_ARCH_PWR7");
977 if (defs & ArchDefineA2)
978 Builder.defineMacro("_ARCH_A2");
979 if (defs & ArchDefineA2q) {
980 Builder.defineMacro("_ARCH_A2Q");
981 Builder.defineMacro("_ARCH_QP");
984 if (getTriple().getVendor() == llvm::Triple::BGQ) {
985 Builder.defineMacro("__bg__");
986 Builder.defineMacro("__THW_BLUEGENE__");
987 Builder.defineMacro("__bgq__");
988 Builder.defineMacro("__TOS_BGQ__");
991 // FIXME: The following are not yet generated here by Clang, but are
995 // __RECIP_PRECISION__
1006 // __CMODEL_MEDIUM__
1013 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1023 .Case("ppc64", true)
1026 Features["qpx"] = (CPU == "a2q");
1029 bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1031 bool Enabled) const {
1032 if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1033 Name == "popcntd" || Name == "qpx") {
1034 Features[Name] = Enabled;
1041 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1042 return Feature == "powerpc";
1046 const char * const PPCTargetInfo::GCCRegNames[] = {
1047 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1048 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1049 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1050 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1051 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1052 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1053 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1054 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1055 "mq", "lr", "ctr", "ap",
1056 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1058 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1059 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1060 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1061 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1063 "spe_acc", "spefscr",
1067 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1068 unsigned &NumNames) const {
1069 Names = GCCRegNames;
1070 NumNames = llvm::array_lengthof(GCCRegNames);
1073 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1074 // While some of these aliases do map to different registers
1075 // they still share the same register name.
1086 { { "10" }, "r10" },
1087 { { "11" }, "r11" },
1088 { { "12" }, "r12" },
1089 { { "13" }, "r13" },
1090 { { "14" }, "r14" },
1091 { { "15" }, "r15" },
1092 { { "16" }, "r16" },
1093 { { "17" }, "r17" },
1094 { { "18" }, "r18" },
1095 { { "19" }, "r19" },
1096 { { "20" }, "r20" },
1097 { { "21" }, "r21" },
1098 { { "22" }, "r22" },
1099 { { "23" }, "r23" },
1100 { { "24" }, "r24" },
1101 { { "25" }, "r25" },
1102 { { "26" }, "r26" },
1103 { { "27" }, "r27" },
1104 { { "28" }, "r28" },
1105 { { "29" }, "r29" },
1106 { { "30" }, "r30" },
1107 { { "31" }, "r31" },
1108 { { "fr0" }, "f0" },
1109 { { "fr1" }, "f1" },
1110 { { "fr2" }, "f2" },
1111 { { "fr3" }, "f3" },
1112 { { "fr4" }, "f4" },
1113 { { "fr5" }, "f5" },
1114 { { "fr6" }, "f6" },
1115 { { "fr7" }, "f7" },
1116 { { "fr8" }, "f8" },
1117 { { "fr9" }, "f9" },
1118 { { "fr10" }, "f10" },
1119 { { "fr11" }, "f11" },
1120 { { "fr12" }, "f12" },
1121 { { "fr13" }, "f13" },
1122 { { "fr14" }, "f14" },
1123 { { "fr15" }, "f15" },
1124 { { "fr16" }, "f16" },
1125 { { "fr17" }, "f17" },
1126 { { "fr18" }, "f18" },
1127 { { "fr19" }, "f19" },
1128 { { "fr20" }, "f20" },
1129 { { "fr21" }, "f21" },
1130 { { "fr22" }, "f22" },
1131 { { "fr23" }, "f23" },
1132 { { "fr24" }, "f24" },
1133 { { "fr25" }, "f25" },
1134 { { "fr26" }, "f26" },
1135 { { "fr27" }, "f27" },
1136 { { "fr28" }, "f28" },
1137 { { "fr29" }, "f29" },
1138 { { "fr30" }, "f30" },
1139 { { "fr31" }, "f31" },
1140 { { "cc" }, "cr0" },
1143 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1144 unsigned &NumAliases) const {
1145 Aliases = GCCRegAliases;
1146 NumAliases = llvm::array_lengthof(GCCRegAliases);
1148 } // end anonymous namespace.
1151 class PPC32TargetInfo : public PPCTargetInfo {
1153 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1154 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1155 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1157 switch (getTriple().getOS()) {
1158 case llvm::Triple::Linux:
1159 case llvm::Triple::FreeBSD:
1160 case llvm::Triple::NetBSD:
1161 SizeType = UnsignedInt;
1162 PtrDiffType = SignedInt;
1163 IntPtrType = SignedInt;
1169 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1170 LongDoubleWidth = LongDoubleAlign = 64;
1171 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1174 // PPC32 supports atomics up to 4 bytes.
1175 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1178 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1179 // This is the ELF definition, and is overridden by the Darwin sub-target
1180 return TargetInfo::PowerABIBuiltinVaList;
1183 } // end anonymous namespace.
1186 class PPC64TargetInfo : public PPCTargetInfo {
1188 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1189 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1190 IntMaxType = SignedLong;
1191 UIntMaxType = UnsignedLong;
1192 Int64Type = SignedLong;
1194 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1195 LongDoubleWidth = LongDoubleAlign = 64;
1196 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1197 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1198 "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1199 "v128:128:128-n32:64";
1201 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1203 "v128:128:128-n32:64";
1205 // PPC64 supports atomics up to 8 bytes.
1206 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1208 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1209 return TargetInfo::CharPtrBuiltinVaList;
1212 } // end anonymous namespace.
1216 class DarwinPPC32TargetInfo :
1217 public DarwinTargetInfo<PPC32TargetInfo> {
1219 DarwinPPC32TargetInfo(const std::string& triple)
1220 : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1221 HasAlignMac68kSupport = true;
1222 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1224 SuitableAlign = 128;
1225 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1226 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1228 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1229 return TargetInfo::CharPtrBuiltinVaList;
1233 class DarwinPPC64TargetInfo :
1234 public DarwinTargetInfo<PPC64TargetInfo> {
1236 DarwinPPC64TargetInfo(const std::string& triple)
1237 : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1238 HasAlignMac68kSupport = true;
1239 SuitableAlign = 128;
1240 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1241 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1244 } // end anonymous namespace.
1247 static const unsigned NVPTXAddrSpaceMap[] = {
1250 4, // opencl_constant
1255 class NVPTXTargetInfo : public TargetInfo {
1256 static const char * const GCCRegNames[];
1257 static const Builtin::Info BuiltinInfo[];
1258 std::vector<StringRef> AvailableFeatures;
1260 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1262 TLSSupported = false;
1263 LongWidth = LongAlign = 64;
1264 AddrSpaceMap = &NVPTXAddrSpaceMap;
1265 // Define available target features
1266 // These must be defined in sorted order!
1267 NoAsmVariants = true;
1269 virtual void getTargetDefines(const LangOptions &Opts,
1270 MacroBuilder &Builder) const {
1271 Builder.defineMacro("__PTX__");
1272 Builder.defineMacro("__NVPTX__");
1274 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1275 unsigned &NumRecords) const {
1276 Records = BuiltinInfo;
1277 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1279 virtual bool hasFeature(StringRef Feature) const {
1280 return Feature == "ptx" || Feature == "nvptx";
1283 virtual void getGCCRegNames(const char * const *&Names,
1284 unsigned &NumNames) const;
1285 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1286 unsigned &NumAliases) const {
1291 virtual bool validateAsmConstraint(const char *&Name,
1292 TargetInfo::ConstraintInfo &info) const {
1296 virtual const char *getClobbers() const {
1297 // FIXME: Is this really right?
1300 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1302 return TargetInfo::CharPtrBuiltinVaList;
1304 virtual bool setCPU(const std::string &Name) {
1305 bool Valid = llvm::StringSwitch<bool>(Name)
1306 .Case("sm_20", true)
1307 .Case("sm_21", true)
1308 .Case("sm_30", true)
1309 .Case("sm_35", true)
1314 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1316 bool Enabled) const;
1319 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1320 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1321 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1323 #include "clang/Basic/BuiltinsNVPTX.def"
1326 const char * const NVPTXTargetInfo::GCCRegNames[] = {
1330 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1331 unsigned &NumNames) const {
1332 Names = GCCRegNames;
1333 NumNames = llvm::array_lengthof(GCCRegNames);
1336 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1338 bool Enabled) const {
1339 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1341 Features[Name] = Enabled;
1348 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1350 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1351 PointerWidth = PointerAlign = 32;
1352 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1354 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1355 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1360 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1362 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1363 PointerWidth = PointerAlign = 64;
1364 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1366 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1367 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1375 static const unsigned R600AddrSpaceMap[] = {
1378 2, // opencl_constant
1384 static const char *DescriptionStringR600 =
1387 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1388 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1389 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1392 static const char *DescriptionStringR600DoubleOps =
1395 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1396 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1397 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1400 static const char *DescriptionStringSI =
1403 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1404 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1405 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1408 class R600TargetInfo : public TargetInfo {
1409 /// \brief The GPU profiles supported by the R600 target.
1417 GK_EVERGREEN_DOUBLE_OPS,
1418 GK_NORTHERN_ISLANDS,
1424 R600TargetInfo(const std::string& triple)
1425 : TargetInfo(triple),
1427 DescriptionString = DescriptionStringR600;
1428 AddrSpaceMap = &R600AddrSpaceMap;
1431 virtual const char * getClobbers() const {
1435 virtual void getGCCRegNames(const char * const *&Names,
1436 unsigned &numNames) const {
1441 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1442 unsigned &NumAliases) const {
1447 virtual bool validateAsmConstraint(const char *&Name,
1448 TargetInfo::ConstraintInfo &info) const {
1452 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1453 unsigned &NumRecords) const {
1459 virtual void getTargetDefines(const LangOptions &Opts,
1460 MacroBuilder &Builder) const {
1461 Builder.defineMacro("__R600__");
1464 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1465 return TargetInfo::CharPtrBuiltinVaList;
1468 virtual bool setCPU(const std::string &Name) {
1469 GPU = llvm::StringSwitch<GPUKind>(Name)
1470 .Case("r600" , GK_R600)
1471 .Case("rv610", GK_R600)
1472 .Case("rv620", GK_R600)
1473 .Case("rv630", GK_R600)
1474 .Case("rv635", GK_R600)
1475 .Case("rs780", GK_R600)
1476 .Case("rs880", GK_R600)
1477 .Case("rv670", GK_R600_DOUBLE_OPS)
1478 .Case("rv710", GK_R700)
1479 .Case("rv730", GK_R700)
1480 .Case("rv740", GK_R700_DOUBLE_OPS)
1481 .Case("rv770", GK_R700_DOUBLE_OPS)
1482 .Case("palm", GK_EVERGREEN)
1483 .Case("cedar", GK_EVERGREEN)
1484 .Case("sumo", GK_EVERGREEN)
1485 .Case("sumo2", GK_EVERGREEN)
1486 .Case("redwood", GK_EVERGREEN)
1487 .Case("juniper", GK_EVERGREEN)
1488 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1489 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1490 .Case("barts", GK_NORTHERN_ISLANDS)
1491 .Case("turks", GK_NORTHERN_ISLANDS)
1492 .Case("caicos", GK_NORTHERN_ISLANDS)
1493 .Case("cayman", GK_CAYMAN)
1494 .Case("aruba", GK_CAYMAN)
1495 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1496 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1497 .Case("verde", GK_SOUTHERN_ISLANDS)
1498 .Case("oland", GK_SOUTHERN_ISLANDS)
1501 if (GPU == GK_NONE) {
1505 // Set the correct data layout
1511 case GK_NORTHERN_ISLANDS:
1512 DescriptionString = DescriptionStringR600;
1514 case GK_R600_DOUBLE_OPS:
1515 case GK_R700_DOUBLE_OPS:
1516 case GK_EVERGREEN_DOUBLE_OPS:
1518 DescriptionString = DescriptionStringR600DoubleOps;
1520 case GK_SOUTHERN_ISLANDS:
1521 DescriptionString = DescriptionStringSI;
1529 } // end anonymous namespace
1532 // MBlaze abstract base class
1533 class MBlazeTargetInfo : public TargetInfo {
1534 static const char * const GCCRegNames[];
1535 static const TargetInfo::GCCRegAlias GCCRegAliases[];
1538 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1539 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1542 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1543 unsigned &NumRecords) const {
1544 // FIXME: Implement.
1549 virtual void getTargetDefines(const LangOptions &Opts,
1550 MacroBuilder &Builder) const;
1552 virtual bool hasFeature(StringRef Feature) const {
1553 return Feature == "mblaze";
1556 virtual BuiltinVaListKind getBuiltinVaListKind() const {
1557 return TargetInfo::CharPtrBuiltinVaList;
1559 virtual const char *getTargetPrefix() const {
1562 virtual void getGCCRegNames(const char * const *&Names,
1563 unsigned &NumNames) const;
1564 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1565 unsigned &NumAliases) const;
1566 virtual bool validateAsmConstraint(const char *&Name,
1567 TargetInfo::ConstraintInfo &Info) const {
1569 default: return false;
1572 case 'b': // Base register
1573 case 'f': // Floating point register
1574 Info.setAllowsRegister();
1578 virtual const char *getClobbers() const {
1583 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1584 /// #defines that are not tied to a specific subtarget.
1585 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1586 MacroBuilder &Builder) const {
1587 // Target identification.
1588 Builder.defineMacro("__microblaze__");
1589 Builder.defineMacro("_ARCH_MICROBLAZE");
1590 Builder.defineMacro("__MICROBLAZE__");
1592 // Target properties.
1593 Builder.defineMacro("_BIG_ENDIAN");
1594 Builder.defineMacro("__BIG_ENDIAN__");
1596 // Subtarget options.
1597 Builder.defineMacro("__REGISTER_PREFIX__", "");
1601 const char * const MBlazeTargetInfo::GCCRegNames[] = {
1602 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1603 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1604 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1605 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1606 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1607 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1608 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1609 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1610 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1611 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp"
1614 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1615 unsigned &NumNames) const {
1616 Names = GCCRegNames;
1617 NumNames = llvm::array_lengthof(GCCRegNames);
1620 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1655 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1656 unsigned &NumAliases) const {
1657 Aliases = GCCRegAliases;
1658 NumAliases = llvm::array_lengthof(GCCRegAliases);
1660 } // end anonymous namespace.
1663 // Namespace for x86 abstract base class
1664 const Builtin::Info BuiltinInfo[] = {
1665 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1666 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1668 #include "clang/Basic/BuiltinsX86.def"
1671 static const char* const GCCRegNames[] = {
1672 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1673 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1674 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1675 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1676 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1677 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1678 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1679 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1680 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1683 const TargetInfo::AddlRegName AddlRegNames[] = {
1684 { { "al", "ah", "eax", "rax" }, 0 },
1685 { { "bl", "bh", "ebx", "rbx" }, 3 },
1686 { { "cl", "ch", "ecx", "rcx" }, 2 },
1687 { { "dl", "dh", "edx", "rdx" }, 1 },
1688 { { "esi", "rsi" }, 4 },
1689 { { "edi", "rdi" }, 5 },
1690 { { "esp", "rsp" }, 7 },
1691 { { "ebp", "rbp" }, 6 },
1694 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1695 // most of the implementation can be shared.
1696 class X86TargetInfo : public TargetInfo {
1698 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1701 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1720 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1722 /// Each enumeration represents a particular CPU supported by Clang. These
1723 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1728 /// i386-generation processors.
1734 /// i486-generation processors.
1743 /// i586-generation processors, P5 microarchitecture based.
1751 /// i686-generation processors, P6 / Pentium M microarchitecture based.
1761 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1762 /// Clang however has some logic to suport this.
1763 // FIXME: Warn, deprecate, and potentially remove this.
1768 /// Netburst microarchitecture based processors.
1777 /// Core microarchitecture based processors.
1781 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1782 /// codename which GCC no longer accepts as an option to -march, but Clang
1783 /// has some logic for recognizing it.
1784 // FIXME: Warn, deprecate, and potentially remove this.
1795 /// Nehalem microarchitecture based processors.
1804 /// K6 architecture processors.
1812 /// K7 architecture processors.
1815 CK_AthlonThunderbird,
1822 /// K8 architecture processors.
1835 /// Bobcat architecture processors.
1842 /// Bulldozer architecture processors.
1848 /// This specification is deprecated and will be removed in the future.
1849 /// Users should prefer \see CK_K8.
1850 // FIXME: Warn on this when the CPU is set to it.
1855 /// Geode processors.
1862 X86TargetInfo(const std::string& triple)
1863 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1864 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1865 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1866 HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1867 HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1869 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1871 virtual unsigned getFloatEvalMethod() const {
1872 // X87 evaluates with 80 bits "long double" precision.
1873 return SSELevel == NoSSE ? 2 : 0;
1875 virtual void getTargetBuiltins(const Builtin::Info *&Records,
1876 unsigned &NumRecords) const {
1877 Records = BuiltinInfo;
1878 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1880 virtual void getGCCRegNames(const char * const *&Names,
1881 unsigned &NumNames) const {
1882 Names = GCCRegNames;
1883 NumNames = llvm::array_lengthof(GCCRegNames);
1885 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1886 unsigned &NumAliases) const {
1890 virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1891 unsigned &NumNames) const {
1892 Names = AddlRegNames;
1893 NumNames = llvm::array_lengthof(AddlRegNames);
1895 virtual bool validateAsmConstraint(const char *&Name,
1896 TargetInfo::ConstraintInfo &info) const;
1897 virtual std::string convertConstraint(const char *&Constraint) const;
1898 virtual const char *getClobbers() const {
1899 return "~{dirflag},~{fpsr},~{flags}";
1901 virtual void getTargetDefines(const LangOptions &Opts,
1902 MacroBuilder &Builder) const;
1903 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1905 bool Enabled) const;
1906 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1907 virtual bool hasFeature(StringRef Feature) const;
1908 virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1909 virtual const char* getABI() const {
1910 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1912 else if (getTriple().getArch() == llvm::Triple::x86 &&
1913 MMX3DNowLevel == NoMMX3DNow)
1917 virtual bool setCPU(const std::string &Name) {
1918 CPU = llvm::StringSwitch<CPUKind>(Name)
1919 .Case("i386", CK_i386)
1920 .Case("i486", CK_i486)
1921 .Case("winchip-c6", CK_WinChipC6)
1922 .Case("winchip2", CK_WinChip2)
1924 .Case("i586", CK_i586)
1925 .Case("pentium", CK_Pentium)
1926 .Case("pentium-mmx", CK_PentiumMMX)
1927 .Case("i686", CK_i686)
1928 .Case("pentiumpro", CK_PentiumPro)
1929 .Case("pentium2", CK_Pentium2)
1930 .Case("pentium3", CK_Pentium3)
1931 .Case("pentium3m", CK_Pentium3M)
1932 .Case("pentium-m", CK_PentiumM)
1933 .Case("c3-2", CK_C3_2)
1934 .Case("yonah", CK_Yonah)
1935 .Case("pentium4", CK_Pentium4)
1936 .Case("pentium4m", CK_Pentium4M)
1937 .Case("prescott", CK_Prescott)
1938 .Case("nocona", CK_Nocona)
1939 .Case("core2", CK_Core2)
1940 .Case("penryn", CK_Penryn)
1941 .Case("atom", CK_Atom)
1942 .Case("corei7", CK_Corei7)
1943 .Case("corei7-avx", CK_Corei7AVX)
1944 .Case("core-avx-i", CK_CoreAVXi)
1945 .Case("core-avx2", CK_CoreAVX2)
1947 .Case("k6-2", CK_K6_2)
1948 .Case("k6-3", CK_K6_3)
1949 .Case("athlon", CK_Athlon)
1950 .Case("athlon-tbird", CK_AthlonThunderbird)
1951 .Case("athlon-4", CK_Athlon4)
1952 .Case("athlon-xp", CK_AthlonXP)
1953 .Case("athlon-mp", CK_AthlonMP)
1954 .Case("athlon64", CK_Athlon64)
1955 .Case("athlon64-sse3", CK_Athlon64SSE3)
1956 .Case("athlon-fx", CK_AthlonFX)
1958 .Case("k8-sse3", CK_K8SSE3)
1959 .Case("opteron", CK_Opteron)
1960 .Case("opteron-sse3", CK_OpteronSSE3)
1961 .Case("amdfam10", CK_AMDFAM10)
1962 .Case("btver1", CK_BTVER1)
1963 .Case("btver2", CK_BTVER2)
1964 .Case("bdver1", CK_BDVER1)
1965 .Case("bdver2", CK_BDVER2)
1966 .Case("x86-64", CK_x86_64)
1967 .Case("geode", CK_Geode)
1968 .Default(CK_Generic);
1970 // Perform any per-CPU checks necessary to determine if this CPU is
1972 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1973 // invalid without explaining *why*.
1976 // No processor selected!
2002 case CK_AthlonThunderbird:
2007 // Only accept certain architectures when compiling in 32-bit mode.
2008 if (getTriple().getArch() != llvm::Triple::x86)
2021 case CK_Athlon64SSE3:
2026 case CK_OpteronSSE3:
2035 llvm_unreachable("Unhandled CPU kind");
2038 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2039 // We accept all non-ARM calling conventions
2040 return (CC == CC_X86ThisCall ||
2041 CC == CC_X86FastCall ||
2042 CC == CC_X86StdCall ||
2044 CC == CC_X86Pascal ||
2045 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2048 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2049 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2053 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2054 // FIXME: This should not be here.
2055 Features["3dnow"] = false;
2056 Features["3dnowa"] = false;
2057 Features["mmx"] = false;
2058 Features["sse"] = false;
2059 Features["sse2"] = false;
2060 Features["sse3"] = false;
2061 Features["ssse3"] = false;
2062 Features["sse41"] = false;
2063 Features["sse42"] = false;
2064 Features["sse4a"] = false;
2065 Features["aes"] = false;
2066 Features["pclmul"] = false;
2067 Features["avx"] = false;
2068 Features["avx2"] = false;
2069 Features["lzcnt"] = false;
2070 Features["rdrand"] = false;
2071 Features["bmi"] = false;
2072 Features["bmi2"] = false;
2073 Features["popcnt"] = false;
2074 Features["rtm"] = false;
2075 Features["prfchw"] = false;
2076 Features["rdseed"] = false;
2077 Features["fma4"] = false;
2078 Features["fma"] = false;
2079 Features["xop"] = false;
2080 Features["f16c"] = false;
2082 // FIXME: This *really* should not be here.
2084 // X86_64 always has SSE2.
2085 if (getTriple().getArch() == llvm::Triple::x86_64)
2086 setFeatureEnabled(Features, "sse2", true);
2099 setFeatureEnabled(Features, "mmx", true);
2103 setFeatureEnabled(Features, "sse", true);
2109 setFeatureEnabled(Features, "sse2", true);
2114 setFeatureEnabled(Features, "sse3", true);
2117 setFeatureEnabled(Features, "ssse3", true);
2120 setFeatureEnabled(Features, "sse4.1", true);
2123 setFeatureEnabled(Features, "ssse3", true);
2126 setFeatureEnabled(Features, "sse4", true);
2129 setFeatureEnabled(Features, "avx", true);
2130 setFeatureEnabled(Features, "aes", true);
2131 setFeatureEnabled(Features, "pclmul", true);
2134 setFeatureEnabled(Features, "avx", true);
2135 setFeatureEnabled(Features, "aes", true);
2136 setFeatureEnabled(Features, "pclmul", true);
2137 setFeatureEnabled(Features, "rdrnd", true);
2138 setFeatureEnabled(Features, "f16c", true);
2141 setFeatureEnabled(Features, "avx2", true);
2142 setFeatureEnabled(Features, "aes", true);
2143 setFeatureEnabled(Features, "pclmul", true);
2144 setFeatureEnabled(Features, "lzcnt", true);
2145 setFeatureEnabled(Features, "rdrnd", true);
2146 setFeatureEnabled(Features, "f16c", true);
2147 setFeatureEnabled(Features, "bmi", true);
2148 setFeatureEnabled(Features, "bmi2", true);
2149 setFeatureEnabled(Features, "rtm", true);
2150 setFeatureEnabled(Features, "fma", true);
2154 setFeatureEnabled(Features, "mmx", true);
2160 setFeatureEnabled(Features, "3dnow", true);
2163 case CK_AthlonThunderbird:
2165 setFeatureEnabled(Features, "3dnowa", true);
2170 setFeatureEnabled(Features, "sse", true);
2171 setFeatureEnabled(Features, "3dnowa", true);
2177 setFeatureEnabled(Features, "sse2", true);
2178 setFeatureEnabled(Features, "3dnowa", true);
2181 case CK_OpteronSSE3:
2182 case CK_Athlon64SSE3:
2183 setFeatureEnabled(Features, "sse3", true);
2184 setFeatureEnabled(Features, "3dnowa", true);
2187 setFeatureEnabled(Features, "sse3", true);
2188 setFeatureEnabled(Features, "sse4a", true);
2189 setFeatureEnabled(Features, "3dnowa", true);
2190 setFeatureEnabled(Features, "lzcnt", true);
2191 setFeatureEnabled(Features, "popcnt", true);
2194 setFeatureEnabled(Features, "ssse3", true);
2195 setFeatureEnabled(Features, "sse4a", true);
2196 setFeatureEnabled(Features, "lzcnt", true);
2197 setFeatureEnabled(Features, "popcnt", true);
2200 setFeatureEnabled(Features, "avx", true);
2201 setFeatureEnabled(Features, "sse4a", true);
2202 setFeatureEnabled(Features, "lzcnt", true);
2203 setFeatureEnabled(Features, "aes", true);
2204 setFeatureEnabled(Features, "pclmul", true);
2205 setFeatureEnabled(Features, "bmi", true);
2206 setFeatureEnabled(Features, "f16c", true);
2209 setFeatureEnabled(Features, "xop", true);
2210 setFeatureEnabled(Features, "lzcnt", true);
2211 setFeatureEnabled(Features, "aes", true);
2212 setFeatureEnabled(Features, "pclmul", true);
2215 setFeatureEnabled(Features, "xop", true);
2216 setFeatureEnabled(Features, "lzcnt", true);
2217 setFeatureEnabled(Features, "aes", true);
2218 setFeatureEnabled(Features, "pclmul", true);
2219 setFeatureEnabled(Features, "bmi", true);
2220 setFeatureEnabled(Features, "fma", true);
2221 setFeatureEnabled(Features, "f16c", true);
2224 setFeatureEnabled(Features, "sse", true);
2229 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2231 bool Enabled) const {
2232 // FIXME: This *really* should not be here. We need some way of translating
2233 // options into llvm subtarget features.
2234 if (!Features.count(Name) &&
2235 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2239 // FIXME: this should probably use a switch with fall through.
2243 Features["mmx"] = true;
2244 else if (Name == "sse")
2245 Features["mmx"] = Features["sse"] = true;
2246 else if (Name == "sse2")
2247 Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2248 else if (Name == "sse3")
2249 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2251 else if (Name == "ssse3")
2252 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2253 Features["ssse3"] = true;
2254 else if (Name == "sse4" || Name == "sse4.2")
2255 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2256 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2257 Features["popcnt"] = true;
2258 else if (Name == "sse4.1")
2259 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2260 Features["ssse3"] = Features["sse41"] = true;
2261 else if (Name == "3dnow")
2262 Features["mmx"] = Features["3dnow"] = true;
2263 else if (Name == "3dnowa")
2264 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2265 else if (Name == "aes")
2266 Features["sse"] = Features["sse2"] = Features["aes"] = true;
2267 else if (Name == "pclmul")
2268 Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2269 else if (Name == "avx")
2270 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2271 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2272 Features["popcnt"] = Features["avx"] = true;
2273 else if (Name == "avx2")
2274 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2275 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2276 Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2277 else if (Name == "fma")
2278 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2279 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2280 Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2281 else if (Name == "fma4")
2282 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2283 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2284 Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2285 Features["fma4"] = true;
2286 else if (Name == "xop")
2287 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2288 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2289 Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2290 Features["fma4"] = Features["xop"] = true;
2291 else if (Name == "sse4a")
2292 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2293 Features["sse4a"] = true;
2294 else if (Name == "lzcnt")
2295 Features["lzcnt"] = true;
2296 else if (Name == "rdrnd")
2297 Features["rdrand"] = true;
2298 else if (Name == "bmi")
2299 Features["bmi"] = true;
2300 else if (Name == "bmi2")
2301 Features["bmi2"] = true;
2302 else if (Name == "popcnt")
2303 Features["popcnt"] = true;
2304 else if (Name == "f16c")
2305 Features["f16c"] = true;
2306 else if (Name == "rtm")
2307 Features["rtm"] = true;
2308 else if (Name == "prfchw")
2309 Features["prfchw"] = true;
2310 else if (Name == "rdseed")
2311 Features["rdseed"] = true;
2314 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2315 else if (Name == "sse")
2316 Features["sse"] = Features["sse2"] = Features["sse3"] =
2317 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2318 Features["sse4a"] = Features["avx"] = Features["avx2"] =
2319 Features["fma"] = Features["fma4"] = Features["aes"] =
2320 Features["pclmul"] = Features["xop"] = false;
2321 else if (Name == "sse2")
2322 Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2323 Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2324 Features["avx"] = Features["avx2"] = Features["fma"] =
2325 Features["fma4"] = Features["aes"] = Features["pclmul"] =
2326 Features["xop"] = false;
2327 else if (Name == "sse3")
2328 Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2329 Features["sse42"] = Features["sse4a"] = Features["avx"] =
2330 Features["avx2"] = Features["fma"] = Features["fma4"] =
2331 Features["xop"] = false;
2332 else if (Name == "ssse3")
2333 Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2334 Features["avx"] = Features["avx2"] = Features["fma"] = false;
2335 else if (Name == "sse4" || Name == "sse4.1")
2336 Features["sse41"] = Features["sse42"] = Features["avx"] =
2337 Features["avx2"] = Features["fma"] = false;
2338 else if (Name == "sse4.2")
2339 Features["sse42"] = Features["avx"] = Features["avx2"] =
2340 Features["fma"] = false;
2341 else if (Name == "3dnow")
2342 Features["3dnow"] = Features["3dnowa"] = false;
2343 else if (Name == "3dnowa")
2344 Features["3dnowa"] = false;
2345 else if (Name == "aes")
2346 Features["aes"] = false;
2347 else if (Name == "pclmul")
2348 Features["pclmul"] = false;
2349 else if (Name == "avx")
2350 Features["avx"] = Features["avx2"] = Features["fma"] =
2351 Features["fma4"] = Features["xop"] = false;
2352 else if (Name == "avx2")
2353 Features["avx2"] = false;
2354 else if (Name == "fma")
2355 Features["fma"] = false;
2356 else if (Name == "sse4a")
2357 Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2358 else if (Name == "lzcnt")
2359 Features["lzcnt"] = false;
2360 else if (Name == "rdrnd")
2361 Features["rdrand"] = false;
2362 else if (Name == "bmi")
2363 Features["bmi"] = false;
2364 else if (Name == "bmi2")
2365 Features["bmi2"] = false;
2366 else if (Name == "popcnt")
2367 Features["popcnt"] = false;
2368 else if (Name == "fma4")
2369 Features["fma4"] = Features["xop"] = false;
2370 else if (Name == "xop")
2371 Features["xop"] = false;
2372 else if (Name == "f16c")
2373 Features["f16c"] = false;
2374 else if (Name == "rtm")
2375 Features["rtm"] = false;
2376 else if (Name == "prfchw")
2377 Features["prfchw"] = false;
2378 else if (Name == "rdseed")
2379 Features["rdseed"] = false;
2385 /// HandleTargetOptions - Perform initialization based on the user
2386 /// configured set of features.
2387 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2388 // Remember the maximum enabled sselevel.
2389 for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2390 // Ignore disabled features.
2391 if (Features[i][0] == '-')
2394 StringRef Feature = StringRef(Features[i]).substr(1);
2396 if (Feature == "aes") {
2401 if (Feature == "pclmul") {
2406 if (Feature == "lzcnt") {
2411 if (Feature == "rdrand") {
2416 if (Feature == "bmi") {
2421 if (Feature == "bmi2") {
2426 if (Feature == "popcnt") {
2431 if (Feature == "rtm") {
2436 if (Feature == "prfchw") {
2441 if (Feature == "rdseed") {
2446 if (Feature == "sse4a") {
2451 if (Feature == "fma4") {
2456 if (Feature == "fma") {
2461 if (Feature == "xop") {
2466 if (Feature == "f16c") {
2471 assert(Features[i][0] == '+' && "Invalid target feature!");
2472 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2475 .Case("sse42", SSE42)
2476 .Case("sse41", SSE41)
2477 .Case("ssse3", SSSE3)
2482 SSELevel = std::max(SSELevel, Level);
2484 MMX3DNowEnum ThreeDNowLevel =
2485 llvm::StringSwitch<MMX3DNowEnum>(Feature)
2486 .Case("3dnowa", AMD3DNowAthlon)
2487 .Case("3dnow", AMD3DNow)
2489 .Default(NoMMX3DNow);
2491 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2494 // Don't tell the backend if we're turning off mmx; it will end up disabling
2495 // SSE, which we don't want.
2496 std::vector<std::string>::iterator it;
2497 it = std::find(Features.begin(), Features.end(), "-mmx");
2498 if (it != Features.end())
2502 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2503 /// definitions for this particular subtarget.
2504 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2505 MacroBuilder &Builder) const {
2506 // Target identification.
2507 if (getTriple().getArch() == llvm::Triple::x86_64) {
2508 Builder.defineMacro("__amd64__");
2509 Builder.defineMacro("__amd64");
2510 Builder.defineMacro("__x86_64");
2511 Builder.defineMacro("__x86_64__");
2513 DefineStd(Builder, "i386", Opts);
2516 // Subtarget options.
2517 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2518 // truly should be based on -mtune options.
2523 // The rest are coming from the i386 define above.
2524 Builder.defineMacro("__tune_i386__");
2530 defineCPUMacros(Builder, "i486");
2533 Builder.defineMacro("__pentium_mmx__");
2534 Builder.defineMacro("__tune_pentium_mmx__");
2538 defineCPUMacros(Builder, "i586");
2539 defineCPUMacros(Builder, "pentium");
2544 Builder.defineMacro("__tune_pentium3__");
2548 Builder.defineMacro("__tune_pentium2__");
2551 Builder.defineMacro("__tune_i686__");
2552 Builder.defineMacro("__tune_pentiumpro__");
2555 Builder.defineMacro("__i686");
2556 Builder.defineMacro("__i686__");
2557 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2558 Builder.defineMacro("__pentiumpro");
2559 Builder.defineMacro("__pentiumpro__");
2563 defineCPUMacros(Builder, "pentium4");
2568 defineCPUMacros(Builder, "nocona");
2572 defineCPUMacros(Builder, "core2");
2575 defineCPUMacros(Builder, "atom");
2581 defineCPUMacros(Builder, "corei7");
2584 Builder.defineMacro("__k6_2__");
2585 Builder.defineMacro("__tune_k6_2__");
2588 if (CPU != CK_K6_2) { // In case of fallthrough
2589 // FIXME: GCC may be enabling these in cases where some other k6
2590 // architecture is specified but -m3dnow is explicitly provided. The
2591 // exact semantics need to be determined and emulated here.
2592 Builder.defineMacro("__k6_3__");
2593 Builder.defineMacro("__tune_k6_3__");
2597 defineCPUMacros(Builder, "k6");
2600 case CK_AthlonThunderbird:
2604 defineCPUMacros(Builder, "athlon");
2605 if (SSELevel != NoSSE) {
2606 Builder.defineMacro("__athlon_sse__");
2607 Builder.defineMacro("__tune_athlon_sse__");
2614 case CK_OpteronSSE3:
2616 case CK_Athlon64SSE3:
2618 defineCPUMacros(Builder, "k8");
2621 defineCPUMacros(Builder, "amdfam10");
2624 defineCPUMacros(Builder, "btver1");
2627 defineCPUMacros(Builder, "btver2");
2630 defineCPUMacros(Builder, "bdver1");
2633 defineCPUMacros(Builder, "bdver2");
2636 defineCPUMacros(Builder, "geode");
2640 // Target properties.
2641 Builder.defineMacro("__LITTLE_ENDIAN__");
2642 Builder.defineMacro("__REGISTER_PREFIX__", "");
2644 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2645 // functions in glibc header files that use FP Stack inline asm which the
2646 // backend can't deal with (PR879).
2647 Builder.defineMacro("__NO_MATH_INLINES");
2650 Builder.defineMacro("__AES__");
2653 Builder.defineMacro("__PCLMUL__");
2656 Builder.defineMacro("__LZCNT__");
2659 Builder.defineMacro("__RDRND__");
2662 Builder.defineMacro("__BMI__");
2665 Builder.defineMacro("__BMI2__");
2668 Builder.defineMacro("__POPCNT__");
2671 Builder.defineMacro("__RTM__");
2674 Builder.defineMacro("__PRFCHW__");
2677 Builder.defineMacro("__RDSEED__");
2680 Builder.defineMacro("__SSE4A__");
2683 Builder.defineMacro("__FMA4__");
2686 Builder.defineMacro("__FMA__");
2689 Builder.defineMacro("__XOP__");
2692 Builder.defineMacro("__F16C__");
2694 // Each case falls through to the previous one here.
2697 Builder.defineMacro("__AVX2__");
2699 Builder.defineMacro("__AVX__");
2701 Builder.defineMacro("__SSE4_2__");
2703 Builder.defineMacro("__SSE4_1__");
2705 Builder.defineMacro("__SSSE3__");
2707 Builder.defineMacro("__SSE3__");
2709 Builder.defineMacro("__SSE2__");
2710 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
2712 Builder.defineMacro("__SSE__");
2713 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
2718 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2727 Builder.defineMacro("_M_IX86_FP", Twine(2));
2730 Builder.defineMacro("_M_IX86_FP", Twine(1));
2733 Builder.defineMacro("_M_IX86_FP", Twine(0));
2737 // Each case falls through to the previous one here.
2738 switch (MMX3DNowLevel) {
2739 case AMD3DNowAthlon:
2740 Builder.defineMacro("__3dNOW_A__");
2742 Builder.defineMacro("__3dNOW__");
2744 Builder.defineMacro("__MMX__");
2749 if (CPU >= CK_i486) {
2750 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2751 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2752 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2755 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2758 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2759 return llvm::StringSwitch<bool>(Feature)
2760 .Case("aes", HasAES)
2761 .Case("avx", SSELevel >= AVX)
2762 .Case("avx2", SSELevel >= AVX2)
2763 .Case("bmi", HasBMI)
2764 .Case("bmi2", HasBMI2)
2765 .Case("fma", HasFMA)
2766 .Case("fma4", HasFMA4)
2767 .Case("lzcnt", HasLZCNT)
2768 .Case("rdrnd", HasRDRND)
2769 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2770 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2771 .Case("mmx", MMX3DNowLevel >= MMX)
2772 .Case("pclmul", HasPCLMUL)
2773 .Case("popcnt", HasPOPCNT)
2774 .Case("rtm", HasRTM)
2775 .Case("prfchw", HasPRFCHW)
2776 .Case("rdseed", HasRDSEED)
2777 .Case("sse", SSELevel >= SSE1)
2778 .Case("sse2", SSELevel >= SSE2)
2779 .Case("sse3", SSELevel >= SSE3)
2780 .Case("ssse3", SSELevel >= SSSE3)
2781 .Case("sse41", SSELevel >= SSE41)
2782 .Case("sse42", SSELevel >= SSE42)
2783 .Case("sse4a", HasSSE4a)
2785 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2786 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2787 .Case("xop", HasXOP)
2788 .Case("f16c", HasF16C)
2793 X86TargetInfo::validateAsmConstraint(const char *&Name,
2794 TargetInfo::ConstraintInfo &Info) const {
2796 default: return false;
2797 case 'Y': // first letter of a pair:
2798 switch (*(Name+1)) {
2799 default: return false;
2800 case '0': // First SSE register.
2801 case 't': // Any SSE register, when SSE2 is enabled.
2802 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
2803 case 'm': // any MMX register, when inter-unit moves enabled.
2804 break; // falls through to setAllowsRegister.
2812 case 'A': // edx:eax.
2813 case 'f': // any x87 floating point stack register.
2814 case 't': // top of floating point stack.
2815 case 'u': // second from top of floating point stack.
2816 case 'q': // Any register accessible as [r]l: a, b, c, and d.
2817 case 'y': // Any MMX register.
2818 case 'x': // Any SSE register.
2819 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2820 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2821 case 'l': // "Index" registers: any general register that can be used as an
2822 // index in a base+index memory access.
2823 Info.setAllowsRegister();
2825 case 'C': // SSE floating point constant.
2826 case 'G': // x87 floating point constant.
2827 case 'e': // 32-bit signed integer constant for use with zero-extending
2828 // x86_64 instructions.
2829 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2830 // x86_64 instructions.
2837 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2838 switch (*Constraint) {
2839 case 'a': return std::string("{ax}");
2840 case 'b': return std::string("{bx}");
2841 case 'c': return std::string("{cx}");
2842 case 'd': return std::string("{dx}");
2843 case 'S': return std::string("{si}");
2844 case 'D': return std::string("{di}");
2845 case 'p': // address
2846 return std::string("im");
2847 case 't': // top of floating point stack.
2848 return std::string("{st}");
2849 case 'u': // second from top of floating point stack.
2850 return std::string("{st(1)}"); // second from top of floating point stack.
2852 return std::string(1, *Constraint);
2855 } // end anonymous namespace
2858 // X86-32 generic target
2859 class X86_32TargetInfo : public X86TargetInfo {
2861 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2862 DoubleAlign = LongLongAlign = 32;
2863 LongDoubleWidth = 96;
2864 LongDoubleAlign = 32;
2865 SuitableAlign = 128;
2866 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2867 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2868 "a0:0:64-f80:32:32-n8:16:32-S128";
2869 SizeType = UnsignedInt;
2870 PtrDiffType = SignedInt;
2871 IntPtrType = SignedInt;
2874 // Use fpret for all types.
2875 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2876 (1 << TargetInfo::Double) |
2877 (1 << TargetInfo::LongDouble));
2879 // x86-32 has atomics up to 8 bytes
2880 // FIXME: Check that we actually have cmpxchg8b before setting
2881 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2882 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2884 virtual BuiltinVaListKind getBuiltinVaListKind() const {
2885 return TargetInfo::CharPtrBuiltinVaList;
2888 int getEHDataRegisterNumber(unsigned RegNo) const {
2889 if (RegNo == 0) return 0;
2890 if (RegNo == 1) return 2;
2893 virtual bool validateInputSize(StringRef Constraint,
2894 unsigned Size) const {
2895 switch (Constraint[0]) {
2907 } // end anonymous namespace
2910 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2912 NetBSDI386TargetInfo(const std::string &triple) :
2913 NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2916 virtual unsigned getFloatEvalMethod() const {
2917 // NetBSD defaults to "double" rounding
2921 } // end anonymous namespace
2924 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2926 OpenBSDI386TargetInfo(const std::string& triple) :
2927 OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2928 SizeType = UnsignedLong;
2929 IntPtrType = SignedLong;
2930 PtrDiffType = SignedLong;
2933 } // end anonymous namespace
2936 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2938 BitrigI386TargetInfo(const std::string& triple) :
2939 BitrigTargetInfo<X86_32TargetInfo>(triple) {
2940 SizeType = UnsignedLong;
2941 IntPtrType = SignedLong;
2942 PtrDiffType = SignedLong;
2945 } // end anonymous namespace
2948 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2950 DarwinI386TargetInfo(const std::string& triple) :
2951 DarwinTargetInfo<X86_32TargetInfo>(triple) {
2952 LongDoubleWidth = 128;
2953 LongDoubleAlign = 128;
2954 SuitableAlign = 128;
2955 MaxVectorAlign = 256;
2956 SizeType = UnsignedLong;
2957 IntPtrType = SignedLong;
2958 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2959 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2960 "a0:0:64-f80:128:128-n8:16:32-S128";
2961 HasAlignMac68kSupport = true;
2965 } // end anonymous namespace
2968 // x86-32 Windows target
2969 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2971 WindowsX86_32TargetInfo(const std::string& triple)
2972 : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2973 TLSSupported = false;
2974 WCharType = UnsignedShort;
2975 DoubleAlign = LongLongAlign = 64;
2976 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2977 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2978 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2980 virtual void getTargetDefines(const LangOptions &Opts,
2981 MacroBuilder &Builder) const {
2982 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2985 } // end anonymous namespace
2989 // x86-32 Windows Visual Studio target
2990 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2992 VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2993 : WindowsX86_32TargetInfo(triple) {
2994 LongDoubleWidth = LongDoubleAlign = 64;
2995 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2997 virtual void getTargetDefines(const LangOptions &Opts,
2998 MacroBuilder &Builder) const {
2999 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3000 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3001 // The value of the following reflects processor type.
3002 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3003 // We lost the original triple, so we use the default.
3004 Builder.defineMacro("_M_IX86", "600");
3007 } // end anonymous namespace
3010 // x86-32 MinGW target
3011 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3013 MinGWX86_32TargetInfo(const std::string& triple)
3014 : WindowsX86_32TargetInfo(triple) {
3016 virtual void getTargetDefines(const LangOptions &Opts,
3017 MacroBuilder &Builder) const {
3018 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3019 DefineStd(Builder, "WIN32", Opts);
3020 DefineStd(Builder, "WINNT", Opts);
3021 Builder.defineMacro("_X86_");
3022 Builder.defineMacro("__MSVCRT__");
3023 Builder.defineMacro("__MINGW32__");
3025 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3026 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3027 if (Opts.MicrosoftExt)
3028 // Provide "as-is" __declspec.
3029 Builder.defineMacro("__declspec", "__declspec");
3031 // Provide alias of __attribute__ like mingw32-gcc.
3032 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3035 } // end anonymous namespace
3038 // x86-32 Cygwin target
3039 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3041 CygwinX86_32TargetInfo(const std::string& triple)
3042 : X86_32TargetInfo(triple) {
3043 TLSSupported = false;
3044 WCharType = UnsignedShort;
3045 DoubleAlign = LongLongAlign = 64;
3046 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3047 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3048 "a0:0:64-f80:32:32-n8:16:32-S32";
3050 virtual void getTargetDefines(const LangOptions &Opts,
3051 MacroBuilder &Builder) const {
3052 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3053 Builder.defineMacro("_X86_");
3054 Builder.defineMacro("__CYGWIN__");
3055 Builder.defineMacro("__CYGWIN32__");
3056 DefineStd(Builder, "unix", Opts);
3058 Builder.defineMacro("_GNU_SOURCE");
3061 } // end anonymous namespace
3064 // x86-32 Haiku target
3065 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3067 HaikuX86_32TargetInfo(const std::string& triple)
3068 : X86_32TargetInfo(triple) {
3069 SizeType = UnsignedLong;
3070 IntPtrType = SignedLong;
3071 PtrDiffType = SignedLong;
3072 ProcessIDType = SignedLong;
3073 this->UserLabelPrefix = "";
3074 this->TLSSupported = false;
3076 virtual void getTargetDefines(const LangOptions &Opts,
3077 MacroBuilder &Builder) const {
3078 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3079 Builder.defineMacro("__INTEL__");
3080 Builder.defineMacro("__HAIKU__");
3083 } // end anonymous namespace
3086 template<typename Target>
3087 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3089 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3090 MacroBuilder &Builder) const {
3091 // RTEMS defines; list based off of gcc output
3093 Builder.defineMacro("__rtems__");
3094 Builder.defineMacro("__ELF__");
3097 RTEMSTargetInfo(const std::string &triple)
3098 : OSTargetInfo<Target>(triple) {
3099 this->UserLabelPrefix = "";
3101 llvm::Triple Triple(triple);
3102 switch (Triple.getArch()) {
3104 case llvm::Triple::x86:
3105 // this->MCountName = ".mcount";
3107 case llvm::Triple::mips:
3108 case llvm::Triple::mipsel:
3109 case llvm::Triple::ppc:
3110 case llvm::Triple::ppc64:
3111 // this->MCountName = "_mcount";
3113 case llvm::Triple::arm:
3114 // this->MCountName = "__mcount";
3122 // x86-32 RTEMS target
3123 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3125 RTEMSX86_32TargetInfo(const std::string& triple)
3126 : X86_32TargetInfo(triple) {
3127 SizeType = UnsignedLong;
3128 IntPtrType = SignedLong;
3129 PtrDiffType = SignedLong;
3130 this->UserLabelPrefix = "";
3132 virtual void getTargetDefines(const LangOptions &Opts,
3133 MacroBuilder &Builder) const {
3134 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3135 Builder.defineMacro("__INTEL__");
3136 Builder.defineMacro("__rtems__");
3139 } // end anonymous namespace
3142 // x86-64 generic target
3143 class X86_64TargetInfo : public X86TargetInfo {
3145 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3146 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3147 LongDoubleWidth = 128;
3148 LongDoubleAlign = 128;
3149 LargeArrayMinWidth = 128;
3150 LargeArrayAlign = 128;
3151 SuitableAlign = 128;
3152 IntMaxType = SignedLong;
3153 UIntMaxType = UnsignedLong;
3154 Int64Type = SignedLong;
3157 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3158 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3159 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3161 // Use fpret only for long double.
3162 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3164 // Use fp2ret for _Complex long double.
3165 ComplexLongDoubleUsesFP2Ret = true;
3167 // x86-64 has atomics up to 16 bytes.
3168 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3169 // on CPUs with cmpxchg16b
3170 MaxAtomicPromoteWidth = 128;
3171 MaxAtomicInlineWidth = 64;
3173 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3174 return TargetInfo::X86_64ABIBuiltinVaList;
3177 int getEHDataRegisterNumber(unsigned RegNo) const {
3178 if (RegNo == 0) return 0;
3179 if (RegNo == 1) return 1;
3183 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3184 return (CC == CC_Default ||
3186 CC == CC_IntelOclBicc ||
3187 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3190 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3195 } // end anonymous namespace
3198 // x86-64 Windows target
3199 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3201 WindowsX86_64TargetInfo(const std::string& triple)
3202 : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3203 TLSSupported = false;
3204 WCharType = UnsignedShort;
3205 LongWidth = LongAlign = 32;
3206 DoubleAlign = LongLongAlign = 64;
3207 IntMaxType = SignedLongLong;
3208 UIntMaxType = UnsignedLongLong;
3209 Int64Type = SignedLongLong;
3210 SizeType = UnsignedLongLong;
3211 PtrDiffType = SignedLongLong;
3212 IntPtrType = SignedLongLong;
3213 this->UserLabelPrefix = "";
3215 virtual void getTargetDefines(const LangOptions &Opts,
3216 MacroBuilder &Builder) const {
3217 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3218 Builder.defineMacro("_WIN64");
3220 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3221 return TargetInfo::CharPtrBuiltinVaList;
3223 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3224 return (CC == CC_C ||
3225 CC == CC_IntelOclBicc ||
3226 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3229 } // end anonymous namespace
3232 // x86-64 Windows Visual Studio target
3233 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3235 VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3236 : WindowsX86_64TargetInfo(triple) {
3237 LongDoubleWidth = LongDoubleAlign = 64;
3238 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3240 virtual void getTargetDefines(const LangOptions &Opts,
3241 MacroBuilder &Builder) const {
3242 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3243 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3244 Builder.defineMacro("_M_X64");
3245 Builder.defineMacro("_M_AMD64");
3248 } // end anonymous namespace
3251 // x86-64 MinGW target
3252 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3254 MinGWX86_64TargetInfo(const std::string& triple)
3255 : WindowsX86_64TargetInfo(triple) {
3257 virtual void getTargetDefines(const LangOptions &Opts,
3258 MacroBuilder &Builder) const {
3259 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3260 DefineStd(Builder, "WIN64", Opts);
3261 Builder.defineMacro("__MSVCRT__");
3262 Builder.defineMacro("__MINGW32__");
3263 Builder.defineMacro("__MINGW64__");
3265 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3266 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3267 if (Opts.MicrosoftExt)
3268 // Provide "as-is" __declspec.
3269 Builder.defineMacro("__declspec", "__declspec");
3271 // Provide alias of __attribute__ like mingw32-gcc.
3272 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3275 } // end anonymous namespace
3278 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3280 DarwinX86_64TargetInfo(const std::string& triple)
3281 : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3282 Int64Type = SignedLongLong;
3283 MaxVectorAlign = 256;
3286 } // end anonymous namespace
3289 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3291 OpenBSDX86_64TargetInfo(const std::string& triple)
3292 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3293 IntMaxType = SignedLongLong;
3294 UIntMaxType = UnsignedLongLong;
3295 Int64Type = SignedLongLong;
3298 } // end anonymous namespace
3301 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3303 BitrigX86_64TargetInfo(const std::string& triple)
3304 : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3305 IntMaxType = SignedLongLong;
3306 UIntMaxType = UnsignedLongLong;
3307 Int64Type = SignedLongLong;
3313 class AArch64TargetInfo : public TargetInfo {
3314 static const char * const GCCRegNames[];
3315 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3317 static const Builtin::Info BuiltinInfo[];
3319 AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3321 LongWidth = LongAlign = 64;
3322 LongDoubleWidth = LongDoubleAlign = 128;
3323 PointerWidth = PointerAlign = 64;
3324 SuitableAlign = 128;
3325 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3326 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3327 "f128:128:128-n32:64-S128";
3329 WCharType = UnsignedInt;
3330 LongDoubleFormat = &llvm::APFloat::IEEEquad;
3332 // AArch64 backend supports 64-bit operations at the moment. In principle
3333 // 128-bit is possible if register-pairs are used.
3334 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3336 TheCXXABI.set(TargetCXXABI::GenericAArch64);
3338 virtual void getTargetDefines(const LangOptions &Opts,
3339 MacroBuilder &Builder) const {
3340 // GCC defines theses currently
3341 Builder.defineMacro("__aarch64__");
3342 Builder.defineMacro("__AARCH64EL__");
3344 // ACLE predefines. Many can only have one possible value on v8 AArch64.
3346 // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3347 // which was intended to be compatible with a 64-bit implementation. They
3348 // will need updating when a real 64-bit ACLE exists. Particularly pressing
3349 // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3350 Builder.defineMacro("__ARM_ACLE", "101");
3351 Builder.defineMacro("__ARM_ARCH", "8");
3352 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3354 Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3355 Builder.defineMacro("__ARM_FEATURE_CLZ");
3356 Builder.defineMacro("__ARM_FEATURE_FMA");
3358 // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3359 // 128-bit LDXP present, at which point this becomes 0x1f.
3360 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3362 // 0xe implies support for half, single and double precision operations.
3363 Builder.defineMacro("__ARM_FP", "0xe");
3365 // PCS specifies this for SysV variants, which is all we support. Other ABIs
3366 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3367 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3369 if (Opts.FastMath || Opts.FiniteMathOnly)
3370 Builder.defineMacro("__ARM_FP_FAST");
3372 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3373 Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3375 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3376 Opts.ShortWChar ? "2" : "4");
3378 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3379 Opts.ShortEnums ? "1" : "4");
3382 Builder.defineMacro("__ARM_BIG_ENDIAN");
3384 virtual void getTargetBuiltins(const Builtin::Info *&Records,
3385 unsigned &NumRecords) const {
3386 Records = BuiltinInfo;
3387 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3389 virtual bool hasFeature(StringRef Feature) const {
3390 return Feature == "aarch64";
3392 virtual void getGCCRegNames(const char * const *&Names,
3393 unsigned &NumNames) const;
3394 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3395 unsigned &NumAliases) const;
3397 virtual bool isCLZForZeroUndef() const { return false; }
3399 virtual bool validateAsmConstraint(const char *&Name,
3400 TargetInfo::ConstraintInfo &Info) const {
3402 default: return false;
3403 case 'w': // An FP/SIMD vector register
3404 Info.setAllowsRegister();
3406 case 'I': // Constant that can be used with an ADD instruction
3407 case 'J': // Constant that can be used with a SUB instruction
3408 case 'K': // Constant that can be used with a 32-bit logical instruction
3409 case 'L': // Constant that can be used with a 64-bit logical instruction
3410 case 'M': // Constant that can be used as a 32-bit MOV immediate
3411 case 'N': // Constant that can be used as a 64-bit MOV immediate
3412 case 'Y': // Floating point constant zero
3413 case 'Z': // Integer constant zero
3415 case 'Q': // A memory reference with base register and no offset
3416 Info.setAllowsMemory();
3418 case 'S': // A symbolic address
3419 Info.setAllowsRegister();
3422 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3423 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3424 // Usa: An absolute symbolic address
3425 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3426 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3430 virtual const char *getClobbers() const {
3431 // There are no AArch64 clobbers shared by all asm statements.
3435 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3436 return TargetInfo::AArch64ABIBuiltinVaList;
3440 const char * const AArch64TargetInfo::GCCRegNames[] = {
3441 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3442 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3443 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3444 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3446 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3447 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3448 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3449 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3451 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3452 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3453 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3454 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3456 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3457 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3458 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3459 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3461 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3462 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3463 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3464 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3466 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3467 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3468 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3469 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3471 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3472 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3473 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3474 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3477 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3478 unsigned &NumNames) const {
3479 Names = GCCRegNames;
3480 NumNames = llvm::array_lengthof(GCCRegNames);
3483 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3484 { { "x16" }, "ip0"},
3485 { { "x17" }, "ip1"},
3486 { { "x29" }, "fp" },
3490 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3491 unsigned &NumAliases) const {
3492 Aliases = GCCRegAliases;
3493 NumAliases = llvm::array_lengthof(GCCRegAliases);
3497 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3498 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3499 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3501 #include "clang/Basic/BuiltinsAArch64.def"
3504 } // end anonymous namespace
3507 class ARMTargetInfo : public TargetInfo {
3508 // Possible FPU choices.
3516 static bool FPUModeIsVFP(FPUMode Mode) {
3517 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3520 static const TargetInfo::GCCRegAlias GCCRegAliases[];
3521 static const char * const GCCRegNames[];
3523 std::string ABI, CPU;
3527 unsigned IsAAPCS : 1;
3528 unsigned IsThumb : 1;
3530 // Initialized via features.
3531 unsigned SoftFloat : 1;
3532 unsigned SoftFloatABI : 1;
3534 static const Builtin::Info BuiltinInfo[];
3536 static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3537 // On linux, binaries targeting old cpus call functions in libgcc to
3538 // perform atomic operations. The implementation in libgcc then calls into
3539 // the kernel which on armv6 and newer uses ldrex and strex. The net result
3540 // is that if we assume the kernel is at least as recent as the hardware,
3541 // it is safe to use atomic instructions on armv6 and newer.
3542 if (T.getOS() != llvm::Triple::Linux && T.getOS() != llvm::Triple::FreeBSD)
3544 StringRef ArchName = T.getArchName();
3545 if (T.getArch() == llvm::Triple::arm) {
3546 if (!ArchName.startswith("armv"))
3548 StringRef VersionStr = ArchName.substr(4);
3550 if (VersionStr.getAsInteger(10, Version))
3552 return Version >= 6;
3554 assert(T.getArch() == llvm::Triple::thumb);
3555 if (!ArchName.startswith("thumbv"))
3557 StringRef VersionStr = ArchName.substr(6);
3559 if (VersionStr.getAsInteger(10, Version))
3561 return Version >= 7;
3565 ARMTargetInfo(const std::string &TripleStr)
3566 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3569 SizeType = UnsignedInt;
3570 PtrDiffType = SignedInt;
3571 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3572 WCharType = UnsignedInt;
3574 // {} in inline assembly are neon specifiers, not assembly variant
3576 NoAsmVariants = true;
3578 // FIXME: Should we just treat this as a feature?
3579 IsThumb = getTriple().getArchName().startswith("thumb");
3581 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3582 // so set preferred for small types to 32.
3583 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3584 "i64:64:64-f32:32:32-f64:64:64-"
3585 "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3587 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3588 "i64:64:64-f32:32:32-f64:64:64-"
3589 "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3592 // ARM targets default to using the ARM C++ ABI.
3593 TheCXXABI.set(TargetCXXABI::GenericARM);
3595 // ARM has atomics up to 8 bytes
3596 MaxAtomicPromoteWidth = 64;
3597 if (shouldUseInlineAtomic(getTriple()))
3598 MaxAtomicInlineWidth = 64;
3600 // Do force alignment of members that follow zero length bitfields. If
3601 // the alignment of the zero-length bitfield is greater than the member
3602 // that follows it, `bar', `bar' will be aligned as the type of the
3603 // zero length bitfield.
3604 UseZeroLengthBitfieldAlignment = true;
3606 virtual const char *getABI() const { return ABI.c_str(); }
3607 virtual bool setABI(const std::string &Name) {
3610 // The defaults (above) are for AAPCS, check if we need to change them.
3612 // FIXME: We need support for -meabi... we could just mangle it into the
3614 if (Name == "apcs-gnu") {
3615 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3616 // size_t is unsigned int on FreeBSD.
3617 if (getTriple().getOS() != llvm::Triple::FreeBSD)
3618 SizeType = UnsignedLong;
3620 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3621 WCharType = SignedInt;
3623 // Do not respect the alignment of bit-field types when laying out
3624 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3625 UseBitFieldTypeAlignment = false;
3627 /// gcc forces the alignment to 4 bytes, regardless of the type of the
3628 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
3630 ZeroLengthBitfieldBoundary = 32;
3635 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3636 // so set preferred for small types to 32.
3637 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3638 "i64:32:64-f32:32:32-f64:32:64-"
3639 "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3641 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3642 "i64:32:64-f32:32:32-f64:32:64-"
3643 "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3646 // FIXME: Override "preferred align" for double and long long.
3647 } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3649 // FIXME: Enumerated types are variable width in straight AAPCS.
3650 } else if (Name == "aapcs-linux") {
3658 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3659 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3660 Features["vfp2"] = true;
3661 else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3662 CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3663 Features["neon"] = true;
3664 else if (CPU == "swift" || CPU == "cortex-a7") {
3665 Features["vfp4"] = true;
3666 Features["neon"] = true;
3670 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3672 bool Enabled) const {
3673 if (Name == "soft-float" || Name == "soft-float-abi" ||
3674 Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3675 Name == "d16" || Name == "neonfp") {
3676 Features[Name] = Enabled;
3683 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3685 SoftFloat = SoftFloatABI = false;
3686 for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3687 if (Features[i] == "+soft-float")
3689 else if (Features[i] == "+soft-float-abi")
3690 SoftFloatABI = true;
3691 else if (Features[i] == "+vfp2")
3693 else if (Features[i] == "+vfp3")
3695 else if (Features[i] == "+vfp4")
3697 else if (Features[i] == "+neon")
3701 // Remove front-end specific options which the backend handles differently.
3702 std::vector<std::string>::iterator it;
3703 it = std::find(Features.begin(), Features.end(), "+soft-float");
3704 if (it != Features.end())
3706 it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3707 if (it != Features.end())
3711 virtual bool hasFeature(StringRef Feature) const {
3712 return llvm::StringSwitch<bool>(Feature)
3714 .Case("softfloat", SoftFloat)
3715 .Case("thumb", IsThumb)
3716 .Case("neon", FPU == NeonFPU && !SoftFloat &&
3717 StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3720 // FIXME: Should we actually have some table instead of these switches?
3721 static const char *getCPUDefineSuffix(StringRef Name) {
3722 return llvm::StringSwitch<const char*>(Name)
3723 .Cases("arm8", "arm810", "4")
3724 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3725 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3726 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3727 .Case("ep9312", "4T")
3728 .Cases("arm10tdmi", "arm1020t", "5T")
3729 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3730 .Case("arm926ej-s", "5TEJ")
3731 .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3732 .Cases("xscale", "iwmmxt", "5TE")
3733 .Case("arm1136j-s", "6J")
3734 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3735 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3736 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3737 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3738 .Cases("cortex-a9", "cortex-a15", "7A")
3739 .Case("cortex-r5", "7R")
3740 .Case("cortex-a9-mp", "7F")
3741 .Case("swift", "7S")
3742 .Cases("cortex-m3", "cortex-m4", "7M")
3743 .Case("cortex-m0", "6M")
3746 static const char *getCPUProfile(StringRef Name) {
3747 return llvm::StringSwitch<const char*>(Name)
3748 .Cases("cortex-a8", "cortex-a9", "A")
3749 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3750 .Case("cortex-r5", "R")
3753 virtual bool setCPU(const std::string &Name) {
3754 if (!getCPUDefineSuffix(Name))
3760 virtual void getTargetDefines(const LangOptions &Opts,
3761 MacroBuilder &Builder) const {
3762 // Target identification.
3763 Builder.defineMacro("__arm");
3764 Builder.defineMacro("__arm__");
3766 // Target properties.
3767 Builder.defineMacro("__ARMEL__");
3768 Builder.defineMacro("__LITTLE_ENDIAN__");
3769 Builder.defineMacro("__REGISTER_PREFIX__", "");
3771 StringRef CPUArch = getCPUDefineSuffix(CPU);
3772 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3773 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3774 StringRef CPUProfile = getCPUProfile(CPU);
3775 if (!CPUProfile.empty())
3776 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3778 // Subtarget options.
3780 // FIXME: It's more complicated than this and we don't really support
3782 if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3783 Builder.defineMacro("__THUMB_INTERWORK__");
3785 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3786 // M-class CPUs on Darwin follow AAPCS, but not EABI.
3787 if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3788 Builder.defineMacro("__ARM_EABI__");
3789 Builder.defineMacro("__ARM_PCS", "1");
3791 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3792 Builder.defineMacro("__ARM_PCS_VFP", "1");
3796 Builder.defineMacro("__SOFTFP__");
3798 if (CPU == "xscale")
3799 Builder.defineMacro("__XSCALE__");
3801 bool IsARMv7 = CPUArch.startswith("7");
3803 Builder.defineMacro("__THUMBEL__");
3804 Builder.defineMacro("__thumb__");
3805 if (CPUArch == "6T2" || IsARMv7)
3806 Builder.defineMacro("__thumb2__");
3809 // Note, this is always on in gcc, even though it doesn't make sense.
3810 Builder.defineMacro("__APCS_32__");
3812 if (FPUModeIsVFP((FPUMode) FPU)) {
3813 Builder.defineMacro("__VFP_FP__");
3815 Builder.defineMacro("__ARM_VFPV2__");
3817 Builder.defineMacro("__ARM_VFPV3__");
3819 Builder.defineMacro("__ARM_VFPV4__");
3822 // This only gets set when Neon instructions are actually available, unlike
3823 // the VFP define, hence the soft float and arch check. This is subtly
3824 // different from gcc, we follow the intent which was that it should be set
3825 // when Neon instructions are actually available.
3826 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3827 Builder.defineMacro("__ARM_NEON__");
3829 virtual void getTargetBuiltins(const Builtin::Info *&Records,
3830 unsigned &NumRecords) const {
3831 Records = BuiltinInfo;
3832 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3834 virtual bool isCLZForZeroUndef() const { return false; }
3835 virtual BuiltinVaListKind getBuiltinVaListKind() const {
3836 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3838 virtual void getGCCRegNames(const char * const *&Names,
3839 unsigned &NumNames) const;
3840 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3841 unsigned &NumAliases) const;
3842 virtual bool validateAsmConstraint(const char *&Name,
3843 TargetInfo::ConstraintInfo &Info) const {
3848 case 'w': // VFP Floating point register single precision
3849 case 'P': // VFP Floating point register double precision
3850 Info.setAllowsRegister();
3852 case 'Q': // A memory address that is a single base register.
3853 Info.setAllowsMemory();
3855 case 'U': // a memory reference...
3857 case 'q': // ...ARMV4 ldrsb
3858 case 'v': // ...VFP load/store (reg+constant offset)
3859 case 'y': // ...iWMMXt load/store
3860 case 't': // address valid for load/store opaque types wider
3862 case 'n': // valid address for Neon doubleword vector load/store
3863 case 'm': // valid address for Neon element and structure load/store
3864 case 's': // valid address for non-offset loads/stores of quad-word
3865 // values in four ARM registers
3866 Info.setAllowsMemory();
3873 virtual std::string convertConstraint(const char *&Constraint) const {
3875 switch (*Constraint) {
3876 case 'U': // Two-character constraint; add "^" hint for later parsing.
3877 R = std::string("^") + std::string(Constraint, 2);
3880 case 'p': // 'p' should be translated to 'r' by default.
3881 R = std::string("r");
3884 return std::string(1, *Constraint);
3888 virtual bool validateConstraintModifier(StringRef Constraint,
3889 const char Modifier,
3890 unsigned Size) const {
3891 bool isOutput = (Constraint[0] == '=');
3892 bool isInOut = (Constraint[0] == '+');
3894 // Strip off constraint modifiers.
3895 while (Constraint[0] == '=' ||
3896 Constraint[0] == '+' ||
3897 Constraint[0] == '&')
3898 Constraint = Constraint.substr(1);
3900 switch (Constraint[0]) {
3905 return isInOut || (isOutput && Size >= 32) ||
3906 (!isOutput && !isInOut && Size <= 32);
3908 // A register of size 32 cannot fit a vector type.
3916 virtual const char *getClobbers() const {
3917 // FIXME: Is this really right?
3921 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3922 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3925 virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3926 if (RegNo == 0) return 0;
3927 if (RegNo == 1) return 1;
3932 const char * const ARMTargetInfo::GCCRegNames[] = {
3933 // Integer registers
3934 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3935 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3938 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3939 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3940 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3941 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3944 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3945 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3946 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3947 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3950 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3951 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3954 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3955 unsigned &NumNames) const {
3956 Names = GCCRegNames;
3957 NumNames = llvm::array_lengthof(GCCRegNames);
3960 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3970 { { "v6", "rfp" }, "r9" },
3971 { { "sl" }, "r10" },
3972 { { "fp" }, "r11" },
3973 { { "ip" }, "r12" },
3974 { { "r13" }, "sp" },
3975 { { "r14" }, "lr" },
3976 { { "r15" }, "pc" },
3977 // The S, D and Q registers overlap, but aren't really aliases; we
3978 // don't want to substitute one of these for a different-sized one.
3981 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3982 unsigned &NumAliases) const {
3983 Aliases = GCCRegAliases;
3984 NumAliases = llvm::array_lengthof(GCCRegAliases);
3987 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3988 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3989 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3991 #include "clang/Basic/BuiltinsARM.def"
3993 } // end anonymous namespace.
3996 class DarwinARMTargetInfo :
3997 public DarwinTargetInfo<ARMTargetInfo> {
3999 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4000 MacroBuilder &Builder) const {
4001 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4005 DarwinARMTargetInfo(const std::string& triple)
4006 : DarwinTargetInfo<ARMTargetInfo>(triple) {
4007 HasAlignMac68kSupport = true;
4008 // iOS always has 64-bit atomic instructions.
4009 // FIXME: This should be based off of the target features in ARMTargetInfo.
4010 MaxAtomicInlineWidth = 64;
4012 // Darwin on iOS uses a variant of the ARM C++ ABI.
4013 TheCXXABI.set(TargetCXXABI::iOS);
4016 } // end anonymous namespace.
4020 // Hexagon abstract base class
4021 class HexagonTargetInfo : public TargetInfo {
4022 static const Builtin::Info BuiltinInfo[];
4023 static const char * const GCCRegNames[];
4024 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4027 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) {
4029 DescriptionString = ("e-p:32:32:32-"
4030 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4031 "f64:64:64-f32:32:32-a0:0-n32");
4033 // {} in inline assembly are packet specifiers, not assembly variant
4035 NoAsmVariants = true;
4038 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4039 unsigned &NumRecords) const {
4040 Records = BuiltinInfo;
4041 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4044 virtual bool validateAsmConstraint(const char *&Name,
4045 TargetInfo::ConstraintInfo &Info) const {
4049 virtual void getTargetDefines(const LangOptions &Opts,
4050 MacroBuilder &Builder) const;
4052 virtual bool hasFeature(StringRef Feature) const {
4053 return Feature == "hexagon";
4056 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4057 return TargetInfo::CharPtrBuiltinVaList;
4059 virtual void getGCCRegNames(const char * const *&Names,
4060 unsigned &NumNames) const;
4061 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4062 unsigned &NumAliases) const;
4063 virtual const char *getClobbers() const {
4067 static const char *getHexagonCPUSuffix(StringRef Name) {
4068 return llvm::StringSwitch<const char*>(Name)
4069 .Case("hexagonv4", "4")
4070 .Case("hexagonv5", "5")
4074 virtual bool setCPU(const std::string &Name) {
4075 if (!getHexagonCPUSuffix(Name))
4083 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4084 MacroBuilder &Builder) const {
4085 Builder.defineMacro("qdsp6");
4086 Builder.defineMacro("__qdsp6", "1");
4087 Builder.defineMacro("__qdsp6__", "1");
4089 Builder.defineMacro("hexagon");
4090 Builder.defineMacro("__hexagon", "1");
4091 Builder.defineMacro("__hexagon__", "1");
4093 if(CPU == "hexagonv1") {
4094 Builder.defineMacro("__HEXAGON_V1__");
4095 Builder.defineMacro("__HEXAGON_ARCH__", "1");
4096 if(Opts.HexagonQdsp6Compat) {
4097 Builder.defineMacro("__QDSP6_V1__");
4098 Builder.defineMacro("__QDSP6_ARCH__", "1");
4101 else if(CPU == "hexagonv2") {
4102 Builder.defineMacro("__HEXAGON_V2__");
4103 Builder.defineMacro("__HEXAGON_ARCH__", "2");
4104 if(Opts.HexagonQdsp6Compat) {
4105 Builder.defineMacro("__QDSP6_V2__");
4106 Builder.defineMacro("__QDSP6_ARCH__", "2");
4109 else if(CPU == "hexagonv3") {
4110 Builder.defineMacro("__HEXAGON_V3__");
4111 Builder.defineMacro("__HEXAGON_ARCH__", "3");
4112 if(Opts.HexagonQdsp6Compat) {
4113 Builder.defineMacro("__QDSP6_V3__");
4114 Builder.defineMacro("__QDSP6_ARCH__", "3");
4117 else if(CPU == "hexagonv4") {
4118 Builder.defineMacro("__HEXAGON_V4__");
4119 Builder.defineMacro("__HEXAGON_ARCH__", "4");
4120 if(Opts.HexagonQdsp6Compat) {
4121 Builder.defineMacro("__QDSP6_V4__");
4122 Builder.defineMacro("__QDSP6_ARCH__", "4");
4125 else if(CPU == "hexagonv5") {
4126 Builder.defineMacro("__HEXAGON_V5__");
4127 Builder.defineMacro("__HEXAGON_ARCH__", "5");
4128 if(Opts.HexagonQdsp6Compat) {
4129 Builder.defineMacro("__QDSP6_V5__");
4130 Builder.defineMacro("__QDSP6_ARCH__", "5");
4135 const char * const HexagonTargetInfo::GCCRegNames[] = {
4136 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4137 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4138 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4139 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4140 "p0", "p1", "p2", "p3",
4141 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4144 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4145 unsigned &NumNames) const {
4146 Names = GCCRegNames;
4147 NumNames = llvm::array_lengthof(GCCRegNames);
4151 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4152 { { "sp" }, "r29" },
4153 { { "fp" }, "r30" },
4154 { { "lr" }, "r31" },
4157 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4158 unsigned &NumAliases) const {
4159 Aliases = GCCRegAliases;
4160 NumAliases = llvm::array_lengthof(GCCRegAliases);
4164 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4165 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4166 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4168 #include "clang/Basic/BuiltinsHexagon.def"
4174 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4175 class SparcTargetInfo : public TargetInfo {
4176 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4177 static const char * const GCCRegNames[];
4180 SparcTargetInfo(const std::string &triple) : TargetInfo(triple) {}
4182 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4184 bool Enabled) const {
4185 if (Name == "soft-float")
4186 Features[Name] = Enabled;
4192 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4194 for (unsigned i = 0, e = Features.size(); i != e; ++i)
4195 if (Features[i] == "+soft-float")
4198 virtual void getTargetDefines(const LangOptions &Opts,
4199 MacroBuilder &Builder) const {
4200 DefineStd(Builder, "sparc", Opts);
4201 Builder.defineMacro("__REGISTER_PREFIX__", "");
4204 Builder.defineMacro("SOFT_FLOAT", "1");
4207 virtual bool hasFeature(StringRef Feature) const {
4208 return llvm::StringSwitch<bool>(Feature)
4209 .Case("softfloat", SoftFloat)
4210 .Case("sparc", true)
4214 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4215 unsigned &NumRecords) const {
4216 // FIXME: Implement!
4218 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4219 return TargetInfo::VoidPtrBuiltinVaList;
4221 virtual void getGCCRegNames(const char * const *&Names,
4222 unsigned &NumNames) const;
4223 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4224 unsigned &NumAliases) const;
4225 virtual bool validateAsmConstraint(const char *&Name,
4226 TargetInfo::ConstraintInfo &info) const {
4227 // FIXME: Implement!
4230 virtual const char *getClobbers() const {
4231 // FIXME: Implement!
4236 const char * const SparcTargetInfo::GCCRegNames[] = {
4237 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4238 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4239 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4240 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4243 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4244 unsigned &NumNames) const {
4245 Names = GCCRegNames;
4246 NumNames = llvm::array_lengthof(GCCRegNames);
4249 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4260 { { "o2" }, "r10" },
4261 { { "o3" }, "r11" },
4262 { { "o4" }, "r12" },
4263 { { "o5" }, "r13" },
4264 { { "o6", "sp" }, "r14" },
4265 { { "o7" }, "r15" },
4266 { { "l0" }, "r16" },
4267 { { "l1" }, "r17" },
4268 { { "l2" }, "r18" },
4269 { { "l3" }, "r19" },
4270 { { "l4" }, "r20" },
4271 { { "l5" }, "r21" },
4272 { { "l6" }, "r22" },
4273 { { "l7" }, "r23" },
4274 { { "i0" }, "r24" },
4275 { { "i1" }, "r25" },
4276 { { "i2" }, "r26" },
4277 { { "i3" }, "r27" },
4278 { { "i4" }, "r28" },
4279 { { "i5" }, "r29" },
4280 { { "i6", "fp" }, "r30" },
4281 { { "i7" }, "r31" },
4284 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4285 unsigned &NumAliases) const {
4286 Aliases = GCCRegAliases;
4287 NumAliases = llvm::array_lengthof(GCCRegAliases);
4290 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4291 class SparcV8TargetInfo : public SparcTargetInfo {
4293 SparcV8TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4294 // FIXME: Support Sparc quad-precision long double?
4295 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4296 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4299 virtual void getTargetDefines(const LangOptions &Opts,
4300 MacroBuilder &Builder) const {
4301 SparcTargetInfo::getTargetDefines(Opts, Builder);
4302 Builder.defineMacro("__sparcv8");
4306 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4307 class SparcV9TargetInfo : public SparcTargetInfo {
4309 SparcV9TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4310 // FIXME: Support Sparc quad-precision long double?
4311 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4312 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4315 virtual void getTargetDefines(const LangOptions &Opts,
4316 MacroBuilder &Builder) const {
4317 SparcTargetInfo::getTargetDefines(Opts, Builder);
4318 Builder.defineMacro("__sparcv9");
4319 Builder.defineMacro("__arch64__");
4320 // Solaris and its derivative AuroraUX don't need these variants, but the
4322 if (getTriple().getOS() != llvm::Triple::Solaris &&
4323 getTriple().getOS() != llvm::Triple::AuroraUX) {
4324 Builder.defineMacro("__sparc64__");
4325 Builder.defineMacro("__sparc_v9__");
4326 Builder.defineMacro("__sparcv9__");
4331 } // end anonymous namespace.
4334 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4336 AuroraUXSparcV8TargetInfo(const std::string& triple) :
4337 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4338 SizeType = UnsignedInt;
4339 PtrDiffType = SignedInt;
4342 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4344 SolarisSparcV8TargetInfo(const std::string& triple) :
4345 SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4346 SizeType = UnsignedInt;
4347 PtrDiffType = SignedInt;
4350 } // end anonymous namespace.
4353 class SystemZTargetInfo : public TargetInfo {
4354 static const char *const GCCRegNames[];
4357 SystemZTargetInfo(const std::string& triple) : TargetInfo(triple) {
4358 TLSSupported = true;
4359 IntWidth = IntAlign = 32;
4360 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4361 PointerWidth = PointerAlign = 64;
4362 LongDoubleWidth = 128;
4363 LongDoubleAlign = 64;
4364 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4365 MinGlobalAlign = 16;
4366 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4367 "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4368 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4370 virtual void getTargetDefines(const LangOptions &Opts,
4371 MacroBuilder &Builder) const {
4372 Builder.defineMacro("__s390__");
4373 Builder.defineMacro("__s390x__");
4374 Builder.defineMacro("__zarch__");
4375 Builder.defineMacro("__LONG_DOUBLE_128__");
4377 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4378 unsigned &NumRecords) const {
4379 // FIXME: Implement.
4384 virtual void getGCCRegNames(const char *const *&Names,
4385 unsigned &NumNames) const;
4386 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4387 unsigned &NumAliases) const {
4392 virtual bool validateAsmConstraint(const char *&Name,
4393 TargetInfo::ConstraintInfo &info) const;
4394 virtual const char *getClobbers() const {
4395 // FIXME: Is this really right?
4398 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4399 return TargetInfo::SystemZBuiltinVaList;
4403 const char *const SystemZTargetInfo::GCCRegNames[] = {
4404 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4405 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4406 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
4407 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
4410 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4411 unsigned &NumNames) const {
4412 Names = GCCRegNames;
4413 NumNames = llvm::array_lengthof(GCCRegNames);
4416 bool SystemZTargetInfo::
4417 validateAsmConstraint(const char *&Name,
4418 TargetInfo::ConstraintInfo &Info) const {
4423 case 'a': // Address register
4424 case 'd': // Data register (equivalent to 'r')
4425 case 'f': // Floating-point register
4426 Info.setAllowsRegister();
4429 case 'I': // Unsigned 8-bit constant
4430 case 'J': // Unsigned 12-bit constant
4431 case 'K': // Signed 16-bit constant
4432 case 'L': // Signed 20-bit displacement (on all targets we support)
4433 case 'M': // 0x7fffffff
4436 case 'Q': // Memory with base and unsigned 12-bit displacement
4437 case 'R': // Likewise, plus an index
4438 case 'S': // Memory with base and signed 20-bit displacement
4439 case 'T': // Likewise, plus an index
4440 Info.setAllowsMemory();
4447 class MSP430TargetInfo : public TargetInfo {
4448 static const char * const GCCRegNames[];
4450 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4452 TLSSupported = false;
4453 IntWidth = 16; IntAlign = 16;
4454 LongWidth = 32; LongLongWidth = 64;
4455 LongAlign = LongLongAlign = 16;
4456 PointerWidth = 16; PointerAlign = 16;
4458 SizeType = UnsignedInt;
4459 IntMaxType = SignedLong;
4460 UIntMaxType = UnsignedLong;
4461 IntPtrType = SignedShort;
4462 PtrDiffType = SignedInt;
4463 SigAtomicType = SignedLong;
4464 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4466 virtual void getTargetDefines(const LangOptions &Opts,
4467 MacroBuilder &Builder) const {
4468 Builder.defineMacro("MSP430");
4469 Builder.defineMacro("__MSP430__");
4470 // FIXME: defines for different 'flavours' of MCU
4472 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4473 unsigned &NumRecords) const {
4474 // FIXME: Implement.
4478 virtual bool hasFeature(StringRef Feature) const {
4479 return Feature == "msp430";
4481 virtual void getGCCRegNames(const char * const *&Names,
4482 unsigned &NumNames) const;
4483 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4484 unsigned &NumAliases) const {
4489 virtual bool validateAsmConstraint(const char *&Name,
4490 TargetInfo::ConstraintInfo &info) const {
4491 // No target constraints for now.
4494 virtual const char *getClobbers() const {
4495 // FIXME: Is this really right?
4498 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4500 return TargetInfo::CharPtrBuiltinVaList;
4504 const char * const MSP430TargetInfo::GCCRegNames[] = {
4505 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4506 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4509 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4510 unsigned &NumNames) const {
4511 Names = GCCRegNames;
4512 NumNames = llvm::array_lengthof(GCCRegNames);
4518 // LLVM and Clang cannot be used directly to output native binaries for
4519 // target, but is used to compile C code to llvm bitcode with correct
4520 // type and alignment information.
4522 // TCE uses the llvm bitcode as input and uses it for generating customized
4523 // target processor and program binary. TCE co-design environment is
4524 // publicly available in http://tce.cs.tut.fi
4526 static const unsigned TCEOpenCLAddrSpaceMap[] = {
4529 5, // opencl_constant
4535 class TCETargetInfo : public TargetInfo{
4537 TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4538 TLSSupported = false;
4540 LongWidth = LongLongWidth = 32;
4543 LongAlign = LongLongAlign = 32;
4546 SizeType = UnsignedInt;
4547 IntMaxType = SignedLong;
4548 UIntMaxType = UnsignedLong;
4549 IntPtrType = SignedInt;
4550 PtrDiffType = SignedInt;
4555 LongDoubleWidth = 32;
4556 LongDoubleAlign = 32;
4557 FloatFormat = &llvm::APFloat::IEEEsingle;
4558 DoubleFormat = &llvm::APFloat::IEEEsingle;
4559 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4560 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4561 "i16:16:32-i32:32:32-i64:32:32-"
4562 "f32:32:32-f64:32:32-v64:32:32-"
4563 "v128:32:32-a0:0:32-n32";
4564 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4567 virtual void getTargetDefines(const LangOptions &Opts,
4568 MacroBuilder &Builder) const {
4569 DefineStd(Builder, "tce", Opts);
4570 Builder.defineMacro("__TCE__");
4571 Builder.defineMacro("__TCE_V1__");
4573 virtual bool hasFeature(StringRef Feature) const {
4574 return Feature == "tce";
4577 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4578 unsigned &NumRecords) const {}
4579 virtual const char *getClobbers() const {
4582 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4583 return TargetInfo::VoidPtrBuiltinVaList;
4585 virtual void getGCCRegNames(const char * const *&Names,
4586 unsigned &NumNames) const {}
4587 virtual bool validateAsmConstraint(const char *&Name,
4588 TargetInfo::ConstraintInfo &info) const {
4591 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4592 unsigned &NumAliases) const {}
4597 class MipsTargetInfoBase : public TargetInfo {
4598 static const Builtin::Info BuiltinInfo[];
4604 HardFloat, SoftFloat
4614 MipsTargetInfoBase(const std::string& triple,
4615 const std::string& ABIStr,
4616 const std::string& CPUStr)
4617 : TargetInfo(triple),
4621 IsSingleFloat(false),
4622 FloatABI(HardFloat),
4627 virtual const char *getABI() const { return ABI.c_str(); }
4628 virtual bool setABI(const std::string &Name) = 0;
4629 virtual bool setCPU(const std::string &Name) {
4633 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4634 Features[ABI] = true;
4635 Features[CPU] = true;
4638 virtual void getTargetDefines(const LangOptions &Opts,
4639 MacroBuilder &Builder) const {
4640 DefineStd(Builder, "mips", Opts);
4641 Builder.defineMacro("_mips");
4642 Builder.defineMacro("__REGISTER_PREFIX__", "");
4646 Builder.defineMacro("__mips_hard_float", Twine(1));
4649 Builder.defineMacro("__mips_soft_float", Twine(1));
4654 Builder.defineMacro("__mips_single_float", Twine(1));
4657 Builder.defineMacro("__mips16", Twine(1));
4660 Builder.defineMacro("__mips_micromips", Twine(1));
4666 Builder.defineMacro("__mips_dsp_rev", Twine(1));
4667 Builder.defineMacro("__mips_dsp", Twine(1));
4670 Builder.defineMacro("__mips_dsp_rev", Twine(2));
4671 Builder.defineMacro("__mips_dspr2", Twine(1));
4672 Builder.defineMacro("__mips_dsp", Twine(1));
4676 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4677 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4678 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4680 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4681 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4684 virtual void getTargetBuiltins(const Builtin::Info *&Records,
4685 unsigned &NumRecords) const {
4686 Records = BuiltinInfo;
4687 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4689 virtual bool hasFeature(StringRef Feature) const {
4690 return Feature == "mips";
4692 virtual BuiltinVaListKind getBuiltinVaListKind() const {
4693 return TargetInfo::VoidPtrBuiltinVaList;
4695 virtual void getGCCRegNames(const char * const *&Names,
4696 unsigned &NumNames) const {
4697 static const char * const GCCRegNames[] = {
4698 // CPU register names
4699 // Must match second column of GCCRegAliases
4700 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
4701 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
4702 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
4703 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
4704 // Floating point register names
4705 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
4706 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4707 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4708 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4709 // Hi/lo and condition register names
4710 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4711 "$fcc5","$fcc6","$fcc7"
4713 Names = GCCRegNames;
4714 NumNames = llvm::array_lengthof(GCCRegNames);
4716 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4717 unsigned &NumAliases) const = 0;
4718 virtual bool validateAsmConstraint(const char *&Name,
4719 TargetInfo::ConstraintInfo &Info) const {
4724 case 'r': // CPU registers.
4725 case 'd': // Equivalent to "r" unless generating MIPS16 code.
4726 case 'y': // Equivalent to "r", backwards compatibility only.
4727 case 'f': // floating-point registers.
4728 case 'c': // $25 for indirect jumps
4729 case 'l': // lo register
4730 case 'x': // hilo register pair
4731 Info.setAllowsRegister();
4733 case 'R': // An address that can be used in a non-macro load or store
4734 Info.setAllowsMemory();
4739 virtual const char *getClobbers() const {
4740 // FIXME: Implement!
4744 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4746 bool Enabled) const {
4747 if (Name == "soft-float" || Name == "single-float" ||
4748 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4749 Name == "mips32" || Name == "mips32r2" ||
4750 Name == "mips64" || Name == "mips64r2" ||
4751 Name == "mips16" || Name == "micromips" ||
4752 Name == "dsp" || Name == "dspr2") {
4753 Features[Name] = Enabled;
4755 } else if (Name == "32") {
4756 Features["o32"] = Enabled;
4758 } else if (Name == "64") {
4759 Features["n64"] = Enabled;
4765 virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4767 IsMicromips = false;
4768 IsSingleFloat = false;
4769 FloatABI = HardFloat;
4772 for (std::vector<std::string>::iterator it = Features.begin(),
4773 ie = Features.end(); it != ie; ++it) {
4774 if (*it == "+single-float")
4775 IsSingleFloat = true;
4776 else if (*it == "+soft-float")
4777 FloatABI = SoftFloat;
4778 else if (*it == "+mips16")
4780 else if (*it == "+micromips")
4782 else if (*it == "+dsp")
4783 DspRev = std::max(DspRev, DSP1);
4784 else if (*it == "+dspr2")
4785 DspRev = std::max(DspRev, DSP2);
4788 // Remove front-end specific option.
4789 std::vector<std::string>::iterator it =
4790 std::find(Features.begin(), Features.end(), "+soft-float");
4791 if (it != Features.end())
4795 virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4796 if (RegNo == 0) return 4;
4797 if (RegNo == 1) return 5;
4802 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4803 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4804 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4806 #include "clang/Basic/BuiltinsMips.def"
4809 class Mips32TargetInfoBase : public MipsTargetInfoBase {
4811 Mips32TargetInfoBase(const std::string& triple) :
4812 MipsTargetInfoBase(triple, "o32", "mips32") {
4813 SizeType = UnsignedInt;
4814 PtrDiffType = SignedInt;
4815 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4817 virtual bool setABI(const std::string &Name) {
4818 if ((Name == "o32") || (Name == "eabi")) {
4821 } else if (Name == "32") {
4827 virtual void getTargetDefines(const LangOptions &Opts,
4828 MacroBuilder &Builder) const {
4829 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4832 Builder.defineMacro("__mips_o32");
4833 Builder.defineMacro("_ABIO32", "1");
4834 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4836 else if (ABI == "eabi")
4837 Builder.defineMacro("__mips_eabi");
4839 llvm_unreachable("Invalid ABI for Mips32.");
4841 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4842 unsigned &NumAliases) const {
4843 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4853 { { "t2" }, "$10" },
4854 { { "t3" }, "$11" },
4855 { { "t4" }, "$12" },
4856 { { "t5" }, "$13" },
4857 { { "t6" }, "$14" },
4858 { { "t7" }, "$15" },
4859 { { "s0" }, "$16" },
4860 { { "s1" }, "$17" },
4861 { { "s2" }, "$18" },
4862 { { "s3" }, "$19" },
4863 { { "s4" }, "$20" },
4864 { { "s5" }, "$21" },
4865 { { "s6" }, "$22" },
4866 { { "s7" }, "$23" },
4867 { { "t8" }, "$24" },
4868 { { "t9" }, "$25" },
4869 { { "k0" }, "$26" },
4870 { { "k1" }, "$27" },
4871 { { "gp" }, "$28" },
4872 { { "sp","$sp" }, "$29" },
4873 { { "fp","$fp" }, "$30" },
4876 Aliases = GCCRegAliases;
4877 NumAliases = llvm::array_lengthof(GCCRegAliases);
4881 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4883 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4884 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4885 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4887 virtual void getTargetDefines(const LangOptions &Opts,
4888 MacroBuilder &Builder) const {
4889 DefineStd(Builder, "MIPSEB", Opts);
4890 Builder.defineMacro("_MIPSEB");
4891 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4895 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4897 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4899 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4900 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4902 virtual void getTargetDefines(const LangOptions &Opts,
4903 MacroBuilder &Builder) const {
4904 DefineStd(Builder, "MIPSEL", Opts);
4905 Builder.defineMacro("_MIPSEL");
4906 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4910 class Mips64TargetInfoBase : public MipsTargetInfoBase {
4911 virtual void SetDescriptionString(const std::string &Name) = 0;
4913 Mips64TargetInfoBase(const std::string& triple) :
4914 MipsTargetInfoBase(triple, "n64", "mips64") {
4915 LongWidth = LongAlign = 64;
4916 PointerWidth = PointerAlign = 64;
4917 LongDoubleWidth = LongDoubleAlign = 128;
4918 LongDoubleFormat = &llvm::APFloat::IEEEquad;
4919 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4920 LongDoubleWidth = LongDoubleAlign = 64;
4921 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4923 SuitableAlign = 128;
4924 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4926 virtual bool setABI(const std::string &Name) {
4927 SetDescriptionString(Name);
4928 if (Name == "n32") {
4929 LongWidth = LongAlign = 32;
4930 PointerWidth = PointerAlign = 32;
4933 } else if (Name == "n64") {
4936 } else if (Name == "64") {
4942 virtual void getTargetDefines(const LangOptions &Opts,
4943 MacroBuilder &Builder) const {
4944 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4946 Builder.defineMacro("__mips64");
4947 Builder.defineMacro("__mips64__");
4950 Builder.defineMacro("__mips_n32");
4951 Builder.defineMacro("_ABIN32", "2");
4952 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4954 else if (ABI == "n64") {
4955 Builder.defineMacro("__mips_n64");
4956 Builder.defineMacro("_ABI64", "3");
4957 Builder.defineMacro("_MIPS_SIM", "_ABI64");
4960 llvm_unreachable("Invalid ABI for Mips64.");
4962 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4963 unsigned &NumAliases) const {
4964 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4974 { { "a6" }, "$10" },
4975 { { "a7" }, "$11" },
4976 { { "t0" }, "$12" },
4977 { { "t1" }, "$13" },
4978 { { "t2" }, "$14" },
4979 { { "t3" }, "$15" },
4980 { { "s0" }, "$16" },
4981 { { "s1" }, "$17" },
4982 { { "s2" }, "$18" },
4983 { { "s3" }, "$19" },
4984 { { "s4" }, "$20" },
4985 { { "s5" }, "$21" },
4986 { { "s6" }, "$22" },
4987 { { "s7" }, "$23" },
4988 { { "t8" }, "$24" },
4989 { { "t9" }, "$25" },
4990 { { "k0" }, "$26" },
4991 { { "k1" }, "$27" },
4992 { { "gp" }, "$28" },
4993 { { "sp","$sp" }, "$29" },
4994 { { "fp","$fp" }, "$30" },
4997 Aliases = GCCRegAliases;
4998 NumAliases = llvm::array_lengthof(GCCRegAliases);
5002 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5003 virtual void SetDescriptionString(const std::string &Name) {
5004 // Change DescriptionString only if ABI is n32.
5006 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5007 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5008 "v64:64:64-n32:64-S128";
5011 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5012 // Default ABI is n64.
5013 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5014 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5015 "v64:64:64-n32:64-S128";
5017 virtual void getTargetDefines(const LangOptions &Opts,
5018 MacroBuilder &Builder) const {
5019 DefineStd(Builder, "MIPSEB", Opts);
5020 Builder.defineMacro("_MIPSEB");
5021 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5025 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5026 virtual void SetDescriptionString(const std::string &Name) {
5027 // Change DescriptionString only if ABI is n32.
5029 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5030 "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5031 "-v64:64:64-n32:64-S128";
5034 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5035 // Default ABI is n64.
5037 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5038 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5039 "v64:64:64-n32:64-S128";
5041 virtual void getTargetDefines(const LangOptions &Opts,
5042 MacroBuilder &Builder) const {
5043 DefineStd(Builder, "MIPSEL", Opts);
5044 Builder.defineMacro("_MIPSEL");
5045 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5048 } // end anonymous namespace.
5051 class PNaClTargetInfo : public TargetInfo {
5053 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
5055 this->UserLabelPrefix = "";
5056 this->LongAlign = 32;
5057 this->LongWidth = 32;
5058 this->PointerAlign = 32;
5059 this->PointerWidth = 32;
5060 this->IntMaxType = TargetInfo::SignedLongLong;
5061 this->UIntMaxType = TargetInfo::UnsignedLongLong;
5062 this->Int64Type = TargetInfo::SignedLongLong;
5063 this->DoubleAlign = 64;
5064 this->LongDoubleWidth = 64;
5065 this->LongDoubleAlign = 64;
5066 this->SizeType = TargetInfo::UnsignedInt;
5067 this->PtrDiffType = TargetInfo::SignedInt;
5068 this->IntPtrType = TargetInfo::SignedInt;
5069 this->RegParmMax = 0; // Disallow regparm
5070 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5071 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5074 void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5076 virtual void getArchDefines(const LangOptions &Opts,
5077 MacroBuilder &Builder) const {
5078 Builder.defineMacro("__le32__");
5079 Builder.defineMacro("__pnacl__");
5081 virtual void getTargetDefines(const LangOptions &Opts,
5082 MacroBuilder &Builder) const {
5083 Builder.defineMacro("__LITTLE_ENDIAN__");
5084 getArchDefines(Opts, Builder);
5086 virtual bool hasFeature(StringRef Feature) const {
5087 return Feature == "pnacl";
5089 virtual void getTargetBuiltins(const Builtin::Info *&Records,
5090 unsigned &NumRecords) const {
5092 virtual BuiltinVaListKind getBuiltinVaListKind() const {
5093 return TargetInfo::PNaClABIBuiltinVaList;
5095 virtual void getGCCRegNames(const char * const *&Names,
5096 unsigned &NumNames) const;
5097 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5098 unsigned &NumAliases) const;
5099 virtual bool validateAsmConstraint(const char *&Name,
5100 TargetInfo::ConstraintInfo &Info) const {
5104 virtual const char *getClobbers() const {
5109 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5110 unsigned &NumNames) const {
5115 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5116 unsigned &NumAliases) const {
5120 } // end anonymous namespace.
5123 static const unsigned SPIRAddrSpaceMap[] = {
5126 2, // opencl_constant
5131 class SPIRTargetInfo : public TargetInfo {
5132 static const char * const GCCRegNames[];
5133 static const Builtin::Info BuiltinInfo[];
5134 std::vector<StringRef> AvailableFeatures;
5136 SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
5137 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5138 "SPIR target must use unknown OS");
5139 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5140 "SPIR target must use unknown environment type");
5142 TLSSupported = false;
5143 LongWidth = LongAlign = 64;
5144 AddrSpaceMap = &SPIRAddrSpaceMap;
5145 // Define available target features
5146 // These must be defined in sorted order!
5147 NoAsmVariants = true;
5149 virtual void getTargetDefines(const LangOptions &Opts,
5150 MacroBuilder &Builder) const {
5151 DefineStd(Builder, "SPIR", Opts);
5153 virtual bool hasFeature(StringRef Feature) const {
5154 return Feature == "spir";
5157 virtual void getTargetBuiltins(const Builtin::Info *&Records,
5158 unsigned &NumRecords) const {}
5159 virtual const char *getClobbers() const {
5162 virtual void getGCCRegNames(const char * const *&Names,
5163 unsigned &NumNames) const {}
5164 virtual bool validateAsmConstraint(const char *&Name,
5165 TargetInfo::ConstraintInfo &info) const {
5168 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5169 unsigned &NumAliases) const {}
5170 virtual BuiltinVaListKind getBuiltinVaListKind() const {
5171 return TargetInfo::VoidPtrBuiltinVaList;
5176 class SPIR32TargetInfo : public SPIRTargetInfo {
5178 SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5179 PointerWidth = PointerAlign = 32;
5180 SizeType = TargetInfo::UnsignedInt;
5181 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5183 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5184 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5185 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5186 "v512:512:512-v1024:1024:1024";
5188 virtual void getTargetDefines(const LangOptions &Opts,
5189 MacroBuilder &Builder) const {
5190 DefineStd(Builder, "SPIR32", Opts);
5194 class SPIR64TargetInfo : public SPIRTargetInfo {
5196 SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5197 PointerWidth = PointerAlign = 64;
5198 SizeType = TargetInfo::UnsignedLong;
5199 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5201 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5202 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5203 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5204 "v512:512:512-v1024:1024:1024";
5206 virtual void getTargetDefines(const LangOptions &Opts,
5207 MacroBuilder &Builder) const {
5208 DefineStd(Builder, "SPIR64", Opts);
5214 //===----------------------------------------------------------------------===//
5216 //===----------------------------------------------------------------------===//
5218 static TargetInfo *AllocateTarget(const std::string &T) {
5219 llvm::Triple Triple(T);
5220 llvm::Triple::OSType os = Triple.getOS();
5222 switch (Triple.getArch()) {
5226 case llvm::Triple::hexagon:
5227 return new HexagonTargetInfo(T);
5229 case llvm::Triple::aarch64:
5231 case llvm::Triple::Linux:
5232 return new LinuxTargetInfo<AArch64TargetInfo>(T);
5234 return new AArch64TargetInfo(T);
5237 case llvm::Triple::arm:
5238 case llvm::Triple::thumb:
5239 if (Triple.isOSDarwin())
5240 return new DarwinARMTargetInfo(T);
5243 case llvm::Triple::Linux:
5244 return new LinuxTargetInfo<ARMTargetInfo>(T);
5245 case llvm::Triple::FreeBSD:
5246 return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5247 case llvm::Triple::NetBSD:
5248 return new NetBSDTargetInfo<ARMTargetInfo>(T);
5249 case llvm::Triple::OpenBSD:
5250 return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5251 case llvm::Triple::Bitrig:
5252 return new BitrigTargetInfo<ARMTargetInfo>(T);
5253 case llvm::Triple::RTEMS:
5254 return new RTEMSTargetInfo<ARMTargetInfo>(T);
5255 case llvm::Triple::NaCl:
5256 return new NaClTargetInfo<ARMTargetInfo>(T);
5258 return new ARMTargetInfo(T);
5261 case llvm::Triple::msp430:
5262 return new MSP430TargetInfo(T);
5264 case llvm::Triple::mips:
5266 case llvm::Triple::Linux:
5267 return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5268 case llvm::Triple::RTEMS:
5269 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5270 case llvm::Triple::FreeBSD:
5271 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5272 case llvm::Triple::NetBSD:
5273 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5275 return new Mips32EBTargetInfo(T);
5278 case llvm::Triple::mipsel:
5280 case llvm::Triple::Linux:
5281 return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5282 case llvm::Triple::RTEMS:
5283 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5284 case llvm::Triple::FreeBSD:
5285 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5286 case llvm::Triple::NetBSD:
5287 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5289 return new Mips32ELTargetInfo(T);
5292 case llvm::Triple::mips64:
5294 case llvm::Triple::Linux:
5295 return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5296 case llvm::Triple::RTEMS:
5297 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5298 case llvm::Triple::FreeBSD:
5299 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5300 case llvm::Triple::NetBSD:
5301 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5302 case llvm::Triple::OpenBSD:
5303 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5305 return new Mips64EBTargetInfo(T);
5308 case llvm::Triple::mips64el:
5310 case llvm::Triple::Linux:
5311 return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5312 case llvm::Triple::RTEMS:
5313 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5314 case llvm::Triple::FreeBSD:
5315 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5316 case llvm::Triple::NetBSD:
5317 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5318 case llvm::Triple::OpenBSD:
5319 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5321 return new Mips64ELTargetInfo(T);
5324 case llvm::Triple::le32:
5326 case llvm::Triple::NaCl:
5327 return new NaClTargetInfo<PNaClTargetInfo>(T);
5332 case llvm::Triple::ppc:
5333 if (Triple.isOSDarwin())
5334 return new DarwinPPC32TargetInfo(T);
5336 case llvm::Triple::Linux:
5337 return new LinuxTargetInfo<PPC32TargetInfo>(T);
5338 case llvm::Triple::FreeBSD:
5339 return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5340 case llvm::Triple::NetBSD:
5341 return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5342 case llvm::Triple::OpenBSD:
5343 return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5344 case llvm::Triple::RTEMS:
5345 return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5347 return new PPC32TargetInfo(T);
5350 case llvm::Triple::ppc64:
5351 if (Triple.isOSDarwin())
5352 return new DarwinPPC64TargetInfo(T);
5354 case llvm::Triple::Linux:
5355 return new LinuxTargetInfo<PPC64TargetInfo>(T);
5356 case llvm::Triple::Lv2:
5357 return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5358 case llvm::Triple::FreeBSD:
5359 return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5360 case llvm::Triple::NetBSD:
5361 return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5363 return new PPC64TargetInfo(T);
5366 case llvm::Triple::nvptx:
5367 return new NVPTX32TargetInfo(T);
5368 case llvm::Triple::nvptx64:
5369 return new NVPTX64TargetInfo(T);
5371 case llvm::Triple::mblaze:
5372 return new MBlazeTargetInfo(T);
5374 case llvm::Triple::r600:
5375 return new R600TargetInfo(T);
5377 case llvm::Triple::sparc:
5379 case llvm::Triple::Linux:
5380 return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5381 case llvm::Triple::AuroraUX:
5382 return new AuroraUXSparcV8TargetInfo(T);
5383 case llvm::Triple::Solaris:
5384 return new SolarisSparcV8TargetInfo(T);
5385 case llvm::Triple::NetBSD:
5386 return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5387 case llvm::Triple::OpenBSD:
5388 return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5389 case llvm::Triple::RTEMS:
5390 return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5392 return new SparcV8TargetInfo(T);
5395 case llvm::Triple::sparcv9:
5397 case llvm::Triple::Linux:
5398 return new LinuxTargetInfo<SparcV9TargetInfo>(T);
5399 case llvm::Triple::AuroraUX:
5400 return new AuroraUXTargetInfo<SparcV9TargetInfo>(T);
5401 case llvm::Triple::Solaris:
5402 return new SolarisTargetInfo<SparcV9TargetInfo>(T);
5403 case llvm::Triple::NetBSD:
5404 return new NetBSDTargetInfo<SparcV9TargetInfo>(T);
5405 case llvm::Triple::OpenBSD:
5406 return new OpenBSDTargetInfo<SparcV9TargetInfo>(T);
5407 case llvm::Triple::FreeBSD:
5408 return new FreeBSDTargetInfo<SparcV9TargetInfo>(T);
5410 return new SparcV9TargetInfo(T);
5413 case llvm::Triple::systemz:
5415 case llvm::Triple::Linux:
5416 return new LinuxTargetInfo<SystemZTargetInfo>(T);
5418 return new SystemZTargetInfo(T);
5421 case llvm::Triple::tce:
5422 return new TCETargetInfo(T);
5424 case llvm::Triple::x86:
5425 if (Triple.isOSDarwin())
5426 return new DarwinI386TargetInfo(T);
5429 case llvm::Triple::AuroraUX:
5430 return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5431 case llvm::Triple::Linux:
5432 return new LinuxTargetInfo<X86_32TargetInfo>(T);
5433 case llvm::Triple::DragonFly:
5434 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5435 case llvm::Triple::NetBSD:
5436 return new NetBSDI386TargetInfo(T);
5437 case llvm::Triple::OpenBSD:
5438 return new OpenBSDI386TargetInfo(T);
5439 case llvm::Triple::Bitrig:
5440 return new BitrigI386TargetInfo(T);
5441 case llvm::Triple::FreeBSD:
5442 return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5443 case llvm::Triple::Minix:
5444 return new MinixTargetInfo<X86_32TargetInfo>(T);
5445 case llvm::Triple::Solaris:
5446 return new SolarisTargetInfo<X86_32TargetInfo>(T);
5447 case llvm::Triple::Cygwin:
5448 return new CygwinX86_32TargetInfo(T);
5449 case llvm::Triple::MinGW32:
5450 return new MinGWX86_32TargetInfo(T);
5451 case llvm::Triple::Win32:
5452 return new VisualStudioWindowsX86_32TargetInfo(T);
5453 case llvm::Triple::Haiku:
5454 return new HaikuX86_32TargetInfo(T);
5455 case llvm::Triple::RTEMS:
5456 return new RTEMSX86_32TargetInfo(T);
5457 case llvm::Triple::NaCl:
5458 return new NaClTargetInfo<X86_32TargetInfo>(T);
5460 return new X86_32TargetInfo(T);
5463 case llvm::Triple::x86_64:
5464 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5465 return new DarwinX86_64TargetInfo(T);
5468 case llvm::Triple::AuroraUX:
5469 return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5470 case llvm::Triple::Linux:
5471 return new LinuxTargetInfo<X86_64TargetInfo>(T);
5472 case llvm::Triple::DragonFly:
5473 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5474 case llvm::Triple::NetBSD:
5475 return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5476 case llvm::Triple::OpenBSD:
5477 return new OpenBSDX86_64TargetInfo(T);
5478 case llvm::Triple::Bitrig:
5479 return new BitrigX86_64TargetInfo(T);
5480 case llvm::Triple::FreeBSD:
5481 return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5482 case llvm::Triple::Solaris:
5483 return new SolarisTargetInfo<X86_64TargetInfo>(T);
5484 case llvm::Triple::MinGW32:
5485 return new MinGWX86_64TargetInfo(T);
5486 case llvm::Triple::Win32: // This is what Triple.h supports now.
5487 return new VisualStudioWindowsX86_64TargetInfo(T);
5488 case llvm::Triple::NaCl:
5489 return new NaClTargetInfo<X86_64TargetInfo>(T);
5491 return new X86_64TargetInfo(T);
5494 case llvm::Triple::spir: {
5495 llvm::Triple Triple(T);
5496 if (Triple.getOS() != llvm::Triple::UnknownOS ||
5497 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5499 return new SPIR32TargetInfo(T);
5501 case llvm::Triple::spir64: {
5502 llvm::Triple Triple(T);
5503 if (Triple.getOS() != llvm::Triple::UnknownOS ||
5504 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5506 return new SPIR64TargetInfo(T);
5511 /// CreateTargetInfo - Return the target info object for the specified target
5513 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5514 TargetOptions *Opts) {
5515 llvm::Triple Triple(Opts->Triple);
5517 // Construct the target
5518 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5520 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5523 Target->setTargetOpts(Opts);
5525 // Set the target CPU if specified.
5526 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5527 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5531 // Set the target ABI if specified.
5532 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5533 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5537 // Set the target C++ ABI.
5538 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5539 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5543 // Compute the default target features, we need the target to handle this
5544 // because features may have dependencies on one another.
5545 llvm::StringMap<bool> Features;
5546 Target->getDefaultFeatures(Features);
5548 // Apply the user specified deltas.
5549 // First the enables.
5550 for (std::vector<std::string>::const_iterator
5551 it = Opts->FeaturesAsWritten.begin(),
5552 ie = Opts->FeaturesAsWritten.end();
5554 const char *Name = it->c_str();
5559 // Apply the feature via the target.
5560 if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5561 Diags.Report(diag::err_target_invalid_feature) << Name;
5566 // Then the disables.
5567 for (std::vector<std::string>::const_iterator
5568 it = Opts->FeaturesAsWritten.begin(),
5569 ie = Opts->FeaturesAsWritten.end();
5571 const char *Name = it->c_str();
5576 // Apply the feature via the target.
5577 if (Name[0] != '-' ||
5578 !Target->setFeatureEnabled(Features, Name + 1, false)) {
5579 Diags.Report(diag::err_target_invalid_feature) << Name;
5584 // Add the features to the compile options.
5586 // FIXME: If we are completely confident that we have the right set, we only
5587 // need to pass the minuses.
5588 Opts->Features.clear();
5589 for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5590 ie = Features.end(); it != ie; ++it)
5591 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5592 Target->HandleTargetFeatures(Opts->Features);
5594 return Target.take();