1 //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 #include "EmulateInstructionARM.h"
13 #include "EmulationStateARM.h"
14 #include "lldb/Core/ArchSpec.h"
15 #include "lldb/Core/Address.h"
16 #include "lldb/Core/ConstString.h"
17 #include "lldb/Core/PluginManager.h"
18 #include "lldb/Core/Stream.h"
19 #include "lldb/Interpreter/OptionValueArray.h"
20 #include "lldb/Interpreter/OptionValueDictionary.h"
21 #include "lldb/Symbol/UnwindPlan.h"
23 #include "Plugins/Process/Utility/ARMDefines.h"
24 #include "Plugins/Process/Utility/ARMUtils.h"
25 #include "Utility/ARM_DWARF_Registers.h"
27 #include "llvm/Support/MathExtras.h" // for SignExtend32 template function
28 // and CountTrailingZeros_32 function
31 using namespace lldb_private;
33 // Convenient macro definitions.
34 #define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS)
35 #define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)
37 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
39 //----------------------------------------------------------------------
41 // ITSession implementation
43 //----------------------------------------------------------------------
46 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
48 CountITSize (uint32_t ITMask) {
49 // First count the trailing zeros of the IT mask.
50 uint32_t TZ = llvm::CountTrailingZeros_32(ITMask);
53 #ifdef LLDB_CONFIGURATION_DEBUG
54 printf("Encoding error: IT Mask '0000'\n");
61 // Init ITState. Note that at least one bit is always 1 in mask.
62 bool ITSession::InitIT(uint32_t bits7_0)
64 ITCounter = CountITSize(Bits32(bits7_0, 3, 0));
69 unsigned short FirstCond = Bits32(bits7_0, 7, 4);
72 #ifdef LLDB_CONFIGURATION_DEBUG
73 printf("Encoding error: IT FirstCond '1111'\n");
77 if (FirstCond == 0xE && ITCounter != 1)
79 #ifdef LLDB_CONFIGURATION_DEBUG
80 printf("Encoding error: IT FirstCond '1110' && Mask != '1000'\n");
89 // Update ITState if necessary.
90 void ITSession::ITAdvance()
98 unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1;
99 SetBits32(ITState, 4, 0, NewITState4_0);
103 // Return true if we're inside an IT Block.
104 bool ITSession::InITBlock()
106 return ITCounter != 0;
109 // Return true if we're the last instruction inside an IT Block.
110 bool ITSession::LastInITBlock()
112 return ITCounter == 1;
115 // Get condition bits for the current thumb instruction.
116 uint32_t ITSession::GetCond()
119 return Bits32(ITState, 7, 4);
124 // ARM constants used during decoding
126 #define LDM_REGLIST 1
130 #define PC_REGLIST_BIT 0x8000
132 #define ARMv4 (1u << 0)
133 #define ARMv4T (1u << 1)
134 #define ARMv5T (1u << 2)
135 #define ARMv5TE (1u << 3)
136 #define ARMv5TEJ (1u << 4)
137 #define ARMv6 (1u << 5)
138 #define ARMv6K (1u << 6)
139 #define ARMv6T2 (1u << 7)
140 #define ARMv7 (1u << 8)
141 #define ARMv7S (1u << 9)
142 #define ARMv8 (1u << 10)
143 #define ARMvAll (0xffffffffu)
145 #define ARMV4T_ABOVE (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
146 #define ARMV5_ABOVE (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
147 #define ARMV5TE_ABOVE (ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
148 #define ARMV5J_ABOVE (ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
149 #define ARMV6_ABOVE (ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
150 #define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv7S|ARMv8)
151 #define ARMV7_ABOVE (ARMv7|ARMv7S|ARMv8)
154 #define VFPv1 (1u << 1)
155 #define VFPv2 (1u << 2)
156 #define VFPv3 (1u << 3)
157 #define AdvancedSIMD (1u << 4)
159 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
160 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
161 #define VFPv2v3 (VFPv2 | VFPv3)
163 //----------------------------------------------------------------------
165 // EmulateInstructionARM implementation
167 //----------------------------------------------------------------------
170 EmulateInstructionARM::Initialize ()
172 PluginManager::RegisterPlugin (GetPluginNameStatic (),
173 GetPluginDescriptionStatic (),
178 EmulateInstructionARM::Terminate ()
180 PluginManager::UnregisterPlugin (CreateInstance);
184 EmulateInstructionARM::GetPluginNameStatic ()
186 static ConstString g_name("arm");
191 EmulateInstructionARM::GetPluginDescriptionStatic ()
193 return "Emulate instructions for the ARM architecture.";
197 EmulateInstructionARM::CreateInstance (const ArchSpec &arch, InstructionType inst_type)
199 if (EmulateInstructionARM::SupportsEmulatingIntructionsOfTypeStatic(inst_type))
201 if (arch.GetTriple().getArch() == llvm::Triple::arm)
203 std::unique_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch));
205 if (emulate_insn_ap.get())
206 return emulate_insn_ap.release();
208 else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
210 std::unique_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch));
212 if (emulate_insn_ap.get())
213 return emulate_insn_ap.release();
221 EmulateInstructionARM::SetTargetTriple (const ArchSpec &arch)
223 if (arch.GetTriple().getArch () == llvm::Triple::arm)
225 else if (arch.GetTriple().getArch () == llvm::Triple::thumb)
231 // Write "bits (32) UNKNOWN" to memory address "address". Helper function for many ARM instructions.
233 EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address)
235 EmulateInstruction::Context context;
236 context.type = EmulateInstruction::eContextWriteMemoryRandomBits;
237 context.SetNoArgs ();
239 uint32_t random_data = rand ();
240 const uint32_t addr_byte_size = GetAddressByteSize();
242 if (!MemAWrite (context, address, random_data, addr_byte_size))
248 // Write "bits (32) UNKNOWN" to register n. Helper function for many ARM instructions.
250 EmulateInstructionARM::WriteBits32Unknown (int n)
252 EmulateInstruction::Context context;
253 context.type = EmulateInstruction::eContextWriteRegisterRandomBits;
254 context.SetNoArgs ();
257 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
262 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
269 EmulateInstructionARM::GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo ®_info)
271 if (reg_kind == eRegisterKindGeneric)
275 case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = dwarf_pc; break;
276 case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sp; break;
277 case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_r7; break;
278 case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = dwarf_lr; break;
279 case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = dwarf_cpsr; break;
280 default: return false;
284 if (reg_kind == eRegisterKindDWARF)
285 return GetARMDWARFRegisterInfo(reg_num, reg_info);
290 EmulateInstructionARM::GetFramePointerRegisterNumber () const
292 if (m_opcode_mode == eModeThumb)
294 switch (m_arch.GetTriple().getOS())
296 case llvm::Triple::Darwin:
297 case llvm::Triple::MacOSX:
298 case llvm::Triple::IOS:
308 EmulateInstructionARM::GetFramePointerDWARFRegisterNumber () const
310 if (m_opcode_mode == eModeThumb)
312 switch (m_arch.GetTriple().getOS())
314 case llvm::Triple::Darwin:
315 case llvm::Triple::MacOSX:
316 case llvm::Triple::IOS:
325 // Push Multiple Registers stores multiple registers to the stack, storing to
326 // consecutive memory locations ending just below the address in SP, and updates
327 // SP to point to the start of the stored data.
329 EmulateInstructionARM::EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding)
332 // ARM pseudo code...
333 if (ConditionPassed())
335 EncodingSpecificOperations();
336 NullCheckIfThumbEE(13);
337 address = SP - 4*BitCount(registers);
341 if (registers<i> == '1')
343 if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1
344 MemA[address,4] = bits(32) UNKNOWN;
346 MemA[address,4] = R[i];
347 address = address + 4;
351 if (registers<15> == '1') // Only possible for encoding A1 or A2
352 MemA[address,4] = PCStoreValue();
354 SP = SP - 4*BitCount(registers);
358 bool conditional = false;
359 bool success = false;
360 if (ConditionPassed(opcode, &conditional))
362 const uint32_t addr_byte_size = GetAddressByteSize();
363 const addr_t sp = ReadCoreReg (SP_REG, &success);
366 uint32_t registers = 0;
367 uint32_t Rt; // the source register
370 registers = Bits32(opcode, 7, 0);
371 // The M bit represents LR.
372 if (Bit32(opcode, 8))
373 registers |= (1u << 14);
374 // if BitCount(registers) < 1 then UNPREDICTABLE;
375 if (BitCount(registers) < 1)
379 // Ignore bits 15 & 13.
380 registers = Bits32(opcode, 15, 0) & ~0xa000;
381 // if BitCount(registers) < 2 then UNPREDICTABLE;
382 if (BitCount(registers) < 2)
386 Rt = Bits32(opcode, 15, 12);
387 // if BadReg(t) then UNPREDICTABLE;
390 registers = (1u << Rt);
393 registers = Bits32(opcode, 15, 0);
394 // Instead of return false, let's handle the following case as well,
395 // which amounts to pushing one reg onto the full descending stacks.
396 // if BitCount(register_list) < 2 then SEE STMDB / STMFD;
399 Rt = Bits32(opcode, 15, 12);
400 // if t == 13 then UNPREDICTABLE;
403 registers = (1u << Rt);
408 addr_t sp_offset = addr_byte_size * BitCount (registers);
409 addr_t addr = sp - sp_offset;
412 EmulateInstruction::Context context;
414 context.type = EmulateInstruction::eContextRegisterStore;
416 context.type = EmulateInstruction::eContextPushRegisterOnStack;
417 RegisterInfo reg_info;
419 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
422 if (BitIsSet (registers, i))
424 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, reg_info);
425 context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
426 uint32_t reg_value = ReadCoreReg(i, &success);
429 if (!MemAWrite (context, addr, reg_value, addr_byte_size))
431 addr += addr_byte_size;
435 if (BitIsSet (registers, 15))
437 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, reg_info);
438 context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
439 const uint32_t pc = ReadCoreReg(PC_REG, &success);
442 if (!MemAWrite (context, addr, pc, addr_byte_size))
446 context.type = EmulateInstruction::eContextAdjustStackPointer;
447 context.SetImmediateSigned (-sp_offset);
449 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
455 // Pop Multiple Registers loads multiple registers from the stack, loading from
456 // consecutive memory locations staring at the address in SP, and updates
457 // SP to point just above the loaded data.
459 EmulateInstructionARM::EmulatePOP (const uint32_t opcode, const ARMEncoding encoding)
462 // ARM pseudo code...
463 if (ConditionPassed())
465 EncodingSpecificOperations(); NullCheckIfThumbEE(13);
468 if registers<i> == '1' then
469 R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
470 if registers<15> == '1' then
471 if UnalignedAllowed then
472 LoadWritePC(MemU[address,4]);
474 LoadWritePC(MemA[address,4]);
475 if registers<13> == '0' then SP = SP + 4*BitCount(registers);
476 if registers<13> == '1' then SP = bits(32) UNKNOWN;
480 bool success = false;
482 bool conditional = false;
483 if (ConditionPassed(opcode, &conditional))
485 const uint32_t addr_byte_size = GetAddressByteSize();
486 const addr_t sp = ReadCoreReg (SP_REG, &success);
489 uint32_t registers = 0;
490 uint32_t Rt; // the destination register
493 registers = Bits32(opcode, 7, 0);
494 // The P bit represents PC.
495 if (Bit32(opcode, 8))
496 registers |= (1u << 15);
497 // if BitCount(registers) < 1 then UNPREDICTABLE;
498 if (BitCount(registers) < 1)
503 registers = Bits32(opcode, 15, 0) & ~0x2000;
504 // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
505 if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14)))
507 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
508 if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
512 Rt = Bits32(opcode, 15, 12);
513 // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
516 if (Rt == 15 && InITBlock() && !LastInITBlock())
518 registers = (1u << Rt);
521 registers = Bits32(opcode, 15, 0);
522 // Instead of return false, let's handle the following case as well,
523 // which amounts to popping one reg from the full descending stacks.
524 // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD;
526 // if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE;
527 if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7)
531 Rt = Bits32(opcode, 15, 12);
532 // if t == 13 then UNPREDICTABLE;
535 registers = (1u << Rt);
540 addr_t sp_offset = addr_byte_size * BitCount (registers);
544 EmulateInstruction::Context context;
546 context.type = EmulateInstruction::eContextRegisterLoad;
548 context.type = EmulateInstruction::eContextPopRegisterOffStack;
551 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
555 if (BitIsSet (registers, i))
557 context.SetRegisterPlusOffset (sp_reg, addr - sp);
558 data = MemARead(context, addr, 4, 0, &success);
561 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i, data))
563 addr += addr_byte_size;
567 if (BitIsSet (registers, 15))
569 context.SetRegisterPlusOffset (sp_reg, addr - sp);
570 data = MemARead(context, addr, 4, 0, &success);
573 // In ARMv5T and above, this is an interworking branch.
574 if (!LoadWritePC(context, data))
576 //addr += addr_byte_size;
579 context.type = EmulateInstruction::eContextAdjustStackPointer;
580 context.SetImmediateSigned (sp_offset);
582 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
588 // Set r7 or ip to point to saved value residing within the stack.
589 // ADD (SP plus immediate)
591 EmulateInstructionARM::EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding)
594 // ARM pseudo code...
595 if (ConditionPassed())
597 EncodingSpecificOperations();
598 (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
600 ALUWritePC(result); // setflags is always FALSE here
605 APSR.Z = IsZeroBit(result);
611 bool success = false;
613 if (ConditionPassed(opcode))
615 const addr_t sp = ReadCoreReg (SP_REG, &success);
618 uint32_t Rd; // the destination register
623 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
626 Rd = Bits32(opcode, 15, 12);
627 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
632 addr_t sp_offset = imm32;
633 addr_t addr = sp + sp_offset; // a pointer to the stack area
635 EmulateInstruction::Context context;
636 context.type = eContextSetFramePointer;
638 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
639 context.SetRegisterPlusOffset (sp_reg, sp_offset);
641 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr))
647 // Set r7 or ip to the current stack pointer.
650 EmulateInstructionARM::EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding)
653 // ARM pseudo code...
654 if (ConditionPassed())
656 EncodingSpecificOperations();
659 ALUWritePC(result); // setflags is always FALSE here
664 APSR.Z = IsZeroBit(result);
670 bool success = false;
672 if (ConditionPassed(opcode))
674 const addr_t sp = ReadCoreReg (SP_REG, &success);
677 uint32_t Rd; // the destination register
689 EmulateInstruction::Context context;
690 if (Rd == GetFramePointerRegisterNumber())
691 context.type = EmulateInstruction::eContextSetFramePointer;
693 context.type = EmulateInstruction::eContextRegisterPlusOffset;
695 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
696 context.SetRegisterPlusOffset (sp_reg, 0);
698 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
704 // Move from high register (r8-r15) to low register (r0-r7).
707 EmulateInstructionARM::EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding)
709 return EmulateMOVRdRm (opcode, encoding);
712 // Move from register to register.
715 EmulateInstructionARM::EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding)
718 // ARM pseudo code...
719 if (ConditionPassed())
721 EncodingSpecificOperations();
724 ALUWritePC(result); // setflags is always FALSE here
729 APSR.Z = IsZeroBit(result);
735 bool success = false;
737 if (ConditionPassed(opcode))
739 uint32_t Rm; // the source register
740 uint32_t Rd; // the destination register
744 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
745 Rm = Bits32(opcode, 6, 3);
747 if (Rd == 15 && InITBlock() && !LastInITBlock())
751 Rd = Bits32(opcode, 2, 0);
752 Rm = Bits32(opcode, 5, 3);
758 Rd = Bits32(opcode, 11, 8);
759 Rm = Bits32(opcode, 3, 0);
760 setflags = BitIsSet(opcode, 20);
761 // if setflags && (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
762 if (setflags && (BadReg(Rd) || BadReg(Rm)))
764 // if !setflags && (d == 15 || m == 15 || (d == 13 && m == 13)) then UNPREDICTABLE;
765 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
769 Rd = Bits32(opcode, 15, 12);
770 Rm = Bits32(opcode, 3, 0);
771 setflags = BitIsSet(opcode, 20);
773 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
774 if (Rd == 15 && setflags)
775 return EmulateSUBSPcLrEtc (opcode, encoding);
780 uint32_t result = ReadCoreReg(Rm, &success);
784 // The context specifies that Rm is to be moved into Rd.
785 EmulateInstruction::Context context;
786 context.type = EmulateInstruction::eContextRegisterLoad;
787 RegisterInfo dwarf_reg;
788 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
789 context.SetRegister (dwarf_reg);
791 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
797 // Move (immediate) writes an immediate value to the destination register. It
798 // can optionally update the condition flags based on the value.
801 EmulateInstructionARM::EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding)
804 // ARM pseudo code...
805 if (ConditionPassed())
807 EncodingSpecificOperations();
809 if d == 15 then // Can only occur for ARM encoding
810 ALUWritePC(result); // setflags is always FALSE here
815 APSR.Z = IsZeroBit(result);
821 if (ConditionPassed(opcode))
823 uint32_t Rd; // the destination register
824 uint32_t imm32; // the immediate value to be written to Rd
825 uint32_t carry = 0; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C.
826 // for setflags == false, this value is a don't care
827 // initialized to 0 to silence the static analyzer
831 Rd = Bits32(opcode, 10, 8);
832 setflags = !InITBlock();
833 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
839 Rd = Bits32(opcode, 11, 8);
840 setflags = BitIsSet(opcode, 20);
841 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
849 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8, 32);
850 Rd = Bits32 (opcode, 11, 8);
852 uint32_t imm4 = Bits32 (opcode, 19, 16);
853 uint32_t imm3 = Bits32 (opcode, 14, 12);
854 uint32_t i = Bit32 (opcode, 26);
855 uint32_t imm8 = Bits32 (opcode, 7, 0);
856 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
858 // if BadReg(d) then UNPREDICTABLE;
865 // d = UInt(Rd); setflags = (S == Ô1Õ); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C);
866 Rd = Bits32 (opcode, 15, 12);
867 setflags = BitIsSet (opcode, 20);
868 imm32 = ARMExpandImm_C (opcode, APSR_C, carry);
870 // if Rd == Ô1111Õ && S == Ô1Õ then SEE SUBS PC, LR and related instructions;
871 if ((Rd == 15) && setflags)
872 return EmulateSUBSPcLrEtc (opcode, encoding);
878 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
879 Rd = Bits32 (opcode, 15, 12);
881 uint32_t imm4 = Bits32 (opcode, 19, 16);
882 uint32_t imm12 = Bits32 (opcode, 11, 0);
883 imm32 = (imm4 << 12) | imm12;
885 // if d == 15 then UNPREDICTABLE;
894 uint32_t result = imm32;
896 // The context specifies that an immediate is to be moved into Rd.
897 EmulateInstruction::Context context;
898 context.type = EmulateInstruction::eContextImmediate;
899 context.SetNoArgs ();
901 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
907 // MUL multiplies two register values. The least significant 32 bits of the result are written to the destination
908 // register. These 32 bits do not depend on whether the source register values are considered to be signed values or
911 // Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is
912 // limited to only a few forms of the instruction.
914 EmulateInstructionARM::EmulateMUL (const uint32_t opcode, const ARMEncoding encoding)
917 if ConditionPassed() then
918 EncodingSpecificOperations();
919 operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
920 operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
921 result = operand1 * operand2;
925 APSR.Z = IsZeroBit(result);
926 if ArchVersion() == 4 then
927 APSR.C = bit UNKNOWN;
928 // else APSR.C unchanged
929 // APSR.V always unchanged
932 if (ConditionPassed(opcode))
939 // EncodingSpecificOperations();
943 // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
944 d = Bits32 (opcode, 2, 0);
945 n = Bits32 (opcode, 5, 3);
946 m = Bits32 (opcode, 2, 0);
947 setflags = !InITBlock();
949 // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
950 if ((ArchVersion() < ARMv6) && (d == n))
956 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
957 d = Bits32 (opcode, 11, 8);
958 n = Bits32 (opcode, 19, 16);
959 m = Bits32 (opcode, 3, 0);
962 // if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;
963 if (BadReg (d) || BadReg (n) || BadReg (m))
969 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
970 d = Bits32 (opcode, 19, 16);
971 n = Bits32 (opcode, 3, 0);
972 m = Bits32 (opcode, 11, 8);
973 setflags = BitIsSet (opcode, 20);
975 // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
976 if ((d == 15) || (n == 15) || (m == 15))
979 // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
980 if ((ArchVersion() < ARMv6) && (d == n))
989 bool success = false;
991 // operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
992 uint64_t operand1 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
996 // operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
997 uint64_t operand2 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
1001 // result = operand1 * operand2;
1002 uint64_t result = operand1 * operand2;
1004 // R[d] = result<31:0>;
1005 RegisterInfo op1_reg;
1006 RegisterInfo op2_reg;
1007 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, op1_reg);
1008 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, op2_reg);
1010 EmulateInstruction::Context context;
1011 context.type = eContextArithmetic;
1012 context.SetRegisterRegisterOperands (op1_reg, op2_reg);
1014 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (0x0000ffff & result)))
1020 // APSR.N = result<31>;
1021 // APSR.Z = IsZeroBit(result);
1022 m_new_inst_cpsr = m_opcode_cpsr;
1023 SetBit32 (m_new_inst_cpsr, CPSR_N_POS, Bit32 (result, 31));
1024 SetBit32 (m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
1025 if (m_new_inst_cpsr != m_opcode_cpsr)
1027 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
1031 // if ArchVersion() == 4 then
1032 // APSR.C = bit UNKNOWN;
1038 // Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register.
1039 // It can optionally update the condition flags based on the value.
1041 EmulateInstructionARM::EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding)
1044 // ARM pseudo code...
1045 if (ConditionPassed())
1047 EncodingSpecificOperations();
1048 result = NOT(imm32);
1049 if d == 15 then // Can only occur for ARM encoding
1050 ALUWritePC(result); // setflags is always FALSE here
1054 APSR.N = result<31>;
1055 APSR.Z = IsZeroBit(result);
1061 if (ConditionPassed(opcode))
1063 uint32_t Rd; // the destination register
1064 uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C
1065 uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C
1069 Rd = Bits32(opcode, 11, 8);
1070 setflags = BitIsSet(opcode, 20);
1071 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1074 Rd = Bits32(opcode, 15, 12);
1075 setflags = BitIsSet(opcode, 20);
1076 imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1078 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1079 if (Rd == 15 && setflags)
1080 return EmulateSUBSPcLrEtc (opcode, encoding);
1085 uint32_t result = ~imm32;
1087 // The context specifies that an immediate is to be moved into Rd.
1088 EmulateInstruction::Context context;
1089 context.type = EmulateInstruction::eContextImmediate;
1090 context.SetNoArgs ();
1092 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1098 // Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register.
1099 // It can optionally update the condition flags based on the result.
1101 EmulateInstructionARM::EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding)
1104 // ARM pseudo code...
1105 if (ConditionPassed())
1107 EncodingSpecificOperations();
1108 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
1109 result = NOT(shifted);
1110 if d == 15 then // Can only occur for ARM encoding
1111 ALUWritePC(result); // setflags is always FALSE here
1115 APSR.N = result<31>;
1116 APSR.Z = IsZeroBit(result);
1122 if (ConditionPassed(opcode))
1124 uint32_t Rm; // the source register
1125 uint32_t Rd; // the destination register
1126 ARM_ShifterType shift_t;
1127 uint32_t shift_n; // the shift applied to the value read from Rm
1129 uint32_t carry; // the carry bit after the shift operation
1132 Rd = Bits32(opcode, 2, 0);
1133 Rm = Bits32(opcode, 5, 3);
1134 setflags = !InITBlock();
1135 shift_t = SRType_LSL;
1141 Rd = Bits32(opcode, 11, 8);
1142 Rm = Bits32(opcode, 3, 0);
1143 setflags = BitIsSet(opcode, 20);
1144 shift_n = DecodeImmShiftThumb(opcode, shift_t);
1145 // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
1146 if (BadReg(Rd) || BadReg(Rm))
1150 Rd = Bits32(opcode, 15, 12);
1151 Rm = Bits32(opcode, 3, 0);
1152 setflags = BitIsSet(opcode, 20);
1153 shift_n = DecodeImmShiftARM(opcode, shift_t);
1158 bool success = false;
1159 uint32_t value = ReadCoreReg(Rm, &success);
1163 uint32_t shifted = Shift_C(value, shift_t, shift_n, APSR_C, carry, &success);
1166 uint32_t result = ~shifted;
1168 // The context specifies that an immediate is to be moved into Rd.
1169 EmulateInstruction::Context context;
1170 context.type = EmulateInstruction::eContextImmediate;
1171 context.SetNoArgs ();
1173 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
1179 // PC relative immediate load into register, possibly followed by ADD (SP plus register).
1182 EmulateInstructionARM::EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding)
1185 // ARM pseudo code...
1186 if (ConditionPassed())
1188 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
1190 address = if add then (base + imm32) else (base - imm32);
1191 data = MemU[address,4];
1193 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
1194 elsif UnalignedSupport() || address<1:0> = '00' then
1196 else // Can only apply before ARMv7
1197 if CurrentInstrSet() == InstrSet_ARM then
1198 R[t] = ROR(data, 8*UInt(address<1:0>));
1200 R[t] = bits(32) UNKNOWN;
1204 if (ConditionPassed(opcode))
1206 bool success = false;
1207 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1211 // PC relative immediate load context
1212 EmulateInstruction::Context context;
1213 context.type = EmulateInstruction::eContextRegisterPlusOffset;
1214 RegisterInfo pc_reg;
1215 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
1216 context.SetRegisterPlusOffset (pc_reg, 0);
1218 uint32_t Rt; // the destination register
1219 uint32_t imm32; // immediate offset from the PC
1220 bool add; // +imm32 or -imm32?
1221 addr_t base; // the base address
1222 addr_t address; // the PC relative address
1223 uint32_t data; // the literal data value from the PC relative load
1226 Rt = Bits32(opcode, 10, 8);
1227 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
1231 Rt = Bits32(opcode, 15, 12);
1232 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
1233 add = BitIsSet(opcode, 23);
1234 if (Rt == 15 && InITBlock() && !LastInITBlock())
1241 base = Align(pc, 4);
1243 address = base + imm32;
1245 address = base - imm32;
1247 context.SetRegisterPlusOffset(pc_reg, address - base);
1248 data = MemURead(context, address, 4, 0, &success);
1254 if (Bits32(address, 1, 0) == 0)
1256 // In ARMv5T and above, this is an interworking branch.
1257 if (!LoadWritePC(context, data))
1263 else if (UnalignedSupport() || Bits32(address, 1, 0) == 0)
1265 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data))
1268 else // We don't handle ARM for now.
1275 // An add operation to adjust the SP.
1276 // ADD (SP plus immediate)
1278 EmulateInstructionARM::EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding)
1281 // ARM pseudo code...
1282 if (ConditionPassed())
1284 EncodingSpecificOperations();
1285 (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
1286 if d == 15 then // Can only occur for ARM encoding
1287 ALUWritePC(result); // setflags is always FALSE here
1291 APSR.N = result<31>;
1292 APSR.Z = IsZeroBit(result);
1298 bool success = false;
1300 if (ConditionPassed(opcode))
1302 const addr_t sp = ReadCoreReg (SP_REG, &success);
1305 uint32_t imm32; // the immediate operand
1307 //bool setflags = false; // Add this back if/when support eEncodingT3 eEncodingA1
1311 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
1312 d = Bits32 (opcode, 10, 8);
1313 imm32 = (Bits32 (opcode, 7, 0) << 2);
1318 // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32);
1320 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1327 addr_t sp_offset = imm32;
1328 addr_t addr = sp + sp_offset; // the adjusted stack pointer value
1330 EmulateInstruction::Context context;
1331 context.type = EmulateInstruction::eContextAdjustStackPointer;
1332 RegisterInfo sp_reg;
1333 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
1334 context.SetRegisterPlusOffset (sp_reg, sp_offset);
1338 if (!ALUWritePC (context, addr))
1343 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, addr))
1346 // Add this back if/when support eEncodingT3 eEncodingA1
1349 // APSR.N = result<31>;
1350 // APSR.Z = IsZeroBit(result);
1352 // APSR.V = overflow;
1359 // An add operation to adjust the SP.
1360 // ADD (SP plus register)
1362 EmulateInstructionARM::EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding)
1365 // ARM pseudo code...
1366 if (ConditionPassed())
1368 EncodingSpecificOperations();
1369 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
1370 (result, carry, overflow) = AddWithCarry(SP, shifted, '0');
1372 ALUWritePC(result); // setflags is always FALSE here
1376 APSR.N = result<31>;
1377 APSR.Z = IsZeroBit(result);
1383 bool success = false;
1385 if (ConditionPassed(opcode))
1387 const addr_t sp = ReadCoreReg (SP_REG, &success);
1390 uint32_t Rm; // the second operand
1393 Rm = Bits32(opcode, 6, 3);
1398 int32_t reg_value = ReadCoreReg(Rm, &success);
1402 addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value
1404 EmulateInstruction::Context context;
1405 context.type = eContextArithmetic;
1406 RegisterInfo sp_reg;
1407 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
1409 RegisterInfo other_reg;
1410 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, other_reg);
1411 context.SetRegisterRegisterOperands (sp_reg, other_reg);
1413 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr))
1419 // Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine
1420 // at a PC-relative address, and changes instruction set from ARM to Thumb, or
1421 // from Thumb to ARM.
1424 EmulateInstructionARM::EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding)
1427 // ARM pseudo code...
1428 if (ConditionPassed())
1430 EncodingSpecificOperations();
1431 if CurrentInstrSet() == InstrSet_ARM then
1434 LR = PC<31:1> : '1';
1435 if targetInstrSet == InstrSet_ARM then
1436 targetAddress = Align(PC,4) + imm32;
1438 targetAddress = PC + imm32;
1439 SelectInstrSet(targetInstrSet);
1440 BranchWritePC(targetAddress);
1444 bool success = true;
1446 if (ConditionPassed(opcode))
1448 EmulateInstruction::Context context;
1449 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1450 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1453 addr_t lr; // next instruction address
1454 addr_t target; // target address
1455 int32_t imm32; // PC-relative offset
1459 lr = pc | 1u; // return address
1460 uint32_t S = Bit32(opcode, 26);
1461 uint32_t imm10 = Bits32(opcode, 25, 16);
1462 uint32_t J1 = Bit32(opcode, 13);
1463 uint32_t J2 = Bit32(opcode, 11);
1464 uint32_t imm11 = Bits32(opcode, 10, 0);
1465 uint32_t I1 = !(J1 ^ S);
1466 uint32_t I2 = !(J2 ^ S);
1467 uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
1468 imm32 = llvm::SignExtend32<25>(imm25);
1469 target = pc + imm32;
1470 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
1471 if (InITBlock() && !LastInITBlock())
1477 lr = pc | 1u; // return address
1478 uint32_t S = Bit32(opcode, 26);
1479 uint32_t imm10H = Bits32(opcode, 25, 16);
1480 uint32_t J1 = Bit32(opcode, 13);
1481 uint32_t J2 = Bit32(opcode, 11);
1482 uint32_t imm10L = Bits32(opcode, 10, 1);
1483 uint32_t I1 = !(J1 ^ S);
1484 uint32_t I2 = !(J2 ^ S);
1485 uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
1486 imm32 = llvm::SignExtend32<25>(imm25);
1487 target = Align(pc, 4) + imm32;
1488 context.SetISAAndImmediateSigned (eModeARM, 4 + imm32);
1489 if (InITBlock() && !LastInITBlock())
1494 lr = pc - 4; // return address
1495 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
1496 target = Align(pc, 4) + imm32;
1497 context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
1500 lr = pc - 4; // return address
1501 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1);
1502 target = pc + imm32;
1503 context.SetISAAndImmediateSigned (eModeThumb, 8 + imm32);
1508 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
1510 if (!BranchWritePC(context, target))
1516 // Branch with Link and Exchange (register) calls a subroutine at an address and
1517 // instruction set specified by a register.
1520 EmulateInstructionARM::EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding)
1523 // ARM pseudo code...
1524 if (ConditionPassed())
1526 EncodingSpecificOperations();
1528 if CurrentInstrSet() == InstrSet_ARM then
1529 next_instr_addr = PC - 4;
1530 LR = next_instr_addr;
1532 next_instr_addr = PC - 2;
1533 LR = next_instr_addr<31:1> : '1';
1538 bool success = false;
1540 if (ConditionPassed(opcode))
1542 EmulateInstruction::Context context;
1543 context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
1544 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1545 addr_t lr; // next instruction address
1548 uint32_t Rm; // the register with the target address
1551 lr = (pc - 2) | 1u; // return address
1552 Rm = Bits32(opcode, 6, 3);
1553 // if m == 15 then UNPREDICTABLE;
1556 if (InITBlock() && !LastInITBlock())
1560 lr = pc - 4; // return address
1561 Rm = Bits32(opcode, 3, 0);
1562 // if m == 15 then UNPREDICTABLE;
1569 addr_t target = ReadCoreReg (Rm, &success);
1572 RegisterInfo dwarf_reg;
1573 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1574 context.SetRegister (dwarf_reg);
1575 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
1577 if (!BXWritePC(context, target))
1583 // Branch and Exchange causes a branch to an address and instruction set specified by a register.
1585 EmulateInstructionARM::EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding)
1588 // ARM pseudo code...
1589 if (ConditionPassed())
1591 EncodingSpecificOperations();
1596 if (ConditionPassed(opcode))
1598 EmulateInstruction::Context context;
1599 context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
1600 uint32_t Rm; // the register with the target address
1603 Rm = Bits32(opcode, 6, 3);
1604 if (InITBlock() && !LastInITBlock())
1608 Rm = Bits32(opcode, 3, 0);
1613 bool success = false;
1614 addr_t target = ReadCoreReg (Rm, &success);
1618 RegisterInfo dwarf_reg;
1619 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1620 context.SetRegister (dwarf_reg);
1621 if (!BXWritePC(context, target))
1627 // Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an
1628 // address and instruction set specified by a register as though it were a BX instruction.
1630 // TODO: Emulate Jazelle architecture?
1631 // We currently assume that switching to Jazelle state fails, thus treating BXJ as a BX operation.
1633 EmulateInstructionARM::EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding)
1636 // ARM pseudo code...
1637 if (ConditionPassed())
1639 EncodingSpecificOperations();
1640 if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then
1643 if JazelleAcceptsExecution() then
1644 SwitchToJazelleExecution();
1646 SUBARCHITECTURE_DEFINED handler call;
1650 if (ConditionPassed(opcode))
1652 EmulateInstruction::Context context;
1653 context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
1654 uint32_t Rm; // the register with the target address
1657 Rm = Bits32(opcode, 19, 16);
1660 if (InITBlock() && !LastInITBlock())
1664 Rm = Bits32(opcode, 3, 0);
1671 bool success = false;
1672 addr_t target = ReadCoreReg (Rm, &success);
1676 RegisterInfo dwarf_reg;
1677 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
1678 context.SetRegister (dwarf_reg);
1679 if (!BXWritePC(context, target))
1685 // Set r7 to point to some ip offset.
1688 EmulateInstructionARM::EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding)
1691 // ARM pseudo code...
1692 if (ConditionPassed())
1694 EncodingSpecificOperations();
1695 (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
1696 if d == 15 then // Can only occur for ARM encoding
1697 ALUWritePC(result); // setflags is always FALSE here
1701 APSR.N = result<31>;
1702 APSR.Z = IsZeroBit(result);
1708 if (ConditionPassed(opcode))
1710 bool success = false;
1711 const addr_t ip = ReadCoreReg (12, &success);
1717 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1722 addr_t ip_offset = imm32;
1723 addr_t addr = ip - ip_offset; // the adjusted ip value
1725 EmulateInstruction::Context context;
1726 context.type = EmulateInstruction::eContextRegisterPlusOffset;
1727 RegisterInfo dwarf_reg;
1728 GetRegisterInfo (eRegisterKindDWARF, dwarf_r12, dwarf_reg);
1729 context.SetRegisterPlusOffset (dwarf_reg, -ip_offset);
1731 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr))
1737 // Set ip to point to some stack offset.
1738 // SUB (SP minus immediate)
1740 EmulateInstructionARM::EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding)
1743 // ARM pseudo code...
1744 if (ConditionPassed())
1746 EncodingSpecificOperations();
1747 (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
1748 if d == 15 then // Can only occur for ARM encoding
1749 ALUWritePC(result); // setflags is always FALSE here
1753 APSR.N = result<31>;
1754 APSR.Z = IsZeroBit(result);
1760 if (ConditionPassed(opcode))
1762 bool success = false;
1763 const addr_t sp = ReadCoreReg (SP_REG, &success);
1769 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1774 addr_t sp_offset = imm32;
1775 addr_t addr = sp - sp_offset; // the adjusted stack pointer value
1777 EmulateInstruction::Context context;
1778 context.type = EmulateInstruction::eContextRegisterPlusOffset;
1779 RegisterInfo dwarf_reg;
1780 GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, dwarf_reg);
1781 context.SetRegisterPlusOffset (dwarf_reg, -sp_offset);
1783 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr))
1789 // This instruction subtracts an immediate value from the SP value, and writes
1790 // the result to the destination register.
1792 // If Rd == 13 => A sub operation to adjust the SP -- allocate space for local storage.
1794 EmulateInstructionARM::EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding)
1797 // ARM pseudo code...
1798 if (ConditionPassed())
1800 EncodingSpecificOperations();
1801 (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
1802 if d == 15 then // Can only occur for ARM encoding
1803 ALUWritePC(result); // setflags is always FALSE here
1807 APSR.N = result<31>;
1808 APSR.Z = IsZeroBit(result);
1814 bool success = false;
1815 if (ConditionPassed(opcode))
1817 const addr_t sp = ReadCoreReg (SP_REG, &success);
1828 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1831 Rd = Bits32(opcode, 11, 8);
1832 setflags = BitIsSet(opcode, 20);
1833 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
1834 if (Rd == 15 && setflags)
1835 return EmulateCMPImm(opcode, eEncodingT2);
1836 if (Rd == 15 && !setflags)
1840 Rd = Bits32(opcode, 11, 8);
1842 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
1847 Rd = Bits32(opcode, 15, 12);
1848 setflags = BitIsSet(opcode, 20);
1849 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1851 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
1852 if (Rd == 15 && setflags)
1853 return EmulateSUBSPcLrEtc (opcode, encoding);
1858 AddWithCarryResult res = AddWithCarry(sp, ~imm32, 1);
1860 EmulateInstruction::Context context;
1863 uint64_t imm64 = imm32; // Need to expand it to 64 bits before attempting to negate it, or the wrong
1864 // value gets passed down to context.SetImmediateSigned.
1865 context.type = EmulateInstruction::eContextAdjustStackPointer;
1866 context.SetImmediateSigned (-imm64); // the stack pointer offset
1870 context.type = EmulateInstruction::eContextImmediate;
1871 context.SetNoArgs ();
1874 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
1880 // A store operation to the stack that also updates the SP.
1882 EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding)
1885 // ARM pseudo code...
1886 if (ConditionPassed())
1888 EncodingSpecificOperations();
1889 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
1890 address = if index then offset_addr else R[n];
1891 MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
1892 if wback then R[n] = offset_addr;
1896 bool conditional = false;
1897 bool success = false;
1898 if (ConditionPassed(opcode, &conditional))
1900 const uint32_t addr_byte_size = GetAddressByteSize();
1901 const addr_t sp = ReadCoreReg (SP_REG, &success);
1904 uint32_t Rt; // the source register
1906 uint32_t Rn; // This function assumes Rn is the SP, but we should verify that.
1913 Rt = Bits32(opcode, 15, 12);
1914 imm12 = Bits32(opcode, 11, 0);
1915 Rn = Bits32 (opcode, 19, 16);
1917 if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP.
1920 index = BitIsSet (opcode, 24);
1921 add = BitIsSet (opcode, 23);
1922 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
1924 if (wback && ((Rn == 15) || (Rn == Rt)))
1932 offset_addr = sp + imm12;
1934 offset_addr = sp - imm12;
1942 EmulateInstruction::Context context;
1944 context.type = EmulateInstruction::eContextRegisterStore;
1946 context.type = EmulateInstruction::eContextPushRegisterOnStack;
1947 RegisterInfo sp_reg;
1948 RegisterInfo dwarf_reg;
1950 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
1951 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rt, dwarf_reg);
1952 context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp);
1955 uint32_t reg_value = ReadCoreReg(Rt, &success);
1958 if (!MemUWrite (context, addr, reg_value, addr_byte_size))
1963 const uint32_t pc = ReadCoreReg(PC_REG, &success);
1966 if (!MemUWrite (context, addr, pc, addr_byte_size))
1973 context.type = EmulateInstruction::eContextAdjustStackPointer;
1974 context.SetImmediateSigned (addr - sp);
1975 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, offset_addr))
1982 // Vector Push stores multiple extension registers to the stack.
1983 // It also updates SP to point to the start of the stored data.
1985 EmulateInstructionARM::EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding)
1988 // ARM pseudo code...
1989 if (ConditionPassed())
1991 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
1992 address = SP - imm32;
1996 MemA[address,4] = S[d+r]; address = address+4;
1999 // Store as two word-aligned words in the correct order for current endianness.
2000 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
2001 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
2002 address = address+8;
2006 bool success = false;
2007 bool conditional = false;
2008 if (ConditionPassed(opcode, &conditional))
2010 const uint32_t addr_byte_size = GetAddressByteSize();
2011 const addr_t sp = ReadCoreReg (SP_REG, &success);
2015 uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register
2016 uint32_t imm32; // stack offset
2017 uint32_t regs; // number of registers
2021 single_regs = false;
2022 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2023 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2024 // If UInt(imm8) is odd, see "FSTMX".
2025 regs = Bits32(opcode, 7, 0) / 2;
2026 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2027 if (regs == 0 || regs > 16 || (d + regs) > 32)
2033 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2034 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2035 regs = Bits32(opcode, 7, 0);
2036 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2037 if (regs == 0 || regs > 16 || (d + regs) > 32)
2043 uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
2044 uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2045 addr_t sp_offset = imm32;
2046 addr_t addr = sp - sp_offset;
2049 EmulateInstruction::Context context;
2051 context.type = EmulateInstruction::eContextRegisterStore;
2053 context.type = EmulateInstruction::eContextPushRegisterOnStack;
2054 RegisterInfo dwarf_reg;
2055 RegisterInfo sp_reg;
2056 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
2057 for (i=0; i<regs; ++i)
2059 GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
2060 context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp);
2061 // uint64_t to accommodate 64-bit registers.
2062 uint64_t reg_value = ReadRegisterUnsigned (&dwarf_reg, 0, &success);
2065 if (!MemAWrite (context, addr, reg_value, reg_byte_size))
2067 addr += reg_byte_size;
2070 context.type = EmulateInstruction::eContextAdjustStackPointer;
2071 context.SetImmediateSigned (-sp_offset);
2073 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
2079 // Vector Pop loads multiple extension registers from the stack.
2080 // It also updates SP to point just above the loaded data.
2082 EmulateInstructionARM::EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding)
2085 // ARM pseudo code...
2086 if (ConditionPassed())
2088 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
2093 S[d+r] = MemA[address,4]; address = address+4;
2096 word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
2097 // Combine the word-aligned words in the correct order for current endianness.
2098 D[d+r] = if BigEndian() then word1:word2 else word2:word1;
2102 bool success = false;
2103 bool conditional = false;
2104 if (ConditionPassed(opcode, &conditional))
2106 const uint32_t addr_byte_size = GetAddressByteSize();
2107 const addr_t sp = ReadCoreReg (SP_REG, &success);
2111 uint32_t d; // UInt(D:Vd) or UInt(Vd:D) starting register
2112 uint32_t imm32; // stack offset
2113 uint32_t regs; // number of registers
2117 single_regs = false;
2118 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2119 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2120 // If UInt(imm8) is odd, see "FLDMX".
2121 regs = Bits32(opcode, 7, 0) / 2;
2122 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2123 if (regs == 0 || regs > 16 || (d + regs) > 32)
2129 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2130 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2131 regs = Bits32(opcode, 7, 0);
2132 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2133 if (regs == 0 || regs > 16 || (d + regs) > 32)
2139 uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
2140 uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
2141 addr_t sp_offset = imm32;
2144 uint64_t data; // uint64_t to accomodate 64-bit registers.
2146 EmulateInstruction::Context context;
2148 context.type = EmulateInstruction::eContextRegisterLoad;
2150 context.type = EmulateInstruction::eContextPopRegisterOffStack;
2151 RegisterInfo dwarf_reg;
2152 RegisterInfo sp_reg;
2153 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
2154 for (i=0; i<regs; ++i)
2156 GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
2157 context.SetRegisterPlusOffset (sp_reg, addr - sp);
2158 data = MemARead(context, addr, reg_byte_size, 0, &success);
2161 if (!WriteRegisterUnsigned(context, &dwarf_reg, data))
2163 addr += reg_byte_size;
2166 context.type = EmulateInstruction::eContextAdjustStackPointer;
2167 context.SetImmediateSigned (sp_offset);
2169 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
2175 // SVC (previously SWI)
2177 EmulateInstructionARM::EmulateSVC (const uint32_t opcode, const ARMEncoding encoding)
2180 // ARM pseudo code...
2181 if (ConditionPassed())
2183 EncodingSpecificOperations();
2188 bool success = false;
2190 if (ConditionPassed(opcode))
2192 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2193 addr_t lr; // next instruction address
2196 uint32_t imm32; // the immediate constant
2197 uint32_t mode; // ARM or Thumb mode
2200 lr = (pc + 2) | 1u; // return address
2201 imm32 = Bits32(opcode, 7, 0);
2205 lr = pc + 4; // return address
2206 imm32 = Bits32(opcode, 23, 0);
2213 EmulateInstruction::Context context;
2214 context.type = EmulateInstruction::eContextSupervisorCall;
2215 context.SetISAAndImmediate (mode, imm32);
2216 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
2222 // If Then makes up to four following instructions (the IT block) conditional.
2224 EmulateInstructionARM::EmulateIT (const uint32_t opcode, const ARMEncoding encoding)
2227 // ARM pseudo code...
2228 EncodingSpecificOperations();
2229 ITSTATE.IT<7:0> = firstcond:mask;
2232 m_it_session.InitIT(Bits32(opcode, 7, 0));
2237 EmulateInstructionARM::EmulateNop (const uint32_t opcode, const ARMEncoding encoding)
2239 // NOP, nothing to do...
2243 // Branch causes a branch to a target address.
2245 EmulateInstructionARM::EmulateB (const uint32_t opcode, const ARMEncoding encoding)
2248 // ARM pseudo code...
2249 if (ConditionPassed())
2251 EncodingSpecificOperations();
2252 BranchWritePC(PC + imm32);
2256 bool success = false;
2258 if (ConditionPassed(opcode))
2260 EmulateInstruction::Context context;
2261 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2262 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2265 addr_t target; // target address
2266 int32_t imm32; // PC-relative offset
2269 // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2270 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
2271 target = pc + imm32;
2272 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2275 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0));
2276 target = pc + imm32;
2277 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2280 // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2282 uint32_t S = Bit32(opcode, 26);
2283 uint32_t imm6 = Bits32(opcode, 21, 16);
2284 uint32_t J1 = Bit32(opcode, 13);
2285 uint32_t J2 = Bit32(opcode, 11);
2286 uint32_t imm11 = Bits32(opcode, 10, 0);
2287 uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
2288 imm32 = llvm::SignExtend32<21>(imm21);
2289 target = pc + imm32;
2290 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2295 uint32_t S = Bit32(opcode, 26);
2296 uint32_t imm10 = Bits32(opcode, 25, 16);
2297 uint32_t J1 = Bit32(opcode, 13);
2298 uint32_t J2 = Bit32(opcode, 11);
2299 uint32_t imm11 = Bits32(opcode, 10, 0);
2300 uint32_t I1 = !(J1 ^ S);
2301 uint32_t I2 = !(J2 ^ S);
2302 uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
2303 imm32 = llvm::SignExtend32<25>(imm25);
2304 target = pc + imm32;
2305 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2309 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2310 target = pc + imm32;
2311 context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
2316 if (!BranchWritePC(context, target))
2322 // Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with
2323 // zero and conditionally branch forward a constant value. They do not affect the condition flags.
2326 EmulateInstructionARM::EmulateCB (const uint32_t opcode, const ARMEncoding encoding)
2329 // ARM pseudo code...
2330 EncodingSpecificOperations();
2331 if nonzero ^ IsZero(R[n]) then
2332 BranchWritePC(PC + imm32);
2335 bool success = false;
2337 // Read the register value from the operand register Rn.
2338 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success);
2342 EmulateInstruction::Context context;
2343 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2344 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2348 addr_t target; // target address
2349 uint32_t imm32; // PC-relative offset to branch forward
2353 imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
2354 nonzero = BitIsSet(opcode, 11);
2355 target = pc + imm32;
2356 context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
2361 if (nonzero ^ (reg_val == 0))
2362 if (!BranchWritePC(context, target))
2368 // Table Branch Byte causes a PC-relative forward branch using a table of single byte offsets.
2369 // A base register provides a pointer to the table, and a second register supplies an index into the table.
2370 // The branch length is twice the value of the byte returned from the table.
2372 // Table Branch Halfword causes a PC-relative forward branch using a table of single halfword offsets.
2373 // A base register provides a pointer to the table, and a second register supplies an index into the table.
2374 // The branch length is twice the value of the halfword returned from the table.
2377 EmulateInstructionARM::EmulateTB (const uint32_t opcode, const ARMEncoding encoding)
2380 // ARM pseudo code...
2381 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
2383 halfwords = UInt(MemU[R[n]+LSL(R[m],1), 2]);
2385 halfwords = UInt(MemU[R[n]+R[m], 1]);
2386 BranchWritePC(PC + 2*halfwords);
2389 bool success = false;
2391 uint32_t Rn; // the base register which contains the address of the table of branch lengths
2392 uint32_t Rm; // the index register which contains an integer pointing to a byte/halfword in the table
2393 bool is_tbh; // true if table branch halfword
2396 Rn = Bits32(opcode, 19, 16);
2397 Rm = Bits32(opcode, 3, 0);
2398 is_tbh = BitIsSet(opcode, 4);
2399 if (Rn == 13 || BadReg(Rm))
2401 if (InITBlock() && !LastInITBlock())
2408 // Read the address of the table from the operand register Rn.
2409 // The PC can be used, in which case the table immediately follows this instruction.
2410 uint32_t base = ReadCoreReg(Rm, &success);
2415 uint32_t index = ReadCoreReg(Rm, &success);
2419 // the offsetted table address
2420 addr_t addr = base + (is_tbh ? index*2 : index);
2422 // PC-relative offset to branch forward
2423 EmulateInstruction::Context context;
2424 context.type = EmulateInstruction::eContextTableBranchReadMemory;
2425 uint32_t offset = MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
2429 const uint32_t pc = ReadCoreReg(PC_REG, &success);
2434 addr_t target = pc + offset;
2435 context.type = EmulateInstruction::eContextRelativeBranchImmediate;
2436 context.SetISAAndImmediateSigned (eModeThumb, 4 + offset);
2438 if (!BranchWritePC(context, target))
2444 // This instruction adds an immediate value to a register value, and writes the result to the destination register.
2445 // It can optionally update the condition flags based on the result.
2447 EmulateInstructionARM::EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding)
2450 if ConditionPassed() then
2451 EncodingSpecificOperations();
2452 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
2455 APSR.N = result<31>;
2456 APSR.Z = IsZeroBit(result);
2461 bool success = false;
2463 if (ConditionPassed(opcode))
2471 //EncodingSpecificOperations();
2475 // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 = ZeroExtend(imm3, 32);
2476 d = Bits32 (opcode, 2, 0);
2477 n = Bits32 (opcode, 5, 3);
2478 setflags = !InITBlock();
2479 imm32 = Bits32 (opcode, 8,6);
2484 // d = UInt(Rdn); n = UInt(Rdn); setflags = !InITBlock(); imm32 = ZeroExtend(imm8, 32);
2485 d = Bits32 (opcode, 10, 8);
2486 n = Bits32 (opcode, 10, 8);
2487 setflags = !InITBlock();
2488 imm32 = Bits32 (opcode, 7, 0);
2493 // if Rd == '1111' && S == '1' then SEE CMN (immediate);
2494 // if Rn == '1101' then SEE ADD (SP plus immediate);
2495 // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = ThumbExpandImm(i:imm3:imm8);
2496 d = Bits32 (opcode, 11, 8);
2497 n = Bits32 (opcode, 19, 16);
2498 setflags = BitIsSet (opcode, 20);
2499 imm32 = ThumbExpandImm_C (opcode, APSR_C, carry_out);
2501 // if BadReg(d) || n == 15 then UNPREDICTABLE;
2502 if (BadReg (d) || (n == 15))
2509 // if Rn == '1111' then SEE ADR;
2510 // if Rn == '1101' then SEE ADD (SP plus immediate);
2511 // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
2512 d = Bits32 (opcode, 11, 8);
2513 n = Bits32 (opcode, 19, 16);
2515 uint32_t i = Bit32 (opcode, 26);
2516 uint32_t imm3 = Bits32 (opcode, 14, 12);
2517 uint32_t imm8 = Bits32 (opcode, 7, 0);
2518 imm32 = (i << 11) | (imm3 << 8) | imm8;
2520 // if BadReg(d) then UNPREDICTABLE;
2530 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
2534 //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
2535 AddWithCarryResult res = AddWithCarry (Rn, imm32, 0);
2538 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
2540 EmulateInstruction::Context context;
2541 context.type = eContextArithmetic;
2542 context.SetRegisterPlusOffset (reg_n, imm32);
2546 //APSR.N = result<31>;
2547 //APSR.Z = IsZeroBit(result);
2549 //APSR.V = overflow;
2550 if (!WriteCoreRegOptionalFlags (context, res.result, d, setflags, res.carry_out, res.overflow))
2557 // This instruction adds an immediate value to a register value, and writes the result to the destination
2558 // register. It can optionally update the condition flags based on the result.
2560 EmulateInstructionARM::EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding)
2563 // ARM pseudo code...
2564 if ConditionPassed() then
2565 EncodingSpecificOperations();
2566 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
2568 ALUWritePC(result); // setflags is always FALSE here
2572 APSR.N = result<31>;
2573 APSR.Z = IsZeroBit(result);
2578 bool success = false;
2580 if (ConditionPassed(opcode))
2583 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
2588 Rd = Bits32(opcode, 15, 12);
2589 Rn = Bits32(opcode, 19, 16);
2590 setflags = BitIsSet(opcode, 20);
2591 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2597 // Read the first operand.
2598 uint32_t val1 = ReadCoreReg(Rn, &success);
2602 AddWithCarryResult res = AddWithCarry(val1, imm32, 0);
2604 EmulateInstruction::Context context;
2605 context.type = eContextArithmetic;
2606 RegisterInfo dwarf_reg;
2607 GetRegisterInfo (eRegisterKindDWARF, Rn, dwarf_reg);
2608 context.SetRegisterPlusOffset (dwarf_reg, imm32);
2610 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
2616 // This instruction adds a register value and an optionally-shifted register value, and writes the result
2617 // to the destination register. It can optionally update the condition flags based on the result.
2619 EmulateInstructionARM::EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding)
2622 // ARM pseudo code...
2623 if ConditionPassed() then
2624 EncodingSpecificOperations();
2625 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
2626 (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
2628 ALUWritePC(result); // setflags is always FALSE here
2632 APSR.N = result<31>;
2633 APSR.Z = IsZeroBit(result);
2638 bool success = false;
2640 if (ConditionPassed(opcode))
2642 uint32_t Rd, Rn, Rm;
2643 ARM_ShifterType shift_t;
2644 uint32_t shift_n; // the shift applied to the value read from Rm
2649 Rd = Bits32(opcode, 2, 0);
2650 Rn = Bits32(opcode, 5, 3);
2651 Rm = Bits32(opcode, 8, 6);
2652 setflags = !InITBlock();
2653 shift_t = SRType_LSL;
2657 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2658 Rm = Bits32(opcode, 6, 3);
2660 shift_t = SRType_LSL;
2662 if (Rn == 15 && Rm == 15)
2664 if (Rd == 15 && InITBlock() && !LastInITBlock())
2668 Rd = Bits32(opcode, 15, 12);
2669 Rn = Bits32(opcode, 19, 16);
2670 Rm = Bits32(opcode, 3, 0);
2671 setflags = BitIsSet(opcode, 20);
2672 shift_n = DecodeImmShiftARM(opcode, shift_t);
2678 // Read the first operand.
2679 uint32_t val1 = ReadCoreReg(Rn, &success);
2683 // Read the second operand.
2684 uint32_t val2 = ReadCoreReg(Rm, &success);
2688 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
2691 AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
2693 EmulateInstruction::Context context;
2694 context.type = eContextArithmetic;
2695 RegisterInfo op1_reg;
2696 RegisterInfo op2_reg;
2697 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, op1_reg);
2698 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, op2_reg);
2699 context.SetRegisterRegisterOperands (op1_reg, op2_reg);
2701 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
2707 // Compare Negative (immediate) adds a register value and an immediate value.
2708 // It updates the condition flags based on the result, and discards the result.
2710 EmulateInstructionARM::EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding)
2713 // ARM pseudo code...
2714 if ConditionPassed() then
2715 EncodingSpecificOperations();
2716 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
2717 APSR.N = result<31>;
2718 APSR.Z = IsZeroBit(result);
2723 bool success = false;
2725 uint32_t Rn; // the first operand
2726 uint32_t imm32; // the immediate value to be compared with
2729 Rn = Bits32(opcode, 19, 16);
2730 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2735 Rn = Bits32(opcode, 19, 16);
2736 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2741 // Read the register value from the operand register Rn.
2742 uint32_t reg_val = ReadCoreReg(Rn, &success);
2746 AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0);
2748 EmulateInstruction::Context context;
2749 context.type = EmulateInstruction::eContextImmediate;
2750 context.SetNoArgs ();
2751 if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
2757 // Compare Negative (register) adds a register value and an optionally-shifted register value.
2758 // It updates the condition flags based on the result, and discards the result.
2760 EmulateInstructionARM::EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding)
2763 // ARM pseudo code...
2764 if ConditionPassed() then
2765 EncodingSpecificOperations();
2766 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
2767 (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
2768 APSR.N = result<31>;
2769 APSR.Z = IsZeroBit(result);
2774 bool success = false;
2776 uint32_t Rn; // the first operand
2777 uint32_t Rm; // the second operand
2778 ARM_ShifterType shift_t;
2779 uint32_t shift_n; // the shift applied to the value read from Rm
2782 Rn = Bits32(opcode, 2, 0);
2783 Rm = Bits32(opcode, 5, 3);
2784 shift_t = SRType_LSL;
2788 Rn = Bits32(opcode, 19, 16);
2789 Rm = Bits32(opcode, 3, 0);
2790 shift_n = DecodeImmShiftThumb(opcode, shift_t);
2791 // if n == 15 || BadReg(m) then UNPREDICTABLE;
2792 if (Rn == 15 || BadReg(Rm))
2796 Rn = Bits32(opcode, 19, 16);
2797 Rm = Bits32(opcode, 3, 0);
2798 shift_n = DecodeImmShiftARM(opcode, shift_t);
2803 // Read the register value from register Rn.
2804 uint32_t val1 = ReadCoreReg(Rn, &success);
2808 // Read the register value from register Rm.
2809 uint32_t val2 = ReadCoreReg(Rm, &success);
2813 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
2816 AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
2818 EmulateInstruction::Context context;
2819 context.type = EmulateInstruction::eContextImmediate;
2820 context.SetNoArgs();
2821 if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
2827 // Compare (immediate) subtracts an immediate value from a register value.
2828 // It updates the condition flags based on the result, and discards the result.
2830 EmulateInstructionARM::EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding)
2833 // ARM pseudo code...
2834 if ConditionPassed() then
2835 EncodingSpecificOperations();
2836 (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
2837 APSR.N = result<31>;
2838 APSR.Z = IsZeroBit(result);
2843 bool success = false;
2845 uint32_t Rn; // the first operand
2846 uint32_t imm32; // the immediate value to be compared with
2849 Rn = Bits32(opcode, 10, 8);
2850 imm32 = Bits32(opcode, 7, 0);
2853 Rn = Bits32(opcode, 19, 16);
2854 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2859 Rn = Bits32(opcode, 19, 16);
2860 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2865 // Read the register value from the operand register Rn.
2866 uint32_t reg_val = ReadCoreReg(Rn, &success);
2870 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
2872 EmulateInstruction::Context context;
2873 context.type = EmulateInstruction::eContextImmediate;
2874 context.SetNoArgs ();
2875 if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
2881 // Compare (register) subtracts an optionally-shifted register value from a register value.
2882 // It updates the condition flags based on the result, and discards the result.
2884 EmulateInstructionARM::EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding)
2887 // ARM pseudo code...
2888 if ConditionPassed() then
2889 EncodingSpecificOperations();
2890 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
2891 (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1');
2892 APSR.N = result<31>;
2893 APSR.Z = IsZeroBit(result);
2898 bool success = false;
2900 uint32_t Rn; // the first operand
2901 uint32_t Rm; // the second operand
2902 ARM_ShifterType shift_t;
2903 uint32_t shift_n; // the shift applied to the value read from Rm
2906 Rn = Bits32(opcode, 2, 0);
2907 Rm = Bits32(opcode, 5, 3);
2908 shift_t = SRType_LSL;
2912 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
2913 Rm = Bits32(opcode, 6, 3);
2914 shift_t = SRType_LSL;
2916 if (Rn < 8 && Rm < 8)
2918 if (Rn == 15 || Rm == 15)
2922 Rn = Bits32(opcode, 19, 16);
2923 Rm = Bits32(opcode, 3, 0);
2924 shift_n = DecodeImmShiftARM(opcode, shift_t);
2929 // Read the register value from register Rn.
2930 uint32_t val1 = ReadCoreReg(Rn, &success);
2934 // Read the register value from register Rm.
2935 uint32_t val2 = ReadCoreReg(Rm, &success);
2939 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
2942 AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1);
2944 EmulateInstruction::Context context;
2945 context.type = EmulateInstruction::eContextImmediate;
2946 context.SetNoArgs();
2947 if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
2953 // Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits,
2954 // shifting in copies of its sign bit, and writes the result to the destination register. It can
2955 // optionally update the condition flags based on the result.
2957 EmulateInstructionARM::EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding)
2960 // ARM pseudo code...
2961 if ConditionPassed() then
2962 EncodingSpecificOperations();
2963 (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
2964 if d == 15 then // Can only occur for ARM encoding
2965 ALUWritePC(result); // setflags is always FALSE here
2969 APSR.N = result<31>;
2970 APSR.Z = IsZeroBit(result);
2975 return EmulateShiftImm (opcode, encoding, SRType_ASR);
2978 // Arithmetic Shift Right (register) shifts a register value right by a variable number of bits,
2979 // shifting in copies of its sign bit, and writes the result to the destination register.
2980 // The variable number of bits is read from the bottom byte of a register. It can optionally update
2981 // the condition flags based on the result.
2983 EmulateInstructionARM::EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding)
2986 // ARM pseudo code...
2987 if ConditionPassed() then
2988 EncodingSpecificOperations();
2989 shift_n = UInt(R[m]<7:0>);
2990 (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
2993 APSR.N = result<31>;
2994 APSR.Z = IsZeroBit(result);
2999 return EmulateShiftReg (opcode, encoding, SRType_ASR);
3002 // Logical Shift Left (immediate) shifts a register value left by an immediate number of bits,
3003 // shifting in zeros, and writes the result to the destination register. It can optionally
3004 // update the condition flags based on the result.
3006 EmulateInstructionARM::EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding)
3009 // ARM pseudo code...
3010 if ConditionPassed() then
3011 EncodingSpecificOperations();
3012 (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
3013 if d == 15 then // Can only occur for ARM encoding
3014 ALUWritePC(result); // setflags is always FALSE here
3018 APSR.N = result<31>;
3019 APSR.Z = IsZeroBit(result);
3024 return EmulateShiftImm (opcode, encoding, SRType_LSL);
3027 // Logical Shift Left (register) shifts a register value left by a variable number of bits,
3028 // shifting in zeros, and writes the result to the destination register. The variable number
3029 // of bits is read from the bottom byte of a register. It can optionally update the condition
3030 // flags based on the result.
3032 EmulateInstructionARM::EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding)
3035 // ARM pseudo code...
3036 if ConditionPassed() then
3037 EncodingSpecificOperations();
3038 shift_n = UInt(R[m]<7:0>);
3039 (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
3042 APSR.N = result<31>;
3043 APSR.Z = IsZeroBit(result);
3048 return EmulateShiftReg (opcode, encoding, SRType_LSL);
3051 // Logical Shift Right (immediate) shifts a register value right by an immediate number of bits,
3052 // shifting in zeros, and writes the result to the destination register. It can optionally
3053 // update the condition flags based on the result.
3055 EmulateInstructionARM::EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding)
3058 // ARM pseudo code...
3059 if ConditionPassed() then
3060 EncodingSpecificOperations();
3061 (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
3062 if d == 15 then // Can only occur for ARM encoding
3063 ALUWritePC(result); // setflags is always FALSE here
3067 APSR.N = result<31>;
3068 APSR.Z = IsZeroBit(result);
3073 return EmulateShiftImm (opcode, encoding, SRType_LSR);
3076 // Logical Shift Right (register) shifts a register value right by a variable number of bits,
3077 // shifting in zeros, and writes the result to the destination register. The variable number
3078 // of bits is read from the bottom byte of a register. It can optionally update the condition
3079 // flags based on the result.
3081 EmulateInstructionARM::EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding)
3084 // ARM pseudo code...
3085 if ConditionPassed() then
3086 EncodingSpecificOperations();
3087 shift_n = UInt(R[m]<7:0>);
3088 (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
3091 APSR.N = result<31>;
3092 APSR.Z = IsZeroBit(result);
3097 return EmulateShiftReg (opcode, encoding, SRType_LSR);
3100 // Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value.
3101 // The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
3102 // It can optionally update the condition flags based on the result.
3104 EmulateInstructionARM::EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding)
3107 // ARM pseudo code...
3108 if ConditionPassed() then
3109 EncodingSpecificOperations();
3110 (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
3111 if d == 15 then // Can only occur for ARM encoding
3112 ALUWritePC(result); // setflags is always FALSE here
3116 APSR.N = result<31>;
3117 APSR.Z = IsZeroBit(result);
3122 return EmulateShiftImm (opcode, encoding, SRType_ROR);
3125 // Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits.
3126 // The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
3127 // The variable number of bits is read from the bottom byte of a register. It can optionally update the condition
3128 // flags based on the result.
3130 EmulateInstructionARM::EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding)
3133 // ARM pseudo code...
3134 if ConditionPassed() then
3135 EncodingSpecificOperations();
3136 shift_n = UInt(R[m]<7:0>);
3137 (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
3140 APSR.N = result<31>;
3141 APSR.Z = IsZeroBit(result);
3146 return EmulateShiftReg (opcode, encoding, SRType_ROR);
3149 // Rotate Right with Extend provides the value of the contents of a register shifted right by one place,
3150 // with the carry flag shifted into bit [31].
3152 // RRX can optionally update the condition flags based on the result.
3153 // In that case, bit [0] is shifted into the carry flag.
3155 EmulateInstructionARM::EmulateRRX (const uint32_t opcode, const ARMEncoding encoding)
3158 // ARM pseudo code...
3159 if ConditionPassed() then
3160 EncodingSpecificOperations();
3161 (result, carry) = Shift_C(R[m], SRType_RRX, 1, APSR.C);
3162 if d == 15 then // Can only occur for ARM encoding
3163 ALUWritePC(result); // setflags is always FALSE here
3167 APSR.N = result<31>;
3168 APSR.Z = IsZeroBit(result);
3173 return EmulateShiftImm (opcode, encoding, SRType_RRX);
3177 EmulateInstructionARM::EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type)
3179 // assert(shift_type == SRType_ASR
3180 // || shift_type == SRType_LSL
3181 // || shift_type == SRType_LSR
3182 // || shift_type == SRType_ROR
3183 // || shift_type == SRType_RRX);
3185 bool success = false;
3187 if (ConditionPassed(opcode))
3189 uint32_t Rd; // the destination register
3190 uint32_t Rm; // the first operand register
3191 uint32_t imm5; // encoding for the shift amount
3192 uint32_t carry; // the carry bit after the shift operation
3195 // Special case handling!
3196 // A8.6.139 ROR (immediate) -- Encoding T1
3197 ARMEncoding use_encoding = encoding;
3198 if (shift_type == SRType_ROR && use_encoding == eEncodingT1)
3200 // Morph the T1 encoding from the ARM Architecture Manual into T2 encoding to
3201 // have the same decoding of bit fields as the other Thumb2 shift operations.
3202 use_encoding = eEncodingT2;
3205 switch (use_encoding) {
3207 // Due to the above special case handling!
3208 if (shift_type == SRType_ROR)
3211 Rd = Bits32(opcode, 2, 0);
3212 Rm = Bits32(opcode, 5, 3);
3213 setflags = !InITBlock();
3214 imm5 = Bits32(opcode, 10, 6);
3218 // There's no imm form of RRX instructions.
3219 if (shift_type == SRType_RRX)
3222 Rd = Bits32(opcode, 11, 8);
3223 Rm = Bits32(opcode, 3, 0);
3224 setflags = BitIsSet(opcode, 20);
3225 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6);
3226 if (BadReg(Rd) || BadReg(Rm))
3230 Rd = Bits32(opcode, 15, 12);
3231 Rm = Bits32(opcode, 3, 0);
3232 setflags = BitIsSet(opcode, 20);
3233 imm5 = Bits32(opcode, 11, 7);
3239 // A8.6.139 ROR (immediate)
3240 if (shift_type == SRType_ROR && imm5 == 0)
3241 shift_type = SRType_RRX;
3243 // Get the first operand.
3244 uint32_t value = ReadCoreReg (Rm, &success);
3248 // Decode the shift amount if not RRX.
3249 uint32_t amt = (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5));
3251 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3255 // The context specifies that an immediate is to be moved into Rd.
3256 EmulateInstruction::Context context;
3257 context.type = EmulateInstruction::eContextImmediate;
3258 context.SetNoArgs ();
3260 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3267 EmulateInstructionARM::EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type)
3269 // assert(shift_type == SRType_ASR
3270 // || shift_type == SRType_LSL
3271 // || shift_type == SRType_LSR
3272 // || shift_type == SRType_ROR);
3274 bool success = false;
3276 if (ConditionPassed(opcode))
3278 uint32_t Rd; // the destination register
3279 uint32_t Rn; // the first operand register
3280 uint32_t Rm; // the register whose bottom byte contains the amount to shift by
3281 uint32_t carry; // the carry bit after the shift operation
3285 Rd = Bits32(opcode, 2, 0);
3287 Rm = Bits32(opcode, 5, 3);
3288 setflags = !InITBlock();
3291 Rd = Bits32(opcode, 11, 8);
3292 Rn = Bits32(opcode, 19, 16);
3293 Rm = Bits32(opcode, 3, 0);
3294 setflags = BitIsSet(opcode, 20);
3295 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3299 Rd = Bits32(opcode, 15, 12);
3300 Rn = Bits32(opcode, 3, 0);
3301 Rm = Bits32(opcode, 11, 8);
3302 setflags = BitIsSet(opcode, 20);
3303 if (Rd == 15 || Rn == 15 || Rm == 15)
3310 // Get the first operand.
3311 uint32_t value = ReadCoreReg (Rn, &success);
3314 // Get the Rm register content.
3315 uint32_t val = ReadCoreReg (Rm, &success);
3319 // Get the shift amount.
3320 uint32_t amt = Bits32(val, 7, 0);
3322 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
3326 // The context specifies that an immediate is to be moved into Rd.
3327 EmulateInstruction::Context context;
3328 context.type = EmulateInstruction::eContextImmediate;
3329 context.SetNoArgs ();
3331 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
3337 // LDM loads multiple registers from consecutive memory locations, using an
3338 // address from a base register. Optionally the address just above the highest of those locations
3339 // can be written back to the base register.
3341 EmulateInstructionARM::EmulateLDM (const uint32_t opcode, const ARMEncoding encoding)
3344 // ARM pseudo code...
3345 if ConditionPassed()
3346 EncodingSpecificOperations(); NullCheckIfThumbEE (n);
3350 if registers<i> == '1' then
3351 R[i] = MemA[address, 4]; address = address + 4;
3352 if registers<15> == '1' then
3353 LoadWritePC (MemA[address, 4]);
3355 if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers);
3356 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3360 bool success = false;
3361 bool conditional = false;
3362 if (ConditionPassed(opcode, &conditional))
3365 uint32_t registers = 0;
3367 const uint32_t addr_byte_size = GetAddressByteSize();
3371 // n = UInt(Rn); registers = '00000000':register_list; wback = (registers<n> == '0');
3372 n = Bits32 (opcode, 10, 8);
3373 registers = Bits32 (opcode, 7, 0);
3374 registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
3375 wback = BitIsClear (registers, n);
3376 // if BitCount(registers) < 1 then UNPREDICTABLE;
3377 if (BitCount(registers) < 1)
3381 // if W == '1' && Rn == '1101' then SEE POP;
3382 // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3383 n = Bits32 (opcode, 19, 16);
3384 registers = Bits32 (opcode, 15, 0);
3385 registers = registers & 0xdfff; // Make sure bit 13 is zero.
3386 wback = BitIsSet (opcode, 21);
3388 // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
3390 || (BitCount (registers) < 2)
3391 || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15)))
3394 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3395 if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock())
3398 // if wback && registers<n> == '1' then UNPREDICTABLE;
3400 && BitIsSet (registers, n))
3405 n = Bits32 (opcode, 19, 16);
3406 registers = Bits32 (opcode, 15, 0);
3407 wback = BitIsSet (opcode, 21);
3409 || (BitCount (registers) < 1))
3417 const addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3421 EmulateInstruction::Context context;
3422 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3423 RegisterInfo dwarf_reg;
3424 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3425 context.SetRegisterPlusOffset (dwarf_reg, offset);
3427 for (int i = 0; i < 14; ++i)
3429 if (BitIsSet (registers, i))
3431 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3432 context.SetRegisterPlusOffset (dwarf_reg, offset);
3433 if (wback && (n == 13)) // Pop Instruction
3436 context.type = EmulateInstruction::eContextRegisterLoad;
3438 context.type = EmulateInstruction::eContextPopRegisterOffStack;
3441 // R[i] = MemA [address, 4]; address = address + 4;
3442 uint32_t data = MemARead (context, base_address + offset, addr_byte_size, 0, &success);
3446 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
3449 offset += addr_byte_size;
3453 if (BitIsSet (registers, 15))
3455 //LoadWritePC (MemA [address, 4]);
3456 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3457 context.SetRegisterPlusOffset (dwarf_reg, offset);
3458 uint32_t data = MemARead (context, base_address + offset, addr_byte_size, 0, &success);
3461 // In ARMv5T and above, this is an interworking branch.
3462 if (!LoadWritePC(context, data))
3466 if (wback && BitIsClear (registers, n))
3468 // R[n] = R[n] + 4 * BitCount (registers)
3469 int32_t offset = addr_byte_size * BitCount (registers);
3470 context.type = EmulateInstruction::eContextAdjustBaseRegister;
3471 context.SetRegisterPlusOffset (dwarf_reg, offset);
3473 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, base_address + offset))
3476 if (wback && BitIsSet (registers, n))
3477 // R[n] bits(32) UNKNOWN;
3478 return WriteBits32Unknown (n);
3483 // LDMDA loads multiple registers from consecutive memory locations using an address from a base register.
3484 // The consecutive memory locations end at this address and the address just below the lowest of those locations
3485 // can optionally be written back to the base register.
3487 EmulateInstructionARM::EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding)
3490 // ARM pseudo code...
3491 if ConditionPassed() then
3492 EncodingSpecificOperations();
3493 address = R[n] - 4*BitCount(registers) + 4;
3496 if registers<i> == '1' then
3497 R[i] = MemA[address,4]; address = address + 4;
3499 if registers<15> == '1' then
3500 LoadWritePC(MemA[address,4]);
3502 if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3503 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3506 bool success = false;
3508 if (ConditionPassed(opcode))
3511 uint32_t registers = 0;
3513 const uint32_t addr_byte_size = GetAddressByteSize();
3515 // EncodingSpecificOperations();
3519 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3520 n = Bits32 (opcode, 19, 16);
3521 registers = Bits32 (opcode, 15, 0);
3522 wback = BitIsSet (opcode, 21);
3524 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3525 if ((n == 15) || (BitCount (registers) < 1))
3533 // address = R[n] - 4*BitCount(registers) + 4;
3536 addr_t Rn = ReadCoreReg (n, &success);
3541 addr_t address = Rn - (addr_byte_size * BitCount (registers)) + addr_byte_size;
3543 EmulateInstruction::Context context;
3544 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3545 RegisterInfo dwarf_reg;
3546 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3547 context.SetRegisterPlusOffset (dwarf_reg, offset);
3550 for (int i = 0; i < 14; ++i)
3552 // if registers<i> == '1' then
3553 if (BitIsSet (registers, i))
3555 // R[i] = MemA[address,4]; address = address + 4;
3556 context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
3557 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3560 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
3562 offset += addr_byte_size;
3566 // if registers<15> == '1' then
3567 // LoadWritePC(MemA[address,4]);
3568 if (BitIsSet (registers, 15))
3570 context.SetRegisterPlusOffset (dwarf_reg, offset);
3571 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3574 // In ARMv5T and above, this is an interworking branch.
3575 if (!LoadWritePC(context, data))
3579 // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3580 if (wback && BitIsClear (registers, n))
3585 offset = (addr_byte_size * BitCount (registers)) * -1;
3586 context.type = EmulateInstruction::eContextAdjustBaseRegister;
3587 context.SetImmediateSigned (offset);
3588 addr_t addr = Rn + offset;
3589 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
3593 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3594 if (wback && BitIsSet (registers, n))
3595 return WriteBits32Unknown (n);
3600 // LDMDB loads multiple registers from consecutive memory locations using an address from a base register. The
3601 // consecutive memory lcoations end just below this address, and the address of the lowest of those locations can
3602 // be optionally written back to the base register.
3604 EmulateInstructionARM::EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding)
3607 // ARM pseudo code...
3608 if ConditionPassed() then
3609 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
3610 address = R[n] - 4*BitCount(registers);
3613 if registers<i> == '1' then
3614 R[i] = MemA[address,4]; address = address + 4;
3615 if registers<15> == '1' then
3616 LoadWritePC(MemA[address,4]);
3618 if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3619 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3622 bool success = false;
3624 if (ConditionPassed(opcode))
3627 uint32_t registers = 0;
3629 const uint32_t addr_byte_size = GetAddressByteSize();
3633 // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3634 n = Bits32 (opcode, 19, 16);
3635 registers = Bits32 (opcode, 15, 0);
3636 registers = registers & 0xdfff; // Make sure bit 13 is a zero.
3637 wback = BitIsSet (opcode, 21);
3639 // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
3641 || (BitCount (registers) < 2)
3642 || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15)))
3645 // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3646 if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock())
3649 // if wback && registers<n> == '1' then UNPREDICTABLE;
3650 if (wback && BitIsSet (registers, n))
3656 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3657 n = Bits32 (opcode, 19, 16);
3658 registers = Bits32 (opcode, 15, 0);
3659 wback = BitIsSet (opcode, 21);
3661 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3662 if ((n == 15) || (BitCount (registers) < 1))
3671 // address = R[n] - 4*BitCount(registers);
3674 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3679 addr_t address = Rn - (addr_byte_size * BitCount (registers));
3680 EmulateInstruction::Context context;
3681 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3682 RegisterInfo dwarf_reg;
3683 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3684 context.SetRegisterPlusOffset (dwarf_reg, Rn - address);
3686 for (int i = 0; i < 14; ++i)
3688 if (BitIsSet (registers, i))
3690 // R[i] = MemA[address,4]; address = address + 4;
3691 context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
3692 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3696 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
3699 offset += addr_byte_size;
3703 // if registers<15> == '1' then
3704 // LoadWritePC(MemA[address,4]);
3705 if (BitIsSet (registers, 15))
3707 context.SetRegisterPlusOffset (dwarf_reg, offset);
3708 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3711 // In ARMv5T and above, this is an interworking branch.
3712 if (!LoadWritePC(context, data))
3716 // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
3717 if (wback && BitIsClear (registers, n))
3722 offset = (addr_byte_size * BitCount (registers)) * -1;
3723 context.type = EmulateInstruction::eContextAdjustBaseRegister;
3724 context.SetImmediateSigned (offset);
3725 addr_t addr = Rn + offset;
3726 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
3730 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3731 if (wback && BitIsSet (registers, n))
3732 return WriteBits32Unknown (n);
3737 // LDMIB loads multiple registers from consecutive memory locations using an address from a base register. The
3738 // consecutive memory locations start just above this address, and thea ddress of the last of those locations can
3739 // optinoally be written back to the base register.
3741 EmulateInstructionARM::EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding)
3744 if ConditionPassed() then
3745 EncodingSpecificOperations();
3749 if registers<i> == '1' then
3750 R[i] = MemA[address,4]; address = address + 4;
3751 if registers<15> == '1' then
3752 LoadWritePC(MemA[address,4]);
3754 if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
3755 if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
3758 bool success = false;
3760 if (ConditionPassed(opcode))
3763 uint32_t registers = 0;
3765 const uint32_t addr_byte_size = GetAddressByteSize();
3769 // n = UInt(Rn); registers = register_list; wback = (W == '1');
3770 n = Bits32 (opcode, 19, 16);
3771 registers = Bits32 (opcode, 15, 0);
3772 wback = BitIsSet (opcode, 21);
3774 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
3775 if ((n == 15) || (BitCount (registers) < 1))
3782 // address = R[n] + 4;
3785 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3790 addr_t address = Rn + addr_byte_size;
3792 EmulateInstruction::Context context;
3793 context.type = EmulateInstruction::eContextRegisterPlusOffset;
3794 RegisterInfo dwarf_reg;
3795 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
3796 context.SetRegisterPlusOffset (dwarf_reg, offset);
3798 for (int i = 0; i < 14; ++i)
3800 if (BitIsSet (registers, i))
3802 // R[i] = MemA[address,4]; address = address + 4;
3804 context.SetRegisterPlusOffset (dwarf_reg, offset + addr_byte_size);
3805 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3809 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
3812 offset += addr_byte_size;
3816 // if registers<15> == '1' then
3817 // LoadWritePC(MemA[address,4]);
3818 if (BitIsSet (registers, 15))
3820 context.SetRegisterPlusOffset (dwarf_reg, offset);
3821 uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
3824 // In ARMv5T and above, this is an interworking branch.
3825 if (!LoadWritePC(context, data))
3829 // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
3830 if (wback && BitIsClear (registers, n))
3835 offset = addr_byte_size * BitCount (registers);
3836 context.type = EmulateInstruction::eContextAdjustBaseRegister;
3837 context.SetImmediateSigned (offset);
3838 addr_t addr = Rn + offset;
3839 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
3843 // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
3844 if (wback && BitIsSet (registers, n))
3845 return WriteBits32Unknown (n);
3850 // Load Register (immediate) calculates an address from a base register value and
3851 // an immediate offset, loads a word from memory, and writes to a register.
3852 // LDR (immediate, Thumb)
3854 EmulateInstructionARM::EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding)
3857 // ARM pseudo code...
3858 if (ConditionPassed())
3860 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
3861 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
3862 address = if index then offset_addr else R[n];
3863 data = MemU[address,4];
3864 if wback then R[n] = offset_addr;
3866 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
3867 elsif UnalignedSupport() || address<1:0> = '00' then
3869 else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7
3873 bool success = false;
3875 if (ConditionPassed(opcode))
3877 uint32_t Rt; // the destination register
3878 uint32_t Rn; // the base register
3879 uint32_t imm32; // the immediate offset used to form the address
3880 addr_t offset_addr; // the offset address
3881 addr_t address; // the calculated address
3882 uint32_t data; // the literal data value from memory load
3883 bool add, index, wback;
3886 Rt = Bits32(opcode, 2, 0);
3887 Rn = Bits32(opcode, 5, 3);
3888 imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32);
3889 // index = TRUE; add = TRUE; wback = FALSE
3897 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
3898 Rt = Bits32 (opcode, 10, 8);
3900 imm32 = Bits32 (opcode, 7, 0) << 2;
3902 // index = TRUE; add = TRUE; wback = FALSE;
3910 // if Rn == '1111' then SEE LDR (literal);
3911 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
3912 Rt = Bits32 (opcode, 15, 12);
3913 Rn = Bits32 (opcode, 19, 16);
3914 imm32 = Bits32 (opcode, 11, 0);
3916 // index = TRUE; add = TRUE; wback = FALSE;
3921 // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
3922 if ((Rt == 15) && InITBlock() && !LastInITBlock())
3928 // if Rn == '1111' then SEE LDR (literal);
3929 // if P == '1' && U == '1' && W == '0' then SEE LDRT;
3930 // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP;
3931 // if P == '0' && W == '0' then UNDEFINED;
3932 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
3935 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
3936 Rt = Bits32 (opcode, 15, 12);
3937 Rn = Bits32 (opcode, 19, 16);
3938 imm32 = Bits32 (opcode, 7, 0);
3940 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
3941 index = BitIsSet (opcode, 10);
3942 add = BitIsSet (opcode, 9);
3943 wback = BitIsSet (opcode, 8);
3945 // if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
3946 if ((wback && (Rn == Rt)) || ((Rt == 15) && InITBlock() && !LastInITBlock()))
3954 uint32_t base = ReadCoreReg (Rn, &success);
3958 offset_addr = base + imm32;
3960 offset_addr = base - imm32;
3962 address = (index ? offset_addr : base);
3964 RegisterInfo base_reg;
3965 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
3968 EmulateInstruction::Context ctx;
3969 ctx.type = EmulateInstruction::eContextAdjustBaseRegister;
3970 ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));
3972 if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr))
3976 // Prepare to write to the Rt register.
3977 EmulateInstruction::Context context;
3978 context.type = EmulateInstruction::eContextRegisterLoad;
3979 context.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));
3981 // Read memory from the address.
3982 data = MemURead(context, address, 4, 0, &success);
3988 if (Bits32(address, 1, 0) == 0)
3990 if (!LoadWritePC(context, data))
3996 else if (UnalignedSupport() || Bits32(address, 1, 0) == 0)
3998 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data))
4002 WriteBits32Unknown (Rt);
4007 // STM (Store Multiple Increment After) stores multiple registers to consecutive memory locations using an address
4008 // from a base register. The consecutive memory locations start at this address, and teh address just above the last
4009 // of those locations can optionally be written back to the base register.
4011 EmulateInstructionARM::EmulateSTM (const uint32_t opcode, const ARMEncoding encoding)
4014 if ConditionPassed() then
4015 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4019 if registers<i> == '1' then
4020 if i == n && wback && i != LowestSetBit(registers) then
4021 MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
4023 MemA[address,4] = R[i];
4024 address = address + 4;
4026 if registers<15> == '1' then // Only possible for encoding A1
4027 MemA[address,4] = PCStoreValue();
4028 if wback then R[n] = R[n] + 4*BitCount(registers);
4031 bool success = false;
4033 if (ConditionPassed(opcode))
4036 uint32_t registers = 0;
4038 const uint32_t addr_byte_size = GetAddressByteSize();
4040 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4044 // n = UInt(Rn); registers = '00000000':register_list; wback = TRUE;
4045 n = Bits32 (opcode, 10, 8);
4046 registers = Bits32 (opcode, 7, 0);
4047 registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
4050 // if BitCount(registers) < 1 then UNPREDICTABLE;
4051 if (BitCount (registers) < 1)
4057 // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4058 n = Bits32 (opcode, 19, 16);
4059 registers = Bits32 (opcode, 15, 0);
4060 registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4061 wback = BitIsSet (opcode, 21);
4063 // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4064 if ((n == 15) || (BitCount (registers) < 2))
4067 // if wback && registers<n> == '1' then UNPREDICTABLE;
4068 if (wback && BitIsSet (registers, n))
4074 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4075 n = Bits32 (opcode, 19, 16);
4076 registers = Bits32 (opcode, 15, 0);
4077 wback = BitIsSet (opcode, 21);
4079 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4080 if ((n == 15) || (BitCount (registers) < 1))
4091 const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4095 EmulateInstruction::Context context;
4096 context.type = EmulateInstruction::eContextRegisterStore;
4097 RegisterInfo base_reg;
4098 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4101 uint32_t lowest_set_bit = 14;
4102 for (uint32_t i = 0; i < 14; ++i)
4104 // if registers<i> == '1' then
4105 if (BitIsSet (registers, i))
4107 if (i < lowest_set_bit)
4109 // if i == n && wback && i != LowestSetBit(registers) then
4110 if ((i == n) && wback && (i != lowest_set_bit))
4111 // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
4112 WriteBits32UnknownToMemory (address + offset);
4115 // MemA[address,4] = R[i];
4116 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
4120 RegisterInfo data_reg;
4121 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4122 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
4123 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4127 // address = address + 4;
4128 offset += addr_byte_size;
4132 // if registers<15> == '1' then // Only possible for encoding A1
4133 // MemA[address,4] = PCStoreValue();
4134 if (BitIsSet (registers, 15))
4136 RegisterInfo pc_reg;
4137 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
4138 context.SetRegisterPlusOffset (pc_reg, 8);
4139 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4143 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4147 // if wback then R[n] = R[n] + 4*BitCount(registers);
4150 offset = addr_byte_size * BitCount (registers);
4151 context.type = EmulateInstruction::eContextAdjustBaseRegister;
4152 context.SetImmediateSigned (offset);
4153 addr_t data = address + offset;
4154 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
4161 // STMDA (Store Multiple Decrement After) stores multiple registers to consecutive memory locations using an address
4162 // from a base register. The consecutive memory locations end at this address, and the address just below the lowest
4163 // of those locations can optionally be written back to the base register.
4165 EmulateInstructionARM::EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding)
4168 if ConditionPassed() then
4169 EncodingSpecificOperations();
4170 address = R[n] - 4*BitCount(registers) + 4;
4173 if registers<i> == '1' then
4174 if i == n && wback && i != LowestSetBit(registers) then
4175 MemA[address,4] = bits(32) UNKNOWN;
4177 MemA[address,4] = R[i];
4178 address = address + 4;
4180 if registers<15> == '1' then
4181 MemA[address,4] = PCStoreValue();
4183 if wback then R[n] = R[n] - 4*BitCount(registers);
4186 bool success = false;
4188 if (ConditionPassed(opcode))
4191 uint32_t registers = 0;
4193 const uint32_t addr_byte_size = GetAddressByteSize();
4195 // EncodingSpecificOperations();
4199 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4200 n = Bits32 (opcode, 19, 16);
4201 registers = Bits32 (opcode, 15, 0);
4202 wback = BitIsSet (opcode, 21);
4204 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4205 if ((n == 15) || (BitCount (registers) < 1))
4212 // address = R[n] - 4*BitCount(registers) + 4;
4214 addr_t Rn = ReadCoreReg (n, &success);
4218 addr_t address = Rn - (addr_byte_size * BitCount (registers)) + 4;
4220 EmulateInstruction::Context context;
4221 context.type = EmulateInstruction::eContextRegisterStore;
4222 RegisterInfo base_reg;
4223 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4226 uint32_t lowest_bit_set = 14;
4227 for (uint32_t i = 0; i < 14; ++i)
4229 // if registers<i> == '1' then
4230 if (BitIsSet (registers, i))
4232 if (i < lowest_bit_set)
4234 //if i == n && wback && i != LowestSetBit(registers) then
4235 if ((i == n) && wback && (i != lowest_bit_set))
4236 // MemA[address,4] = bits(32) UNKNOWN;
4237 WriteBits32UnknownToMemory (address + offset);
4240 // MemA[address,4] = R[i];
4241 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
4245 RegisterInfo data_reg;
4246 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4247 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
4248 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4252 // address = address + 4;
4253 offset += addr_byte_size;
4257 // if registers<15> == '1' then
4258 // MemA[address,4] = PCStoreValue();
4259 if (BitIsSet (registers, 15))
4261 RegisterInfo pc_reg;
4262 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
4263 context.SetRegisterPlusOffset (pc_reg, 8);
4264 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4268 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4272 // if wback then R[n] = R[n] - 4*BitCount(registers);
4275 offset = (addr_byte_size * BitCount (registers)) * -1;
4276 context.type = EmulateInstruction::eContextAdjustBaseRegister;
4277 context.SetImmediateSigned (offset);
4278 addr_t data = Rn + offset;
4279 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
4286 // STMDB (Store Multiple Decrement Before) stores multiple registers to consecutive memory locations using an address
4287 // from a base register. The consecutive memory locations end just below this address, and the address of the first of
4288 // those locations can optionally be written back to the base register.
4290 EmulateInstructionARM::EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding)
4293 if ConditionPassed() then
4294 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4295 address = R[n] - 4*BitCount(registers);
4298 if registers<i> == '1' then
4299 if i == n && wback && i != LowestSetBit(registers) then
4300 MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
4302 MemA[address,4] = R[i];
4303 address = address + 4;
4305 if registers<15> == '1' then // Only possible for encoding A1
4306 MemA[address,4] = PCStoreValue();
4308 if wback then R[n] = R[n] - 4*BitCount(registers);
4312 bool success = false;
4314 if (ConditionPassed(opcode))
4317 uint32_t registers = 0;
4319 const uint32_t addr_byte_size = GetAddressByteSize();
4321 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4325 // if W == '1' && Rn == '1101' then SEE PUSH;
4326 if ((BitIsSet (opcode, 21)) && (Bits32 (opcode, 19, 16) == 13))
4330 // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4331 n = Bits32 (opcode, 19, 16);
4332 registers = Bits32 (opcode, 15, 0);
4333 registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4334 wback = BitIsSet (opcode, 21);
4335 // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
4336 if ((n == 15) || BitCount (registers) < 2)
4338 // if wback && registers<n> == '1' then UNPREDICTABLE;
4339 if (wback && BitIsSet (registers, n))
4344 // if W == '1' && Rn == '1101Õ && BitCount(register_list) >= 2 then SEE PUSH;
4345 if (BitIsSet (opcode, 21) && (Bits32 (opcode, 19, 16) == 13) && BitCount (Bits32 (opcode, 15, 0)) >= 2)
4349 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4350 n = Bits32 (opcode, 19, 16);
4351 registers = Bits32 (opcode, 15, 0);
4352 wback = BitIsSet (opcode, 21);
4353 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4354 if ((n == 15) || BitCount (registers) < 1)
4362 // address = R[n] - 4*BitCount(registers);
4365 addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4369 addr_t address = Rn - (addr_byte_size * BitCount (registers));
4371 EmulateInstruction::Context context;
4372 context.type = EmulateInstruction::eContextRegisterStore;
4373 RegisterInfo base_reg;
4374 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4377 uint32_t lowest_set_bit = 14;
4378 for (uint32_t i = 0; i < 14; ++i)
4380 // if registers<i> == '1' then
4381 if (BitIsSet (registers, i))
4383 if (i < lowest_set_bit)
4385 // if i == n && wback && i != LowestSetBit(registers) then
4386 if ((i == n) && wback && (i != lowest_set_bit))
4387 // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
4388 WriteBits32UnknownToMemory (address + offset);
4391 // MemA[address,4] = R[i];
4392 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
4396 RegisterInfo data_reg;
4397 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4398 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
4399 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4403 // address = address + 4;
4404 offset += addr_byte_size;
4408 // if registers<15> == '1' then // Only possible for encoding A1
4409 // MemA[address,4] = PCStoreValue();
4410 if (BitIsSet (registers, 15))
4412 RegisterInfo pc_reg;
4413 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
4414 context.SetRegisterPlusOffset (pc_reg, 8);
4415 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4419 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4423 // if wback then R[n] = R[n] - 4*BitCount(registers);
4426 offset = (addr_byte_size * BitCount (registers)) * -1;
4427 context.type = EmulateInstruction::eContextAdjustBaseRegister;
4428 context.SetImmediateSigned (offset);
4429 addr_t data = Rn + offset;
4430 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
4437 // STMIB (Store Multiple Increment Before) stores multiple registers to consecutive memory locations using an address
4438 // from a base register. The consecutive memory locations start just above this address, and the address of the last
4439 // of those locations can optionally be written back to the base register.
4441 EmulateInstructionARM::EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding)
4444 if ConditionPassed() then
4445 EncodingSpecificOperations();
4449 if registers<i> == '1' then
4450 if i == n && wback && i != LowestSetBit(registers) then
4451 MemA[address,4] = bits(32) UNKNOWN;
4453 MemA[address,4] = R[i];
4454 address = address + 4;
4456 if registers<15> == '1' then
4457 MemA[address,4] = PCStoreValue();
4459 if wback then R[n] = R[n] + 4*BitCount(registers);
4462 bool success = false;
4464 if (ConditionPassed(opcode))
4467 uint32_t registers = 0;
4469 const uint32_t addr_byte_size = GetAddressByteSize();
4471 // EncodingSpecificOperations();
4475 // n = UInt(Rn); registers = register_list; wback = (W == '1');
4476 n = Bits32 (opcode, 19, 16);
4477 registers = Bits32 (opcode, 15, 0);
4478 wback = BitIsSet (opcode, 21);
4480 // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
4481 if ((n == 15) && (BitCount (registers) < 1))
4487 // address = R[n] + 4;
4490 addr_t Rn = ReadCoreReg (n, &success);
4494 addr_t address = Rn + addr_byte_size;
4496 EmulateInstruction::Context context;
4497 context.type = EmulateInstruction::eContextRegisterStore;
4498 RegisterInfo base_reg;
4499 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4501 uint32_t lowest_set_bit = 14;
4503 for (uint32_t i = 0; i < 14; ++i)
4505 // if registers<i> == '1' then
4506 if (BitIsSet (registers, i))
4508 if (i < lowest_set_bit)
4510 // if i == n && wback && i != LowestSetBit(registers) then
4511 if ((i == n) && wback && (i != lowest_set_bit))
4512 // MemA[address,4] = bits(32) UNKNOWN;
4513 WriteBits32UnknownToMemory (address + offset);
4517 // MemA[address,4] = R[i];
4518 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
4522 RegisterInfo data_reg;
4523 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
4524 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset + addr_byte_size);
4525 if (!MemAWrite (context, address + offset, data, addr_byte_size))
4529 // address = address + 4;
4530 offset += addr_byte_size;
4534 // if registers<15> == '1' then
4535 // MemA[address,4] = PCStoreValue();
4536 if (BitIsSet (registers, 15))
4538 RegisterInfo pc_reg;
4539 GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
4540 context.SetRegisterPlusOffset (pc_reg, 8);
4541 const uint32_t pc = ReadCoreReg (PC_REG, &success);
4545 if (!MemAWrite (context, address + offset, pc, addr_byte_size))
4549 // if wback then R[n] = R[n] + 4*BitCount(registers);
4552 offset = addr_byte_size * BitCount (registers);
4553 context.type = EmulateInstruction::eContextAdjustBaseRegister;
4554 context.SetImmediateSigned (offset);
4555 addr_t data = Rn + offset;
4556 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
4563 // STR (store immediate) calcualtes an address from a base register value and an immediate offset, and stores a word
4564 // from a register to memory. It can use offset, post-indexed, or pre-indexed addressing.
4566 EmulateInstructionARM::EmulateSTRThumb (const uint32_t opcode, const ARMEncoding encoding)
4569 if ConditionPassed() then
4570 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4571 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4572 address = if index then offset_addr else R[n];
4573 if UnalignedSupport() || address<1:0> == '00' then
4574 MemU[address,4] = R[t];
4575 else // Can only occur before ARMv7
4576 MemU[address,4] = bits(32) UNKNOWN;
4577 if wback then R[n] = offset_addr;
4580 bool success = false;
4582 if (ConditionPassed(opcode))
4584 const uint32_t addr_byte_size = GetAddressByteSize();
4592 // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
4596 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
4597 t = Bits32 (opcode, 2, 0);
4598 n = Bits32 (opcode, 5, 3);
4599 imm32 = Bits32 (opcode, 10, 6) << 2;
4601 // index = TRUE; add = TRUE; wback = FALSE;
4608 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
4609 t = Bits32 (opcode, 10, 8);
4611 imm32 = Bits32 (opcode, 7, 0) << 2;
4613 // index = TRUE; add = TRUE; wback = FALSE;
4620 // if Rn == '1111' then UNDEFINED;
4621 if (Bits32 (opcode, 19, 16) == 15)
4624 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4625 t = Bits32 (opcode, 15, 12);
4626 n = Bits32 (opcode, 19, 16);
4627 imm32 = Bits32 (opcode, 11, 0);
4629 // index = TRUE; add = TRUE; wback = FALSE;
4634 // if t == 15 then UNPREDICTABLE;
4640 // if P == '1' && U == '1' && W == '0' then SEE STRT;
4641 // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100' then SEE PUSH;
4642 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
4643 if ((Bits32 (opcode, 19, 16) == 15)
4644 || (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)))
4647 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
4648 t = Bits32 (opcode, 15, 12);
4649 n = Bits32 (opcode, 19, 16);
4650 imm32 = Bits32 (opcode, 7, 0);
4652 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
4653 index = BitIsSet (opcode, 10);
4654 add = BitIsSet (opcode, 9);
4655 wback = BitIsSet (opcode, 8);
4657 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
4658 if ((t == 15) || (wback && (n == t)))
4669 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4670 uint32_t base_address = ReadCoreReg (n, &success);
4675 offset_addr = base_address + imm32;
4677 offset_addr = base_address - imm32;
4679 // address = if index then offset_addr else R[n];
4681 address = offset_addr;
4683 address = base_address;
4685 EmulateInstruction::Context context;
4686 context.type = eContextRegisterStore;
4687 RegisterInfo base_reg;
4688 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4690 // if UnalignedSupport() || address<1:0> == '00' then
4691 if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)))
4693 // MemU[address,4] = R[t];
4694 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
4698 RegisterInfo data_reg;
4699 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
4700 int32_t offset = address - base_address;
4701 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
4702 if (!MemUWrite (context, address, data, addr_byte_size))
4707 // MemU[address,4] = bits(32) UNKNOWN;
4708 WriteBits32UnknownToMemory (address);
4711 // if wback then R[n] = offset_addr;
4714 context.type = eContextRegisterLoad;
4715 context.SetAddress (offset_addr);
4716 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
4723 // STR (Store Register) calculates an address from a base register value and an offset register value, stores a
4724 // word from a register to memory. The offset register value can optionally be shifted.
4726 EmulateInstructionARM::EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding)
4729 if ConditionPassed() then
4730 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4731 offset = Shift(R[m], shift_t, shift_n, APSR.C);
4732 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
4733 address = if index then offset_addr else R[n];
4734 if t == 15 then // Only possible for encoding A1
4735 data = PCStoreValue();
4738 if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
4739 MemU[address,4] = data;
4740 else // Can only occur before ARMv7
4741 MemU[address,4] = bits(32) UNKNOWN;
4742 if wback then R[n] = offset_addr;
4745 bool success = false;
4747 if (ConditionPassed(opcode))
4749 const uint32_t addr_byte_size = GetAddressByteSize();
4754 ARM_ShifterType shift_t;
4760 // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
4764 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
4765 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4766 t = Bits32 (opcode, 2, 0);
4767 n = Bits32 (opcode, 5, 3);
4768 m = Bits32 (opcode, 8, 6);
4770 // index = TRUE; add = TRUE; wback = FALSE;
4775 // (shift_t, shift_n) = (SRType_LSL, 0);
4776 shift_t = SRType_LSL;
4781 // if Rn == '1111' then UNDEFINED;
4782 if (Bits32 (opcode, 19, 16) == 15)
4785 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4786 t = Bits32 (opcode, 15, 12);
4787 n = Bits32 (opcode, 19, 16);
4788 m = Bits32 (opcode, 3, 0);
4790 // index = TRUE; add = TRUE; wback = FALSE;
4795 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
4796 shift_t = SRType_LSL;
4797 shift_n = Bits32 (opcode, 5, 4);
4799 // if t == 15 || BadReg(m) then UNPREDICTABLE;
4800 if ((t == 15) || (BadReg (m)))
4806 // if P == '0' && W == '1' then SEE STRT;
4807 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
4808 t = Bits32 (opcode, 15, 12);
4809 n = Bits32 (opcode, 19, 16);
4810 m = Bits32 (opcode, 3, 0);
4812 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
4813 index = BitIsSet (opcode, 24);
4814 add = BitIsSet (opcode, 23);
4815 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
4817 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
4818 uint32_t typ = Bits32 (opcode, 6, 5);
4819 uint32_t imm5 = Bits32 (opcode, 11, 7);
4820 shift_n = DecodeImmShift(typ, imm5, shift_t);
4822 // if m == 15 then UNPREDICTABLE;
4826 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
4827 if (wback && ((n == 15) || (n == t)))
4840 addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4844 uint32_t Rm_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
4848 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
4849 offset = Shift (Rm_data, shift_t, shift_n, APSR_C, &success);
4853 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
4855 offset_addr = base_address + offset;
4857 offset_addr = base_address - offset;
4859 // address = if index then offset_addr else R[n];
4861 address = offset_addr;
4863 address = base_address;
4866 // if t == 15 then // Only possible for encoding A1
4868 // data = PCStoreValue();
4869 data = ReadCoreReg (PC_REG, &success);
4872 data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
4877 EmulateInstruction::Context context;
4878 context.type = eContextRegisterStore;
4880 // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
4881 if (UnalignedSupport ()
4882 || (BitIsClear (address, 1) && BitIsClear (address, 0))
4883 || CurrentInstrSet() == eModeARM)
4885 // MemU[address,4] = data;
4887 RegisterInfo base_reg;
4888 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
4890 RegisterInfo data_reg;
4891 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
4893 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);
4894 if (!MemUWrite (context, address, data, addr_byte_size))
4899 // MemU[address,4] = bits(32) UNKNOWN;
4900 WriteBits32UnknownToMemory (address);
4902 // if wback then R[n] = offset_addr;
4905 context.type = eContextRegisterLoad;
4906 context.SetAddress (offset_addr);
4907 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
4916 EmulateInstructionARM::EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding)
4919 if ConditionPassed() then
4920 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4921 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
4922 address = if index then offset_addr else R[n];
4923 MemU[address,1] = R[t]<7:0>;
4924 if wback then R[n] = offset_addr;
4928 bool success = false;
4930 if (ConditionPassed(opcode))
4938 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
4942 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
4943 t = Bits32 (opcode, 2, 0);
4944 n = Bits32 (opcode, 5, 3);
4945 imm32 = Bits32 (opcode, 10, 6);
4947 // index = TRUE; add = TRUE; wback = FALSE;
4954 // if Rn == '1111' then UNDEFINED;
4955 if (Bits32 (opcode, 19, 16) == 15)
4958 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
4959 t = Bits32 (opcode, 15, 12);
4960 n = Bits32 (opcode, 19, 16);
4961 imm32 = Bits32 (opcode, 11, 0);
4963 // index = TRUE; add = TRUE; wback = FALSE;
4968 // if BadReg(t) then UNPREDICTABLE;
4974 // if P == '1' && U == '1' && W == '0' then SEE STRBT;
4975 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
4976 if (Bits32 (opcode, 19, 16) == 15)
4979 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
4980 t = Bits32 (opcode, 15, 12);
4981 n = Bits32 (opcode, 19, 16);
4982 imm32 = Bits32 (opcode, 7, 0);
4984 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
4985 index = BitIsSet (opcode, 10);
4986 add = BitIsSet (opcode, 9);
4987 wback = BitIsSet (opcode, 8);
4989 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE
4990 if ((BadReg (t)) || (wback && (n == t)))
5000 addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
5004 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5006 offset_addr = base_address + imm32;
5008 offset_addr = base_address - imm32;
5010 // address = if index then offset_addr else R[n];
5012 address = offset_addr;
5014 address = base_address;
5016 // MemU[address,1] = R[t]<7:0>
5017 RegisterInfo base_reg;
5018 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5020 RegisterInfo data_reg;
5021 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5023 EmulateInstruction::Context context;
5024 context.type = eContextRegisterStore;
5025 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);
5027 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5031 data = Bits32 (data, 7, 0);
5033 if (!MemUWrite (context, address, data, 1))
5036 // if wback then R[n] = offset_addr;
5039 context.type = eContextRegisterLoad;
5040 context.SetAddress (offset_addr);
5041 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
5050 // STRH (register) calculates an address from a base register value and an offset register value, and stores a
5051 // halfword from a register to memory. The offset register alue can be shifted left by 0, 1, 2, or 3 bits.
5053 EmulateInstructionARM::EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding)
5056 if ConditionPassed() then
5057 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5058 offset = Shift(R[m], shift_t, shift_n, APSR.C);
5059 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5060 address = if index then offset_addr else R[n];
5061 if UnalignedSupport() || address<0> == '0' then
5062 MemU[address,2] = R[t]<15:0>;
5063 else // Can only occur before ARMv7
5064 MemU[address,2] = bits(16) UNKNOWN;
5065 if wback then R[n] = offset_addr;
5068 bool success = false;
5070 if (ConditionPassed(opcode))
5078 ARM_ShifterType shift_t;
5081 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5085 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
5086 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5087 t = Bits32 (opcode, 2, 0);
5088 n = Bits32 (opcode, 5, 3);
5089 m = Bits32 (opcode, 8, 6);
5091 // index = TRUE; add = TRUE; wback = FALSE;
5096 // (shift_t, shift_n) = (SRType_LSL, 0);
5097 shift_t = SRType_LSL;
5103 // if Rn == '1111' then UNDEFINED;
5104 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5105 t = Bits32 (opcode, 15, 12);
5106 n = Bits32 (opcode, 19, 16);
5107 m = Bits32 (opcode, 3, 0);
5111 // index = TRUE; add = TRUE; wback = FALSE;
5116 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
5117 shift_t = SRType_LSL;
5118 shift_n = Bits32 (opcode, 5, 4);
5120 // if BadReg(t) || BadReg(m) then UNPREDICTABLE;
5121 if (BadReg (t) || BadReg (m))
5127 // if P == '0' && W == '1' then SEE STRHT;
5128 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5129 t = Bits32 (opcode, 15, 12);
5130 n = Bits32 (opcode, 19, 16);
5131 m = Bits32 (opcode, 3, 0);
5133 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
5134 index = BitIsSet (opcode, 24);
5135 add = BitIsSet (opcode, 23);
5136 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
5138 // (shift_t, shift_n) = (SRType_LSL, 0);
5139 shift_t = SRType_LSL;
5142 // if t == 15 || m == 15 then UNPREDICTABLE;
5143 if ((t == 15) || (m == 15))
5146 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
5147 if (wback && ((n == 15) || (n == t)))
5156 uint32_t Rm = ReadCoreReg (m, &success);
5160 uint32_t Rn = ReadCoreReg (n, &success);
5164 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
5165 uint32_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
5169 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5172 offset_addr = Rn + offset;
5174 offset_addr = Rn - offset;
5176 // address = if index then offset_addr else R[n];
5179 address = offset_addr;
5183 EmulateInstruction::Context context;
5184 context.type = eContextRegisterStore;
5185 RegisterInfo base_reg;
5186 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5187 RegisterInfo offset_reg;
5188 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
5190 // if UnalignedSupport() || address<0> == '0' then
5191 if (UnalignedSupport() || BitIsClear (address, 0))
5193 // MemU[address,2] = R[t]<15:0>;
5194 uint32_t Rt = ReadCoreReg (t, &success);
5198 EmulateInstruction::Context context;
5199 context.type = eContextRegisterStore;
5200 RegisterInfo base_reg;
5201 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5202 RegisterInfo offset_reg;
5203 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
5204 RegisterInfo data_reg;
5205 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
5206 context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
5208 if (!MemUWrite (context, address, Bits32 (Rt, 15, 0), 2))
5211 else // Can only occur before ARMv7
5213 // MemU[address,2] = bits(16) UNKNOWN;
5216 // if wback then R[n] = offset_addr;
5219 context.type = eContextAdjustBaseRegister;
5220 context.SetAddress (offset_addr);
5221 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
5229 // Add with Carry (immediate) adds an immediate value and the carry flag value to a register value,
5230 // and writes the result to the destination register. It can optionally update the condition flags
5231 // based on the result.
5233 EmulateInstructionARM::EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding)
5236 // ARM pseudo code...
5237 if ConditionPassed() then
5238 EncodingSpecificOperations();
5239 (result, carry, overflow) = AddWithCarry(R[n], imm32, APSR.C);
5240 if d == 15 then // Can only occur for ARM encoding
5241 ALUWritePC(result); // setflags is always FALSE here
5245 APSR.N = result<31>;
5246 APSR.Z = IsZeroBit(result);
5251 bool success = false;
5253 if (ConditionPassed(opcode))
5256 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
5261 Rd = Bits32(opcode, 11, 8);
5262 Rn = Bits32(opcode, 19, 16);
5263 setflags = BitIsSet(opcode, 20);
5264 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
5265 if (BadReg(Rd) || BadReg(Rn))
5269 Rd = Bits32(opcode, 15, 12);
5270 Rn = Bits32(opcode, 19, 16);
5271 setflags = BitIsSet(opcode, 20);
5272 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5274 if (Rd == 15 && setflags)
5275 return EmulateSUBSPcLrEtc (opcode, encoding);
5281 // Read the first operand.
5282 int32_t val1 = ReadCoreReg(Rn, &success);
5286 AddWithCarryResult res = AddWithCarry(val1, imm32, APSR_C);
5288 EmulateInstruction::Context context;
5289 context.type = EmulateInstruction::eContextImmediate;
5290 context.SetNoArgs ();
5292 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
5298 // Add with Carry (register) adds a register value, the carry flag value, and an optionally-shifted
5299 // register value, and writes the result to the destination register. It can optionally update the
5300 // condition flags based on the result.
5302 EmulateInstructionARM::EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding)
5305 // ARM pseudo code...
5306 if ConditionPassed() then
5307 EncodingSpecificOperations();
5308 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
5309 (result, carry, overflow) = AddWithCarry(R[n], shifted, APSR.C);
5310 if d == 15 then // Can only occur for ARM encoding
5311 ALUWritePC(result); // setflags is always FALSE here
5315 APSR.N = result<31>;
5316 APSR.Z = IsZeroBit(result);
5321 bool success = false;
5323 if (ConditionPassed(opcode))
5325 uint32_t Rd, Rn, Rm;
5326 ARM_ShifterType shift_t;
5327 uint32_t shift_n; // the shift applied to the value read from Rm
5332 Rd = Rn = Bits32(opcode, 2, 0);
5333 Rm = Bits32(opcode, 5, 3);
5334 setflags = !InITBlock();
5335 shift_t = SRType_LSL;
5339 Rd = Bits32(opcode, 11, 8);
5340 Rn = Bits32(opcode, 19, 16);
5341 Rm = Bits32(opcode, 3, 0);
5342 setflags = BitIsSet(opcode, 20);
5343 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5344 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5348 Rd = Bits32(opcode, 15, 12);
5349 Rn = Bits32(opcode, 19, 16);
5350 Rm = Bits32(opcode, 3, 0);
5351 setflags = BitIsSet(opcode, 20);
5352 shift_n = DecodeImmShiftARM(opcode, shift_t);
5354 if (Rd == 15 && setflags)
5355 return EmulateSUBSPcLrEtc (opcode, encoding);
5361 // Read the first operand.
5362 int32_t val1 = ReadCoreReg(Rn, &success);
5366 // Read the second operand.
5367 int32_t val2 = ReadCoreReg(Rm, &success);
5371 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
5374 AddWithCarryResult res = AddWithCarry(val1, shifted, APSR_C);
5376 EmulateInstruction::Context context;
5377 context.type = EmulateInstruction::eContextImmediate;
5378 context.SetNoArgs ();
5380 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
5386 // This instruction adds an immediate value to the PC value to form a PC-relative address,
5387 // and writes the result to the destination register.
5389 EmulateInstructionARM::EmulateADR (const uint32_t opcode, const ARMEncoding encoding)
5392 // ARM pseudo code...
5393 if ConditionPassed() then
5394 EncodingSpecificOperations();
5395 result = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
5396 if d == 15 then // Can only occur for ARM encodings
5402 bool success = false;
5404 if (ConditionPassed(opcode))
5407 uint32_t imm32; // the immediate value to be added/subtracted to/from the PC
5412 Rd = Bits32(opcode, 10, 8);
5413 imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32)
5418 Rd = Bits32(opcode, 11, 8);
5419 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
5420 add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB
5426 Rd = Bits32(opcode, 15, 12);
5427 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5428 add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB
5434 // Read the PC value.
5435 uint32_t pc = ReadCoreReg(PC_REG, &success);
5439 uint32_t result = (add ? Align(pc, 4) + imm32 : Align(pc, 4) - imm32);
5441 EmulateInstruction::Context context;
5442 context.type = EmulateInstruction::eContextImmediate;
5443 context.SetNoArgs ();
5445 if (!WriteCoreReg(context, result, Rd))
5451 // This instruction performs a bitwise AND of a register value and an immediate value, and writes the result
5452 // to the destination register. It can optionally update the condition flags based on the result.
5454 EmulateInstructionARM::EmulateANDImm (const uint32_t opcode, const ARMEncoding encoding)
5457 // ARM pseudo code...
5458 if ConditionPassed() then
5459 EncodingSpecificOperations();
5460 result = R[n] AND imm32;
5461 if d == 15 then // Can only occur for ARM encoding
5462 ALUWritePC(result); // setflags is always FALSE here
5466 APSR.N = result<31>;
5467 APSR.Z = IsZeroBit(result);
5472 bool success = false;
5474 if (ConditionPassed(opcode))
5477 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
5479 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
5483 Rd = Bits32(opcode, 11, 8);
5484 Rn = Bits32(opcode, 19, 16);
5485 setflags = BitIsSet(opcode, 20);
5486 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
5487 // if Rd == '1111' && S == '1' then SEE TST (immediate);
5488 if (Rd == 15 && setflags)
5489 return EmulateTSTImm(opcode, eEncodingT1);
5490 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
5494 Rd = Bits32(opcode, 15, 12);
5495 Rn = Bits32(opcode, 19, 16);
5496 setflags = BitIsSet(opcode, 20);
5497 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
5499 if (Rd == 15 && setflags)
5500 return EmulateSUBSPcLrEtc (opcode, encoding);
5506 // Read the first operand.
5507 uint32_t val1 = ReadCoreReg(Rn, &success);
5511 uint32_t result = val1 & imm32;
5513 EmulateInstruction::Context context;
5514 context.type = EmulateInstruction::eContextImmediate;
5515 context.SetNoArgs ();
5517 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5523 // This instruction performs a bitwise AND of a register value and an optionally-shifted register value,
5524 // and writes the result to the destination register. It can optionally update the condition flags
5525 // based on the result.
5527 EmulateInstructionARM::EmulateANDReg (const uint32_t opcode, const ARMEncoding encoding)
5530 // ARM pseudo code...
5531 if ConditionPassed() then
5532 EncodingSpecificOperations();
5533 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
5534 result = R[n] AND shifted;
5535 if d == 15 then // Can only occur for ARM encoding
5536 ALUWritePC(result); // setflags is always FALSE here
5540 APSR.N = result<31>;
5541 APSR.Z = IsZeroBit(result);
5546 bool success = false;
5548 if (ConditionPassed(opcode))
5550 uint32_t Rd, Rn, Rm;
5551 ARM_ShifterType shift_t;
5552 uint32_t shift_n; // the shift applied to the value read from Rm
5558 Rd = Rn = Bits32(opcode, 2, 0);
5559 Rm = Bits32(opcode, 5, 3);
5560 setflags = !InITBlock();
5561 shift_t = SRType_LSL;
5565 Rd = Bits32(opcode, 11, 8);
5566 Rn = Bits32(opcode, 19, 16);
5567 Rm = Bits32(opcode, 3, 0);
5568 setflags = BitIsSet(opcode, 20);
5569 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5570 // if Rd == '1111' && S == '1' then SEE TST (register);
5571 if (Rd == 15 && setflags)
5572 return EmulateTSTReg(opcode, eEncodingT2);
5573 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
5577 Rd = Bits32(opcode, 15, 12);
5578 Rn = Bits32(opcode, 19, 16);
5579 Rm = Bits32(opcode, 3, 0);
5580 setflags = BitIsSet(opcode, 20);
5581 shift_n = DecodeImmShiftARM(opcode, shift_t);
5583 if (Rd == 15 && setflags)
5584 return EmulateSUBSPcLrEtc (opcode, encoding);
5590 // Read the first operand.
5591 uint32_t val1 = ReadCoreReg(Rn, &success);
5595 // Read the second operand.
5596 uint32_t val2 = ReadCoreReg(Rm, &success);
5600 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
5603 uint32_t result = val1 & shifted;
5605 EmulateInstruction::Context context;
5606 context.type = EmulateInstruction::eContextImmediate;
5607 context.SetNoArgs ();
5609 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5615 // Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an
5616 // immediate value, and writes the result to the destination register. It can optionally update the
5617 // condition flags based on the result.
5619 EmulateInstructionARM::EmulateBICImm (const uint32_t opcode, const ARMEncoding encoding)
5622 // ARM pseudo code...
5623 if ConditionPassed() then
5624 EncodingSpecificOperations();
5625 result = R[n] AND NOT(imm32);
5626 if d == 15 then // Can only occur for ARM encoding
5627 ALUWritePC(result); // setflags is always FALSE here
5631 APSR.N = result<31>;
5632 APSR.Z = IsZeroBit(result);
5637 bool success = false;
5639 if (ConditionPassed(opcode))
5642 uint32_t imm32; // the immediate value to be bitwise inverted and ANDed to the value obtained from Rn
5644 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
5648 Rd = Bits32(opcode, 11, 8);
5649 Rn = Bits32(opcode, 19, 16);
5650 setflags = BitIsSet(opcode, 20);
5651 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
5652 if (BadReg(Rd) || BadReg(Rn))
5656 Rd = Bits32(opcode, 15, 12);
5657 Rn = Bits32(opcode, 19, 16);
5658 setflags = BitIsSet(opcode, 20);
5659 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
5661 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5662 if (Rd == 15 && setflags)
5663 return EmulateSUBSPcLrEtc (opcode, encoding);
5669 // Read the first operand.
5670 uint32_t val1 = ReadCoreReg(Rn, &success);
5674 uint32_t result = val1 & ~imm32;
5676 EmulateInstruction::Context context;
5677 context.type = EmulateInstruction::eContextImmediate;
5678 context.SetNoArgs ();
5680 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5686 // Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an
5687 // optionally-shifted register value, and writes the result to the destination register.
5688 // It can optionally update the condition flags based on the result.
5690 EmulateInstructionARM::EmulateBICReg (const uint32_t opcode, const ARMEncoding encoding)
5693 // ARM pseudo code...
5694 if ConditionPassed() then
5695 EncodingSpecificOperations();
5696 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
5697 result = R[n] AND NOT(shifted);
5698 if d == 15 then // Can only occur for ARM encoding
5699 ALUWritePC(result); // setflags is always FALSE here
5703 APSR.N = result<31>;
5704 APSR.Z = IsZeroBit(result);
5709 bool success = false;
5711 if (ConditionPassed(opcode))
5713 uint32_t Rd, Rn, Rm;
5714 ARM_ShifterType shift_t;
5715 uint32_t shift_n; // the shift applied to the value read from Rm
5721 Rd = Rn = Bits32(opcode, 2, 0);
5722 Rm = Bits32(opcode, 5, 3);
5723 setflags = !InITBlock();
5724 shift_t = SRType_LSL;
5728 Rd = Bits32(opcode, 11, 8);
5729 Rn = Bits32(opcode, 19, 16);
5730 Rm = Bits32(opcode, 3, 0);
5731 setflags = BitIsSet(opcode, 20);
5732 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5733 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5737 Rd = Bits32(opcode, 15, 12);
5738 Rn = Bits32(opcode, 19, 16);
5739 Rm = Bits32(opcode, 3, 0);
5740 setflags = BitIsSet(opcode, 20);
5741 shift_n = DecodeImmShiftARM(opcode, shift_t);
5743 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
5744 if (Rd == 15 && setflags)
5745 return EmulateSUBSPcLrEtc (opcode, encoding);
5751 // Read the first operand.
5752 uint32_t val1 = ReadCoreReg(Rn, &success);
5756 // Read the second operand.
5757 uint32_t val2 = ReadCoreReg(Rm, &success);
5761 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
5764 uint32_t result = val1 & ~shifted;
5766 EmulateInstruction::Context context;
5767 context.type = EmulateInstruction::eContextImmediate;
5768 context.SetNoArgs ();
5770 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
5776 // LDR (immediate, ARM) calculates an address from a base register value and an immediate offset, loads a word
5777 // from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing.
5779 EmulateInstructionARM::EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding)
5782 if ConditionPassed() then
5783 EncodingSpecificOperations();
5784 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5785 address = if index then offset_addr else R[n];
5786 data = MemU[address,4];
5787 if wback then R[n] = offset_addr;
5789 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5790 elsif UnalignedSupport() || address<1:0> = '00' then
5792 else // Can only apply before ARMv7
5793 R[t] = ROR(data, 8*UInt(address<1:0>));
5796 bool success = false;
5798 if (ConditionPassed(opcode))
5800 const uint32_t addr_byte_size = GetAddressByteSize();
5812 // if Rn == '1111' then SEE LDR (literal);
5813 // if P == '0' && W == '1' then SEE LDRT;
5814 // if Rn == '1101' && P == '0' && U == '1' && W == '0' && imm12 == '000000000100' then SEE POP;
5815 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
5816 t = Bits32 (opcode, 15, 12);
5817 n = Bits32 (opcode, 19, 16);
5818 imm32 = Bits32 (opcode, 11, 0);
5820 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
5821 index = BitIsSet (opcode, 24);
5822 add = BitIsSet (opcode, 23);
5823 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
5825 // if wback && n == t then UNPREDICTABLE;
5826 if (wback && (n == t))
5837 addr_t base_address = ReadCoreReg (n, &success);
5841 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
5843 offset_addr = base_address + imm32;
5845 offset_addr = base_address - imm32;
5847 // address = if index then offset_addr else R[n];
5849 address = offset_addr;
5851 address = base_address;
5853 // data = MemU[address,4];
5855 RegisterInfo base_reg;
5856 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
5858 EmulateInstruction::Context context;
5859 context.type = eContextRegisterLoad;
5860 context.SetRegisterPlusOffset (base_reg, address - base_address);
5862 uint64_t data = MemURead (context, address, addr_byte_size, 0, &success);
5866 // if wback then R[n] = offset_addr;
5869 context.type = eContextAdjustBaseRegister;
5870 context.SetAddress (offset_addr);
5871 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
5878 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5879 if (BitIsClear (address, 1) && BitIsClear (address, 0))
5881 // LoadWritePC (data);
5882 context.type = eContextRegisterLoad;
5883 context.SetRegisterPlusOffset (base_reg, address - base_address);
5884 LoadWritePC (context, data);
5889 // elsif UnalignedSupport() || address<1:0> = '00' then
5890 else if (UnalignedSupport() || (BitIsClear (address, 1) && BitIsClear (address, 0)))
5893 context.type = eContextRegisterLoad;
5894 context.SetRegisterPlusOffset (base_reg, address - base_address);
5895 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
5898 // else // Can only apply before ARMv7
5901 // R[t] = ROR(data, 8*UInt(address<1:0>));
5902 data = ROR (data, Bits32 (address, 1, 0), &success);
5905 context.type = eContextRegisterLoad;
5906 context.SetImmediate (data);
5907 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
5915 // LDR (register) calculates an address from a base register value and an offset register value, loads a word
5916 // from memory, and writes it to a resgister. The offset register value can optionally be shifted.
5918 EmulateInstructionARM::EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding)
5921 if ConditionPassed() then
5922 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
5923 offset = Shift(R[m], shift_t, shift_n, APSR.C);
5924 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
5925 address = if index then offset_addr else R[n];
5926 data = MemU[address,4];
5927 if wback then R[n] = offset_addr;
5929 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
5930 elsif UnalignedSupport() || address<1:0> = '00' then
5932 else // Can only apply before ARMv7
5933 if CurrentInstrSet() == InstrSet_ARM then
5934 R[t] = ROR(data, 8*UInt(address<1:0>));
5936 R[t] = bits(32) UNKNOWN;
5939 bool success = false;
5941 if (ConditionPassed(opcode))
5943 const uint32_t addr_byte_size = GetAddressByteSize();
5951 ARM_ShifterType shift_t;
5957 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
5958 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5959 t = Bits32 (opcode, 2, 0);
5960 n = Bits32 (opcode, 5, 3);
5961 m = Bits32 (opcode, 8, 6);
5963 // index = TRUE; add = TRUE; wback = FALSE;
5968 // (shift_t, shift_n) = (SRType_LSL, 0);
5969 shift_t = SRType_LSL;
5975 // if Rn == '1111' then SEE LDR (literal);
5976 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5977 t = Bits32 (opcode, 15, 12);
5978 n = Bits32 (opcode, 19, 16);
5979 m = Bits32 (opcode, 3, 0);
5981 // index = TRUE; add = TRUE; wback = FALSE;
5986 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
5987 shift_t = SRType_LSL;
5988 shift_n = Bits32 (opcode, 5, 4);
5990 // if BadReg(m) then UNPREDICTABLE;
5994 // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
5995 if ((t == 15) && InITBlock() && !LastInITBlock())
6002 // if P == '0' && W == '1' then SEE LDRT;
6003 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6004 t = Bits32 (opcode, 15, 12);
6005 n = Bits32 (opcode, 19, 16);
6006 m = Bits32 (opcode, 3, 0);
6008 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
6009 index = BitIsSet (opcode, 24);
6010 add = BitIsSet (opcode, 23);
6011 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6013 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
6014 uint32_t type = Bits32 (opcode, 6, 5);
6015 uint32_t imm5 = Bits32 (opcode, 11, 7);
6016 shift_n = DecodeImmShift (type, imm5, shift_t);
6018 // if m == 15 then UNPREDICTABLE;
6022 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6023 if (wback && ((n == 15) || (n == t)))
6033 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6037 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6044 // offset = Shift(R[m], shift_t, shift_n, APSR.C); -- Note "The APSR is an application level alias for the CPSR".
6045 addr_t offset = Shift (Rm, shift_t, shift_n, Bit32 (m_opcode_cpsr, APSR_C), &success);
6049 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6051 offset_addr = Rn + offset;
6053 offset_addr = Rn - offset;
6055 // address = if index then offset_addr else R[n];
6057 address = offset_addr;
6061 // data = MemU[address,4];
6062 RegisterInfo base_reg;
6063 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6065 EmulateInstruction::Context context;
6066 context.type = eContextRegisterLoad;
6067 context.SetRegisterPlusOffset (base_reg, address - Rn);
6069 uint64_t data = MemURead (context, address, addr_byte_size, 0, &success);
6073 // if wback then R[n] = offset_addr;
6076 context.type = eContextAdjustBaseRegister;
6077 context.SetAddress (offset_addr);
6078 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6085 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
6086 if (BitIsClear (address, 1) && BitIsClear (address, 0))
6088 context.type = eContextRegisterLoad;
6089 context.SetRegisterPlusOffset (base_reg, address - Rn);
6090 LoadWritePC (context, data);
6095 // elsif UnalignedSupport() || address<1:0> = '00' then
6096 else if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)))
6099 context.type = eContextRegisterLoad;
6100 context.SetRegisterPlusOffset (base_reg, address - Rn);
6101 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6104 else // Can only apply before ARMv7
6106 // if CurrentInstrSet() == InstrSet_ARM then
6107 if (CurrentInstrSet () == eModeARM)
6109 // R[t] = ROR(data, 8*UInt(address<1:0>));
6110 data = ROR (data, Bits32 (address, 1, 0), &success);
6113 context.type = eContextRegisterLoad;
6114 context.SetImmediate (data);
6115 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6120 // R[t] = bits(32) UNKNOWN;
6121 WriteBits32Unknown (t);
6128 // LDRB (immediate, Thumb)
6130 EmulateInstructionARM::EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding)
6133 if ConditionPassed() then
6134 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6135 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6136 address = if index then offset_addr else R[n];
6137 R[t] = ZeroExtend(MemU[address,1], 32);
6138 if wback then R[n] = offset_addr;
6141 bool success = false;
6143 if (ConditionPassed(opcode))
6152 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6156 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
6157 t = Bits32 (opcode, 2, 0);
6158 n = Bits32 (opcode, 5, 3);
6159 imm32 = Bits32 (opcode, 10, 6);
6161 // index = TRUE; add = TRUE; wback = FALSE;
6169 // if Rt == '1111' then SEE PLD;
6170 // if Rn == '1111' then SEE LDRB (literal);
6171 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6172 t = Bits32 (opcode, 15, 12);
6173 n = Bits32 (opcode, 19, 16);
6174 imm32 = Bits32 (opcode, 11, 0);
6176 // index = TRUE; add = TRUE; wback = FALSE;
6181 // if t == 13 then UNPREDICTABLE;
6188 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD;
6189 // if Rn == '1111' then SEE LDRB (literal);
6190 // if P == '1' && U == '1' && W == '0' then SEE LDRBT;
6191 // if P == '0' && W == '0' then UNDEFINED;
6192 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
6195 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6196 t = Bits32 (opcode, 15, 12);
6197 n = Bits32 (opcode, 19, 16);
6198 imm32 = Bits32 (opcode, 7, 0);
6200 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
6201 index = BitIsSet (opcode, 10);
6202 add = BitIsSet (opcode, 9);
6203 wback = BitIsSet (opcode, 8);
6205 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
6206 if (BadReg (t) || (wback && (n == t)))
6215 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6222 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6224 offset_addr = Rn + imm32;
6226 offset_addr = Rn - imm32;
6228 // address = if index then offset_addr else R[n];
6230 address = offset_addr;
6234 // R[t] = ZeroExtend(MemU[address,1], 32);
6235 RegisterInfo base_reg;
6236 RegisterInfo data_reg;
6237 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6238 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
6240 EmulateInstruction::Context context;
6241 context.type = eContextRegisterLoad;
6242 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
6244 uint64_t data = MemURead (context, address, 1, 0, &success);
6248 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6251 // if wback then R[n] = offset_addr;
6254 context.type = eContextAdjustBaseRegister;
6255 context.SetAddress (offset_addr);
6256 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6263 // LDRB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
6264 // zero-extends it to form a 32-bit word and writes it to a register.
6266 EmulateInstructionARM::EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding)
6269 if ConditionPassed() then
6270 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
6272 address = if add then (base + imm32) else (base - imm32);
6273 R[t] = ZeroExtend(MemU[address,1], 32);
6276 bool success = false;
6278 if (ConditionPassed(opcode))
6286 // if Rt == '1111' then SEE PLD;
6287 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6288 t = Bits32 (opcode, 15, 12);
6289 imm32 = Bits32 (opcode, 11, 0);
6290 add = BitIsSet (opcode, 23);
6292 // if t == 13 then UNPREDICTABLE;
6299 // t == UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6300 t = Bits32 (opcode, 15, 12);
6301 imm32 = Bits32 (opcode, 11, 0);
6302 add = BitIsSet (opcode, 23);
6304 // if t == 15 then UNPREDICTABLE;
6313 // base = Align(PC,4);
6314 uint32_t pc_val = ReadCoreReg (PC_REG, &success);
6318 uint32_t base = AlignPC (pc_val);
6321 // address = if add then (base + imm32) else (base - imm32);
6323 address = base + imm32;
6325 address = base - imm32;
6327 // R[t] = ZeroExtend(MemU[address,1], 32);
6328 EmulateInstruction::Context context;
6329 context.type = eContextRelativeBranchImmediate;
6330 context.SetImmediate (address - base);
6332 uint64_t data = MemURead (context, address, 1, 0, &success);
6336 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6342 // LDRB (register) calculates an address from a base register value and an offset rigister value, loads a byte from
6343 // memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can
6344 // optionally be shifted.
6346 EmulateInstructionARM::EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding)
6349 if ConditionPassed() then
6350 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6351 offset = Shift(R[m], shift_t, shift_n, APSR.C);
6352 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6353 address = if index then offset_addr else R[n];
6354 R[t] = ZeroExtend(MemU[address,1],32);
6355 if wback then R[n] = offset_addr;
6358 bool success = false;
6360 if (ConditionPassed(opcode))
6368 ARM_ShifterType shift_t;
6371 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6375 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6376 t = Bits32 (opcode, 2, 0);
6377 n = Bits32 (opcode, 5, 3);
6378 m = Bits32 (opcode, 8, 6);
6380 // index = TRUE; add = TRUE; wback = FALSE;
6385 // (shift_t, shift_n) = (SRType_LSL, 0);
6386 shift_t = SRType_LSL;
6391 // if Rt == '1111' then SEE PLD;
6392 // if Rn == '1111' then SEE LDRB (literal);
6393 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6394 t = Bits32 (opcode, 15, 12);
6395 n = Bits32 (opcode, 19, 16);
6396 m = Bits32 (opcode, 3, 0);
6398 // index = TRUE; add = TRUE; wback = FALSE;
6403 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
6404 shift_t = SRType_LSL;
6405 shift_n = Bits32 (opcode, 5, 4);
6407 // if t == 13 || BadReg(m) then UNPREDICTABLE;
6408 if ((t == 13) || BadReg (m))
6414 // if P == '0' && W == '1' then SEE LDRBT;
6415 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6416 t = Bits32 (opcode, 15, 12);
6417 n = Bits32 (opcode, 19, 16);
6418 m = Bits32 (opcode, 3, 0);
6420 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
6421 index = BitIsSet (opcode, 24);
6422 add = BitIsSet (opcode, 23);
6423 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6425 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
6426 uint32_t type = Bits32 (opcode, 6, 5);
6427 uint32_t imm5 = Bits32 (opcode, 11, 7);
6428 shift_n = DecodeImmShift (type, imm5, shift_t);
6430 // if t == 15 || m == 15 then UNPREDICTABLE;
6431 if ((t == 15) || (m == 15))
6434 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6435 if (wback && ((n == 15) || (n == t)))
6447 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
6448 uint32_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6452 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
6456 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6457 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6462 offset_addr = Rn + offset;
6464 offset_addr = Rn - offset;
6466 // address = if index then offset_addr else R[n];
6468 address = offset_addr;
6472 // R[t] = ZeroExtend(MemU[address,1],32);
6473 RegisterInfo base_reg;
6474 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6476 EmulateInstruction::Context context;
6477 context.type = eContextRegisterLoad;
6478 context.SetRegisterPlusOffset (base_reg, address - Rn);
6480 uint64_t data = MemURead (context, address, 1, 0, &success);
6484 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6487 // if wback then R[n] = offset_addr;
6490 context.type = eContextAdjustBaseRegister;
6491 context.SetAddress (offset_addr);
6492 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6499 // LDRH (immediate, Thumb) calculates an address from a base register value and an immediate offset, loads a
6500 // halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset,
6501 // post-indexed, or pre-indexed addressing.
6503 EmulateInstructionARM::EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding)
6506 if ConditionPassed() then
6507 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6508 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6509 address = if index then offset_addr else R[n];
6510 data = MemU[address,2];
6511 if wback then R[n] = offset_addr;
6512 if UnalignedSupport() || address<0> = '0' then
6513 R[t] = ZeroExtend(data, 32);
6514 else // Can only apply before ARMv7
6515 R[t] = bits(32) UNKNOWN;
6519 bool success = false;
6521 if (ConditionPassed(opcode))
6530 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6534 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32);
6535 t = Bits32 (opcode, 2, 0);
6536 n = Bits32 (opcode, 5, 3);
6537 imm32 = Bits32 (opcode, 10, 6) << 1;
6539 // index = TRUE; add = TRUE; wback = FALSE;
6547 // if Rt == '1111' then SEE "Unallocated memory hints";
6548 // if Rn == '1111' then SEE LDRH (literal);
6549 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6550 t = Bits32 (opcode, 15, 12);
6551 n = Bits32 (opcode, 19, 16);
6552 imm32 = Bits32 (opcode, 11, 0);
6554 // index = TRUE; add = TRUE; wback = FALSE;
6559 // if t == 13 then UNPREDICTABLE;
6565 // if Rn == '1111' then SEE LDRH (literal);
6566 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints";
6567 // if P == '1' && U == '1' && W == '0' then SEE LDRHT;
6568 // if P == '0' && W == '0' then UNDEFINED;
6569 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
6572 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6573 t = Bits32 (opcode, 15, 12);
6574 n = Bits32 (opcode, 19, 16);
6575 imm32 = Bits32 (opcode, 7, 0);
6577 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
6578 index = BitIsSet (opcode, 10);
6579 add = BitIsSet (opcode, 9);
6580 wback = BitIsSet (opcode, 8);
6582 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
6583 if (BadReg (t) || (wback && (n == t)))
6591 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6592 uint32_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6600 offset_addr = Rn + imm32;
6602 offset_addr = Rn - imm32;
6604 // address = if index then offset_addr else R[n];
6606 address = offset_addr;
6610 // data = MemU[address,2];
6611 RegisterInfo base_reg;
6612 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6614 EmulateInstruction::Context context;
6615 context.type = eContextRegisterLoad;
6616 context.SetRegisterPlusOffset (base_reg, address - Rn);
6618 uint64_t data = MemURead (context, address, 2, 0, &success);
6622 // if wback then R[n] = offset_addr;
6625 context.type = eContextAdjustBaseRegister;
6626 context.SetAddress (offset_addr);
6627 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6631 // if UnalignedSupport() || address<0> = '0' then
6632 if (UnalignedSupport () || BitIsClear (address, 0))
6634 // R[t] = ZeroExtend(data, 32);
6635 context.type = eContextRegisterLoad;
6636 context.SetRegisterPlusOffset (base_reg, address - Rn);
6637 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6640 else // Can only apply before ARMv7
6642 // R[t] = bits(32) UNKNOWN;
6643 WriteBits32Unknown (t);
6649 // LDRH (literal) caculates an address from the PC value and an immediate offset, loads a halfword from memory,
6650 // zero-extends it to form a 32-bit word, and writes it to a register.
6652 EmulateInstructionARM::EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding)
6655 if ConditionPassed() then
6656 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
6658 address = if add then (base + imm32) else (base - imm32);
6659 data = MemU[address,2];
6660 if UnalignedSupport() || address<0> = '0' then
6661 R[t] = ZeroExtend(data, 32);
6662 else // Can only apply before ARMv7
6663 R[t] = bits(32) UNKNOWN;
6666 bool success = false;
6668 if (ConditionPassed(opcode))
6674 // EncodingSpecificOperations(); NullCheckIfThumbEE(15);
6678 // if Rt == '1111' then SEE "Unallocated memory hints";
6679 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
6680 t = Bits32 (opcode, 15, 12);
6681 imm32 = Bits32 (opcode, 11, 0);
6682 add = BitIsSet (opcode, 23);
6684 // if t == 13 then UNPREDICTABLE;
6692 uint32_t imm4H = Bits32 (opcode, 11, 8);
6693 uint32_t imm4L = Bits32 (opcode, 3, 0);
6695 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
6696 t = Bits32 (opcode, 15, 12);
6697 imm32 = (imm4H << 4) | imm4L;
6698 add = BitIsSet (opcode, 23);
6700 // if t == 15 then UNPREDICTABLE;
6710 // base = Align(PC,4);
6711 uint64_t pc_value = ReadCoreReg (PC_REG, &success);
6715 addr_t base = AlignPC (pc_value);
6718 // address = if add then (base + imm32) else (base - imm32);
6720 address = base + imm32;
6722 address = base - imm32;
6724 // data = MemU[address,2];
6725 RegisterInfo base_reg;
6726 GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
6728 EmulateInstruction::Context context;
6729 context.type = eContextRegisterLoad;
6730 context.SetRegisterPlusOffset (base_reg, address - base);
6732 uint64_t data = MemURead (context, address, 2, 0, &success);
6737 // if UnalignedSupport() || address<0> = '0' then
6738 if (UnalignedSupport () || BitIsClear (address, 0))
6740 // R[t] = ZeroExtend(data, 32);
6741 context.type = eContextRegisterLoad;
6742 context.SetRegisterPlusOffset (base_reg, address - base);
6743 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6747 else // Can only apply before ARMv7
6749 // R[t] = bits(32) UNKNOWN;
6750 WriteBits32Unknown (t);
6756 // LDRH (literal) calculates an address from a base register value and an offset register value, loads a halfword
6757 // from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can
6758 // be shifted left by 0, 1, 2, or 3 bits.
6760 EmulateInstructionARM::EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding)
6763 if ConditionPassed() then
6764 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6765 offset = Shift(R[m], shift_t, shift_n, APSR.C);
6766 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6767 address = if index then offset_addr else R[n];
6768 data = MemU[address,2];
6769 if wback then R[n] = offset_addr;
6770 if UnalignedSupport() || address<0> = '0' then
6771 R[t] = ZeroExtend(data, 32);
6772 else // Can only apply before ARMv7
6773 R[t] = bits(32) UNKNOWN;
6776 bool success = false;
6778 if (ConditionPassed(opcode))
6786 ARM_ShifterType shift_t;
6789 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6793 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
6794 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6795 t = Bits32 (opcode, 2, 0);
6796 n = Bits32 (opcode, 5, 3);
6797 m = Bits32 (opcode, 8, 6);
6799 // index = TRUE; add = TRUE; wback = FALSE;
6804 // (shift_t, shift_n) = (SRType_LSL, 0);
6805 shift_t = SRType_LSL;
6811 // if Rn == '1111' then SEE LDRH (literal);
6812 // if Rt == '1111' then SEE "Unallocated memory hints";
6813 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6814 t = Bits32 (opcode, 15, 12);
6815 n = Bits32 (opcode, 19, 16);
6816 m = Bits32 (opcode, 3, 0);
6818 // index = TRUE; add = TRUE; wback = FALSE;
6823 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
6824 shift_t = SRType_LSL;
6825 shift_n = Bits32 (opcode, 5, 4);
6827 // if t == 13 || BadReg(m) then UNPREDICTABLE;
6828 if ((t == 13) || BadReg (m))
6833 // if P == '0' && W == '1' then SEE LDRHT;
6834 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6835 t = Bits32 (opcode, 15, 12);
6836 n = Bits32 (opcode, 19, 16);
6837 m = Bits32 (opcode, 3, 0);
6839 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
6840 index = BitIsSet (opcode, 24);
6841 add = BitIsSet (opcode, 23);
6842 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
6844 // (shift_t, shift_n) = (SRType_LSL, 0);
6845 shift_t = SRType_LSL;
6848 // if t == 15 || m == 15 then UNPREDICTABLE;
6849 if ((t == 15) || (m == 15))
6852 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
6853 if (wback && ((n == 15) || (n == t)))
6862 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
6864 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6868 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
6875 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
6876 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6881 offset_addr = Rn + offset;
6883 offset_addr = Rn - offset;
6885 // address = if index then offset_addr else R[n];
6887 address = offset_addr;
6891 // data = MemU[address,2];
6892 RegisterInfo base_reg;
6893 RegisterInfo offset_reg;
6894 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
6895 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
6897 EmulateInstruction::Context context;
6898 context.type = eContextRegisterLoad;
6899 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
6900 uint64_t data = MemURead (context, address, 2, 0, &success);
6904 // if wback then R[n] = offset_addr;
6907 context.type = eContextAdjustBaseRegister;
6908 context.SetAddress (offset_addr);
6909 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
6913 // if UnalignedSupport() || address<0> = '0' then
6914 if (UnalignedSupport() || BitIsClear (address, 0))
6916 // R[t] = ZeroExtend(data, 32);
6917 context.type = eContextRegisterLoad;
6918 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
6919 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
6922 else // Can only apply before ARMv7
6924 // R[t] = bits(32) UNKNOWN;
6925 WriteBits32Unknown (t);
6931 // LDRSB (immediate) calculates an address from a base register value and an immediate offset, loads a byte from
6932 // memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed,
6933 // or pre-indexed addressing.
6935 EmulateInstructionARM::EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding)
6938 if ConditionPassed() then
6939 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6940 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
6941 address = if index then offset_addr else R[n];
6942 R[t] = SignExtend(MemU[address,1], 32);
6943 if wback then R[n] = offset_addr;
6946 bool success = false;
6948 if (ConditionPassed(opcode))
6957 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
6961 // if Rt == '1111' then SEE PLI;
6962 // if Rn == '1111' then SEE LDRSB (literal);
6963 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
6964 t = Bits32 (opcode, 15, 12);
6965 n = Bits32 (opcode, 19, 16);
6966 imm32 = Bits32 (opcode, 11, 0);
6968 // index = TRUE; add = TRUE; wback = FALSE;
6973 // if t == 13 then UNPREDICTABLE;
6980 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLI;
6981 // if Rn == '1111' then SEE LDRSB (literal);
6982 // if P == '1' && U == '1' && W == '0' then SEE LDRSBT;
6983 // if P == '0' && W == '0' then UNDEFINED;
6984 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
6987 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
6988 t = Bits32 (opcode, 15, 12);
6989 n = Bits32 (opcode, 19, 16);
6990 imm32 = Bits32 (opcode, 7, 0);
6992 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
6993 index = BitIsSet (opcode, 10);
6994 add = BitIsSet (opcode, 9);
6995 wback = BitIsSet (opcode, 8);
6997 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
6998 if (((t == 13) || ((t == 15)
6999 && (BitIsClear (opcode, 10) || BitIsSet (opcode, 9) || BitIsSet (opcode, 8))))
7000 || (wback && (n == t)))
7007 // if Rn == '1111' then SEE LDRSB (literal);
7008 // if P == '0' && W == '1' then SEE LDRSBT;
7009 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7010 t = Bits32 (opcode, 15, 12);
7011 n = Bits32 (opcode, 19, 16);
7013 uint32_t imm4H = Bits32 (opcode, 11, 8);
7014 uint32_t imm4L = Bits32 (opcode, 3, 0);
7015 imm32 = (imm4H << 4) | imm4L;
7017 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
7018 index = BitIsSet (opcode, 24);
7019 add = BitIsSet (opcode, 23);
7020 wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));
7022 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
7023 if ((t == 15) || (wback && (n == t)))
7033 uint64_t Rn = ReadCoreReg (n, &success);
7040 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7042 offset_addr = Rn + imm32;
7044 offset_addr = Rn - imm32;
7046 // address = if index then offset_addr else R[n];
7048 address = offset_addr;
7052 // R[t] = SignExtend(MemU[address,1], 32);
7053 RegisterInfo base_reg;
7054 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
7056 EmulateInstruction::Context context;
7057 context.type = eContextRegisterLoad;
7058 context.SetRegisterPlusOffset (base_reg, address - Rn);
7060 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7064 int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
7065 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7068 // if wback then R[n] = offset_addr;
7071 context.type = eContextAdjustBaseRegister;
7072 context.SetAddress (offset_addr);
7073 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
7081 // LDRSB (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory,
7082 // sign-extends it to form a 32-bit word, and writes tit to a register.
7084 EmulateInstructionARM::EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding)
7087 if ConditionPassed() then
7088 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
7090 address = if add then (base + imm32) else (base - imm32);
7091 R[t] = SignExtend(MemU[address,1], 32);
7094 bool success = false;
7096 if (ConditionPassed(opcode))
7102 // EncodingSpecificOperations(); NullCheckIfThumbEE(15);
7106 // if Rt == '1111' then SEE PLI;
7107 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7108 t = Bits32 (opcode, 15, 12);
7109 imm32 = Bits32 (opcode, 11, 0);
7110 add = BitIsSet (opcode, 23);
7112 // if t == 13 then UNPREDICTABLE;
7120 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
7121 t = Bits32 (opcode, 15, 12);
7122 uint32_t imm4H = Bits32 (opcode, 11, 8);
7123 uint32_t imm4L = Bits32 (opcode, 3, 0);
7124 imm32 = (imm4H << 4) | imm4L;
7125 add = BitIsSet (opcode, 23);
7127 // if t == 15 then UNPREDICTABLE;
7138 // base = Align(PC,4);
7139 uint64_t pc_value = ReadCoreReg (PC_REG, &success);
7142 uint64_t base = AlignPC (pc_value);
7144 // address = if add then (base + imm32) else (base - imm32);
7147 address = base + imm32;
7149 address = base - imm32;
7151 // R[t] = SignExtend(MemU[address,1], 32);
7152 RegisterInfo base_reg;
7153 GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
7155 EmulateInstruction::Context context;
7156 context.type = eContextRegisterLoad;
7157 context.SetRegisterPlusOffset (base_reg, address - base);
7159 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7163 int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
7164 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7170 // LDRSB (register) calculates an address from a base register value and an offset register value, loadsa byte from
7171 // memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be
7172 // shifted left by 0, 1, 2, or 3 bits.
7174 EmulateInstructionARM::EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding)
7177 if ConditionPassed() then
7178 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7179 offset = Shift(R[m], shift_t, shift_n, APSR.C);
7180 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7181 address = if index then offset_addr else R[n];
7182 R[t] = SignExtend(MemU[address,1], 32);
7183 if wback then R[n] = offset_addr;
7186 bool success = false;
7188 if (ConditionPassed(opcode))
7196 ARM_ShifterType shift_t;
7199 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7203 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7204 t = Bits32 (opcode, 2, 0);
7205 n = Bits32 (opcode, 5, 3);
7206 m = Bits32 (opcode, 8, 6);
7208 // index = TRUE; add = TRUE; wback = FALSE;
7213 // (shift_t, shift_n) = (SRType_LSL, 0);
7214 shift_t = SRType_LSL;
7220 // if Rt == '1111' then SEE PLI;
7221 // if Rn == '1111' then SEE LDRSB (literal);
7222 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7223 t = Bits32 (opcode, 15, 12);
7224 n = Bits32 (opcode, 19, 16);
7225 m = Bits32 (opcode, 3, 0);
7227 // index = TRUE; add = TRUE; wback = FALSE;
7232 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
7233 shift_t = SRType_LSL;
7234 shift_n = Bits32 (opcode, 5, 4);
7236 // if t == 13 || BadReg(m) then UNPREDICTABLE;
7237 if ((t == 13) || BadReg (m))
7242 // if P == '0' && W == '1' then SEE LDRSBT;
7243 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7244 t = Bits32 (opcode, 15, 12);
7245 n = Bits32 (opcode, 19, 16);
7246 m = Bits32 (opcode, 3, 0);
7248 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
7249 index = BitIsSet (opcode, 24);
7250 add = BitIsSet (opcode, 23);
7251 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7253 // (shift_t, shift_n) = (SRType_LSL, 0);
7254 shift_t = SRType_LSL;
7257 // if t == 15 || m == 15 then UNPREDICTABLE;
7258 if ((t == 15) || (m == 15))
7261 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
7262 if (wback && ((n == 15) || (n == t)))
7270 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7274 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
7275 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
7282 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7283 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7288 offset_addr = Rn + offset;
7290 offset_addr = Rn - offset;
7292 // address = if index then offset_addr else R[n];
7294 address = offset_addr;
7298 // R[t] = SignExtend(MemU[address,1], 32);
7299 RegisterInfo base_reg;
7300 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
7301 RegisterInfo offset_reg;
7302 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
7304 EmulateInstruction::Context context;
7305 context.type = eContextRegisterLoad;
7306 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
7308 uint64_t unsigned_data = MemURead (context, address, 1, 0, &success);
7312 int64_t signed_data = llvm::SignExtend64<8>(unsigned_data);
7313 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7316 // if wback then R[n] = offset_addr;
7319 context.type = eContextAdjustBaseRegister;
7320 context.SetAddress (offset_addr);
7321 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
7328 // LDRSH (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from
7329 // memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or
7330 // pre-indexed addressing.
7332 EmulateInstructionARM::EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding)
7335 if ConditionPassed() then
7336 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7337 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7338 address = if index then offset_addr else R[n];
7339 data = MemU[address,2];
7340 if wback then R[n] = offset_addr;
7341 if UnalignedSupport() || address<0> = '0' then
7342 R[t] = SignExtend(data, 32);
7343 else // Can only apply before ARMv7
7344 R[t] = bits(32) UNKNOWN;
7347 bool success = false;
7349 if (ConditionPassed(opcode))
7358 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7362 // if Rn == '1111' then SEE LDRSH (literal);
7363 // if Rt == '1111' then SEE "Unallocated memory hints";
7364 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
7365 t = Bits32 (opcode, 15, 12);
7366 n = Bits32 (opcode, 19, 16);
7367 imm32 = Bits32 (opcode, 11, 0);
7369 // index = TRUE; add = TRUE; wback = FALSE;
7374 // if t == 13 then UNPREDICTABLE;
7381 // if Rn == '1111' then SEE LDRSH (literal);
7382 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE "Unallocated memory hints";
7383 // if P == '1' && U == '1' && W == '0' then SEE LDRSHT;
7384 // if P == '0' && W == '0' then UNDEFINED;
7385 if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
7388 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7389 t = Bits32 (opcode, 15, 12);
7390 n = Bits32 (opcode, 19, 16);
7391 imm32 = Bits32 (opcode, 7, 0);
7393 // index = (P == '1'); add = (U == '1'); wback = (W == '1');
7394 index = BitIsSet (opcode, 10);
7395 add = BitIsSet (opcode, 9);
7396 wback = BitIsSet (opcode, 8);
7398 // if BadReg(t) || (wback && n == t) then UNPREDICTABLE;
7399 if (BadReg (t) || (wback && (n == t)))
7406 // if Rn == '1111' then SEE LDRSH (literal);
7407 // if P == '0' && W == '1' then SEE LDRSHT;
7408 // t == UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
7409 t = Bits32 (opcode, 15, 12);
7410 n = Bits32 (opcode, 19, 16);
7411 uint32_t imm4H = Bits32 (opcode, 11,8);
7412 uint32_t imm4L = Bits32 (opcode, 3, 0);
7413 imm32 = (imm4H << 4) | imm4L;
7415 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
7416 index = BitIsSet (opcode, 24);
7417 add = BitIsSet (opcode, 23);
7418 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7420 // if t == 15 || (wback && n == t) then UNPREDICTABLE;
7421 if ((t == 15) || (wback && (n == t)))
7431 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
7432 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7438 offset_addr = Rn + imm32;
7440 offset_addr = Rn - imm32;
7442 // address = if index then offset_addr else R[n];
7445 address = offset_addr;
7449 // data = MemU[address,2];
7450 RegisterInfo base_reg;
7451 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
7453 EmulateInstruction::Context context;
7454 context.type = eContextRegisterLoad;
7455 context.SetRegisterPlusOffset (base_reg, address - Rn);
7457 uint64_t data = MemURead (context, address, 2, 0, &success);
7461 // if wback then R[n] = offset_addr;
7464 context.type = eContextAdjustBaseRegister;
7465 context.SetAddress (offset_addr);
7466 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
7470 // if UnalignedSupport() || address<0> = '0' then
7471 if (UnalignedSupport() || BitIsClear (address, 0))
7473 // R[t] = SignExtend(data, 32);
7474 int64_t signed_data = llvm::SignExtend64<16>(data);
7475 context.type = eContextRegisterLoad;
7476 context.SetRegisterPlusOffset (base_reg, address - Rn);
7477 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7480 else // Can only apply before ARMv7
7482 // R[t] = bits(32) UNKNOWN;
7483 WriteBits32Unknown (t);
7489 // LDRSH (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory,
7490 // sign-extends it to from a 32-bit word, and writes it to a register.
7492 EmulateInstructionARM::EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding)
7495 if ConditionPassed() then
7496 EncodingSpecificOperations(); NullCheckIfThumbEE(15);
7498 address = if add then (base + imm32) else (base - imm32);
7499 data = MemU[address,2];
7500 if UnalignedSupport() || address<0> = '0' then
7501 R[t] = SignExtend(data, 32);
7502 else // Can only apply before ARMv7
7503 R[t] = bits(32) UNKNOWN;
7506 bool success = false;
7508 if (ConditionPassed(opcode))
7514 // EncodingSpecificOperations(); NullCheckIfThumbEE(15);
7518 // if Rt == '1111' then SEE "Unallocated memory hints";
7519 // t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == '1');
7520 t = Bits32 (opcode, 15, 12);
7521 imm32 = Bits32 (opcode, 11, 0);
7522 add = BitIsSet (opcode, 23);
7524 // if t == 13 then UNPREDICTABLE;
7532 // t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == '1');
7533 t = Bits32 (opcode, 15, 12);
7534 uint32_t imm4H = Bits32 (opcode, 11, 8);
7535 uint32_t imm4L = Bits32 (opcode, 3, 0);
7536 imm32 = (imm4H << 4) | imm4L;
7537 add = BitIsSet (opcode, 23);
7539 // if t == 15 then UNPREDICTABLE;
7549 // base = Align(PC,4);
7550 uint64_t pc_value = ReadCoreReg (PC_REG, &success);
7554 uint64_t base = AlignPC (pc_value);
7557 // address = if add then (base + imm32) else (base - imm32);
7559 address = base + imm32;
7561 address = base - imm32;
7563 // data = MemU[address,2];
7564 RegisterInfo base_reg;
7565 GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, base_reg);
7567 EmulateInstruction::Context context;
7568 context.type = eContextRegisterLoad;
7569 context.SetRegisterPlusOffset (base_reg, imm32);
7571 uint64_t data = MemURead (context, address, 2, 0, &success);
7575 // if UnalignedSupport() || address<0> = '0' then
7576 if (UnalignedSupport() || BitIsClear (address, 0))
7578 // R[t] = SignExtend(data, 32);
7579 int64_t signed_data = llvm::SignExtend64<16>(data);
7580 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7583 else // Can only apply before ARMv7
7585 // R[t] = bits(32) UNKNOWN;
7586 WriteBits32Unknown (t);
7592 // LDRSH (register) calculates an address from a base register value and an offset register value, loads a halfword
7593 // from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be
7594 // shifted left by 0, 1, 2, or 3 bits.
7596 EmulateInstructionARM::EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding)
7599 if ConditionPassed() then
7600 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7601 offset = Shift(R[m], shift_t, shift_n, APSR.C);
7602 offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7603 address = if index then offset_addr else R[n];
7604 data = MemU[address,2];
7605 if wback then R[n] = offset_addr;
7606 if UnalignedSupport() || address<0> = '0' then
7607 R[t] = SignExtend(data, 32);
7608 else // Can only apply before ARMv7
7609 R[t] = bits(32) UNKNOWN;
7612 bool success = false;
7614 if (ConditionPassed(opcode))
7622 ARM_ShifterType shift_t;
7625 // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
7629 // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
7630 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7631 t = Bits32 (opcode, 2, 0);
7632 n = Bits32 (opcode, 5, 3);
7633 m = Bits32 (opcode, 8, 6);
7635 // index = TRUE; add = TRUE; wback = FALSE;
7640 // (shift_t, shift_n) = (SRType_LSL, 0);
7641 shift_t = SRType_LSL;
7647 // if Rn == '1111' then SEE LDRSH (literal);
7648 // if Rt == '1111' then SEE "Unallocated memory hints";
7649 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7650 t = Bits32 (opcode, 15, 12);
7651 n = Bits32 (opcode, 19, 16);
7652 m = Bits32 (opcode, 3, 0);
7654 // index = TRUE; add = TRUE; wback = FALSE;
7659 // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
7660 shift_t = SRType_LSL;
7661 shift_n = Bits32 (opcode, 5, 4);
7663 // if t == 13 || BadReg(m) then UNPREDICTABLE;
7664 if ((t == 13) || BadReg (m))
7670 // if P == '0' && W == '1' then SEE LDRSHT;
7671 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7672 t = Bits32 (opcode, 15, 12);
7673 n = Bits32 (opcode, 19, 16);
7674 m = Bits32 (opcode, 3, 0);
7676 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
7677 index = BitIsSet (opcode, 24);
7678 add = BitIsSet (opcode, 23);
7679 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
7681 // (shift_t, shift_n) = (SRType_LSL, 0);
7682 shift_t = SRType_LSL;
7685 // if t == 15 || m == 15 then UNPREDICTABLE;
7686 if ((t == 15) || (m == 15))
7689 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
7690 if (wback && ((n == 15) || (n == t)))
7699 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7703 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7707 // offset = Shift(R[m], shift_t, shift_n, APSR.C);
7708 addr_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
7715 // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
7717 offset_addr = Rn + offset;
7719 offset_addr = Rn - offset;
7721 // address = if index then offset_addr else R[n];
7723 address = offset_addr;
7727 // data = MemU[address,2];
7728 RegisterInfo base_reg;
7729 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
7731 RegisterInfo offset_reg;
7732 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
7734 EmulateInstruction::Context context;
7735 context.type = eContextRegisterLoad;
7736 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
7738 uint64_t data = MemURead (context, address, 2, 0, &success);
7742 // if wback then R[n] = offset_addr;
7745 context.type = eContextAdjustBaseRegister;
7746 context.SetAddress (offset_addr);
7747 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
7751 // if UnalignedSupport() || address<0> = '0' then
7752 if (UnalignedSupport() || BitIsClear (address, 0))
7754 // R[t] = SignExtend(data, 32);
7755 context.type = eContextRegisterLoad;
7756 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
7758 int64_t signed_data = llvm::SignExtend64<16>(data);
7759 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, (uint64_t) signed_data))
7762 else // Can only apply before ARMv7
7764 // R[t] = bits(32) UNKNOWN;
7765 WriteBits32Unknown (t);
7771 // SXTB extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination
7772 // register. You can specifiy a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.
7774 EmulateInstructionARM::EmulateSXTB (const uint32_t opcode, const ARMEncoding encoding)
7777 if ConditionPassed() then
7778 EncodingSpecificOperations();
7779 rotated = ROR(R[m], rotation);
7780 R[d] = SignExtend(rotated<7:0>, 32);
7783 bool success = false;
7785 if (ConditionPassed(opcode))
7791 // EncodingSpecificOperations();
7795 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7796 d = Bits32 (opcode, 2, 0);
7797 m = Bits32 (opcode, 5, 3);
7803 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7804 d = Bits32 (opcode, 11, 8);
7805 m = Bits32 (opcode, 3, 0);
7806 rotation = Bits32 (opcode, 5, 4) << 3;
7808 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
7809 if (BadReg (d) || BadReg (m))
7815 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7816 d = Bits32 (opcode, 15, 12);
7817 m = Bits32 (opcode, 3, 0);
7818 rotation = Bits32 (opcode, 11, 10) << 3;
7820 // if d == 15 || m == 15 then UNPREDICTABLE;
7821 if ((d == 15) || (m == 15))
7830 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7834 // rotated = ROR(R[m], rotation);
7835 uint64_t rotated = ROR (Rm, rotation, &success);
7839 // R[d] = SignExtend(rotated<7:0>, 32);
7840 int64_t data = llvm::SignExtend64<8>(rotated);
7842 RegisterInfo source_reg;
7843 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
7845 EmulateInstruction::Context context;
7846 context.type = eContextRegisterLoad;
7847 context.SetRegister (source_reg);
7849 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (uint64_t) data))
7855 // SXTH extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination
7856 // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
7858 EmulateInstructionARM::EmulateSXTH (const uint32_t opcode, const ARMEncoding encoding)
7861 if ConditionPassed() then
7862 EncodingSpecificOperations();
7863 rotated = ROR(R[m], rotation);
7864 R[d] = SignExtend(rotated<15:0>, 32);
7867 bool success = false;
7869 if (ConditionPassed(opcode))
7875 // EncodingSpecificOperations();
7879 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7880 d = Bits32 (opcode, 2, 0);
7881 m = Bits32 (opcode, 5, 3);
7887 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7888 d = Bits32 (opcode, 11, 8);
7889 m = Bits32 (opcode, 3, 0);
7890 rotation = Bits32 (opcode, 5, 4) << 3;
7892 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
7893 if (BadReg (d) || BadReg (m))
7899 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7900 d = Bits32 (opcode, 15, 12);
7901 m = Bits32 (opcode, 3, 0);
7902 rotation = Bits32 (opcode, 11, 10) << 3;
7904 // if d == 15 || m == 15 then UNPREDICTABLE;
7905 if ((d == 15) || (m == 15))
7914 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7918 // rotated = ROR(R[m], rotation);
7919 uint64_t rotated = ROR (Rm, rotation, &success);
7923 // R[d] = SignExtend(rotated<15:0>, 32);
7924 RegisterInfo source_reg;
7925 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
7927 EmulateInstruction::Context context;
7928 context.type = eContextRegisterLoad;
7929 context.SetRegister (source_reg);
7931 int64_t data = llvm::SignExtend64<16> (rotated);
7932 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (uint64_t) data))
7939 // UXTB extracts an 8-bit value from a register, zero-extneds it to 32 bits, and writes the result to the destination
7940 // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.
7942 EmulateInstructionARM::EmulateUXTB (const uint32_t opcode, const ARMEncoding encoding)
7945 if ConditionPassed() then
7946 EncodingSpecificOperations();
7947 rotated = ROR(R[m], rotation);
7948 R[d] = ZeroExtend(rotated<7:0>, 32);
7951 bool success = false;
7953 if (ConditionPassed(opcode))
7959 // EncodingSpecificOperations();
7963 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
7964 d = Bits32 (opcode, 2, 0);
7965 m = Bits32 (opcode, 5, 3);
7971 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7972 d = Bits32 (opcode, 11, 8);
7973 m = Bits32 (opcode, 3, 0);
7974 rotation = Bits32 (opcode, 5, 4) << 3;
7976 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
7977 if (BadReg (d) || BadReg (m))
7983 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
7984 d = Bits32 (opcode, 15, 12);
7985 m = Bits32 (opcode, 3, 0);
7986 rotation = Bits32 (opcode, 11, 10) << 3;
7988 // if d == 15 || m == 15 then UNPREDICTABLE;
7989 if ((d == 15) || (m == 15))
7998 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8002 // rotated = ROR(R[m], rotation);
8003 uint64_t rotated = ROR (Rm, rotation, &success);
8007 // R[d] = ZeroExtend(rotated<7:0>, 32);
8008 RegisterInfo source_reg;
8009 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
8011 EmulateInstruction::Context context;
8012 context.type = eContextRegisterLoad;
8013 context.SetRegister (source_reg);
8015 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, Bits32 (rotated, 7, 0)))
8021 // UXTH extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination
8022 // register. You can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.
8024 EmulateInstructionARM::EmulateUXTH (const uint32_t opcode, const ARMEncoding encoding)
8027 if ConditionPassed() then
8028 EncodingSpecificOperations();
8029 rotated = ROR(R[m], rotation);
8030 R[d] = ZeroExtend(rotated<15:0>, 32);
8033 bool success = false;
8035 if (ConditionPassed(opcode))
8044 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8045 d = Bits32 (opcode, 2, 0);
8046 m = Bits32 (opcode, 5, 3);
8052 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8053 d = Bits32 (opcode, 11, 8);
8054 m = Bits32 (opcode, 3, 0);
8055 rotation = Bits32 (opcode, 5, 4) << 3;
8057 // if BadReg(d) || BadReg(m) then UNPREDICTABLE;
8058 if (BadReg (d) || BadReg (m))
8064 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8065 d = Bits32 (opcode, 15, 12);
8066 m = Bits32 (opcode, 3, 0);
8067 rotation = Bits32 (opcode, 11, 10) << 3;
8069 // if d == 15 || m == 15 then UNPREDICTABLE;
8070 if ((d == 15) || (m == 15))
8079 uint64_t Rm = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8083 // rotated = ROR(R[m], rotation);
8084 uint64_t rotated = ROR (Rm, rotation, &success);
8088 // R[d] = ZeroExtend(rotated<15:0>, 32);
8089 RegisterInfo source_reg;
8090 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, source_reg);
8092 EmulateInstruction::Context context;
8093 context.type = eContextRegisterLoad;
8094 context.SetRegister (source_reg);
8096 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, Bits32 (rotated, 15, 0)))
8102 // RFE (Return From Exception) loads the PC and the CPSR from the word at the specified address and the following
8103 // word respectively.
8105 EmulateInstructionARM::EmulateRFE (const uint32_t opcode, const ARMEncoding encoding)
8108 if ConditionPassed() then
8109 EncodingSpecificOperations();
8110 if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then
8113 address = if increment then R[n] else R[n]-8;
8114 if wordhigher then address = address+4;
8115 CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE);
8116 BranchWritePC(MemA[address,4]);
8117 if wback then R[n] = if increment then R[n]+8 else R[n]-8;
8120 bool success = false;
8122 if (ConditionPassed(opcode))
8129 // EncodingSpecificOperations();
8133 // n = UInt(Rn); wback = (W == '1'); increment = FALSE; wordhigher = FALSE;
8134 n = Bits32 (opcode, 19, 16);
8135 wback = BitIsSet (opcode, 21);
8139 // if n == 15 then UNPREDICTABLE;
8143 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
8144 if (InITBlock() && !LastInITBlock())
8150 // n = UInt(Rn); wback = (W == '1'); increment = TRUE; wordhigher = FALSE;
8151 n = Bits32 (opcode, 19, 16);
8152 wback = BitIsSet (opcode, 21);
8156 // if n == 15 then UNPREDICTABLE;
8160 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
8161 if (InITBlock() && !LastInITBlock())
8168 n = Bits32 (opcode, 19, 16);
8170 // wback = (W == '1'); inc = (U == '1'); wordhigher = (P == U);
8171 wback = BitIsSet (opcode, 21);
8172 increment = BitIsSet (opcode, 23);
8173 wordhigher = (Bit32 (opcode, 24) == Bit32 (opcode, 23));
8175 // if n == 15 then UNPREDICTABLE;
8185 // if !CurrentModeIsPrivileged() || CurrentInstrSet() == InstrSet_ThumbEE then
8186 if (!CurrentModeIsPrivileged ())
8191 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
8196 // address = if increment then R[n] else R[n]-8;
8202 // if wordhigher then address = address+4;
8204 address = address + 4;
8206 // CPSRWriteByInstr(MemA[address+4,4], '1111', TRUE);
8207 RegisterInfo base_reg;
8208 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
8210 EmulateInstruction::Context context;
8211 context.type = eContextReturnFromException;
8212 context.SetRegisterPlusOffset (base_reg, address - Rn);
8214 uint64_t data = MemARead (context, address + 4, 4, 0, &success);
8218 CPSRWriteByInstr (data, 15, true);
8220 // BranchWritePC(MemA[address,4]);
8221 uint64_t data2 = MemARead (context, address, 4, 0, &success);
8225 BranchWritePC (context, data2);
8227 // if wback then R[n] = if increment then R[n]+8 else R[n]-8;
8230 context.type = eContextAdjustBaseRegister;
8233 context.SetOffset (8);
8234 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + 8))
8239 context.SetOffset (-8);
8240 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn - 8))
8245 } // if ConditionPassed()
8249 // Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
8250 // and writes the result to the destination register. It can optionally update the condition flags based on
8253 EmulateInstructionARM::EmulateEORImm (const uint32_t opcode, const ARMEncoding encoding)
8256 // ARM pseudo code...
8257 if ConditionPassed() then
8258 EncodingSpecificOperations();
8259 result = R[n] EOR imm32;
8260 if d == 15 then // Can only occur for ARM encoding
8261 ALUWritePC(result); // setflags is always FALSE here
8265 APSR.N = result<31>;
8266 APSR.Z = IsZeroBit(result);
8271 bool success = false;
8273 if (ConditionPassed(opcode))
8276 uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn
8278 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
8282 Rd = Bits32(opcode, 11, 8);
8283 Rn = Bits32(opcode, 19, 16);
8284 setflags = BitIsSet(opcode, 20);
8285 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
8286 // if Rd == '1111' && S == '1' then SEE TEQ (immediate);
8287 if (Rd == 15 && setflags)
8288 return EmulateTEQImm (opcode, eEncodingT1);
8289 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn))
8293 Rd = Bits32(opcode, 15, 12);
8294 Rn = Bits32(opcode, 19, 16);
8295 setflags = BitIsSet(opcode, 20);
8296 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
8298 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8299 if (Rd == 15 && setflags)
8300 return EmulateSUBSPcLrEtc (opcode, encoding);
8306 // Read the first operand.
8307 uint32_t val1 = ReadCoreReg(Rn, &success);
8311 uint32_t result = val1 ^ imm32;
8313 EmulateInstruction::Context context;
8314 context.type = EmulateInstruction::eContextImmediate;
8315 context.SetNoArgs ();
8317 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8323 // Bitwise Exclusive OR (register) performs a bitwise exclusive OR of a register value and an
8324 // optionally-shifted register value, and writes the result to the destination register.
8325 // It can optionally update the condition flags based on the result.
8327 EmulateInstructionARM::EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding)
8330 // ARM pseudo code...
8331 if ConditionPassed() then
8332 EncodingSpecificOperations();
8333 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
8334 result = R[n] EOR shifted;
8335 if d == 15 then // Can only occur for ARM encoding
8336 ALUWritePC(result); // setflags is always FALSE here
8340 APSR.N = result<31>;
8341 APSR.Z = IsZeroBit(result);
8346 bool success = false;
8348 if (ConditionPassed(opcode))
8350 uint32_t Rd, Rn, Rm;
8351 ARM_ShifterType shift_t;
8352 uint32_t shift_n; // the shift applied to the value read from Rm
8358 Rd = Rn = Bits32(opcode, 2, 0);
8359 Rm = Bits32(opcode, 5, 3);
8360 setflags = !InITBlock();
8361 shift_t = SRType_LSL;
8365 Rd = Bits32(opcode, 11, 8);
8366 Rn = Bits32(opcode, 19, 16);
8367 Rm = Bits32(opcode, 3, 0);
8368 setflags = BitIsSet(opcode, 20);
8369 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8370 // if Rd == '1111' && S == '1' then SEE TEQ (register);
8371 if (Rd == 15 && setflags)
8372 return EmulateTEQReg (opcode, eEncodingT1);
8373 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
8377 Rd = Bits32(opcode, 15, 12);
8378 Rn = Bits32(opcode, 19, 16);
8379 Rm = Bits32(opcode, 3, 0);
8380 setflags = BitIsSet(opcode, 20);
8381 shift_n = DecodeImmShiftARM(opcode, shift_t);
8383 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8384 if (Rd == 15 && setflags)
8385 return EmulateSUBSPcLrEtc (opcode, encoding);
8391 // Read the first operand.
8392 uint32_t val1 = ReadCoreReg(Rn, &success);
8396 // Read the second operand.
8397 uint32_t val2 = ReadCoreReg(Rm, &success);
8401 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
8404 uint32_t result = val1 ^ shifted;
8406 EmulateInstruction::Context context;
8407 context.type = EmulateInstruction::eContextImmediate;
8408 context.SetNoArgs ();
8410 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8416 // Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and
8417 // writes the result to the destination register. It can optionally update the condition flags based
8420 EmulateInstructionARM::EmulateORRImm (const uint32_t opcode, const ARMEncoding encoding)
8423 // ARM pseudo code...
8424 if ConditionPassed() then
8425 EncodingSpecificOperations();
8426 result = R[n] OR imm32;
8427 if d == 15 then // Can only occur for ARM encoding
8428 ALUWritePC(result); // setflags is always FALSE here
8432 APSR.N = result<31>;
8433 APSR.Z = IsZeroBit(result);
8438 bool success = false;
8440 if (ConditionPassed(opcode))
8443 uint32_t imm32; // the immediate value to be ORed to the value obtained from Rn
8445 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
8449 Rd = Bits32(opcode, 11, 8);
8450 Rn = Bits32(opcode, 19, 16);
8451 setflags = BitIsSet(opcode, 20);
8452 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
8453 // if Rn == '1111' then SEE MOV (immediate);
8455 return EmulateMOVRdImm (opcode, eEncodingT2);
8456 if (BadReg(Rd) || Rn == 13)
8460 Rd = Bits32(opcode, 15, 12);
8461 Rn = Bits32(opcode, 19, 16);
8462 setflags = BitIsSet(opcode, 20);
8463 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
8465 if (Rd == 15 && setflags)
8466 return EmulateSUBSPcLrEtc (opcode, encoding);
8472 // Read the first operand.
8473 uint32_t val1 = ReadCoreReg(Rn, &success);
8477 uint32_t result = val1 | imm32;
8479 EmulateInstruction::Context context;
8480 context.type = EmulateInstruction::eContextImmediate;
8481 context.SetNoArgs ();
8483 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8489 // Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register
8490 // value, and writes the result to the destination register. It can optionally update the condition flags based
8493 EmulateInstructionARM::EmulateORRReg (const uint32_t opcode, const ARMEncoding encoding)
8496 // ARM pseudo code...
8497 if ConditionPassed() then
8498 EncodingSpecificOperations();
8499 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
8500 result = R[n] OR shifted;
8501 if d == 15 then // Can only occur for ARM encoding
8502 ALUWritePC(result); // setflags is always FALSE here
8506 APSR.N = result<31>;
8507 APSR.Z = IsZeroBit(result);
8512 bool success = false;
8514 if (ConditionPassed(opcode))
8516 uint32_t Rd, Rn, Rm;
8517 ARM_ShifterType shift_t;
8518 uint32_t shift_n; // the shift applied to the value read from Rm
8524 Rd = Rn = Bits32(opcode, 2, 0);
8525 Rm = Bits32(opcode, 5, 3);
8526 setflags = !InITBlock();
8527 shift_t = SRType_LSL;
8531 Rd = Bits32(opcode, 11, 8);
8532 Rn = Bits32(opcode, 19, 16);
8533 Rm = Bits32(opcode, 3, 0);
8534 setflags = BitIsSet(opcode, 20);
8535 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8536 // if Rn == '1111' then SEE MOV (register);
8538 return EmulateMOVRdRm (opcode, eEncodingT3);
8539 if (BadReg(Rd) || Rn == 13 || BadReg(Rm))
8543 Rd = Bits32(opcode, 15, 12);
8544 Rn = Bits32(opcode, 19, 16);
8545 Rm = Bits32(opcode, 3, 0);
8546 setflags = BitIsSet(opcode, 20);
8547 shift_n = DecodeImmShiftARM(opcode, shift_t);
8549 if (Rd == 15 && setflags)
8550 return EmulateSUBSPcLrEtc (opcode, encoding);
8556 // Read the first operand.
8557 uint32_t val1 = ReadCoreReg(Rn, &success);
8561 // Read the second operand.
8562 uint32_t val2 = ReadCoreReg(Rm, &success);
8566 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
8569 uint32_t result = val1 | shifted;
8571 EmulateInstruction::Context context;
8572 context.type = EmulateInstruction::eContextImmediate;
8573 context.SetNoArgs ();
8575 if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
8581 // Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to
8582 // the destination register. It can optionally update the condition flags based on the result.
8584 EmulateInstructionARM::EmulateRSBImm (const uint32_t opcode, const ARMEncoding encoding)
8587 // ARM pseudo code...
8588 if ConditionPassed() then
8589 EncodingSpecificOperations();
8590 (result, carry, overflow) = AddWithCarry(NOT(R[n]), imm32, '1');
8591 if d == 15 then // Can only occur for ARM encoding
8592 ALUWritePC(result); // setflags is always FALSE here
8596 APSR.N = result<31>;
8597 APSR.Z = IsZeroBit(result);
8602 bool success = false;
8604 uint32_t Rd; // the destination register
8605 uint32_t Rn; // the first operand
8607 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8610 Rd = Bits32(opcode, 2, 0);
8611 Rn = Bits32(opcode, 5, 3);
8612 setflags = !InITBlock();
8616 Rd = Bits32(opcode, 11, 8);
8617 Rn = Bits32(opcode, 19, 16);
8618 setflags = BitIsSet(opcode, 20);
8619 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
8620 if (BadReg(Rd) || BadReg(Rn))
8624 Rd = Bits32(opcode, 15, 12);
8625 Rn = Bits32(opcode, 19, 16);
8626 setflags = BitIsSet(opcode, 20);
8627 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8629 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8630 if (Rd == 15 && setflags)
8631 return EmulateSUBSPcLrEtc (opcode, encoding);
8636 // Read the register value from the operand register Rn.
8637 uint32_t reg_val = ReadCoreReg(Rn, &success);
8641 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, 1);
8643 EmulateInstruction::Context context;
8644 context.type = EmulateInstruction::eContextImmediate;
8645 context.SetNoArgs ();
8647 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8653 // Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the
8654 // result to the destination register. It can optionally update the condition flags based on the result.
8656 EmulateInstructionARM::EmulateRSBReg (const uint32_t opcode, const ARMEncoding encoding)
8659 // ARM pseudo code...
8660 if ConditionPassed() then
8661 EncodingSpecificOperations();
8662 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
8663 (result, carry, overflow) = AddWithCarry(NOT(R[n]), shifted, '1');
8664 if d == 15 then // Can only occur for ARM encoding
8665 ALUWritePC(result); // setflags is always FALSE here
8669 APSR.N = result<31>;
8670 APSR.Z = IsZeroBit(result);
8675 bool success = false;
8677 uint32_t Rd; // the destination register
8678 uint32_t Rn; // the first operand
8679 uint32_t Rm; // the second operand
8681 ARM_ShifterType shift_t;
8682 uint32_t shift_n; // the shift applied to the value read from Rm
8685 Rd = Bits32(opcode, 11, 8);
8686 Rn = Bits32(opcode, 19, 16);
8687 Rm = Bits32(opcode, 3, 0);
8688 setflags = BitIsSet(opcode, 20);
8689 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8690 // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
8691 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8695 Rd = Bits32(opcode, 15, 12);
8696 Rn = Bits32(opcode, 19, 16);
8697 Rm = Bits32(opcode, 3, 0);
8698 setflags = BitIsSet(opcode, 20);
8699 shift_n = DecodeImmShiftARM(opcode, shift_t);
8701 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8702 if (Rd == 15 && setflags)
8703 return EmulateSUBSPcLrEtc (opcode, encoding);
8708 // Read the register value from register Rn.
8709 uint32_t val1 = ReadCoreReg(Rn, &success);
8713 // Read the register value from register Rm.
8714 uint32_t val2 = ReadCoreReg(Rm, &success);
8718 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
8721 AddWithCarryResult res = AddWithCarry(~val1, shifted, 1);
8723 EmulateInstruction::Context context;
8724 context.type = EmulateInstruction::eContextImmediate;
8725 context.SetNoArgs();
8726 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8732 // Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from
8733 // an immediate value, and writes the result to the destination register. It can optionally update the condition
8734 // flags based on the result.
8736 EmulateInstructionARM::EmulateRSCImm (const uint32_t opcode, const ARMEncoding encoding)
8739 // ARM pseudo code...
8740 if ConditionPassed() then
8741 EncodingSpecificOperations();
8742 (result, carry, overflow) = AddWithCarry(NOT(R[n]), imm32, APSR.C);
8744 ALUWritePC(result); // setflags is always FALSE here
8748 APSR.N = result<31>;
8749 APSR.Z = IsZeroBit(result);
8754 bool success = false;
8756 uint32_t Rd; // the destination register
8757 uint32_t Rn; // the first operand
8759 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8762 Rd = Bits32(opcode, 15, 12);
8763 Rn = Bits32(opcode, 19, 16);
8764 setflags = BitIsSet(opcode, 20);
8765 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8767 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8768 if (Rd == 15 && setflags)
8769 return EmulateSUBSPcLrEtc (opcode, encoding);
8774 // Read the register value from the operand register Rn.
8775 uint32_t reg_val = ReadCoreReg(Rn, &success);
8779 AddWithCarryResult res = AddWithCarry(~reg_val, imm32, APSR_C);
8781 EmulateInstruction::Context context;
8782 context.type = EmulateInstruction::eContextImmediate;
8783 context.SetNoArgs ();
8785 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8791 // Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an
8792 // optionally-shifted register value, and writes the result to the destination register. It can optionally update the
8793 // condition flags based on the result.
8795 EmulateInstructionARM::EmulateRSCReg (const uint32_t opcode, const ARMEncoding encoding)
8798 // ARM pseudo code...
8799 if ConditionPassed() then
8800 EncodingSpecificOperations();
8801 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
8802 (result, carry, overflow) = AddWithCarry(NOT(R[n]), shifted, APSR.C);
8804 ALUWritePC(result); // setflags is always FALSE here
8808 APSR.N = result<31>;
8809 APSR.Z = IsZeroBit(result);
8814 bool success = false;
8816 uint32_t Rd; // the destination register
8817 uint32_t Rn; // the first operand
8818 uint32_t Rm; // the second operand
8820 ARM_ShifterType shift_t;
8821 uint32_t shift_n; // the shift applied to the value read from Rm
8824 Rd = Bits32(opcode, 15, 12);
8825 Rn = Bits32(opcode, 19, 16);
8826 Rm = Bits32(opcode, 3, 0);
8827 setflags = BitIsSet(opcode, 20);
8828 shift_n = DecodeImmShiftARM(opcode, shift_t);
8830 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8831 if (Rd == 15 && setflags)
8832 return EmulateSUBSPcLrEtc (opcode, encoding);
8837 // Read the register value from register Rn.
8838 uint32_t val1 = ReadCoreReg(Rn, &success);
8842 // Read the register value from register Rm.
8843 uint32_t val2 = ReadCoreReg(Rm, &success);
8847 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
8850 AddWithCarryResult res = AddWithCarry(~val1, shifted, APSR_C);
8852 EmulateInstruction::Context context;
8853 context.type = EmulateInstruction::eContextImmediate;
8854 context.SetNoArgs();
8855 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8861 // Subtract with Carry (immediate) subtracts an immediate value and the value of
8862 // NOT (Carry flag) from a register value, and writes the result to the destination register.
8863 // It can optionally update the condition flags based on the result.
8865 EmulateInstructionARM::EmulateSBCImm (const uint32_t opcode, const ARMEncoding encoding)
8868 // ARM pseudo code...
8869 if ConditionPassed() then
8870 EncodingSpecificOperations();
8871 (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), APSR.C);
8872 if d == 15 then // Can only occur for ARM encoding
8873 ALUWritePC(result); // setflags is always FALSE here
8877 APSR.N = result<31>;
8878 APSR.Z = IsZeroBit(result);
8883 bool success = false;
8885 uint32_t Rd; // the destination register
8886 uint32_t Rn; // the first operand
8888 uint32_t imm32; // the immediate value to be added to the value obtained from Rn
8891 Rd = Bits32(opcode, 11, 8);
8892 Rn = Bits32(opcode, 19, 16);
8893 setflags = BitIsSet(opcode, 20);
8894 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
8895 if (BadReg(Rd) || BadReg(Rn))
8899 Rd = Bits32(opcode, 15, 12);
8900 Rn = Bits32(opcode, 19, 16);
8901 setflags = BitIsSet(opcode, 20);
8902 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
8904 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8905 if (Rd == 15 && setflags)
8906 return EmulateSUBSPcLrEtc (opcode, encoding);
8911 // Read the register value from the operand register Rn.
8912 uint32_t reg_val = ReadCoreReg(Rn, &success);
8916 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, APSR_C);
8918 EmulateInstruction::Context context;
8919 context.type = EmulateInstruction::eContextImmediate;
8920 context.SetNoArgs ();
8922 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
8928 // Subtract with Carry (register) subtracts an optionally-shifted register value and the value of
8929 // NOT (Carry flag) from a register value, and writes the result to the destination register.
8930 // It can optionally update the condition flags based on the result.
8932 EmulateInstructionARM::EmulateSBCReg (const uint32_t opcode, const ARMEncoding encoding)
8935 // ARM pseudo code...
8936 if ConditionPassed() then
8937 EncodingSpecificOperations();
8938 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
8939 (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), APSR.C);
8940 if d == 15 then // Can only occur for ARM encoding
8941 ALUWritePC(result); // setflags is always FALSE here
8945 APSR.N = result<31>;
8946 APSR.Z = IsZeroBit(result);
8951 bool success = false;
8953 uint32_t Rd; // the destination register
8954 uint32_t Rn; // the first operand
8955 uint32_t Rm; // the second operand
8957 ARM_ShifterType shift_t;
8958 uint32_t shift_n; // the shift applied to the value read from Rm
8961 Rd = Rn = Bits32(opcode, 2, 0);
8962 Rm = Bits32(opcode, 5, 3);
8963 setflags = !InITBlock();
8964 shift_t = SRType_LSL;
8968 Rd = Bits32(opcode, 11, 8);
8969 Rn = Bits32(opcode, 19, 16);
8970 Rm = Bits32(opcode, 3, 0);
8971 setflags = BitIsSet(opcode, 20);
8972 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8973 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
8977 Rd = Bits32(opcode, 15, 12);
8978 Rn = Bits32(opcode, 19, 16);
8979 Rm = Bits32(opcode, 3, 0);
8980 setflags = BitIsSet(opcode, 20);
8981 shift_n = DecodeImmShiftARM(opcode, shift_t);
8983 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
8984 if (Rd == 15 && setflags)
8985 return EmulateSUBSPcLrEtc (opcode, encoding);
8990 // Read the register value from register Rn.
8991 uint32_t val1 = ReadCoreReg(Rn, &success);
8995 // Read the register value from register Rm.
8996 uint32_t val2 = ReadCoreReg(Rm, &success);
9000 uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
9003 AddWithCarryResult res = AddWithCarry(val1, ~shifted, APSR_C);
9005 EmulateInstruction::Context context;
9006 context.type = EmulateInstruction::eContextImmediate;
9007 context.SetNoArgs();
9008 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9014 // This instruction subtracts an immediate value from a register value, and writes the result
9015 // to the destination register. It can optionally update the condition flags based on the result.
9017 EmulateInstructionARM::EmulateSUBImmThumb (const uint32_t opcode, const ARMEncoding encoding)
9020 // ARM pseudo code...
9021 if ConditionPassed() then
9022 EncodingSpecificOperations();
9023 (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
9026 APSR.N = result<31>;
9027 APSR.Z = IsZeroBit(result);
9032 bool success = false;
9034 uint32_t Rd; // the destination register
9035 uint32_t Rn; // the first operand
9037 uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn
9040 Rd = Bits32(opcode, 2, 0);
9041 Rn = Bits32(opcode, 5, 3);
9042 setflags = !InITBlock();
9043 imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32)
9046 Rd = Rn = Bits32(opcode, 10, 8);
9047 setflags = !InITBlock();
9048 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
9051 Rd = Bits32(opcode, 11, 8);
9052 Rn = Bits32(opcode, 19, 16);
9053 setflags = BitIsSet(opcode, 20);
9054 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9056 // if Rd == '1111' && S == '1' then SEE CMP (immediate);
9057 if (Rd == 15 && setflags)
9058 return EmulateCMPImm (opcode, eEncodingT2);
9060 // if Rn == '1101' then SEE SUB (SP minus immediate);
9062 return EmulateSUBSPImm (opcode, eEncodingT2);
9064 // if d == 13 || (d == 15 && S == '0') || n == 15 then UNPREDICTABLE;
9065 if (Rd == 13 || (Rd == 15 && !setflags) || Rn == 15)
9069 Rd = Bits32(opcode, 11, 8);
9070 Rn = Bits32(opcode, 19, 16);
9071 setflags = BitIsSet(opcode, 20);
9072 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
9074 // if Rn == '1111' then SEE ADR;
9076 return EmulateADR (opcode, eEncodingT2);
9078 // if Rn == '1101' then SEE SUB (SP minus immediate);
9080 return EmulateSUBSPImm (opcode, eEncodingT3);
9088 // Read the register value from the operand register Rn.
9089 uint32_t reg_val = ReadCoreReg(Rn, &success);
9093 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
9095 EmulateInstruction::Context context;
9096 context.type = EmulateInstruction::eContextImmediate;
9097 context.SetNoArgs ();
9099 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9105 // This instruction subtracts an immediate value from a register value, and writes the result
9106 // to the destination register. It can optionally update the condition flags based on the result.
9108 EmulateInstructionARM::EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding)
9111 // ARM pseudo code...
9112 if ConditionPassed() then
9113 EncodingSpecificOperations();
9114 (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
9116 ALUWritePC(result); // setflags is always FALSE here
9120 APSR.N = result<31>;
9121 APSR.Z = IsZeroBit(result);
9126 bool success = false;
9128 uint32_t Rd; // the destination register
9129 uint32_t Rn; // the first operand
9131 uint32_t imm32; // the immediate value to be subtracted from the value obtained from Rn
9134 Rd = Bits32(opcode, 15, 12);
9135 Rn = Bits32(opcode, 19, 16);
9136 setflags = BitIsSet(opcode, 20);
9137 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9139 // if Rn == '1111' && S == '0' then SEE ADR;
9140 if (Rn == 15 && !setflags)
9141 return EmulateADR (opcode, eEncodingA2);
9143 // if Rn == '1101' then SEE SUB (SP minus immediate);
9145 return EmulateSUBSPImm (opcode, eEncodingA1);
9147 // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
9148 if (Rd == 15 && setflags)
9149 return EmulateSUBSPcLrEtc (opcode, encoding);
9154 // Read the register value from the operand register Rn.
9155 uint32_t reg_val = ReadCoreReg(Rn, &success);
9159 AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);
9161 EmulateInstruction::Context context;
9162 context.type = EmulateInstruction::eContextImmediate;
9163 context.SetNoArgs ();
9165 if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
9171 // Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an
9172 // immediate value. It updates the condition flags based on the result, and discards the result.
9174 EmulateInstructionARM::EmulateTEQImm (const uint32_t opcode, const ARMEncoding encoding)
9177 // ARM pseudo code...
9178 if ConditionPassed() then
9179 EncodingSpecificOperations();
9180 result = R[n] EOR imm32;
9181 APSR.N = result<31>;
9182 APSR.Z = IsZeroBit(result);
9187 bool success = false;
9189 if (ConditionPassed(opcode))
9192 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
9193 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
9197 Rn = Bits32(opcode, 19, 16);
9198 imm32 = ThumbExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9203 Rn = Bits32(opcode, 19, 16);
9204 imm32 = ARMExpandImm_C (opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
9210 // Read the first operand.
9211 uint32_t val1 = ReadCoreReg(Rn, &success);
9215 uint32_t result = val1 ^ imm32;
9217 EmulateInstruction::Context context;
9218 context.type = EmulateInstruction::eContextImmediate;
9219 context.SetNoArgs ();
9221 if (!WriteFlags(context, result, carry))
9227 // Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an
9228 // optionally-shifted register value. It updates the condition flags based on the result, and discards
9231 EmulateInstructionARM::EmulateTEQReg (const uint32_t opcode, const ARMEncoding encoding)
9234 // ARM pseudo code...
9235 if ConditionPassed() then
9236 EncodingSpecificOperations();
9237 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
9238 result = R[n] EOR shifted;
9239 APSR.N = result<31>;
9240 APSR.Z = IsZeroBit(result);
9245 bool success = false;
9247 if (ConditionPassed(opcode))
9250 ARM_ShifterType shift_t;
9251 uint32_t shift_n; // the shift applied to the value read from Rm
9256 Rn = Bits32(opcode, 19, 16);
9257 Rm = Bits32(opcode, 3, 0);
9258 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9259 if (BadReg(Rn) || BadReg(Rm))
9263 Rn = Bits32(opcode, 19, 16);
9264 Rm = Bits32(opcode, 3, 0);
9265 shift_n = DecodeImmShiftARM(opcode, shift_t);
9271 // Read the first operand.
9272 uint32_t val1 = ReadCoreReg(Rn, &success);
9276 // Read the second operand.
9277 uint32_t val2 = ReadCoreReg(Rm, &success);
9281 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
9284 uint32_t result = val1 ^ shifted;
9286 EmulateInstruction::Context context;
9287 context.type = EmulateInstruction::eContextImmediate;
9288 context.SetNoArgs ();
9290 if (!WriteFlags(context, result, carry))
9296 // Test (immediate) performs a bitwise AND operation on a register value and an immediate value.
9297 // It updates the condition flags based on the result, and discards the result.
9299 EmulateInstructionARM::EmulateTSTImm (const uint32_t opcode, const ARMEncoding encoding)
9302 // ARM pseudo code...
9303 if ConditionPassed() then
9304 EncodingSpecificOperations();
9305 result = R[n] AND imm32;
9306 APSR.N = result<31>;
9307 APSR.Z = IsZeroBit(result);
9312 bool success = false;
9314 if (ConditionPassed(opcode))
9317 uint32_t imm32; // the immediate value to be ANDed to the value obtained from Rn
9318 uint32_t carry; // the carry bit after ARM/Thumb Expand operation
9322 Rn = Bits32(opcode, 19, 16);
9323 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9328 Rn = Bits32(opcode, 19, 16);
9329 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); // (imm32, carry) = ARMExpandImm(imm12, APSR.C)
9335 // Read the first operand.
9336 uint32_t val1 = ReadCoreReg(Rn, &success);
9340 uint32_t result = val1 & imm32;
9342 EmulateInstruction::Context context;
9343 context.type = EmulateInstruction::eContextImmediate;
9344 context.SetNoArgs ();
9346 if (!WriteFlags(context, result, carry))
9352 // Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value.
9353 // It updates the condition flags based on the result, and discards the result.
9355 EmulateInstructionARM::EmulateTSTReg (const uint32_t opcode, const ARMEncoding encoding)
9358 // ARM pseudo code...
9359 if ConditionPassed() then
9360 EncodingSpecificOperations();
9361 (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
9362 result = R[n] AND shifted;
9363 APSR.N = result<31>;
9364 APSR.Z = IsZeroBit(result);
9369 bool success = false;
9371 if (ConditionPassed(opcode))
9374 ARM_ShifterType shift_t;
9375 uint32_t shift_n; // the shift applied to the value read from Rm
9380 Rn = Bits32(opcode, 2, 0);
9381 Rm = Bits32(opcode, 5, 3);
9382 shift_t = SRType_LSL;
9386 Rn = Bits32(opcode, 19, 16);
9387 Rm = Bits32(opcode, 3, 0);
9388 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9389 if (BadReg(Rn) || BadReg(Rm))
9393 Rn = Bits32(opcode, 19, 16);
9394 Rm = Bits32(opcode, 3, 0);
9395 shift_n = DecodeImmShiftARM(opcode, shift_t);
9401 // Read the first operand.
9402 uint32_t val1 = ReadCoreReg(Rn, &success);
9406 // Read the second operand.
9407 uint32_t val2 = ReadCoreReg(Rm, &success);
9411 uint32_t shifted = Shift_C(val2, shift_t, shift_n, APSR_C, carry, &success);
9414 uint32_t result = val1 & shifted;
9416 EmulateInstruction::Context context;
9417 context.type = EmulateInstruction::eContextImmediate;
9418 context.SetNoArgs ();
9420 if (!WriteFlags(context, result, carry))
9426 // A8.6.216 SUB (SP minus register)
9428 EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding)
9431 if ConditionPassed() then
9432 EncodingSpecificOperations();
9433 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9434 (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), Ô1Õ);
9435 if d == 15 then // Can only occur for ARM encoding
9436 ALUWritePC(result); // setflags is always FALSE here
9440 APSR.N = result<31>;
9441 APSR.Z = IsZeroBit(result);
9446 bool success = false;
9448 if (ConditionPassed(opcode))
9453 ARM_ShifterType shift_t;
9459 // d = UInt(Rd); m = UInt(Rm); setflags = (S == Ô1Õ);
9460 d = Bits32 (opcode, 11, 8);
9461 m = Bits32 (opcode, 3, 0);
9462 setflags = BitIsSet (opcode, 20);
9464 // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2);
9465 shift_n = DecodeImmShiftThumb (opcode, shift_t);
9467 // if d == 13 && (shift_t != SRType_LSL || shift_n > 3) then UNPREDICTABLE;
9468 if ((d == 13) && ((shift_t != SRType_LSL) || (shift_n > 3)))
9471 // if d == 15 || BadReg(m) then UNPREDICTABLE;
9472 if ((d == 15) || BadReg (m))
9477 // d = UInt(Rd); m = UInt(Rm); setflags = (S == Ô1Õ);
9478 d = Bits32 (opcode, 15, 12);
9479 m = Bits32 (opcode, 3, 0);
9480 setflags = BitIsSet (opcode, 20);
9482 // if Rd == Ô1111Õ && S == Ô1Õ then SEE SUBS PC, LR and related instructions;
9483 if (d == 15 && setflags)
9484 EmulateSUBSPcLrEtc (opcode, encoding);
9486 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
9487 shift_n = DecodeImmShiftARM (opcode, shift_t);
9494 // shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9495 uint32_t Rm = ReadCoreReg (m, &success);
9499 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
9503 // (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), Ô1Õ);
9504 uint32_t sp_val = ReadCoreReg (SP_REG, &success);
9508 AddWithCarryResult res = AddWithCarry (sp_val, ~shifted, 1);
9510 EmulateInstruction::Context context;
9511 context.type = eContextArithmetic;
9512 RegisterInfo sp_reg;
9513 GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
9514 RegisterInfo dwarf_reg;
9515 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, dwarf_reg);
9516 context.SetRegisterRegisterOperands (sp_reg, dwarf_reg);
9518 if (!WriteCoreRegOptionalFlags(context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow))
9525 // A8.6.7 ADD (register-shifted register)
9527 EmulateInstructionARM::EmulateADDRegShift (const uint32_t opcode, const ARMEncoding encoding)
9530 if ConditionPassed() then
9531 EncodingSpecificOperations();
9532 shift_n = UInt(R[s]<7:0>);
9533 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9534 (result, carry, overflow) = AddWithCarry(R[n], shifted, Ô0Õ);
9537 APSR.N = result<31>;
9538 APSR.Z = IsZeroBit(result);
9543 bool success = false;
9545 if (ConditionPassed(opcode))
9552 ARM_ShifterType shift_t;
9557 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
9558 d = Bits32 (opcode, 15, 12);
9559 n = Bits32 (opcode, 19, 16);
9560 m = Bits32 (opcode, 3, 0);
9561 s = Bits32 (opcode, 11, 8);
9563 // setflags = (S == Ô1Õ); shift_t = DecodeRegShift(type);
9564 setflags = BitIsSet (opcode, 20);
9565 shift_t = DecodeRegShift (Bits32 (opcode, 6, 5));
9567 // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
9568 if ((d == 15) || (m == 15) || (m == 15) || (s == 15))
9576 // shift_n = UInt(R[s]<7:0>);
9577 uint32_t Rs = ReadCoreReg (s, &success);
9581 uint32_t shift_n = Bits32 (Rs, 7, 0);
9583 // shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9584 uint32_t Rm = ReadCoreReg (m, &success);
9588 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
9592 // (result, carry, overflow) = AddWithCarry(R[n], shifted, Ô0Õ);
9593 uint32_t Rn = ReadCoreReg (n, &success);
9597 AddWithCarryResult res = AddWithCarry (Rn, shifted, 0);
9600 EmulateInstruction::Context context;
9601 context.type = eContextArithmetic;
9603 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
9605 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, reg_m);
9607 context.SetRegisterRegisterOperands (reg_n, reg_m);
9609 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, res.result))
9613 // APSR.N = result<31>;
9614 // APSR.Z = IsZeroBit(result);
9616 // APSR.V = overflow;
9618 return WriteFlags (context, res.result, res.carry_out, res.overflow);
9623 // A8.6.213 SUB (register)
9625 EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding)
9628 if ConditionPassed() then
9629 EncodingSpecificOperations();
9630 shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9631 (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), Ô1Õ);
9632 if d == 15 then // Can only occur for ARM encoding
9633 ALUWritePC(result); // setflags is always FALSE here
9637 APSR.N = result<31>;
9638 APSR.Z = IsZeroBit(result);
9643 bool success = false;
9645 if (ConditionPassed(opcode))
9651 ARM_ShifterType shift_t;
9657 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock();
9658 d = Bits32 (opcode, 2, 0);
9659 n = Bits32 (opcode, 5, 3);
9660 m = Bits32 (opcode, 8, 6);
9661 setflags = !InITBlock();
9663 // (shift_t, shift_n) = (SRType_LSL, 0);
9664 shift_t = SRType_LSL;
9670 // if Rd == Ô1111Õ && S == Ô1Õ then SEE CMP (register);
9671 // if Rn == Ô1101Õ then SEE SUB (SP minus register);
9672 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == Ô1Õ);
9673 d = Bits32 (opcode, 11, 8);
9674 n = Bits32 (opcode, 19, 16);
9675 m = Bits32 (opcode, 3, 0);
9676 setflags = BitIsSet (opcode, 20);
9678 // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2);
9679 shift_n = DecodeImmShiftThumb (opcode, shift_t);
9681 // if d == 13 || (d == 15 && S == '0') || n == 15 || BadReg(m) then UNPREDICTABLE;
9682 if ((d == 13) || ((d == 15) && BitIsClear (opcode, 20)) || (n == 15) || BadReg (m))
9688 // if Rn == Ô1101Õ then SEE SUB (SP minus register);
9689 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == Ô1Õ);
9690 d = Bits32 (opcode, 15, 12);
9691 n = Bits32 (opcode, 19, 16);
9692 m = Bits32 (opcode, 3, 0);
9693 setflags = BitIsSet (opcode, 20);
9695 // if Rd == Ô1111Õ && S == Ô1Õ then SEE SUBS PC, LR and related instructions;
9696 if ((d == 15) && setflags)
9697 EmulateSUBSPcLrEtc (opcode, encoding);
9699 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
9700 shift_n = DecodeImmShiftARM (opcode, shift_t);
9708 // shifted = Shift(R[m], shift_t, shift_n, APSR.C);
9709 uint32_t Rm = ReadCoreReg (m, &success);
9713 uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C, &success);
9717 // (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), Ô1Õ);
9718 uint32_t Rn = ReadCoreReg (n, &success);
9722 AddWithCarryResult res = AddWithCarry (Rn, ~shifted, 1);
9724 // if d == 15 then // Can only occur for ARM encoding
9725 // ALUWritePC(result); // setflags is always FALSE here
9729 // APSR.N = result<31>;
9730 // APSR.Z = IsZeroBit(result);
9732 // APSR.V = overflow;
9734 EmulateInstruction::Context context;
9735 context.type = eContextArithmetic;
9737 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);
9739 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, reg_m);
9740 context.SetRegisterRegisterOperands (reg_n, reg_m);
9742 if (!WriteCoreRegOptionalFlags (context, res.result, dwarf_r0 + d, setflags, res.carry_out, res.overflow))
9749 // Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a
9750 // word from a register to memory if the executing processor has exclusive access to the memory addressed.
9752 EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding)
9755 if ConditionPassed() then
9756 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
9757 address = R[n] + imm32;
9758 if ExclusiveMonitorsPass(address,4) then
9759 MemA[address,4] = R[t];
9765 bool success = false;
9767 if (ConditionPassed(opcode))
9773 const uint32_t addr_byte_size = GetAddressByteSize();
9778 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
9779 d = Bits32 (opcode, 11, 8);
9780 t = Bits32 (opcode, 15, 12);
9781 n = Bits32 (opcode, 19, 16);
9782 imm32 = Bits32 (opcode, 7, 0) << 2;
9784 // if BadReg(d) || BadReg(t) || n == 15 then UNPREDICTABLE;
9785 if (BadReg (d) || BadReg (t) || (n == 15))
9788 // if d == n || d == t then UNPREDICTABLE;
9789 if ((d == n) || (d == t))
9795 // d = UInt(Rd); t = UInt(Rt); n = UInt(Rn); imm32 = Zeros(32); // Zero offset
9796 d = Bits32 (opcode, 15, 12);
9797 t = Bits32 (opcode, 3, 0);
9798 n = Bits32 (opcode, 19, 16);
9801 // if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
9802 if ((d == 15) || (t == 15) || (n == 15))
9805 // if d == n || d == t then UNPREDICTABLE;
9806 if ((d == n) || (d == t))
9815 // address = R[n] + imm32;
9816 uint32_t Rn = ReadCoreReg (n, &success);
9820 addr_t address = Rn + imm32;
9822 RegisterInfo base_reg;
9823 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
9824 RegisterInfo data_reg;
9825 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
9826 EmulateInstruction::Context context;
9827 context.type = eContextRegisterStore;
9828 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, imm32);
9830 // if ExclusiveMonitorsPass(address,4) then
9831 // if (ExclusiveMonitorsPass (address, addr_byte_size)) -- For now, for the sake of emulation, we will say this
9832 // always return true.
9835 // MemA[address,4] = R[t];
9836 uint32_t Rt = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
9840 if (!MemAWrite (context, address, Rt, addr_byte_size))
9844 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, 0))
9850 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, 1))
9857 // A8.6.197 STRB (immediate, ARM)
9859 EmulateInstructionARM::EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding)
9862 if ConditionPassed() then
9863 EncodingSpecificOperations();
9864 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9865 address = if index then offset_addr else R[n];
9866 MemU[address,1] = R[t]<7:0>;
9867 if wback then R[n] = offset_addr;
9870 bool success = false;
9872 if (ConditionPassed(opcode))
9884 // if P == Ô0Õ && W == Ô1Õ then SEE STRBT;
9885 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
9886 t = Bits32 (opcode, 15, 12);
9887 n = Bits32 (opcode, 19, 16);
9888 imm32 = Bits32 (opcode, 11, 0);
9890 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
9891 index = BitIsSet (opcode, 24);
9892 add = BitIsSet (opcode, 23);
9893 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
9895 // if t == 15 then UNPREDICTABLE;
9899 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
9900 if (wback && ((n == 15) || (n == t)))
9909 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9910 uint32_t Rn = ReadCoreReg (n, &success);
9916 offset_addr = Rn + imm32;
9918 offset_addr = Rn - imm32;
9920 // address = if index then offset_addr else R[n];
9923 address = offset_addr;
9927 // MemU[address,1] = R[t]<7:0>;
9928 uint32_t Rt = ReadCoreReg (t, &success);
9932 RegisterInfo base_reg;
9933 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
9934 RegisterInfo data_reg;
9935 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
9936 EmulateInstruction::Context context;
9937 context.type = eContextRegisterStore;
9938 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
9940 if (!MemUWrite (context, address, Bits32 (Rt, 7, 0), 1))
9943 // if wback then R[n] = offset_addr;
9946 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
9953 // A8.6.194 STR (immediate, ARM)
9955 EmulateInstructionARM::EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding)
9958 if ConditionPassed() then
9959 EncodingSpecificOperations();
9960 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
9961 address = if index then offset_addr else R[n];
9962 MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
9963 if wback then R[n] = offset_addr;
9966 bool success = false;
9968 if (ConditionPassed(opcode))
9977 const uint32_t addr_byte_size = GetAddressByteSize();
9982 // if P == Ô0Õ && W == Ô1Õ then SEE STRT;
9983 // if Rn == Ô1101Õ && P == Ô1Õ && U == Ô0Õ && W == Ô1Õ && imm12 == Ô000000000100Õ then SEE PUSH;
9984 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
9985 t = Bits32 (opcode, 15, 12);
9986 n = Bits32 (opcode, 19, 16);
9987 imm32 = Bits32 (opcode, 11, 0);
9989 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
9990 index = BitIsSet (opcode, 24);
9991 add = BitIsSet (opcode, 23);
9992 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
9994 // if wback && (n == 15 || n == t) then UNPREDICTABLE;
9995 if (wback && ((n == 15) || (n == t)))
10004 // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10005 uint32_t Rn = ReadCoreReg (n, &success);
10009 addr_t offset_addr;
10011 offset_addr = Rn + imm32;
10013 offset_addr = Rn - imm32;
10015 // address = if index then offset_addr else R[n];
10018 address = offset_addr;
10022 RegisterInfo base_reg;
10023 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10024 RegisterInfo data_reg;
10025 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
10026 EmulateInstruction::Context context;
10027 context.type = eContextRegisterStore;
10028 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10030 // MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
10031 uint32_t Rt = ReadCoreReg (t, &success);
10037 uint32_t pc_value = ReadCoreReg (PC_REG, &success);
10041 if (!MemUWrite (context, address, pc_value, addr_byte_size))
10046 if (!MemUWrite (context, address, Rt, addr_byte_size))
10050 // if wback then R[n] = offset_addr;
10053 context.type = eContextAdjustBaseRegister;
10054 context.SetImmediate (offset_addr);
10056 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10063 // A8.6.66 LDRD (immediate)
10064 // Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two
10065 // words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing.
10067 EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding)
10070 if ConditionPassed() then
10071 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
10072 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10073 address = if index then offset_addr else R[n];
10074 R[t] = MemA[address,4];
10075 R[t2] = MemA[address+4,4];
10076 if wback then R[n] = offset_addr;
10079 bool success = false;
10081 if (ConditionPassed(opcode))
10094 //if P == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10095 //if Rn == Ô1111Õ then SEE LDRD (literal);
10096 //t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
10097 t = Bits32 (opcode, 15, 12);
10098 t2 = Bits32 (opcode, 11, 8);
10099 n = Bits32 (opcode, 19, 16);
10100 imm32 = Bits32 (opcode, 7, 0) << 2;
10102 //index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (W == Ô1Õ);
10103 index = BitIsSet (opcode, 24);
10104 add = BitIsSet (opcode, 23);
10105 wback = BitIsSet (opcode, 21);
10107 //if wback && (n == t || n == t2) then UNPREDICTABLE;
10108 if (wback && ((n == t) || (n == t2)))
10111 //if BadReg(t) || BadReg(t2) || t == t2 then UNPREDICTABLE;
10112 if (BadReg (t) || BadReg (t2) || (t == t2))
10118 //if Rn == Ô1111Õ then SEE LDRD (literal);
10119 //if Rt<0> == Ô1Õ then UNPREDICTABLE;
10120 //t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
10121 t = Bits32 (opcode, 15, 12);
10122 if (BitIsSet (t, 0))
10125 n = Bits32 (opcode, 19, 16);
10126 imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0);
10128 //index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10129 index = BitIsSet (opcode, 24);
10130 add = BitIsSet (opcode, 23);
10131 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10133 //if P == Ô0Õ && W == Ô1Õ then UNPREDICTABLE;
10134 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10137 //if wback && (n == t || n == t2) then UNPREDICTABLE;
10138 if (wback && ((n == t) || (n == t2)))
10141 //if t2 == 15 then UNPREDICTABLE;
10151 //offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10152 uint32_t Rn = ReadCoreReg (n, &success);
10156 addr_t offset_addr;
10158 offset_addr = Rn + imm32;
10160 offset_addr = Rn - imm32;
10162 //address = if index then offset_addr else R[n];
10165 address = offset_addr;
10169 //R[t] = MemA[address,4];
10170 RegisterInfo base_reg;
10171 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10173 EmulateInstruction::Context context;
10174 context.type = eContextRegisterLoad;
10175 context.SetRegisterPlusOffset (base_reg, address - Rn);
10177 const uint32_t addr_byte_size = GetAddressByteSize();
10178 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10182 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
10185 //R[t2] = MemA[address+4,4];
10187 context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn);
10188 data = MemARead (context, address + 4, addr_byte_size, 0, &success);
10192 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t2, data))
10195 //if wback then R[n] = offset_addr;
10198 context.type = eContextAdjustBaseRegister;
10199 context.SetAddress (offset_addr);
10201 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10208 // A8.6.68 LDRD (register)
10209 // Load Register Dual (register) calculates an address from a base register value and a register offset, loads two
10210 // words from memory, and writes them to two registers. It can use offset, post-indexed or pre-indexed addressing.
10212 EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding)
10215 if ConditionPassed() then
10216 EncodingSpecificOperations();
10217 offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10218 address = if index then offset_addr else R[n];
10219 R[t] = MemA[address,4];
10220 R[t2] = MemA[address+4,4];
10221 if wback then R[n] = offset_addr;
10224 bool success = false;
10226 if (ConditionPassed(opcode))
10239 // if Rt<0> == Ô1Õ then UNPREDICTABLE;
10240 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10241 t = Bits32 (opcode, 15, 12);
10242 if (BitIsSet (t, 0))
10245 n = Bits32 (opcode, 19, 16);
10246 m = Bits32 (opcode, 3, 0);
10248 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10249 index = BitIsSet (opcode, 24);
10250 add = BitIsSet (opcode, 23);
10251 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10253 // if P == Ô0Õ && W == Ô1Õ then UNPREDICTABLE;
10254 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10257 // if t2 == 15 || m == 15 || m == t || m == t2 then UNPREDICTABLE;
10258 if ((t2 == 15) || (m == 15) || (m == t) || (m == t2))
10261 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10262 if (wback && ((n == 15) || (n == t) || (n == t2)))
10265 // if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
10266 if ((ArchVersion() < 6) && wback && (m == n))
10274 uint32_t Rn = ReadCoreReg (n, &success);
10277 RegisterInfo base_reg;
10278 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10280 uint32_t Rm = ReadCoreReg (m, &success);
10283 RegisterInfo offset_reg;
10284 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
10286 // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10287 addr_t offset_addr;
10289 offset_addr = Rn + Rm;
10291 offset_addr = Rn - Rm;
10293 // address = if index then offset_addr else R[n];
10296 address = offset_addr;
10300 EmulateInstruction::Context context;
10301 context.type = eContextRegisterLoad;
10302 context.SetRegisterPlusIndirectOffset (base_reg, offset_reg);
10304 // R[t] = MemA[address,4];
10305 const uint32_t addr_byte_size = GetAddressByteSize();
10306 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10310 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
10313 // R[t2] = MemA[address+4,4];
10315 data = MemARead (context, address + 4, addr_byte_size, 0, &success);
10319 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t2, data))
10322 // if wback then R[n] = offset_addr;
10325 context.type = eContextAdjustBaseRegister;
10326 context.SetAddress (offset_addr);
10328 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10335 // A8.6.200 STRD (immediate)
10336 // Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and
10337 // stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing.
10339 EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding)
10342 if ConditionPassed() then
10343 EncodingSpecificOperations(); NullCheckIfThumbEE(n);
10344 offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10345 address = if index then offset_addr else R[n];
10346 MemA[address,4] = R[t];
10347 MemA[address+4,4] = R[t2];
10348 if wback then R[n] = offset_addr;
10351 bool success = false;
10353 if (ConditionPassed(opcode))
10366 // if P == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10367 // t = UInt(Rt); t2 = UInt(Rt2); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
10368 t = Bits32 (opcode, 15, 12);
10369 t2 = Bits32 (opcode, 11, 8);
10370 n = Bits32 (opcode, 19, 16);
10371 imm32 = Bits32 (opcode, 7, 0) << 2;
10373 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (W == Ô1Õ);
10374 index = BitIsSet (opcode, 24);
10375 add = BitIsSet (opcode, 23);
10376 wback = BitIsSet (opcode, 21);
10378 // if wback && (n == t || n == t2) then UNPREDICTABLE;
10379 if (wback && ((n == t) || (n == t2)))
10382 // if n == 15 || BadReg(t) || BadReg(t2) then UNPREDICTABLE;
10383 if ((n == 15) || BadReg (t) || BadReg (t2))
10389 // if Rt<0> == Ô1Õ then UNPREDICTABLE;
10390 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); imm32 = ZeroExtend(imm4H:imm4L, 32);
10391 t = Bits32 (opcode, 15, 12);
10392 if (BitIsSet (t, 0))
10396 n = Bits32 (opcode, 19, 16);
10397 imm32 = (Bits32 (opcode, 11, 8) << 4) | Bits32 (opcode, 3, 0);
10399 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10400 index = BitIsSet (opcode, 24);
10401 add = BitIsSet (opcode, 23);
10402 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10404 // if P == Ô0Õ && W == Ô1Õ then UNPREDICTABLE;
10405 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10408 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10409 if (wback && ((n == 15) || (n == t) || (n == t2)))
10412 // if t2 == 15 then UNPREDICTABLE;
10422 RegisterInfo base_reg;
10423 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10425 uint32_t Rn = ReadCoreReg (n, &success);
10429 //offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
10430 addr_t offset_addr;
10432 offset_addr = Rn + imm32;
10434 offset_addr = Rn - imm32;
10436 //address = if index then offset_addr else R[n];
10439 address = offset_addr;
10443 //MemA[address,4] = R[t];
10444 RegisterInfo data_reg;
10445 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
10447 uint32_t data = ReadCoreReg (t, &success);
10451 EmulateInstruction::Context context;
10452 context.type = eContextRegisterStore;
10453 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10455 const uint32_t addr_byte_size = GetAddressByteSize();
10457 if (!MemAWrite (context, address, data, addr_byte_size))
10460 //MemA[address+4,4] = R[t2];
10461 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t2, data_reg);
10462 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
10464 data = ReadCoreReg (t2, &success);
10468 if (!MemAWrite (context, address + 4, data, addr_byte_size))
10471 //if wback then R[n] = offset_addr;
10474 context.type = eContextAdjustBaseRegister;
10475 context.SetAddress (offset_addr);
10477 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10485 // A8.6.201 STRD (register)
10487 EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding)
10490 if ConditionPassed() then
10491 EncodingSpecificOperations();
10492 offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10493 address = if index then offset_addr else R[n];
10494 MemA[address,4] = R[t];
10495 MemA[address+4,4] = R[t2];
10496 if wback then R[n] = offset_addr;
10499 bool success = false;
10501 if (ConditionPassed(opcode))
10514 // if Rt<0> == Ô1Õ then UNPREDICTABLE;
10515 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10516 t = Bits32 (opcode, 15, 12);
10517 if (BitIsSet (t, 0))
10521 n = Bits32 (opcode, 19, 16);
10522 m = Bits32 (opcode, 3, 0);
10524 // index = (P == Ô1Õ); add = (U == Ô1Õ); wback = (P == Ô0Õ) || (W == Ô1Õ);
10525 index = BitIsSet (opcode, 24);
10526 add = BitIsSet (opcode, 23);
10527 wback = BitIsClear (opcode, 24) || BitIsSet (opcode, 21);
10529 // if P == Ô0Õ && W == Ô1Õ then UNPREDICTABLE;
10530 if (BitIsClear (opcode, 24) && BitIsSet (opcode, 21))
10533 // if t2 == 15 || m == 15 then UNPREDICTABLE;
10534 if ((t2 == 15) || (m == 15))
10537 // if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
10538 if (wback && ((n == 15) || (n == t) || (n == t2)))
10541 // if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;
10542 if ((ArchVersion() < 6) && wback && (m == n))
10551 RegisterInfo base_reg;
10552 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10553 RegisterInfo offset_reg;
10554 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
10555 RegisterInfo data_reg;
10557 uint32_t Rn = ReadCoreReg (n, &success);
10561 uint32_t Rm = ReadCoreReg (m, &success);
10565 // offset_addr = if add then (R[n] + R[m]) else (R[n] - R[m]);
10566 addr_t offset_addr;
10568 offset_addr = Rn + Rm;
10570 offset_addr = Rn - Rm;
10572 // address = if index then offset_addr else R[n];
10575 address = offset_addr;
10578 // MemA[address,4] = R[t];
10579 uint32_t Rt = ReadCoreReg (t, &success);
10583 EmulateInstruction::Context context;
10584 context.type = eContextRegisterStore;
10585 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
10586 context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
10588 const uint32_t addr_byte_size = GetAddressByteSize();
10590 if (!MemAWrite (context, address, Rt, addr_byte_size))
10593 // MemA[address+4,4] = R[t2];
10594 uint32_t Rt2 = ReadCoreReg (t2, &success);
10598 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t2, data_reg);
10600 context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);
10602 if (!MemAWrite (context, address + 4, Rt2, addr_byte_size))
10605 // if wback then R[n] = offset_addr;
10608 context.type = eContextAdjustBaseRegister;
10609 context.SetAddress (offset_addr);
10611 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
10620 // Vector Load Multiple loads multiple extension registers from consecutive memory locations using an address from
10621 // an ARM core register.
10623 EmulateInstructionARM::EmulateVLDM (const uint32_t opcode, const ARMEncoding encoding)
10626 if ConditionPassed() then
10627 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
10628 address = if add then R[n] else R[n]-imm32;
10629 if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10630 for r = 0 to regs-1
10631 if single_regs then
10632 S[d+r] = MemA[address,4]; address = address+4;
10634 word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
10635 // Combine the word-aligned words in the correct order for current endianness.
10636 D[d+r] = if BigEndian() then word1:word2 else word2:word1;
10639 bool success = false;
10641 if (ConditionPassed(opcode))
10655 // if P == Ô0Õ && U == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10656 // if P == Ô0Õ && U == Ô1Õ && W == Ô1Õ && Rn == Ô1101Õ then SEE VPOP;
10657 // if P == Ô1Õ && W == Ô0Õ then SEE VLDR;
10658 // if P == U && W == Ô1Õ then UNDEFINED;
10659 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10662 // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
10663 // single_regs = FALSE; add = (U == Ô1Õ); wback = (W == Ô1Õ);
10664 single_regs = false;
10665 add = BitIsSet (opcode, 23);
10666 wback = BitIsSet (opcode, 21);
10668 // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
10669 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
10670 n = Bits32 (opcode, 19, 16);
10671 imm32 = Bits32 (opcode, 7, 0) << 2;
10673 // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see ÒFLDMXÓ.
10674 regs = Bits32 (opcode, 7, 0) / 2;
10676 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10677 if (n == 15 && (wback || CurrentInstrSet() != eModeARM))
10680 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
10681 if ((regs == 0) || (regs > 16) || ((d + regs) > 32))
10688 // if P == Ô0Õ && U == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10689 // if P == Ô0Õ && U == Ô1Õ && W == Ô1Õ && Rn == Ô1101Õ then SEE VPOP;
10690 // if P == Ô1Õ && W == Ô0Õ then SEE VLDR;
10691 // if P == U && W == Ô1Õ then UNDEFINED;
10692 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10695 // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
10696 // single_regs = TRUE; add = (U == Ô1Õ); wback = (W == Ô1Õ); d = UInt(Vd:D); n = UInt(Rn);
10697 single_regs = true;
10698 add = BitIsSet (opcode, 23);
10699 wback = BitIsSet (opcode, 21);
10700 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
10701 n = Bits32 (opcode, 19, 16);
10703 // imm32 = ZeroExtend(imm8:Õ00Õ, 32); regs = UInt(imm8);
10704 imm32 = Bits32 (opcode, 7, 0) << 2;
10705 regs = Bits32 (opcode, 7, 0);
10707 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10708 if ((n == 15) && (wback || (CurrentInstrSet() != eModeARM)))
10711 // if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
10712 if ((regs == 0) || ((d + regs) > 32))
10720 RegisterInfo base_reg;
10721 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10723 uint32_t Rn = ReadCoreReg (n, &success);
10727 // address = if add then R[n] else R[n]-imm32;
10732 address = Rn - imm32;
10734 // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10735 EmulateInstruction::Context context;
10741 value = Rn + imm32;
10743 value = Rn - imm32;
10745 context.type = eContextAdjustBaseRegister;
10746 context.SetImmediateSigned (value - Rn);
10747 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
10752 const uint32_t addr_byte_size = GetAddressByteSize();
10753 uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
10755 context.type = eContextRegisterLoad;
10757 // for r = 0 to regs-1
10758 for (uint32_t r = 0; r < regs; ++r)
10762 // S[d+r] = MemA[address,4]; address = address+4;
10763 context.SetRegisterPlusOffset (base_reg, address - Rn);
10765 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
10769 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, start_reg + d + r, data))
10772 address = address + 4;
10776 // word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
10777 context.SetRegisterPlusOffset (base_reg, address - Rn);
10778 uint32_t word1 = MemARead (context, address, addr_byte_size, 0, &success);
10782 context.SetRegisterPlusOffset (base_reg, (address + 4) - Rn);
10783 uint32_t word2 = MemARead (context, address + 4, addr_byte_size, 0, &success);
10787 address = address + 8;
10788 // // Combine the word-aligned words in the correct order for current endianness.
10789 // D[d+r] = if BigEndian() then word1:word2 else word2:word1;
10791 if (GetByteOrder() == eByteOrderBig)
10794 data = (data << 32) | word2;
10799 data = (data << 32) | word1;
10802 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, start_reg + d + r, data))
10811 // Vector Store Multiple stores multiple extension registers to consecutive memory locations using an address from an
10812 // ARM core register.
10814 EmulateInstructionARM::EmulateVSTM (const uint32_t opcode, const ARMEncoding encoding)
10817 if ConditionPassed() then
10818 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
10819 address = if add then R[n] else R[n]-imm32;
10820 if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10821 for r = 0 to regs-1
10822 if single_regs then
10823 MemA[address,4] = S[d+r]; address = address+4;
10825 // Store as two word-aligned words in the correct order for current endianness.
10826 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
10827 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
10828 address = address+8;
10831 bool success = false;
10833 if (ConditionPassed (opcode))
10847 // if P == Ô0Õ && U == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10848 // if P == Ô1Õ && U == Ô0Õ && W == Ô1Õ && Rn == Ô1101Õ then SEE VPUSH;
10849 // if P == Ô1Õ && W == Ô0Õ then SEE VSTR;
10850 // if P == U && W == Ô1Õ then UNDEFINED;
10851 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10854 // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
10855 // single_regs = FALSE; add = (U == Ô1Õ); wback = (W == Ô1Õ);
10856 single_regs = false;
10857 add = BitIsSet (opcode, 23);
10858 wback = BitIsSet (opcode, 21);
10860 // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
10861 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
10862 n = Bits32 (opcode, 19, 16);
10863 imm32 = Bits32 (opcode, 7, 0) << 2;
10865 // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see ÒFSTMXÓ.
10866 regs = Bits32 (opcode, 7, 0) / 2;
10868 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10869 if ((n == 15) && (wback || (CurrentInstrSet() != eModeARM)))
10872 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
10873 if ((regs == 0) || (regs > 16) || ((d + regs) > 32))
10880 // if P == Ô0Õ && U == Ô0Õ && W == Ô0Õ then SEE ÒRelated encodingsÓ;
10881 // if P == Ô1Õ && U == Ô0Õ && W == Ô1Õ && Rn == Ô1101Õ then SEE VPUSH;
10882 // if P == Ô1Õ && W == Ô0Õ then SEE VSTR;
10883 // if P == U && W == Ô1Õ then UNDEFINED;
10884 if ((Bit32 (opcode, 24) == Bit32 (opcode, 23)) && BitIsSet (opcode, 21))
10887 // // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
10888 // single_regs = TRUE; add = (U == Ô1Õ); wback = (W == Ô1Õ); d = UInt(Vd:D); n = UInt(Rn);
10889 single_regs = true;
10890 add = BitIsSet (opcode, 23);
10891 wback = BitIsSet (opcode, 21);
10892 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
10893 n = Bits32 (opcode, 19, 16);
10895 // imm32 = ZeroExtend(imm8:Õ00Õ, 32); regs = UInt(imm8);
10896 imm32 = Bits32 (opcode, 7, 0) << 2;
10897 regs = Bits32 (opcode, 7, 0);
10899 // if n == 15 && (wback || CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;
10900 if ((n == 15) && (wback || (CurrentInstrSet () != eModeARM)))
10903 // if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
10904 if ((regs == 0) || ((d + regs) > 32))
10913 RegisterInfo base_reg;
10914 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
10916 uint32_t Rn = ReadCoreReg (n, &success);
10920 // address = if add then R[n] else R[n]-imm32;
10925 address = Rn - imm32;
10927 EmulateInstruction::Context context;
10928 // if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
10933 value = Rn + imm32;
10935 value = Rn - imm32;
10937 context.type = eContextAdjustBaseRegister;
10938 context.SetRegisterPlusOffset (base_reg, value - Rn);
10940 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
10944 const uint32_t addr_byte_size = GetAddressByteSize();
10945 uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
10947 context.type = eContextRegisterStore;
10948 // for r = 0 to regs-1
10949 for (uint32_t r = 0; r < regs; ++r)
10954 // MemA[address,4] = S[d+r]; address = address+4;
10955 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d + r, 0, &success);
10959 RegisterInfo data_reg;
10960 GetRegisterInfo (eRegisterKindDWARF, start_reg + d + r, data_reg);
10961 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10962 if (!MemAWrite (context, address, data, addr_byte_size))
10965 address = address + 4;
10969 // // Store as two word-aligned words in the correct order for current endianness.
10970 // MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
10971 // MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
10972 uint64_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d + r, 0, &success);
10976 RegisterInfo data_reg;
10977 GetRegisterInfo (eRegisterKindDWARF, start_reg + d + r, data_reg);
10979 if (GetByteOrder() == eByteOrderBig)
10981 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10982 if (!MemAWrite (context, address, Bits64 (data, 63, 32), addr_byte_size))
10985 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
10986 if (!MemAWrite (context, address+ 4, Bits64 (data, 31, 0), addr_byte_size))
10991 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
10992 if (!MemAWrite (context, address, Bits64 (data, 31, 0), addr_byte_size))
10995 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
10996 if (!MemAWrite (context, address + 4, Bits64 (data, 63, 32), addr_byte_size))
10999 // address = address+8;
11000 address = address + 8;
11008 // This instruciton loads a single extension register fronm memory, using an address from an ARM core register, with
11009 // an optional offset.
11011 EmulateInstructionARM::EmulateVLDR (const uint32_t opcode, ARMEncoding encoding)
11014 if ConditionPassed() then
11015 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
11016 base = if n == 15 then Align(PC,4) else R[n];
11017 address = if add then (base + imm32) else (base - imm32);
11019 S[d] = MemA[address,4];
11021 word1 = MemA[address,4]; word2 = MemA[address+4,4];
11022 // Combine the word-aligned words in the correct order for current endianness.
11023 D[d] = if BigEndian() then word1:word2 else word2:word1;
11026 bool success = false;
11028 if (ConditionPassed (opcode))
11040 // single_reg = FALSE; add = (U == Ô1Õ); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
11041 single_reg = false;
11042 add = BitIsSet (opcode, 23);
11043 imm32 = Bits32 (opcode, 7, 0) << 2;
11045 // d = UInt(D:Vd); n = UInt(Rn);
11046 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11047 n = Bits32 (opcode, 19, 16);
11053 // single_reg = TRUE; add = (U == Ô1Õ); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
11055 add = BitIsSet (opcode, 23);
11056 imm32 = Bits32 (opcode, 7, 0) << 2;
11058 // d = UInt(Vd:D); n = UInt(Rn);
11059 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
11060 n = Bits32 (opcode, 19, 16);
11067 RegisterInfo base_reg;
11068 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11070 uint32_t Rn = ReadCoreReg (n, &success);
11074 // base = if n == 15 then Align(PC,4) else R[n];
11077 base = AlignPC (Rn);
11081 // address = if add then (base + imm32) else (base - imm32);
11084 address = base + imm32;
11086 address = base - imm32;
11088 const uint32_t addr_byte_size = GetAddressByteSize();
11089 uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0;
11091 EmulateInstruction::Context context;
11092 context.type = eContextRegisterLoad;
11093 context.SetRegisterPlusOffset (base_reg, address - base);
11097 // S[d] = MemA[address,4];
11098 uint32_t data = MemARead (context, address, addr_byte_size, 0, &success);
11102 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, start_reg + d, data))
11107 // word1 = MemA[address,4]; word2 = MemA[address+4,4];
11108 uint32_t word1 = MemARead (context, address, addr_byte_size, 0, &success);
11112 context.SetRegisterPlusOffset (base_reg, (address + 4) - base);
11113 uint32_t word2 = MemARead (context, address + 4, addr_byte_size, 0, &success);
11116 // // Combine the word-aligned words in the correct order for current endianness.
11117 // D[d] = if BigEndian() then word1:word2 else word2:word1;
11119 if (GetByteOrder() == eByteOrderBig)
11122 data64 = (data64 << 32) | word2;
11127 data64 = (data64 << 32) | word1;
11130 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, start_reg + d, data64))
11138 // This instruction stores a signle extension register to memory, using an address from an ARM core register, with an
11139 // optional offset.
11141 EmulateInstructionARM::EmulateVSTR (const uint32_t opcode, ARMEncoding encoding)
11144 if ConditionPassed() then
11145 EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(n);
11146 address = if add then (R[n] + imm32) else (R[n] - imm32);
11148 MemA[address,4] = S[d];
11150 // Store as two word-aligned words in the correct order for current endianness.
11151 MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11152 MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11155 bool success = false;
11157 if (ConditionPassed (opcode))
11169 // single_reg = FALSE; add = (U == Ô1Õ); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
11170 single_reg = false;
11171 add = BitIsSet (opcode, 23);
11172 imm32 = Bits32 (opcode, 7, 0) << 2;
11174 // d = UInt(D:Vd); n = UInt(Rn);
11175 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11176 n = Bits32 (opcode, 19, 16);
11178 // if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;
11179 if ((n == 15) && (CurrentInstrSet() != eModeARM))
11186 // single_reg = TRUE; add = (U == Ô1Õ); imm32 = ZeroExtend(imm8:Õ00Õ, 32);
11188 add = BitIsSet (opcode, 23);
11189 imm32 = Bits32 (opcode, 7, 0) << 2;
11191 // d = UInt(Vd:D); n = UInt(Rn);
11192 d = (Bits32 (opcode, 15, 12) << 1) | Bit32 (opcode, 22);
11193 n = Bits32 (opcode, 19, 16);
11195 // if n == 15 && CurrentInstrSet() != InstrSet_ARM then UNPREDICTABLE;
11196 if ((n == 15) && (CurrentInstrSet() != eModeARM))
11205 RegisterInfo base_reg;
11206 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11208 uint32_t Rn = ReadCoreReg (n, &success);
11212 // address = if add then (R[n] + imm32) else (R[n] - imm32);
11215 address = Rn + imm32;
11217 address = Rn - imm32;
11219 const uint32_t addr_byte_size = GetAddressByteSize();
11220 uint32_t start_reg = single_reg ? dwarf_s0 : dwarf_d0;
11222 RegisterInfo data_reg;
11223 GetRegisterInfo (eRegisterKindDWARF, start_reg + d, data_reg);
11224 EmulateInstruction::Context context;
11225 context.type = eContextRegisterStore;
11226 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11230 // MemA[address,4] = S[d];
11231 uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d, 0, &success);
11235 if (!MemAWrite (context, address, data, addr_byte_size))
11240 // // Store as two word-aligned words in the correct order for current endianness.
11241 // MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11242 // MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11243 uint64_t data = ReadRegisterUnsigned (eRegisterKindDWARF, start_reg + d, 0, &success);
11247 if (GetByteOrder() == eByteOrderBig)
11249 if (!MemAWrite (context, address, Bits64 (data, 63, 32), addr_byte_size))
11252 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11253 if (!MemAWrite (context, address + 4, Bits64 (data, 31, 0), addr_byte_size))
11258 if (!MemAWrite (context, address, Bits64 (data, 31, 0), addr_byte_size))
11261 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, (address + 4) - Rn);
11262 if (!MemAWrite (context, address + 4, Bits64 (data, 63, 32), addr_byte_size))
11270 // A8.6.307 VLDI1 (multiple single elements)
11271 // This instruction loads elements from memory into one, two, three or four registers, without de-interleaving. Every
11272 // element of each register is loaded.
11274 EmulateInstructionARM::EmulateVLD1Multiple (const uint32_t opcode, ARMEncoding encoding)
11277 if ConditionPassed() then
11278 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11279 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11280 if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11281 for r = 0 to regs-1
11282 for e = 0 to elements-1
11283 Elem[D[d+r],e,esize] = MemU[address,ebytes];
11284 address = address + ebytes;
11287 bool success = false;
11289 if (ConditionPassed (opcode))
11292 uint32_t alignment;
11300 bool register_index;
11309 // regs = 1; if align<1> == Ô1Õ then UNDEFINED;
11311 // regs = 2; if align == Ô11Õ then UNDEFINED;
11313 // regs = 3; if align<1> == Ô1Õ then UNDEFINED;
11317 // SEE ÒRelated encodingsÓ;
11318 uint32_t type = Bits32 (opcode, 11, 8);
11319 uint32_t align = Bits32 (opcode, 5, 4);
11320 if (type == 7) // '0111'
11323 if (BitIsSet (align, 1))
11326 else if (type == 10) // '1010'
11333 else if (type == 6) // '0110'
11336 if (BitIsSet (align, 1))
11339 else if (type == 2) // '0010'
11346 // alignment = if align == Ô00Õ then 1 else 4 << UInt(align);
11350 alignment = 4 << align;
11352 // ebytes = 1 << UInt(size); esize = 8 * ebytes; elements = 8 DIV ebytes;
11353 ebytes = 1 << Bits32 (opcode, 7, 6);
11354 esize = 8 * ebytes;
11355 elements = 8 / ebytes;
11357 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11358 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11359 n = Bits32 (opcode, 19, 15);
11360 m = Bits32 (opcode, 3, 0);
11362 // wback = (m != 15); register_index = (m != 15 && m != 13);
11364 register_index = ((m != 15) && (m != 13));
11366 // if d+regs > 32 then UNPREDICTABLE;
11367 if ((d + regs) > 32)
11376 RegisterInfo base_reg;
11377 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11379 uint32_t Rn = ReadCoreReg (n, &success);
11383 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11384 addr_t address = Rn;
11385 if ((address % alignment) != 0)
11388 EmulateInstruction::Context context;
11389 // if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11392 uint32_t Rm = ReadCoreReg (m, &success);
11397 if (register_index)
11402 uint32_t value = Rn + offset;
11403 context.type = eContextAdjustBaseRegister;
11404 context.SetRegisterPlusOffset (base_reg, offset);
11406 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
11411 // for r = 0 to regs-1
11412 for (uint32_t r = 0; r < regs; ++r)
11414 // for e = 0 to elements-1
11415 uint64_t assembled_data = 0;
11416 for (uint32_t e = 0; e < elements; ++e)
11418 // Elem[D[d+r],e,esize] = MemU[address,ebytes];
11419 context.type = eContextRegisterLoad;
11420 context.SetRegisterPlusOffset (base_reg, address - Rn);
11421 uint64_t data = MemURead (context, address, ebytes, 0, &success);
11425 assembled_data = (data << (e * esize)) | assembled_data; // New data goes to the left of existing data
11427 // address = address + ebytes;
11428 address = address + ebytes;
11430 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_d0 + d + r, assembled_data))
11437 // A8.6.308 VLD1 (single element to one lane)
11440 EmulateInstructionARM::EmulateVLD1Single (const uint32_t opcode, const ARMEncoding encoding)
11443 if ConditionPassed() then
11444 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11445 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11446 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11447 Elem[D[d],index,esize] = MemU[address,ebytes];
11450 bool success = false;
11452 if (ConditionPassed (opcode))
11457 uint32_t alignment;
11462 bool register_index;
11469 uint32_t size = Bits32 (opcode, 11, 10);
11470 uint32_t index_align = Bits32 (opcode, 7, 4);
11471 // if size == Ô11Õ then SEE VLD1 (single element to all lanes);
11473 return EmulateVLD1SingleAll (opcode, encoding);
11475 if (size == 0) // when '00'
11477 // if index_align<0> != Ô0Õ then UNDEFINED;
11478 if (BitIsClear (index_align, 0))
11481 // ebytes = 1; esize = 8; index = UInt(index_align<3:1>); alignment = 1;
11484 index = Bits32 (index_align, 3, 1);
11487 else if (size == 1) // when Ô01Õ
11489 // if index_align<1> != Ô0Õ then UNDEFINED;
11490 if (BitIsClear (index_align, 1))
11493 // ebytes = 2; esize = 16; index = UInt(index_align<3:2>);
11496 index = Bits32 (index_align, 3, 2);
11498 // alignment = if index_align<0> == Ô0Õ then 1 else 2;
11499 if (BitIsClear (index_align, 0))
11504 else if (size == 2) // when Ô10Õ
11506 // if index_align<2> != Ô0Õ then UNDEFINED;
11507 if (BitIsClear (index_align, 2))
11510 // if index_align<1:0> != Ô00Õ && index_align<1:0> != Ô11Õ then UNDEFINED;
11511 if ((Bits32 (index_align, 1, 0) != 0) && (Bits32 (index_align, 1, 0) != 3))
11514 // ebytes = 4; esize = 32; index = UInt(index_align<3>);
11517 index = Bit32 (index_align, 3);
11519 // alignment = if index_align<1:0> == Ô00Õ then 1 else 4;
11520 if (Bits32 (index_align, 1, 0) == 0)
11529 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11530 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11531 n = Bits32 (opcode, 19, 16);
11532 m = Bits32 (opcode, 3, 0);
11534 // wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE;
11536 register_index = ((m != 15) && (m != 13));
11548 RegisterInfo base_reg;
11549 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11551 uint32_t Rn = ReadCoreReg (n, &success);
11555 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11556 addr_t address = Rn;
11557 if ((address % alignment) != 0)
11560 EmulateInstruction::Context context;
11561 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11564 uint32_t Rm = ReadCoreReg (m, &success);
11569 if (register_index)
11574 uint32_t value = Rn + offset;
11576 context.type = eContextAdjustBaseRegister;
11577 context.SetRegisterPlusOffset (base_reg, offset);
11579 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
11583 // Elem[D[d],index,esize] = MemU[address,ebytes];
11584 uint32_t element = MemURead (context, address, esize, 0, &success);
11588 element = element << (index * esize);
11590 uint64_t reg_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_d0 + d, 0, &success);
11594 uint64_t all_ones = -1;
11595 uint64_t mask = all_ones << ((index+1) * esize); // mask is all 1's to left of where 'element' goes, & all 0's
11596 // at element & to the right of element.
11598 mask = mask | Bits64 (all_ones, (index * esize) - 1, 0); // add 1's to the right of where 'element' goes.
11599 // now mask should be 0's where element goes & 1's
11600 // everywhere else.
11602 uint64_t masked_reg = reg_data & mask; // Take original reg value & zero out 'element' bits
11603 reg_data = masked_reg & element; // Put 'element' into those bits in reg_data.
11605 context.type = eContextRegisterLoad;
11606 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, reg_data))
11612 // A8.6.391 VST1 (multiple single elements)
11613 // Vector Store (multiple single elements) stores elements to memory from one, two, three, or four regsiters, without
11614 // interleaving. Every element of each register is stored.
11616 EmulateInstructionARM::EmulateVST1Multiple (const uint32_t opcode, ARMEncoding encoding)
11619 if ConditionPassed() then
11620 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11621 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11622 if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11623 for r = 0 to regs-1
11624 for e = 0 to elements-1
11625 MemU[address,ebytes] = Elem[D[d+r],e,esize];
11626 address = address + ebytes;
11629 bool success = false;
11631 if (ConditionPassed (opcode))
11634 uint32_t alignment;
11642 bool register_index;
11649 uint32_t type = Bits32 (opcode, 11, 8);
11650 uint32_t align = Bits32 (opcode, 5, 4);
11653 if (type == 7) // when Ô0111Õ
11655 // regs = 1; if align<1> == Ô1Õ then UNDEFINED;
11657 if (BitIsSet (align, 1))
11660 else if (type == 10) // when Ô1010Õ
11662 // regs = 2; if align == Ô11Õ then UNDEFINED;
11667 else if (type == 6) // when Ô0110Õ
11669 // regs = 3; if align<1> == Ô1Õ then UNDEFINED;
11671 if (BitIsSet (align, 1))
11674 else if (type == 2) // when Ô0010Õ
11678 // SEE ÒRelated encodingsÓ;
11681 // alignment = if align == Ô00Õ then 1 else 4 << UInt(align);
11685 alignment = 4 << align;
11687 // ebytes = 1 << UInt(size); esize = 8 * ebytes; elements = 8 DIV ebytes;
11688 ebytes = 1 << Bits32 (opcode,7, 6);
11689 esize = 8 * ebytes;
11690 elements = 8 / ebytes;
11692 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11693 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11694 n = Bits32 (opcode, 19, 16);
11695 m = Bits32 (opcode, 3, 0);
11697 // wback = (m != 15); register_index = (m != 15 && m != 13);
11699 register_index = ((m != 15) && (m != 13));
11701 // if d+regs > 32 then UNPREDICTABLE; if n == 15 then UNPREDICTABLE;
11702 if ((d + regs) > 32)
11715 RegisterInfo base_reg;
11716 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11718 uint32_t Rn = ReadCoreReg (n, &success);
11722 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11723 addr_t address = Rn;
11724 if ((address % alignment) != 0)
11727 EmulateInstruction::Context context;
11728 // if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
11731 uint32_t Rm = ReadCoreReg (m, &success);
11736 if (register_index)
11741 context.type = eContextAdjustBaseRegister;
11742 context.SetRegisterPlusOffset (base_reg, offset);
11744 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
11748 RegisterInfo data_reg;
11749 context.type = eContextRegisterStore;
11750 // for r = 0 to regs-1
11751 for (uint32_t r = 0; r < regs; ++r)
11753 GetRegisterInfo (eRegisterKindDWARF, dwarf_d0 + d + r, data_reg);
11754 uint64_t register_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_d0 + d + r, 0, &success);
11758 // for e = 0 to elements-1
11759 for (uint32_t e = 0; e < elements; ++e)
11761 // MemU[address,ebytes] = Elem[D[d+r],e,esize];
11762 uint64_t word = Bits64 (register_data, ((e + 1) * esize) - 1, e * esize);
11764 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11765 if (!MemUWrite (context, address, word, ebytes))
11768 // address = address + ebytes;
11769 address = address + ebytes;
11776 // A8.6.392 VST1 (single element from one lane)
11777 // This instruction stores one element to memory from one element of a register.
11779 EmulateInstructionARM::EmulateVST1Single (const uint32_t opcode, ARMEncoding encoding)
11782 if ConditionPassed() then
11783 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11784 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11785 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11786 MemU[address,ebytes] = Elem[D[d],index,esize];
11789 bool success = false;
11791 if (ConditionPassed (opcode))
11796 uint32_t alignment;
11801 bool register_index;
11808 uint32_t size = Bits32 (opcode, 11, 10);
11809 uint32_t index_align = Bits32 (opcode, 7, 4);
11811 // if size == Ô11Õ then UNDEFINED;
11816 if (size == 0) // when Ô00Õ
11818 // if index_align<0> != Ô0Õ then UNDEFINED;
11819 if (BitIsClear (index_align, 0))
11821 // ebytes = 1; esize = 8; index = UInt(index_align<3:1>); alignment = 1;
11824 index = Bits32 (index_align, 3, 1);
11827 else if (size == 1) // when Ô01Õ
11829 // if index_align<1> != Ô0Õ then UNDEFINED;
11830 if (BitIsClear (index_align, 1))
11833 // ebytes = 2; esize = 16; index = UInt(index_align<3:2>);
11836 index = Bits32 (index_align, 3, 2);
11838 // alignment = if index_align<0> == Ô0Õ then 1 else 2;
11839 if (BitIsClear (index_align, 0))
11844 else if (size == 2) // when Ô10Õ
11846 // if index_align<2> != Ô0Õ then UNDEFINED;
11847 if (BitIsClear (index_align, 2))
11850 // if index_align<1:0> != Ô00Õ && index_align<1:0> != Ô11Õ then UNDEFINED;
11851 if ((Bits32 (index_align, 1, 0) != 0) && (Bits32 (index_align, 1, 0) != 3))
11854 // ebytes = 4; esize = 32; index = UInt(index_align<3>);
11857 index = Bit32 (index_align, 3);
11859 // alignment = if index_align<1:0> == Ô00Õ then 1 else 4;
11860 if (Bits32 (index_align, 1, 0) == 0)
11869 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11870 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11871 n = Bits32 (opcode, 19, 16);
11872 m = Bits32 (opcode, 3, 0);
11874 // wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 then UNPREDICTABLE;
11876 register_index = ((m != 15) && (m != 13));
11887 RegisterInfo base_reg;
11888 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
11890 uint32_t Rn = ReadCoreReg (n, &success);
11894 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11895 addr_t address = Rn;
11896 if ((address % alignment) != 0)
11899 EmulateInstruction::Context context;
11900 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11903 uint32_t Rm = ReadCoreReg (m, &success);
11908 if (register_index)
11913 context.type = eContextAdjustBaseRegister;
11914 context.SetRegisterPlusOffset (base_reg, offset);
11916 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
11920 // MemU[address,ebytes] = Elem[D[d],index,esize];
11921 uint64_t register_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_d0 + d, 0, &success);
11925 uint64_t word = Bits64 (register_data, ((index + 1) * esize) - 1, index * esize);
11927 RegisterInfo data_reg;
11928 GetRegisterInfo (eRegisterKindDWARF, dwarf_d0 + d, data_reg);
11929 context.type = eContextRegisterStore;
11930 context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn);
11932 if (!MemUWrite (context, address, word, ebytes))
11938 // A8.6.309 VLD1 (single element to all lanes)
11939 // This instruction loads one element from memory into every element of one or two vectors.
11941 EmulateInstructionARM::EmulateVLD1SingleAll (const uint32_t opcode, const ARMEncoding encoding)
11944 if ConditionPassed() then
11945 EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
11946 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11947 if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
11948 replicated_element = Replicate(MemU[address,ebytes], elements);
11949 for r = 0 to regs-1
11950 D[d+r] = replicated_element;
11953 bool success = false;
11955 if (ConditionPassed (opcode))
11960 uint32_t alignment;
11965 bool register_index;
11972 //if size == Ô11Õ || (size == Ô00Õ && a == Ô1Õ) then UNDEFINED;
11973 uint32_t size = Bits32 (opcode, 7, 6);
11974 if ((size == 3) || ((size == 0) && BitIsSet (opcode, 4)))
11977 //ebytes = 1 << UInt(size); elements = 8 DIV ebytes; regs = if T == Ô0Õ then 1 else 2;
11978 ebytes = 1 << size;
11979 elements = 8 / ebytes;
11980 if (BitIsClear (opcode, 5))
11985 //alignment = if a == Ô0Õ then 1 else ebytes;
11986 if (BitIsClear (opcode, 4))
11989 alignment = ebytes;
11991 //d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11992 d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
11993 n = Bits32 (opcode, 19, 16);
11994 m = Bits32 (opcode, 3, 0);
11996 //wback = (m != 15); register_index = (m != 15 && m != 13);
11998 register_index = ((m != 15) && (m != 13));
12000 //if d+regs > 32 then UNPREDICTABLE; if n == 15 then UNPREDICTABLE;
12001 if ((d + regs) > 32)
12013 RegisterInfo base_reg;
12014 GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
12016 uint32_t Rn = ReadCoreReg (n, &success);
12020 // address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
12021 addr_t address = Rn;
12022 if ((address % alignment) != 0)
12025 EmulateInstruction::Context context;
12026 // if wback then R[n] = R[n] + (if register_index then R[m] else ebytes);
12029 uint32_t Rm = ReadCoreReg (m, &success);
12034 if (register_index)
12039 context.type = eContextAdjustBaseRegister;
12040 context.SetRegisterPlusOffset (base_reg, offset);
12042 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, Rn + offset))
12046 // replicated_element = Replicate(MemU[address,ebytes], elements);
12048 context.type = eContextRegisterLoad;
12049 uint64_t word = MemURead (context, address, ebytes, 0, &success);
12053 uint64_t replicated_element = 0;
12054 uint32_t esize = ebytes * 8;
12055 for (uint32_t e = 0; e < elements; ++e)
12056 replicated_element = (replicated_element << esize) | Bits64 (word, esize - 1, 0);
12058 // for r = 0 to regs-1
12059 for (uint32_t r = 0; r < regs; ++r)
12061 // D[d+r] = replicated_element;
12062 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_d0 + d + r, replicated_element))
12069 // B6.2.13 SUBS PC, LR and related instructions
12070 //The SUBS PC, LR, #<const? instruction provides an exception return without the use of the stack. It subtracts the
12071 // immediate constant from the LR, branches to the resulting address, and also copies the SPSR to the CPSR.
12073 EmulateInstructionARM::EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncoding encoding)
12076 if ConditionPassed() then
12077 EncodingSpecificOperations();
12078 if CurrentInstrSet() == InstrSet_ThumbEE then
12080 operand2 = if register_form then Shift(R[m], shift_t, shift_n, APSR.C) else imm32;
12082 when Ô0000Õ result = R[n] AND operand2; // AND
12083 when Ô0001Õ result = R[n] EOR operand2; // EOR
12084 when Ô0010Õ (result, -, -) = AddWithCarry(R[n], NOT(operand2), Ô1Õ); // SUB
12085 when Ô0011Õ (result, -, -) = AddWithCarry(NOT(R[n]), operand2, Ô1Õ); // RSB
12086 when Ô0100Õ (result, -, -) = AddWithCarry(R[n], operand2, Ô0Õ); // ADD
12087 when Ô0101Õ (result, -, -) = AddWithCarry(R[n], operand2, APSR.c); // ADC
12088 when Ô0110Õ (result, -, -) = AddWithCarry(R[n], NOT(operand2), APSR.C); // SBC
12089 when Ô0111Õ (result, -, -) = AddWithCarry(NOT(R[n]), operand2, APSR.C); // RSC
12090 when Ô1100Õ result = R[n] OR operand2; // ORR
12091 when Ô1101Õ result = operand2; // MOV
12092 when Ô1110Õ result = R[n] AND NOT(operand2); // BIC
12093 when Ô1111Õ result = NOT(operand2); // MVN
12094 CPSRWriteByInstr(SPSR[], Ô1111Õ, TRUE);
12095 BranchWritePC(result);
12098 bool success = false;
12100 if (ConditionPassed (opcode))
12105 bool register_form;
12106 ARM_ShifterType shift_t;
12113 // if CurrentInstrSet() == InstrSet_ThumbEE then UNPREDICTABLE
12114 // n = 14; imm32 = ZeroExtend(imm8, 32); register_form = FALSE; opcode = Ô0010Õ; // = SUB
12116 imm32 = Bits32 (opcode, 7, 0);
12117 register_form = false;
12120 // if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
12121 if (InITBlock() && !LastInITBlock())
12127 // n = UInt(Rn); imm32 = ARMExpandImm(imm12); register_form = FALSE;
12128 n = Bits32 (opcode, 19, 16);
12129 imm32 = ARMExpandImm (opcode);
12130 register_form = false;
12131 code = Bits32 (opcode, 24, 21);
12136 // n = UInt(Rn); m = UInt(Rm); register_form = TRUE;
12137 n = Bits32 (opcode, 19, 16);
12138 m = Bits32 (opcode, 3, 0);
12139 register_form = true;
12141 // (shift_t, shift_n) = DecodeImmShift(type, imm5);
12142 shift_n = DecodeImmShiftARM (opcode, shift_t);
12150 // operand2 = if register_form then Shift(R[m], shift_t, shift_n, APSR.C) else imm32;
12154 uint32_t Rm = ReadCoreReg (m, &success);
12158 operand2 = Shift (Rm, shift_t, shift_n, APSR_C, &success);
12167 uint32_t Rn = ReadCoreReg (n, &success);
12171 AddWithCarryResult result;
12176 case 0: // when Ô0000Õ
12177 // result = R[n] AND operand2; // AND
12178 result.result = Rn & operand2;
12181 case 1: // when Ô0001Õ
12182 // result = R[n] EOR operand2; // EOR
12183 result.result = Rn ^ operand2;
12186 case 2: // when Ô0010Õ
12187 // (result, -, -) = AddWithCarry(R[n], NOT(operand2), Ô1Õ); // SUB
12188 result = AddWithCarry (Rn, ~(operand2), 1);
12191 case 3: // when Ô0011Õ
12192 // (result, -, -) = AddWithCarry(NOT(R[n]), operand2, Ô1Õ); // RSB
12193 result = AddWithCarry (~(Rn), operand2, 1);
12196 case 4: // when Ô0100Õ
12197 // (result, -, -) = AddWithCarry(R[n], operand2, Ô0Õ); // ADD
12198 result = AddWithCarry (Rn, operand2, 0);
12201 case 5: // when Ô0101Õ
12202 // (result, -, -) = AddWithCarry(R[n], operand2, APSR.c); // ADC
12203 result = AddWithCarry (Rn, operand2, APSR_C);
12206 case 6: // when Ô0110Õ
12207 // (result, -, -) = AddWithCarry(R[n], NOT(operand2), APSR.C); // SBC
12208 result = AddWithCarry (Rn, ~(operand2), APSR_C);
12211 case 7: // when Ô0111Õ
12212 // (result, -, -) = AddWithCarry(NOT(R[n]), operand2, APSR.C); // RSC
12213 result = AddWithCarry (~(Rn), operand2, APSR_C);
12216 case 10: // when Ô1100Õ
12217 // result = R[n] OR operand2; // ORR
12218 result.result = Rn | operand2;
12221 case 11: // when Ô1101Õ
12222 // result = operand2; // MOV
12223 result.result = operand2;
12226 case 12: // when Ô1110Õ
12227 // result = R[n] AND NOT(operand2); // BIC
12228 result.result = Rn & ~(operand2);
12231 case 15: // when Ô1111Õ
12232 // result = NOT(operand2); // MVN
12233 result.result = ~(operand2);
12239 // CPSRWriteByInstr(SPSR[], Ô1111Õ, TRUE);
12241 // For now, in emulation mode, we don't have access to the SPSR, so we will use the CPSR instead, and hope for
12243 uint32_t spsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_cpsr, 0, &success);
12247 CPSRWriteByInstr (spsr, 15, true);
12249 // BranchWritePC(result);
12250 EmulateInstruction::Context context;
12251 context.type = eContextAdjustPC;
12252 context.SetImmediate (result.result);
12254 BranchWritePC (context, result.result);
12259 EmulateInstructionARM::ARMOpcode*
12260 EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode, uint32_t arm_isa)
12265 //----------------------------------------------------------------------
12266 // Prologue instructions
12267 //----------------------------------------------------------------------
12269 // push register(s)
12270 { 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulatePUSH, "push <registers>" },
12271 { 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulatePUSH, "push <register>" },
12273 // set r7 to point to a stack offset
12274 { 0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRdSPImm, "add r7, sp, #<const>" },
12275 { 0x0ffff000, 0x024c7000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBR7IPImm, "sub r7, ip, #<const>"},
12276 // copy the stack pointer to ip
12277 { 0x0fffffff, 0x01a0c00d, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdSP, "mov ip, sp" },
12278 { 0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRdSPImm, "add ip, sp, #<const>" },
12279 { 0x0ffff000, 0x024dc000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBIPSPImm, "sub ip, sp, #<const>"},
12281 // adjust the stack pointer
12282 { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #<const>"},
12283 { 0x0fef0010, 0x004d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" },
12285 // push one register
12286 // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH;
12287 { 0x0e5f0000, 0x040d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!" },
12289 // vector push consecutive extension register(s)
12290 { 0x0fbf0f00, 0x0d2d0b00, ARMV6T2_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"},
12291 { 0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"},
12293 //----------------------------------------------------------------------
12294 // Epilogue instructions
12295 //----------------------------------------------------------------------
12297 { 0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop <registers>"},
12298 { 0x0fff0fff, 0x049d0004, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop <register>"},
12299 { 0x0fbf0f00, 0x0cbd0b00, ARMV6T2_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"},
12300 { 0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"},
12302 //----------------------------------------------------------------------
12303 // Supervisor Call (previously Software Interrupt)
12304 //----------------------------------------------------------------------
12305 { 0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSVC, "svc #imm24"},
12307 //----------------------------------------------------------------------
12308 // Branch instructions
12309 //----------------------------------------------------------------------
12310 { 0x0f000000, 0x0a000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateB, "b #imm24"},
12311 // To resolve ambiguity, "blx <label>" should come before "bl <label>".
12312 { 0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"},
12313 { 0x0f000000, 0x0b000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"},
12314 { 0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
12315 // for example, "bx lr"
12316 { 0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
12318 { 0x0ffffff0, 0x012fff20, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
12320 //----------------------------------------------------------------------
12321 // Data-processing instructions
12322 //----------------------------------------------------------------------
12324 { 0x0fe00000, 0x02a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"},
12326 { 0x0fe00010, 0x00a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12328 { 0x0fe00000, 0x02800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmARM, "add{s}<c> <Rd>, <Rn>, #const"},
12330 { 0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDReg, "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12331 // add (register-shifted register)
12332 { 0x0fe00090, 0x00800010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDRegShift, "add{s}<c> <Rd>, <Rn>, <Rm>, <type> <RS>"},
12334 { 0x0fff0000, 0x028f0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12335 { 0x0fff0000, 0x024f0000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12337 { 0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"},
12339 { 0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12341 { 0x0fe00000, 0x03c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #const"},
12343 { 0x0fe00010, 0x01c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12345 { 0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"},
12347 { 0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12349 { 0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"},
12351 { 0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12353 { 0x0fe00000, 0x02600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c> <Rd>, <Rn>, #<const>"},
12355 { 0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12357 { 0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"},
12359 { 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12361 { 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12363 { 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12364 // sub (immediate, ARM)
12365 { 0x0fe00000, 0x02400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmARM, "sub{s}<c> <Rd>, <Rn>, #<const>"},
12366 // sub (sp minus immediate)
12367 { 0x0fef0000, 0x024d0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}<c> <Rd>, sp, #<const>"},
12369 { 0x0fe00010, 0x00400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"},
12371 { 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #const"},
12373 { 0x0ff0f010, 0x01300000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12375 { 0x0ff0f000, 0x03100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #const"},
12377 { 0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rn>, <Rm> {,<shift>}"},
12380 { 0x0fef0000, 0x03a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c> <Rd>, #<const>"},
12381 { 0x0ff00000, 0x03000000, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>, #<imm16>" },
12383 { 0x0fef0ff0, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"},
12385 { 0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s}<c> <Rd>, #<const>"},
12387 { 0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c> <Rd>, <Rm> {,<shift>}"},
12389 { 0x0ff0f000, 0x03700000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"},
12391 { 0x0ff0f010, 0x01700000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
12393 { 0x0ff0f000, 0x03500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #<const>"},
12395 { 0x0ff0f010, 0x01500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm> {,<shift>}"},
12397 { 0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"},
12399 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
12401 { 0x0fef0070, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"},
12403 { 0x0fef00f0, 0x01a00010, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
12405 { 0x0fef0070, 0x01a00020, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"},
12407 { 0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
12408 // rrx is a special case encoding of ror (immediate)
12409 { 0x0fef0ff0, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"},
12411 { 0x0fef0070, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"},
12413 { 0x0fef00f0, 0x01a00070, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
12415 { 0x0fe000f0, 0x00000090, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>" },
12417 // subs pc, lr and related instructions
12418 { 0x0e10f000, 0x0210f000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,#<const> | <Rn>,#<const>" },
12419 { 0x0e10f010, 0x0010f000, ARMvAll, eEncodingA2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "<opc>S<c> PC,<Rn>,<Rm{,<shift>}" },
12421 //----------------------------------------------------------------------
12422 // Load instructions
12423 //----------------------------------------------------------------------
12424 { 0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" },
12425 { 0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>" },
12426 { 0x0fd00000, 0x09100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" },
12427 { 0x0fd00000, 0x09900000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>" },
12428 { 0x0e500000, 0x04100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRImmediateARM, "ldr<c> <Rt> [<Rn> {#+/-<imm12>}]" },
12429 { 0x0e500010, 0x06100000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}" },
12430 { 0x0e5f0000, 0x045f0000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"},
12431 { 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" },
12432 { 0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
12433 { 0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12434 { 0x0e5000f0, 0x005000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>, [<Rn>{,#+/-<imm8>}]" },
12435 { 0x0e5f00f0, 0x005f00d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt> <label>" },
12436 { 0x0e5000f0, 0x001000d0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12437 { 0x0e5000f0, 0x005000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>{,#+/-<imm8>}]"},
12438 { 0x0e5f00f0, 0x005f00f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" },
12439 { 0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
12440 { 0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
12441 { 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12442 { 0x0e100f00, 0x0c100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12443 { 0x0e100f00, 0x0c100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12444 { 0x0f300f00, 0x0d100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12445 { 0x0f300f00, 0x0d100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
12446 { 0xffb00000, 0xf4200000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12447 { 0xffb00300, 0xf4a00000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Single, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12448 { 0xffb00f00, 0xf4a00c00, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12450 //----------------------------------------------------------------------
12451 // Store instructions
12452 //----------------------------------------------------------------------
12453 { 0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" },
12454 { 0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDA, "stmda<c> <Rn>{!} <registers>" },
12455 { 0x0fd00000, 0x09000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" },
12456 { 0x0fd00000, 0x09800000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMIB, "stmib<c> <Rn>{!} <registers>" },
12457 { 0x0e500010, 0x06000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> [<Rn> +/-<Rm> {<shift>}]{!}" },
12458 { 0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,+/-<Rm>[{!}" },
12459 { 0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
12460 { 0x0e500000, 0x04400000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBImmARM, "strb<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12461 { 0x0e500000, 0x04000000, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRImmARM, "str<c> <Rt>,[<Rn>,#+/-<imm12>]!"},
12462 { 0x0e5000f0, 0x004000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"},
12463 { 0x0e500ff0, 0x000000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDReg, "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
12464 { 0x0e100f00, 0x0c000b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!} <list>"},
12465 { 0x0e100f00, 0x0c000a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!} <list>"},
12466 { 0x0f300f00, 0x0d000b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Dd> [<Rn>{,#+/-<imm>}]"},
12467 { 0x0f300f00, 0x0d000a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Sd> [<Rn>{,#+/-<imm>}]"},
12468 { 0xffb00000, 0xf4000000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Multiple, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12469 { 0xffb00300, 0xf4800000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12471 //----------------------------------------------------------------------
12472 // Other instructions
12473 //----------------------------------------------------------------------
12474 { 0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}" },
12475 { 0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}" },
12476 { 0x0fff00f0, 0x06ef0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}" },
12477 { 0x0fff00f0, 0x06ff0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}" },
12478 { 0xfe500000, 0xf8100000, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{<amode>} <Rn>{!}" }
12481 static const size_t k_num_arm_opcodes = sizeof(g_arm_opcodes)/sizeof(ARMOpcode);
12483 for (size_t i=0; i<k_num_arm_opcodes; ++i)
12485 if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value &&
12486 (g_arm_opcodes[i].variants & arm_isa) != 0)
12487 return &g_arm_opcodes[i];
12493 EmulateInstructionARM::ARMOpcode*
12494 EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode, uint32_t arm_isa)
12498 g_thumb_opcodes[] =
12500 //----------------------------------------------------------------------
12501 // Prologue instructions
12502 //----------------------------------------------------------------------
12504 // push register(s)
12505 { 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulatePUSH, "push <registers>" },
12506 { 0xffff0000, 0xe92d0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulatePUSH, "push.w <registers>" },
12507 { 0xffff0fff, 0xf84d0d04, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulatePUSH, "push.w <register>" },
12509 // set r7 to point to a stack offset
12510 { 0xffffff00, 0x0000af00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDRdSPImm, "add r7, sp, #imm" },
12511 // copy the stack pointer to r7
12512 { 0xffffffff, 0x0000466f, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdSP, "mov r7, sp" },
12513 // move from high register to low register (comes after "mov r7, sp" to resolve ambiguity)
12514 { 0xffffffc0, 0x00004640, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVLowHigh, "mov r0-r7, r8-r15" },
12516 // PC-relative load into register (see also EmulateADDSPRm)
12517 { 0xfffff800, 0x00004800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"},
12519 // adjust the stack pointer
12520 { 0xffffff87, 0x00004485, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPRm, "add sp, <Rm>"},
12521 { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #imm"},
12522 { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub.w sp, sp, #<const>"},
12523 { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw sp, sp, #imm12"},
12524 { 0xffef8000, 0xebad0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}" },
12526 // vector push consecutive extension register(s)
12527 { 0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"},
12528 { 0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"},
12530 //----------------------------------------------------------------------
12531 // Epilogue instructions
12532 //----------------------------------------------------------------------
12534 { 0xfffff800, 0x0000a800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"},
12535 { 0xffffff80, 0x0000b000, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDSPImm, "add sp, #imm"},
12536 { 0xfffffe00, 0x0000bc00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulatePOP, "pop <registers>"},
12537 { 0xffff0000, 0xe8bd0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop.w <registers>" },
12538 { 0xffff0fff, 0xf85d0d04, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulatePOP, "pop.w <register>" },
12539 { 0xffbf0f00, 0xecbd0b00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"},
12540 { 0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"},
12542 //----------------------------------------------------------------------
12543 // Supervisor Call (previously Software Interrupt)
12544 //----------------------------------------------------------------------
12545 { 0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSVC, "svc #imm8"},
12547 //----------------------------------------------------------------------
12548 // If Then makes up to four following instructions conditional.
12549 //----------------------------------------------------------------------
12550 // The next 5 opcode _must_ come before the if then instruction
12551 { 0xffffffff, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop"},
12552 { 0xffffffff, 0x0000bf10, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop YIELD (yield hint)"},
12553 { 0xffffffff, 0x0000bf20, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop WFE (wait for event hint)"},
12554 { 0xffffffff, 0x0000bf30, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop WFI (wait for interrupt hint)"},
12555 { 0xffffffff, 0x0000bf40, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateNop, "nop SEV (send event hint)"},
12556 { 0xffffff00, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"},
12558 //----------------------------------------------------------------------
12559 // Branch instructions
12560 //----------------------------------------------------------------------
12561 // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8".
12562 { 0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"},
12563 { 0xfffff800, 0x0000e000, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateB, "b<c> #imm11 (outside or last in IT)"},
12564 { 0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"},
12565 { 0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside or last in IT)"},
12567 { 0xf800d000, 0xf000d000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"},
12569 { 0xf800d001, 0xf000c000, ARMV5_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"},
12570 { 0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
12571 // for example, "bx lr"
12572 { 0xffffff87, 0x00004700, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
12574 { 0xfff0ffff, 0xf3c08f00, ARMV5J_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
12575 // compare and branch
12576 { 0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"},
12577 // table branch byte
12578 { 0xfff0fff0, 0xe8d0f000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbb<c> <Rn>, <Rm>"},
12579 // table branch halfword
12580 { 0xfff0fff0, 0xe8d0f010, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"},
12582 //----------------------------------------------------------------------
12583 // Data-processing instructions
12584 //----------------------------------------------------------------------
12586 { 0xfbe08000, 0xf1400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"},
12588 { 0xffffffc0, 0x00004140, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADCReg, "adcs|adc<c> <Rdn>, <Rm>"},
12589 { 0xffe08000, 0xeb400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADCReg, "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12591 { 0xfffffe00, 0x00001800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
12592 // Make sure "add sp, <Rm>" comes before this instruction, so there's no ambiguity decoding the two.
12593 { 0xffffff00, 0x00004400, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDReg, "add<c> <Rdn>, <Rm>"},
12595 { 0xfffff800, 0x0000a000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12596 { 0xfbff8000, 0xf2af0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12597 { 0xfbff8000, 0xf20f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12599 { 0xfbe08000, 0xf0000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #<const>"},
12601 { 0xffffffc0, 0x00004000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateANDReg, "ands|and<c> <Rdn>, <Rm>"},
12602 { 0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateANDReg, "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12604 { 0xfbe08000, 0xf0200000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #<const>"},
12606 { 0xffffffc0, 0x00004380, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateBICReg, "bics|bic<c> <Rdn>, <Rm>"},
12607 { 0xffe08000, 0xea200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateBICReg, "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12609 { 0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"},
12611 { 0xffffffc0, 0x00004040, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateEORReg, "eors|eor<c> <Rdn>, <Rm>"},
12612 { 0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateEORReg, "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12614 { 0xfbe08000, 0xf0400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"},
12616 { 0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateORRReg, "orrs|orr<c> <Rdn>, <Rm>"},
12617 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateORRReg, "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12619 { 0xffffffc0, 0x00004240, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"},
12620 { 0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c>.w <Rd>, <Rn>, #<const>"},
12622 { 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12624 { 0xfbe08000, 0xf1600000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12626 { 0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc<c> <Rdn>, <Rm>"},
12627 { 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
12628 // add (immediate, Thumb)
12629 { 0xfffffe00, 0x00001c00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rd>,<Rn>,#<imm3>" },
12630 { 0xfffff800, 0x00003000, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rdn>,#<imm8>" },
12631 { 0xfbe08000, 0xf1000000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "add{s}<c>.w <Rd>,<Rn>,#<const>" },
12632 { 0xfbf08000, 0xf2000000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateADDImmThumb, "addw<c> <Rd>,<Rn>,#<imm12>" },
12633 // sub (immediate, Thumb)
12634 { 0xfffffe00, 0x00001e00, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub<c> <Rd>, <Rn> #imm3"},
12635 { 0xfffff800, 0x00003800, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub<c> <Rdn>, #imm8"},
12636 { 0xfbe08000, 0xf1a00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "sub{s}<c>.w <Rd>, <Rn>, #<const>"},
12637 { 0xfbf08000, 0xf2a00000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBImmThumb, "subw<c> <Rd>, <Rn>, #imm12"},
12638 // sub (sp minus immediate)
12639 { 0xfbef8000, 0xf1ad0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w <Rd>, sp, #<const>"},
12640 { 0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw<c> <Rd>, sp, #imm12"},
12642 { 0xfffffe00, 0x00001a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
12643 { 0xffe08000, 0xeba00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBReg, "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"},
12645 { 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #<const>"},
12647 { 0xfff08f00, 0xea900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12649 { 0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #<const>"},
12651 { 0xffffffc0, 0x00004200, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rdn>, <Rm>"},
12652 { 0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateTSTReg, "tst<c>.w <Rn>, <Rm> {,<shift>}"},
12655 // move from high register to high register
12656 { 0xffffff00, 0x00004600, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"},
12657 // move from low register to low register
12658 { 0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"},
12659 // mov{s}<c>.w <Rd>, <Rm>
12660 { 0xffeff0f0, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"},
12662 { 0xfffff800, 0x00002000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov<c> <Rd>, #imm8"},
12663 { 0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c>.w <Rd>, #<const>"},
12664 { 0xfbf08000, 0xf2400000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>,#<imm16>"},
12666 { 0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNImm, "mvn{s} <Rd>, #<const>"},
12668 { 0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"},
12669 { 0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMVNReg, "mvn{s}<c>.w <Rd>, <Rm> {,<shift>}"},
12671 { 0xfbf08f00, 0xf1100f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"},
12673 { 0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm>"},
12674 { 0xfff08f00, 0xeb100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
12676 { 0xfffff800, 0x00002800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #imm8"},
12677 { 0xfbf08f00, 0xf1b00f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateCMPImm, "cmp<c>.w <Rn>, #<const>"},
12678 // cmp (register) (Rn and Rm both from r0-r7)
12679 { 0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
12680 // cmp (register) (Rn and Rm not both from r0-r7)
12681 { 0xffffff00, 0x00004500, ARMvAll, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
12683 { 0xfffff800, 0x00001000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
12684 { 0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
12686 { 0xffffffc0, 0x00004100, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateASRReg, "asrs|asr<c> <Rdn>, <Rm>"},
12687 { 0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12689 { 0xfffff800, 0x00000000, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},
12690 { 0xffef8030, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"},
12692 { 0xffffffc0, 0x00004080, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSLReg, "lsls|lsl<c> <Rdn>, <Rm>"},
12693 { 0xffe0f0f0, 0xfa00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
12695 { 0xfffff800, 0x00000800, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"},
12696 { 0xffef8030, 0xea4f0010, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"},
12698 { 0xffffffc0, 0x000040c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLSRReg, "lsrs|lsr<c> <Rdn>, <Rm>"},
12699 { 0xffe0f0f0, 0xfa20f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
12700 // rrx is a special case encoding of ror (immediate)
12701 { 0xffeff0f0, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"},
12703 { 0xffef8030, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"},
12705 { 0xffffffc0, 0x000041c0, ARMvAll, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateRORReg, "rors|ror<c> <Rdn>, <Rm>"},
12706 { 0xffe0f0f0, 0xfa60f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
12708 { 0xffffffc0, 0x00004340, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateMUL, "muls <Rdm>,<Rn>,<Rdm>" },
12710 { 0xfff0f0f0, 0xfb00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>" },
12712 // subs pc, lr and related instructions
12713 { 0xffffff00, 0xf3de8f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSUBSPcLrEtc, "SUBS<c> PC, LR, #<imm8>" },
12715 //----------------------------------------------------------------------
12716 // RFE instructions *** IMPORTANT *** THESE MUST BE LISTED **BEFORE** THE LDM.. Instructions in this table;
12717 // otherwise the wrong instructions will be selected.
12718 //----------------------------------------------------------------------
12720 { 0xffd0ffff, 0xe810c000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfedb<c> <Rn>{!}" },
12721 { 0xffd0ffff, 0xe990c000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateRFE, "rfe{ia}<c> <Rn>{!}" },
12723 //----------------------------------------------------------------------
12724 // Load instructions
12725 //----------------------------------------------------------------------
12726 { 0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>" },
12727 { 0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDM, "ldm<c>.w <Rn>{!} <registers>" },
12728 { 0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>" },
12729 { 0xfffff800, 0x00006800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"},
12730 { 0xfffff800, 0x00009800, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [SP{,#imm}]"},
12731 { 0xfff00000, 0xf8d00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c>.w <Rt>, [<Rn>{,#imm12}]"},
12732 { 0xfff00800, 0xf8500800, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#+/-<imm8>}]{!}"},
12733 // Thumb2 PC-relative load into register
12734 { 0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr<c>.w <Rt>, [PC, +/-#imm}]"},
12735 { 0xfffffe00, 0x00005800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]" },
12736 { 0xfff00fc0, 0xf8500000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c>.w <Rt>, [<Rn>,<Rm>{,LSL #<imm2>}]" },
12737 { 0xfffff800, 0x00007800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>{,#<imm5>}]" },
12738 { 0xfff00000, 0xf8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12739 { 0xfff00800, 0xf8100800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBImmediate, "ldrb<c> <Rt>,[<Rn>, #+/-<imm8>]{!}" },
12740 { 0xff7f0000, 0xf81f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>,[...]" },
12741 { 0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]" },
12742 { 0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12743 { 0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>, [<Rn>{,#<imm>}]" },
12744 { 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
12745 { 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" },
12746 { 0xff7f0000, 0xf83f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
12747 { 0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c> <Rt>, [<Rn>,<Rm>]" },
12748 { 0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRHRegister, "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12749 { 0xfff00000, 0xf9900000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#<imm12>]" },
12750 { 0xfff00800, 0xf9100800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBImmediate, "ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]" },
12751 { 0xff7f0000, 0xf91f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt>, <label>" },
12752 { 0xfffffe00, 0x00005600, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c> <Rt>,[<Rn>,<Rm>]" },
12753 { 0xfff00fc0, 0xf9100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSBRegister, "ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]" },
12754 { 0xfff00000, 0xf9b00000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#<imm12>]" },
12755 { 0xfff00800, 0xf9300800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHImmediate, "ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]" },
12756 { 0xff7f0000, 0xf93f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>" },
12757 { 0xfffffe00, 0x00005e00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,<Rm>]" },
12758 { 0xfff00fc0, 0xf9300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12759 { 0xfe500000, 0xe8500000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm>]!"},
12760 { 0xfe100f00, 0xec100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
12761 { 0xfe100f00, 0xec100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>" },
12762 { 0xffe00f00, 0xed100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12763 { 0xff300f00, 0xed100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, {<Rn>{,#+/-<imm>}]"},
12764 { 0xffb00000, 0xf9200000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
12765 { 0xffb00300, 0xf9a00000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Single, "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
12766 { 0xffb00f00, 0xf9a00c00, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1SingleAll, "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12768 //----------------------------------------------------------------------
12769 // Store instructions
12770 //----------------------------------------------------------------------
12771 { 0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>" },
12772 { 0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>" },
12773 { 0xffd00000, 0xe9000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>" },
12774 { 0xfffff800, 0x00006000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>{,#<imm>}]" },
12775 { 0xfffff800, 0x00009000, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [SP,#<imm>]" },
12776 { 0xfff00000, 0xf8c00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c>.w <Rt>, [<Rn>,#<imm12>]" },
12777 { 0xfff00800, 0xf8400800, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>,#+/-<imm8>]" },
12778 { 0xfffffe00, 0x00005000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]" },
12779 { 0xfff00fc0, 0xf8400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRRegister, "str<c>.w <Rt>, [<Rn>, <Rm> {lsl #imm2>}]" },
12780 { 0xfffff800, 0x00007000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt>, [<Rn>, #<imm5>]" },
12781 { 0xfff00000, 0xf8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c>.w <Rt>, [<Rn>, #<imm12>]" },
12782 { 0xfff00800, 0xf8000800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRBThumb, "strb<c> <Rt> ,[<Rn>, #+/-<imm8>]{!}" },
12783 { 0xfffffe00, 0x00005200, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]" },
12784 { 0xfff00fc0, 0xf8200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRHRegister, "strh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
12785 { 0xfff00000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn{,#<imm>}]" },
12786 { 0xfe500000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateSTRDImm, "strd<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!"},
12787 { 0xfe100f00, 0xec000b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!}, <list>"},
12788 { 0xfea00f00, 0xec000a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!}, <list>"},
12789 { 0xff300f00, 0xed000b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
12790 { 0xff300f00, 0xed000a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
12791 { 0xffb00000, 0xf9000000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Multiple, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12792 { 0xffb00300, 0xf9800000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVST1Single, "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
12794 //----------------------------------------------------------------------
12795 // Other instructions
12796 //----------------------------------------------------------------------
12797 { 0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>" },
12798 { 0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
12799 { 0xffffffc0, 0x0000b200, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>" },
12800 { 0xfffff080, 0xfa0ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}" },
12801 { 0xffffffc0, 0x0000b2c0, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>" },
12802 { 0xfffff080, 0xfa5ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}" },
12803 { 0xffffffc0, 0x0000b280, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>" },
12804 { 0xfffff080, 0xfa1ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}" },
12807 const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode);
12808 for (size_t i=0; i<k_num_thumb_opcodes; ++i)
12810 if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value &&
12811 (g_thumb_opcodes[i].variants & arm_isa) != 0)
12812 return &g_thumb_opcodes[i];
12818 EmulateInstructionARM::SetArchitecture (const ArchSpec &arch)
12822 const char *arch_cstr = arch.GetArchitectureName ();
12825 if (0 == ::strcasecmp(arch_cstr, "armv4t")) m_arm_isa = ARMv4T;
12826 else if (0 == ::strcasecmp(arch_cstr, "armv5tej")) m_arm_isa = ARMv5TEJ;
12827 else if (0 == ::strcasecmp(arch_cstr, "armv5te")) m_arm_isa = ARMv5TE;
12828 else if (0 == ::strcasecmp(arch_cstr, "armv5t")) m_arm_isa = ARMv5T;
12829 else if (0 == ::strcasecmp(arch_cstr, "armv6k")) m_arm_isa = ARMv6K;
12830 else if (0 == ::strcasecmp(arch_cstr, "armv6t2")) m_arm_isa = ARMv6T2;
12831 else if (0 == ::strcasecmp(arch_cstr, "armv7s")) m_arm_isa = ARMv7S;
12832 else if (0 == ::strcasecmp(arch_cstr, "arm")) m_arm_isa = ARMvAll;
12833 else if (0 == ::strcasecmp(arch_cstr, "thumb")) m_arm_isa = ARMvAll;
12834 else if (0 == ::strncasecmp(arch_cstr,"armv4", 5)) m_arm_isa = ARMv4;
12835 else if (0 == ::strncasecmp(arch_cstr,"armv6", 5)) m_arm_isa = ARMv6;
12836 else if (0 == ::strncasecmp(arch_cstr,"armv7", 5)) m_arm_isa = ARMv7;
12837 else if (0 == ::strncasecmp(arch_cstr,"armv8", 5)) m_arm_isa = ARMv8;
12839 return m_arm_isa != 0;
12843 EmulateInstructionARM::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target)
12845 if (EmulateInstruction::SetInstruction (insn_opcode, inst_addr, target))
12847 if (m_arch.GetTriple().getArch() == llvm::Triple::thumb)
12848 m_opcode_mode = eModeThumb;
12851 AddressClass addr_class = inst_addr.GetAddressClass();
12853 if ((addr_class == eAddressClassCode) || (addr_class == eAddressClassUnknown))
12854 m_opcode_mode = eModeARM;
12855 else if (addr_class == eAddressClassCodeAlternateISA)
12856 m_opcode_mode = eModeThumb;
12860 if (m_opcode_mode == eModeThumb)
12861 m_opcode_cpsr = CPSR_MODE_USR | MASK_CPSR_T;
12863 m_opcode_cpsr = CPSR_MODE_USR;
12870 EmulateInstructionARM::ReadInstruction ()
12872 bool success = false;
12873 m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, 0, &success);
12876 addr_t pc = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success);
12879 Context read_inst_context;
12880 read_inst_context.type = eContextReadOpcode;
12881 read_inst_context.SetNoArgs ();
12883 if (m_opcode_cpsr & MASK_CPSR_T)
12885 m_opcode_mode = eModeThumb;
12886 uint32_t thumb_opcode = MemARead(read_inst_context, pc, 2, 0, &success);
12890 if ((thumb_opcode & 0xe000) != 0xe000 || ((thumb_opcode & 0x1800u) == 0))
12892 m_opcode.SetOpcode16 (thumb_opcode);
12896 m_opcode.SetOpcode32 ((thumb_opcode << 16) | MemARead(read_inst_context, pc + 2, 2, 0, &success));
12902 m_opcode_mode = eModeARM;
12903 m_opcode.SetOpcode32 (MemARead(read_inst_context, pc, 4, 0, &success));
12909 m_opcode_mode = eModeInvalid;
12910 m_addr = LLDB_INVALID_ADDRESS;
12916 EmulateInstructionARM::ArchVersion ()
12922 EmulateInstructionARM::ConditionPassed (const uint32_t opcode, bool *is_conditional)
12924 // If we are ignoring conditions, then always return true.
12925 // this allows us to iterate over disassembly code and still
12926 // emulate an instruction even if we don't have all the right
12927 // bits set in the CPSR register...
12928 if (m_ignore_conditions)
12931 if (is_conditional)
12932 *is_conditional = true;
12934 const uint32_t cond = CurrentCond (opcode);
12936 if (cond == UINT32_MAX)
12939 bool result = false;
12940 switch (UnsignedBits(cond, 3, 1))
12943 if (m_opcode_cpsr == 0)
12946 result = (m_opcode_cpsr & MASK_CPSR_Z) != 0;
12949 if (m_opcode_cpsr == 0)
12952 result = (m_opcode_cpsr & MASK_CPSR_C) != 0;
12955 if (m_opcode_cpsr == 0)
12958 result = (m_opcode_cpsr & MASK_CPSR_N) != 0;
12961 if (m_opcode_cpsr == 0)
12964 result = (m_opcode_cpsr & MASK_CPSR_V) != 0;
12967 if (m_opcode_cpsr == 0)
12970 result = ((m_opcode_cpsr & MASK_CPSR_C) != 0) && ((m_opcode_cpsr & MASK_CPSR_Z) == 0);
12973 if (m_opcode_cpsr == 0)
12977 bool n = (m_opcode_cpsr & MASK_CPSR_N);
12978 bool v = (m_opcode_cpsr & MASK_CPSR_V);
12983 if (m_opcode_cpsr == 0)
12987 bool n = (m_opcode_cpsr & MASK_CPSR_N);
12988 bool v = (m_opcode_cpsr & MASK_CPSR_V);
12989 result = n == v && ((m_opcode_cpsr & MASK_CPSR_Z) == 0);
12993 // Always execute (cond == 0b1110, or the special 0b1111 which gives
12994 // opcodes different meanings, but always means execution happpens.
12995 if (is_conditional)
12996 *is_conditional = false;
13007 EmulateInstructionARM::CurrentCond (const uint32_t opcode)
13009 switch (m_opcode_mode)
13015 return UnsignedBits(opcode, 31, 28);
13018 // For T1 and T3 encodings of the Branch instruction, it returns the 4-bit
13019 // 'cond' field of the encoding.
13021 const uint32_t byte_size = m_opcode.GetByteSize();
13022 if (byte_size == 2)
13024 if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 7) != 0x0f)
13025 return Bits32(opcode, 11, 7);
13027 else if (byte_size == 4)
13029 if (Bits32(opcode, 31, 27) == 0x1e &&
13030 Bits32(opcode, 15, 14) == 0x02 &&
13031 Bits32(opcode, 12, 12) == 0x00 &&
13032 Bits32(opcode, 25, 22) <= 0x0d)
13034 return Bits32(opcode, 25, 22);
13038 // We have an invalid thumb instruction, let's bail out.
13041 return m_it_session.GetCond();
13044 return UINT32_MAX; // Return invalid value
13048 EmulateInstructionARM::InITBlock()
13050 return CurrentInstrSet() == eModeThumb && m_it_session.InITBlock();
13054 EmulateInstructionARM::LastInITBlock()
13056 return CurrentInstrSet() == eModeThumb && m_it_session.LastInITBlock();
13060 EmulateInstructionARM::BadMode (uint32_t mode)
13065 case 16: return false; // '10000'
13066 case 17: return false; // '10001'
13067 case 18: return false; // '10010'
13068 case 19: return false; // '10011'
13069 case 22: return false; // '10110'
13070 case 23: return false; // '10111'
13071 case 27: return false; // '11011'
13072 case 31: return false; // '11111'
13073 default: return true;
13079 EmulateInstructionARM::CurrentModeIsPrivileged ()
13081 uint32_t mode = Bits32 (m_opcode_cpsr, 4, 0);
13083 if (BadMode (mode))
13093 EmulateInstructionARM::CPSRWriteByInstr (uint32_t value, uint32_t bytemask, bool affect_execstate)
13095 bool privileged = CurrentModeIsPrivileged();
13097 uint32_t tmp_cpsr = Bits32 (m_opcode_cpsr, 23, 20) << 20;
13099 if (BitIsSet (bytemask, 3))
13101 tmp_cpsr = tmp_cpsr | (Bits32 (value, 31, 27) << 27);
13102 if (affect_execstate)
13103 tmp_cpsr = tmp_cpsr | (Bits32 (value, 26, 24) << 24);
13106 if (BitIsSet (bytemask, 2))
13108 tmp_cpsr = tmp_cpsr | (Bits32 (value, 19, 16) << 16);
13111 if (BitIsSet (bytemask, 1))
13113 if (affect_execstate)
13114 tmp_cpsr = tmp_cpsr | (Bits32 (value, 15, 10) << 10);
13115 tmp_cpsr = tmp_cpsr | (Bit32 (value, 9) << 9);
13117 tmp_cpsr = tmp_cpsr | (Bit32 (value, 8) << 8);
13120 if (BitIsSet (bytemask, 0))
13123 tmp_cpsr = tmp_cpsr | (Bits32 (value, 7, 6) << 6);
13124 if (affect_execstate)
13125 tmp_cpsr = tmp_cpsr | (Bit32 (value, 5) << 5);
13127 tmp_cpsr = tmp_cpsr | Bits32 (value, 4, 0);
13130 m_opcode_cpsr = tmp_cpsr;
13135 EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr)
13139 // Check the current instruction set.
13140 if (CurrentInstrSet() == eModeARM)
13141 target = addr & 0xfffffffc;
13143 target = addr & 0xfffffffe;
13145 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target))
13151 // As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr.
13153 EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr)
13156 // If the CPSR is changed due to switching between ARM and Thumb ISETSTATE,
13157 // we want to record it and issue a WriteRegister callback so the clients
13158 // can track the mode changes accordingly.
13159 bool cpsr_changed = false;
13161 if (BitIsSet(addr, 0))
13163 if (CurrentInstrSet() != eModeThumb)
13165 SelectInstrSet(eModeThumb);
13166 cpsr_changed = true;
13168 target = addr & 0xfffffffe;
13169 context.SetISA (eModeThumb);
13171 else if (BitIsClear(addr, 1))
13173 if (CurrentInstrSet() != eModeARM)
13175 SelectInstrSet(eModeARM);
13176 cpsr_changed = true;
13178 target = addr & 0xfffffffc;
13179 context.SetISA (eModeARM);
13182 return false; // address<1:0> == '10' => UNPREDICTABLE
13186 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
13189 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, target))
13195 // Dispatches to either BXWritePC or BranchWritePC based on architecture versions.
13197 EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr)
13199 if (ArchVersion() >= ARMv5T)
13200 return BXWritePC(context, addr);
13202 return BranchWritePC((const Context)context, addr);
13205 // Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set.
13207 EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr)
13209 if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM)
13210 return BXWritePC(context, addr);
13212 return BranchWritePC((const Context)context, addr);
13215 EmulateInstructionARM::Mode
13216 EmulateInstructionARM::CurrentInstrSet ()
13218 return m_opcode_mode;
13221 // Set the 'T' bit of our CPSR. The m_opcode_mode gets updated when the next
13222 // ReadInstruction() is performed. This function has a side effect of updating
13223 // the m_new_inst_cpsr member variable if necessary.
13225 EmulateInstructionARM::SelectInstrSet (Mode arm_or_thumb)
13227 m_new_inst_cpsr = m_opcode_cpsr;
13228 switch (arm_or_thumb)
13233 // Clear the T bit.
13234 m_new_inst_cpsr &= ~MASK_CPSR_T;
13238 m_new_inst_cpsr |= MASK_CPSR_T;
13244 // This function returns TRUE if the processor currently provides support for
13245 // unaligned memory accesses, or FALSE otherwise. This is always TRUE in ARMv7,
13246 // controllable by the SCTLR.U bit in ARMv6, and always FALSE before ARMv6.
13248 EmulateInstructionARM::UnalignedSupport()
13250 return (ArchVersion() >= ARMv7);
13253 // The main addition and subtraction instructions can produce status information
13254 // about both unsigned carry and signed overflow conditions. This status
13255 // information can be used to synthesize multi-word additions and subtractions.
13256 EmulateInstructionARM::AddWithCarryResult
13257 EmulateInstructionARM::AddWithCarry (uint32_t x, uint32_t y, uint8_t carry_in)
13263 uint64_t unsigned_sum = x + y + carry_in;
13264 int64_t signed_sum = (int32_t)x + (int32_t)y + (int32_t)carry_in;
13266 result = UnsignedBits(unsigned_sum, 31, 0);
13267 // carry_out = (result == unsigned_sum ? 0 : 1);
13268 overflow = ((int32_t)result == signed_sum ? 0 : 1);
13271 carry_out = ((int32_t) x >= (int32_t) (~y)) ? 1 : 0;
13273 carry_out = ((int32_t) x > (int32_t) y) ? 1 : 0;
13275 AddWithCarryResult res = { result, carry_out, overflow };
13280 EmulateInstructionARM::ReadCoreReg(uint32_t num, bool *success)
13282 uint32_t reg_kind, reg_num;
13286 reg_kind = eRegisterKindGeneric;
13287 reg_num = LLDB_REGNUM_GENERIC_SP;
13290 reg_kind = eRegisterKindGeneric;
13291 reg_num = LLDB_REGNUM_GENERIC_RA;
13294 reg_kind = eRegisterKindGeneric;
13295 reg_num = LLDB_REGNUM_GENERIC_PC;
13300 reg_kind = eRegisterKindDWARF;
13301 reg_num = dwarf_r0 + num;
13305 //assert(0 && "Invalid register number");
13312 // Read our register.
13313 uint32_t val = ReadRegisterUnsigned (reg_kind, reg_num, 0, success);
13315 // When executing an ARM instruction , PC reads as the address of the current
13316 // instruction plus 8.
13317 // When executing a Thumb instruction , PC reads as the address of the current
13318 // instruction plus 4.
13321 if (CurrentInstrSet() == eModeARM)
13330 // Write the result to the ARM core register Rd, and optionally update the
13331 // condition flags based on the result.
13333 // This helper method tries to encapsulate the following pseudocode from the
13334 // ARM Architecture Reference Manual:
13336 // if d == 15 then // Can only occur for encoding A1
13337 // ALUWritePC(result); // setflags is always FALSE here
13340 // if setflags then
13341 // APSR.N = result<31>;
13342 // APSR.Z = IsZeroBit(result);
13344 // // APSR.V unchanged
13346 // In the above case, the API client does not pass in the overflow arg, which
13347 // defaults to ~0u.
13349 EmulateInstructionARM::WriteCoreRegOptionalFlags (Context &context,
13350 const uint32_t result,
13353 const uint32_t carry,
13354 const uint32_t overflow)
13358 if (!ALUWritePC (context, result))
13363 uint32_t reg_kind, reg_num;
13367 reg_kind = eRegisterKindGeneric;
13368 reg_num = LLDB_REGNUM_GENERIC_SP;
13371 reg_kind = eRegisterKindGeneric;
13372 reg_num = LLDB_REGNUM_GENERIC_RA;
13375 reg_kind = eRegisterKindDWARF;
13376 reg_num = dwarf_r0 + Rd;
13378 if (!WriteRegisterUnsigned (context, reg_kind, reg_num, result))
13381 return WriteFlags (context, result, carry, overflow);
13386 // This helper method tries to encapsulate the following pseudocode from the
13387 // ARM Architecture Reference Manual:
13389 // APSR.N = result<31>;
13390 // APSR.Z = IsZeroBit(result);
13392 // APSR.V = overflow
13394 // Default arguments can be specified for carry and overflow parameters, which means
13395 // not to update the respective flags.
13397 EmulateInstructionARM::WriteFlags (Context &context,
13398 const uint32_t result,
13399 const uint32_t carry,
13400 const uint32_t overflow)
13402 m_new_inst_cpsr = m_opcode_cpsr;
13403 SetBit32(m_new_inst_cpsr, CPSR_N_POS, Bit32(result, CPSR_N_POS));
13404 SetBit32(m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
13406 SetBit32(m_new_inst_cpsr, CPSR_C_POS, carry);
13407 if (overflow != ~0u)
13408 SetBit32(m_new_inst_cpsr, CPSR_V_POS, overflow);
13409 if (m_new_inst_cpsr != m_opcode_cpsr)
13411 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
13418 EmulateInstructionARM::EvaluateInstruction (uint32_t evaluate_options)
13420 // Advance the ITSTATE bits to their values for the next instruction.
13421 if (m_opcode_mode == eModeThumb && m_it_session.InITBlock())
13422 m_it_session.ITAdvance();
13424 ARMOpcode *opcode_data = NULL;
13426 if (m_opcode_mode == eModeThumb)
13427 opcode_data = GetThumbOpcodeForInstruction (m_opcode.GetOpcode32(), m_arm_isa);
13428 else if (m_opcode_mode == eModeARM)
13429 opcode_data = GetARMOpcodeForInstruction (m_opcode.GetOpcode32(), m_arm_isa);
13431 if (opcode_data == NULL)
13434 const bool auto_advance_pc = evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
13435 m_ignore_conditions = evaluate_options & eEmulateInstructionOptionIgnoreConditions;
13437 bool success = false;
13438 if (m_opcode_cpsr == 0 || m_ignore_conditions == false)
13440 m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindDWARF,
13446 // Only return false if we are unable to read the CPSR if we care about conditions
13447 if (success == false && m_ignore_conditions == false)
13450 uint32_t orig_pc_value = 0;
13451 if (auto_advance_pc)
13453 orig_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc, 0, &success);
13458 // Call the Emulate... function.
13459 success = (this->*opcode_data->callback) (m_opcode.GetOpcode32(), opcode_data->encoding);
13463 if (auto_advance_pc)
13465 uint32_t after_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc, 0, &success);
13469 if (auto_advance_pc && (after_pc_value == orig_pc_value))
13471 if (opcode_data->size == eSize32)
13472 after_pc_value += 4;
13473 else if (opcode_data->size == eSize16)
13474 after_pc_value += 2;
13476 EmulateInstruction::Context context;
13477 context.type = eContextAdvancePC;
13478 context.SetNoArgs();
13479 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc, after_pc_value))
13488 EmulateInstructionARM::TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data)
13492 out_stream->Printf ("TestEmulation: Missing test data.\n");
13496 static ConstString opcode_key ("opcode");
13497 static ConstString before_key ("before_state");
13498 static ConstString after_key ("after_state");
13500 OptionValueSP value_sp = test_data->GetValueForKey (opcode_key);
13502 uint32_t test_opcode;
13503 if ((value_sp.get() == NULL) || (value_sp->GetType() != OptionValue::eTypeUInt64))
13505 out_stream->Printf ("TestEmulation: Error reading opcode from test file.\n");
13508 test_opcode = value_sp->GetUInt64Value ();
13510 if (arch.GetTriple().getArch() == llvm::Triple::arm)
13512 m_opcode_mode = eModeARM;
13513 m_opcode.SetOpcode32 (test_opcode);
13515 else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
13517 m_opcode_mode = eModeThumb;
13518 if (test_opcode < 0x10000)
13519 m_opcode.SetOpcode16 (test_opcode);
13521 m_opcode.SetOpcode32 (test_opcode);
13526 out_stream->Printf ("TestEmulation: Invalid arch.\n");
13530 EmulationStateARM before_state;
13531 EmulationStateARM after_state;
13533 value_sp = test_data->GetValueForKey (before_key);
13534 if ((value_sp.get() == NULL) || (value_sp->GetType() != OptionValue::eTypeDictionary))
13536 out_stream->Printf ("TestEmulation: Failed to find 'before' state.\n");
13540 OptionValueDictionary *state_dictionary = value_sp->GetAsDictionary ();
13541 if (!before_state.LoadStateFromDictionary (state_dictionary))
13543 out_stream->Printf ("TestEmulation: Failed loading 'before' state.\n");
13547 value_sp = test_data->GetValueForKey (after_key);
13548 if ((value_sp.get() == NULL) || (value_sp->GetType() != OptionValue::eTypeDictionary))
13550 out_stream->Printf ("TestEmulation: Failed to find 'after' state.\n");
13554 state_dictionary = value_sp->GetAsDictionary ();
13555 if (!after_state.LoadStateFromDictionary (state_dictionary))
13557 out_stream->Printf ("TestEmulation: Failed loading 'after' state.\n");
13561 SetBaton ((void *) &before_state);
13562 SetCallbacks (&EmulationStateARM::ReadPseudoMemory,
13563 &EmulationStateARM::WritePseudoMemory,
13564 &EmulationStateARM::ReadPseudoRegister,
13565 &EmulationStateARM::WritePseudoRegister);
13567 bool success = EvaluateInstruction (eEmulateInstructionOptionAutoAdvancePC);
13570 out_stream->Printf ("TestEmulation: EvaluateInstruction() failed.\n");
13574 success = before_state.CompareState (after_state);
13576 out_stream->Printf ("TestEmulation: 'before' and 'after' states do not match.\n");
13583 //EmulateInstructionARM::GetRegisterName (uint32_t reg_kind, uint32_t reg_num)
13585 // if (reg_kind == eRegisterKindGeneric)
13587 // switch (reg_num)
13589 // case LLDB_REGNUM_GENERIC_PC: return "pc";
13590 // case LLDB_REGNUM_GENERIC_SP: return "sp";
13591 // case LLDB_REGNUM_GENERIC_FP: return "fp";
13592 // case LLDB_REGNUM_GENERIC_RA: return "lr";
13593 // case LLDB_REGNUM_GENERIC_FLAGS: return "cpsr";
13594 // default: return NULL;
13597 // else if (reg_kind == eRegisterKindDWARF)
13599 // return GetARMDWARFRegisterName (reg_num);
13605 EmulateInstructionARM::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan)
13607 unwind_plan.Clear();
13608 unwind_plan.SetRegisterKind (eRegisterKindDWARF);
13610 UnwindPlan::RowSP row(new UnwindPlan::Row);
13612 // Our previous Call Frame Address is the stack pointer
13613 row->SetCFARegister (dwarf_sp);
13615 // Our previous PC is in the LR
13616 row->SetRegisterLocationToRegister(dwarf_pc, dwarf_lr, true);
13617 unwind_plan.AppendRow (row);
13619 // All other registers are the same.
13621 unwind_plan.SetSourceName ("EmulateInstructionARM");
13622 unwind_plan.SetSourcedFromCompiler (eLazyBoolNo);
13623 unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes);