2 .\" Copyright (c) 2012 SRI International
3 .\" All rights reserved.
5 .\" This software was developed by SRI International and the University of
6 .\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 .\" ("CTSRD"), as part of the DARPA CRASH research programme.
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37 .Nd driver for Intel StrataFlash NOR flash devices
42 .Pa /boot/device.hints :
43 .Cd hint.isf.0.at="nexus0"
44 .Cd hint.isf.0.maddr=0x74000000
45 .Cd hint.isf.0.msize=0x2000000
49 device driver provides support for Intel StrataFlash NOR flash devices.
50 Devices are presented as
52 devices and read access is supported along with limited write support.
53 Erasing blocks is supported the
57 The erase block size of
60 NOR flash blocks contains all 1's after an erase cycle.
63 devices are allowed to succeed if and only if they all bits in the write
64 block (512-bytes) remain the same or transition from 1 to 0.
66 The current version of the
68 driver is known to support the 64MB part found on the Altera DE4 board.
69 It attempts to support other StrataFlash parts documented in the
70 datasheet, but those are untested.
77 .Bl -tag -width ISF_ERASE
79 Erase one or more blocks.
80 .Dv ISF_ERASE is defined as follows:
87 #define ISF_ERASE _IOW('I', 1, struct isf_range)
92 member marks the beginning of the area to be erased and must fall on at 128K
96 member indicates the size of the area to be erased and must a multiple
103 .%T Intel StrataFlash Embedded Memory (P30)
105 .%I Intel Corporation
106 .%U http://www.xilinx.com/products/boards/ml505/datasheets/30666604.pdf
111 device driver first appeared in
116 device driver and this manual page were
117 developed by SRI International and the University of Cambridge Computer
118 Laboratory under DARPA/AFRL contract
121 as part of the DARPA CRASH research programme.
123 While an erase is in progress, all read and write operations return
125 In principle, reads could be allowed outside the programming region the
126 blocked currently being erased resides in and writes could be allowed by
127 suspending the erase, but neither of these is currently implemented.
129 Depending on the flash part ether the top or bottom 128K of the flash
130 address space is divided into 4 32K erase blocks.
133 driver hides this from the user requiring that all erase requests be
134 multiples of 128K in size and erasing the individual blocks as needed at