2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #include <sys/_unrhdr.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_object.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_pageout.h>
132 #include <vm/vm_pager.h>
133 #include <vm/vm_phys.h>
134 #include <vm/vm_radix.h>
135 #include <vm/vm_reserv.h>
138 #include <machine/intr_machdep.h>
139 #include <machine/apicvar.h>
140 #include <machine/cpu.h>
141 #include <machine/cputypes.h>
142 #include <machine/md_var.h>
143 #include <machine/pcb.h>
144 #include <machine/specialreg.h>
146 #include <machine/smp.h>
149 static __inline boolean_t
150 pmap_type_guest(pmap_t pmap)
153 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
156 static __inline boolean_t
157 pmap_emulate_ad_bits(pmap_t pmap)
160 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
163 static __inline pt_entry_t
164 pmap_valid_bit(pmap_t pmap)
168 switch (pmap->pm_type) {
174 if (pmap_emulate_ad_bits(pmap))
175 mask = EPT_PG_EMUL_V;
180 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
186 static __inline pt_entry_t
187 pmap_rw_bit(pmap_t pmap)
191 switch (pmap->pm_type) {
197 if (pmap_emulate_ad_bits(pmap))
198 mask = EPT_PG_EMUL_RW;
203 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
209 static __inline pt_entry_t
210 pmap_global_bit(pmap_t pmap)
214 switch (pmap->pm_type) {
223 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
229 static __inline pt_entry_t
230 pmap_accessed_bit(pmap_t pmap)
234 switch (pmap->pm_type) {
240 if (pmap_emulate_ad_bits(pmap))
246 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
252 static __inline pt_entry_t
253 pmap_modified_bit(pmap_t pmap)
257 switch (pmap->pm_type) {
263 if (pmap_emulate_ad_bits(pmap))
269 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
275 #if !defined(DIAGNOSTIC)
276 #ifdef __GNUC_GNU_INLINE__
277 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
279 #define PMAP_INLINE extern inline
286 #define PV_STAT(x) do { x ; } while (0)
288 #define PV_STAT(x) do { } while (0)
291 #define pa_index(pa) ((pa) >> PDRSHIFT)
292 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
294 #define NPV_LIST_LOCKS MAXCPU
296 #define PHYS_TO_PV_LIST_LOCK(pa) \
297 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
299 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
300 struct rwlock **_lockp = (lockp); \
301 struct rwlock *_new_lock; \
303 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
304 if (_new_lock != *_lockp) { \
305 if (*_lockp != NULL) \
306 rw_wunlock(*_lockp); \
307 *_lockp = _new_lock; \
312 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
313 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
315 #define RELEASE_PV_LIST_LOCK(lockp) do { \
316 struct rwlock **_lockp = (lockp); \
318 if (*_lockp != NULL) { \
319 rw_wunlock(*_lockp); \
324 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
325 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
327 struct pmap kernel_pmap_store;
329 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
330 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
333 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
334 "Number of kernel page table pages allocated on bootup");
337 vm_paddr_t dmaplimit;
338 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
341 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
343 static int pat_works = 1;
344 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
345 "Is page attribute table fully functional?");
347 static int pg_ps_enabled = 1;
348 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
349 "Are large page mappings enabled?");
351 #define PAT_INDEX_SIZE 8
352 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
354 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
355 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
356 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
357 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
359 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
360 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
361 static int ndmpdpphys; /* number of DMPDPphys pages */
363 static struct rwlock_padalign pvh_global_lock;
366 * Data for the pv entry allocation mechanism
368 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
369 static struct mtx pv_chunks_mutex;
370 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
371 static struct md_page *pv_table;
374 * All those kernel PT submaps that BSD is so fond of
376 pt_entry_t *CMAP1 = 0;
379 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
381 static struct unrhdr pcid_unr;
382 static struct mtx pcid_mtx;
383 int pmap_pcid_enabled = 0;
384 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN, &pmap_pcid_enabled,
385 0, "Is TLB Context ID enabled ?");
386 int invpcid_works = 0;
387 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
388 "Is the invpcid instruction available ?");
391 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
398 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
400 return (sysctl_handle_64(oidp, &res, 0, req));
402 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
403 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
404 "Count of saved TLB context on switch");
406 /* pmap_copy_pages() over non-DMAP */
407 static struct mtx cpage_lock;
408 static vm_offset_t cpage_a;
409 static vm_offset_t cpage_b;
414 static caddr_t crashdumpmap;
416 static void free_pv_chunk(struct pv_chunk *pc);
417 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
418 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
419 static int popcnt_pc_map_elem(uint64_t elem);
420 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
421 static void reserve_pv_entries(pmap_t pmap, int needed,
422 struct rwlock **lockp);
423 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
424 struct rwlock **lockp);
425 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
426 struct rwlock **lockp);
427 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
428 struct rwlock **lockp);
429 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
430 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
433 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
434 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
435 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
436 vm_offset_t va, struct rwlock **lockp);
437 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
439 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
440 vm_prot_t prot, struct rwlock **lockp);
441 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
442 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
443 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
444 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
445 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
446 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
447 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
448 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
449 struct rwlock **lockp);
450 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
452 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
453 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
454 struct spglist *free, struct rwlock **lockp);
455 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
456 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
457 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
458 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
459 struct spglist *free);
460 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
461 vm_page_t m, struct rwlock **lockp);
462 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
464 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
466 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
467 struct rwlock **lockp);
468 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
469 struct rwlock **lockp);
470 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
471 struct rwlock **lockp);
473 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
474 struct spglist *free);
475 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
476 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
479 * Move the kernel virtual free pointer to the next
480 * 2MB. This is used to help improve performance
481 * by using a large (2MB) page for much of the kernel
482 * (.text, .data, .bss)
485 pmap_kmem_choose(vm_offset_t addr)
487 vm_offset_t newaddr = addr;
489 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
493 /********************/
494 /* Inline functions */
495 /********************/
497 /* Return a non-clipped PD index for a given VA */
498 static __inline vm_pindex_t
499 pmap_pde_pindex(vm_offset_t va)
501 return (va >> PDRSHIFT);
505 /* Return various clipped indexes for a given VA */
506 static __inline vm_pindex_t
507 pmap_pte_index(vm_offset_t va)
510 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
513 static __inline vm_pindex_t
514 pmap_pde_index(vm_offset_t va)
517 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
520 static __inline vm_pindex_t
521 pmap_pdpe_index(vm_offset_t va)
524 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
527 static __inline vm_pindex_t
528 pmap_pml4e_index(vm_offset_t va)
531 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
534 /* Return a pointer to the PML4 slot that corresponds to a VA */
535 static __inline pml4_entry_t *
536 pmap_pml4e(pmap_t pmap, vm_offset_t va)
539 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
542 /* Return a pointer to the PDP slot that corresponds to a VA */
543 static __inline pdp_entry_t *
544 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
548 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
549 return (&pdpe[pmap_pdpe_index(va)]);
552 /* Return a pointer to the PDP slot that corresponds to a VA */
553 static __inline pdp_entry_t *
554 pmap_pdpe(pmap_t pmap, vm_offset_t va)
559 PG_V = pmap_valid_bit(pmap);
560 pml4e = pmap_pml4e(pmap, va);
561 if ((*pml4e & PG_V) == 0)
563 return (pmap_pml4e_to_pdpe(pml4e, va));
566 /* Return a pointer to the PD slot that corresponds to a VA */
567 static __inline pd_entry_t *
568 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
572 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
573 return (&pde[pmap_pde_index(va)]);
576 /* Return a pointer to the PD slot that corresponds to a VA */
577 static __inline pd_entry_t *
578 pmap_pde(pmap_t pmap, vm_offset_t va)
583 PG_V = pmap_valid_bit(pmap);
584 pdpe = pmap_pdpe(pmap, va);
585 if (pdpe == NULL || (*pdpe & PG_V) == 0)
587 return (pmap_pdpe_to_pde(pdpe, va));
590 /* Return a pointer to the PT slot that corresponds to a VA */
591 static __inline pt_entry_t *
592 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
596 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
597 return (&pte[pmap_pte_index(va)]);
600 /* Return a pointer to the PT slot that corresponds to a VA */
601 static __inline pt_entry_t *
602 pmap_pte(pmap_t pmap, vm_offset_t va)
607 PG_V = pmap_valid_bit(pmap);
608 pde = pmap_pde(pmap, va);
609 if (pde == NULL || (*pde & PG_V) == 0)
611 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
612 return ((pt_entry_t *)pde);
613 return (pmap_pde_to_pte(pde, va));
617 pmap_resident_count_inc(pmap_t pmap, int count)
620 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
621 pmap->pm_stats.resident_count += count;
625 pmap_resident_count_dec(pmap_t pmap, int count)
628 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
629 KASSERT(pmap->pm_stats.resident_count >= count,
630 ("pmap %p resident count underflow %ld %d", pmap,
631 pmap->pm_stats.resident_count, count));
632 pmap->pm_stats.resident_count -= count;
635 PMAP_INLINE pt_entry_t *
636 vtopte(vm_offset_t va)
638 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
640 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
642 return (PTmap + ((va >> PAGE_SHIFT) & mask));
645 static __inline pd_entry_t *
646 vtopde(vm_offset_t va)
648 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
650 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
652 return (PDmap + ((va >> PDRSHIFT) & mask));
656 allocpages(vm_paddr_t *firstaddr, int n)
661 bzero((void *)ret, n * PAGE_SIZE);
662 *firstaddr += n * PAGE_SIZE;
666 CTASSERT(powerof2(NDMPML4E));
668 /* number of kernel PDP slots */
669 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
672 nkpt_init(vm_paddr_t addr)
679 pt_pages = howmany(addr, 1 << PDRSHIFT);
680 pt_pages += NKPDPE(pt_pages);
683 * Add some slop beyond the bare minimum required for bootstrapping
686 * This is quite important when allocating KVA for kernel modules.
687 * The modules are required to be linked in the negative 2GB of
688 * the address space. If we run out of KVA in this region then
689 * pmap_growkernel() will need to allocate page table pages to map
690 * the entire 512GB of KVA space which is an unnecessary tax on
693 pt_pages += 8; /* 16MB additional slop for kernel modules */
699 create_pagetables(vm_paddr_t *firstaddr)
701 int i, j, ndm1g, nkpdpe;
707 /* Allocate page table pages for the direct map */
708 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
709 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
711 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
712 if (ndmpdpphys > NDMPML4E) {
714 * Each NDMPML4E allows 512 GB, so limit to that,
715 * and then readjust ndmpdp and ndmpdpphys.
717 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
718 Maxmem = atop(NDMPML4E * NBPML4);
719 ndmpdpphys = NDMPML4E;
720 ndmpdp = NDMPML4E * NPDEPG;
722 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
724 if ((amd_feature & AMDID_PAGE1GB) != 0)
725 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
727 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
728 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
731 KPML4phys = allocpages(firstaddr, 1);
732 KPDPphys = allocpages(firstaddr, NKPML4E);
735 * Allocate the initial number of kernel page table pages required to
736 * bootstrap. We defer this until after all memory-size dependent
737 * allocations are done (e.g. direct map), so that we don't have to
738 * build in too much slop in our estimate.
740 * Note that when NKPML4E > 1, we have an empty page underneath
741 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
742 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
744 nkpt_init(*firstaddr);
745 nkpdpe = NKPDPE(nkpt);
747 KPTphys = allocpages(firstaddr, nkpt);
748 KPDphys = allocpages(firstaddr, nkpdpe);
750 /* Fill in the underlying page table pages */
751 /* Nominally read-only (but really R/W) from zero to physfree */
752 /* XXX not fully used, underneath 2M pages */
753 pt_p = (pt_entry_t *)KPTphys;
754 for (i = 0; ptoa(i) < *firstaddr; i++)
755 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
757 /* Now map the page tables at their location within PTmap */
758 pd_p = (pd_entry_t *)KPDphys;
759 for (i = 0; i < nkpt; i++)
760 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
762 /* Map from zero to end of allocations under 2M pages */
763 /* This replaces some of the KPTphys entries above */
764 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
765 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
768 /* And connect up the PD to the PDP (leaving room for L4 pages) */
769 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
770 for (i = 0; i < nkpdpe; i++)
771 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
775 * Now, set up the direct map region using 2MB and/or 1GB pages. If
776 * the end of physical memory is not aligned to a 1GB page boundary,
777 * then the residual physical memory is mapped with 2MB pages. Later,
778 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
779 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
780 * that are partially used.
782 pd_p = (pd_entry_t *)DMPDphys;
783 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
784 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
785 /* Preset PG_M and PG_A because demotion expects it. */
786 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
789 pdp_p = (pdp_entry_t *)DMPDPphys;
790 for (i = 0; i < ndm1g; i++) {
791 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
792 /* Preset PG_M and PG_A because demotion expects it. */
793 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
796 for (j = 0; i < ndmpdp; i++, j++) {
797 pdp_p[i] = DMPDphys + ptoa(j);
798 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
801 /* And recursively map PML4 to itself in order to get PTmap */
802 p4_p = (pml4_entry_t *)KPML4phys;
803 p4_p[PML4PML4I] = KPML4phys;
804 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
806 /* Connect the Direct Map slot(s) up to the PML4. */
807 for (i = 0; i < ndmpdpphys; i++) {
808 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
809 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
812 /* Connect the KVA slots up to the PML4 */
813 for (i = 0; i < NKPML4E; i++) {
814 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
815 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
820 * Bootstrap the system enough to run with virtual memory.
822 * On amd64 this is called after mapping has already been enabled
823 * and just syncs the pmap module with what has already been done.
824 * [We can't call it easily with mapping off since the kernel is not
825 * mapped with PA == VA, hence we would have to relocate every address
826 * from the linked base (virtual) address "KERNBASE" to the actual
827 * (physical) address starting relative to 0]
830 pmap_bootstrap(vm_paddr_t *firstaddr)
836 * Create an initial set of page tables to run the kernel in.
838 create_pagetables(firstaddr);
841 * Add a physical memory segment (vm_phys_seg) corresponding to the
842 * preallocated kernel page table pages so that vm_page structures
843 * representing these pages will be created. The vm_page structures
844 * are required for promotion of the corresponding kernel virtual
845 * addresses to superpage mappings.
847 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
849 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
850 virtual_avail = pmap_kmem_choose(virtual_avail);
852 virtual_end = VM_MAX_KERNEL_ADDRESS;
855 /* XXX do %cr0 as well */
856 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
858 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
859 load_cr4(rcr4() | CR4_SMEP);
862 * Initialize the kernel pmap (which is statically allocated).
864 PMAP_LOCK_INIT(kernel_pmap);
865 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
866 kernel_pmap->pm_cr3 = KPML4phys;
867 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
868 CPU_FILL(&kernel_pmap->pm_save); /* always superset of pm_active */
869 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
870 kernel_pmap->pm_flags = pmap_flags;
873 * Initialize the global pv list lock.
875 rw_init(&pvh_global_lock, "pmap pv global");
878 * Reserve some special page table entries/VA space for temporary
881 #define SYSMAP(c, p, v, n) \
882 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
888 * Crashdump maps. The first page is reused as CMAP1 for the
891 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
892 CADDR1 = crashdumpmap;
896 /* Initialize the PAT MSR. */
899 /* Initialize TLB Context Id. */
900 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
901 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
902 load_cr4(rcr4() | CR4_PCIDE);
903 mtx_init(&pcid_mtx, "pcid", NULL, MTX_DEF);
904 init_unrhdr(&pcid_unr, 1, (1 << 12) - 1, &pcid_mtx);
905 /* Check for INVPCID support */
906 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
908 kernel_pmap->pm_pcid = 0;
910 pmap_pcid_enabled = 0;
913 pmap_pcid_enabled = 0;
922 int pat_table[PAT_INDEX_SIZE];
927 /* Bail if this CPU doesn't implement PAT. */
928 if ((cpu_feature & CPUID_PAT) == 0)
931 /* Set default PAT index table. */
932 for (i = 0; i < PAT_INDEX_SIZE; i++)
934 pat_table[PAT_WRITE_BACK] = 0;
935 pat_table[PAT_WRITE_THROUGH] = 1;
936 pat_table[PAT_UNCACHEABLE] = 3;
937 pat_table[PAT_WRITE_COMBINING] = 3;
938 pat_table[PAT_WRITE_PROTECTED] = 3;
939 pat_table[PAT_UNCACHED] = 3;
941 /* Initialize default PAT entries. */
942 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
943 PAT_VALUE(1, PAT_WRITE_THROUGH) |
944 PAT_VALUE(2, PAT_UNCACHED) |
945 PAT_VALUE(3, PAT_UNCACHEABLE) |
946 PAT_VALUE(4, PAT_WRITE_BACK) |
947 PAT_VALUE(5, PAT_WRITE_THROUGH) |
948 PAT_VALUE(6, PAT_UNCACHED) |
949 PAT_VALUE(7, PAT_UNCACHEABLE);
953 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
954 * Program 5 and 6 as WP and WC.
955 * Leave 4 and 7 as WB and UC.
957 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
958 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
959 PAT_VALUE(6, PAT_WRITE_COMBINING);
960 pat_table[PAT_UNCACHED] = 2;
961 pat_table[PAT_WRITE_PROTECTED] = 5;
962 pat_table[PAT_WRITE_COMBINING] = 6;
965 * Just replace PAT Index 2 with WC instead of UC-.
967 pat_msr &= ~PAT_MASK(2);
968 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
969 pat_table[PAT_WRITE_COMBINING] = 2;
974 load_cr4(cr4 & ~CR4_PGE);
976 /* Disable caches (CD = 1, NW = 0). */
978 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
980 /* Flushes caches and TLBs. */
984 /* Update PAT and index table. */
985 wrmsr(MSR_PAT, pat_msr);
986 for (i = 0; i < PAT_INDEX_SIZE; i++)
987 pat_index[i] = pat_table[i];
989 /* Flush caches and TLBs again. */
993 /* Restore caches and PGE. */
999 * Initialize a vm_page's machine-dependent fields.
1002 pmap_page_init(vm_page_t m)
1005 TAILQ_INIT(&m->md.pv_list);
1006 m->md.pat_mode = PAT_WRITE_BACK;
1010 * Initialize the pmap module.
1011 * Called by vm_init, to initialize any structures that the pmap
1012 * system needs to map virtual memory.
1022 * Initialize the vm page array entries for the kernel pmap's
1025 for (i = 0; i < nkpt; i++) {
1026 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1027 KASSERT(mpte >= vm_page_array &&
1028 mpte < &vm_page_array[vm_page_array_size],
1029 ("pmap_init: page table page is out of range"));
1030 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1031 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1035 * If the kernel is running on a virtual machine, then it must assume
1036 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1037 * be prepared for the hypervisor changing the vendor and family that
1038 * are reported by CPUID. Consequently, the workaround for AMD Family
1039 * 10h Erratum 383 is enabled if the processor's feature set does not
1040 * include at least one feature that is only supported by older Intel
1041 * or newer AMD processors.
1043 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
1044 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1045 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1047 workaround_erratum383 = 1;
1050 * Are large page mappings enabled?
1052 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1053 if (pg_ps_enabled) {
1054 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1055 ("pmap_init: can't assign to pagesizes[1]"));
1056 pagesizes[1] = NBPDR;
1060 * Initialize the pv chunk list mutex.
1062 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1065 * Initialize the pool of pv list locks.
1067 for (i = 0; i < NPV_LIST_LOCKS; i++)
1068 rw_init(&pv_list_locks[i], "pmap pv list");
1071 * Calculate the size of the pv head table for superpages.
1073 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1076 * Allocate memory for the pv head table for superpages.
1078 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1080 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1082 for (i = 0; i < pv_npg; i++)
1083 TAILQ_INIT(&pv_table[i].pv_list);
1085 mtx_init(&cpage_lock, "cpage", NULL, MTX_DEF);
1086 cpage_a = kva_alloc(PAGE_SIZE);
1087 cpage_b = kva_alloc(PAGE_SIZE);
1090 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1091 "2MB page mapping counters");
1093 static u_long pmap_pde_demotions;
1094 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1095 &pmap_pde_demotions, 0, "2MB page demotions");
1097 static u_long pmap_pde_mappings;
1098 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1099 &pmap_pde_mappings, 0, "2MB page mappings");
1101 static u_long pmap_pde_p_failures;
1102 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1103 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1105 static u_long pmap_pde_promotions;
1106 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1107 &pmap_pde_promotions, 0, "2MB page promotions");
1109 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1110 "1GB page mapping counters");
1112 static u_long pmap_pdpe_demotions;
1113 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1114 &pmap_pdpe_demotions, 0, "1GB page demotions");
1116 /***************************************************
1117 * Low level helper routines.....
1118 ***************************************************/
1121 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1123 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1125 switch (pmap->pm_type) {
1128 /* Verify that both PAT bits are not set at the same time */
1129 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1130 ("Invalid PAT bits in entry %#lx", entry));
1132 /* Swap the PAT bits if one of them is set */
1133 if ((entry & x86_pat_bits) != 0)
1134 entry ^= x86_pat_bits;
1138 * Nothing to do - the memory attributes are represented
1139 * the same way for regular pages and superpages.
1143 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1150 * Determine the appropriate bits to set in a PTE or PDE for a specified
1154 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1156 int cache_bits, pat_flag, pat_idx;
1158 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1159 panic("Unknown caching mode %d\n", mode);
1161 switch (pmap->pm_type) {
1164 /* The PAT bit is different for PTE's and PDE's. */
1165 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1167 /* Map the caching mode to a PAT index. */
1168 pat_idx = pat_index[mode];
1170 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1173 cache_bits |= pat_flag;
1175 cache_bits |= PG_NC_PCD;
1177 cache_bits |= PG_NC_PWT;
1181 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1185 panic("unsupported pmap type %d", pmap->pm_type);
1188 return (cache_bits);
1192 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1196 switch (pmap->pm_type) {
1199 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1202 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1205 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1211 static __inline boolean_t
1212 pmap_ps_enabled(pmap_t pmap)
1215 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1219 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1222 switch (pmap->pm_type) {
1229 * This is a little bogus since the generation number is
1230 * supposed to be bumped up when a region of the address
1231 * space is invalidated in the page tables.
1233 * In this case the old PDE entry is valid but yet we want
1234 * to make sure that any mappings using the old entry are
1235 * invalidated in the TLB.
1237 * The reason this works as expected is because we rendezvous
1238 * "all" host cpus and force any vcpu context to exit as a
1241 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1244 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1246 pde_store(pde, newpde);
1250 * After changing the page size for the specified virtual address in the page
1251 * table, flush the corresponding entries from the processor's TLB. Only the
1252 * calling processor's TLB is affected.
1254 * The calling thread must be pinned to a processor.
1257 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1261 if (pmap_type_guest(pmap))
1264 KASSERT(pmap->pm_type == PT_X86,
1265 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1267 PG_G = pmap_global_bit(pmap);
1269 if ((newpde & PG_PS) == 0)
1270 /* Demotion: flush a specific 2MB page mapping. */
1272 else if ((newpde & PG_G) == 0)
1274 * Promotion: flush every 4KB page mapping from the TLB
1275 * because there are too many to flush individually.
1280 * Promotion: flush every 4KB page mapping from the TLB,
1281 * including any global (PG_G) mappings.
1289 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va)
1291 struct invpcid_descr d;
1294 if (invpcid_works) {
1295 d.pcid = pmap->pm_pcid;
1298 invpcid(&d, INVPCID_ADDR);
1304 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1306 load_cr3(cr3 | CR3_PCID_SAVE);
1311 * For SMP, these functions have to use the IPI mechanism for coherence.
1313 * N.B.: Before calling any of the following TLB invalidation functions,
1314 * the calling processor must ensure that all stores updating a non-
1315 * kernel page table are globally performed. Otherwise, another
1316 * processor could cache an old, pre-update entry without being
1317 * invalidated. This can happen one of two ways: (1) The pmap becomes
1318 * active on another processor after its pm_active field is checked by
1319 * one of the following functions but before a store updating the page
1320 * table is globally performed. (2) The pmap becomes active on another
1321 * processor before its pm_active field is checked but due to
1322 * speculative loads one of the following functions stills reads the
1323 * pmap as inactive on the other processor.
1325 * The kernel page table is exempt because its pm_active field is
1326 * immutable. The kernel page table is always active on every
1331 * Interrupt the cpus that are executing in the guest context.
1332 * This will force the vcpu to exit and the cached EPT mappings
1333 * will be invalidated by the host before the next vmresume.
1335 static __inline void
1336 pmap_invalidate_ept(pmap_t pmap)
1341 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1342 ("pmap_invalidate_ept: absurd pm_active"));
1345 * The TLB mappings associated with a vcpu context are not
1346 * flushed each time a different vcpu is chosen to execute.
1348 * This is in contrast with a process's vtop mappings that
1349 * are flushed from the TLB on each context switch.
1351 * Therefore we need to do more than just a TLB shootdown on
1352 * the active cpus in 'pmap->pm_active'. To do this we keep
1353 * track of the number of invalidations performed on this pmap.
1355 * Each vcpu keeps a cache of this counter and compares it
1356 * just before a vmresume. If the counter is out-of-date an
1357 * invept will be done to flush stale mappings from the TLB.
1359 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1362 * Force the vcpu to exit and trap back into the hypervisor.
1364 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1365 ipi_selected(pmap->pm_active, ipinum);
1370 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1372 cpuset_t other_cpus;
1375 if (pmap_type_guest(pmap)) {
1376 pmap_invalidate_ept(pmap);
1380 KASSERT(pmap->pm_type == PT_X86,
1381 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1384 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1385 if (!pmap_pcid_enabled) {
1388 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1389 if (pmap == PCPU_GET(curpmap))
1392 pmap_invalidate_page_pcid(pmap, va);
1397 smp_invlpg(pmap, va);
1399 cpuid = PCPU_GET(cpuid);
1400 other_cpus = all_cpus;
1401 CPU_CLR(cpuid, &other_cpus);
1402 if (CPU_ISSET(cpuid, &pmap->pm_active))
1404 else if (pmap_pcid_enabled) {
1405 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1406 pmap_invalidate_page_pcid(pmap, va);
1410 if (pmap_pcid_enabled)
1411 CPU_AND(&other_cpus, &pmap->pm_save);
1413 CPU_AND(&other_cpus, &pmap->pm_active);
1414 if (!CPU_EMPTY(&other_cpus))
1415 smp_masked_invlpg(other_cpus, pmap, va);
1421 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1423 struct invpcid_descr d;
1427 if (invpcid_works) {
1428 d.pcid = pmap->pm_pcid;
1430 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
1432 invpcid(&d, INVPCID_ADDR);
1439 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1440 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1442 load_cr3(cr3 | CR3_PCID_SAVE);
1447 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1449 cpuset_t other_cpus;
1453 if (pmap_type_guest(pmap)) {
1454 pmap_invalidate_ept(pmap);
1458 KASSERT(pmap->pm_type == PT_X86,
1459 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1462 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1463 if (!pmap_pcid_enabled) {
1464 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1467 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1468 if (pmap == PCPU_GET(curpmap)) {
1469 for (addr = sva; addr < eva;
1473 pmap_invalidate_range_pcid(pmap,
1480 smp_invlpg_range(pmap, sva, eva);
1482 cpuid = PCPU_GET(cpuid);
1483 other_cpus = all_cpus;
1484 CPU_CLR(cpuid, &other_cpus);
1485 if (CPU_ISSET(cpuid, &pmap->pm_active)) {
1486 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1488 } else if (pmap_pcid_enabled) {
1489 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1490 pmap_invalidate_range_pcid(pmap, sva, eva);
1494 if (pmap_pcid_enabled)
1495 CPU_AND(&other_cpus, &pmap->pm_save);
1497 CPU_AND(&other_cpus, &pmap->pm_active);
1498 if (!CPU_EMPTY(&other_cpus))
1499 smp_masked_invlpg_range(other_cpus, pmap, sva, eva);
1505 pmap_invalidate_all(pmap_t pmap)
1507 cpuset_t other_cpus;
1508 struct invpcid_descr d;
1512 if (pmap_type_guest(pmap)) {
1513 pmap_invalidate_ept(pmap);
1517 KASSERT(pmap->pm_type == PT_X86,
1518 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1521 cpuid = PCPU_GET(cpuid);
1522 if (pmap == kernel_pmap ||
1523 (pmap_pcid_enabled && !CPU_CMP(&pmap->pm_save, &all_cpus)) ||
1524 !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1525 if (invpcid_works) {
1526 bzero(&d, sizeof(d));
1527 invpcid(&d, INVPCID_CTXGLOB);
1531 if (!CPU_ISSET(cpuid, &pmap->pm_active))
1532 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1535 other_cpus = all_cpus;
1536 CPU_CLR(cpuid, &other_cpus);
1539 * This logic is duplicated in the Xinvltlb shootdown
1542 if (pmap_pcid_enabled) {
1543 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1544 if (invpcid_works) {
1545 d.pcid = pmap->pm_pcid;
1548 invpcid(&d, INVPCID_CTX);
1554 * Bit 63 is clear, pcid TLB
1555 * entries are invalidated.
1557 load_cr3(pmap->pm_cr3);
1558 load_cr3(cr3 | CR3_PCID_SAVE);
1564 } else if (CPU_ISSET(cpuid, &pmap->pm_active))
1566 if (!CPU_ISSET(cpuid, &pmap->pm_active))
1567 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1568 if (pmap_pcid_enabled)
1569 CPU_AND(&other_cpus, &pmap->pm_save);
1571 CPU_AND(&other_cpus, &pmap->pm_active);
1572 if (!CPU_EMPTY(&other_cpus))
1573 smp_masked_invltlb(other_cpus, pmap);
1579 pmap_invalidate_cache(void)
1589 cpuset_t invalidate; /* processors that invalidate their TLB */
1594 u_int store; /* processor that updates the PDE */
1598 pmap_update_pde_action(void *arg)
1600 struct pde_action *act = arg;
1602 if (act->store == PCPU_GET(cpuid))
1603 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1607 pmap_update_pde_teardown(void *arg)
1609 struct pde_action *act = arg;
1611 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1612 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1616 * Change the page size for the specified virtual address in a way that
1617 * prevents any possibility of the TLB ever having two entries that map the
1618 * same virtual address using different page sizes. This is the recommended
1619 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1620 * machine check exception for a TLB state that is improperly diagnosed as a
1624 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1626 struct pde_action act;
1627 cpuset_t active, other_cpus;
1631 cpuid = PCPU_GET(cpuid);
1632 other_cpus = all_cpus;
1633 CPU_CLR(cpuid, &other_cpus);
1634 if (pmap == kernel_pmap || pmap_type_guest(pmap))
1637 active = pmap->pm_active;
1638 CPU_AND_ATOMIC(&pmap->pm_save, &active);
1640 if (CPU_OVERLAP(&active, &other_cpus)) {
1642 act.invalidate = active;
1646 act.newpde = newpde;
1647 CPU_SET(cpuid, &active);
1648 smp_rendezvous_cpus(active,
1649 smp_no_rendevous_barrier, pmap_update_pde_action,
1650 pmap_update_pde_teardown, &act);
1652 pmap_update_pde_store(pmap, pde, newpde);
1653 if (CPU_ISSET(cpuid, &active))
1654 pmap_update_pde_invalidate(pmap, va, newpde);
1660 * Normal, non-SMP, invalidation functions.
1661 * We inline these within pmap.c for speed.
1664 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1667 switch (pmap->pm_type) {
1669 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1677 panic("pmap_invalidate_page: unknown type: %d", pmap->pm_type);
1682 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1686 switch (pmap->pm_type) {
1688 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1689 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1697 panic("pmap_invalidate_range: unknown type: %d", pmap->pm_type);
1702 pmap_invalidate_all(pmap_t pmap)
1705 switch (pmap->pm_type) {
1707 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1715 panic("pmap_invalidate_all: unknown type %d", pmap->pm_type);
1720 pmap_invalidate_cache(void)
1727 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1730 pmap_update_pde_store(pmap, pde, newpde);
1731 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1732 pmap_update_pde_invalidate(pmap, va, newpde);
1734 CPU_ZERO(&pmap->pm_save);
1738 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1741 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1745 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1747 KASSERT((sva & PAGE_MASK) == 0,
1748 ("pmap_invalidate_cache_range: sva not page-aligned"));
1749 KASSERT((eva & PAGE_MASK) == 0,
1750 ("pmap_invalidate_cache_range: eva not page-aligned"));
1753 if ((cpu_feature & CPUID_SS) != 0 && !force)
1754 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1755 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1756 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1759 * XXX: Some CPUs fault, hang, or trash the local APIC
1760 * registers if we use CLFLUSH on the local APIC
1761 * range. The local APIC is always uncached, so we
1762 * don't need to flush for that range anyway.
1764 if (pmap_kextract(sva) == lapic_paddr)
1768 * Otherwise, do per-cache line flush. Use the mfence
1769 * instruction to insure that previous stores are
1770 * included in the write-back. The processor
1771 * propagates flush to other processors in the cache
1775 for (; sva < eva; sva += cpu_clflush_line_size)
1781 * No targeted cache flush methods are supported by CPU,
1782 * or the supplied range is bigger than 2MB.
1783 * Globally invalidate cache.
1785 pmap_invalidate_cache();
1790 * Remove the specified set of pages from the data and instruction caches.
1792 * In contrast to pmap_invalidate_cache_range(), this function does not
1793 * rely on the CPU's self-snoop feature, because it is intended for use
1794 * when moving pages into a different cache domain.
1797 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1799 vm_offset_t daddr, eva;
1802 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1803 (cpu_feature & CPUID_CLFSH) == 0)
1804 pmap_invalidate_cache();
1807 for (i = 0; i < count; i++) {
1808 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1809 eva = daddr + PAGE_SIZE;
1810 for (; daddr < eva; daddr += cpu_clflush_line_size)
1818 * Routine: pmap_extract
1820 * Extract the physical page address associated
1821 * with the given map/virtual_address pair.
1824 pmap_extract(pmap_t pmap, vm_offset_t va)
1828 pt_entry_t *pte, PG_V;
1832 PG_V = pmap_valid_bit(pmap);
1834 pdpe = pmap_pdpe(pmap, va);
1835 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1836 if ((*pdpe & PG_PS) != 0)
1837 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1839 pde = pmap_pdpe_to_pde(pdpe, va);
1840 if ((*pde & PG_V) != 0) {
1841 if ((*pde & PG_PS) != 0) {
1842 pa = (*pde & PG_PS_FRAME) |
1845 pte = pmap_pde_to_pte(pde, va);
1846 pa = (*pte & PG_FRAME) |
1857 * Routine: pmap_extract_and_hold
1859 * Atomically extract and hold the physical page
1860 * with the given pmap and virtual address pair
1861 * if that mapping permits the given protection.
1864 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1866 pd_entry_t pde, *pdep;
1867 pt_entry_t pte, PG_RW, PG_V;
1873 PG_RW = pmap_rw_bit(pmap);
1874 PG_V = pmap_valid_bit(pmap);
1877 pdep = pmap_pde(pmap, va);
1878 if (pdep != NULL && (pde = *pdep)) {
1880 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1881 if (vm_page_pa_tryrelock(pmap, (pde &
1882 PG_PS_FRAME) | (va & PDRMASK), &pa))
1884 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1889 pte = *pmap_pde_to_pte(pdep, va);
1891 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1892 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1895 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1906 pmap_kextract(vm_offset_t va)
1911 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1912 pa = DMAP_TO_PHYS(va);
1916 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1919 * Beware of a concurrent promotion that changes the
1920 * PDE at this point! For example, vtopte() must not
1921 * be used to access the PTE because it would use the
1922 * new PDE. It is, however, safe to use the old PDE
1923 * because the page table page is preserved by the
1926 pa = *pmap_pde_to_pte(&pde, va);
1927 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1933 /***************************************************
1934 * Low level mapping routines.....
1935 ***************************************************/
1938 * Add a wired page to the kva.
1939 * Note: not SMP coherent.
1942 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1947 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
1950 static __inline void
1951 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1957 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
1958 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
1962 * Remove a page from the kernel pagetables.
1963 * Note: not SMP coherent.
1966 pmap_kremove(vm_offset_t va)
1975 * Used to map a range of physical addresses into kernel
1976 * virtual address space.
1978 * The value passed in '*virt' is a suggested virtual address for
1979 * the mapping. Architectures which can support a direct-mapped
1980 * physical to virtual region can return the appropriate address
1981 * within that region, leaving '*virt' unchanged. Other
1982 * architectures should map the pages starting at '*virt' and
1983 * update '*virt' with the first usable address after the mapped
1987 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1989 return PHYS_TO_DMAP(start);
1994 * Add a list of wired pages to the kva
1995 * this routine is only used for temporary
1996 * kernel mappings that do not need to have
1997 * page modification or references recorded.
1998 * Note that old mappings are simply written
1999 * over. The page *must* be wired.
2000 * Note: SMP coherent. Uses a ranged shootdown IPI.
2003 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
2005 pt_entry_t *endpte, oldpte, pa, *pte;
2011 endpte = pte + count;
2012 while (pte < endpte) {
2014 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
2015 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
2016 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
2018 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
2022 if (__predict_false((oldpte & X86_PG_V) != 0))
2023 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2028 * This routine tears out page mappings from the
2029 * kernel -- it is meant only for temporary mappings.
2030 * Note: SMP coherent. Uses a ranged shootdown IPI.
2033 pmap_qremove(vm_offset_t sva, int count)
2038 while (count-- > 0) {
2039 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2043 pmap_invalidate_range(kernel_pmap, sva, va);
2046 /***************************************************
2047 * Page table page management routines.....
2048 ***************************************************/
2049 static __inline void
2050 pmap_free_zero_pages(struct spglist *free)
2054 while ((m = SLIST_FIRST(free)) != NULL) {
2055 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2056 /* Preserve the page's PG_ZERO setting. */
2057 vm_page_free_toq(m);
2062 * Schedule the specified unused page table page to be freed. Specifically,
2063 * add the page to the specified list of pages that will be released to the
2064 * physical memory manager after the TLB has been updated.
2066 static __inline void
2067 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2068 boolean_t set_PG_ZERO)
2072 m->flags |= PG_ZERO;
2074 m->flags &= ~PG_ZERO;
2075 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2079 * Inserts the specified page table page into the specified pmap's collection
2080 * of idle page table pages. Each of a pmap's page table pages is responsible
2081 * for mapping a distinct range of virtual addresses. The pmap's collection is
2082 * ordered by this virtual address range.
2085 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2088 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2089 return (vm_radix_insert(&pmap->pm_root, mpte));
2093 * Looks for a page table page mapping the specified virtual address in the
2094 * specified pmap's collection of idle page table pages. Returns NULL if there
2095 * is no page table page corresponding to the specified virtual address.
2097 static __inline vm_page_t
2098 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
2101 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2102 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
2106 * Removes the specified page table page from the specified pmap's collection
2107 * of idle page table pages. The specified page table page must be a member of
2108 * the pmap's collection.
2110 static __inline void
2111 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
2114 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2115 vm_radix_remove(&pmap->pm_root, mpte->pindex);
2119 * Decrements a page table page's wire count, which is used to record the
2120 * number of valid page table entries within the page. If the wire count
2121 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2122 * page table page was unmapped and FALSE otherwise.
2124 static inline boolean_t
2125 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2129 if (m->wire_count == 0) {
2130 _pmap_unwire_ptp(pmap, va, m, free);
2137 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2140 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2142 * unmap the page table page
2144 if (m->pindex >= (NUPDE + NUPDPE)) {
2147 pml4 = pmap_pml4e(pmap, va);
2149 } else if (m->pindex >= NUPDE) {
2152 pdp = pmap_pdpe(pmap, va);
2157 pd = pmap_pde(pmap, va);
2160 pmap_resident_count_dec(pmap, 1);
2161 if (m->pindex < NUPDE) {
2162 /* We just released a PT, unhold the matching PD */
2165 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2166 pmap_unwire_ptp(pmap, va, pdpg, free);
2168 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2169 /* We just released a PD, unhold the matching PDP */
2172 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2173 pmap_unwire_ptp(pmap, va, pdppg, free);
2177 * This is a release store so that the ordinary store unmapping
2178 * the page table page is globally performed before TLB shoot-
2181 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
2184 * Put page on a list so that it is released after
2185 * *ALL* TLB shootdown is done
2187 pmap_add_delayed_free_list(m, free, TRUE);
2191 * After removing a page table entry, this routine is used to
2192 * conditionally free the page, and manage the hold/wire counts.
2195 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2196 struct spglist *free)
2200 if (va >= VM_MAXUSER_ADDRESS)
2202 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2203 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2204 return (pmap_unwire_ptp(pmap, va, mpte, free));
2208 pmap_pinit0(pmap_t pmap)
2211 PMAP_LOCK_INIT(pmap);
2212 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2213 pmap->pm_cr3 = KPML4phys;
2214 pmap->pm_root.rt_root = 0;
2215 CPU_ZERO(&pmap->pm_active);
2216 CPU_ZERO(&pmap->pm_save);
2217 PCPU_SET(curpmap, pmap);
2218 TAILQ_INIT(&pmap->pm_pvchunk);
2219 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2220 pmap->pm_pcid = pmap_pcid_enabled ? 0 : -1;
2221 pmap->pm_flags = pmap_flags;
2225 * Initialize a preallocated and zeroed pmap structure,
2226 * such as one in a vmspace structure.
2229 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2232 vm_paddr_t pml4phys;
2236 * allocate the page directory page
2238 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2239 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2242 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2243 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2245 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2247 if ((pml4pg->flags & PG_ZERO) == 0)
2248 pagezero(pmap->pm_pml4);
2251 * Do not install the host kernel mappings in the nested page
2252 * tables. These mappings are meaningless in the guest physical
2255 if ((pmap->pm_type = pm_type) == PT_X86) {
2256 pmap->pm_cr3 = pml4phys;
2258 /* Wire in kernel global address entries. */
2259 for (i = 0; i < NKPML4E; i++) {
2260 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
2261 X86_PG_RW | X86_PG_V | PG_U;
2263 for (i = 0; i < ndmpdpphys; i++) {
2264 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
2265 X86_PG_RW | X86_PG_V | PG_U;
2268 /* install self-referential address mapping entry(s) */
2269 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
2270 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2272 if (pmap_pcid_enabled) {
2273 pmap->pm_pcid = alloc_unr(&pcid_unr);
2274 if (pmap->pm_pcid != -1)
2275 pmap->pm_cr3 |= pmap->pm_pcid;
2279 pmap->pm_root.rt_root = 0;
2280 CPU_ZERO(&pmap->pm_active);
2281 TAILQ_INIT(&pmap->pm_pvchunk);
2282 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2283 pmap->pm_flags = flags;
2284 pmap->pm_eptgen = 0;
2285 CPU_ZERO(&pmap->pm_save);
2291 pmap_pinit(pmap_t pmap)
2294 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2298 * This routine is called if the desired page table page does not exist.
2300 * If page table page allocation fails, this routine may sleep before
2301 * returning NULL. It sleeps only if a lock pointer was given.
2303 * Note: If a page allocation fails at page table level two or three,
2304 * one or two pages may be held during the wait, only to be released
2305 * afterwards. This conservative approach is easily argued to avoid
2309 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2311 vm_page_t m, pdppg, pdpg;
2312 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2314 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2316 PG_A = pmap_accessed_bit(pmap);
2317 PG_M = pmap_modified_bit(pmap);
2318 PG_V = pmap_valid_bit(pmap);
2319 PG_RW = pmap_rw_bit(pmap);
2322 * Allocate a page table page.
2324 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2325 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2326 if (lockp != NULL) {
2327 RELEASE_PV_LIST_LOCK(lockp);
2329 rw_runlock(&pvh_global_lock);
2331 rw_rlock(&pvh_global_lock);
2336 * Indicate the need to retry. While waiting, the page table
2337 * page may have been allocated.
2341 if ((m->flags & PG_ZERO) == 0)
2345 * Map the pagetable page into the process address space, if
2346 * it isn't already there.
2349 if (ptepindex >= (NUPDE + NUPDPE)) {
2351 vm_pindex_t pml4index;
2353 /* Wire up a new PDPE page */
2354 pml4index = ptepindex - (NUPDE + NUPDPE);
2355 pml4 = &pmap->pm_pml4[pml4index];
2356 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2358 } else if (ptepindex >= NUPDE) {
2359 vm_pindex_t pml4index;
2360 vm_pindex_t pdpindex;
2364 /* Wire up a new PDE page */
2365 pdpindex = ptepindex - NUPDE;
2366 pml4index = pdpindex >> NPML4EPGSHIFT;
2368 pml4 = &pmap->pm_pml4[pml4index];
2369 if ((*pml4 & PG_V) == 0) {
2370 /* Have to allocate a new pdp, recurse */
2371 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2374 atomic_subtract_int(&cnt.v_wire_count, 1);
2375 vm_page_free_zero(m);
2379 /* Add reference to pdp page */
2380 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2381 pdppg->wire_count++;
2383 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2385 /* Now find the pdp page */
2386 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2387 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2390 vm_pindex_t pml4index;
2391 vm_pindex_t pdpindex;
2396 /* Wire up a new PTE page */
2397 pdpindex = ptepindex >> NPDPEPGSHIFT;
2398 pml4index = pdpindex >> NPML4EPGSHIFT;
2400 /* First, find the pdp and check that its valid. */
2401 pml4 = &pmap->pm_pml4[pml4index];
2402 if ((*pml4 & PG_V) == 0) {
2403 /* Have to allocate a new pd, recurse */
2404 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2407 atomic_subtract_int(&cnt.v_wire_count, 1);
2408 vm_page_free_zero(m);
2411 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2412 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2414 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2415 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2416 if ((*pdp & PG_V) == 0) {
2417 /* Have to allocate a new pd, recurse */
2418 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2421 atomic_subtract_int(&cnt.v_wire_count,
2423 vm_page_free_zero(m);
2427 /* Add reference to the pd page */
2428 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2432 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2434 /* Now we know where the page directory page is */
2435 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2436 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2439 pmap_resident_count_inc(pmap, 1);
2445 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2447 vm_pindex_t pdpindex, ptepindex;
2448 pdp_entry_t *pdpe, PG_V;
2451 PG_V = pmap_valid_bit(pmap);
2454 pdpe = pmap_pdpe(pmap, va);
2455 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2456 /* Add a reference to the pd page. */
2457 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2460 /* Allocate a pd page. */
2461 ptepindex = pmap_pde_pindex(va);
2462 pdpindex = ptepindex >> NPDPEPGSHIFT;
2463 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2464 if (pdpg == NULL && lockp != NULL)
2471 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2473 vm_pindex_t ptepindex;
2474 pd_entry_t *pd, PG_V;
2477 PG_V = pmap_valid_bit(pmap);
2480 * Calculate pagetable page index
2482 ptepindex = pmap_pde_pindex(va);
2485 * Get the page directory entry
2487 pd = pmap_pde(pmap, va);
2490 * This supports switching from a 2MB page to a
2493 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2494 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2496 * Invalidation of the 2MB page mapping may have caused
2497 * the deallocation of the underlying PD page.
2504 * If the page table page is mapped, we just increment the
2505 * hold count, and activate it.
2507 if (pd != NULL && (*pd & PG_V) != 0) {
2508 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2512 * Here if the pte page isn't mapped, or if it has been
2515 m = _pmap_allocpte(pmap, ptepindex, lockp);
2516 if (m == NULL && lockp != NULL)
2523 /***************************************************
2524 * Pmap allocation/deallocation routines.
2525 ***************************************************/
2528 * Release any resources held by the given physical map.
2529 * Called when a pmap initialized by pmap_pinit is being released.
2530 * Should only be called if the map contains no valid mappings.
2533 pmap_release(pmap_t pmap)
2538 KASSERT(pmap->pm_stats.resident_count == 0,
2539 ("pmap_release: pmap resident count %ld != 0",
2540 pmap->pm_stats.resident_count));
2541 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2542 ("pmap_release: pmap has reserved page table page(s)"));
2544 if (pmap_pcid_enabled) {
2546 * Invalidate any left TLB entries, to allow the reuse
2549 pmap_invalidate_all(pmap);
2552 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2554 for (i = 0; i < NKPML4E; i++) /* KVA */
2555 pmap->pm_pml4[KPML4BASE + i] = 0;
2556 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2557 pmap->pm_pml4[DMPML4I + i] = 0;
2558 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2561 atomic_subtract_int(&cnt.v_wire_count, 1);
2562 vm_page_free_zero(m);
2563 if (pmap->pm_pcid != -1)
2564 free_unr(&pcid_unr, pmap->pm_pcid);
2568 kvm_size(SYSCTL_HANDLER_ARGS)
2570 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2572 return sysctl_handle_long(oidp, &ksize, 0, req);
2574 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2575 0, 0, kvm_size, "LU", "Size of KVM");
2578 kvm_free(SYSCTL_HANDLER_ARGS)
2580 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2582 return sysctl_handle_long(oidp, &kfree, 0, req);
2584 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2585 0, 0, kvm_free, "LU", "Amount of KVM free");
2588 * grow the number of kernel page table entries, if needed
2591 pmap_growkernel(vm_offset_t addr)
2595 pd_entry_t *pde, newpdir;
2598 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2601 * Return if "addr" is within the range of kernel page table pages
2602 * that were preallocated during pmap bootstrap. Moreover, leave
2603 * "kernel_vm_end" and the kernel page table as they were.
2605 * The correctness of this action is based on the following
2606 * argument: vm_map_insert() allocates contiguous ranges of the
2607 * kernel virtual address space. It calls this function if a range
2608 * ends after "kernel_vm_end". If the kernel is mapped between
2609 * "kernel_vm_end" and "addr", then the range cannot begin at
2610 * "kernel_vm_end". In fact, its beginning address cannot be less
2611 * than the kernel. Thus, there is no immediate need to allocate
2612 * any new kernel page table pages between "kernel_vm_end" and
2615 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2618 addr = roundup2(addr, NBPDR);
2619 if (addr - 1 >= kernel_map->max_offset)
2620 addr = kernel_map->max_offset;
2621 while (kernel_vm_end < addr) {
2622 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2623 if ((*pdpe & X86_PG_V) == 0) {
2624 /* We need a new PDP entry */
2625 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2626 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2627 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2629 panic("pmap_growkernel: no memory to grow kernel");
2630 if ((nkpg->flags & PG_ZERO) == 0)
2631 pmap_zero_page(nkpg);
2632 paddr = VM_PAGE_TO_PHYS(nkpg);
2633 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2634 X86_PG_A | X86_PG_M);
2635 continue; /* try again */
2637 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2638 if ((*pde & X86_PG_V) != 0) {
2639 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2640 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2641 kernel_vm_end = kernel_map->max_offset;
2647 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2648 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2651 panic("pmap_growkernel: no memory to grow kernel");
2652 if ((nkpg->flags & PG_ZERO) == 0)
2653 pmap_zero_page(nkpg);
2654 paddr = VM_PAGE_TO_PHYS(nkpg);
2655 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2656 pde_store(pde, newpdir);
2658 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2659 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2660 kernel_vm_end = kernel_map->max_offset;
2667 /***************************************************
2668 * page management routines.
2669 ***************************************************/
2671 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2672 CTASSERT(_NPCM == 3);
2673 CTASSERT(_NPCPV == 168);
2675 static __inline struct pv_chunk *
2676 pv_to_chunk(pv_entry_t pv)
2679 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2682 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2684 #define PC_FREE0 0xfffffffffffffffful
2685 #define PC_FREE1 0xfffffffffffffffful
2686 #define PC_FREE2 0x000000fffffffffful
2688 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2691 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2693 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2694 "Current number of pv entry chunks");
2695 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2696 "Current number of pv entry chunks allocated");
2697 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2698 "Current number of pv entry chunks frees");
2699 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2700 "Number of times tried to get a chunk page but failed.");
2702 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2703 static int pv_entry_spare;
2705 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2706 "Current number of pv entry frees");
2707 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2708 "Current number of pv entry allocs");
2709 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2710 "Current number of pv entries");
2711 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2712 "Current number of spare pv entries");
2716 * We are in a serious low memory condition. Resort to
2717 * drastic measures to free some pages so we can allocate
2718 * another pv entry chunk.
2720 * Returns NULL if PV entries were reclaimed from the specified pmap.
2722 * We do not, however, unmap 2mpages because subsequent accesses will
2723 * allocate per-page pv entries until repromotion occurs, thereby
2724 * exacerbating the shortage of free pv entries.
2727 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2729 struct pch new_tail;
2730 struct pv_chunk *pc;
2731 struct md_page *pvh;
2734 pt_entry_t *pte, tpte;
2735 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2739 struct spglist free;
2741 int bit, field, freed;
2743 rw_assert(&pvh_global_lock, RA_LOCKED);
2744 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2745 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2748 PG_G = PG_A = PG_M = PG_RW = 0;
2750 TAILQ_INIT(&new_tail);
2751 mtx_lock(&pv_chunks_mutex);
2752 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2753 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2754 mtx_unlock(&pv_chunks_mutex);
2755 if (pmap != pc->pc_pmap) {
2757 pmap_invalidate_all(pmap);
2758 if (pmap != locked_pmap)
2762 /* Avoid deadlock and lock recursion. */
2763 if (pmap > locked_pmap) {
2764 RELEASE_PV_LIST_LOCK(lockp);
2766 } else if (pmap != locked_pmap &&
2767 !PMAP_TRYLOCK(pmap)) {
2769 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2770 mtx_lock(&pv_chunks_mutex);
2773 PG_G = pmap_global_bit(pmap);
2774 PG_A = pmap_accessed_bit(pmap);
2775 PG_M = pmap_modified_bit(pmap);
2776 PG_RW = pmap_rw_bit(pmap);
2780 * Destroy every non-wired, 4 KB page mapping in the chunk.
2783 for (field = 0; field < _NPCM; field++) {
2784 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2785 inuse != 0; inuse &= ~(1UL << bit)) {
2787 pv = &pc->pc_pventry[field * 64 + bit];
2789 pde = pmap_pde(pmap, va);
2790 if ((*pde & PG_PS) != 0)
2792 pte = pmap_pde_to_pte(pde, va);
2793 if ((*pte & PG_W) != 0)
2795 tpte = pte_load_clear(pte);
2796 if ((tpte & PG_G) != 0)
2797 pmap_invalidate_page(pmap, va);
2798 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2799 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2801 if ((tpte & PG_A) != 0)
2802 vm_page_aflag_set(m, PGA_REFERENCED);
2803 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2804 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2806 if (TAILQ_EMPTY(&m->md.pv_list) &&
2807 (m->flags & PG_FICTITIOUS) == 0) {
2808 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2809 if (TAILQ_EMPTY(&pvh->pv_list)) {
2810 vm_page_aflag_clear(m,
2814 pc->pc_map[field] |= 1UL << bit;
2815 pmap_unuse_pt(pmap, va, *pde, &free);
2820 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2821 mtx_lock(&pv_chunks_mutex);
2824 /* Every freed mapping is for a 4 KB page. */
2825 pmap_resident_count_dec(pmap, freed);
2826 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2827 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2828 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2829 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2830 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2831 pc->pc_map[2] == PC_FREE2) {
2832 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2833 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2834 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2835 /* Entire chunk is free; return it. */
2836 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2837 dump_drop_page(m_pc->phys_addr);
2838 mtx_lock(&pv_chunks_mutex);
2841 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2842 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2843 mtx_lock(&pv_chunks_mutex);
2844 /* One freed pv entry in locked_pmap is sufficient. */
2845 if (pmap == locked_pmap)
2848 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2849 mtx_unlock(&pv_chunks_mutex);
2851 pmap_invalidate_all(pmap);
2852 if (pmap != locked_pmap)
2855 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2856 m_pc = SLIST_FIRST(&free);
2857 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2858 /* Recycle a freed page table page. */
2859 m_pc->wire_count = 1;
2860 atomic_add_int(&cnt.v_wire_count, 1);
2862 pmap_free_zero_pages(&free);
2867 * free the pv_entry back to the free list
2870 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2872 struct pv_chunk *pc;
2873 int idx, field, bit;
2875 rw_assert(&pvh_global_lock, RA_LOCKED);
2876 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2877 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2878 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2879 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2880 pc = pv_to_chunk(pv);
2881 idx = pv - &pc->pc_pventry[0];
2884 pc->pc_map[field] |= 1ul << bit;
2885 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2886 pc->pc_map[2] != PC_FREE2) {
2887 /* 98% of the time, pc is already at the head of the list. */
2888 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2889 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2890 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2894 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2899 free_pv_chunk(struct pv_chunk *pc)
2903 mtx_lock(&pv_chunks_mutex);
2904 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2905 mtx_unlock(&pv_chunks_mutex);
2906 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2907 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2908 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2909 /* entire chunk is free, return it */
2910 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2911 dump_drop_page(m->phys_addr);
2912 vm_page_unwire(m, 0);
2917 * Returns a new PV entry, allocating a new PV chunk from the system when
2918 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2919 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2922 * The given PV list lock may be released.
2925 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2929 struct pv_chunk *pc;
2932 rw_assert(&pvh_global_lock, RA_LOCKED);
2933 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2934 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2936 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2938 for (field = 0; field < _NPCM; field++) {
2939 if (pc->pc_map[field]) {
2940 bit = bsfq(pc->pc_map[field]);
2944 if (field < _NPCM) {
2945 pv = &pc->pc_pventry[field * 64 + bit];
2946 pc->pc_map[field] &= ~(1ul << bit);
2947 /* If this was the last item, move it to tail */
2948 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2949 pc->pc_map[2] == 0) {
2950 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2951 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2954 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2955 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2959 /* No free items, allocate another chunk */
2960 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2963 if (lockp == NULL) {
2964 PV_STAT(pc_chunk_tryfail++);
2967 m = reclaim_pv_chunk(pmap, lockp);
2971 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2972 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2973 dump_add_page(m->phys_addr);
2974 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2976 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2977 pc->pc_map[1] = PC_FREE1;
2978 pc->pc_map[2] = PC_FREE2;
2979 mtx_lock(&pv_chunks_mutex);
2980 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2981 mtx_unlock(&pv_chunks_mutex);
2982 pv = &pc->pc_pventry[0];
2983 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2984 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2985 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2990 * Returns the number of one bits within the given PV chunk map element.
2993 popcnt_pc_map_elem(uint64_t elem)
2998 * This simple method of counting the one bits performs well because
2999 * the given element typically contains more zero bits than one bits.
3002 for (; elem != 0; elem &= elem - 1)
3008 * Ensure that the number of spare PV entries in the specified pmap meets or
3009 * exceeds the given count, "needed".
3011 * The given PV list lock may be released.
3014 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
3016 struct pch new_tail;
3017 struct pv_chunk *pc;
3021 rw_assert(&pvh_global_lock, RA_LOCKED);
3022 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3023 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
3026 * Newly allocated PV chunks must be stored in a private list until
3027 * the required number of PV chunks have been allocated. Otherwise,
3028 * reclaim_pv_chunk() could recycle one of these chunks. In
3029 * contrast, these chunks must be added to the pmap upon allocation.
3031 TAILQ_INIT(&new_tail);
3034 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3035 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
3036 free = popcnt_pc_map_elem(pc->pc_map[0]);
3037 free += popcnt_pc_map_elem(pc->pc_map[1]);
3038 free += popcnt_pc_map_elem(pc->pc_map[2]);
3040 free = popcntq(pc->pc_map[0]);
3041 free += popcntq(pc->pc_map[1]);
3042 free += popcntq(pc->pc_map[2]);
3047 if (avail >= needed)
3050 for (; avail < needed; avail += _NPCPV) {
3051 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3054 m = reclaim_pv_chunk(pmap, lockp);
3058 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3059 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3060 dump_add_page(m->phys_addr);
3061 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3063 pc->pc_map[0] = PC_FREE0;
3064 pc->pc_map[1] = PC_FREE1;
3065 pc->pc_map[2] = PC_FREE2;
3066 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3067 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3068 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3070 if (!TAILQ_EMPTY(&new_tail)) {
3071 mtx_lock(&pv_chunks_mutex);
3072 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3073 mtx_unlock(&pv_chunks_mutex);
3078 * First find and then remove the pv entry for the specified pmap and virtual
3079 * address from the specified pv list. Returns the pv entry if found and NULL
3080 * otherwise. This operation can be performed on pv lists for either 4KB or
3081 * 2MB page mappings.
3083 static __inline pv_entry_t
3084 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3088 rw_assert(&pvh_global_lock, RA_LOCKED);
3089 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3090 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3091 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3100 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3101 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3102 * entries for each of the 4KB page mappings.
3105 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3106 struct rwlock **lockp)
3108 struct md_page *pvh;
3109 struct pv_chunk *pc;
3111 vm_offset_t va_last;
3115 rw_assert(&pvh_global_lock, RA_LOCKED);
3116 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3117 KASSERT((pa & PDRMASK) == 0,
3118 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3119 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3122 * Transfer the 2mpage's pv entry for this mapping to the first
3123 * page's pv list. Once this transfer begins, the pv list lock
3124 * must not be released until the last pv entry is reinstantiated.
3126 pvh = pa_to_pvh(pa);
3127 va = trunc_2mpage(va);
3128 pv = pmap_pvh_remove(pvh, pmap, va);
3129 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3130 m = PHYS_TO_VM_PAGE(pa);
3131 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3133 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3134 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3135 va_last = va + NBPDR - PAGE_SIZE;
3137 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3138 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3139 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3140 for (field = 0; field < _NPCM; field++) {
3141 while (pc->pc_map[field]) {
3142 bit = bsfq(pc->pc_map[field]);
3143 pc->pc_map[field] &= ~(1ul << bit);
3144 pv = &pc->pc_pventry[field * 64 + bit];
3148 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3149 ("pmap_pv_demote_pde: page %p is not managed", m));
3150 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3156 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3157 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3160 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3161 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3162 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3164 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3165 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3169 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3170 * replace the many pv entries for the 4KB page mappings by a single pv entry
3171 * for the 2MB page mapping.
3174 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3175 struct rwlock **lockp)
3177 struct md_page *pvh;
3179 vm_offset_t va_last;
3182 rw_assert(&pvh_global_lock, RA_LOCKED);
3183 KASSERT((pa & PDRMASK) == 0,
3184 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3185 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3188 * Transfer the first page's pv entry for this mapping to the 2mpage's
3189 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3190 * a transfer avoids the possibility that get_pv_entry() calls
3191 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3192 * mappings that is being promoted.
3194 m = PHYS_TO_VM_PAGE(pa);
3195 va = trunc_2mpage(va);
3196 pv = pmap_pvh_remove(&m->md, pmap, va);
3197 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3198 pvh = pa_to_pvh(pa);
3199 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3201 /* Free the remaining NPTEPG - 1 pv entries. */
3202 va_last = va + NBPDR - PAGE_SIZE;
3206 pmap_pvh_free(&m->md, pmap, va);
3207 } while (va < va_last);
3211 * First find and then destroy the pv entry for the specified pmap and virtual
3212 * address. This operation can be performed on pv lists for either 4KB or 2MB
3216 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3220 pv = pmap_pvh_remove(pvh, pmap, va);
3221 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3222 free_pv_entry(pmap, pv);
3226 * Conditionally create the PV entry for a 4KB page mapping if the required
3227 * memory can be allocated without resorting to reclamation.
3230 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3231 struct rwlock **lockp)
3235 rw_assert(&pvh_global_lock, RA_LOCKED);
3236 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3237 /* Pass NULL instead of the lock pointer to disable reclamation. */
3238 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3240 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3241 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3249 * Conditionally create the PV entry for a 2MB page mapping if the required
3250 * memory can be allocated without resorting to reclamation.
3253 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3254 struct rwlock **lockp)
3256 struct md_page *pvh;
3259 rw_assert(&pvh_global_lock, RA_LOCKED);
3260 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3261 /* Pass NULL instead of the lock pointer to disable reclamation. */
3262 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3264 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3265 pvh = pa_to_pvh(pa);
3266 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3274 * Fills a page table page with mappings to consecutive physical pages.
3277 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3281 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3283 newpte += PAGE_SIZE;
3288 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3289 * mapping is invalidated.
3292 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3294 struct rwlock *lock;
3298 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3305 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3306 struct rwlock **lockp)
3308 pd_entry_t newpde, oldpde;
3309 pt_entry_t *firstpte, newpte;
3310 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3313 struct spglist free;
3316 PG_G = pmap_global_bit(pmap);
3317 PG_A = pmap_accessed_bit(pmap);
3318 PG_M = pmap_modified_bit(pmap);
3319 PG_RW = pmap_rw_bit(pmap);
3320 PG_V = pmap_valid_bit(pmap);
3321 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3323 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3325 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3326 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3327 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
3329 pmap_remove_pt_page(pmap, mpte);
3331 KASSERT((oldpde & PG_W) == 0,
3332 ("pmap_demote_pde: page table page for a wired mapping"
3336 * Invalidate the 2MB page mapping and return "failure" if the
3337 * mapping was never accessed or the allocation of the new
3338 * page table page fails. If the 2MB page mapping belongs to
3339 * the direct map region of the kernel's address space, then
3340 * the page allocation request specifies the highest possible
3341 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3342 * normal. Page table pages are preallocated for every other
3343 * part of the kernel address space, so the direct map region
3344 * is the only part of the kernel address space that must be
3347 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3348 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3349 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3350 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3352 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
3354 pmap_invalidate_page(pmap, trunc_2mpage(va));
3355 pmap_free_zero_pages(&free);
3356 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3357 " in pmap %p", va, pmap);
3360 if (va < VM_MAXUSER_ADDRESS)
3361 pmap_resident_count_inc(pmap, 1);
3363 mptepa = VM_PAGE_TO_PHYS(mpte);
3364 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3365 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3366 KASSERT((oldpde & PG_A) != 0,
3367 ("pmap_demote_pde: oldpde is missing PG_A"));
3368 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3369 ("pmap_demote_pde: oldpde is missing PG_M"));
3370 newpte = oldpde & ~PG_PS;
3371 newpte = pmap_swap_pat(pmap, newpte);
3374 * If the page table page is new, initialize it.
3376 if (mpte->wire_count == 1) {
3377 mpte->wire_count = NPTEPG;
3378 pmap_fill_ptp(firstpte, newpte);
3380 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3381 ("pmap_demote_pde: firstpte and newpte map different physical"
3385 * If the mapping has changed attributes, update the page table
3388 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3389 pmap_fill_ptp(firstpte, newpte);
3392 * The spare PV entries must be reserved prior to demoting the
3393 * mapping, that is, prior to changing the PDE. Otherwise, the state
3394 * of the PDE and the PV lists will be inconsistent, which can result
3395 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3396 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3397 * PV entry for the 2MB page mapping that is being demoted.
3399 if ((oldpde & PG_MANAGED) != 0)
3400 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3403 * Demote the mapping. This pmap is locked. The old PDE has
3404 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3405 * set. Thus, there is no danger of a race with another
3406 * processor changing the setting of PG_A and/or PG_M between
3407 * the read above and the store below.
3409 if (workaround_erratum383)
3410 pmap_update_pde(pmap, va, pde, newpde);
3412 pde_store(pde, newpde);
3415 * Invalidate a stale recursive mapping of the page table page.
3417 if (va >= VM_MAXUSER_ADDRESS)
3418 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3421 * Demote the PV entry.
3423 if ((oldpde & PG_MANAGED) != 0)
3424 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3426 atomic_add_long(&pmap_pde_demotions, 1);
3427 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3428 " in pmap %p", va, pmap);
3433 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3436 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3442 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3443 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3444 mpte = pmap_lookup_pt_page(pmap, va);
3446 panic("pmap_remove_kernel_pde: Missing pt page.");
3448 pmap_remove_pt_page(pmap, mpte);
3449 mptepa = VM_PAGE_TO_PHYS(mpte);
3450 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3453 * Initialize the page table page.
3455 pagezero((void *)PHYS_TO_DMAP(mptepa));
3458 * Demote the mapping.
3460 if (workaround_erratum383)
3461 pmap_update_pde(pmap, va, pde, newpde);
3463 pde_store(pde, newpde);
3466 * Invalidate a stale recursive mapping of the page table page.
3468 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3472 * pmap_remove_pde: do the things to unmap a superpage in a process
3475 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3476 struct spglist *free, struct rwlock **lockp)
3478 struct md_page *pvh;
3480 vm_offset_t eva, va;
3482 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3484 PG_G = pmap_global_bit(pmap);
3485 PG_A = pmap_accessed_bit(pmap);
3486 PG_M = pmap_modified_bit(pmap);
3487 PG_RW = pmap_rw_bit(pmap);
3489 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3490 KASSERT((sva & PDRMASK) == 0,
3491 ("pmap_remove_pde: sva is not 2mpage aligned"));
3492 oldpde = pte_load_clear(pdq);
3494 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3497 * Machines that don't support invlpg, also don't support
3501 pmap_invalidate_page(kernel_pmap, sva);
3502 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3503 if (oldpde & PG_MANAGED) {
3504 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3505 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3506 pmap_pvh_free(pvh, pmap, sva);
3508 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3509 va < eva; va += PAGE_SIZE, m++) {
3510 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3513 vm_page_aflag_set(m, PGA_REFERENCED);
3514 if (TAILQ_EMPTY(&m->md.pv_list) &&
3515 TAILQ_EMPTY(&pvh->pv_list))
3516 vm_page_aflag_clear(m, PGA_WRITEABLE);
3519 if (pmap == kernel_pmap) {
3520 pmap_remove_kernel_pde(pmap, pdq, sva);
3522 mpte = pmap_lookup_pt_page(pmap, sva);
3524 pmap_remove_pt_page(pmap, mpte);
3525 pmap_resident_count_dec(pmap, 1);
3526 KASSERT(mpte->wire_count == NPTEPG,
3527 ("pmap_remove_pde: pte page wire count error"));
3528 mpte->wire_count = 0;
3529 pmap_add_delayed_free_list(mpte, free, FALSE);
3530 atomic_subtract_int(&cnt.v_wire_count, 1);
3533 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3537 * pmap_remove_pte: do the things to unmap a page in a process
3540 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3541 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3543 struct md_page *pvh;
3544 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3547 PG_A = pmap_accessed_bit(pmap);
3548 PG_M = pmap_modified_bit(pmap);
3549 PG_RW = pmap_rw_bit(pmap);
3551 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3552 oldpte = pte_load_clear(ptq);
3554 pmap->pm_stats.wired_count -= 1;
3555 pmap_resident_count_dec(pmap, 1);
3556 if (oldpte & PG_MANAGED) {
3557 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3558 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3561 vm_page_aflag_set(m, PGA_REFERENCED);
3562 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3563 pmap_pvh_free(&m->md, pmap, va);
3564 if (TAILQ_EMPTY(&m->md.pv_list) &&
3565 (m->flags & PG_FICTITIOUS) == 0) {
3566 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3567 if (TAILQ_EMPTY(&pvh->pv_list))
3568 vm_page_aflag_clear(m, PGA_WRITEABLE);
3571 return (pmap_unuse_pt(pmap, va, ptepde, free));
3575 * Remove a single page from a process address space
3578 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3579 struct spglist *free)
3581 struct rwlock *lock;
3582 pt_entry_t *pte, PG_V;
3584 PG_V = pmap_valid_bit(pmap);
3585 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3586 if ((*pde & PG_V) == 0)
3588 pte = pmap_pde_to_pte(pde, va);
3589 if ((*pte & PG_V) == 0)
3592 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3595 pmap_invalidate_page(pmap, va);
3599 * Remove the given range of addresses from the specified map.
3601 * It is assumed that the start and end are properly
3602 * rounded to the page size.
3605 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3607 struct rwlock *lock;
3608 vm_offset_t va, va_next;
3609 pml4_entry_t *pml4e;
3611 pd_entry_t ptpaddr, *pde;
3612 pt_entry_t *pte, PG_G, PG_V;
3613 struct spglist free;
3616 PG_G = pmap_global_bit(pmap);
3617 PG_V = pmap_valid_bit(pmap);
3620 * Perform an unsynchronized read. This is, however, safe.
3622 if (pmap->pm_stats.resident_count == 0)
3628 rw_rlock(&pvh_global_lock);
3632 * special handling of removing one page. a very
3633 * common operation and easy to short circuit some
3636 if (sva + PAGE_SIZE == eva) {
3637 pde = pmap_pde(pmap, sva);
3638 if (pde && (*pde & PG_PS) == 0) {
3639 pmap_remove_page(pmap, sva, pde, &free);
3645 for (; sva < eva; sva = va_next) {
3647 if (pmap->pm_stats.resident_count == 0)
3650 pml4e = pmap_pml4e(pmap, sva);
3651 if ((*pml4e & PG_V) == 0) {
3652 va_next = (sva + NBPML4) & ~PML4MASK;
3658 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3659 if ((*pdpe & PG_V) == 0) {
3660 va_next = (sva + NBPDP) & ~PDPMASK;
3667 * Calculate index for next page table.
3669 va_next = (sva + NBPDR) & ~PDRMASK;
3673 pde = pmap_pdpe_to_pde(pdpe, sva);
3677 * Weed out invalid mappings.
3683 * Check for large page.
3685 if ((ptpaddr & PG_PS) != 0) {
3687 * Are we removing the entire large page? If not,
3688 * demote the mapping and fall through.
3690 if (sva + NBPDR == va_next && eva >= va_next) {
3692 * The TLB entry for a PG_G mapping is
3693 * invalidated by pmap_remove_pde().
3695 if ((ptpaddr & PG_G) == 0)
3697 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3699 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3701 /* The large page mapping was destroyed. */
3708 * Limit our scan to either the end of the va represented
3709 * by the current page table page, or to the end of the
3710 * range being removed.
3716 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3719 if (va != va_next) {
3720 pmap_invalidate_range(pmap, va, sva);
3725 if ((*pte & PG_G) == 0)
3727 else if (va == va_next)
3729 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3736 pmap_invalidate_range(pmap, va, sva);
3742 pmap_invalidate_all(pmap);
3743 rw_runlock(&pvh_global_lock);
3745 pmap_free_zero_pages(&free);
3749 * Routine: pmap_remove_all
3751 * Removes this physical page from
3752 * all physical maps in which it resides.
3753 * Reflects back modify bits to the pager.
3756 * Original versions of this routine were very
3757 * inefficient because they iteratively called
3758 * pmap_remove (slow...)
3762 pmap_remove_all(vm_page_t m)
3764 struct md_page *pvh;
3767 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3770 struct spglist free;
3772 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3773 ("pmap_remove_all: page %p is not managed", m));
3775 rw_wlock(&pvh_global_lock);
3776 if ((m->flags & PG_FICTITIOUS) != 0)
3777 goto small_mappings;
3778 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3779 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3783 pde = pmap_pde(pmap, va);
3784 (void)pmap_demote_pde(pmap, pde, va);
3788 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3791 PG_A = pmap_accessed_bit(pmap);
3792 PG_M = pmap_modified_bit(pmap);
3793 PG_RW = pmap_rw_bit(pmap);
3794 pmap_resident_count_dec(pmap, 1);
3795 pde = pmap_pde(pmap, pv->pv_va);
3796 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3797 " a 2mpage in page %p's pv list", m));
3798 pte = pmap_pde_to_pte(pde, pv->pv_va);
3799 tpte = pte_load_clear(pte);
3801 pmap->pm_stats.wired_count--;
3803 vm_page_aflag_set(m, PGA_REFERENCED);
3806 * Update the vm_page_t clean and reference bits.
3808 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3810 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3811 pmap_invalidate_page(pmap, pv->pv_va);
3812 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3814 free_pv_entry(pmap, pv);
3817 vm_page_aflag_clear(m, PGA_WRITEABLE);
3818 rw_wunlock(&pvh_global_lock);
3819 pmap_free_zero_pages(&free);
3823 * pmap_protect_pde: do the things to protect a 2mpage in a process
3826 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3828 pd_entry_t newpde, oldpde;
3829 vm_offset_t eva, va;
3831 boolean_t anychanged;
3832 pt_entry_t PG_G, PG_M, PG_RW;
3834 PG_G = pmap_global_bit(pmap);
3835 PG_M = pmap_modified_bit(pmap);
3836 PG_RW = pmap_rw_bit(pmap);
3838 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3839 KASSERT((sva & PDRMASK) == 0,
3840 ("pmap_protect_pde: sva is not 2mpage aligned"));
3843 oldpde = newpde = *pde;
3844 if (oldpde & PG_MANAGED) {
3846 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3847 va < eva; va += PAGE_SIZE, m++)
3848 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3851 if ((prot & VM_PROT_WRITE) == 0)
3852 newpde &= ~(PG_RW | PG_M);
3853 if ((prot & VM_PROT_EXECUTE) == 0)
3855 if (newpde != oldpde) {
3856 if (!atomic_cmpset_long(pde, oldpde, newpde))
3859 pmap_invalidate_page(pmap, sva);
3863 return (anychanged);
3867 * Set the physical protection on the
3868 * specified range of this map as requested.
3871 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3873 vm_offset_t va_next;
3874 pml4_entry_t *pml4e;
3876 pd_entry_t ptpaddr, *pde;
3877 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
3878 boolean_t anychanged, pv_lists_locked;
3880 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3881 if (prot == VM_PROT_NONE) {
3882 pmap_remove(pmap, sva, eva);
3886 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3887 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3890 PG_G = pmap_global_bit(pmap);
3891 PG_M = pmap_modified_bit(pmap);
3892 PG_V = pmap_valid_bit(pmap);
3893 PG_RW = pmap_rw_bit(pmap);
3894 pv_lists_locked = FALSE;
3899 for (; sva < eva; sva = va_next) {
3901 pml4e = pmap_pml4e(pmap, sva);
3902 if ((*pml4e & PG_V) == 0) {
3903 va_next = (sva + NBPML4) & ~PML4MASK;
3909 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3910 if ((*pdpe & PG_V) == 0) {
3911 va_next = (sva + NBPDP) & ~PDPMASK;
3917 va_next = (sva + NBPDR) & ~PDRMASK;
3921 pde = pmap_pdpe_to_pde(pdpe, sva);
3925 * Weed out invalid mappings.
3931 * Check for large page.
3933 if ((ptpaddr & PG_PS) != 0) {
3935 * Are we protecting the entire large page? If not,
3936 * demote the mapping and fall through.
3938 if (sva + NBPDR == va_next && eva >= va_next) {
3940 * The TLB entry for a PG_G mapping is
3941 * invalidated by pmap_protect_pde().
3943 if (pmap_protect_pde(pmap, pde, sva, prot))
3947 if (!pv_lists_locked) {
3948 pv_lists_locked = TRUE;
3949 if (!rw_try_rlock(&pvh_global_lock)) {
3951 pmap_invalidate_all(
3954 rw_rlock(&pvh_global_lock);
3958 if (!pmap_demote_pde(pmap, pde, sva)) {
3960 * The large page mapping was
3971 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3973 pt_entry_t obits, pbits;
3977 obits = pbits = *pte;
3978 if ((pbits & PG_V) == 0)
3981 if ((prot & VM_PROT_WRITE) == 0) {
3982 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3983 (PG_MANAGED | PG_M | PG_RW)) {
3984 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3987 pbits &= ~(PG_RW | PG_M);
3989 if ((prot & VM_PROT_EXECUTE) == 0)
3992 if (pbits != obits) {
3993 if (!atomic_cmpset_long(pte, obits, pbits))
3996 pmap_invalidate_page(pmap, sva);
4003 pmap_invalidate_all(pmap);
4004 if (pv_lists_locked)
4005 rw_runlock(&pvh_global_lock);
4010 * Tries to promote the 512, contiguous 4KB page mappings that are within a
4011 * single page table page (PTP) to a single 2MB page mapping. For promotion
4012 * to occur, two conditions must be met: (1) the 4KB page mappings must map
4013 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
4014 * identical characteristics.
4017 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4018 struct rwlock **lockp)
4021 pt_entry_t *firstpte, oldpte, pa, *pte;
4022 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
4023 vm_offset_t oldpteva;
4027 PG_A = pmap_accessed_bit(pmap);
4028 PG_G = pmap_global_bit(pmap);
4029 PG_M = pmap_modified_bit(pmap);
4030 PG_V = pmap_valid_bit(pmap);
4031 PG_RW = pmap_rw_bit(pmap);
4032 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4034 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4037 * Examine the first PTE in the specified PTP. Abort if this PTE is
4038 * either invalid, unused, or does not map the first 4KB physical page
4039 * within a 2MB page.
4041 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4044 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4045 atomic_add_long(&pmap_pde_p_failures, 1);
4046 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4047 " in pmap %p", va, pmap);
4050 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4052 * When PG_M is already clear, PG_RW can be cleared without
4053 * a TLB invalidation.
4055 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4061 * Examine each of the other PTEs in the specified PTP. Abort if this
4062 * PTE maps an unexpected 4KB physical page or does not have identical
4063 * characteristics to the first PTE.
4065 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4066 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4069 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4070 atomic_add_long(&pmap_pde_p_failures, 1);
4071 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4072 " in pmap %p", va, pmap);
4075 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4077 * When PG_M is already clear, PG_RW can be cleared
4078 * without a TLB invalidation.
4080 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4083 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
4085 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4086 " in pmap %p", oldpteva, pmap);
4088 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4089 atomic_add_long(&pmap_pde_p_failures, 1);
4090 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4091 " in pmap %p", va, pmap);
4098 * Save the page table page in its current state until the PDE
4099 * mapping the superpage is demoted by pmap_demote_pde() or
4100 * destroyed by pmap_remove_pde().
4102 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4103 KASSERT(mpte >= vm_page_array &&
4104 mpte < &vm_page_array[vm_page_array_size],
4105 ("pmap_promote_pde: page table page is out of range"));
4106 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4107 ("pmap_promote_pde: page table page's pindex is wrong"));
4108 if (pmap_insert_pt_page(pmap, mpte)) {
4109 atomic_add_long(&pmap_pde_p_failures, 1);
4111 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4117 * Promote the pv entries.
4119 if ((newpde & PG_MANAGED) != 0)
4120 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4123 * Propagate the PAT index to its proper position.
4125 newpde = pmap_swap_pat(pmap, newpde);
4128 * Map the superpage.
4130 if (workaround_erratum383)
4131 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4133 pde_store(pde, PG_PS | newpde);
4135 atomic_add_long(&pmap_pde_promotions, 1);
4136 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4137 " in pmap %p", va, pmap);
4141 * Insert the given physical page (p) at
4142 * the specified virtual address (v) in the
4143 * target physical map with the protection requested.
4145 * If specified, the page will be wired down, meaning
4146 * that the related pte can not be reclaimed.
4148 * NB: This is the only routine which MAY NOT lazy-evaluate
4149 * or lose information. That is, this routine must actually
4150 * insert this page into the given map NOW.
4153 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4154 u_int flags, int8_t psind __unused)
4156 struct rwlock *lock;
4158 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4159 pt_entry_t newpte, origpte;
4165 PG_A = pmap_accessed_bit(pmap);
4166 PG_G = pmap_global_bit(pmap);
4167 PG_M = pmap_modified_bit(pmap);
4168 PG_V = pmap_valid_bit(pmap);
4169 PG_RW = pmap_rw_bit(pmap);
4171 va = trunc_page(va);
4172 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4173 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4174 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4176 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4177 va >= kmi.clean_eva,
4178 ("pmap_enter: managed mapping within the clean submap"));
4179 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4180 VM_OBJECT_ASSERT_LOCKED(m->object);
4181 pa = VM_PAGE_TO_PHYS(m);
4182 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4183 if ((flags & VM_PROT_WRITE) != 0)
4185 if ((prot & VM_PROT_WRITE) != 0)
4187 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4188 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4189 if ((prot & VM_PROT_EXECUTE) == 0)
4191 if ((flags & PMAP_ENTER_WIRED) != 0)
4193 if (va < VM_MAXUSER_ADDRESS)
4195 if (pmap == kernel_pmap)
4197 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4200 * Set modified bit gratuitously for writeable mappings if
4201 * the page is unmanaged. We do not want to take a fault
4202 * to do the dirty bit accounting for these mappings.
4204 if ((m->oflags & VPO_UNMANAGED) != 0) {
4205 if ((newpte & PG_RW) != 0)
4212 rw_rlock(&pvh_global_lock);
4216 * In the case that a page table page is not
4217 * resident, we are creating it here.
4220 pde = pmap_pde(pmap, va);
4221 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4222 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4223 pte = pmap_pde_to_pte(pde, va);
4224 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4225 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4228 } else if (va < VM_MAXUSER_ADDRESS) {
4230 * Here if the pte page isn't mapped, or if it has been
4233 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4234 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4235 nosleep ? NULL : &lock);
4236 if (mpte == NULL && nosleep) {
4239 rw_runlock(&pvh_global_lock);
4241 return (KERN_RESOURCE_SHORTAGE);
4245 panic("pmap_enter: invalid page directory va=%#lx", va);
4250 * Is the specified virtual address already mapped?
4252 if ((origpte & PG_V) != 0) {
4254 * Wiring change, just update stats. We don't worry about
4255 * wiring PT pages as they remain resident as long as there
4256 * are valid mappings in them. Hence, if a user page is wired,
4257 * the PT page will be also.
4259 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4260 pmap->pm_stats.wired_count++;
4261 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4262 pmap->pm_stats.wired_count--;
4265 * Remove the extra PT page reference.
4269 KASSERT(mpte->wire_count > 0,
4270 ("pmap_enter: missing reference to page table page,"
4275 * Has the physical page changed?
4277 opa = origpte & PG_FRAME;
4280 * No, might be a protection or wiring change.
4282 if ((origpte & PG_MANAGED) != 0) {
4283 newpte |= PG_MANAGED;
4284 if ((newpte & PG_RW) != 0)
4285 vm_page_aflag_set(m, PGA_WRITEABLE);
4287 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4293 * Increment the counters.
4295 if ((newpte & PG_W) != 0)
4296 pmap->pm_stats.wired_count++;
4297 pmap_resident_count_inc(pmap, 1);
4301 * Enter on the PV list if part of our managed memory.
4303 if ((m->oflags & VPO_UNMANAGED) == 0) {
4304 newpte |= PG_MANAGED;
4305 pv = get_pv_entry(pmap, &lock);
4307 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4308 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4310 if ((newpte & PG_RW) != 0)
4311 vm_page_aflag_set(m, PGA_WRITEABLE);
4317 if ((origpte & PG_V) != 0) {
4319 origpte = pte_load_store(pte, newpte);
4320 opa = origpte & PG_FRAME;
4322 if ((origpte & PG_MANAGED) != 0) {
4323 om = PHYS_TO_VM_PAGE(opa);
4324 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4327 if ((origpte & PG_A) != 0)
4328 vm_page_aflag_set(om, PGA_REFERENCED);
4329 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4330 pmap_pvh_free(&om->md, pmap, va);
4331 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4332 TAILQ_EMPTY(&om->md.pv_list) &&
4333 ((om->flags & PG_FICTITIOUS) != 0 ||
4334 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4335 vm_page_aflag_clear(om, PGA_WRITEABLE);
4337 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4338 PG_RW)) == (PG_M | PG_RW)) {
4339 if ((origpte & PG_MANAGED) != 0)
4343 * Although the PTE may still have PG_RW set, TLB
4344 * invalidation may nonetheless be required because
4345 * the PTE no longer has PG_M set.
4347 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4349 * This PTE change does not require TLB invalidation.
4353 if ((origpte & PG_A) != 0)
4354 pmap_invalidate_page(pmap, va);
4356 pte_store(pte, newpte);
4361 * If both the page table page and the reservation are fully
4362 * populated, then attempt promotion.
4364 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4365 pmap_ps_enabled(pmap) &&
4366 (m->flags & PG_FICTITIOUS) == 0 &&
4367 vm_reserv_level_iffullpop(m) == 0)
4368 pmap_promote_pde(pmap, pde, va, &lock);
4372 rw_runlock(&pvh_global_lock);
4374 return (KERN_SUCCESS);
4378 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4379 * otherwise. Fails if (1) a page table page cannot be allocated without
4380 * blocking, (2) a mapping already exists at the specified virtual address, or
4381 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4384 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4385 struct rwlock **lockp)
4387 pd_entry_t *pde, newpde;
4390 struct spglist free;
4392 PG_V = pmap_valid_bit(pmap);
4393 rw_assert(&pvh_global_lock, RA_LOCKED);
4394 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4396 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4397 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4398 " in pmap %p", va, pmap);
4401 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4402 pde = &pde[pmap_pde_index(va)];
4403 if ((*pde & PG_V) != 0) {
4404 KASSERT(mpde->wire_count > 1,
4405 ("pmap_enter_pde: mpde's wire count is too low"));
4407 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4408 " in pmap %p", va, pmap);
4411 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4413 if ((m->oflags & VPO_UNMANAGED) == 0) {
4414 newpde |= PG_MANAGED;
4417 * Abort this mapping if its PV entry could not be created.
4419 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4422 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4423 pmap_invalidate_page(pmap, va);
4424 pmap_free_zero_pages(&free);
4426 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4427 " in pmap %p", va, pmap);
4431 if ((prot & VM_PROT_EXECUTE) == 0)
4433 if (va < VM_MAXUSER_ADDRESS)
4437 * Increment counters.
4439 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4442 * Map the superpage.
4444 pde_store(pde, newpde);
4446 atomic_add_long(&pmap_pde_mappings, 1);
4447 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4448 " in pmap %p", va, pmap);
4453 * Maps a sequence of resident pages belonging to the same object.
4454 * The sequence begins with the given page m_start. This page is
4455 * mapped at the given virtual address start. Each subsequent page is
4456 * mapped at a virtual address that is offset from start by the same
4457 * amount as the page is offset from m_start within the object. The
4458 * last page in the sequence is the page with the largest offset from
4459 * m_start that can be mapped at a virtual address less than the given
4460 * virtual address end. Not every virtual page between start and end
4461 * is mapped; only those for which a resident page exists with the
4462 * corresponding offset from m_start are mapped.
4465 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4466 vm_page_t m_start, vm_prot_t prot)
4468 struct rwlock *lock;
4471 vm_pindex_t diff, psize;
4473 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4475 psize = atop(end - start);
4479 rw_rlock(&pvh_global_lock);
4481 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4482 va = start + ptoa(diff);
4483 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4484 m->psind == 1 && pmap_ps_enabled(pmap) &&
4485 pmap_enter_pde(pmap, va, m, prot, &lock))
4486 m = &m[NBPDR / PAGE_SIZE - 1];
4488 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4490 m = TAILQ_NEXT(m, listq);
4494 rw_runlock(&pvh_global_lock);
4499 * this code makes some *MAJOR* assumptions:
4500 * 1. Current pmap & pmap exists.
4503 * 4. No page table pages.
4504 * but is *MUCH* faster than pmap_enter...
4508 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4510 struct rwlock *lock;
4513 rw_rlock(&pvh_global_lock);
4515 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4518 rw_runlock(&pvh_global_lock);
4523 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4524 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4526 struct spglist free;
4527 pt_entry_t *pte, PG_V;
4530 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4531 (m->oflags & VPO_UNMANAGED) != 0,
4532 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4533 PG_V = pmap_valid_bit(pmap);
4534 rw_assert(&pvh_global_lock, RA_LOCKED);
4535 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4538 * In the case that a page table page is not
4539 * resident, we are creating it here.
4541 if (va < VM_MAXUSER_ADDRESS) {
4542 vm_pindex_t ptepindex;
4546 * Calculate pagetable page index
4548 ptepindex = pmap_pde_pindex(va);
4549 if (mpte && (mpte->pindex == ptepindex)) {
4553 * Get the page directory entry
4555 ptepa = pmap_pde(pmap, va);
4558 * If the page table page is mapped, we just increment
4559 * the hold count, and activate it. Otherwise, we
4560 * attempt to allocate a page table page. If this
4561 * attempt fails, we don't retry. Instead, we give up.
4563 if (ptepa && (*ptepa & PG_V) != 0) {
4566 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4570 * Pass NULL instead of the PV list lock
4571 * pointer, because we don't intend to sleep.
4573 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4578 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4579 pte = &pte[pmap_pte_index(va)];
4593 * Enter on the PV list if part of our managed memory.
4595 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4596 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4599 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4600 pmap_invalidate_page(pmap, va);
4601 pmap_free_zero_pages(&free);
4609 * Increment counters
4611 pmap_resident_count_inc(pmap, 1);
4613 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4614 if ((prot & VM_PROT_EXECUTE) == 0)
4618 * Now validate mapping with RO protection
4620 if ((m->oflags & VPO_UNMANAGED) != 0)
4621 pte_store(pte, pa | PG_V | PG_U);
4623 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4628 * Make a temporary mapping for a physical address. This is only intended
4629 * to be used for panic dumps.
4632 pmap_kenter_temporary(vm_paddr_t pa, int i)
4636 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4637 pmap_kenter(va, pa);
4639 return ((void *)crashdumpmap);
4643 * This code maps large physical mmap regions into the
4644 * processor address space. Note that some shortcuts
4645 * are taken, but the code works.
4648 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4649 vm_pindex_t pindex, vm_size_t size)
4652 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4653 vm_paddr_t pa, ptepa;
4657 PG_A = pmap_accessed_bit(pmap);
4658 PG_M = pmap_modified_bit(pmap);
4659 PG_V = pmap_valid_bit(pmap);
4660 PG_RW = pmap_rw_bit(pmap);
4662 VM_OBJECT_ASSERT_WLOCKED(object);
4663 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4664 ("pmap_object_init_pt: non-device object"));
4665 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4666 if (!pmap_ps_enabled(pmap))
4668 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4670 p = vm_page_lookup(object, pindex);
4671 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4672 ("pmap_object_init_pt: invalid page %p", p));
4673 pat_mode = p->md.pat_mode;
4676 * Abort the mapping if the first page is not physically
4677 * aligned to a 2MB page boundary.
4679 ptepa = VM_PAGE_TO_PHYS(p);
4680 if (ptepa & (NBPDR - 1))
4684 * Skip the first page. Abort the mapping if the rest of
4685 * the pages are not physically contiguous or have differing
4686 * memory attributes.
4688 p = TAILQ_NEXT(p, listq);
4689 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4691 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4692 ("pmap_object_init_pt: invalid page %p", p));
4693 if (pa != VM_PAGE_TO_PHYS(p) ||
4694 pat_mode != p->md.pat_mode)
4696 p = TAILQ_NEXT(p, listq);
4700 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4701 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4702 * will not affect the termination of this loop.
4705 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4706 pa < ptepa + size; pa += NBPDR) {
4707 pdpg = pmap_allocpde(pmap, addr, NULL);
4710 * The creation of mappings below is only an
4711 * optimization. If a page directory page
4712 * cannot be allocated without blocking,
4713 * continue on to the next mapping rather than
4719 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4720 pde = &pde[pmap_pde_index(addr)];
4721 if ((*pde & PG_V) == 0) {
4722 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4723 PG_U | PG_RW | PG_V);
4724 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4725 atomic_add_long(&pmap_pde_mappings, 1);
4727 /* Continue on if the PDE is already valid. */
4729 KASSERT(pdpg->wire_count > 0,
4730 ("pmap_object_init_pt: missing reference "
4731 "to page directory page, va: 0x%lx", addr));
4740 * Clear the wired attribute from the mappings for the specified range of
4741 * addresses in the given pmap. Every valid mapping within that range
4742 * must have the wired attribute set. In contrast, invalid mappings
4743 * cannot have the wired attribute set, so they are ignored.
4745 * The wired attribute of the page table entry is not a hardware feature,
4746 * so there is no need to invalidate any TLB entries.
4749 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4751 vm_offset_t va_next;
4752 pml4_entry_t *pml4e;
4755 pt_entry_t *pte, PG_V;
4756 boolean_t pv_lists_locked;
4758 PG_V = pmap_valid_bit(pmap);
4759 pv_lists_locked = FALSE;
4762 for (; sva < eva; sva = va_next) {
4763 pml4e = pmap_pml4e(pmap, sva);
4764 if ((*pml4e & PG_V) == 0) {
4765 va_next = (sva + NBPML4) & ~PML4MASK;
4770 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4771 if ((*pdpe & PG_V) == 0) {
4772 va_next = (sva + NBPDP) & ~PDPMASK;
4777 va_next = (sva + NBPDR) & ~PDRMASK;
4780 pde = pmap_pdpe_to_pde(pdpe, sva);
4781 if ((*pde & PG_V) == 0)
4783 if ((*pde & PG_PS) != 0) {
4784 if ((*pde & PG_W) == 0)
4785 panic("pmap_unwire: pde %#jx is missing PG_W",
4789 * Are we unwiring the entire large page? If not,
4790 * demote the mapping and fall through.
4792 if (sva + NBPDR == va_next && eva >= va_next) {
4793 atomic_clear_long(pde, PG_W);
4794 pmap->pm_stats.wired_count -= NBPDR /
4798 if (!pv_lists_locked) {
4799 pv_lists_locked = TRUE;
4800 if (!rw_try_rlock(&pvh_global_lock)) {
4802 rw_rlock(&pvh_global_lock);
4807 if (!pmap_demote_pde(pmap, pde, sva))
4808 panic("pmap_unwire: demotion failed");
4813 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4815 if ((*pte & PG_V) == 0)
4817 if ((*pte & PG_W) == 0)
4818 panic("pmap_unwire: pte %#jx is missing PG_W",
4822 * PG_W must be cleared atomically. Although the pmap
4823 * lock synchronizes access to PG_W, another processor
4824 * could be setting PG_M and/or PG_A concurrently.
4826 atomic_clear_long(pte, PG_W);
4827 pmap->pm_stats.wired_count--;
4830 if (pv_lists_locked)
4831 rw_runlock(&pvh_global_lock);
4836 * Copy the range specified by src_addr/len
4837 * from the source map to the range dst_addr/len
4838 * in the destination map.
4840 * This routine is only advisory and need not do anything.
4844 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4845 vm_offset_t src_addr)
4847 struct rwlock *lock;
4848 struct spglist free;
4850 vm_offset_t end_addr = src_addr + len;
4851 vm_offset_t va_next;
4852 pt_entry_t PG_A, PG_M, PG_V;
4854 if (dst_addr != src_addr)
4857 if (dst_pmap->pm_type != src_pmap->pm_type)
4861 * EPT page table entries that require emulation of A/D bits are
4862 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
4863 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
4864 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
4865 * implementations flag an EPT misconfiguration for exec-only
4866 * mappings we skip this function entirely for emulated pmaps.
4868 if (pmap_emulate_ad_bits(dst_pmap))
4872 rw_rlock(&pvh_global_lock);
4873 if (dst_pmap < src_pmap) {
4874 PMAP_LOCK(dst_pmap);
4875 PMAP_LOCK(src_pmap);
4877 PMAP_LOCK(src_pmap);
4878 PMAP_LOCK(dst_pmap);
4881 PG_A = pmap_accessed_bit(dst_pmap);
4882 PG_M = pmap_modified_bit(dst_pmap);
4883 PG_V = pmap_valid_bit(dst_pmap);
4885 for (addr = src_addr; addr < end_addr; addr = va_next) {
4886 pt_entry_t *src_pte, *dst_pte;
4887 vm_page_t dstmpde, dstmpte, srcmpte;
4888 pml4_entry_t *pml4e;
4890 pd_entry_t srcptepaddr, *pde;
4892 KASSERT(addr < UPT_MIN_ADDRESS,
4893 ("pmap_copy: invalid to pmap_copy page tables"));
4895 pml4e = pmap_pml4e(src_pmap, addr);
4896 if ((*pml4e & PG_V) == 0) {
4897 va_next = (addr + NBPML4) & ~PML4MASK;
4903 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4904 if ((*pdpe & PG_V) == 0) {
4905 va_next = (addr + NBPDP) & ~PDPMASK;
4911 va_next = (addr + NBPDR) & ~PDRMASK;
4915 pde = pmap_pdpe_to_pde(pdpe, addr);
4917 if (srcptepaddr == 0)
4920 if (srcptepaddr & PG_PS) {
4921 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4923 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4924 if (dstmpde == NULL)
4926 pde = (pd_entry_t *)
4927 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4928 pde = &pde[pmap_pde_index(addr)];
4929 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4930 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4931 PG_PS_FRAME, &lock))) {
4932 *pde = srcptepaddr & ~PG_W;
4933 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4935 dstmpde->wire_count--;
4939 srcptepaddr &= PG_FRAME;
4940 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4941 KASSERT(srcmpte->wire_count > 0,
4942 ("pmap_copy: source page table page is unused"));
4944 if (va_next > end_addr)
4947 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4948 src_pte = &src_pte[pmap_pte_index(addr)];
4950 while (addr < va_next) {
4954 * we only virtual copy managed pages
4956 if ((ptetemp & PG_MANAGED) != 0) {
4957 if (dstmpte != NULL &&
4958 dstmpte->pindex == pmap_pde_pindex(addr))
4959 dstmpte->wire_count++;
4960 else if ((dstmpte = pmap_allocpte(dst_pmap,
4961 addr, NULL)) == NULL)
4963 dst_pte = (pt_entry_t *)
4964 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4965 dst_pte = &dst_pte[pmap_pte_index(addr)];
4966 if (*dst_pte == 0 &&
4967 pmap_try_insert_pv_entry(dst_pmap, addr,
4968 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4971 * Clear the wired, modified, and
4972 * accessed (referenced) bits
4975 *dst_pte = ptetemp & ~(PG_W | PG_M |
4977 pmap_resident_count_inc(dst_pmap, 1);
4980 if (pmap_unwire_ptp(dst_pmap, addr,
4982 pmap_invalidate_page(dst_pmap,
4984 pmap_free_zero_pages(&free);
4988 if (dstmpte->wire_count >= srcmpte->wire_count)
4998 rw_runlock(&pvh_global_lock);
4999 PMAP_UNLOCK(src_pmap);
5000 PMAP_UNLOCK(dst_pmap);
5004 * pmap_zero_page zeros the specified hardware page by mapping
5005 * the page into KVM and using bzero to clear its contents.
5008 pmap_zero_page(vm_page_t m)
5010 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5012 pagezero((void *)va);
5016 * pmap_zero_page_area zeros the specified hardware page by mapping
5017 * the page into KVM and using bzero to clear its contents.
5019 * off and size may not cover an area beyond a single hardware page.
5022 pmap_zero_page_area(vm_page_t m, int off, int size)
5024 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5026 if (off == 0 && size == PAGE_SIZE)
5027 pagezero((void *)va);
5029 bzero((char *)va + off, size);
5033 * pmap_zero_page_idle zeros the specified hardware page by mapping
5034 * the page into KVM and using bzero to clear its contents. This
5035 * is intended to be called from the vm_pagezero process only and
5039 pmap_zero_page_idle(vm_page_t m)
5041 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5043 pagezero((void *)va);
5047 * pmap_copy_page copies the specified (machine independent)
5048 * page by mapping the page into virtual memory and using
5049 * bcopy to copy the page, one machine dependent page at a
5053 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5055 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5056 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5058 pagecopy((void *)src, (void *)dst);
5061 int unmapped_buf_allowed = 1;
5064 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5065 vm_offset_t b_offset, int xfersize)
5069 vm_paddr_t p_a, p_b;
5071 vm_offset_t a_pg_offset, b_pg_offset;
5076 * NB: The sequence of updating a page table followed by accesses
5077 * to the corresponding pages used in the !DMAP case is subject to
5078 * the situation described in the "AMD64 Architecture Programmer's
5079 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
5080 * Coherency Considerations". Therefore, issuing the INVLPG right
5081 * after modifying the PTE bits is crucial.
5084 while (xfersize > 0) {
5085 a_pg_offset = a_offset & PAGE_MASK;
5086 m_a = ma[a_offset >> PAGE_SHIFT];
5087 p_a = m_a->phys_addr;
5088 b_pg_offset = b_offset & PAGE_MASK;
5089 m_b = mb[b_offset >> PAGE_SHIFT];
5090 p_b = m_b->phys_addr;
5091 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5092 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5093 if (__predict_false(p_a < DMAP_MIN_ADDRESS ||
5094 p_a > DMAP_MIN_ADDRESS + dmaplimit)) {
5095 mtx_lock(&cpage_lock);
5098 pte = vtopte(cpage_a);
5099 *pte = p_a | X86_PG_A | X86_PG_V |
5100 pmap_cache_bits(kernel_pmap, m_a->md.pat_mode, 0);
5102 a_cp = (char *)cpage_a + a_pg_offset;
5104 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
5106 if (__predict_false(p_b < DMAP_MIN_ADDRESS ||
5107 p_b > DMAP_MIN_ADDRESS + dmaplimit)) {
5109 mtx_lock(&cpage_lock);
5113 pte = vtopte(cpage_b);
5114 *pte = p_b | X86_PG_A | X86_PG_M | X86_PG_RW |
5115 X86_PG_V | pmap_cache_bits(kernel_pmap,
5116 m_b->md.pat_mode, 0);
5118 b_cp = (char *)cpage_b + b_pg_offset;
5120 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
5122 bcopy(a_cp, b_cp, cnt);
5123 if (__predict_false(pinned)) {
5125 mtx_unlock(&cpage_lock);
5135 * Returns true if the pmap's pv is one of the first
5136 * 16 pvs linked to from this page. This count may
5137 * be changed upwards or downwards in the future; it
5138 * is only necessary that true be returned for a small
5139 * subset of pmaps for proper page aging.
5142 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5144 struct md_page *pvh;
5145 struct rwlock *lock;
5150 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5151 ("pmap_page_exists_quick: page %p is not managed", m));
5153 rw_rlock(&pvh_global_lock);
5154 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5156 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5157 if (PV_PMAP(pv) == pmap) {
5165 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5166 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5167 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5168 if (PV_PMAP(pv) == pmap) {
5178 rw_runlock(&pvh_global_lock);
5183 * pmap_page_wired_mappings:
5185 * Return the number of managed mappings to the given physical page
5189 pmap_page_wired_mappings(vm_page_t m)
5191 struct rwlock *lock;
5192 struct md_page *pvh;
5196 int count, md_gen, pvh_gen;
5198 if ((m->oflags & VPO_UNMANAGED) != 0)
5200 rw_rlock(&pvh_global_lock);
5201 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5205 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5207 if (!PMAP_TRYLOCK(pmap)) {
5208 md_gen = m->md.pv_gen;
5212 if (md_gen != m->md.pv_gen) {
5217 pte = pmap_pte(pmap, pv->pv_va);
5218 if ((*pte & PG_W) != 0)
5222 if ((m->flags & PG_FICTITIOUS) == 0) {
5223 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5224 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5226 if (!PMAP_TRYLOCK(pmap)) {
5227 md_gen = m->md.pv_gen;
5228 pvh_gen = pvh->pv_gen;
5232 if (md_gen != m->md.pv_gen ||
5233 pvh_gen != pvh->pv_gen) {
5238 pte = pmap_pde(pmap, pv->pv_va);
5239 if ((*pte & PG_W) != 0)
5245 rw_runlock(&pvh_global_lock);
5250 * Returns TRUE if the given page is mapped individually or as part of
5251 * a 2mpage. Otherwise, returns FALSE.
5254 pmap_page_is_mapped(vm_page_t m)
5256 struct rwlock *lock;
5259 if ((m->oflags & VPO_UNMANAGED) != 0)
5261 rw_rlock(&pvh_global_lock);
5262 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5264 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5265 ((m->flags & PG_FICTITIOUS) == 0 &&
5266 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5268 rw_runlock(&pvh_global_lock);
5273 * Destroy all managed, non-wired mappings in the given user-space
5274 * pmap. This pmap cannot be active on any processor besides the
5277 * This function cannot be applied to the kernel pmap. Moreover, it
5278 * is not intended for general use. It is only to be used during
5279 * process termination. Consequently, it can be implemented in ways
5280 * that make it faster than pmap_remove(). First, it can more quickly
5281 * destroy mappings by iterating over the pmap's collection of PV
5282 * entries, rather than searching the page table. Second, it doesn't
5283 * have to test and clear the page table entries atomically, because
5284 * no processor is currently accessing the user address space. In
5285 * particular, a page table entry's dirty bit won't change state once
5286 * this function starts.
5289 pmap_remove_pages(pmap_t pmap)
5292 pt_entry_t *pte, tpte;
5293 pt_entry_t PG_M, PG_RW, PG_V;
5294 struct spglist free;
5295 vm_page_t m, mpte, mt;
5297 struct md_page *pvh;
5298 struct pv_chunk *pc, *npc;
5299 struct rwlock *lock;
5301 uint64_t inuse, bitmask;
5302 int allfree, field, freed, idx;
5303 boolean_t superpage;
5307 * Assert that the given pmap is only active on the current
5308 * CPU. Unfortunately, we cannot block another CPU from
5309 * activating the pmap while this function is executing.
5311 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5314 cpuset_t other_cpus;
5316 other_cpus = all_cpus;
5318 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5319 CPU_AND(&other_cpus, &pmap->pm_active);
5321 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5326 PG_M = pmap_modified_bit(pmap);
5327 PG_V = pmap_valid_bit(pmap);
5328 PG_RW = pmap_rw_bit(pmap);
5331 rw_rlock(&pvh_global_lock);
5333 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5336 for (field = 0; field < _NPCM; field++) {
5337 inuse = ~pc->pc_map[field] & pc_freemask[field];
5338 while (inuse != 0) {
5340 bitmask = 1UL << bit;
5341 idx = field * 64 + bit;
5342 pv = &pc->pc_pventry[idx];
5345 pte = pmap_pdpe(pmap, pv->pv_va);
5347 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5349 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5352 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5354 pte = &pte[pmap_pte_index(pv->pv_va)];
5358 * Keep track whether 'tpte' is a
5359 * superpage explicitly instead of
5360 * relying on PG_PS being set.
5362 * This is because PG_PS is numerically
5363 * identical to PG_PTE_PAT and thus a
5364 * regular page could be mistaken for
5370 if ((tpte & PG_V) == 0) {
5371 panic("bad pte va %lx pte %lx",
5376 * We cannot remove wired pages from a process' mapping at this time
5384 pa = tpte & PG_PS_FRAME;
5386 pa = tpte & PG_FRAME;
5388 m = PHYS_TO_VM_PAGE(pa);
5389 KASSERT(m->phys_addr == pa,
5390 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5391 m, (uintmax_t)m->phys_addr,
5394 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5395 m < &vm_page_array[vm_page_array_size],
5396 ("pmap_remove_pages: bad tpte %#jx",
5402 * Update the vm_page_t clean/reference bits.
5404 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5406 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5412 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5415 pc->pc_map[field] |= bitmask;
5417 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5418 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5419 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5421 if (TAILQ_EMPTY(&pvh->pv_list)) {
5422 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5423 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5424 TAILQ_EMPTY(&mt->md.pv_list))
5425 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5427 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
5429 pmap_remove_pt_page(pmap, mpte);
5430 pmap_resident_count_dec(pmap, 1);
5431 KASSERT(mpte->wire_count == NPTEPG,
5432 ("pmap_remove_pages: pte page wire count error"));
5433 mpte->wire_count = 0;
5434 pmap_add_delayed_free_list(mpte, &free, FALSE);
5435 atomic_subtract_int(&cnt.v_wire_count, 1);
5438 pmap_resident_count_dec(pmap, 1);
5439 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5441 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5442 TAILQ_EMPTY(&m->md.pv_list) &&
5443 (m->flags & PG_FICTITIOUS) == 0) {
5444 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5445 if (TAILQ_EMPTY(&pvh->pv_list))
5446 vm_page_aflag_clear(m, PGA_WRITEABLE);
5449 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5453 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5454 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5455 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5457 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5463 pmap_invalidate_all(pmap);
5464 rw_runlock(&pvh_global_lock);
5466 pmap_free_zero_pages(&free);
5470 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5472 struct rwlock *lock;
5474 struct md_page *pvh;
5475 pt_entry_t *pte, mask;
5476 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5478 int md_gen, pvh_gen;
5482 rw_rlock(&pvh_global_lock);
5483 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5486 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5488 if (!PMAP_TRYLOCK(pmap)) {
5489 md_gen = m->md.pv_gen;
5493 if (md_gen != m->md.pv_gen) {
5498 pte = pmap_pte(pmap, pv->pv_va);
5501 PG_M = pmap_modified_bit(pmap);
5502 PG_RW = pmap_rw_bit(pmap);
5503 mask |= PG_RW | PG_M;
5506 PG_A = pmap_accessed_bit(pmap);
5507 PG_V = pmap_valid_bit(pmap);
5508 mask |= PG_V | PG_A;
5510 rv = (*pte & mask) == mask;
5515 if ((m->flags & PG_FICTITIOUS) == 0) {
5516 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5517 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5519 if (!PMAP_TRYLOCK(pmap)) {
5520 md_gen = m->md.pv_gen;
5521 pvh_gen = pvh->pv_gen;
5525 if (md_gen != m->md.pv_gen ||
5526 pvh_gen != pvh->pv_gen) {
5531 pte = pmap_pde(pmap, pv->pv_va);
5534 PG_M = pmap_modified_bit(pmap);
5535 PG_RW = pmap_rw_bit(pmap);
5536 mask |= PG_RW | PG_M;
5539 PG_A = pmap_accessed_bit(pmap);
5540 PG_V = pmap_valid_bit(pmap);
5541 mask |= PG_V | PG_A;
5543 rv = (*pte & mask) == mask;
5551 rw_runlock(&pvh_global_lock);
5558 * Return whether or not the specified physical page was modified
5559 * in any physical maps.
5562 pmap_is_modified(vm_page_t m)
5565 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5566 ("pmap_is_modified: page %p is not managed", m));
5569 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5570 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5571 * is clear, no PTEs can have PG_M set.
5573 VM_OBJECT_ASSERT_WLOCKED(m->object);
5574 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5576 return (pmap_page_test_mappings(m, FALSE, TRUE));
5580 * pmap_is_prefaultable:
5582 * Return whether or not the specified virtual address is eligible
5586 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5589 pt_entry_t *pte, PG_V;
5592 PG_V = pmap_valid_bit(pmap);
5595 pde = pmap_pde(pmap, addr);
5596 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5597 pte = pmap_pde_to_pte(pde, addr);
5598 rv = (*pte & PG_V) == 0;
5605 * pmap_is_referenced:
5607 * Return whether or not the specified physical page was referenced
5608 * in any physical maps.
5611 pmap_is_referenced(vm_page_t m)
5614 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5615 ("pmap_is_referenced: page %p is not managed", m));
5616 return (pmap_page_test_mappings(m, TRUE, FALSE));
5620 * Clear the write and modified bits in each of the given page's mappings.
5623 pmap_remove_write(vm_page_t m)
5625 struct md_page *pvh;
5627 struct rwlock *lock;
5628 pv_entry_t next_pv, pv;
5630 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5632 int pvh_gen, md_gen;
5634 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5635 ("pmap_remove_write: page %p is not managed", m));
5638 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5639 * set by another thread while the object is locked. Thus,
5640 * if PGA_WRITEABLE is clear, no page table entries need updating.
5642 VM_OBJECT_ASSERT_WLOCKED(m->object);
5643 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5645 rw_rlock(&pvh_global_lock);
5646 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5647 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5650 if ((m->flags & PG_FICTITIOUS) != 0)
5651 goto small_mappings;
5652 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5654 if (!PMAP_TRYLOCK(pmap)) {
5655 pvh_gen = pvh->pv_gen;
5659 if (pvh_gen != pvh->pv_gen) {
5665 PG_RW = pmap_rw_bit(pmap);
5667 pde = pmap_pde(pmap, va);
5668 if ((*pde & PG_RW) != 0)
5669 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5670 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5671 ("inconsistent pv lock %p %p for page %p",
5672 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5676 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5678 if (!PMAP_TRYLOCK(pmap)) {
5679 pvh_gen = pvh->pv_gen;
5680 md_gen = m->md.pv_gen;
5684 if (pvh_gen != pvh->pv_gen ||
5685 md_gen != m->md.pv_gen) {
5691 PG_M = pmap_modified_bit(pmap);
5692 PG_RW = pmap_rw_bit(pmap);
5693 pde = pmap_pde(pmap, pv->pv_va);
5694 KASSERT((*pde & PG_PS) == 0,
5695 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5697 pte = pmap_pde_to_pte(pde, pv->pv_va);
5700 if (oldpte & PG_RW) {
5701 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5704 if ((oldpte & PG_M) != 0)
5706 pmap_invalidate_page(pmap, pv->pv_va);
5711 vm_page_aflag_clear(m, PGA_WRITEABLE);
5712 rw_runlock(&pvh_global_lock);
5715 static __inline boolean_t
5716 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5719 if (!pmap_emulate_ad_bits(pmap))
5722 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5725 * RWX = 010 or 110 will cause an unconditional EPT misconfiguration
5726 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5727 * if the EPT_PG_WRITE bit is set.
5729 if ((pte & EPT_PG_WRITE) != 0)
5733 * RWX = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5735 if ((pte & EPT_PG_EXECUTE) == 0 ||
5736 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5742 #define PMAP_TS_REFERENCED_MAX 5
5745 * pmap_ts_referenced:
5747 * Return a count of reference bits for a page, clearing those bits.
5748 * It is not necessary for every reference bit to be cleared, but it
5749 * is necessary that 0 only be returned when there are truly no
5750 * reference bits set.
5752 * XXX: The exact number of bits to check and clear is a matter that
5753 * should be tested and standardized at some point in the future for
5754 * optimal aging of shared pages.
5757 pmap_ts_referenced(vm_page_t m)
5759 struct md_page *pvh;
5762 struct rwlock *lock;
5763 pd_entry_t oldpde, *pde;
5764 pt_entry_t *pte, PG_A;
5767 int cleared, md_gen, not_cleared, pvh_gen;
5768 struct spglist free;
5771 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5772 ("pmap_ts_referenced: page %p is not managed", m));
5775 pa = VM_PAGE_TO_PHYS(m);
5776 lock = PHYS_TO_PV_LIST_LOCK(pa);
5777 pvh = pa_to_pvh(pa);
5778 rw_rlock(&pvh_global_lock);
5782 if ((m->flags & PG_FICTITIOUS) != 0 ||
5783 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5784 goto small_mappings;
5790 if (!PMAP_TRYLOCK(pmap)) {
5791 pvh_gen = pvh->pv_gen;
5795 if (pvh_gen != pvh->pv_gen) {
5800 PG_A = pmap_accessed_bit(pmap);
5802 pde = pmap_pde(pmap, pv->pv_va);
5804 if ((*pde & PG_A) != 0) {
5806 * Since this reference bit is shared by 512 4KB
5807 * pages, it should not be cleared every time it is
5808 * tested. Apply a simple "hash" function on the
5809 * physical page number, the virtual superpage number,
5810 * and the pmap address to select one 4KB page out of
5811 * the 512 on which testing the reference bit will
5812 * result in clearing that reference bit. This
5813 * function is designed to avoid the selection of the
5814 * same 4KB page for every 2MB page mapping.
5816 * On demotion, a mapping that hasn't been referenced
5817 * is simply destroyed. To avoid the possibility of a
5818 * subsequent page fault on a demoted wired mapping,
5819 * always leave its reference bit set. Moreover,
5820 * since the superpage is wired, the current state of
5821 * its reference bit won't affect page replacement.
5823 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5824 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5825 (*pde & PG_W) == 0) {
5826 if (safe_to_clear_referenced(pmap, oldpde)) {
5827 atomic_clear_long(pde, PG_A);
5828 pmap_invalidate_page(pmap, pv->pv_va);
5830 } else if (pmap_demote_pde_locked(pmap, pde,
5831 pv->pv_va, &lock)) {
5833 * Remove the mapping to a single page
5834 * so that a subsequent access may
5835 * repromote. Since the underlying
5836 * page table page is fully populated,
5837 * this removal never frees a page
5841 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5843 pte = pmap_pde_to_pte(pde, va);
5844 pmap_remove_pte(pmap, pte, va, *pde,
5846 pmap_invalidate_page(pmap, va);
5852 * The superpage mapping was removed
5853 * entirely and therefore 'pv' is no
5861 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5862 ("inconsistent pv lock %p %p for page %p",
5863 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5868 /* Rotate the PV list if it has more than one entry. */
5869 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5870 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5871 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5874 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5876 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5878 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5885 if (!PMAP_TRYLOCK(pmap)) {
5886 pvh_gen = pvh->pv_gen;
5887 md_gen = m->md.pv_gen;
5891 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5896 PG_A = pmap_accessed_bit(pmap);
5897 pde = pmap_pde(pmap, pv->pv_va);
5898 KASSERT((*pde & PG_PS) == 0,
5899 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5901 pte = pmap_pde_to_pte(pde, pv->pv_va);
5902 if ((*pte & PG_A) != 0) {
5903 if (safe_to_clear_referenced(pmap, *pte)) {
5904 atomic_clear_long(pte, PG_A);
5905 pmap_invalidate_page(pmap, pv->pv_va);
5907 } else if ((*pte & PG_W) == 0) {
5909 * Wired pages cannot be paged out so
5910 * doing accessed bit emulation for
5911 * them is wasted effort. We do the
5912 * hard work for unwired pages only.
5914 pmap_remove_pte(pmap, pte, pv->pv_va,
5915 *pde, &free, &lock);
5916 pmap_invalidate_page(pmap, pv->pv_va);
5921 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5922 ("inconsistent pv lock %p %p for page %p",
5923 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5928 /* Rotate the PV list if it has more than one entry. */
5929 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5930 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5931 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5934 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5935 not_cleared < PMAP_TS_REFERENCED_MAX);
5938 rw_runlock(&pvh_global_lock);
5939 pmap_free_zero_pages(&free);
5940 return (cleared + not_cleared);
5944 * Apply the given advice to the specified range of addresses within the
5945 * given pmap. Depending on the advice, clear the referenced and/or
5946 * modified flags in each mapping and set the mapped page's dirty field.
5949 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5951 struct rwlock *lock;
5952 pml4_entry_t *pml4e;
5954 pd_entry_t oldpde, *pde;
5955 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
5956 vm_offset_t va_next;
5958 boolean_t anychanged, pv_lists_locked;
5960 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5964 * A/D bit emulation requires an alternate code path when clearing
5965 * the modified and accessed bits below. Since this function is
5966 * advisory in nature we skip it entirely for pmaps that require
5967 * A/D bit emulation.
5969 if (pmap_emulate_ad_bits(pmap))
5972 PG_A = pmap_accessed_bit(pmap);
5973 PG_G = pmap_global_bit(pmap);
5974 PG_M = pmap_modified_bit(pmap);
5975 PG_V = pmap_valid_bit(pmap);
5976 PG_RW = pmap_rw_bit(pmap);
5978 pv_lists_locked = FALSE;
5982 for (; sva < eva; sva = va_next) {
5983 pml4e = pmap_pml4e(pmap, sva);
5984 if ((*pml4e & PG_V) == 0) {
5985 va_next = (sva + NBPML4) & ~PML4MASK;
5990 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5991 if ((*pdpe & PG_V) == 0) {
5992 va_next = (sva + NBPDP) & ~PDPMASK;
5997 va_next = (sva + NBPDR) & ~PDRMASK;
6000 pde = pmap_pdpe_to_pde(pdpe, sva);
6002 if ((oldpde & PG_V) == 0)
6004 else if ((oldpde & PG_PS) != 0) {
6005 if ((oldpde & PG_MANAGED) == 0)
6007 if (!pv_lists_locked) {
6008 pv_lists_locked = TRUE;
6009 if (!rw_try_rlock(&pvh_global_lock)) {
6011 pmap_invalidate_all(pmap);
6013 rw_rlock(&pvh_global_lock);
6018 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
6023 * The large page mapping was destroyed.
6029 * Unless the page mappings are wired, remove the
6030 * mapping to a single page so that a subsequent
6031 * access may repromote. Since the underlying page
6032 * table page is fully populated, this removal never
6033 * frees a page table page.
6035 if ((oldpde & PG_W) == 0) {
6036 pte = pmap_pde_to_pte(pde, sva);
6037 KASSERT((*pte & PG_V) != 0,
6038 ("pmap_advise: invalid PTE"));
6039 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6048 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6050 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
6053 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6054 if (advice == MADV_DONTNEED) {
6056 * Future calls to pmap_is_modified()
6057 * can be avoided by making the page
6060 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6063 atomic_clear_long(pte, PG_M | PG_A);
6064 } else if ((*pte & PG_A) != 0)
6065 atomic_clear_long(pte, PG_A);
6068 if ((*pte & PG_G) != 0)
6069 pmap_invalidate_page(pmap, sva);
6075 pmap_invalidate_all(pmap);
6076 if (pv_lists_locked)
6077 rw_runlock(&pvh_global_lock);
6082 * Clear the modify bits on the specified physical page.
6085 pmap_clear_modify(vm_page_t m)
6087 struct md_page *pvh;
6089 pv_entry_t next_pv, pv;
6090 pd_entry_t oldpde, *pde;
6091 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6092 struct rwlock *lock;
6094 int md_gen, pvh_gen;
6096 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6097 ("pmap_clear_modify: page %p is not managed", m));
6098 VM_OBJECT_ASSERT_WLOCKED(m->object);
6099 KASSERT(!vm_page_xbusied(m),
6100 ("pmap_clear_modify: page %p is exclusive busied", m));
6103 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6104 * If the object containing the page is locked and the page is not
6105 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6107 if ((m->aflags & PGA_WRITEABLE) == 0)
6109 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6110 rw_rlock(&pvh_global_lock);
6111 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6114 if ((m->flags & PG_FICTITIOUS) != 0)
6115 goto small_mappings;
6116 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6118 if (!PMAP_TRYLOCK(pmap)) {
6119 pvh_gen = pvh->pv_gen;
6123 if (pvh_gen != pvh->pv_gen) {
6128 PG_M = pmap_modified_bit(pmap);
6129 PG_V = pmap_valid_bit(pmap);
6130 PG_RW = pmap_rw_bit(pmap);
6132 pde = pmap_pde(pmap, va);
6134 if ((oldpde & PG_RW) != 0) {
6135 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6136 if ((oldpde & PG_W) == 0) {
6138 * Write protect the mapping to a
6139 * single page so that a subsequent
6140 * write access may repromote.
6142 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6144 pte = pmap_pde_to_pte(pde, va);
6146 if ((oldpte & PG_V) != 0) {
6147 while (!atomic_cmpset_long(pte,
6149 oldpte & ~(PG_M | PG_RW)))
6152 pmap_invalidate_page(pmap, va);
6160 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6162 if (!PMAP_TRYLOCK(pmap)) {
6163 md_gen = m->md.pv_gen;
6164 pvh_gen = pvh->pv_gen;
6168 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6173 PG_M = pmap_modified_bit(pmap);
6174 PG_RW = pmap_rw_bit(pmap);
6175 pde = pmap_pde(pmap, pv->pv_va);
6176 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6177 " a 2mpage in page %p's pv list", m));
6178 pte = pmap_pde_to_pte(pde, pv->pv_va);
6179 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6180 atomic_clear_long(pte, PG_M);
6181 pmap_invalidate_page(pmap, pv->pv_va);
6186 rw_runlock(&pvh_global_lock);
6190 * Miscellaneous support routines follow
6193 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6194 static __inline void
6195 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6200 * The cache mode bits are all in the low 32-bits of the
6201 * PTE, so we can just spin on updating the low 32-bits.
6204 opte = *(u_int *)pte;
6205 npte = opte & ~mask;
6207 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6210 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6211 static __inline void
6212 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6217 * The cache mode bits are all in the low 32-bits of the
6218 * PDE, so we can just spin on updating the low 32-bits.
6221 opde = *(u_int *)pde;
6222 npde = opde & ~mask;
6224 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6228 * Map a set of physical memory pages into the kernel virtual
6229 * address space. Return a pointer to where it is mapped. This
6230 * routine is intended to be used for mapping device memory,
6234 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6236 vm_offset_t va, offset;
6240 * If the specified range of physical addresses fits within the direct
6241 * map window, use the direct map.
6243 if (pa < dmaplimit && pa + size < dmaplimit) {
6244 va = PHYS_TO_DMAP(pa);
6245 if (!pmap_change_attr(va, size, mode))
6246 return ((void *)va);
6248 offset = pa & PAGE_MASK;
6249 size = round_page(offset + size);
6250 va = kva_alloc(size);
6252 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
6253 pa = trunc_page(pa);
6254 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6255 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6256 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6257 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6258 return ((void *)(va + offset));
6262 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6265 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6269 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6272 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6276 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6278 vm_offset_t base, offset;
6280 /* If we gave a direct map region in pmap_mapdev, do nothing */
6281 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6283 base = trunc_page(va);
6284 offset = va & PAGE_MASK;
6285 size = round_page(offset + size);
6286 kva_free(base, size);
6290 * Tries to demote a 1GB page mapping.
6293 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6295 pdp_entry_t newpdpe, oldpdpe;
6296 pd_entry_t *firstpde, newpde, *pde;
6297 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6301 PG_A = pmap_accessed_bit(pmap);
6302 PG_M = pmap_modified_bit(pmap);
6303 PG_V = pmap_valid_bit(pmap);
6304 PG_RW = pmap_rw_bit(pmap);
6306 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6308 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6309 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6310 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6311 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6312 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6313 " in pmap %p", va, pmap);
6316 mpdepa = VM_PAGE_TO_PHYS(mpde);
6317 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6318 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6319 KASSERT((oldpdpe & PG_A) != 0,
6320 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6321 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6322 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6326 * Initialize the page directory page.
6328 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6334 * Demote the mapping.
6339 * Invalidate a stale recursive mapping of the page directory page.
6341 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6343 pmap_pdpe_demotions++;
6344 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6345 " in pmap %p", va, pmap);
6350 * Sets the memory attribute for the specified page.
6353 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6356 m->md.pat_mode = ma;
6359 * If "m" is a normal page, update its direct mapping. This update
6360 * can be relied upon to perform any cache operations that are
6361 * required for data coherence.
6363 if ((m->flags & PG_FICTITIOUS) == 0 &&
6364 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6366 panic("memory attribute change on the direct map failed");
6370 * Changes the specified virtual address range's memory type to that given by
6371 * the parameter "mode". The specified virtual address range must be
6372 * completely contained within either the direct map or the kernel map. If
6373 * the virtual address range is contained within the kernel map, then the
6374 * memory type for each of the corresponding ranges of the direct map is also
6375 * changed. (The corresponding ranges of the direct map are those ranges that
6376 * map the same physical pages as the specified virtual address range.) These
6377 * changes to the direct map are necessary because Intel describes the
6378 * behavior of their processors as "undefined" if two or more mappings to the
6379 * same physical page have different memory types.
6381 * Returns zero if the change completed successfully, and either EINVAL or
6382 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6383 * of the virtual address range was not mapped, and ENOMEM is returned if
6384 * there was insufficient memory available to complete the change. In the
6385 * latter case, the memory type may have been changed on some part of the
6386 * virtual address range or the direct map.
6389 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6393 PMAP_LOCK(kernel_pmap);
6394 error = pmap_change_attr_locked(va, size, mode);
6395 PMAP_UNLOCK(kernel_pmap);
6400 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6402 vm_offset_t base, offset, tmpva;
6403 vm_paddr_t pa_start, pa_end;
6407 int cache_bits_pte, cache_bits_pde, error;
6410 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6411 base = trunc_page(va);
6412 offset = va & PAGE_MASK;
6413 size = round_page(offset + size);
6416 * Only supported on kernel virtual addresses, including the direct
6417 * map but excluding the recursive map.
6419 if (base < DMAP_MIN_ADDRESS)
6422 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6423 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6427 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6428 * into 4KB pages if required.
6430 for (tmpva = base; tmpva < base + size; ) {
6431 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6434 if (*pdpe & PG_PS) {
6436 * If the current 1GB page already has the required
6437 * memory type, then we need not demote this page. Just
6438 * increment tmpva to the next 1GB page frame.
6440 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6441 tmpva = trunc_1gpage(tmpva) + NBPDP;
6446 * If the current offset aligns with a 1GB page frame
6447 * and there is at least 1GB left within the range, then
6448 * we need not break down this page into 2MB pages.
6450 if ((tmpva & PDPMASK) == 0 &&
6451 tmpva + PDPMASK < base + size) {
6455 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6458 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6463 * If the current 2MB page already has the required
6464 * memory type, then we need not demote this page. Just
6465 * increment tmpva to the next 2MB page frame.
6467 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6468 tmpva = trunc_2mpage(tmpva) + NBPDR;
6473 * If the current offset aligns with a 2MB page frame
6474 * and there is at least 2MB left within the range, then
6475 * we need not break down this page into 4KB pages.
6477 if ((tmpva & PDRMASK) == 0 &&
6478 tmpva + PDRMASK < base + size) {
6482 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6485 pte = pmap_pde_to_pte(pde, tmpva);
6493 * Ok, all the pages exist, so run through them updating their
6494 * cache mode if required.
6496 pa_start = pa_end = 0;
6497 for (tmpva = base; tmpva < base + size; ) {
6498 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6499 if (*pdpe & PG_PS) {
6500 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6501 pmap_pde_attr(pdpe, cache_bits_pde,
6505 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6506 if (pa_start == pa_end) {
6507 /* Start physical address run. */
6508 pa_start = *pdpe & PG_PS_FRAME;
6509 pa_end = pa_start + NBPDP;
6510 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6513 /* Run ended, update direct map. */
6514 error = pmap_change_attr_locked(
6515 PHYS_TO_DMAP(pa_start),
6516 pa_end - pa_start, mode);
6519 /* Start physical address run. */
6520 pa_start = *pdpe & PG_PS_FRAME;
6521 pa_end = pa_start + NBPDP;
6524 tmpva = trunc_1gpage(tmpva) + NBPDP;
6527 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6529 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6530 pmap_pde_attr(pde, cache_bits_pde,
6534 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6535 if (pa_start == pa_end) {
6536 /* Start physical address run. */
6537 pa_start = *pde & PG_PS_FRAME;
6538 pa_end = pa_start + NBPDR;
6539 } else if (pa_end == (*pde & PG_PS_FRAME))
6542 /* Run ended, update direct map. */
6543 error = pmap_change_attr_locked(
6544 PHYS_TO_DMAP(pa_start),
6545 pa_end - pa_start, mode);
6548 /* Start physical address run. */
6549 pa_start = *pde & PG_PS_FRAME;
6550 pa_end = pa_start + NBPDR;
6553 tmpva = trunc_2mpage(tmpva) + NBPDR;
6555 pte = pmap_pde_to_pte(pde, tmpva);
6556 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6557 pmap_pte_attr(pte, cache_bits_pte,
6561 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6562 if (pa_start == pa_end) {
6563 /* Start physical address run. */
6564 pa_start = *pte & PG_FRAME;
6565 pa_end = pa_start + PAGE_SIZE;
6566 } else if (pa_end == (*pte & PG_FRAME))
6567 pa_end += PAGE_SIZE;
6569 /* Run ended, update direct map. */
6570 error = pmap_change_attr_locked(
6571 PHYS_TO_DMAP(pa_start),
6572 pa_end - pa_start, mode);
6575 /* Start physical address run. */
6576 pa_start = *pte & PG_FRAME;
6577 pa_end = pa_start + PAGE_SIZE;
6583 if (error == 0 && pa_start != pa_end)
6584 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6585 pa_end - pa_start, mode);
6588 * Flush CPU caches if required to make sure any data isn't cached that
6589 * shouldn't be, etc.
6592 pmap_invalidate_range(kernel_pmap, base, tmpva);
6593 pmap_invalidate_cache_range(base, tmpva, FALSE);
6599 * Demotes any mapping within the direct map region that covers more than the
6600 * specified range of physical addresses. This range's size must be a power
6601 * of two and its starting address must be a multiple of its size. Since the
6602 * demotion does not change any attributes of the mapping, a TLB invalidation
6603 * is not mandatory. The caller may, however, request a TLB invalidation.
6606 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6615 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6616 KASSERT((base & (len - 1)) == 0,
6617 ("pmap_demote_DMAP: base is not a multiple of len"));
6618 if (len < NBPDP && base < dmaplimit) {
6619 va = PHYS_TO_DMAP(base);
6621 PMAP_LOCK(kernel_pmap);
6622 pdpe = pmap_pdpe(kernel_pmap, va);
6623 if ((*pdpe & X86_PG_V) == 0)
6624 panic("pmap_demote_DMAP: invalid PDPE");
6625 if ((*pdpe & PG_PS) != 0) {
6626 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6627 panic("pmap_demote_DMAP: PDPE failed");
6631 pde = pmap_pdpe_to_pde(pdpe, va);
6632 if ((*pde & X86_PG_V) == 0)
6633 panic("pmap_demote_DMAP: invalid PDE");
6634 if ((*pde & PG_PS) != 0) {
6635 if (!pmap_demote_pde(kernel_pmap, pde, va))
6636 panic("pmap_demote_DMAP: PDE failed");
6640 if (changed && invalidate)
6641 pmap_invalidate_page(kernel_pmap, va);
6642 PMAP_UNLOCK(kernel_pmap);
6647 * perform the pmap work for mincore
6650 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6653 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6657 PG_A = pmap_accessed_bit(pmap);
6658 PG_M = pmap_modified_bit(pmap);
6659 PG_V = pmap_valid_bit(pmap);
6660 PG_RW = pmap_rw_bit(pmap);
6664 pdep = pmap_pde(pmap, addr);
6665 if (pdep != NULL && (*pdep & PG_V)) {
6666 if (*pdep & PG_PS) {
6668 /* Compute the physical address of the 4KB page. */
6669 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6671 val = MINCORE_SUPER;
6673 pte = *pmap_pde_to_pte(pdep, addr);
6674 pa = pte & PG_FRAME;
6682 if ((pte & PG_V) != 0) {
6683 val |= MINCORE_INCORE;
6684 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6685 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6686 if ((pte & PG_A) != 0)
6687 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6689 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6690 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6691 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6692 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6693 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6696 PA_UNLOCK_COND(*locked_pa);
6702 pmap_activate(struct thread *td)
6704 pmap_t pmap, oldpmap;
6708 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6709 oldpmap = PCPU_GET(curpmap);
6710 cpuid = PCPU_GET(cpuid);
6712 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6713 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6714 CPU_SET_ATOMIC(cpuid, &pmap->pm_save);
6716 CPU_CLR(cpuid, &oldpmap->pm_active);
6717 CPU_SET(cpuid, &pmap->pm_active);
6718 CPU_SET(cpuid, &pmap->pm_save);
6720 td->td_pcb->pcb_cr3 = pmap->pm_cr3;
6721 load_cr3(pmap->pm_cr3);
6722 PCPU_SET(curpmap, pmap);
6727 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6732 * Increase the starting virtual address of the given mapping if a
6733 * different alignment might result in more superpage mappings.
6736 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6737 vm_offset_t *addr, vm_size_t size)
6739 vm_offset_t superpage_offset;
6743 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6744 offset += ptoa(object->pg_color);
6745 superpage_offset = offset & PDRMASK;
6746 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6747 (*addr & PDRMASK) == superpage_offset)
6749 if ((*addr & PDRMASK) < superpage_offset)
6750 *addr = (*addr & ~PDRMASK) + superpage_offset;
6752 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6756 static unsigned long num_dirty_emulations;
6757 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6758 &num_dirty_emulations, 0, NULL);
6760 static unsigned long num_accessed_emulations;
6761 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6762 &num_accessed_emulations, 0, NULL);
6764 static unsigned long num_superpage_accessed_emulations;
6765 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6766 &num_superpage_accessed_emulations, 0, NULL);
6768 static unsigned long ad_emulation_superpage_promotions;
6769 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6770 &ad_emulation_superpage_promotions, 0, NULL);
6771 #endif /* INVARIANTS */
6774 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6777 struct rwlock *lock;
6780 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
6781 boolean_t pv_lists_locked;
6783 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
6784 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
6786 if (!pmap_emulate_ad_bits(pmap))
6789 PG_A = pmap_accessed_bit(pmap);
6790 PG_M = pmap_modified_bit(pmap);
6791 PG_V = pmap_valid_bit(pmap);
6792 PG_RW = pmap_rw_bit(pmap);
6796 pv_lists_locked = FALSE;
6800 pde = pmap_pde(pmap, va);
6801 if (pde == NULL || (*pde & PG_V) == 0)
6804 if ((*pde & PG_PS) != 0) {
6805 if (ftype == VM_PROT_READ) {
6807 atomic_add_long(&num_superpage_accessed_emulations, 1);
6815 pte = pmap_pde_to_pte(pde, va);
6816 if ((*pte & PG_V) == 0)
6819 if (ftype == VM_PROT_WRITE) {
6820 if ((*pte & PG_RW) == 0)
6823 * Set the modified and accessed bits simultaneously.
6825 * Intel EPT PTEs that do software emulation of A/D bits map
6826 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
6827 * An EPT misconfiguration is triggered if the PTE is writable
6828 * but not readable (WR=10). This is avoided by setting PG_A
6829 * and PG_M simultaneously.
6831 *pte |= PG_M | PG_A;
6836 /* try to promote the mapping */
6837 if (va < VM_MAXUSER_ADDRESS)
6838 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6842 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6844 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
6845 pmap_ps_enabled(pmap) &&
6846 (m->flags & PG_FICTITIOUS) == 0 &&
6847 vm_reserv_level_iffullpop(m) == 0) {
6848 if (!pv_lists_locked) {
6849 pv_lists_locked = TRUE;
6850 if (!rw_try_rlock(&pvh_global_lock)) {
6852 rw_rlock(&pvh_global_lock);
6856 pmap_promote_pde(pmap, pde, va, &lock);
6858 atomic_add_long(&ad_emulation_superpage_promotions, 1);
6862 if (ftype == VM_PROT_WRITE)
6863 atomic_add_long(&num_dirty_emulations, 1);
6865 atomic_add_long(&num_accessed_emulations, 1);
6867 rv = 0; /* success */
6871 if (pv_lists_locked)
6872 rw_runlock(&pvh_global_lock);
6878 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
6883 pt_entry_t *pte, PG_V;
6887 PG_V = pmap_valid_bit(pmap);
6890 pml4 = pmap_pml4e(pmap, va);
6892 if ((*pml4 & PG_V) == 0)
6895 pdp = pmap_pml4e_to_pdpe(pml4, va);
6897 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
6900 pde = pmap_pdpe_to_pde(pdp, va);
6902 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
6905 pte = pmap_pde_to_pte(pde, va);
6913 #include "opt_ddb.h"
6915 #include <ddb/ddb.h>
6917 DB_SHOW_COMMAND(pte, pmap_print_pte)
6923 pt_entry_t *pte, PG_V;
6927 va = (vm_offset_t)addr;
6928 pmap = PCPU_GET(curpmap); /* XXX */
6930 db_printf("show pte addr\n");
6933 PG_V = pmap_valid_bit(pmap);
6934 pml4 = pmap_pml4e(pmap, va);
6935 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
6936 if ((*pml4 & PG_V) == 0) {
6940 pdp = pmap_pml4e_to_pdpe(pml4, va);
6941 db_printf(" pdpe %#016lx", *pdp);
6942 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
6946 pde = pmap_pdpe_to_pde(pdp, va);
6947 db_printf(" pde %#016lx", *pde);
6948 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
6952 pte = pmap_pde_to_pte(pde, va);
6953 db_printf(" pte %#016lx\n", *pte);
6956 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
6961 a = (vm_paddr_t)addr;
6962 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
6964 db_printf("show phys2dmap addr\n");