2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #include <sys/_unrhdr.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_object.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_pageout.h>
132 #include <vm/vm_pager.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
137 #include <machine/intr_machdep.h>
138 #include <machine/apicvar.h>
139 #include <machine/cpu.h>
140 #include <machine/cputypes.h>
141 #include <machine/md_var.h>
142 #include <machine/pcb.h>
143 #include <machine/specialreg.h>
145 #include <machine/smp.h>
148 static __inline boolean_t
149 pmap_emulate_ad_bits(pmap_t pmap)
152 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
155 static __inline pt_entry_t
156 pmap_valid_bit(pmap_t pmap)
160 switch (pmap->pm_type) {
165 if (pmap_emulate_ad_bits(pmap))
166 mask = EPT_PG_EMUL_V;
171 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
177 static __inline pt_entry_t
178 pmap_rw_bit(pmap_t pmap)
182 switch (pmap->pm_type) {
187 if (pmap_emulate_ad_bits(pmap))
188 mask = EPT_PG_EMUL_RW;
193 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
199 static __inline pt_entry_t
200 pmap_global_bit(pmap_t pmap)
204 switch (pmap->pm_type) {
212 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
218 static __inline pt_entry_t
219 pmap_accessed_bit(pmap_t pmap)
223 switch (pmap->pm_type) {
228 if (pmap_emulate_ad_bits(pmap))
234 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
240 static __inline pt_entry_t
241 pmap_modified_bit(pmap_t pmap)
245 switch (pmap->pm_type) {
250 if (pmap_emulate_ad_bits(pmap))
256 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
262 #if !defined(DIAGNOSTIC)
263 #ifdef __GNUC_GNU_INLINE__
264 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
266 #define PMAP_INLINE extern inline
273 #define PV_STAT(x) do { x ; } while (0)
275 #define PV_STAT(x) do { } while (0)
278 #define pa_index(pa) ((pa) >> PDRSHIFT)
279 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
281 #define NPV_LIST_LOCKS MAXCPU
283 #define PHYS_TO_PV_LIST_LOCK(pa) \
284 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
286 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
287 struct rwlock **_lockp = (lockp); \
288 struct rwlock *_new_lock; \
290 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
291 if (_new_lock != *_lockp) { \
292 if (*_lockp != NULL) \
293 rw_wunlock(*_lockp); \
294 *_lockp = _new_lock; \
299 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
300 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
302 #define RELEASE_PV_LIST_LOCK(lockp) do { \
303 struct rwlock **_lockp = (lockp); \
305 if (*_lockp != NULL) { \
306 rw_wunlock(*_lockp); \
311 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
312 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
314 struct pmap kernel_pmap_store;
316 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
317 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
320 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
321 "Number of kernel page table pages allocated on bootup");
324 static vm_paddr_t dmaplimit;
325 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
328 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
330 static int pat_works = 1;
331 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
332 "Is page attribute table fully functional?");
334 static int pg_ps_enabled = 1;
335 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
336 "Are large page mappings enabled?");
338 #define PAT_INDEX_SIZE 8
339 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
341 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
342 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
343 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
344 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
346 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
347 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
348 static int ndmpdpphys; /* number of DMPDPphys pages */
350 static struct rwlock_padalign pvh_global_lock;
353 * Data for the pv entry allocation mechanism
355 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
356 static struct mtx pv_chunks_mutex;
357 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
358 static struct md_page *pv_table;
361 * All those kernel PT submaps that BSD is so fond of
363 pt_entry_t *CMAP1 = 0;
366 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
368 static struct unrhdr pcid_unr;
369 static struct mtx pcid_mtx;
370 int pmap_pcid_enabled = 1;
371 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN, &pmap_pcid_enabled,
372 0, "Is TLB Context ID enabled ?");
373 int invpcid_works = 0;
376 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
383 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
385 return (sysctl_handle_64(oidp, &res, 0, req));
387 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
388 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
389 "Count of saved TLB context on switch");
394 static caddr_t crashdumpmap;
396 static void free_pv_chunk(struct pv_chunk *pc);
397 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
398 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
399 static int popcnt_pc_map_elem(uint64_t elem);
400 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
401 static void reserve_pv_entries(pmap_t pmap, int needed,
402 struct rwlock **lockp);
403 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
404 struct rwlock **lockp);
405 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
406 struct rwlock **lockp);
407 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
408 struct rwlock **lockp);
409 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
410 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
413 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
414 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
415 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
416 vm_offset_t va, struct rwlock **lockp);
417 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
419 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
420 vm_prot_t prot, struct rwlock **lockp);
421 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
422 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
423 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
424 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
425 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
426 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
427 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
428 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
429 struct rwlock **lockp);
430 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
432 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
433 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
434 struct spglist *free, struct rwlock **lockp);
435 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
436 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
437 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
438 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
439 struct spglist *free);
440 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
441 vm_page_t m, struct rwlock **lockp);
442 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
444 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
446 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
447 struct rwlock **lockp);
448 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
449 struct rwlock **lockp);
450 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
451 struct rwlock **lockp);
453 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
454 struct spglist *free);
455 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
456 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
459 * Move the kernel virtual free pointer to the next
460 * 2MB. This is used to help improve performance
461 * by using a large (2MB) page for much of the kernel
462 * (.text, .data, .bss)
465 pmap_kmem_choose(vm_offset_t addr)
467 vm_offset_t newaddr = addr;
469 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
473 /********************/
474 /* Inline functions */
475 /********************/
477 /* Return a non-clipped PD index for a given VA */
478 static __inline vm_pindex_t
479 pmap_pde_pindex(vm_offset_t va)
481 return (va >> PDRSHIFT);
485 /* Return various clipped indexes for a given VA */
486 static __inline vm_pindex_t
487 pmap_pte_index(vm_offset_t va)
490 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
493 static __inline vm_pindex_t
494 pmap_pde_index(vm_offset_t va)
497 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
500 static __inline vm_pindex_t
501 pmap_pdpe_index(vm_offset_t va)
504 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
507 static __inline vm_pindex_t
508 pmap_pml4e_index(vm_offset_t va)
511 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
514 /* Return a pointer to the PML4 slot that corresponds to a VA */
515 static __inline pml4_entry_t *
516 pmap_pml4e(pmap_t pmap, vm_offset_t va)
519 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
522 /* Return a pointer to the PDP slot that corresponds to a VA */
523 static __inline pdp_entry_t *
524 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
528 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
529 return (&pdpe[pmap_pdpe_index(va)]);
532 /* Return a pointer to the PDP slot that corresponds to a VA */
533 static __inline pdp_entry_t *
534 pmap_pdpe(pmap_t pmap, vm_offset_t va)
539 PG_V = pmap_valid_bit(pmap);
540 pml4e = pmap_pml4e(pmap, va);
541 if ((*pml4e & PG_V) == 0)
543 return (pmap_pml4e_to_pdpe(pml4e, va));
546 /* Return a pointer to the PD slot that corresponds to a VA */
547 static __inline pd_entry_t *
548 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
552 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
553 return (&pde[pmap_pde_index(va)]);
556 /* Return a pointer to the PD slot that corresponds to a VA */
557 static __inline pd_entry_t *
558 pmap_pde(pmap_t pmap, vm_offset_t va)
563 PG_V = pmap_valid_bit(pmap);
564 pdpe = pmap_pdpe(pmap, va);
565 if (pdpe == NULL || (*pdpe & PG_V) == 0)
567 return (pmap_pdpe_to_pde(pdpe, va));
570 /* Return a pointer to the PT slot that corresponds to a VA */
571 static __inline pt_entry_t *
572 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
576 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
577 return (&pte[pmap_pte_index(va)]);
580 /* Return a pointer to the PT slot that corresponds to a VA */
581 static __inline pt_entry_t *
582 pmap_pte(pmap_t pmap, vm_offset_t va)
587 PG_V = pmap_valid_bit(pmap);
588 pde = pmap_pde(pmap, va);
589 if (pde == NULL || (*pde & PG_V) == 0)
591 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
592 return ((pt_entry_t *)pde);
593 return (pmap_pde_to_pte(pde, va));
597 pmap_resident_count_inc(pmap_t pmap, int count)
600 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
601 pmap->pm_stats.resident_count += count;
605 pmap_resident_count_dec(pmap_t pmap, int count)
608 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
609 pmap->pm_stats.resident_count -= count;
612 PMAP_INLINE pt_entry_t *
613 vtopte(vm_offset_t va)
615 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
617 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
619 return (PTmap + ((va >> PAGE_SHIFT) & mask));
622 static __inline pd_entry_t *
623 vtopde(vm_offset_t va)
625 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
627 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
629 return (PDmap + ((va >> PDRSHIFT) & mask));
633 allocpages(vm_paddr_t *firstaddr, int n)
638 bzero((void *)ret, n * PAGE_SIZE);
639 *firstaddr += n * PAGE_SIZE;
643 CTASSERT(powerof2(NDMPML4E));
645 /* number of kernel PDP slots */
646 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
649 nkpt_init(vm_paddr_t addr)
656 pt_pages = howmany(addr, 1 << PDRSHIFT);
657 pt_pages += NKPDPE(pt_pages);
660 * Add some slop beyond the bare minimum required for bootstrapping
663 * This is quite important when allocating KVA for kernel modules.
664 * The modules are required to be linked in the negative 2GB of
665 * the address space. If we run out of KVA in this region then
666 * pmap_growkernel() will need to allocate page table pages to map
667 * the entire 512GB of KVA space which is an unnecessary tax on
670 pt_pages += 8; /* 16MB additional slop for kernel modules */
676 create_pagetables(vm_paddr_t *firstaddr)
678 int i, j, ndm1g, nkpdpe;
684 /* Allocate page table pages for the direct map */
685 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
686 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
688 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
689 if (ndmpdpphys > NDMPML4E) {
691 * Each NDMPML4E allows 512 GB, so limit to that,
692 * and then readjust ndmpdp and ndmpdpphys.
694 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
695 Maxmem = atop(NDMPML4E * NBPML4);
696 ndmpdpphys = NDMPML4E;
697 ndmpdp = NDMPML4E * NPDEPG;
699 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
701 if ((amd_feature & AMDID_PAGE1GB) != 0)
702 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
704 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
705 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
708 KPML4phys = allocpages(firstaddr, 1);
709 KPDPphys = allocpages(firstaddr, NKPML4E);
712 * Allocate the initial number of kernel page table pages required to
713 * bootstrap. We defer this until after all memory-size dependent
714 * allocations are done (e.g. direct map), so that we don't have to
715 * build in too much slop in our estimate.
717 * Note that when NKPML4E > 1, we have an empty page underneath
718 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
719 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
721 nkpt_init(*firstaddr);
722 nkpdpe = NKPDPE(nkpt);
724 KPTphys = allocpages(firstaddr, nkpt);
725 KPDphys = allocpages(firstaddr, nkpdpe);
727 /* Fill in the underlying page table pages */
728 /* Nominally read-only (but really R/W) from zero to physfree */
729 /* XXX not fully used, underneath 2M pages */
730 pt_p = (pt_entry_t *)KPTphys;
731 for (i = 0; ptoa(i) < *firstaddr; i++)
732 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
734 /* Now map the page tables at their location within PTmap */
735 pd_p = (pd_entry_t *)KPDphys;
736 for (i = 0; i < nkpt; i++)
737 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
739 /* Map from zero to end of allocations under 2M pages */
740 /* This replaces some of the KPTphys entries above */
741 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
742 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
745 /* And connect up the PD to the PDP (leaving room for L4 pages) */
746 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
747 for (i = 0; i < nkpdpe; i++)
748 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
752 * Now, set up the direct map region using 2MB and/or 1GB pages. If
753 * the end of physical memory is not aligned to a 1GB page boundary,
754 * then the residual physical memory is mapped with 2MB pages. Later,
755 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
756 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
757 * that are partially used.
759 pd_p = (pd_entry_t *)DMPDphys;
760 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
761 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
762 /* Preset PG_M and PG_A because demotion expects it. */
763 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
766 pdp_p = (pdp_entry_t *)DMPDPphys;
767 for (i = 0; i < ndm1g; i++) {
768 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
769 /* Preset PG_M and PG_A because demotion expects it. */
770 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
773 for (j = 0; i < ndmpdp; i++, j++) {
774 pdp_p[i] = DMPDphys + ptoa(j);
775 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
778 /* And recursively map PML4 to itself in order to get PTmap */
779 p4_p = (pml4_entry_t *)KPML4phys;
780 p4_p[PML4PML4I] = KPML4phys;
781 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
783 /* Connect the Direct Map slot(s) up to the PML4. */
784 for (i = 0; i < ndmpdpphys; i++) {
785 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
786 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
789 /* Connect the KVA slots up to the PML4 */
790 for (i = 0; i < NKPML4E; i++) {
791 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
792 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
797 * Bootstrap the system enough to run with virtual memory.
799 * On amd64 this is called after mapping has already been enabled
800 * and just syncs the pmap module with what has already been done.
801 * [We can't call it easily with mapping off since the kernel is not
802 * mapped with PA == VA, hence we would have to relocate every address
803 * from the linked base (virtual) address "KERNBASE" to the actual
804 * (physical) address starting relative to 0]
807 pmap_bootstrap(vm_paddr_t *firstaddr)
810 pt_entry_t *pte, *unused;
813 * Create an initial set of page tables to run the kernel in.
815 create_pagetables(firstaddr);
817 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
818 virtual_avail = pmap_kmem_choose(virtual_avail);
820 virtual_end = VM_MAX_KERNEL_ADDRESS;
823 /* XXX do %cr0 as well */
824 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
826 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
827 load_cr4(rcr4() | CR4_SMEP);
830 * Initialize the kernel pmap (which is statically allocated).
832 PMAP_LOCK_INIT(kernel_pmap);
833 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
834 kernel_pmap->pm_cr3 = KPML4phys;
835 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
836 CPU_ZERO(&kernel_pmap->pm_save);
837 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
838 kernel_pmap->pm_flags = pmap_flags;
841 * Initialize the global pv list lock.
843 rw_init(&pvh_global_lock, "pmap pv global");
846 * Reserve some special page table entries/VA space for temporary
849 #define SYSMAP(c, p, v, n) \
850 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
856 * CMAP1 is only used for the memory test.
858 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
863 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
867 /* Initialize the PAT MSR. */
870 /* Initialize TLB Context Id. */
871 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
872 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
873 load_cr4(rcr4() | CR4_PCIDE);
874 mtx_init(&pcid_mtx, "pcid", NULL, MTX_DEF);
875 init_unrhdr(&pcid_unr, 1, (1 << 12) - 1, &pcid_mtx);
876 /* Check for INVPCID support */
877 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
879 kernel_pmap->pm_pcid = 0;
881 pmap_pcid_enabled = 0;
884 pmap_pcid_enabled = 0;
893 int pat_table[PAT_INDEX_SIZE];
898 /* Bail if this CPU doesn't implement PAT. */
899 if ((cpu_feature & CPUID_PAT) == 0)
902 /* Set default PAT index table. */
903 for (i = 0; i < PAT_INDEX_SIZE; i++)
905 pat_table[PAT_WRITE_BACK] = 0;
906 pat_table[PAT_WRITE_THROUGH] = 1;
907 pat_table[PAT_UNCACHEABLE] = 3;
908 pat_table[PAT_WRITE_COMBINING] = 3;
909 pat_table[PAT_WRITE_PROTECTED] = 3;
910 pat_table[PAT_UNCACHED] = 3;
912 /* Initialize default PAT entries. */
913 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
914 PAT_VALUE(1, PAT_WRITE_THROUGH) |
915 PAT_VALUE(2, PAT_UNCACHED) |
916 PAT_VALUE(3, PAT_UNCACHEABLE) |
917 PAT_VALUE(4, PAT_WRITE_BACK) |
918 PAT_VALUE(5, PAT_WRITE_THROUGH) |
919 PAT_VALUE(6, PAT_UNCACHED) |
920 PAT_VALUE(7, PAT_UNCACHEABLE);
924 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
925 * Program 5 and 6 as WP and WC.
926 * Leave 4 and 7 as WB and UC.
928 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
929 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
930 PAT_VALUE(6, PAT_WRITE_COMBINING);
931 pat_table[PAT_UNCACHED] = 2;
932 pat_table[PAT_WRITE_PROTECTED] = 5;
933 pat_table[PAT_WRITE_COMBINING] = 6;
936 * Just replace PAT Index 2 with WC instead of UC-.
938 pat_msr &= ~PAT_MASK(2);
939 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
940 pat_table[PAT_WRITE_COMBINING] = 2;
945 load_cr4(cr4 & ~CR4_PGE);
947 /* Disable caches (CD = 1, NW = 0). */
949 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
951 /* Flushes caches and TLBs. */
955 /* Update PAT and index table. */
956 wrmsr(MSR_PAT, pat_msr);
957 for (i = 0; i < PAT_INDEX_SIZE; i++)
958 pat_index[i] = pat_table[i];
960 /* Flush caches and TLBs again. */
964 /* Restore caches and PGE. */
970 * Initialize a vm_page's machine-dependent fields.
973 pmap_page_init(vm_page_t m)
976 TAILQ_INIT(&m->md.pv_list);
977 m->md.pat_mode = PAT_WRITE_BACK;
981 * Initialize the pmap module.
982 * Called by vm_init, to initialize any structures that the pmap
983 * system needs to map virtual memory.
993 * Initialize the vm page array entries for the kernel pmap's
996 for (i = 0; i < nkpt; i++) {
997 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
998 KASSERT(mpte >= vm_page_array &&
999 mpte < &vm_page_array[vm_page_array_size],
1000 ("pmap_init: page table page is out of range"));
1001 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1002 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1006 * If the kernel is running in a virtual machine on an AMD Family 10h
1007 * processor, then it must assume that MCA is enabled by the virtual
1010 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
1011 CPUID_TO_FAMILY(cpu_id) == 0x10)
1012 workaround_erratum383 = 1;
1015 * Are large page mappings enabled?
1017 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1018 if (pg_ps_enabled) {
1019 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1020 ("pmap_init: can't assign to pagesizes[1]"));
1021 pagesizes[1] = NBPDR;
1025 * Initialize the pv chunk list mutex.
1027 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1030 * Initialize the pool of pv list locks.
1032 for (i = 0; i < NPV_LIST_LOCKS; i++)
1033 rw_init(&pv_list_locks[i], "pmap pv list");
1036 * Calculate the size of the pv head table for superpages.
1038 for (i = 0; phys_avail[i + 1]; i += 2);
1039 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
1042 * Allocate memory for the pv head table for superpages.
1044 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1046 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1048 for (i = 0; i < pv_npg; i++)
1049 TAILQ_INIT(&pv_table[i].pv_list);
1052 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1053 "2MB page mapping counters");
1055 static u_long pmap_pde_demotions;
1056 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1057 &pmap_pde_demotions, 0, "2MB page demotions");
1059 static u_long pmap_pde_mappings;
1060 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1061 &pmap_pde_mappings, 0, "2MB page mappings");
1063 static u_long pmap_pde_p_failures;
1064 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1065 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1067 static u_long pmap_pde_promotions;
1068 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1069 &pmap_pde_promotions, 0, "2MB page promotions");
1071 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1072 "1GB page mapping counters");
1074 static u_long pmap_pdpe_demotions;
1075 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1076 &pmap_pdpe_demotions, 0, "1GB page demotions");
1078 /***************************************************
1079 * Low level helper routines.....
1080 ***************************************************/
1083 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1085 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1087 switch (pmap->pm_type) {
1089 /* Verify that both PAT bits are not set at the same time */
1090 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1091 ("Invalid PAT bits in entry %#lx", entry));
1093 /* Swap the PAT bits if one of them is set */
1094 if ((entry & x86_pat_bits) != 0)
1095 entry ^= x86_pat_bits;
1099 * Nothing to do - the memory attributes are represented
1100 * the same way for regular pages and superpages.
1104 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1111 * Determine the appropriate bits to set in a PTE or PDE for a specified
1115 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1117 int cache_bits, pat_flag, pat_idx;
1119 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1120 panic("Unknown caching mode %d\n", mode);
1122 switch (pmap->pm_type) {
1124 /* The PAT bit is different for PTE's and PDE's. */
1125 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1127 /* Map the caching mode to a PAT index. */
1128 pat_idx = pat_index[mode];
1130 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1133 cache_bits |= pat_flag;
1135 cache_bits |= PG_NC_PCD;
1137 cache_bits |= PG_NC_PWT;
1141 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1145 panic("unsupported pmap type %d", pmap->pm_type);
1148 return (cache_bits);
1152 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1156 switch (pmap->pm_type) {
1158 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1161 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1164 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1170 static __inline boolean_t
1171 pmap_ps_enabled(pmap_t pmap)
1174 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1178 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1181 switch (pmap->pm_type) {
1187 * This is a little bogus since the generation number is
1188 * supposed to be bumped up when a region of the address
1189 * space is invalidated in the page tables.
1191 * In this case the old PDE entry is valid but yet we want
1192 * to make sure that any mappings using the old entry are
1193 * invalidated in the TLB.
1195 * The reason this works as expected is because we rendezvous
1196 * "all" host cpus and force any vcpu context to exit as a
1199 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1202 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1204 pde_store(pde, newpde);
1208 * After changing the page size for the specified virtual address in the page
1209 * table, flush the corresponding entries from the processor's TLB. Only the
1210 * calling processor's TLB is affected.
1212 * The calling thread must be pinned to a processor.
1215 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1219 if (pmap->pm_type == PT_EPT)
1222 KASSERT(pmap->pm_type == PT_X86,
1223 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1225 PG_G = pmap_global_bit(pmap);
1227 if ((newpde & PG_PS) == 0)
1228 /* Demotion: flush a specific 2MB page mapping. */
1230 else if ((newpde & PG_G) == 0)
1232 * Promotion: flush every 4KB page mapping from the TLB
1233 * because there are too many to flush individually.
1238 * Promotion: flush every 4KB page mapping from the TLB,
1239 * including any global (PG_G) mappings.
1247 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va)
1249 struct invpcid_descr d;
1252 if (invpcid_works) {
1253 d.pcid = pmap->pm_pcid;
1256 invpcid(&d, INVPCID_ADDR);
1262 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1264 load_cr3(cr3 | CR3_PCID_SAVE);
1269 * For SMP, these functions have to use the IPI mechanism for coherence.
1271 * N.B.: Before calling any of the following TLB invalidation functions,
1272 * the calling processor must ensure that all stores updating a non-
1273 * kernel page table are globally performed. Otherwise, another
1274 * processor could cache an old, pre-update entry without being
1275 * invalidated. This can happen one of two ways: (1) The pmap becomes
1276 * active on another processor after its pm_active field is checked by
1277 * one of the following functions but before a store updating the page
1278 * table is globally performed. (2) The pmap becomes active on another
1279 * processor before its pm_active field is checked but due to
1280 * speculative loads one of the following functions stills reads the
1281 * pmap as inactive on the other processor.
1283 * The kernel page table is exempt because its pm_active field is
1284 * immutable. The kernel page table is always active on every
1289 * Interrupt the cpus that are executing in the guest context.
1290 * This will force the vcpu to exit and the cached EPT mappings
1291 * will be invalidated by the host before the next vmresume.
1293 static __inline void
1294 pmap_invalidate_ept(pmap_t pmap)
1298 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1299 ("pmap_invalidate_ept: absurd pm_active"));
1302 * The TLB mappings associated with a vcpu context are not
1303 * flushed each time a different vcpu is chosen to execute.
1305 * This is in contrast with a process's vtop mappings that
1306 * are flushed from the TLB on each context switch.
1308 * Therefore we need to do more than just a TLB shootdown on
1309 * the active cpus in 'pmap->pm_active'. To do this we keep
1310 * track of the number of invalidations performed on this pmap.
1312 * Each vcpu keeps a cache of this counter and compares it
1313 * just before a vmresume. If the counter is out-of-date an
1314 * invept will be done to flush stale mappings from the TLB.
1316 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1319 * Force the vcpu to exit and trap back into the hypervisor.
1321 * XXX this is not optimal because IPI_AST builds a trapframe
1322 * whereas all we need is an 'eoi' followed by 'iret'.
1324 ipi_selected(pmap->pm_active, IPI_AST);
1329 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1331 cpuset_t other_cpus;
1334 if (pmap->pm_type == PT_EPT) {
1335 pmap_invalidate_ept(pmap);
1339 KASSERT(pmap->pm_type == PT_X86,
1340 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1343 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1344 if (!pmap_pcid_enabled) {
1347 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1348 if (pmap == PCPU_GET(curpmap))
1351 pmap_invalidate_page_pcid(pmap, va);
1356 smp_invlpg(pmap, va);
1358 cpuid = PCPU_GET(cpuid);
1359 other_cpus = all_cpus;
1360 CPU_CLR(cpuid, &other_cpus);
1361 if (CPU_ISSET(cpuid, &pmap->pm_active))
1363 else if (pmap_pcid_enabled) {
1364 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1365 pmap_invalidate_page_pcid(pmap, va);
1369 if (pmap_pcid_enabled)
1370 CPU_AND(&other_cpus, &pmap->pm_save);
1372 CPU_AND(&other_cpus, &pmap->pm_active);
1373 if (!CPU_EMPTY(&other_cpus))
1374 smp_masked_invlpg(other_cpus, pmap, va);
1380 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1382 struct invpcid_descr d;
1386 if (invpcid_works) {
1387 d.pcid = pmap->pm_pcid;
1389 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
1391 invpcid(&d, INVPCID_ADDR);
1398 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1399 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1401 load_cr3(cr3 | CR3_PCID_SAVE);
1406 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1408 cpuset_t other_cpus;
1412 if (pmap->pm_type == PT_EPT) {
1413 pmap_invalidate_ept(pmap);
1417 KASSERT(pmap->pm_type == PT_X86,
1418 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1421 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1422 if (!pmap_pcid_enabled) {
1423 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1426 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1427 if (pmap == PCPU_GET(curpmap)) {
1428 for (addr = sva; addr < eva;
1432 pmap_invalidate_range_pcid(pmap,
1439 smp_invlpg_range(pmap, sva, eva);
1441 cpuid = PCPU_GET(cpuid);
1442 other_cpus = all_cpus;
1443 CPU_CLR(cpuid, &other_cpus);
1444 if (CPU_ISSET(cpuid, &pmap->pm_active)) {
1445 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1447 } else if (pmap_pcid_enabled) {
1448 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1449 pmap_invalidate_range_pcid(pmap, sva, eva);
1453 if (pmap_pcid_enabled)
1454 CPU_AND(&other_cpus, &pmap->pm_save);
1456 CPU_AND(&other_cpus, &pmap->pm_active);
1457 if (!CPU_EMPTY(&other_cpus))
1458 smp_masked_invlpg_range(other_cpus, pmap, sva, eva);
1464 pmap_invalidate_all(pmap_t pmap)
1466 cpuset_t other_cpus;
1467 struct invpcid_descr d;
1471 if (pmap->pm_type == PT_EPT) {
1472 pmap_invalidate_ept(pmap);
1476 KASSERT(pmap->pm_type == PT_X86,
1477 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1480 cpuid = PCPU_GET(cpuid);
1481 if (pmap == kernel_pmap ||
1482 (pmap_pcid_enabled && !CPU_CMP(&pmap->pm_save, &all_cpus)) ||
1483 !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1484 if (invpcid_works) {
1485 bzero(&d, sizeof(d));
1486 invpcid(&d, INVPCID_CTXGLOB);
1490 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1493 other_cpus = all_cpus;
1494 CPU_CLR(cpuid, &other_cpus);
1497 * This logic is duplicated in the Xinvltlb shootdown
1500 if (pmap_pcid_enabled) {
1501 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1502 if (invpcid_works) {
1503 d.pcid = pmap->pm_pcid;
1506 invpcid(&d, INVPCID_CTX);
1512 * Bit 63 is clear, pcid TLB
1513 * entries are invalidated.
1515 load_cr3(pmap->pm_cr3);
1516 load_cr3(cr3 | CR3_PCID_SAVE);
1522 } else if (CPU_ISSET(cpuid, &pmap->pm_active))
1524 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1525 if (pmap_pcid_enabled)
1526 CPU_AND(&other_cpus, &pmap->pm_save);
1528 CPU_AND(&other_cpus, &pmap->pm_active);
1529 if (!CPU_EMPTY(&other_cpus))
1530 smp_masked_invltlb(other_cpus, pmap);
1536 pmap_invalidate_cache(void)
1546 cpuset_t invalidate; /* processors that invalidate their TLB */
1551 u_int store; /* processor that updates the PDE */
1555 pmap_update_pde_action(void *arg)
1557 struct pde_action *act = arg;
1559 if (act->store == PCPU_GET(cpuid))
1560 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1564 pmap_update_pde_teardown(void *arg)
1566 struct pde_action *act = arg;
1568 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1569 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1573 * Change the page size for the specified virtual address in a way that
1574 * prevents any possibility of the TLB ever having two entries that map the
1575 * same virtual address using different page sizes. This is the recommended
1576 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1577 * machine check exception for a TLB state that is improperly diagnosed as a
1581 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1583 struct pde_action act;
1584 cpuset_t active, other_cpus;
1588 cpuid = PCPU_GET(cpuid);
1589 other_cpus = all_cpus;
1590 CPU_CLR(cpuid, &other_cpus);
1591 if (pmap == kernel_pmap || pmap->pm_type == PT_EPT)
1594 active = pmap->pm_active;
1595 CPU_AND_ATOMIC(&pmap->pm_save, &active);
1597 if (CPU_OVERLAP(&active, &other_cpus)) {
1599 act.invalidate = active;
1603 act.newpde = newpde;
1604 CPU_SET(cpuid, &active);
1605 smp_rendezvous_cpus(active,
1606 smp_no_rendevous_barrier, pmap_update_pde_action,
1607 pmap_update_pde_teardown, &act);
1609 pmap_update_pde_store(pmap, pde, newpde);
1610 if (CPU_ISSET(cpuid, &active))
1611 pmap_update_pde_invalidate(pmap, va, newpde);
1617 * Normal, non-SMP, invalidation functions.
1618 * We inline these within pmap.c for speed.
1621 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1624 switch (pmap->pm_type) {
1626 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1633 panic("pmap_invalidate_page: unknown type: %d", pmap->pm_type);
1638 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1642 switch (pmap->pm_type) {
1644 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1645 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1652 panic("pmap_invalidate_range: unknown type: %d", pmap->pm_type);
1657 pmap_invalidate_all(pmap_t pmap)
1660 switch (pmap->pm_type) {
1662 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1669 panic("pmap_invalidate_all: unknown type %d", pmap->pm_type);
1674 pmap_invalidate_cache(void)
1681 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1684 pmap_update_pde_store(pmap, pde, newpde);
1685 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1686 pmap_update_pde_invalidate(pmap, va, newpde);
1688 CPU_ZERO(&pmap->pm_save);
1692 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1695 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1698 KASSERT((sva & PAGE_MASK) == 0,
1699 ("pmap_invalidate_cache_range: sva not page-aligned"));
1700 KASSERT((eva & PAGE_MASK) == 0,
1701 ("pmap_invalidate_cache_range: eva not page-aligned"));
1703 if (cpu_feature & CPUID_SS)
1704 ; /* If "Self Snoop" is supported, do nothing. */
1705 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1706 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1709 * XXX: Some CPUs fault, hang, or trash the local APIC
1710 * registers if we use CLFLUSH on the local APIC
1711 * range. The local APIC is always uncached, so we
1712 * don't need to flush for that range anyway.
1714 if (pmap_kextract(sva) == lapic_paddr)
1718 * Otherwise, do per-cache line flush. Use the mfence
1719 * instruction to insure that previous stores are
1720 * included in the write-back. The processor
1721 * propagates flush to other processors in the cache
1725 for (; sva < eva; sva += cpu_clflush_line_size)
1731 * No targeted cache flush methods are supported by CPU,
1732 * or the supplied range is bigger than 2MB.
1733 * Globally invalidate cache.
1735 pmap_invalidate_cache();
1740 * Remove the specified set of pages from the data and instruction caches.
1742 * In contrast to pmap_invalidate_cache_range(), this function does not
1743 * rely on the CPU's self-snoop feature, because it is intended for use
1744 * when moving pages into a different cache domain.
1747 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1749 vm_offset_t daddr, eva;
1752 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1753 (cpu_feature & CPUID_CLFSH) == 0)
1754 pmap_invalidate_cache();
1757 for (i = 0; i < count; i++) {
1758 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1759 eva = daddr + PAGE_SIZE;
1760 for (; daddr < eva; daddr += cpu_clflush_line_size)
1768 * Are we current address space or kernel?
1771 pmap_is_current(pmap_t pmap)
1773 return (pmap == kernel_pmap ||
1774 (pmap->pm_pml4[PML4PML4I] & PG_FRAME) == (PML4pml4e[0] & PG_FRAME));
1778 * Routine: pmap_extract
1780 * Extract the physical page address associated
1781 * with the given map/virtual_address pair.
1784 pmap_extract(pmap_t pmap, vm_offset_t va)
1788 pt_entry_t *pte, PG_V;
1792 PG_V = pmap_valid_bit(pmap);
1794 pdpe = pmap_pdpe(pmap, va);
1795 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1796 if ((*pdpe & PG_PS) != 0)
1797 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1799 pde = pmap_pdpe_to_pde(pdpe, va);
1800 if ((*pde & PG_V) != 0) {
1801 if ((*pde & PG_PS) != 0) {
1802 pa = (*pde & PG_PS_FRAME) |
1805 pte = pmap_pde_to_pte(pde, va);
1806 pa = (*pte & PG_FRAME) |
1817 * Routine: pmap_extract_and_hold
1819 * Atomically extract and hold the physical page
1820 * with the given pmap and virtual address pair
1821 * if that mapping permits the given protection.
1824 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1826 pd_entry_t pde, *pdep;
1827 pt_entry_t pte, PG_RW, PG_V;
1833 PG_RW = pmap_rw_bit(pmap);
1834 PG_V = pmap_valid_bit(pmap);
1837 pdep = pmap_pde(pmap, va);
1838 if (pdep != NULL && (pde = *pdep)) {
1840 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1841 if (vm_page_pa_tryrelock(pmap, (pde &
1842 PG_PS_FRAME) | (va & PDRMASK), &pa))
1844 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1849 pte = *pmap_pde_to_pte(pdep, va);
1851 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1852 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1855 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1866 pmap_kextract(vm_offset_t va)
1871 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1872 pa = DMAP_TO_PHYS(va);
1876 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1879 * Beware of a concurrent promotion that changes the
1880 * PDE at this point! For example, vtopte() must not
1881 * be used to access the PTE because it would use the
1882 * new PDE. It is, however, safe to use the old PDE
1883 * because the page table page is preserved by the
1886 pa = *pmap_pde_to_pte(&pde, va);
1887 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1893 /***************************************************
1894 * Low level mapping routines.....
1895 ***************************************************/
1898 * Add a wired page to the kva.
1899 * Note: not SMP coherent.
1902 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1907 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
1910 static __inline void
1911 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1917 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
1918 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
1922 * Remove a page from the kernel pagetables.
1923 * Note: not SMP coherent.
1926 pmap_kremove(vm_offset_t va)
1935 * Used to map a range of physical addresses into kernel
1936 * virtual address space.
1938 * The value passed in '*virt' is a suggested virtual address for
1939 * the mapping. Architectures which can support a direct-mapped
1940 * physical to virtual region can return the appropriate address
1941 * within that region, leaving '*virt' unchanged. Other
1942 * architectures should map the pages starting at '*virt' and
1943 * update '*virt' with the first usable address after the mapped
1947 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1949 return PHYS_TO_DMAP(start);
1954 * Add a list of wired pages to the kva
1955 * this routine is only used for temporary
1956 * kernel mappings that do not need to have
1957 * page modification or references recorded.
1958 * Note that old mappings are simply written
1959 * over. The page *must* be wired.
1960 * Note: SMP coherent. Uses a ranged shootdown IPI.
1963 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1965 pt_entry_t *endpte, oldpte, pa, *pte;
1971 endpte = pte + count;
1972 while (pte < endpte) {
1974 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
1975 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
1976 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
1978 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
1982 if (__predict_false((oldpte & X86_PG_V) != 0))
1983 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1988 * This routine tears out page mappings from the
1989 * kernel -- it is meant only for temporary mappings.
1990 * Note: SMP coherent. Uses a ranged shootdown IPI.
1993 pmap_qremove(vm_offset_t sva, int count)
1998 while (count-- > 0) {
1999 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2003 pmap_invalidate_range(kernel_pmap, sva, va);
2006 /***************************************************
2007 * Page table page management routines.....
2008 ***************************************************/
2009 static __inline void
2010 pmap_free_zero_pages(struct spglist *free)
2014 while ((m = SLIST_FIRST(free)) != NULL) {
2015 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2016 /* Preserve the page's PG_ZERO setting. */
2017 vm_page_free_toq(m);
2022 * Schedule the specified unused page table page to be freed. Specifically,
2023 * add the page to the specified list of pages that will be released to the
2024 * physical memory manager after the TLB has been updated.
2026 static __inline void
2027 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2028 boolean_t set_PG_ZERO)
2032 m->flags |= PG_ZERO;
2034 m->flags &= ~PG_ZERO;
2035 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2039 * Inserts the specified page table page into the specified pmap's collection
2040 * of idle page table pages. Each of a pmap's page table pages is responsible
2041 * for mapping a distinct range of virtual addresses. The pmap's collection is
2042 * ordered by this virtual address range.
2045 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2048 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2049 return (vm_radix_insert(&pmap->pm_root, mpte));
2053 * Looks for a page table page mapping the specified virtual address in the
2054 * specified pmap's collection of idle page table pages. Returns NULL if there
2055 * is no page table page corresponding to the specified virtual address.
2057 static __inline vm_page_t
2058 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
2061 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2062 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
2066 * Removes the specified page table page from the specified pmap's collection
2067 * of idle page table pages. The specified page table page must be a member of
2068 * the pmap's collection.
2070 static __inline void
2071 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
2074 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2075 vm_radix_remove(&pmap->pm_root, mpte->pindex);
2079 * Decrements a page table page's wire count, which is used to record the
2080 * number of valid page table entries within the page. If the wire count
2081 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2082 * page table page was unmapped and FALSE otherwise.
2084 static inline boolean_t
2085 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2089 if (m->wire_count == 0) {
2090 _pmap_unwire_ptp(pmap, va, m, free);
2097 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2100 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2102 * unmap the page table page
2104 if (m->pindex >= (NUPDE + NUPDPE)) {
2107 pml4 = pmap_pml4e(pmap, va);
2109 } else if (m->pindex >= NUPDE) {
2112 pdp = pmap_pdpe(pmap, va);
2117 pd = pmap_pde(pmap, va);
2120 pmap_resident_count_dec(pmap, 1);
2121 if (m->pindex < NUPDE) {
2122 /* We just released a PT, unhold the matching PD */
2125 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2126 pmap_unwire_ptp(pmap, va, pdpg, free);
2128 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2129 /* We just released a PD, unhold the matching PDP */
2132 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2133 pmap_unwire_ptp(pmap, va, pdppg, free);
2137 * This is a release store so that the ordinary store unmapping
2138 * the page table page is globally performed before TLB shoot-
2141 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
2144 * Put page on a list so that it is released after
2145 * *ALL* TLB shootdown is done
2147 pmap_add_delayed_free_list(m, free, TRUE);
2151 * After removing a page table entry, this routine is used to
2152 * conditionally free the page, and manage the hold/wire counts.
2155 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2156 struct spglist *free)
2160 if (va >= VM_MAXUSER_ADDRESS)
2162 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2163 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2164 return (pmap_unwire_ptp(pmap, va, mpte, free));
2168 pmap_pinit0(pmap_t pmap)
2171 PMAP_LOCK_INIT(pmap);
2172 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2173 pmap->pm_cr3 = KPML4phys;
2174 pmap->pm_root.rt_root = 0;
2175 CPU_ZERO(&pmap->pm_active);
2176 CPU_ZERO(&pmap->pm_save);
2177 PCPU_SET(curpmap, pmap);
2178 TAILQ_INIT(&pmap->pm_pvchunk);
2179 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2180 pmap->pm_pcid = pmap_pcid_enabled ? 0 : -1;
2181 pmap->pm_flags = pmap_flags;
2185 * Initialize a preallocated and zeroed pmap structure,
2186 * such as one in a vmspace structure.
2189 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2192 vm_paddr_t pml4phys;
2196 * allocate the page directory page
2198 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2199 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2202 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2203 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2205 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2207 if ((pml4pg->flags & PG_ZERO) == 0)
2208 pagezero(pmap->pm_pml4);
2211 * Do not install the host kernel mappings in the nested page
2212 * tables. These mappings are meaningless in the guest physical
2215 if ((pmap->pm_type = pm_type) == PT_X86) {
2216 pmap->pm_cr3 = pml4phys;
2218 /* Wire in kernel global address entries. */
2219 for (i = 0; i < NKPML4E; i++) {
2220 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
2221 X86_PG_RW | X86_PG_V | PG_U;
2223 for (i = 0; i < ndmpdpphys; i++) {
2224 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
2225 X86_PG_RW | X86_PG_V | PG_U;
2228 /* install self-referential address mapping entry(s) */
2229 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
2230 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2232 if (pmap_pcid_enabled) {
2233 pmap->pm_pcid = alloc_unr(&pcid_unr);
2234 if (pmap->pm_pcid != -1)
2235 pmap->pm_cr3 |= pmap->pm_pcid;
2239 pmap->pm_root.rt_root = 0;
2240 CPU_ZERO(&pmap->pm_active);
2241 TAILQ_INIT(&pmap->pm_pvchunk);
2242 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2243 pmap->pm_flags = flags;
2244 pmap->pm_eptgen = 0;
2245 CPU_ZERO(&pmap->pm_save);
2251 pmap_pinit(pmap_t pmap)
2254 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2258 * This routine is called if the desired page table page does not exist.
2260 * If page table page allocation fails, this routine may sleep before
2261 * returning NULL. It sleeps only if a lock pointer was given.
2263 * Note: If a page allocation fails at page table level two or three,
2264 * one or two pages may be held during the wait, only to be released
2265 * afterwards. This conservative approach is easily argued to avoid
2269 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2271 vm_page_t m, pdppg, pdpg;
2272 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2274 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2276 PG_A = pmap_accessed_bit(pmap);
2277 PG_M = pmap_modified_bit(pmap);
2278 PG_V = pmap_valid_bit(pmap);
2279 PG_RW = pmap_rw_bit(pmap);
2282 * Allocate a page table page.
2284 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2285 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2286 if (lockp != NULL) {
2287 RELEASE_PV_LIST_LOCK(lockp);
2289 rw_runlock(&pvh_global_lock);
2291 rw_rlock(&pvh_global_lock);
2296 * Indicate the need to retry. While waiting, the page table
2297 * page may have been allocated.
2301 if ((m->flags & PG_ZERO) == 0)
2305 * Map the pagetable page into the process address space, if
2306 * it isn't already there.
2309 if (ptepindex >= (NUPDE + NUPDPE)) {
2311 vm_pindex_t pml4index;
2313 /* Wire up a new PDPE page */
2314 pml4index = ptepindex - (NUPDE + NUPDPE);
2315 pml4 = &pmap->pm_pml4[pml4index];
2316 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2318 } else if (ptepindex >= NUPDE) {
2319 vm_pindex_t pml4index;
2320 vm_pindex_t pdpindex;
2324 /* Wire up a new PDE page */
2325 pdpindex = ptepindex - NUPDE;
2326 pml4index = pdpindex >> NPML4EPGSHIFT;
2328 pml4 = &pmap->pm_pml4[pml4index];
2329 if ((*pml4 & PG_V) == 0) {
2330 /* Have to allocate a new pdp, recurse */
2331 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2334 atomic_subtract_int(&cnt.v_wire_count, 1);
2335 vm_page_free_zero(m);
2339 /* Add reference to pdp page */
2340 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2341 pdppg->wire_count++;
2343 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2345 /* Now find the pdp page */
2346 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2347 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2350 vm_pindex_t pml4index;
2351 vm_pindex_t pdpindex;
2356 /* Wire up a new PTE page */
2357 pdpindex = ptepindex >> NPDPEPGSHIFT;
2358 pml4index = pdpindex >> NPML4EPGSHIFT;
2360 /* First, find the pdp and check that its valid. */
2361 pml4 = &pmap->pm_pml4[pml4index];
2362 if ((*pml4 & PG_V) == 0) {
2363 /* Have to allocate a new pd, recurse */
2364 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2367 atomic_subtract_int(&cnt.v_wire_count, 1);
2368 vm_page_free_zero(m);
2371 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2372 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2374 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2375 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2376 if ((*pdp & PG_V) == 0) {
2377 /* Have to allocate a new pd, recurse */
2378 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2381 atomic_subtract_int(&cnt.v_wire_count,
2383 vm_page_free_zero(m);
2387 /* Add reference to the pd page */
2388 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2392 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2394 /* Now we know where the page directory page is */
2395 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2396 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2399 pmap_resident_count_inc(pmap, 1);
2405 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2407 vm_pindex_t pdpindex, ptepindex;
2408 pdp_entry_t *pdpe, PG_V;
2411 PG_V = pmap_valid_bit(pmap);
2414 pdpe = pmap_pdpe(pmap, va);
2415 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2416 /* Add a reference to the pd page. */
2417 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2420 /* Allocate a pd page. */
2421 ptepindex = pmap_pde_pindex(va);
2422 pdpindex = ptepindex >> NPDPEPGSHIFT;
2423 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2424 if (pdpg == NULL && lockp != NULL)
2431 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2433 vm_pindex_t ptepindex;
2434 pd_entry_t *pd, PG_V;
2437 PG_V = pmap_valid_bit(pmap);
2440 * Calculate pagetable page index
2442 ptepindex = pmap_pde_pindex(va);
2445 * Get the page directory entry
2447 pd = pmap_pde(pmap, va);
2450 * This supports switching from a 2MB page to a
2453 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2454 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2456 * Invalidation of the 2MB page mapping may have caused
2457 * the deallocation of the underlying PD page.
2464 * If the page table page is mapped, we just increment the
2465 * hold count, and activate it.
2467 if (pd != NULL && (*pd & PG_V) != 0) {
2468 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2472 * Here if the pte page isn't mapped, or if it has been
2475 m = _pmap_allocpte(pmap, ptepindex, lockp);
2476 if (m == NULL && lockp != NULL)
2483 /***************************************************
2484 * Pmap allocation/deallocation routines.
2485 ***************************************************/
2488 * Release any resources held by the given physical map.
2489 * Called when a pmap initialized by pmap_pinit is being released.
2490 * Should only be called if the map contains no valid mappings.
2493 pmap_release(pmap_t pmap)
2498 KASSERT(pmap->pm_stats.resident_count == 0,
2499 ("pmap_release: pmap resident count %ld != 0",
2500 pmap->pm_stats.resident_count));
2501 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2502 ("pmap_release: pmap has reserved page table page(s)"));
2504 if (pmap_pcid_enabled) {
2506 * Invalidate any left TLB entries, to allow the reuse
2509 pmap_invalidate_all(pmap);
2512 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2514 for (i = 0; i < NKPML4E; i++) /* KVA */
2515 pmap->pm_pml4[KPML4BASE + i] = 0;
2516 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2517 pmap->pm_pml4[DMPML4I + i] = 0;
2518 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2521 atomic_subtract_int(&cnt.v_wire_count, 1);
2522 vm_page_free_zero(m);
2523 if (pmap->pm_pcid != -1)
2524 free_unr(&pcid_unr, pmap->pm_pcid);
2528 kvm_size(SYSCTL_HANDLER_ARGS)
2530 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2532 return sysctl_handle_long(oidp, &ksize, 0, req);
2534 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2535 0, 0, kvm_size, "LU", "Size of KVM");
2538 kvm_free(SYSCTL_HANDLER_ARGS)
2540 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2542 return sysctl_handle_long(oidp, &kfree, 0, req);
2544 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2545 0, 0, kvm_free, "LU", "Amount of KVM free");
2548 * grow the number of kernel page table entries, if needed
2551 pmap_growkernel(vm_offset_t addr)
2555 pd_entry_t *pde, newpdir;
2558 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2561 * Return if "addr" is within the range of kernel page table pages
2562 * that were preallocated during pmap bootstrap. Moreover, leave
2563 * "kernel_vm_end" and the kernel page table as they were.
2565 * The correctness of this action is based on the following
2566 * argument: vm_map_findspace() allocates contiguous ranges of the
2567 * kernel virtual address space. It calls this function if a range
2568 * ends after "kernel_vm_end". If the kernel is mapped between
2569 * "kernel_vm_end" and "addr", then the range cannot begin at
2570 * "kernel_vm_end". In fact, its beginning address cannot be less
2571 * than the kernel. Thus, there is no immediate need to allocate
2572 * any new kernel page table pages between "kernel_vm_end" and
2575 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2578 addr = roundup2(addr, NBPDR);
2579 if (addr - 1 >= kernel_map->max_offset)
2580 addr = kernel_map->max_offset;
2581 while (kernel_vm_end < addr) {
2582 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2583 if ((*pdpe & X86_PG_V) == 0) {
2584 /* We need a new PDP entry */
2585 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2586 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2587 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2589 panic("pmap_growkernel: no memory to grow kernel");
2590 if ((nkpg->flags & PG_ZERO) == 0)
2591 pmap_zero_page(nkpg);
2592 paddr = VM_PAGE_TO_PHYS(nkpg);
2593 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2594 X86_PG_A | X86_PG_M);
2595 continue; /* try again */
2597 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2598 if ((*pde & X86_PG_V) != 0) {
2599 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2600 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2601 kernel_vm_end = kernel_map->max_offset;
2607 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2608 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2611 panic("pmap_growkernel: no memory to grow kernel");
2612 if ((nkpg->flags & PG_ZERO) == 0)
2613 pmap_zero_page(nkpg);
2614 paddr = VM_PAGE_TO_PHYS(nkpg);
2615 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2616 pde_store(pde, newpdir);
2618 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2619 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2620 kernel_vm_end = kernel_map->max_offset;
2627 /***************************************************
2628 * page management routines.
2629 ***************************************************/
2631 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2632 CTASSERT(_NPCM == 3);
2633 CTASSERT(_NPCPV == 168);
2635 static __inline struct pv_chunk *
2636 pv_to_chunk(pv_entry_t pv)
2639 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2642 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2644 #define PC_FREE0 0xfffffffffffffffful
2645 #define PC_FREE1 0xfffffffffffffffful
2646 #define PC_FREE2 0x000000fffffffffful
2648 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2651 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2653 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2654 "Current number of pv entry chunks");
2655 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2656 "Current number of pv entry chunks allocated");
2657 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2658 "Current number of pv entry chunks frees");
2659 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2660 "Number of times tried to get a chunk page but failed.");
2662 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2663 static int pv_entry_spare;
2665 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2666 "Current number of pv entry frees");
2667 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2668 "Current number of pv entry allocs");
2669 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2670 "Current number of pv entries");
2671 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2672 "Current number of spare pv entries");
2676 * We are in a serious low memory condition. Resort to
2677 * drastic measures to free some pages so we can allocate
2678 * another pv entry chunk.
2680 * Returns NULL if PV entries were reclaimed from the specified pmap.
2682 * We do not, however, unmap 2mpages because subsequent accesses will
2683 * allocate per-page pv entries until repromotion occurs, thereby
2684 * exacerbating the shortage of free pv entries.
2687 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2689 struct pch new_tail;
2690 struct pv_chunk *pc;
2691 struct md_page *pvh;
2694 pt_entry_t *pte, tpte;
2695 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2699 struct spglist free;
2701 int bit, field, freed;
2703 rw_assert(&pvh_global_lock, RA_LOCKED);
2704 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2705 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2708 PG_G = PG_A = PG_M = PG_RW = 0;
2710 TAILQ_INIT(&new_tail);
2711 mtx_lock(&pv_chunks_mutex);
2712 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2713 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2714 mtx_unlock(&pv_chunks_mutex);
2715 if (pmap != pc->pc_pmap) {
2717 pmap_invalidate_all(pmap);
2718 if (pmap != locked_pmap)
2722 /* Avoid deadlock and lock recursion. */
2723 if (pmap > locked_pmap) {
2724 RELEASE_PV_LIST_LOCK(lockp);
2726 } else if (pmap != locked_pmap &&
2727 !PMAP_TRYLOCK(pmap)) {
2729 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2730 mtx_lock(&pv_chunks_mutex);
2733 PG_G = pmap_global_bit(pmap);
2734 PG_A = pmap_accessed_bit(pmap);
2735 PG_M = pmap_modified_bit(pmap);
2736 PG_RW = pmap_rw_bit(pmap);
2740 * Destroy every non-wired, 4 KB page mapping in the chunk.
2743 for (field = 0; field < _NPCM; field++) {
2744 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2745 inuse != 0; inuse &= ~(1UL << bit)) {
2747 pv = &pc->pc_pventry[field * 64 + bit];
2749 pde = pmap_pde(pmap, va);
2750 if ((*pde & PG_PS) != 0)
2752 pte = pmap_pde_to_pte(pde, va);
2753 if ((*pte & PG_W) != 0)
2755 tpte = pte_load_clear(pte);
2756 if ((tpte & PG_G) != 0)
2757 pmap_invalidate_page(pmap, va);
2758 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2759 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2761 if ((tpte & PG_A) != 0)
2762 vm_page_aflag_set(m, PGA_REFERENCED);
2763 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2764 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2766 if (TAILQ_EMPTY(&m->md.pv_list) &&
2767 (m->flags & PG_FICTITIOUS) == 0) {
2768 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2769 if (TAILQ_EMPTY(&pvh->pv_list)) {
2770 vm_page_aflag_clear(m,
2774 pc->pc_map[field] |= 1UL << bit;
2775 pmap_unuse_pt(pmap, va, *pde, &free);
2780 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2781 mtx_lock(&pv_chunks_mutex);
2784 /* Every freed mapping is for a 4 KB page. */
2785 pmap_resident_count_dec(pmap, freed);
2786 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2787 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2788 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2789 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2790 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2791 pc->pc_map[2] == PC_FREE2) {
2792 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2793 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2794 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2795 /* Entire chunk is free; return it. */
2796 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2797 dump_drop_page(m_pc->phys_addr);
2798 mtx_lock(&pv_chunks_mutex);
2801 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2802 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2803 mtx_lock(&pv_chunks_mutex);
2804 /* One freed pv entry in locked_pmap is sufficient. */
2805 if (pmap == locked_pmap)
2808 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2809 mtx_unlock(&pv_chunks_mutex);
2811 pmap_invalidate_all(pmap);
2812 if (pmap != locked_pmap)
2815 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2816 m_pc = SLIST_FIRST(&free);
2817 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2818 /* Recycle a freed page table page. */
2819 m_pc->wire_count = 1;
2820 atomic_add_int(&cnt.v_wire_count, 1);
2822 pmap_free_zero_pages(&free);
2827 * free the pv_entry back to the free list
2830 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2832 struct pv_chunk *pc;
2833 int idx, field, bit;
2835 rw_assert(&pvh_global_lock, RA_LOCKED);
2836 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2837 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2838 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2839 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2840 pc = pv_to_chunk(pv);
2841 idx = pv - &pc->pc_pventry[0];
2844 pc->pc_map[field] |= 1ul << bit;
2845 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2846 pc->pc_map[2] != PC_FREE2) {
2847 /* 98% of the time, pc is already at the head of the list. */
2848 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2849 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2850 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2854 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2859 free_pv_chunk(struct pv_chunk *pc)
2863 mtx_lock(&pv_chunks_mutex);
2864 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2865 mtx_unlock(&pv_chunks_mutex);
2866 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2867 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2868 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2869 /* entire chunk is free, return it */
2870 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2871 dump_drop_page(m->phys_addr);
2872 vm_page_unwire(m, 0);
2877 * Returns a new PV entry, allocating a new PV chunk from the system when
2878 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2879 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2882 * The given PV list lock may be released.
2885 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2889 struct pv_chunk *pc;
2892 rw_assert(&pvh_global_lock, RA_LOCKED);
2893 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2894 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2896 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2898 for (field = 0; field < _NPCM; field++) {
2899 if (pc->pc_map[field]) {
2900 bit = bsfq(pc->pc_map[field]);
2904 if (field < _NPCM) {
2905 pv = &pc->pc_pventry[field * 64 + bit];
2906 pc->pc_map[field] &= ~(1ul << bit);
2907 /* If this was the last item, move it to tail */
2908 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2909 pc->pc_map[2] == 0) {
2910 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2911 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2914 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2915 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2919 /* No free items, allocate another chunk */
2920 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2923 if (lockp == NULL) {
2924 PV_STAT(pc_chunk_tryfail++);
2927 m = reclaim_pv_chunk(pmap, lockp);
2931 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2932 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2933 dump_add_page(m->phys_addr);
2934 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2936 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2937 pc->pc_map[1] = PC_FREE1;
2938 pc->pc_map[2] = PC_FREE2;
2939 mtx_lock(&pv_chunks_mutex);
2940 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2941 mtx_unlock(&pv_chunks_mutex);
2942 pv = &pc->pc_pventry[0];
2943 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2944 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2945 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2950 * Returns the number of one bits within the given PV chunk map element.
2953 popcnt_pc_map_elem(uint64_t elem)
2958 * This simple method of counting the one bits performs well because
2959 * the given element typically contains more zero bits than one bits.
2962 for (; elem != 0; elem &= elem - 1)
2968 * Ensure that the number of spare PV entries in the specified pmap meets or
2969 * exceeds the given count, "needed".
2971 * The given PV list lock may be released.
2974 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2976 struct pch new_tail;
2977 struct pv_chunk *pc;
2981 rw_assert(&pvh_global_lock, RA_LOCKED);
2982 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2983 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2986 * Newly allocated PV chunks must be stored in a private list until
2987 * the required number of PV chunks have been allocated. Otherwise,
2988 * reclaim_pv_chunk() could recycle one of these chunks. In
2989 * contrast, these chunks must be added to the pmap upon allocation.
2991 TAILQ_INIT(&new_tail);
2994 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2995 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
2996 free = popcnt_pc_map_elem(pc->pc_map[0]);
2997 free += popcnt_pc_map_elem(pc->pc_map[1]);
2998 free += popcnt_pc_map_elem(pc->pc_map[2]);
3000 free = popcntq(pc->pc_map[0]);
3001 free += popcntq(pc->pc_map[1]);
3002 free += popcntq(pc->pc_map[2]);
3007 if (avail >= needed)
3010 for (; avail < needed; avail += _NPCPV) {
3011 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3014 m = reclaim_pv_chunk(pmap, lockp);
3018 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3019 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3020 dump_add_page(m->phys_addr);
3021 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3023 pc->pc_map[0] = PC_FREE0;
3024 pc->pc_map[1] = PC_FREE1;
3025 pc->pc_map[2] = PC_FREE2;
3026 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3027 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3028 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3030 if (!TAILQ_EMPTY(&new_tail)) {
3031 mtx_lock(&pv_chunks_mutex);
3032 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3033 mtx_unlock(&pv_chunks_mutex);
3038 * First find and then remove the pv entry for the specified pmap and virtual
3039 * address from the specified pv list. Returns the pv entry if found and NULL
3040 * otherwise. This operation can be performed on pv lists for either 4KB or
3041 * 2MB page mappings.
3043 static __inline pv_entry_t
3044 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3048 rw_assert(&pvh_global_lock, RA_LOCKED);
3049 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3050 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3051 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3060 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3061 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3062 * entries for each of the 4KB page mappings.
3065 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3066 struct rwlock **lockp)
3068 struct md_page *pvh;
3069 struct pv_chunk *pc;
3071 vm_offset_t va_last;
3075 rw_assert(&pvh_global_lock, RA_LOCKED);
3076 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3077 KASSERT((pa & PDRMASK) == 0,
3078 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3079 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3082 * Transfer the 2mpage's pv entry for this mapping to the first
3083 * page's pv list. Once this transfer begins, the pv list lock
3084 * must not be released until the last pv entry is reinstantiated.
3086 pvh = pa_to_pvh(pa);
3087 va = trunc_2mpage(va);
3088 pv = pmap_pvh_remove(pvh, pmap, va);
3089 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3090 m = PHYS_TO_VM_PAGE(pa);
3091 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3093 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3094 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3095 va_last = va + NBPDR - PAGE_SIZE;
3097 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3098 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3099 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3100 for (field = 0; field < _NPCM; field++) {
3101 while (pc->pc_map[field]) {
3102 bit = bsfq(pc->pc_map[field]);
3103 pc->pc_map[field] &= ~(1ul << bit);
3104 pv = &pc->pc_pventry[field * 64 + bit];
3108 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3109 ("pmap_pv_demote_pde: page %p is not managed", m));
3110 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3116 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3117 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3120 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3121 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3122 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3124 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3125 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3129 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3130 * replace the many pv entries for the 4KB page mappings by a single pv entry
3131 * for the 2MB page mapping.
3134 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3135 struct rwlock **lockp)
3137 struct md_page *pvh;
3139 vm_offset_t va_last;
3142 rw_assert(&pvh_global_lock, RA_LOCKED);
3143 KASSERT((pa & PDRMASK) == 0,
3144 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3145 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3148 * Transfer the first page's pv entry for this mapping to the 2mpage's
3149 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3150 * a transfer avoids the possibility that get_pv_entry() calls
3151 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3152 * mappings that is being promoted.
3154 m = PHYS_TO_VM_PAGE(pa);
3155 va = trunc_2mpage(va);
3156 pv = pmap_pvh_remove(&m->md, pmap, va);
3157 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3158 pvh = pa_to_pvh(pa);
3159 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3161 /* Free the remaining NPTEPG - 1 pv entries. */
3162 va_last = va + NBPDR - PAGE_SIZE;
3166 pmap_pvh_free(&m->md, pmap, va);
3167 } while (va < va_last);
3171 * First find and then destroy the pv entry for the specified pmap and virtual
3172 * address. This operation can be performed on pv lists for either 4KB or 2MB
3176 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3180 pv = pmap_pvh_remove(pvh, pmap, va);
3181 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3182 free_pv_entry(pmap, pv);
3186 * Conditionally create the PV entry for a 4KB page mapping if the required
3187 * memory can be allocated without resorting to reclamation.
3190 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3191 struct rwlock **lockp)
3195 rw_assert(&pvh_global_lock, RA_LOCKED);
3196 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3197 /* Pass NULL instead of the lock pointer to disable reclamation. */
3198 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3200 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3201 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3209 * Conditionally create the PV entry for a 2MB page mapping if the required
3210 * memory can be allocated without resorting to reclamation.
3213 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3214 struct rwlock **lockp)
3216 struct md_page *pvh;
3219 rw_assert(&pvh_global_lock, RA_LOCKED);
3220 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3221 /* Pass NULL instead of the lock pointer to disable reclamation. */
3222 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3224 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3225 pvh = pa_to_pvh(pa);
3226 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3234 * Fills a page table page with mappings to consecutive physical pages.
3237 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3241 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3243 newpte += PAGE_SIZE;
3248 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3249 * mapping is invalidated.
3252 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3254 struct rwlock *lock;
3258 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3265 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3266 struct rwlock **lockp)
3268 pd_entry_t newpde, oldpde;
3269 pt_entry_t *firstpte, newpte;
3270 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3273 struct spglist free;
3276 PG_G = pmap_global_bit(pmap);
3277 PG_A = pmap_accessed_bit(pmap);
3278 PG_M = pmap_modified_bit(pmap);
3279 PG_RW = pmap_rw_bit(pmap);
3280 PG_V = pmap_valid_bit(pmap);
3281 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3283 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3285 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3286 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3287 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
3289 pmap_remove_pt_page(pmap, mpte);
3291 KASSERT((oldpde & PG_W) == 0,
3292 ("pmap_demote_pde: page table page for a wired mapping"
3296 * Invalidate the 2MB page mapping and return "failure" if the
3297 * mapping was never accessed or the allocation of the new
3298 * page table page fails. If the 2MB page mapping belongs to
3299 * the direct map region of the kernel's address space, then
3300 * the page allocation request specifies the highest possible
3301 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3302 * normal. Page table pages are preallocated for every other
3303 * part of the kernel address space, so the direct map region
3304 * is the only part of the kernel address space that must be
3307 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3308 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3309 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3310 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3312 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
3314 pmap_invalidate_page(pmap, trunc_2mpage(va));
3315 pmap_free_zero_pages(&free);
3316 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3317 " in pmap %p", va, pmap);
3320 if (va < VM_MAXUSER_ADDRESS)
3321 pmap_resident_count_inc(pmap, 1);
3323 mptepa = VM_PAGE_TO_PHYS(mpte);
3324 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3325 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3326 KASSERT((oldpde & PG_A) != 0,
3327 ("pmap_demote_pde: oldpde is missing PG_A"));
3328 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3329 ("pmap_demote_pde: oldpde is missing PG_M"));
3330 newpte = oldpde & ~PG_PS;
3331 newpte = pmap_swap_pat(pmap, newpte);
3334 * If the page table page is new, initialize it.
3336 if (mpte->wire_count == 1) {
3337 mpte->wire_count = NPTEPG;
3338 pmap_fill_ptp(firstpte, newpte);
3340 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3341 ("pmap_demote_pde: firstpte and newpte map different physical"
3345 * If the mapping has changed attributes, update the page table
3348 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3349 pmap_fill_ptp(firstpte, newpte);
3352 * The spare PV entries must be reserved prior to demoting the
3353 * mapping, that is, prior to changing the PDE. Otherwise, the state
3354 * of the PDE and the PV lists will be inconsistent, which can result
3355 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3356 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3357 * PV entry for the 2MB page mapping that is being demoted.
3359 if ((oldpde & PG_MANAGED) != 0)
3360 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3363 * Demote the mapping. This pmap is locked. The old PDE has
3364 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3365 * set. Thus, there is no danger of a race with another
3366 * processor changing the setting of PG_A and/or PG_M between
3367 * the read above and the store below.
3369 if (workaround_erratum383)
3370 pmap_update_pde(pmap, va, pde, newpde);
3372 pde_store(pde, newpde);
3375 * Invalidate a stale recursive mapping of the page table page.
3377 if (va >= VM_MAXUSER_ADDRESS)
3378 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3381 * Demote the PV entry.
3383 if ((oldpde & PG_MANAGED) != 0)
3384 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3386 atomic_add_long(&pmap_pde_demotions, 1);
3387 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3388 " in pmap %p", va, pmap);
3393 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3396 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3402 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3403 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3404 mpte = pmap_lookup_pt_page(pmap, va);
3406 panic("pmap_remove_kernel_pde: Missing pt page.");
3408 pmap_remove_pt_page(pmap, mpte);
3409 mptepa = VM_PAGE_TO_PHYS(mpte);
3410 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3413 * Initialize the page table page.
3415 pagezero((void *)PHYS_TO_DMAP(mptepa));
3418 * Demote the mapping.
3420 if (workaround_erratum383)
3421 pmap_update_pde(pmap, va, pde, newpde);
3423 pde_store(pde, newpde);
3426 * Invalidate a stale recursive mapping of the page table page.
3428 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3432 * pmap_remove_pde: do the things to unmap a superpage in a process
3435 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3436 struct spglist *free, struct rwlock **lockp)
3438 struct md_page *pvh;
3440 vm_offset_t eva, va;
3442 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3444 PG_G = pmap_global_bit(pmap);
3445 PG_A = pmap_accessed_bit(pmap);
3446 PG_M = pmap_modified_bit(pmap);
3447 PG_RW = pmap_rw_bit(pmap);
3449 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3450 KASSERT((sva & PDRMASK) == 0,
3451 ("pmap_remove_pde: sva is not 2mpage aligned"));
3452 oldpde = pte_load_clear(pdq);
3454 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3457 * Machines that don't support invlpg, also don't support
3461 pmap_invalidate_page(kernel_pmap, sva);
3462 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3463 if (oldpde & PG_MANAGED) {
3464 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3465 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3466 pmap_pvh_free(pvh, pmap, sva);
3468 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3469 va < eva; va += PAGE_SIZE, m++) {
3470 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3473 vm_page_aflag_set(m, PGA_REFERENCED);
3474 if (TAILQ_EMPTY(&m->md.pv_list) &&
3475 TAILQ_EMPTY(&pvh->pv_list))
3476 vm_page_aflag_clear(m, PGA_WRITEABLE);
3479 if (pmap == kernel_pmap) {
3480 pmap_remove_kernel_pde(pmap, pdq, sva);
3482 mpte = pmap_lookup_pt_page(pmap, sva);
3484 pmap_remove_pt_page(pmap, mpte);
3485 pmap_resident_count_dec(pmap, 1);
3486 KASSERT(mpte->wire_count == NPTEPG,
3487 ("pmap_remove_pde: pte page wire count error"));
3488 mpte->wire_count = 0;
3489 pmap_add_delayed_free_list(mpte, free, FALSE);
3490 atomic_subtract_int(&cnt.v_wire_count, 1);
3493 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3497 * pmap_remove_pte: do the things to unmap a page in a process
3500 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3501 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3503 struct md_page *pvh;
3504 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3507 PG_A = pmap_accessed_bit(pmap);
3508 PG_M = pmap_modified_bit(pmap);
3509 PG_RW = pmap_rw_bit(pmap);
3511 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3512 oldpte = pte_load_clear(ptq);
3514 pmap->pm_stats.wired_count -= 1;
3515 pmap_resident_count_dec(pmap, 1);
3516 if (oldpte & PG_MANAGED) {
3517 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3518 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3521 vm_page_aflag_set(m, PGA_REFERENCED);
3522 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3523 pmap_pvh_free(&m->md, pmap, va);
3524 if (TAILQ_EMPTY(&m->md.pv_list) &&
3525 (m->flags & PG_FICTITIOUS) == 0) {
3526 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3527 if (TAILQ_EMPTY(&pvh->pv_list))
3528 vm_page_aflag_clear(m, PGA_WRITEABLE);
3531 return (pmap_unuse_pt(pmap, va, ptepde, free));
3535 * Remove a single page from a process address space
3538 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3539 struct spglist *free)
3541 struct rwlock *lock;
3542 pt_entry_t *pte, PG_V;
3544 PG_V = pmap_valid_bit(pmap);
3545 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3546 if ((*pde & PG_V) == 0)
3548 pte = pmap_pde_to_pte(pde, va);
3549 if ((*pte & PG_V) == 0)
3552 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3555 pmap_invalidate_page(pmap, va);
3559 * Remove the given range of addresses from the specified map.
3561 * It is assumed that the start and end are properly
3562 * rounded to the page size.
3565 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3567 struct rwlock *lock;
3568 vm_offset_t va, va_next;
3569 pml4_entry_t *pml4e;
3571 pd_entry_t ptpaddr, *pde;
3572 pt_entry_t *pte, PG_G, PG_V;
3573 struct spglist free;
3576 PG_G = pmap_global_bit(pmap);
3577 PG_V = pmap_valid_bit(pmap);
3580 * Perform an unsynchronized read. This is, however, safe.
3582 if (pmap->pm_stats.resident_count == 0)
3588 rw_rlock(&pvh_global_lock);
3592 * special handling of removing one page. a very
3593 * common operation and easy to short circuit some
3596 if (sva + PAGE_SIZE == eva) {
3597 pde = pmap_pde(pmap, sva);
3598 if (pde && (*pde & PG_PS) == 0) {
3599 pmap_remove_page(pmap, sva, pde, &free);
3605 for (; sva < eva; sva = va_next) {
3607 if (pmap->pm_stats.resident_count == 0)
3610 pml4e = pmap_pml4e(pmap, sva);
3611 if ((*pml4e & PG_V) == 0) {
3612 va_next = (sva + NBPML4) & ~PML4MASK;
3618 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3619 if ((*pdpe & PG_V) == 0) {
3620 va_next = (sva + NBPDP) & ~PDPMASK;
3627 * Calculate index for next page table.
3629 va_next = (sva + NBPDR) & ~PDRMASK;
3633 pde = pmap_pdpe_to_pde(pdpe, sva);
3637 * Weed out invalid mappings.
3643 * Check for large page.
3645 if ((ptpaddr & PG_PS) != 0) {
3647 * Are we removing the entire large page? If not,
3648 * demote the mapping and fall through.
3650 if (sva + NBPDR == va_next && eva >= va_next) {
3652 * The TLB entry for a PG_G mapping is
3653 * invalidated by pmap_remove_pde().
3655 if ((ptpaddr & PG_G) == 0)
3657 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3659 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3661 /* The large page mapping was destroyed. */
3668 * Limit our scan to either the end of the va represented
3669 * by the current page table page, or to the end of the
3670 * range being removed.
3676 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3679 if (va != va_next) {
3680 pmap_invalidate_range(pmap, va, sva);
3685 if ((*pte & PG_G) == 0)
3687 else if (va == va_next)
3689 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3696 pmap_invalidate_range(pmap, va, sva);
3702 pmap_invalidate_all(pmap);
3703 rw_runlock(&pvh_global_lock);
3705 pmap_free_zero_pages(&free);
3709 * Routine: pmap_remove_all
3711 * Removes this physical page from
3712 * all physical maps in which it resides.
3713 * Reflects back modify bits to the pager.
3716 * Original versions of this routine were very
3717 * inefficient because they iteratively called
3718 * pmap_remove (slow...)
3722 pmap_remove_all(vm_page_t m)
3724 struct md_page *pvh;
3727 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3730 struct spglist free;
3732 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3733 ("pmap_remove_all: page %p is not managed", m));
3735 rw_wlock(&pvh_global_lock);
3736 if ((m->flags & PG_FICTITIOUS) != 0)
3737 goto small_mappings;
3738 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3739 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3743 pde = pmap_pde(pmap, va);
3744 (void)pmap_demote_pde(pmap, pde, va);
3748 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3751 PG_A = pmap_accessed_bit(pmap);
3752 PG_M = pmap_modified_bit(pmap);
3753 PG_RW = pmap_rw_bit(pmap);
3754 pmap_resident_count_dec(pmap, 1);
3755 pde = pmap_pde(pmap, pv->pv_va);
3756 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3757 " a 2mpage in page %p's pv list", m));
3758 pte = pmap_pde_to_pte(pde, pv->pv_va);
3759 tpte = pte_load_clear(pte);
3761 pmap->pm_stats.wired_count--;
3763 vm_page_aflag_set(m, PGA_REFERENCED);
3766 * Update the vm_page_t clean and reference bits.
3768 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3770 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3771 pmap_invalidate_page(pmap, pv->pv_va);
3772 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3774 free_pv_entry(pmap, pv);
3777 vm_page_aflag_clear(m, PGA_WRITEABLE);
3778 rw_wunlock(&pvh_global_lock);
3779 pmap_free_zero_pages(&free);
3783 * pmap_protect_pde: do the things to protect a 2mpage in a process
3786 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3788 pd_entry_t newpde, oldpde;
3789 vm_offset_t eva, va;
3791 boolean_t anychanged;
3792 pt_entry_t PG_G, PG_M, PG_RW;
3794 PG_G = pmap_global_bit(pmap);
3795 PG_M = pmap_modified_bit(pmap);
3796 PG_RW = pmap_rw_bit(pmap);
3798 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3799 KASSERT((sva & PDRMASK) == 0,
3800 ("pmap_protect_pde: sva is not 2mpage aligned"));
3803 oldpde = newpde = *pde;
3804 if (oldpde & PG_MANAGED) {
3806 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3807 va < eva; va += PAGE_SIZE, m++)
3808 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3811 if ((prot & VM_PROT_WRITE) == 0)
3812 newpde &= ~(PG_RW | PG_M);
3813 if ((prot & VM_PROT_EXECUTE) == 0)
3815 if (newpde != oldpde) {
3816 if (!atomic_cmpset_long(pde, oldpde, newpde))
3819 pmap_invalidate_page(pmap, sva);
3823 return (anychanged);
3827 * Set the physical protection on the
3828 * specified range of this map as requested.
3831 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3833 vm_offset_t va_next;
3834 pml4_entry_t *pml4e;
3836 pd_entry_t ptpaddr, *pde;
3837 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
3838 boolean_t anychanged, pv_lists_locked;
3840 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3841 pmap_remove(pmap, sva, eva);
3845 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3846 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3849 PG_G = pmap_global_bit(pmap);
3850 PG_M = pmap_modified_bit(pmap);
3851 PG_V = pmap_valid_bit(pmap);
3852 PG_RW = pmap_rw_bit(pmap);
3853 pv_lists_locked = FALSE;
3858 for (; sva < eva; sva = va_next) {
3860 pml4e = pmap_pml4e(pmap, sva);
3861 if ((*pml4e & PG_V) == 0) {
3862 va_next = (sva + NBPML4) & ~PML4MASK;
3868 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3869 if ((*pdpe & PG_V) == 0) {
3870 va_next = (sva + NBPDP) & ~PDPMASK;
3876 va_next = (sva + NBPDR) & ~PDRMASK;
3880 pde = pmap_pdpe_to_pde(pdpe, sva);
3884 * Weed out invalid mappings.
3890 * Check for large page.
3892 if ((ptpaddr & PG_PS) != 0) {
3894 * Are we protecting the entire large page? If not,
3895 * demote the mapping and fall through.
3897 if (sva + NBPDR == va_next && eva >= va_next) {
3899 * The TLB entry for a PG_G mapping is
3900 * invalidated by pmap_protect_pde().
3902 if (pmap_protect_pde(pmap, pde, sva, prot))
3906 if (!pv_lists_locked) {
3907 pv_lists_locked = TRUE;
3908 if (!rw_try_rlock(&pvh_global_lock)) {
3910 pmap_invalidate_all(
3913 rw_rlock(&pvh_global_lock);
3917 if (!pmap_demote_pde(pmap, pde, sva)) {
3919 * The large page mapping was
3930 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3932 pt_entry_t obits, pbits;
3936 obits = pbits = *pte;
3937 if ((pbits & PG_V) == 0)
3940 if ((prot & VM_PROT_WRITE) == 0) {
3941 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3942 (PG_MANAGED | PG_M | PG_RW)) {
3943 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3946 pbits &= ~(PG_RW | PG_M);
3948 if ((prot & VM_PROT_EXECUTE) == 0)
3951 if (pbits != obits) {
3952 if (!atomic_cmpset_long(pte, obits, pbits))
3955 pmap_invalidate_page(pmap, sva);
3962 pmap_invalidate_all(pmap);
3963 if (pv_lists_locked)
3964 rw_runlock(&pvh_global_lock);
3969 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3970 * single page table page (PTP) to a single 2MB page mapping. For promotion
3971 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3972 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3973 * identical characteristics.
3976 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3977 struct rwlock **lockp)
3980 pt_entry_t *firstpte, oldpte, pa, *pte;
3981 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
3982 vm_offset_t oldpteva;
3986 PG_A = pmap_accessed_bit(pmap);
3987 PG_G = pmap_global_bit(pmap);
3988 PG_M = pmap_modified_bit(pmap);
3989 PG_V = pmap_valid_bit(pmap);
3990 PG_RW = pmap_rw_bit(pmap);
3991 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3993 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3996 * Examine the first PTE in the specified PTP. Abort if this PTE is
3997 * either invalid, unused, or does not map the first 4KB physical page
3998 * within a 2MB page.
4000 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4003 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4004 atomic_add_long(&pmap_pde_p_failures, 1);
4005 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4006 " in pmap %p", va, pmap);
4009 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4011 * When PG_M is already clear, PG_RW can be cleared without
4012 * a TLB invalidation.
4014 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4020 * Examine each of the other PTEs in the specified PTP. Abort if this
4021 * PTE maps an unexpected 4KB physical page or does not have identical
4022 * characteristics to the first PTE.
4024 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4025 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4028 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4029 atomic_add_long(&pmap_pde_p_failures, 1);
4030 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4031 " in pmap %p", va, pmap);
4034 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4036 * When PG_M is already clear, PG_RW can be cleared
4037 * without a TLB invalidation.
4039 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4042 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
4044 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4045 " in pmap %p", oldpteva, pmap);
4047 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4048 atomic_add_long(&pmap_pde_p_failures, 1);
4049 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4050 " in pmap %p", va, pmap);
4057 * Save the page table page in its current state until the PDE
4058 * mapping the superpage is demoted by pmap_demote_pde() or
4059 * destroyed by pmap_remove_pde().
4061 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4062 KASSERT(mpte >= vm_page_array &&
4063 mpte < &vm_page_array[vm_page_array_size],
4064 ("pmap_promote_pde: page table page is out of range"));
4065 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4066 ("pmap_promote_pde: page table page's pindex is wrong"));
4067 if (pmap_insert_pt_page(pmap, mpte)) {
4068 atomic_add_long(&pmap_pde_p_failures, 1);
4070 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4076 * Promote the pv entries.
4078 if ((newpde & PG_MANAGED) != 0)
4079 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4082 * Propagate the PAT index to its proper position.
4084 newpde = pmap_swap_pat(pmap, newpde);
4087 * Map the superpage.
4089 if (workaround_erratum383)
4090 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4092 pde_store(pde, PG_PS | newpde);
4094 atomic_add_long(&pmap_pde_promotions, 1);
4095 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4096 " in pmap %p", va, pmap);
4100 * Insert the given physical page (p) at
4101 * the specified virtual address (v) in the
4102 * target physical map with the protection requested.
4104 * If specified, the page will be wired down, meaning
4105 * that the related pte can not be reclaimed.
4107 * NB: This is the only routine which MAY NOT lazy-evaluate
4108 * or lose information. That is, this routine must actually
4109 * insert this page into the given map NOW.
4112 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
4113 vm_prot_t prot, boolean_t wired)
4115 struct rwlock *lock;
4117 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4118 pt_entry_t newpte, origpte;
4123 PG_A = pmap_accessed_bit(pmap);
4124 PG_G = pmap_global_bit(pmap);
4125 PG_M = pmap_modified_bit(pmap);
4126 PG_V = pmap_valid_bit(pmap);
4127 PG_RW = pmap_rw_bit(pmap);
4129 va = trunc_page(va);
4130 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4131 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4132 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4134 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4135 va >= kmi.clean_eva,
4136 ("pmap_enter: managed mapping within the clean submap"));
4137 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4138 VM_OBJECT_ASSERT_WLOCKED(m->object);
4139 pa = VM_PAGE_TO_PHYS(m);
4140 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4141 if ((access & VM_PROT_WRITE) != 0)
4143 if ((prot & VM_PROT_WRITE) != 0)
4145 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4146 ("pmap_enter: access includes VM_PROT_WRITE but prot doesn't"));
4147 if ((prot & VM_PROT_EXECUTE) == 0)
4151 if (va < VM_MAXUSER_ADDRESS)
4153 if (pmap == kernel_pmap)
4155 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4158 * Set modified bit gratuitously for writeable mappings if
4159 * the page is unmanaged. We do not want to take a fault
4160 * to do the dirty bit accounting for these mappings.
4162 if ((m->oflags & VPO_UNMANAGED) != 0) {
4163 if ((newpte & PG_RW) != 0)
4170 rw_rlock(&pvh_global_lock);
4174 * In the case that a page table page is not
4175 * resident, we are creating it here.
4178 pde = pmap_pde(pmap, va);
4179 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4180 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4181 pte = pmap_pde_to_pte(pde, va);
4182 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4183 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4186 } else if (va < VM_MAXUSER_ADDRESS) {
4188 * Here if the pte page isn't mapped, or if it has been
4191 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va), &lock);
4194 panic("pmap_enter: invalid page directory va=%#lx", va);
4199 * Is the specified virtual address already mapped?
4201 if ((origpte & PG_V) != 0) {
4203 * Wiring change, just update stats. We don't worry about
4204 * wiring PT pages as they remain resident as long as there
4205 * are valid mappings in them. Hence, if a user page is wired,
4206 * the PT page will be also.
4208 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4209 pmap->pm_stats.wired_count++;
4210 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4211 pmap->pm_stats.wired_count--;
4214 * Remove the extra PT page reference.
4218 KASSERT(mpte->wire_count > 0,
4219 ("pmap_enter: missing reference to page table page,"
4224 * Has the physical page changed?
4226 opa = origpte & PG_FRAME;
4229 * No, might be a protection or wiring change.
4231 if ((origpte & PG_MANAGED) != 0) {
4232 newpte |= PG_MANAGED;
4233 if ((newpte & PG_RW) != 0)
4234 vm_page_aflag_set(m, PGA_WRITEABLE);
4236 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4242 * Increment the counters.
4244 if ((newpte & PG_W) != 0)
4245 pmap->pm_stats.wired_count++;
4246 pmap_resident_count_inc(pmap, 1);
4250 * Enter on the PV list if part of our managed memory.
4252 if ((m->oflags & VPO_UNMANAGED) == 0) {
4253 newpte |= PG_MANAGED;
4254 pv = get_pv_entry(pmap, &lock);
4256 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4257 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4259 if ((newpte & PG_RW) != 0)
4260 vm_page_aflag_set(m, PGA_WRITEABLE);
4266 if ((origpte & PG_V) != 0) {
4268 origpte = pte_load_store(pte, newpte);
4269 opa = origpte & PG_FRAME;
4271 if ((origpte & PG_MANAGED) != 0) {
4272 om = PHYS_TO_VM_PAGE(opa);
4273 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4276 if ((origpte & PG_A) != 0)
4277 vm_page_aflag_set(om, PGA_REFERENCED);
4278 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4279 pmap_pvh_free(&om->md, pmap, va);
4280 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4281 TAILQ_EMPTY(&om->md.pv_list) &&
4282 ((om->flags & PG_FICTITIOUS) != 0 ||
4283 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4284 vm_page_aflag_clear(om, PGA_WRITEABLE);
4286 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4287 PG_RW)) == (PG_M | PG_RW)) {
4288 if ((origpte & PG_MANAGED) != 0)
4292 * Although the PTE may still have PG_RW set, TLB
4293 * invalidation may nonetheless be required because
4294 * the PTE no longer has PG_M set.
4296 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4298 * This PTE change does not require TLB invalidation.
4302 if ((origpte & PG_A) != 0)
4303 pmap_invalidate_page(pmap, va);
4305 pte_store(pte, newpte);
4310 * If both the page table page and the reservation are fully
4311 * populated, then attempt promotion.
4313 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4314 pmap_ps_enabled(pmap) &&
4315 (m->flags & PG_FICTITIOUS) == 0 &&
4316 vm_reserv_level_iffullpop(m) == 0)
4317 pmap_promote_pde(pmap, pde, va, &lock);
4321 rw_runlock(&pvh_global_lock);
4326 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4327 * otherwise. Fails if (1) a page table page cannot be allocated without
4328 * blocking, (2) a mapping already exists at the specified virtual address, or
4329 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4332 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4333 struct rwlock **lockp)
4335 pd_entry_t *pde, newpde;
4338 struct spglist free;
4340 PG_V = pmap_valid_bit(pmap);
4341 rw_assert(&pvh_global_lock, RA_LOCKED);
4342 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4344 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4345 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4346 " in pmap %p", va, pmap);
4349 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4350 pde = &pde[pmap_pde_index(va)];
4351 if ((*pde & PG_V) != 0) {
4352 KASSERT(mpde->wire_count > 1,
4353 ("pmap_enter_pde: mpde's wire count is too low"));
4355 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4356 " in pmap %p", va, pmap);
4359 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4361 if ((m->oflags & VPO_UNMANAGED) == 0) {
4362 newpde |= PG_MANAGED;
4365 * Abort this mapping if its PV entry could not be created.
4367 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4370 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4371 pmap_invalidate_page(pmap, va);
4372 pmap_free_zero_pages(&free);
4374 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4375 " in pmap %p", va, pmap);
4379 if ((prot & VM_PROT_EXECUTE) == 0)
4381 if (va < VM_MAXUSER_ADDRESS)
4385 * Increment counters.
4387 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4390 * Map the superpage.
4392 pde_store(pde, newpde);
4394 atomic_add_long(&pmap_pde_mappings, 1);
4395 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4396 " in pmap %p", va, pmap);
4401 * Maps a sequence of resident pages belonging to the same object.
4402 * The sequence begins with the given page m_start. This page is
4403 * mapped at the given virtual address start. Each subsequent page is
4404 * mapped at a virtual address that is offset from start by the same
4405 * amount as the page is offset from m_start within the object. The
4406 * last page in the sequence is the page with the largest offset from
4407 * m_start that can be mapped at a virtual address less than the given
4408 * virtual address end. Not every virtual page between start and end
4409 * is mapped; only those for which a resident page exists with the
4410 * corresponding offset from m_start are mapped.
4413 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4414 vm_page_t m_start, vm_prot_t prot)
4416 struct rwlock *lock;
4419 vm_pindex_t diff, psize;
4421 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4423 psize = atop(end - start);
4427 rw_rlock(&pvh_global_lock);
4429 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4430 va = start + ptoa(diff);
4431 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4432 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
4433 pmap_ps_enabled(pmap) &&
4434 vm_reserv_level_iffullpop(m) == 0 &&
4435 pmap_enter_pde(pmap, va, m, prot, &lock))
4436 m = &m[NBPDR / PAGE_SIZE - 1];
4438 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4440 m = TAILQ_NEXT(m, listq);
4444 rw_runlock(&pvh_global_lock);
4449 * this code makes some *MAJOR* assumptions:
4450 * 1. Current pmap & pmap exists.
4453 * 4. No page table pages.
4454 * but is *MUCH* faster than pmap_enter...
4458 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4460 struct rwlock *lock;
4463 rw_rlock(&pvh_global_lock);
4465 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4468 rw_runlock(&pvh_global_lock);
4473 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4474 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4476 struct spglist free;
4477 pt_entry_t *pte, PG_V;
4480 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4481 (m->oflags & VPO_UNMANAGED) != 0,
4482 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4483 PG_V = pmap_valid_bit(pmap);
4484 rw_assert(&pvh_global_lock, RA_LOCKED);
4485 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4488 * In the case that a page table page is not
4489 * resident, we are creating it here.
4491 if (va < VM_MAXUSER_ADDRESS) {
4492 vm_pindex_t ptepindex;
4496 * Calculate pagetable page index
4498 ptepindex = pmap_pde_pindex(va);
4499 if (mpte && (mpte->pindex == ptepindex)) {
4503 * Get the page directory entry
4505 ptepa = pmap_pde(pmap, va);
4508 * If the page table page is mapped, we just increment
4509 * the hold count, and activate it. Otherwise, we
4510 * attempt to allocate a page table page. If this
4511 * attempt fails, we don't retry. Instead, we give up.
4513 if (ptepa && (*ptepa & PG_V) != 0) {
4516 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4520 * Pass NULL instead of the PV list lock
4521 * pointer, because we don't intend to sleep.
4523 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4528 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4529 pte = &pte[pmap_pte_index(va)];
4543 * Enter on the PV list if part of our managed memory.
4545 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4546 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4549 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4550 pmap_invalidate_page(pmap, va);
4551 pmap_free_zero_pages(&free);
4559 * Increment counters
4561 pmap_resident_count_inc(pmap, 1);
4563 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4564 if ((prot & VM_PROT_EXECUTE) == 0)
4568 * Now validate mapping with RO protection
4570 if ((m->oflags & VPO_UNMANAGED) != 0)
4571 pte_store(pte, pa | PG_V | PG_U);
4573 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4578 * Make a temporary mapping for a physical address. This is only intended
4579 * to be used for panic dumps.
4582 pmap_kenter_temporary(vm_paddr_t pa, int i)
4586 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4587 pmap_kenter(va, pa);
4589 return ((void *)crashdumpmap);
4593 * This code maps large physical mmap regions into the
4594 * processor address space. Note that some shortcuts
4595 * are taken, but the code works.
4598 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4599 vm_pindex_t pindex, vm_size_t size)
4602 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4603 vm_paddr_t pa, ptepa;
4607 PG_A = pmap_accessed_bit(pmap);
4608 PG_M = pmap_modified_bit(pmap);
4609 PG_V = pmap_valid_bit(pmap);
4610 PG_RW = pmap_rw_bit(pmap);
4612 VM_OBJECT_ASSERT_WLOCKED(object);
4613 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4614 ("pmap_object_init_pt: non-device object"));
4615 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4616 if (!pmap_ps_enabled(pmap))
4618 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4620 p = vm_page_lookup(object, pindex);
4621 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4622 ("pmap_object_init_pt: invalid page %p", p));
4623 pat_mode = p->md.pat_mode;
4626 * Abort the mapping if the first page is not physically
4627 * aligned to a 2MB page boundary.
4629 ptepa = VM_PAGE_TO_PHYS(p);
4630 if (ptepa & (NBPDR - 1))
4634 * Skip the first page. Abort the mapping if the rest of
4635 * the pages are not physically contiguous or have differing
4636 * memory attributes.
4638 p = TAILQ_NEXT(p, listq);
4639 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4641 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4642 ("pmap_object_init_pt: invalid page %p", p));
4643 if (pa != VM_PAGE_TO_PHYS(p) ||
4644 pat_mode != p->md.pat_mode)
4646 p = TAILQ_NEXT(p, listq);
4650 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4651 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4652 * will not affect the termination of this loop.
4655 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4656 pa < ptepa + size; pa += NBPDR) {
4657 pdpg = pmap_allocpde(pmap, addr, NULL);
4660 * The creation of mappings below is only an
4661 * optimization. If a page directory page
4662 * cannot be allocated without blocking,
4663 * continue on to the next mapping rather than
4669 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4670 pde = &pde[pmap_pde_index(addr)];
4671 if ((*pde & PG_V) == 0) {
4672 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4673 PG_U | PG_RW | PG_V);
4674 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4675 atomic_add_long(&pmap_pde_mappings, 1);
4677 /* Continue on if the PDE is already valid. */
4679 KASSERT(pdpg->wire_count > 0,
4680 ("pmap_object_init_pt: missing reference "
4681 "to page directory page, va: 0x%lx", addr));
4690 * Routine: pmap_change_wiring
4691 * Function: Change the wiring attribute for a map/virtual-address
4693 * In/out conditions:
4694 * The mapping must already exist in the pmap.
4697 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
4701 boolean_t pv_lists_locked;
4703 pv_lists_locked = FALSE;
4706 * Wiring is not a hardware characteristic so there is no need to
4711 pde = pmap_pde(pmap, va);
4712 if ((*pde & PG_PS) != 0) {
4713 if (!wired != ((*pde & PG_W) == 0)) {
4714 if (!pv_lists_locked) {
4715 pv_lists_locked = TRUE;
4716 if (!rw_try_rlock(&pvh_global_lock)) {
4718 rw_rlock(&pvh_global_lock);
4722 if (!pmap_demote_pde(pmap, pde, va))
4723 panic("pmap_change_wiring: demotion failed");
4727 pte = pmap_pde_to_pte(pde, va);
4728 if (wired && (*pte & PG_W) == 0) {
4729 pmap->pm_stats.wired_count++;
4730 atomic_set_long(pte, PG_W);
4731 } else if (!wired && (*pte & PG_W) != 0) {
4732 pmap->pm_stats.wired_count--;
4733 atomic_clear_long(pte, PG_W);
4736 if (pv_lists_locked)
4737 rw_runlock(&pvh_global_lock);
4742 * Copy the range specified by src_addr/len
4743 * from the source map to the range dst_addr/len
4744 * in the destination map.
4746 * This routine is only advisory and need not do anything.
4750 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4751 vm_offset_t src_addr)
4753 struct rwlock *lock;
4754 struct spglist free;
4756 vm_offset_t end_addr = src_addr + len;
4757 vm_offset_t va_next;
4758 pt_entry_t PG_A, PG_M, PG_V;
4760 if (dst_addr != src_addr)
4763 if (dst_pmap->pm_type != src_pmap->pm_type)
4767 * EPT page table entries that require emulation of A/D bits are
4768 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
4769 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
4770 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
4771 * implementations flag an EPT misconfiguration for exec-only
4772 * mappings we skip this function entirely for emulated pmaps.
4774 if (pmap_emulate_ad_bits(dst_pmap))
4778 rw_rlock(&pvh_global_lock);
4779 if (dst_pmap < src_pmap) {
4780 PMAP_LOCK(dst_pmap);
4781 PMAP_LOCK(src_pmap);
4783 PMAP_LOCK(src_pmap);
4784 PMAP_LOCK(dst_pmap);
4787 PG_A = pmap_accessed_bit(dst_pmap);
4788 PG_M = pmap_modified_bit(dst_pmap);
4789 PG_V = pmap_valid_bit(dst_pmap);
4791 for (addr = src_addr; addr < end_addr; addr = va_next) {
4792 pt_entry_t *src_pte, *dst_pte;
4793 vm_page_t dstmpde, dstmpte, srcmpte;
4794 pml4_entry_t *pml4e;
4796 pd_entry_t srcptepaddr, *pde;
4798 KASSERT(addr < UPT_MIN_ADDRESS,
4799 ("pmap_copy: invalid to pmap_copy page tables"));
4801 pml4e = pmap_pml4e(src_pmap, addr);
4802 if ((*pml4e & PG_V) == 0) {
4803 va_next = (addr + NBPML4) & ~PML4MASK;
4809 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4810 if ((*pdpe & PG_V) == 0) {
4811 va_next = (addr + NBPDP) & ~PDPMASK;
4817 va_next = (addr + NBPDR) & ~PDRMASK;
4821 pde = pmap_pdpe_to_pde(pdpe, addr);
4823 if (srcptepaddr == 0)
4826 if (srcptepaddr & PG_PS) {
4827 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4829 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4830 if (dstmpde == NULL)
4832 pde = (pd_entry_t *)
4833 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4834 pde = &pde[pmap_pde_index(addr)];
4835 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4836 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4837 PG_PS_FRAME, &lock))) {
4838 *pde = srcptepaddr & ~PG_W;
4839 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4841 dstmpde->wire_count--;
4845 srcptepaddr &= PG_FRAME;
4846 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4847 KASSERT(srcmpte->wire_count > 0,
4848 ("pmap_copy: source page table page is unused"));
4850 if (va_next > end_addr)
4853 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4854 src_pte = &src_pte[pmap_pte_index(addr)];
4856 while (addr < va_next) {
4860 * we only virtual copy managed pages
4862 if ((ptetemp & PG_MANAGED) != 0) {
4863 if (dstmpte != NULL &&
4864 dstmpte->pindex == pmap_pde_pindex(addr))
4865 dstmpte->wire_count++;
4866 else if ((dstmpte = pmap_allocpte(dst_pmap,
4867 addr, NULL)) == NULL)
4869 dst_pte = (pt_entry_t *)
4870 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4871 dst_pte = &dst_pte[pmap_pte_index(addr)];
4872 if (*dst_pte == 0 &&
4873 pmap_try_insert_pv_entry(dst_pmap, addr,
4874 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4877 * Clear the wired, modified, and
4878 * accessed (referenced) bits
4881 *dst_pte = ptetemp & ~(PG_W | PG_M |
4883 pmap_resident_count_inc(dst_pmap, 1);
4886 if (pmap_unwire_ptp(dst_pmap, addr,
4888 pmap_invalidate_page(dst_pmap,
4890 pmap_free_zero_pages(&free);
4894 if (dstmpte->wire_count >= srcmpte->wire_count)
4904 rw_runlock(&pvh_global_lock);
4905 PMAP_UNLOCK(src_pmap);
4906 PMAP_UNLOCK(dst_pmap);
4910 * pmap_zero_page zeros the specified hardware page by mapping
4911 * the page into KVM and using bzero to clear its contents.
4914 pmap_zero_page(vm_page_t m)
4916 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4918 pagezero((void *)va);
4922 * pmap_zero_page_area zeros the specified hardware page by mapping
4923 * the page into KVM and using bzero to clear its contents.
4925 * off and size may not cover an area beyond a single hardware page.
4928 pmap_zero_page_area(vm_page_t m, int off, int size)
4930 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4932 if (off == 0 && size == PAGE_SIZE)
4933 pagezero((void *)va);
4935 bzero((char *)va + off, size);
4939 * pmap_zero_page_idle zeros the specified hardware page by mapping
4940 * the page into KVM and using bzero to clear its contents. This
4941 * is intended to be called from the vm_pagezero process only and
4945 pmap_zero_page_idle(vm_page_t m)
4947 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4949 pagezero((void *)va);
4953 * pmap_copy_page copies the specified (machine independent)
4954 * page by mapping the page into virtual memory and using
4955 * bcopy to copy the page, one machine dependent page at a
4959 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
4961 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
4962 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
4964 pagecopy((void *)src, (void *)dst);
4967 int unmapped_buf_allowed = 1;
4970 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4971 vm_offset_t b_offset, int xfersize)
4974 vm_offset_t a_pg_offset, b_pg_offset;
4977 while (xfersize > 0) {
4978 a_pg_offset = a_offset & PAGE_MASK;
4979 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4980 a_cp = (char *)PHYS_TO_DMAP(ma[a_offset >> PAGE_SHIFT]->
4981 phys_addr) + a_pg_offset;
4982 b_pg_offset = b_offset & PAGE_MASK;
4983 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4984 b_cp = (char *)PHYS_TO_DMAP(mb[b_offset >> PAGE_SHIFT]->
4985 phys_addr) + b_pg_offset;
4986 bcopy(a_cp, b_cp, cnt);
4994 * Returns true if the pmap's pv is one of the first
4995 * 16 pvs linked to from this page. This count may
4996 * be changed upwards or downwards in the future; it
4997 * is only necessary that true be returned for a small
4998 * subset of pmaps for proper page aging.
5001 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5003 struct md_page *pvh;
5004 struct rwlock *lock;
5009 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5010 ("pmap_page_exists_quick: page %p is not managed", m));
5012 rw_rlock(&pvh_global_lock);
5013 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5015 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5016 if (PV_PMAP(pv) == pmap) {
5024 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5025 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5026 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5027 if (PV_PMAP(pv) == pmap) {
5037 rw_runlock(&pvh_global_lock);
5042 * pmap_page_wired_mappings:
5044 * Return the number of managed mappings to the given physical page
5048 pmap_page_wired_mappings(vm_page_t m)
5050 struct rwlock *lock;
5051 struct md_page *pvh;
5055 int count, md_gen, pvh_gen;
5057 if ((m->oflags & VPO_UNMANAGED) != 0)
5059 rw_rlock(&pvh_global_lock);
5060 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5064 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5066 if (!PMAP_TRYLOCK(pmap)) {
5067 md_gen = m->md.pv_gen;
5071 if (md_gen != m->md.pv_gen) {
5076 pte = pmap_pte(pmap, pv->pv_va);
5077 if ((*pte & PG_W) != 0)
5081 if ((m->flags & PG_FICTITIOUS) == 0) {
5082 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5083 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5085 if (!PMAP_TRYLOCK(pmap)) {
5086 md_gen = m->md.pv_gen;
5087 pvh_gen = pvh->pv_gen;
5091 if (md_gen != m->md.pv_gen ||
5092 pvh_gen != pvh->pv_gen) {
5097 pte = pmap_pde(pmap, pv->pv_va);
5098 if ((*pte & PG_W) != 0)
5104 rw_runlock(&pvh_global_lock);
5109 * Returns TRUE if the given page is mapped individually or as part of
5110 * a 2mpage. Otherwise, returns FALSE.
5113 pmap_page_is_mapped(vm_page_t m)
5115 struct rwlock *lock;
5118 if ((m->oflags & VPO_UNMANAGED) != 0)
5120 rw_rlock(&pvh_global_lock);
5121 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5123 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5124 ((m->flags & PG_FICTITIOUS) == 0 &&
5125 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5127 rw_runlock(&pvh_global_lock);
5132 * Remove all pages from specified address space
5133 * this aids process exit speeds. Also, this code
5134 * is special cased for current process only, but
5135 * can have the more generic (and slightly slower)
5136 * mode enabled. This is much faster than pmap_remove
5137 * in the case of running down an entire address space.
5140 pmap_remove_pages(pmap_t pmap)
5143 pt_entry_t *pte, tpte;
5144 pt_entry_t PG_M, PG_RW, PG_V;
5145 struct spglist free;
5146 vm_page_t m, mpte, mt;
5148 struct md_page *pvh;
5149 struct pv_chunk *pc, *npc;
5150 struct rwlock *lock;
5152 uint64_t inuse, bitmask;
5153 int allfree, field, freed, idx;
5154 boolean_t superpage;
5157 if (pmap != PCPU_GET(curpmap)) {
5158 printf("warning: pmap_remove_pages called with non-current pmap\n");
5163 PG_M = pmap_modified_bit(pmap);
5164 PG_V = pmap_valid_bit(pmap);
5165 PG_RW = pmap_rw_bit(pmap);
5168 rw_rlock(&pvh_global_lock);
5170 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5173 for (field = 0; field < _NPCM; field++) {
5174 inuse = ~pc->pc_map[field] & pc_freemask[field];
5175 while (inuse != 0) {
5177 bitmask = 1UL << bit;
5178 idx = field * 64 + bit;
5179 pv = &pc->pc_pventry[idx];
5182 pte = pmap_pdpe(pmap, pv->pv_va);
5184 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5186 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5189 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5191 pte = &pte[pmap_pte_index(pv->pv_va)];
5195 * Keep track whether 'tpte' is a
5196 * superpage explicitly instead of
5197 * relying on PG_PS being set.
5199 * This is because PG_PS is numerically
5200 * identical to PG_PTE_PAT and thus a
5201 * regular page could be mistaken for
5207 if ((tpte & PG_V) == 0) {
5208 panic("bad pte va %lx pte %lx",
5213 * We cannot remove wired pages from a process' mapping at this time
5221 pa = tpte & PG_PS_FRAME;
5223 pa = tpte & PG_FRAME;
5225 m = PHYS_TO_VM_PAGE(pa);
5226 KASSERT(m->phys_addr == pa,
5227 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5228 m, (uintmax_t)m->phys_addr,
5231 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5232 m < &vm_page_array[vm_page_array_size],
5233 ("pmap_remove_pages: bad tpte %#jx",
5239 * Update the vm_page_t clean/reference bits.
5241 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5243 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5249 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5252 pc->pc_map[field] |= bitmask;
5254 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5255 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5256 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5258 if (TAILQ_EMPTY(&pvh->pv_list)) {
5259 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5260 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5261 TAILQ_EMPTY(&mt->md.pv_list))
5262 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5264 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
5266 pmap_remove_pt_page(pmap, mpte);
5267 pmap_resident_count_dec(pmap, 1);
5268 KASSERT(mpte->wire_count == NPTEPG,
5269 ("pmap_remove_pages: pte page wire count error"));
5270 mpte->wire_count = 0;
5271 pmap_add_delayed_free_list(mpte, &free, FALSE);
5272 atomic_subtract_int(&cnt.v_wire_count, 1);
5275 pmap_resident_count_dec(pmap, 1);
5276 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5278 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5279 TAILQ_EMPTY(&m->md.pv_list) &&
5280 (m->flags & PG_FICTITIOUS) == 0) {
5281 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5282 if (TAILQ_EMPTY(&pvh->pv_list))
5283 vm_page_aflag_clear(m, PGA_WRITEABLE);
5286 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5290 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5291 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5292 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5294 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5300 pmap_invalidate_all(pmap);
5301 rw_runlock(&pvh_global_lock);
5303 pmap_free_zero_pages(&free);
5307 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5309 struct rwlock *lock;
5311 struct md_page *pvh;
5312 pt_entry_t *pte, mask;
5313 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5315 int md_gen, pvh_gen;
5319 rw_rlock(&pvh_global_lock);
5320 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5323 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5325 if (!PMAP_TRYLOCK(pmap)) {
5326 md_gen = m->md.pv_gen;
5330 if (md_gen != m->md.pv_gen) {
5335 pte = pmap_pte(pmap, pv->pv_va);
5338 PG_M = pmap_modified_bit(pmap);
5339 PG_RW = pmap_rw_bit(pmap);
5340 mask |= PG_RW | PG_M;
5343 PG_A = pmap_accessed_bit(pmap);
5344 PG_V = pmap_valid_bit(pmap);
5345 mask |= PG_V | PG_A;
5347 rv = (*pte & mask) == mask;
5352 if ((m->flags & PG_FICTITIOUS) == 0) {
5353 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5354 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5356 if (!PMAP_TRYLOCK(pmap)) {
5357 md_gen = m->md.pv_gen;
5358 pvh_gen = pvh->pv_gen;
5362 if (md_gen != m->md.pv_gen ||
5363 pvh_gen != pvh->pv_gen) {
5368 pte = pmap_pde(pmap, pv->pv_va);
5371 PG_M = pmap_modified_bit(pmap);
5372 PG_RW = pmap_rw_bit(pmap);
5373 mask |= PG_RW | PG_M;
5376 PG_A = pmap_accessed_bit(pmap);
5377 PG_V = pmap_valid_bit(pmap);
5378 mask |= PG_V | PG_A;
5380 rv = (*pte & mask) == mask;
5388 rw_runlock(&pvh_global_lock);
5395 * Return whether or not the specified physical page was modified
5396 * in any physical maps.
5399 pmap_is_modified(vm_page_t m)
5402 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5403 ("pmap_is_modified: page %p is not managed", m));
5406 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5407 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5408 * is clear, no PTEs can have PG_M set.
5410 VM_OBJECT_ASSERT_WLOCKED(m->object);
5411 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5413 return (pmap_page_test_mappings(m, FALSE, TRUE));
5417 * pmap_is_prefaultable:
5419 * Return whether or not the specified virtual address is eligible
5423 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5426 pt_entry_t *pte, PG_V;
5429 PG_V = pmap_valid_bit(pmap);
5432 pde = pmap_pde(pmap, addr);
5433 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5434 pte = pmap_pde_to_pte(pde, addr);
5435 rv = (*pte & PG_V) == 0;
5442 * pmap_is_referenced:
5444 * Return whether or not the specified physical page was referenced
5445 * in any physical maps.
5448 pmap_is_referenced(vm_page_t m)
5451 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5452 ("pmap_is_referenced: page %p is not managed", m));
5453 return (pmap_page_test_mappings(m, TRUE, FALSE));
5457 * Clear the write and modified bits in each of the given page's mappings.
5460 pmap_remove_write(vm_page_t m)
5462 struct md_page *pvh;
5464 struct rwlock *lock;
5465 pv_entry_t next_pv, pv;
5467 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5469 int pvh_gen, md_gen;
5471 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5472 ("pmap_remove_write: page %p is not managed", m));
5475 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5476 * set by another thread while the object is locked. Thus,
5477 * if PGA_WRITEABLE is clear, no page table entries need updating.
5479 VM_OBJECT_ASSERT_WLOCKED(m->object);
5480 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5482 rw_rlock(&pvh_global_lock);
5483 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5484 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5487 if ((m->flags & PG_FICTITIOUS) != 0)
5488 goto small_mappings;
5489 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5491 if (!PMAP_TRYLOCK(pmap)) {
5492 pvh_gen = pvh->pv_gen;
5496 if (pvh_gen != pvh->pv_gen) {
5502 PG_RW = pmap_rw_bit(pmap);
5504 pde = pmap_pde(pmap, va);
5505 if ((*pde & PG_RW) != 0)
5506 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5507 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5508 ("inconsistent pv lock %p %p for page %p",
5509 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5513 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5515 if (!PMAP_TRYLOCK(pmap)) {
5516 pvh_gen = pvh->pv_gen;
5517 md_gen = m->md.pv_gen;
5521 if (pvh_gen != pvh->pv_gen ||
5522 md_gen != m->md.pv_gen) {
5528 PG_M = pmap_modified_bit(pmap);
5529 PG_RW = pmap_rw_bit(pmap);
5530 pde = pmap_pde(pmap, pv->pv_va);
5531 KASSERT((*pde & PG_PS) == 0,
5532 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5534 pte = pmap_pde_to_pte(pde, pv->pv_va);
5537 if (oldpte & PG_RW) {
5538 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5541 if ((oldpte & PG_M) != 0)
5543 pmap_invalidate_page(pmap, pv->pv_va);
5548 vm_page_aflag_clear(m, PGA_WRITEABLE);
5549 rw_runlock(&pvh_global_lock);
5552 static __inline boolean_t
5553 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5556 if (!pmap_emulate_ad_bits(pmap))
5559 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5562 * RWX = 010 or 110 will cause an unconditional EPT misconfiguration
5563 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5564 * if the EPT_PG_WRITE bit is set.
5566 if ((pte & EPT_PG_WRITE) != 0)
5570 * RWX = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5572 if ((pte & EPT_PG_EXECUTE) == 0 ||
5573 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5579 #define PMAP_TS_REFERENCED_MAX 5
5582 * pmap_ts_referenced:
5584 * Return a count of reference bits for a page, clearing those bits.
5585 * It is not necessary for every reference bit to be cleared, but it
5586 * is necessary that 0 only be returned when there are truly no
5587 * reference bits set.
5589 * XXX: The exact number of bits to check and clear is a matter that
5590 * should be tested and standardized at some point in the future for
5591 * optimal aging of shared pages.
5594 pmap_ts_referenced(vm_page_t m)
5596 struct md_page *pvh;
5599 struct rwlock *lock;
5600 pd_entry_t oldpde, *pde;
5601 pt_entry_t *pte, PG_A;
5604 int cleared, md_gen, not_cleared, pvh_gen;
5605 struct spglist free;
5608 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5609 ("pmap_ts_referenced: page %p is not managed", m));
5612 pa = VM_PAGE_TO_PHYS(m);
5613 lock = PHYS_TO_PV_LIST_LOCK(pa);
5614 pvh = pa_to_pvh(pa);
5615 rw_rlock(&pvh_global_lock);
5619 if ((m->flags & PG_FICTITIOUS) != 0 ||
5620 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5621 goto small_mappings;
5627 if (!PMAP_TRYLOCK(pmap)) {
5628 pvh_gen = pvh->pv_gen;
5632 if (pvh_gen != pvh->pv_gen) {
5637 PG_A = pmap_accessed_bit(pmap);
5639 pde = pmap_pde(pmap, pv->pv_va);
5641 if ((*pde & PG_A) != 0) {
5643 * Since this reference bit is shared by 512 4KB
5644 * pages, it should not be cleared every time it is
5645 * tested. Apply a simple "hash" function on the
5646 * physical page number, the virtual superpage number,
5647 * and the pmap address to select one 4KB page out of
5648 * the 512 on which testing the reference bit will
5649 * result in clearing that reference bit. This
5650 * function is designed to avoid the selection of the
5651 * same 4KB page for every 2MB page mapping.
5653 * On demotion, a mapping that hasn't been referenced
5654 * is simply destroyed. To avoid the possibility of a
5655 * subsequent page fault on a demoted wired mapping,
5656 * always leave its reference bit set. Moreover,
5657 * since the superpage is wired, the current state of
5658 * its reference bit won't affect page replacement.
5660 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5661 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5662 (*pde & PG_W) == 0) {
5663 if (safe_to_clear_referenced(pmap, oldpde)) {
5664 atomic_clear_long(pde, PG_A);
5665 pmap_invalidate_page(pmap, pv->pv_va);
5667 } else if (pmap_demote_pde_locked(pmap, pde,
5668 pv->pv_va, &lock)) {
5670 * Remove the mapping to a single page
5671 * so that a subsequent access may
5672 * repromote. Since the underlying
5673 * page table page is fully populated,
5674 * this removal never frees a page
5678 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5680 pte = pmap_pde_to_pte(pde, va);
5681 pmap_remove_pte(pmap, pte, va, *pde,
5683 pmap_invalidate_page(pmap, va);
5689 * The superpage mapping was removed
5690 * entirely and therefore 'pv' is no
5698 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5699 ("inconsistent pv lock %p %p for page %p",
5700 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5705 /* Rotate the PV list if it has more than one entry. */
5706 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5707 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5708 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5711 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5713 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5715 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5722 if (!PMAP_TRYLOCK(pmap)) {
5723 pvh_gen = pvh->pv_gen;
5724 md_gen = m->md.pv_gen;
5728 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5733 PG_A = pmap_accessed_bit(pmap);
5734 pde = pmap_pde(pmap, pv->pv_va);
5735 KASSERT((*pde & PG_PS) == 0,
5736 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5738 pte = pmap_pde_to_pte(pde, pv->pv_va);
5739 if ((*pte & PG_A) != 0) {
5740 if (safe_to_clear_referenced(pmap, *pte)) {
5741 atomic_clear_long(pte, PG_A);
5742 pmap_invalidate_page(pmap, pv->pv_va);
5744 } else if ((*pte & PG_W) == 0) {
5746 * Wired pages cannot be paged out so
5747 * doing accessed bit emulation for
5748 * them is wasted effort. We do the
5749 * hard work for unwired pages only.
5751 pmap_remove_pte(pmap, pte, pv->pv_va,
5752 *pde, &free, &lock);
5753 pmap_invalidate_page(pmap, pv->pv_va);
5758 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5759 ("inconsistent pv lock %p %p for page %p",
5760 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5765 /* Rotate the PV list if it has more than one entry. */
5766 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5767 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5768 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5771 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5772 not_cleared < PMAP_TS_REFERENCED_MAX);
5775 rw_runlock(&pvh_global_lock);
5776 pmap_free_zero_pages(&free);
5777 return (cleared + not_cleared);
5781 * Apply the given advice to the specified range of addresses within the
5782 * given pmap. Depending on the advice, clear the referenced and/or
5783 * modified flags in each mapping and set the mapped page's dirty field.
5786 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5788 struct rwlock *lock;
5789 pml4_entry_t *pml4e;
5791 pd_entry_t oldpde, *pde;
5792 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
5793 vm_offset_t va_next;
5795 boolean_t anychanged, pv_lists_locked;
5797 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5801 * A/D bit emulation requires an alternate code path when clearing
5802 * the modified and accessed bits below. Since this function is
5803 * advisory in nature we skip it entirely for pmaps that require
5804 * A/D bit emulation.
5806 if (pmap_emulate_ad_bits(pmap))
5809 PG_A = pmap_accessed_bit(pmap);
5810 PG_G = pmap_global_bit(pmap);
5811 PG_M = pmap_modified_bit(pmap);
5812 PG_V = pmap_valid_bit(pmap);
5813 PG_RW = pmap_rw_bit(pmap);
5815 pv_lists_locked = FALSE;
5819 for (; sva < eva; sva = va_next) {
5820 pml4e = pmap_pml4e(pmap, sva);
5821 if ((*pml4e & PG_V) == 0) {
5822 va_next = (sva + NBPML4) & ~PML4MASK;
5827 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5828 if ((*pdpe & PG_V) == 0) {
5829 va_next = (sva + NBPDP) & ~PDPMASK;
5834 va_next = (sva + NBPDR) & ~PDRMASK;
5837 pde = pmap_pdpe_to_pde(pdpe, sva);
5839 if ((oldpde & PG_V) == 0)
5841 else if ((oldpde & PG_PS) != 0) {
5842 if ((oldpde & PG_MANAGED) == 0)
5844 if (!pv_lists_locked) {
5845 pv_lists_locked = TRUE;
5846 if (!rw_try_rlock(&pvh_global_lock)) {
5848 pmap_invalidate_all(pmap);
5850 rw_rlock(&pvh_global_lock);
5855 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
5860 * The large page mapping was destroyed.
5866 * Unless the page mappings are wired, remove the
5867 * mapping to a single page so that a subsequent
5868 * access may repromote. Since the underlying page
5869 * table page is fully populated, this removal never
5870 * frees a page table page.
5872 if ((oldpde & PG_W) == 0) {
5873 pte = pmap_pde_to_pte(pde, sva);
5874 KASSERT((*pte & PG_V) != 0,
5875 ("pmap_advise: invalid PTE"));
5876 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
5885 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5887 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
5890 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5891 if (advice == MADV_DONTNEED) {
5893 * Future calls to pmap_is_modified()
5894 * can be avoided by making the page
5897 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5900 atomic_clear_long(pte, PG_M | PG_A);
5901 } else if ((*pte & PG_A) != 0)
5902 atomic_clear_long(pte, PG_A);
5905 if ((*pte & PG_G) != 0)
5906 pmap_invalidate_page(pmap, sva);
5912 pmap_invalidate_all(pmap);
5913 if (pv_lists_locked)
5914 rw_runlock(&pvh_global_lock);
5919 * Clear the modify bits on the specified physical page.
5922 pmap_clear_modify(vm_page_t m)
5924 struct md_page *pvh;
5926 pv_entry_t next_pv, pv;
5927 pd_entry_t oldpde, *pde;
5928 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
5929 struct rwlock *lock;
5931 int md_gen, pvh_gen;
5933 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5934 ("pmap_clear_modify: page %p is not managed", m));
5935 VM_OBJECT_ASSERT_WLOCKED(m->object);
5936 KASSERT(!vm_page_xbusied(m),
5937 ("pmap_clear_modify: page %p is exclusive busied", m));
5940 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5941 * If the object containing the page is locked and the page is not
5942 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5944 if ((m->aflags & PGA_WRITEABLE) == 0)
5946 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5947 rw_rlock(&pvh_global_lock);
5948 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5951 if ((m->flags & PG_FICTITIOUS) != 0)
5952 goto small_mappings;
5953 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5955 if (!PMAP_TRYLOCK(pmap)) {
5956 pvh_gen = pvh->pv_gen;
5960 if (pvh_gen != pvh->pv_gen) {
5965 PG_M = pmap_modified_bit(pmap);
5966 PG_V = pmap_valid_bit(pmap);
5967 PG_RW = pmap_rw_bit(pmap);
5969 pde = pmap_pde(pmap, va);
5971 if ((oldpde & PG_RW) != 0) {
5972 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
5973 if ((oldpde & PG_W) == 0) {
5975 * Write protect the mapping to a
5976 * single page so that a subsequent
5977 * write access may repromote.
5979 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5981 pte = pmap_pde_to_pte(pde, va);
5983 if ((oldpte & PG_V) != 0) {
5984 while (!atomic_cmpset_long(pte,
5986 oldpte & ~(PG_M | PG_RW)))
5989 pmap_invalidate_page(pmap, va);
5997 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5999 if (!PMAP_TRYLOCK(pmap)) {
6000 md_gen = m->md.pv_gen;
6001 pvh_gen = pvh->pv_gen;
6005 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6010 PG_M = pmap_modified_bit(pmap);
6011 PG_RW = pmap_rw_bit(pmap);
6012 pde = pmap_pde(pmap, pv->pv_va);
6013 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6014 " a 2mpage in page %p's pv list", m));
6015 pte = pmap_pde_to_pte(pde, pv->pv_va);
6016 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6017 atomic_clear_long(pte, PG_M);
6018 pmap_invalidate_page(pmap, pv->pv_va);
6023 rw_runlock(&pvh_global_lock);
6027 * Miscellaneous support routines follow
6030 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6031 static __inline void
6032 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6037 * The cache mode bits are all in the low 32-bits of the
6038 * PTE, so we can just spin on updating the low 32-bits.
6041 opte = *(u_int *)pte;
6042 npte = opte & ~mask;
6044 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6047 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6048 static __inline void
6049 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6054 * The cache mode bits are all in the low 32-bits of the
6055 * PDE, so we can just spin on updating the low 32-bits.
6058 opde = *(u_int *)pde;
6059 npde = opde & ~mask;
6061 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6065 * Map a set of physical memory pages into the kernel virtual
6066 * address space. Return a pointer to where it is mapped. This
6067 * routine is intended to be used for mapping device memory,
6071 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6073 vm_offset_t va, offset;
6077 * If the specified range of physical addresses fits within the direct
6078 * map window, use the direct map.
6080 if (pa < dmaplimit && pa + size < dmaplimit) {
6081 va = PHYS_TO_DMAP(pa);
6082 if (!pmap_change_attr(va, size, mode))
6083 return ((void *)va);
6085 offset = pa & PAGE_MASK;
6086 size = round_page(offset + size);
6087 va = kva_alloc(size);
6089 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
6090 pa = trunc_page(pa);
6091 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6092 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6093 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6094 pmap_invalidate_cache_range(va, va + tmpsize);
6095 return ((void *)(va + offset));
6099 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6102 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6106 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6109 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6113 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6115 vm_offset_t base, offset;
6117 /* If we gave a direct map region in pmap_mapdev, do nothing */
6118 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6120 base = trunc_page(va);
6121 offset = va & PAGE_MASK;
6122 size = round_page(offset + size);
6123 kva_free(base, size);
6127 * Tries to demote a 1GB page mapping.
6130 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6132 pdp_entry_t newpdpe, oldpdpe;
6133 pd_entry_t *firstpde, newpde, *pde;
6134 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6138 PG_A = pmap_accessed_bit(pmap);
6139 PG_M = pmap_modified_bit(pmap);
6140 PG_V = pmap_valid_bit(pmap);
6141 PG_RW = pmap_rw_bit(pmap);
6143 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6145 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6146 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6147 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6148 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6149 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6150 " in pmap %p", va, pmap);
6153 mpdepa = VM_PAGE_TO_PHYS(mpde);
6154 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6155 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6156 KASSERT((oldpdpe & PG_A) != 0,
6157 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6158 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6159 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6163 * Initialize the page directory page.
6165 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6171 * Demote the mapping.
6176 * Invalidate a stale recursive mapping of the page directory page.
6178 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6180 pmap_pdpe_demotions++;
6181 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6182 " in pmap %p", va, pmap);
6187 * Sets the memory attribute for the specified page.
6190 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6193 m->md.pat_mode = ma;
6196 * If "m" is a normal page, update its direct mapping. This update
6197 * can be relied upon to perform any cache operations that are
6198 * required for data coherence.
6200 if ((m->flags & PG_FICTITIOUS) == 0 &&
6201 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6203 panic("memory attribute change on the direct map failed");
6207 * Changes the specified virtual address range's memory type to that given by
6208 * the parameter "mode". The specified virtual address range must be
6209 * completely contained within either the direct map or the kernel map. If
6210 * the virtual address range is contained within the kernel map, then the
6211 * memory type for each of the corresponding ranges of the direct map is also
6212 * changed. (The corresponding ranges of the direct map are those ranges that
6213 * map the same physical pages as the specified virtual address range.) These
6214 * changes to the direct map are necessary because Intel describes the
6215 * behavior of their processors as "undefined" if two or more mappings to the
6216 * same physical page have different memory types.
6218 * Returns zero if the change completed successfully, and either EINVAL or
6219 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6220 * of the virtual address range was not mapped, and ENOMEM is returned if
6221 * there was insufficient memory available to complete the change. In the
6222 * latter case, the memory type may have been changed on some part of the
6223 * virtual address range or the direct map.
6226 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6230 PMAP_LOCK(kernel_pmap);
6231 error = pmap_change_attr_locked(va, size, mode);
6232 PMAP_UNLOCK(kernel_pmap);
6237 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6239 vm_offset_t base, offset, tmpva;
6240 vm_paddr_t pa_start, pa_end;
6244 int cache_bits_pte, cache_bits_pde, error;
6247 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6248 base = trunc_page(va);
6249 offset = va & PAGE_MASK;
6250 size = round_page(offset + size);
6253 * Only supported on kernel virtual addresses, including the direct
6254 * map but excluding the recursive map.
6256 if (base < DMAP_MIN_ADDRESS)
6259 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6260 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6264 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6265 * into 4KB pages if required.
6267 for (tmpva = base; tmpva < base + size; ) {
6268 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6271 if (*pdpe & PG_PS) {
6273 * If the current 1GB page already has the required
6274 * memory type, then we need not demote this page. Just
6275 * increment tmpva to the next 1GB page frame.
6277 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6278 tmpva = trunc_1gpage(tmpva) + NBPDP;
6283 * If the current offset aligns with a 1GB page frame
6284 * and there is at least 1GB left within the range, then
6285 * we need not break down this page into 2MB pages.
6287 if ((tmpva & PDPMASK) == 0 &&
6288 tmpva + PDPMASK < base + size) {
6292 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6295 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6300 * If the current 2MB page already has the required
6301 * memory type, then we need not demote this page. Just
6302 * increment tmpva to the next 2MB page frame.
6304 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6305 tmpva = trunc_2mpage(tmpva) + NBPDR;
6310 * If the current offset aligns with a 2MB page frame
6311 * and there is at least 2MB left within the range, then
6312 * we need not break down this page into 4KB pages.
6314 if ((tmpva & PDRMASK) == 0 &&
6315 tmpva + PDRMASK < base + size) {
6319 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6322 pte = pmap_pde_to_pte(pde, tmpva);
6330 * Ok, all the pages exist, so run through them updating their
6331 * cache mode if required.
6333 pa_start = pa_end = 0;
6334 for (tmpva = base; tmpva < base + size; ) {
6335 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6336 if (*pdpe & PG_PS) {
6337 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6338 pmap_pde_attr(pdpe, cache_bits_pde,
6342 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6343 if (pa_start == pa_end) {
6344 /* Start physical address run. */
6345 pa_start = *pdpe & PG_PS_FRAME;
6346 pa_end = pa_start + NBPDP;
6347 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6350 /* Run ended, update direct map. */
6351 error = pmap_change_attr_locked(
6352 PHYS_TO_DMAP(pa_start),
6353 pa_end - pa_start, mode);
6356 /* Start physical address run. */
6357 pa_start = *pdpe & PG_PS_FRAME;
6358 pa_end = pa_start + NBPDP;
6361 tmpva = trunc_1gpage(tmpva) + NBPDP;
6364 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6366 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6367 pmap_pde_attr(pde, cache_bits_pde,
6371 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6372 if (pa_start == pa_end) {
6373 /* Start physical address run. */
6374 pa_start = *pde & PG_PS_FRAME;
6375 pa_end = pa_start + NBPDR;
6376 } else if (pa_end == (*pde & PG_PS_FRAME))
6379 /* Run ended, update direct map. */
6380 error = pmap_change_attr_locked(
6381 PHYS_TO_DMAP(pa_start),
6382 pa_end - pa_start, mode);
6385 /* Start physical address run. */
6386 pa_start = *pde & PG_PS_FRAME;
6387 pa_end = pa_start + NBPDR;
6390 tmpva = trunc_2mpage(tmpva) + NBPDR;
6392 pte = pmap_pde_to_pte(pde, tmpva);
6393 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6394 pmap_pte_attr(pte, cache_bits_pte,
6398 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6399 if (pa_start == pa_end) {
6400 /* Start physical address run. */
6401 pa_start = *pte & PG_FRAME;
6402 pa_end = pa_start + PAGE_SIZE;
6403 } else if (pa_end == (*pte & PG_FRAME))
6404 pa_end += PAGE_SIZE;
6406 /* Run ended, update direct map. */
6407 error = pmap_change_attr_locked(
6408 PHYS_TO_DMAP(pa_start),
6409 pa_end - pa_start, mode);
6412 /* Start physical address run. */
6413 pa_start = *pte & PG_FRAME;
6414 pa_end = pa_start + PAGE_SIZE;
6420 if (error == 0 && pa_start != pa_end)
6421 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6422 pa_end - pa_start, mode);
6425 * Flush CPU caches if required to make sure any data isn't cached that
6426 * shouldn't be, etc.
6429 pmap_invalidate_range(kernel_pmap, base, tmpva);
6430 pmap_invalidate_cache_range(base, tmpva);
6436 * Demotes any mapping within the direct map region that covers more than the
6437 * specified range of physical addresses. This range's size must be a power
6438 * of two and its starting address must be a multiple of its size. Since the
6439 * demotion does not change any attributes of the mapping, a TLB invalidation
6440 * is not mandatory. The caller may, however, request a TLB invalidation.
6443 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6452 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6453 KASSERT((base & (len - 1)) == 0,
6454 ("pmap_demote_DMAP: base is not a multiple of len"));
6455 if (len < NBPDP && base < dmaplimit) {
6456 va = PHYS_TO_DMAP(base);
6458 PMAP_LOCK(kernel_pmap);
6459 pdpe = pmap_pdpe(kernel_pmap, va);
6460 if ((*pdpe & X86_PG_V) == 0)
6461 panic("pmap_demote_DMAP: invalid PDPE");
6462 if ((*pdpe & PG_PS) != 0) {
6463 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6464 panic("pmap_demote_DMAP: PDPE failed");
6468 pde = pmap_pdpe_to_pde(pdpe, va);
6469 if ((*pde & X86_PG_V) == 0)
6470 panic("pmap_demote_DMAP: invalid PDE");
6471 if ((*pde & PG_PS) != 0) {
6472 if (!pmap_demote_pde(kernel_pmap, pde, va))
6473 panic("pmap_demote_DMAP: PDE failed");
6477 if (changed && invalidate)
6478 pmap_invalidate_page(kernel_pmap, va);
6479 PMAP_UNLOCK(kernel_pmap);
6484 * perform the pmap work for mincore
6487 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6490 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6494 PG_A = pmap_accessed_bit(pmap);
6495 PG_M = pmap_modified_bit(pmap);
6496 PG_V = pmap_valid_bit(pmap);
6497 PG_RW = pmap_rw_bit(pmap);
6501 pdep = pmap_pde(pmap, addr);
6502 if (pdep != NULL && (*pdep & PG_V)) {
6503 if (*pdep & PG_PS) {
6505 /* Compute the physical address of the 4KB page. */
6506 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6508 val = MINCORE_SUPER;
6510 pte = *pmap_pde_to_pte(pdep, addr);
6511 pa = pte & PG_FRAME;
6519 if ((pte & PG_V) != 0) {
6520 val |= MINCORE_INCORE;
6521 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6522 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6523 if ((pte & PG_A) != 0)
6524 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6526 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6527 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6528 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6529 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6530 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6533 PA_UNLOCK_COND(*locked_pa);
6539 pmap_activate(struct thread *td)
6541 pmap_t pmap, oldpmap;
6545 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6546 oldpmap = PCPU_GET(curpmap);
6547 cpuid = PCPU_GET(cpuid);
6549 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6550 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6551 CPU_SET_ATOMIC(cpuid, &pmap->pm_save);
6553 CPU_CLR(cpuid, &oldpmap->pm_active);
6554 CPU_SET(cpuid, &pmap->pm_active);
6555 CPU_SET(cpuid, &pmap->pm_save);
6557 td->td_pcb->pcb_cr3 = pmap->pm_cr3;
6558 load_cr3(pmap->pm_cr3);
6559 PCPU_SET(curpmap, pmap);
6564 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6569 * Increase the starting virtual address of the given mapping if a
6570 * different alignment might result in more superpage mappings.
6573 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6574 vm_offset_t *addr, vm_size_t size)
6576 vm_offset_t superpage_offset;
6580 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6581 offset += ptoa(object->pg_color);
6582 superpage_offset = offset & PDRMASK;
6583 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6584 (*addr & PDRMASK) == superpage_offset)
6586 if ((*addr & PDRMASK) < superpage_offset)
6587 *addr = (*addr & ~PDRMASK) + superpage_offset;
6589 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6593 static unsigned long num_dirty_emulations;
6594 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6595 &num_dirty_emulations, 0, NULL);
6597 static unsigned long num_accessed_emulations;
6598 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6599 &num_accessed_emulations, 0, NULL);
6601 static unsigned long num_superpage_accessed_emulations;
6602 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6603 &num_superpage_accessed_emulations, 0, NULL);
6605 static unsigned long ad_emulation_superpage_promotions;
6606 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6607 &ad_emulation_superpage_promotions, 0, NULL);
6608 #endif /* INVARIANTS */
6611 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6614 struct rwlock *lock;
6617 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
6618 boolean_t pv_lists_locked;
6620 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
6621 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
6623 if (!pmap_emulate_ad_bits(pmap))
6626 PG_A = pmap_accessed_bit(pmap);
6627 PG_M = pmap_modified_bit(pmap);
6628 PG_V = pmap_valid_bit(pmap);
6629 PG_RW = pmap_rw_bit(pmap);
6633 pv_lists_locked = FALSE;
6637 pde = pmap_pde(pmap, va);
6638 if (pde == NULL || (*pde & PG_V) == 0)
6641 if ((*pde & PG_PS) != 0) {
6642 if (ftype == VM_PROT_READ) {
6644 atomic_add_long(&num_superpage_accessed_emulations, 1);
6652 pte = pmap_pde_to_pte(pde, va);
6653 if ((*pte & PG_V) == 0)
6656 if (ftype == VM_PROT_WRITE) {
6657 if ((*pte & PG_RW) == 0)
6663 /* try to promote the mapping */
6664 if (va < VM_MAXUSER_ADDRESS)
6665 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6669 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6671 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
6672 pmap_ps_enabled(pmap) &&
6673 (m->flags & PG_FICTITIOUS) == 0 &&
6674 vm_reserv_level_iffullpop(m) == 0) {
6675 if (!pv_lists_locked) {
6676 pv_lists_locked = TRUE;
6677 if (!rw_try_rlock(&pvh_global_lock)) {
6679 rw_rlock(&pvh_global_lock);
6683 pmap_promote_pde(pmap, pde, va, &lock);
6685 atomic_add_long(&ad_emulation_superpage_promotions, 1);
6689 if (ftype == VM_PROT_WRITE)
6690 atomic_add_long(&num_dirty_emulations, 1);
6692 atomic_add_long(&num_accessed_emulations, 1);
6694 rv = 0; /* success */
6698 if (pv_lists_locked)
6699 rw_runlock(&pvh_global_lock);
6705 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
6710 pt_entry_t *pte, PG_V;
6714 PG_V = pmap_valid_bit(pmap);
6717 pml4 = pmap_pml4e(pmap, va);
6719 if ((*pml4 & PG_V) == 0)
6722 pdp = pmap_pml4e_to_pdpe(pml4, va);
6724 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
6727 pde = pmap_pdpe_to_pde(pdp, va);
6729 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
6732 pte = pmap_pde_to_pte(pde, va);
6740 #include "opt_ddb.h"
6742 #include <ddb/ddb.h>
6744 DB_SHOW_COMMAND(pte, pmap_print_pte)
6750 pt_entry_t *pte, PG_V;
6754 va = (vm_offset_t)addr;
6755 pmap = PCPU_GET(curpmap); /* XXX */
6757 db_printf("show pte addr\n");
6760 PG_V = pmap_valid_bit(pmap);
6761 pml4 = pmap_pml4e(pmap, va);
6762 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
6763 if ((*pml4 & PG_V) == 0) {
6767 pdp = pmap_pml4e_to_pdpe(pml4, va);
6768 db_printf(" pdpe %#016lx", *pdp);
6769 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
6773 pde = pmap_pdpe_to_pde(pdp, va);
6774 db_printf(" pde %#016lx", *pde);
6775 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
6779 pte = pmap_pde_to_pte(pde, va);
6780 db_printf(" pte %#016lx\n", *pte);
6783 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
6788 a = (vm_paddr_t)addr;
6789 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
6791 db_printf("show phys2dmap addr\n");