2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 * Copyright (C) 2012 Ian Lepore. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
41 #include <sys/selinfo.h>
44 #include <machine/at91_gpio.h>
45 #include <machine/bus.h>
47 #include <arm/at91/at91reg.h>
48 #include <arm/at91/at91_pioreg.h>
49 #include <arm/at91/at91_piovar.h>
55 device_t dev; /* Myself */
56 void *intrhand; /* Interrupt handle */
57 struct resource *irq_res; /* IRQ resource */
58 struct resource *mem_res; /* Memory resource */
59 struct sx sc_mtx; /* basically a perimeter lock */
63 uint8_t buf[MAX_CHANGE];
68 static inline uint32_t
69 RD4(struct at91_pio_softc *sc, bus_size_t off)
72 return (bus_read_4(sc->mem_res, off));
76 WR4(struct at91_pio_softc *sc, bus_size_t off, uint32_t val)
79 bus_write_4(sc->mem_res, off, val);
82 #define AT91_PIO_LOCK(_sc) sx_xlock(&(_sc)->sc_mtx)
83 #define AT91_PIO_UNLOCK(_sc) sx_xunlock(&(_sc)->sc_mtx)
84 #define AT91_PIO_LOCK_INIT(_sc) \
85 sx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev))
86 #define AT91_PIO_LOCK_DESTROY(_sc) sx_destroy(&_sc->sc_mtx);
87 #define AT91_PIO_ASSERT_LOCKED(_sc) sx_assert(&_sc->sc_mtx, SA_XLOCKED);
88 #define AT91_PIO_ASSERT_UNLOCKED(_sc) sx_assert(&_sc->sc_mtx, SA_UNLOCKED);
89 #define CDEV2SOFTC(dev) ((dev)->si_drv1)
91 static devclass_t at91_pio_devclass;
93 /* bus entry points */
95 static int at91_pio_probe(device_t dev);
96 static int at91_pio_attach(device_t dev);
97 static int at91_pio_detach(device_t dev);
98 static void at91_pio_intr(void *);
100 /* helper routines */
101 static int at91_pio_activate(device_t dev);
102 static void at91_pio_deactivate(device_t dev);
105 static d_open_t at91_pio_open;
106 static d_close_t at91_pio_close;
107 static d_read_t at91_pio_read;
108 static d_poll_t at91_pio_poll;
109 static d_ioctl_t at91_pio_ioctl;
111 static struct cdevsw at91_pio_cdevsw =
113 .d_version = D_VERSION,
114 .d_open = at91_pio_open,
115 .d_close = at91_pio_close,
116 .d_read = at91_pio_read,
117 .d_poll = at91_pio_poll,
118 .d_ioctl = at91_pio_ioctl
122 at91_pio_probe(device_t dev)
126 switch (device_get_unit(dev)) {
143 device_set_desc(dev, name);
148 at91_pio_attach(device_t dev)
150 struct at91_pio_softc *sc;
153 sc = device_get_softc(dev);
155 err = at91_pio_activate(dev);
160 device_printf(dev, "ABSR: %#x OSR: %#x PSR:%#x ODSR: %#x\n",
161 RD4(sc, PIO_ABSR), RD4(sc, PIO_OSR), RD4(sc, PIO_PSR),
163 AT91_PIO_LOCK_INIT(sc);
166 * Activate the interrupt, but disable all interrupts in the hardware.
168 WR4(sc, PIO_IDR, 0xffffffff);
169 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
170 NULL, at91_pio_intr, sc, &sc->intrhand);
172 AT91_PIO_LOCK_DESTROY(sc);
175 sc->cdev = make_dev(&at91_pio_cdevsw, device_get_unit(dev), UID_ROOT,
176 GID_WHEEL, 0600, "pio%d", device_get_unit(dev));
177 if (sc->cdev == NULL) {
181 sc->cdev->si_drv1 = sc;
184 at91_pio_deactivate(dev);
189 at91_pio_detach(device_t dev)
192 return (EBUSY); /* XXX */
196 at91_pio_activate(device_t dev)
198 struct at91_pio_softc *sc;
201 sc = device_get_softc(dev);
203 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
205 if (sc->mem_res == NULL)
208 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
209 RF_ACTIVE | RF_SHAREABLE);
210 if (sc->irq_res == NULL)
214 at91_pio_deactivate(dev);
219 at91_pio_deactivate(device_t dev)
221 struct at91_pio_softc *sc;
223 sc = device_get_softc(dev);
225 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
227 bus_generic_detach(sc->dev);
229 bus_release_resource(dev, SYS_RES_MEMORY,
230 rman_get_rid(sc->mem_res), sc->mem_res);
233 bus_release_resource(dev, SYS_RES_IRQ,
234 rman_get_rid(sc->irq_res), sc->irq_res);
239 at91_pio_intr(void *xsc)
241 struct at91_pio_softc *sc = xsc;
245 /* Reading the status also clears the interrupt. */
246 status = RD4(sc, PIO_ISR) & RD4(sc, PIO_IMR);
249 for (i = 0; status != 0 && sc->buflen < MAX_CHANGE; ++i) {
251 sc->buf[sc->buflen++] = (uint8_t)i;
256 selwakeup(&sc->selp);
261 at91_pio_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
263 struct at91_pio_softc *sc;
265 sc = CDEV2SOFTC(dev);
267 if (!(sc->flags & OPENED)) {
275 at91_pio_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
277 struct at91_pio_softc *sc;
279 sc = CDEV2SOFTC(dev);
281 sc->flags &= ~OPENED;
287 at91_pio_poll(struct cdev *dev, int events, struct thread *td)
289 struct at91_pio_softc *sc;
292 sc = CDEV2SOFTC(dev);
294 if (events & (POLLIN | POLLRDNORM)) {
296 revents |= events & (POLLIN | POLLRDNORM);
298 selrecord(td, &sc->selp);
306 at91_pio_read(struct cdev *dev, struct uio *uio, int flag)
308 struct at91_pio_softc *sc;
311 sc = CDEV2SOFTC(dev);
315 while (uio->uio_resid) {
316 while (sc->buflen == 0 && err == 0)
317 err = msleep(sc, &sc->sc_mtx, PCATCH | PZERO, "prd", 0);
320 len = MIN(sc->buflen, uio->uio_resid);
321 err = uiomove(sc->buf, len, uio);
325 * If we read the whole thing no datacopy is needed,
326 * otherwise we move the data down.
329 if (sc->buflen == len)
332 bcopy(sc->buf + len, sc->buf, sc->buflen - len);
335 /* If there's no data left, end the read. */
344 at91_pio_bang32(struct at91_pio_softc *sc, uint32_t bits, uint32_t datapin,
349 for (i = 0; i < 32; i++) {
350 if (bits & 0x80000000)
351 WR4(sc, PIO_SODR, datapin);
353 WR4(sc, PIO_CODR, datapin);
355 WR4(sc, PIO_CODR, clockpin);
356 WR4(sc, PIO_SODR, clockpin);
361 at91_pio_bang(struct at91_pio_softc *sc, uint8_t bits, uint32_t bitcount,
362 uint32_t datapin, uint32_t clockpin)
366 for (i = 0; i < bitcount; i++) {
368 WR4(sc, PIO_SODR, datapin);
370 WR4(sc, PIO_CODR, datapin);
372 WR4(sc, PIO_CODR, clockpin);
373 WR4(sc, PIO_SODR, clockpin);
378 at91_pio_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
381 struct at91_pio_softc *sc;
382 struct at91_gpio_cfg *cfg;
383 struct at91_gpio_info *info;
384 struct at91_gpio_bang *bang;
385 struct at91_gpio_bang_many *bangmany;
387 uint8_t many[1024], *walker;
391 sc = CDEV2SOFTC(dev);
393 case AT91_GPIO_SET: /* turn bits on */
394 WR4(sc, PIO_SODR, *(uint32_t *)data);
396 case AT91_GPIO_CLR: /* turn bits off */
397 WR4(sc, PIO_CODR, *(uint32_t *)data);
399 case AT91_GPIO_READ: /* Get the status of input bits */
400 *(uint32_t *)data = RD4(sc, PIO_PDSR);
402 case AT91_GPIO_CFG: /* Configure AT91_GPIO pins */
403 cfg = (struct at91_gpio_cfg *)data;
404 if (cfg->cfgmask & AT91_GPIO_CFG_INPUT) {
405 WR4(sc, PIO_OER, cfg->iomask & ~cfg->input);
406 WR4(sc, PIO_ODR, cfg->iomask & cfg->input);
408 if (cfg->cfgmask & AT91_GPIO_CFG_HI_Z) {
409 WR4(sc, PIO_MDDR, cfg->iomask & ~cfg->hi_z);
410 WR4(sc, PIO_MDER, cfg->iomask & cfg->hi_z);
412 if (cfg->cfgmask & AT91_GPIO_CFG_PULLUP) {
413 WR4(sc, PIO_PUDR, cfg->iomask & ~cfg->pullup);
414 WR4(sc, PIO_PUER, cfg->iomask & cfg->pullup);
416 if (cfg->cfgmask & AT91_GPIO_CFG_GLITCH) {
417 WR4(sc, PIO_IFDR, cfg->iomask & ~cfg->glitch);
418 WR4(sc, PIO_IFER, cfg->iomask & cfg->glitch);
420 if (cfg->cfgmask & AT91_GPIO_CFG_GPIO) {
421 WR4(sc, PIO_PDR, cfg->iomask & ~cfg->gpio);
422 WR4(sc, PIO_PER, cfg->iomask & cfg->gpio);
424 if (cfg->cfgmask & AT91_GPIO_CFG_PERIPH) {
425 WR4(sc, PIO_ASR, cfg->iomask & ~cfg->periph);
426 WR4(sc, PIO_BSR, cfg->iomask & cfg->periph);
428 if (cfg->cfgmask & AT91_GPIO_CFG_INTR) {
429 WR4(sc, PIO_IDR, cfg->iomask & ~cfg->intr);
430 WR4(sc, PIO_IER, cfg->iomask & cfg->intr);
434 bang = (struct at91_gpio_bang *)data;
435 at91_pio_bang32(sc, bang->bits, bang->datapin, bang->clockpin);
437 case AT91_GPIO_BANG_MANY:
438 bangmany = (struct at91_gpio_bang_many *)data;
439 walker = (uint8_t *)bangmany->bits;
440 bitcount = bangmany->numbits;
441 while (bitcount > 0) {
442 num = MIN((bitcount + 7) / 8, sizeof(many));
443 err = copyin(walker, many, num);
446 for (i = 0; i < num && bitcount > 0; i++, bitcount -= 8)
448 at91_pio_bang(sc, many[i], 8, bangmany->datapin, bangmany->clockpin);
450 at91_pio_bang(sc, many[i], bitcount, bangmany->datapin, bangmany->clockpin);
454 case AT91_GPIO_INFO: /* Learn about this device's AT91_GPIO bits */
455 info = (struct at91_gpio_info *)data;
456 info->output_status = RD4(sc, PIO_ODSR);
457 info->input_status = RD4(sc, PIO_OSR);
458 info->highz_status = RD4(sc, PIO_MDSR);
459 info->pullup_status = RD4(sc, PIO_PUSR);
460 info->glitch_status = RD4(sc, PIO_IFSR);
461 info->enabled_status = RD4(sc, PIO_PSR);
462 info->periph_status = RD4(sc, PIO_ABSR);
463 info->intr_status = RD4(sc, PIO_IMR);
464 memset(info->extra_status, 0, sizeof(info->extra_status));
471 * The following functions are called early in the boot process, so
472 * don't use bus_space, as that isn't yet available when we need to use
477 at91_pio_use_periph_a(uint32_t pio, uint32_t periph_a_mask, int use_pullup)
479 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
481 PIO[PIO_ASR / 4] = periph_a_mask;
482 PIO[PIO_PDR / 4] = periph_a_mask;
484 PIO[PIO_PUER / 4] = periph_a_mask;
486 PIO[PIO_PUDR / 4] = periph_a_mask;
490 at91_pio_use_periph_b(uint32_t pio, uint32_t periph_b_mask, int use_pullup)
492 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
494 PIO[PIO_BSR / 4] = periph_b_mask;
495 PIO[PIO_PDR / 4] = periph_b_mask;
497 PIO[PIO_PUER / 4] = periph_b_mask;
499 PIO[PIO_PUDR / 4] = periph_b_mask;
503 at91_pio_use_gpio(uint32_t pio, uint32_t gpio_mask)
505 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
507 PIO[PIO_PER / 4] = gpio_mask;
511 at91_pio_gpio_input(uint32_t pio, uint32_t input_enable_mask)
513 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
515 PIO[PIO_ODR / 4] = input_enable_mask;
519 at91_pio_gpio_output(uint32_t pio, uint32_t output_enable_mask, int use_pullup)
521 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
523 PIO[PIO_OER / 4] = output_enable_mask;
525 PIO[PIO_PUER / 4] = output_enable_mask;
527 PIO[PIO_PUDR / 4] = output_enable_mask;
531 at91_pio_gpio_high_z(uint32_t pio, uint32_t high_z_mask, int enable)
533 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
536 PIO[PIO_MDER / 4] = high_z_mask;
538 PIO[PIO_MDDR / 4] = high_z_mask;
542 at91_pio_gpio_set(uint32_t pio, uint32_t data_mask)
544 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
546 PIO[PIO_SODR / 4] = data_mask;
550 at91_pio_gpio_clear(uint32_t pio, uint32_t data_mask)
552 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
554 PIO[PIO_CODR / 4] = data_mask;
558 at91_pio_gpio_get(uint32_t pio, uint32_t data_mask)
560 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
562 return (PIO[PIO_PDSR / 4] & data_mask);
566 at91_pio_gpio_set_deglitch(uint32_t pio, uint32_t data_mask, int use_deglitch)
568 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
571 PIO[PIO_IFER / 4] = data_mask;
573 PIO[PIO_IFDR / 4] = data_mask;
577 at91_pio_gpio_set_interrupt(uint32_t pio, uint32_t data_mask,
578 int enable_interrupt)
580 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
582 if (enable_interrupt)
583 PIO[PIO_IER / 4] = data_mask;
585 PIO[PIO_IDR / 4] = data_mask;
589 at91_pio_gpio_clear_interrupt(uint32_t pio)
591 uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
593 /* Reading this register will clear the interrupts. */
594 return (PIO[PIO_ISR / 4]);
597 static device_method_t at91_pio_methods[] = {
598 /* Device interface */
599 DEVMETHOD(device_probe, at91_pio_probe),
600 DEVMETHOD(device_attach, at91_pio_attach),
601 DEVMETHOD(device_detach, at91_pio_detach),
606 static driver_t at91_pio_driver = {
609 sizeof(struct at91_pio_softc),
612 DRIVER_MODULE(at91_pio, atmelarm, at91_pio_driver, at91_pio_devclass, NULL,