2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <dev/mmc/bridge.h>
49 #include <dev/mmc/mmcreg.h>
51 #include <dev/sdhci/sdhci.h>
56 #include "bcm2835_dma.h"
57 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
58 #include "bcm2835_vcbus.h"
60 #define BCM2835_DEFAULT_SDHCI_FREQ 50
62 #define BCM_SDHCI_BUFFER_SIZE 512
63 #define NUM_DMA_SEGS 2
66 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
67 printf(fmt,##args); } while (0)
69 #define dprintf(fmt, args...)
72 static int bcm2835_sdhci_hs = 1;
73 static int bcm2835_sdhci_pio_mode = 0;
75 static struct ofw_compat_data compat_data[] = {
76 {"broadcom,bcm2835-sdhci", 1},
77 {"brcm,bcm2835-mmc", 1},
81 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
82 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
84 struct bcm_sdhci_softc {
86 struct resource * sc_mem_res;
87 struct resource * sc_irq_res;
88 bus_space_tag_t sc_bst;
89 bus_space_handle_t sc_bsh;
91 struct mmc_request * sc_req;
92 struct sdhci_slot sc_slot;
94 bus_dma_tag_t sc_dma_tag;
95 bus_dmamap_t sc_dma_map;
96 vm_paddr_t sc_sdhci_buffer_phys;
97 uint32_t cmd_and_mode;
98 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS];
99 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS];
100 int dmamap_seg_count;
101 int dmamap_seg_index;
105 static int bcm_sdhci_probe(device_t);
106 static int bcm_sdhci_attach(device_t);
107 static int bcm_sdhci_detach(device_t);
108 static void bcm_sdhci_intr(void *);
110 static int bcm_sdhci_get_ro(device_t, device_t);
111 static void bcm_sdhci_dma_intr(int ch, void *arg);
114 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
116 struct bcm_sdhci_softc *sc = arg;
119 sc->dmamap_status = err;
120 sc->dmamap_seg_count = nseg;
122 /* Note nseg is guaranteed to be zero if err is non-zero. */
123 for (i = 0; i < nseg; i++) {
124 sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
125 sc->dmamap_seg_sizes[i] = segs[i].ds_len;
130 bcm_sdhci_probe(device_t dev)
133 if (!ofw_bus_status_okay(dev))
136 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
139 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
141 return (BUS_PROBE_DEFAULT);
145 bcm_sdhci_attach(device_t dev)
147 struct bcm_sdhci_softc *sc = device_get_softc(dev);
156 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC,
160 device_printf(dev, "Unable to enable the power\n");
165 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC,
169 default_freq /= 1000000;
171 if (default_freq == 0) {
172 node = ofw_bus_get_node(sc->sc_dev);
173 if ((OF_getencprop(node, "clock-frequency", &cell,
175 default_freq = cell / 1000000;
177 if (default_freq == 0)
178 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
181 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq);
184 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
186 if (!sc->sc_mem_res) {
187 device_printf(dev, "cannot allocate memory window\n");
192 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
193 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
196 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
198 if (!sc->sc_irq_res) {
199 device_printf(dev, "cannot allocate interrupt\n");
204 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
205 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
206 device_printf(dev, "cannot setup interrupt handler\n");
211 if (!bcm2835_sdhci_pio_mode)
212 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
214 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
215 if (bcm2835_sdhci_hs)
216 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
217 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
218 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
219 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
220 | SDHCI_QUIRK_DONT_SET_HISPD_BIT
221 | SDHCI_QUIRK_MISSING_CAPS;
223 sdhci_init_slot(dev, &sc->sc_slot, 0);
225 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
226 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
229 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
231 /* Allocate bus_dma resources. */
232 err = bus_dma_tag_create(bus_get_dma_tag(dev),
233 1, 0, BUS_SPACE_MAXADDR_32BIT,
234 BUS_SPACE_MAXADDR, NULL, NULL,
235 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
236 BUS_DMA_ALLOCNOW, NULL, NULL,
240 device_printf(dev, "failed allocate DMA tag");
244 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
246 device_printf(dev, "bus_dmamap_create failed\n");
250 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
253 bus_generic_probe(dev);
254 bus_generic_attach(dev);
256 sdhci_start_slot(&sc->sc_slot);
262 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
264 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
266 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
272 bcm_sdhci_detach(device_t dev)
279 bcm_sdhci_intr(void *arg)
281 struct bcm_sdhci_softc *sc = arg;
283 sdhci_generic_intr(&sc->sc_slot);
287 bcm_sdhci_get_ro(device_t bus, device_t child)
293 static inline uint32_t
294 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
296 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
301 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
304 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
306 * The Arasan HC has a bug where it may lose the content of
307 * consecutive writes to registers that are within two SD-card
308 * clock cycles of each other (a clock domain crossing problem).
310 if (sc->sc_slot.clock > 0)
311 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
315 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
317 struct bcm_sdhci_softc *sc = device_get_softc(dev);
318 uint32_t val = RD4(sc, off & ~3);
320 return ((val >> (off & 3)*8) & 0xff);
324 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
326 struct bcm_sdhci_softc *sc = device_get_softc(dev);
327 uint32_t val = RD4(sc, off & ~3);
330 * Standard 32-bit handling of command and transfer mode.
332 if (off == SDHCI_TRANSFER_MODE) {
333 return (sc->cmd_and_mode >> 16);
334 } else if (off == SDHCI_COMMAND_FLAGS) {
335 return (sc->cmd_and_mode & 0x0000ffff);
337 return ((val >> (off & 3)*8) & 0xffff);
341 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
343 struct bcm_sdhci_softc *sc = device_get_softc(dev);
349 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
350 uint32_t *data, bus_size_t count)
352 struct bcm_sdhci_softc *sc = device_get_softc(dev);
354 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
358 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
360 struct bcm_sdhci_softc *sc = device_get_softc(dev);
361 uint32_t val32 = RD4(sc, off & ~3);
362 val32 &= ~(0xff << (off & 3)*8);
363 val32 |= (val << (off & 3)*8);
364 WR4(sc, off & ~3, val32);
368 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
370 struct bcm_sdhci_softc *sc = device_get_softc(dev);
372 if (off == SDHCI_COMMAND_FLAGS)
373 val32 = sc->cmd_and_mode;
375 val32 = RD4(sc, off & ~3);
376 val32 &= ~(0xffff << (off & 3)*8);
377 val32 |= (val << (off & 3)*8);
378 if (off == SDHCI_TRANSFER_MODE)
379 sc->cmd_and_mode = val32;
381 WR4(sc, off & ~3, val32);
382 if (off == SDHCI_COMMAND_FLAGS)
383 sc->cmd_and_mode = val32;
388 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
390 struct bcm_sdhci_softc *sc = device_get_softc(dev);
395 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
396 uint32_t *data, bus_size_t count)
398 struct bcm_sdhci_softc *sc = device_get_softc(dev);
400 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
404 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
406 struct sdhci_slot *slot;
407 vm_paddr_t pdst, psrc;
408 int err, idx, len, sync_op;
411 idx = sc->dmamap_seg_index++;
412 len = sc->dmamap_seg_sizes[idx];
415 if (slot->curcmd->data->flags & MMC_DATA_READ) {
416 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
417 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
418 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
420 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
421 psrc = sc->sc_sdhci_buffer_phys;
422 pdst = sc->dmamap_seg_addrs[idx];
423 sync_op = BUS_DMASYNC_PREREAD;
425 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
427 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
428 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
429 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
430 psrc = sc->dmamap_seg_addrs[idx];
431 pdst = sc->sc_sdhci_buffer_phys;
432 sync_op = BUS_DMASYNC_PREWRITE;
436 * When starting a new DMA operation do the busdma sync operation, and
437 * disable SDCHI data interrrupts because we'll be driven by DMA
438 * interrupts (or SDHCI error interrupts) until the IO is done.
441 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
442 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
443 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
444 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
449 * Start the DMA transfer. Only programming errors (like failing to
450 * allocate a channel) cause a non-zero return from bcm_dma_start().
452 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
453 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
457 bcm_sdhci_dma_intr(int ch, void *arg)
459 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
460 struct sdhci_slot *slot = &sc->sc_slot;
464 mtx_lock(&slot->mtx);
467 * If there are more segments for the current dma, start the next one.
468 * Otherwise unload the dma map and decide what to do next based on the
469 * status of the sdhci controller and whether there's more data left.
471 if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
472 bcm_sdhci_start_dma_seg(sc);
473 mtx_unlock(&slot->mtx);
477 if (slot->curcmd->data->flags & MMC_DATA_READ) {
478 sync_op = BUS_DMASYNC_POSTREAD;
479 mask = SDHCI_INT_DATA_AVAIL;
481 sync_op = BUS_DMASYNC_POSTWRITE;
482 mask = SDHCI_INT_SPACE_AVAIL;
484 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
485 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
487 sc->dmamap_seg_count = 0;
488 sc->dmamap_seg_index = 0;
490 left = min(BCM_SDHCI_BUFFER_SIZE,
491 slot->curcmd->data->len - slot->offset);
494 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
496 if (reg & SDHCI_INT_DATA_END) {
497 /* ACK for all outstanding interrupts */
498 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
501 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
502 | SDHCI_INT_DATA_END;
503 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
506 /* finish this data */
507 sdhci_finish_data(slot);
510 /* already available? */
513 /* ACK for DATA_AVAIL or SPACE_AVAIL */
514 bcm_sdhci_write_4(slot->bus, slot,
515 SDHCI_INT_STATUS, mask);
517 /* continue next DMA transfer */
518 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
519 (uint8_t *)slot->curcmd->data->data +
520 slot->offset, left, bcm_sdhci_dmacb, sc,
521 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
522 slot->curcmd->error = MMC_ERR_NO_MEMORY;
523 sdhci_finish_data(slot);
525 bcm_sdhci_start_dma_seg(sc);
528 /* wait for next data by INT */
531 slot->intmask |= SDHCI_INT_DATA_AVAIL |
532 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
533 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
538 mtx_unlock(&slot->mtx);
542 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
544 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
547 if (sc->dmamap_seg_count != 0) {
548 device_printf(sc->sc_dev, "DMA in use\n");
552 left = min(BCM_SDHCI_BUFFER_SIZE,
553 slot->curcmd->data->len - slot->offset);
555 KASSERT((left & 3) == 0,
556 ("%s: len = %d, not word-aligned", __func__, left));
558 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
559 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
560 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
561 sc->dmamap_status != 0) {
562 slot->curcmd->error = MMC_ERR_NO_MEMORY;
567 bcm_sdhci_start_dma_seg(sc);
571 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
573 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
576 if (sc->dmamap_seg_count != 0) {
577 device_printf(sc->sc_dev, "DMA in use\n");
581 left = min(BCM_SDHCI_BUFFER_SIZE,
582 slot->curcmd->data->len - slot->offset);
584 KASSERT((left & 3) == 0,
585 ("%s: len = %d, not word-aligned", __func__, left));
587 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
588 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
589 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
590 sc->dmamap_status != 0) {
591 slot->curcmd->error = MMC_ERR_NO_MEMORY;
596 bcm_sdhci_start_dma_seg(sc);
600 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
605 * Do not use DMA for transfers less than block size or with a length
606 * that is not a multiple of four.
608 left = min(BCM_DMA_BLOCK_SIZE,
609 slot->curcmd->data->len - slot->offset);
610 if (left < BCM_DMA_BLOCK_SIZE)
619 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
623 /* DMA transfer FIFO 1KB */
624 if (slot->curcmd->data->flags & MMC_DATA_READ)
625 bcm_sdhci_read_dma(dev, slot);
627 bcm_sdhci_write_dma(dev, slot);
631 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
634 sdhci_finish_data(slot);
637 static device_method_t bcm_sdhci_methods[] = {
638 /* Device interface */
639 DEVMETHOD(device_probe, bcm_sdhci_probe),
640 DEVMETHOD(device_attach, bcm_sdhci_attach),
641 DEVMETHOD(device_detach, bcm_sdhci_detach),
644 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
645 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
647 /* MMC bridge interface */
648 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
649 DEVMETHOD(mmcbr_request, sdhci_generic_request),
650 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
651 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
652 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
654 /* Platform transfer methods */
655 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
656 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
657 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
658 /* SDHCI registers accessors */
659 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
660 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
661 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
662 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
663 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
664 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
665 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
666 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
671 static devclass_t bcm_sdhci_devclass;
673 static driver_t bcm_sdhci_driver = {
676 sizeof(struct bcm_sdhci_softc),
679 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass,
681 SDHCI_DEPEND(sdhci_bcm);
682 MMC_DECLARE_BRIDGE(sdhci_bcm);