2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/kthread.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/queue.h>
43 #include <sys/resource.h>
46 #include <sys/timetc.h>
47 #include <sys/watchdog.h>
51 #include <machine/bus.h>
52 #include <machine/cpu.h>
53 #include <machine/cpufunc.h>
54 #include <machine/resource.h>
55 #include <machine/intr.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_bus_subr.h>
60 #include <dev/mmc/bridge.h>
61 #include <dev/mmc/mmcreg.h>
62 #include <dev/mmc/mmcbrvar.h>
64 #include <arm/lpc/lpcreg.h>
65 #include <arm/lpc/lpcvar.h>
68 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
69 printf(fmt,##args); } while (0)
71 #define debugf(fmt, args...)
74 struct lpc_mmc_dmamap_arg {
75 bus_addr_t lm_dma_busaddr;
78 struct lpc_mmc_softc {
81 struct resource * lm_mem_res;
82 struct resource * lm_irq_res;
83 bus_space_tag_t lm_bst;
84 bus_space_handle_t lm_bsh;
86 struct mmc_host lm_host;
87 struct mmc_request * lm_req;
88 struct mmc_data * lm_data;
90 #define LPC_SD_FLAGS_IGNORECRC (1 << 0)
91 int lm_xfer_direction;
92 #define DIRECTION_READ 0
93 #define DIRECTION_WRITE 1
96 bus_dma_tag_t lm_dma_tag;
97 bus_dmamap_t lm_dma_map;
98 bus_addr_t lm_buffer_phys;
102 #define LPC_SD_MAX_BLOCKSIZE 1024
104 #define LPC_MMC_DMACH_READ 1
105 #define LPC_MMC_DMACH_WRITE 0
108 static int lpc_mmc_probe(device_t);
109 static int lpc_mmc_attach(device_t);
110 static int lpc_mmc_detach(device_t);
111 static void lpc_mmc_intr(void *);
113 static void lpc_mmc_cmd(struct lpc_mmc_softc *, struct mmc_command *);
114 static void lpc_mmc_setup_xfer(struct lpc_mmc_softc *, struct mmc_data *);
116 static int lpc_mmc_update_ios(device_t, device_t);
117 static int lpc_mmc_request(device_t, device_t, struct mmc_request *);
118 static int lpc_mmc_get_ro(device_t, device_t);
119 static int lpc_mmc_acquire_host(device_t, device_t);
120 static int lpc_mmc_release_host(device_t, device_t);
122 static void lpc_mmc_dma_rxfinish(void *);
123 static void lpc_mmc_dma_rxerror(void *);
124 static void lpc_mmc_dma_txfinish(void *);
125 static void lpc_mmc_dma_txerror(void *);
127 static void lpc_mmc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
129 #define lpc_mmc_lock(_sc) \
130 mtx_lock(&_sc->lm_mtx);
131 #define lpc_mmc_unlock(_sc) \
132 mtx_unlock(&_sc->lm_mtx);
133 #define lpc_mmc_read_4(_sc, _reg) \
134 bus_space_read_4(_sc->lm_bst, _sc->lm_bsh, _reg)
135 #define lpc_mmc_write_4(_sc, _reg, _value) \
136 bus_space_write_4(_sc->lm_bst, _sc->lm_bsh, _reg, _value)
138 static struct lpc_dmac_channel_config lpc_mmc_dma_rxconf = {
139 .ldc_fcntl = LPC_DMAC_FLOW_D_P2M,
140 .ldc_src_periph = LPC_DMAC_SD_ID,
141 .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
143 .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
144 .ldc_dst_periph = LPC_DMAC_SD_ID,
145 .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
147 .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
148 .ldc_success_handler = lpc_mmc_dma_rxfinish,
149 .ldc_error_handler = lpc_mmc_dma_rxerror,
152 static struct lpc_dmac_channel_config lpc_mmc_dma_txconf = {
153 .ldc_fcntl = LPC_DMAC_FLOW_P_M2P,
154 .ldc_src_periph = LPC_DMAC_SD_ID,
155 .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
157 .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
158 .ldc_dst_periph = LPC_DMAC_SD_ID,
159 .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
161 .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
162 .ldc_success_handler = lpc_mmc_dma_txfinish,
163 .ldc_error_handler = lpc_mmc_dma_txerror,
167 lpc_mmc_probe(device_t dev)
169 if (!ofw_bus_is_compatible(dev, "lpc,mmc"))
172 device_set_desc(dev, "LPC32x0 MMC/SD controller");
173 return (BUS_PROBE_DEFAULT);
177 lpc_mmc_attach(device_t dev)
179 struct lpc_mmc_softc *sc = device_get_softc(dev);
180 struct lpc_mmc_dmamap_arg ctx;
187 mtx_init(&sc->lm_mtx, "lpcmmc", "mmc", MTX_DEF);
190 sc->lm_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
192 if (!sc->lm_mem_res) {
193 device_printf(dev, "cannot allocate memory window\n");
197 sc->lm_bst = rman_get_bustag(sc->lm_mem_res);
198 sc->lm_bsh = rman_get_bushandle(sc->lm_mem_res);
200 debugf("virtual register space: 0x%08lx\n", sc->lm_bsh);
203 sc->lm_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
205 if (!sc->lm_irq_res) {
206 device_printf(dev, "cannot allocate interrupt\n");
207 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
211 if (bus_setup_intr(dev, sc->lm_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
212 NULL, lpc_mmc_intr, sc, &sc->lm_intrhand))
214 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
215 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
216 device_printf(dev, "cannot setup interrupt handler\n");
220 sc->lm_host.f_min = 312500;
221 sc->lm_host.f_max = 2500000;
222 sc->lm_host.host_ocr = MMC_OCR_300_310 | MMC_OCR_310_320 |
223 MMC_OCR_320_330 | MMC_OCR_330_340;
225 sc->lm_host.caps = MMC_CAP_4_BIT_DATA;
228 lpc_pwr_write(dev, LPC_CLKPWR_MS_CTRL,
229 LPC_CLKPWR_MS_CTRL_CLOCK_EN | LPC_CLKPWR_MS_CTRL_SD_CLOCK | 1);
230 lpc_mmc_write_4(sc, LPC_SD_POWER, LPC_SD_POWER_CTRL_ON);
232 device_set_ivars(dev, &sc->lm_host);
234 child = device_add_child(dev, "mmc", -1);
236 device_printf(dev, "attaching MMC bus failed!\n");
237 bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
238 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
239 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
243 /* Alloc DMA memory */
244 err = bus_dma_tag_create(
245 bus_get_dma_tag(sc->lm_dev),
246 4, 0, /* alignment, boundary */
247 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
248 BUS_SPACE_MAXADDR, /* highaddr */
249 NULL, NULL, /* filter, filterarg */
250 LPC_SD_MAX_BLOCKSIZE, 1, /* maxsize, nsegments */
251 LPC_SD_MAX_BLOCKSIZE, 0, /* maxsegsize, flags */
252 NULL, NULL, /* lockfunc, lockarg */
255 err = bus_dmamem_alloc(sc->lm_dma_tag, (void **)&sc->lm_buffer,
258 device_printf(dev, "cannot allocate framebuffer\n");
262 err = bus_dmamap_load(sc->lm_dma_tag, sc->lm_dma_map, sc->lm_buffer,
263 LPC_SD_MAX_BLOCKSIZE, lpc_mmc_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
265 device_printf(dev, "cannot load DMA map\n");
269 sc->lm_buffer_phys = ctx.lm_dma_busaddr;
271 lpc_mmc_dma_rxconf.ldc_handler_arg = (void *)sc;
272 err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_READ, &lpc_mmc_dma_rxconf);
274 device_printf(dev, "cannot allocate RX DMA channel\n");
279 lpc_mmc_dma_txconf.ldc_handler_arg = (void *)sc;
280 err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_WRITE, &lpc_mmc_dma_txconf);
282 device_printf(dev, "cannot allocate TX DMA channel\n");
286 bus_generic_probe(dev);
287 bus_generic_attach(dev);
293 bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
295 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
297 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
302 lpc_mmc_detach(device_t dev)
308 lpc_mmc_intr(void *arg)
310 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
311 struct mmc_command *cmd;
314 status = lpc_mmc_read_4(sc, LPC_SD_STATUS);
316 debugf("interrupt: 0x%08x\n", status);
318 if (status & LPC_SD_STATUS_CMDCRCFAIL) {
319 cmd = sc->lm_req->cmd;
320 cmd->error = sc->lm_flags & LPC_SD_FLAGS_IGNORECRC
321 ? MMC_ERR_NONE : MMC_ERR_BADCRC;
322 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
323 sc->lm_req->done(sc->lm_req);
325 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDCRCFAIL);
328 if (status & LPC_SD_STATUS_CMDACTIVE)
330 debugf("command active\n");
331 cmd = sc->lm_req->cmd;
332 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
333 sc->lm_req->done(sc->lm_req);
337 if (status & LPC_SD_STATUS_DATATIMEOUT) {
338 device_printf(sc->lm_dev, "data timeout\n");
339 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATATIMEOUT);
342 if (status & LPC_SD_STATUS_TXUNDERRUN) {
343 device_printf(sc->lm_dev, "TX underrun\n");
344 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_TXUNDERRUN);
347 if (status & LPC_SD_STATUS_CMDRESPEND) {
348 debugf("command response\n");
349 cmd = sc->lm_req->cmd;
351 if (cmd->flags & MMC_RSP_136) {
352 cmd->resp[3] = lpc_mmc_read_4(sc, LPC_SD_RESP3);
353 cmd->resp[2] = lpc_mmc_read_4(sc, LPC_SD_RESP2);
354 cmd->resp[1] = lpc_mmc_read_4(sc, LPC_SD_RESP1);
357 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
358 cmd->error = MMC_ERR_NONE;
360 if (cmd->data && (cmd->data->flags & MMC_DATA_WRITE))
361 lpc_mmc_setup_xfer(sc, sc->lm_req->cmd->data);
364 sc->lm_req->done(sc->lm_req);
368 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDRESPEND);
371 if (status & LPC_SD_STATUS_CMDSENT) {
372 debugf("command sent\n");
373 cmd = sc->lm_req->cmd;
374 cmd->error = MMC_ERR_NONE;
375 sc->lm_req->done(sc->lm_req);
377 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDSENT);
380 if (status & LPC_SD_STATUS_DATAEND) {
381 if (sc->lm_xfer_direction == DIRECTION_READ)
382 lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
384 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATAEND);
387 if (status & LPC_SD_STATUS_CMDTIMEOUT) {
388 device_printf(sc->lm_dev, "command response timeout\n");
389 cmd = sc->lm_req->cmd;
390 cmd->error = MMC_ERR_TIMEOUT;
391 sc->lm_req->done(sc->lm_req);
393 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDTIMEOUT);
397 if (status & LPC_SD_STATUS_STARTBITERR) {
398 device_printf(sc->lm_dev, "start bit error\n");
399 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_STARTBITERR);
402 if (status & LPC_SD_STATUS_DATACRCFAIL) {
403 device_printf(sc->lm_dev, "data CRC error\n");
404 debugf("data buffer: %p\n", sc->lm_buffer);
405 cmd = sc->lm_req->cmd;
406 cmd->error = MMC_ERR_BADCRC;
407 sc->lm_req->done(sc->lm_req);
410 if (sc->lm_xfer_direction == DIRECTION_READ)
411 lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
413 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATACRCFAIL);
416 if (status & LPC_SD_STATUS_DATABLOCKEND) {
417 debugf("data block end\n");
418 if (sc->lm_xfer_direction == DIRECTION_READ)
419 memcpy(sc->lm_data->data, sc->lm_buffer, sc->lm_data->len);
421 if (sc->lm_xfer_direction == DIRECTION_WRITE) {
422 lpc_dmac_disable_channel(sc->lm_dev, LPC_MMC_DMACH_WRITE);
423 lpc_mmc_write_4(sc, LPC_SD_DATACTRL, 0);
426 sc->lm_req->done(sc->lm_req);
428 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATABLOCKEND);
435 lpc_mmc_request(device_t bus, device_t child, struct mmc_request *req)
437 struct lpc_mmc_softc *sc = device_get_softc(bus);
439 debugf("request: %p\n", req);
447 if (req->cmd->data && req->cmd->data->flags & MMC_DATA_WRITE) {
448 memcpy(sc->lm_buffer, req->cmd->data->data, req->cmd->data->len);
449 lpc_mmc_cmd(sc, req->cmd);
455 lpc_mmc_setup_xfer(sc, req->cmd->data);
457 lpc_mmc_cmd(sc, req->cmd);
464 lpc_mmc_cmd(struct lpc_mmc_softc *sc, struct mmc_command *cmd)
468 debugf("cmd: %d arg: 0x%08x\n", cmd->opcode, cmd->arg);
470 if (lpc_mmc_read_4(sc, LPC_SD_COMMAND) & LPC_SD_COMMAND_ENABLE) {
471 lpc_mmc_write_4(sc, LPC_SD_COMMAND, 0);
475 sc->lm_flags &= ~LPC_SD_FLAGS_IGNORECRC;
477 if (cmd->flags & MMC_RSP_PRESENT)
478 cmdreg |= LPC_SD_COMMAND_RESPONSE;
480 if (MMC_RSP(cmd->flags) == MMC_RSP_R2)
481 cmdreg |= LPC_SD_COMMAND_LONGRSP;
483 if (MMC_RSP(cmd->flags) == MMC_RSP_R3)
484 sc->lm_flags |= LPC_SD_FLAGS_IGNORECRC;
486 cmdreg |= LPC_SD_COMMAND_ENABLE;
487 cmdreg |= (cmd->opcode & LPC_SD_COMMAND_CMDINDEXMASK);
489 lpc_mmc_write_4(sc, LPC_SD_MASK0, 0xffffffff);
490 lpc_mmc_write_4(sc, LPC_SD_MASK1, 0xffffffff);
491 lpc_mmc_write_4(sc, LPC_SD_ARGUMENT, cmd->arg);
492 lpc_mmc_write_4(sc, LPC_SD_COMMAND, cmdreg);
496 lpc_mmc_setup_xfer(struct lpc_mmc_softc *sc, struct mmc_data *data)
498 uint32_t datactrl = 0;
499 int data_words = data->len / 4;
502 sc->lm_xfer_done = 0;
504 debugf("data: %p, len: %d, %s\n", data,
505 data->len, (data->flags & MMC_DATA_READ) ? "read" : "write");
507 if (data->flags & MMC_DATA_READ) {
508 sc->lm_xfer_direction = DIRECTION_READ;
509 lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_READ,
510 LPC_SD_PHYS_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
514 if (data->flags & MMC_DATA_WRITE) {
515 sc->lm_xfer_direction = DIRECTION_WRITE;
516 lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_WRITE,
517 sc->lm_buffer_phys, LPC_SD_PHYS_BASE + LPC_SD_FIFO,
521 datactrl |= (sc->lm_xfer_direction
522 ? LPC_SD_DATACTRL_WRITE
523 : LPC_SD_DATACTRL_READ);
525 datactrl |= LPC_SD_DATACTRL_DMAENABLE | LPC_SD_DATACTRL_ENABLE;
526 datactrl |= (ffs(data->len) - 1) << 4;
528 debugf("datactrl: 0x%08x\n", datactrl);
530 lpc_mmc_write_4(sc, LPC_SD_DATATIMER, 0xFFFF0000);
531 lpc_mmc_write_4(sc, LPC_SD_DATALENGTH, data->len);
532 lpc_mmc_write_4(sc, LPC_SD_DATACTRL, datactrl);
536 lpc_mmc_read_ivar(device_t bus, device_t child, int which,
539 struct lpc_mmc_softc *sc = device_get_softc(bus);
544 case MMCBR_IVAR_BUS_MODE:
545 *(int *)result = sc->lm_host.ios.bus_mode;
547 case MMCBR_IVAR_BUS_WIDTH:
548 *(int *)result = sc->lm_host.ios.bus_width;
550 case MMCBR_IVAR_CHIP_SELECT:
551 *(int *)result = sc->lm_host.ios.chip_select;
553 case MMCBR_IVAR_CLOCK:
554 *(int *)result = sc->lm_host.ios.clock;
556 case MMCBR_IVAR_F_MIN:
557 *(int *)result = sc->lm_host.f_min;
559 case MMCBR_IVAR_F_MAX:
560 *(int *)result = sc->lm_host.f_max;
562 case MMCBR_IVAR_HOST_OCR:
563 *(int *)result = sc->lm_host.host_ocr;
565 case MMCBR_IVAR_MODE:
566 *(int *)result = sc->lm_host.mode;
569 *(int *)result = sc->lm_host.ocr;
571 case MMCBR_IVAR_POWER_MODE:
572 *(int *)result = sc->lm_host.ios.power_mode;
575 *(int *)result = sc->lm_host.ios.vdd;
577 case MMCBR_IVAR_CAPS:
578 *(int *)result = sc->lm_host.caps;
580 case MMCBR_IVAR_MAX_DATA:
589 lpc_mmc_write_ivar(device_t bus, device_t child, int which,
592 struct lpc_mmc_softc *sc = device_get_softc(bus);
597 case MMCBR_IVAR_BUS_MODE:
598 sc->lm_host.ios.bus_mode = value;
600 case MMCBR_IVAR_BUS_WIDTH:
601 sc->lm_host.ios.bus_width = value;
603 case MMCBR_IVAR_CHIP_SELECT:
604 sc->lm_host.ios.chip_select = value;
606 case MMCBR_IVAR_CLOCK:
607 sc->lm_host.ios.clock = value;
609 case MMCBR_IVAR_MODE:
610 sc->lm_host.mode = value;
613 sc->lm_host.ocr = value;
615 case MMCBR_IVAR_POWER_MODE:
616 sc->lm_host.ios.power_mode = value;
619 sc->lm_host.ios.vdd = value;
621 /* These are read-only */
622 case MMCBR_IVAR_CAPS:
623 case MMCBR_IVAR_HOST_OCR:
624 case MMCBR_IVAR_F_MIN:
625 case MMCBR_IVAR_F_MAX:
626 case MMCBR_IVAR_MAX_DATA:
633 lpc_mmc_update_ios(device_t bus, device_t child)
635 struct lpc_mmc_softc *sc = device_get_softc(bus);
636 struct mmc_ios *ios = &sc->lm_host.ios;
637 uint32_t clkdiv = 0, pwr = 0;
639 if (ios->bus_width == bus_width_4)
640 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
642 /* Calculate clock divider */
643 clkdiv = (LPC_SD_CLK / (2 * ios->clock)) - 1;
645 /* Clock rate should not exceed rate requested in ios */
646 if ((LPC_SD_CLK / (2 * (clkdiv + 1))) > ios->clock)
649 debugf("clock: %dHz, clkdiv: %d\n", ios->clock, clkdiv);
651 if (ios->bus_width == bus_width_4) {
652 debugf("using wide bus mode\n");
653 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
656 lpc_mmc_write_4(sc, LPC_SD_CLOCK, clkdiv | LPC_SD_CLOCK_ENABLE);
658 switch (ios->power_mode) {
660 pwr |= LPC_SD_POWER_CTRL_OFF;
663 pwr |= LPC_SD_POWER_CTRL_UP;
666 pwr |= LPC_SD_POWER_CTRL_ON;
670 if (ios->bus_mode == opendrain)
671 pwr |= LPC_SD_POWER_OPENDRAIN;
673 lpc_mmc_write_4(sc, LPC_SD_POWER, pwr);
679 lpc_mmc_get_ro(device_t bus, device_t child)
686 lpc_mmc_acquire_host(device_t bus, device_t child)
688 struct lpc_mmc_softc *sc = device_get_softc(bus);
692 while (sc->lm_bus_busy)
693 error = mtx_sleep(sc, &sc->lm_mtx, PZERO, "mmcah", 0);
701 lpc_mmc_release_host(device_t bus, device_t child)
703 struct lpc_mmc_softc *sc = device_get_softc(bus);
712 static void lpc_mmc_dma_rxfinish(void *arg)
716 static void lpc_mmc_dma_rxerror(void *arg)
718 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
719 device_printf(sc->lm_dev, "DMA RX error\n");
722 static void lpc_mmc_dma_txfinish(void *arg)
726 static void lpc_mmc_dma_txerror(void *arg)
728 struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
729 device_printf(sc->lm_dev, "DMA TX error\n");
733 lpc_mmc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
735 struct lpc_mmc_dmamap_arg *ctx;
740 ctx = (struct lpc_mmc_dmamap_arg *)arg;
741 ctx->lm_dma_busaddr = segs[0].ds_addr;
744 static device_method_t lpc_mmc_methods[] = {
745 /* Device interface */
746 DEVMETHOD(device_probe, lpc_mmc_probe),
747 DEVMETHOD(device_attach, lpc_mmc_attach),
748 DEVMETHOD(device_detach, lpc_mmc_detach),
751 DEVMETHOD(bus_read_ivar, lpc_mmc_read_ivar),
752 DEVMETHOD(bus_write_ivar, lpc_mmc_write_ivar),
753 DEVMETHOD(bus_print_child, bus_generic_print_child),
755 /* MMC bridge interface */
756 DEVMETHOD(mmcbr_update_ios, lpc_mmc_update_ios),
757 DEVMETHOD(mmcbr_request, lpc_mmc_request),
758 DEVMETHOD(mmcbr_get_ro, lpc_mmc_get_ro),
759 DEVMETHOD(mmcbr_acquire_host, lpc_mmc_acquire_host),
760 DEVMETHOD(mmcbr_release_host, lpc_mmc_release_host),
765 static devclass_t lpc_mmc_devclass;
767 static driver_t lpc_mmc_driver = {
770 sizeof(struct lpc_mmc_softc),
773 DRIVER_MODULE(lpcmmc, simplebus, lpc_mmc_driver, lpc_mmc_devclass, 0, 0);