sys/arm/lpc/lpc_mmc.c

   1 /*-
   2  * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  */
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bio.h>
  33 #include <sys/bus.h>
  34 #include <sys/conf.h>
  35 #include <sys/endian.h>
  36 #include <sys/kernel.h>
  37 #include <sys/kthread.h>
  38 #include <sys/lock.h>
  39 #include <sys/malloc.h>
  40 #include <sys/module.h>
  41 #include <sys/mutex.h>
  42 #include <sys/queue.h>
  43 #include <sys/resource.h>
  44 #include <sys/rman.h>
  45 #include <sys/time.h>
  46 #include <sys/timetc.h>
  47 #include <sys/watchdog.h>
  48
  49 #include <sys/kdb.h>
  50
  51 #include <machine/bus.h>
  52 #include <machine/cpu.h>
  53 #include <machine/cpufunc.h>
  54 #include <machine/resource.h>
  55 #include <machine/intr.h>
  56
  57 #include <dev/ofw/ofw_bus.h>
  58 #include <dev/ofw/ofw_bus_subr.h>
  59
  60 #include <dev/mmc/bridge.h>
  61 #include <dev/mmc/mmcreg.h>
  62 #include <dev/mmc/mmcbrvar.h>
  63
  64 #include <arm/lpc/lpcreg.h>
  65 #include <arm/lpc/lpcvar.h>
  66
  67 #define DEBUG
  68 #undef  DEBUG
  69
  70 #ifdef DEBUG
  71 #define debugf(fmt, args...) do { printf("%s(): ", __func__);   \
  72     printf(fmt,##args); } while (0)
  73 #else
  74 #define debugf(fmt, args...)
  75 #endif
  76
  77 struct lpc_mmc_dmamap_arg {
  78         bus_addr_t              lm_dma_busaddr;
  79 };
  80
  81 struct lpc_mmc_softc {
  82         device_t                lm_dev;
  83         struct mtx              lm_mtx;
  84         struct resource *       lm_mem_res;
  85         struct resource *       lm_irq_res;
  86         bus_space_tag_t         lm_bst;
  87         bus_space_handle_t      lm_bsh;
  88         void *                  lm_intrhand;
  89         struct mmc_host         lm_host;
  90         struct mmc_request *    lm_req;
  91         struct mmc_data *       lm_data;
  92         uint32_t                lm_flags;
  93 #define LPC_SD_FLAGS_IGNORECRC          (1 << 0)
  94         int                     lm_xfer_direction;
  95 #define DIRECTION_READ          0
  96 #define DIRECTION_WRITE         1
  97         int                     lm_xfer_done;
  98         int                     lm_bus_busy;
  99         bus_dma_tag_t           lm_dma_tag;
 100         bus_dmamap_t            lm_dma_map;
 101         bus_addr_t              lm_buffer_phys;
 102         void *                  lm_buffer;
 103 };
 104
 105 #define LPC_SD_MAX_BLOCKSIZE    1024
 106 /* XXX */
 107 #define LPC_MMC_DMACH_READ      1
 108 #define LPC_MMC_DMACH_WRITE     0
 109
 110
 111 static int lpc_mmc_probe(device_t);
 112 static int lpc_mmc_attach(device_t);
 113 static int lpc_mmc_detach(device_t);
 114 static void lpc_mmc_intr(void *);
 115
 116 static void lpc_mmc_cmd(struct lpc_mmc_softc *, struct mmc_command *);
 117 static void lpc_mmc_setup_xfer(struct lpc_mmc_softc *, struct mmc_data *);
 118
 119 static int lpc_mmc_update_ios(device_t, device_t);
 120 static int lpc_mmc_request(device_t, device_t, struct mmc_request *);
 121 static int lpc_mmc_get_ro(device_t, device_t);
 122 static int lpc_mmc_acquire_host(device_t, device_t);
 123 static int lpc_mmc_release_host(device_t, device_t);
 124
 125 static void lpc_mmc_dma_rxfinish(void *);
 126 static void lpc_mmc_dma_rxerror(void *);
 127 static void lpc_mmc_dma_txfinish(void *);
 128 static void lpc_mmc_dma_txerror(void *);
 129
 130 static void lpc_mmc_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 131
 132 #define lpc_mmc_lock(_sc)                                               \
 133     mtx_lock(&_sc->lm_mtx);
 134 #define lpc_mmc_unlock(_sc)                                             \
 135     mtx_unlock(&_sc->lm_mtx);
 136 #define lpc_mmc_read_4(_sc, _reg)                                       \
 137     bus_space_read_4(_sc->lm_bst, _sc->lm_bsh, _reg)
 138 #define lpc_mmc_write_4(_sc, _reg, _value)                              \
 139     bus_space_write_4(_sc->lm_bst, _sc->lm_bsh, _reg, _value)
 140
 141 static struct lpc_dmac_channel_config lpc_mmc_dma_rxconf = {
 142         .ldc_fcntl = LPC_DMAC_FLOW_D_P2M,
 143         .ldc_src_periph = LPC_DMAC_SD_ID,
 144         .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
 145         .ldc_src_incr = 0,
 146         .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
 147         .ldc_dst_periph = LPC_DMAC_SD_ID,
 148         .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
 149         .ldc_dst_incr = 1,
 150         .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
 151         .ldc_success_handler = lpc_mmc_dma_rxfinish,
 152         .ldc_error_handler = lpc_mmc_dma_rxerror,
 153 };
 154
 155 static struct lpc_dmac_channel_config lpc_mmc_dma_txconf = {
 156         .ldc_fcntl = LPC_DMAC_FLOW_P_M2P,
 157         .ldc_src_periph = LPC_DMAC_SD_ID,
 158         .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
 159         .ldc_src_incr = 1,
 160         .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8,
 161         .ldc_dst_periph = LPC_DMAC_SD_ID,
 162         .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4,
 163         .ldc_dst_incr = 0,
 164         .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8,
 165         .ldc_success_handler = lpc_mmc_dma_txfinish,
 166         .ldc_error_handler = lpc_mmc_dma_txerror,
 167 };
 168
 169 static int
 170 lpc_mmc_probe(device_t dev)
 171 {
 172         if (!ofw_bus_is_compatible(dev, "lpc,mmc"))
 173                 return (ENXIO);
 174
 175         device_set_desc(dev, "LPC32x0 MMC/SD controller");
 176         return (BUS_PROBE_DEFAULT);
 177 }
 178
 179 static int
 180 lpc_mmc_attach(device_t dev)
 181 {
 182         struct lpc_mmc_softc *sc = device_get_softc(dev);
 183         struct lpc_mmc_dmamap_arg ctx;
 184         device_t child;
 185         int rid, err;
 186
 187         sc->lm_dev = dev;
 188         sc->lm_req = NULL;
 189
 190         mtx_init(&sc->lm_mtx, "lpcmmc", "mmc", MTX_DEF);
 191
 192         rid = 0;
 193         sc->lm_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 194             RF_ACTIVE);
 195         if (!sc->lm_mem_res) {
 196                 device_printf(dev, "cannot allocate memory window\n");
 197                 return (ENXIO);
 198         }
 199
 200         sc->lm_bst = rman_get_bustag(sc->lm_mem_res);
 201         sc->lm_bsh = rman_get_bushandle(sc->lm_mem_res);
 202
 203         debugf("virtual register space: 0x%08lx\n", sc->lm_bsh);
 204
 205         rid = 0;
 206         sc->lm_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 207             RF_ACTIVE);
 208         if (!sc->lm_irq_res) {
 209                 device_printf(dev, "cannot allocate interrupt\n");
 210                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
 211                 return (ENXIO);
 212         }
 213
 214         if (bus_setup_intr(dev, sc->lm_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
 215             NULL, lpc_mmc_intr, sc, &sc->lm_intrhand))
 216         {
 217                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
 218                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
 219                 device_printf(dev, "cannot setup interrupt handler\n");
 220                 return (ENXIO);
 221         }
 222
 223         sc->lm_host.f_min = 312500;
 224         sc->lm_host.f_max = 2500000;
 225         sc->lm_host.host_ocr = MMC_OCR_300_310 | MMC_OCR_310_320 |
 226             MMC_OCR_320_330 | MMC_OCR_330_340;
 227 #if 0
 228         sc->lm_host.caps = MMC_CAP_4_BIT_DATA;
 229 #endif
 230
 231         lpc_pwr_write(dev, LPC_CLKPWR_MS_CTRL,
 232             LPC_CLKPWR_MS_CTRL_CLOCK_EN | LPC_CLKPWR_MS_CTRL_SD_CLOCK | 1);
 233         lpc_mmc_write_4(sc, LPC_SD_POWER, LPC_SD_POWER_CTRL_ON);
 234
 235         device_set_ivars(dev, &sc->lm_host);
 236
 237         child = device_add_child(dev, "mmc", -1);
 238         if (!child) {
 239                 device_printf(dev, "attaching MMC bus failed!\n");
 240                 bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
 241                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
 242                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
 243                 return (ENXIO);
 244         }
 245
 246         /* Alloc DMA memory */
 247         err = bus_dma_tag_create(
 248             bus_get_dma_tag(sc->lm_dev),
 249             4, 0,                       /* alignment, boundary */
 250             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
 251             BUS_SPACE_MAXADDR,          /* highaddr */
 252             NULL, NULL,                 /* filter, filterarg */
 253             LPC_SD_MAX_BLOCKSIZE, 1,    /* maxsize, nsegments */
 254             LPC_SD_MAX_BLOCKSIZE, 0,    /* maxsegsize, flags */
 255             NULL, NULL,                 /* lockfunc, lockarg */
 256             &sc->lm_dma_tag);
 257
 258         err = bus_dmamem_alloc(sc->lm_dma_tag, (void **)&sc->lm_buffer,
 259             0, &sc->lm_dma_map);
 260         if (err) {
 261                 device_printf(dev, "cannot allocate framebuffer\n");
 262                 goto fail;
 263         }
 264
 265         err = bus_dmamap_load(sc->lm_dma_tag, sc->lm_dma_map, sc->lm_buffer,
 266             LPC_SD_MAX_BLOCKSIZE, lpc_mmc_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
 267         if (err) {
 268                 device_printf(dev, "cannot load DMA map\n");
 269                 goto fail;
 270         }
 271
 272         sc->lm_buffer_phys = ctx.lm_dma_busaddr;
 273
 274         lpc_mmc_dma_rxconf.ldc_handler_arg = (void *)sc;
 275         err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_READ, &lpc_mmc_dma_rxconf);
 276         if (err) {
 277                 device_printf(dev, "cannot allocate RX DMA channel\n");
 278                 goto fail;
 279         }
 280
 281
 282         lpc_mmc_dma_txconf.ldc_handler_arg = (void *)sc;
 283         err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_WRITE, &lpc_mmc_dma_txconf);
 284         if (err) {
 285                 device_printf(dev, "cannot allocate TX DMA channel\n");
 286                 goto fail;
 287         }
 288
 289         bus_generic_probe(dev);
 290         bus_generic_attach(dev);
 291
 292         return (0);
 293
 294 fail:
 295         if (sc->lm_intrhand)
 296                 bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand);
 297         if (sc->lm_irq_res)
 298                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res);
 299         if (sc->lm_mem_res)
 300                 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res);
 301         return (err);
 302 }
 303
 304 static int
 305 lpc_mmc_detach(device_t dev)
 306 {
 307         return (EBUSY);
 308 }
 309
 310 static void
 311 lpc_mmc_intr(void *arg)
 312 {
 313         struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
 314         struct mmc_command *cmd;
 315         uint32_t status;
 316
 317         status = lpc_mmc_read_4(sc, LPC_SD_STATUS);
 318
 319         debugf("interrupt: 0x%08x\n", status);
 320
 321         if (status & LPC_SD_STATUS_CMDCRCFAIL) {
 322                 cmd = sc->lm_req->cmd;
 323                 cmd->error = sc->lm_flags & LPC_SD_FLAGS_IGNORECRC
 324                     ? MMC_ERR_NONE : MMC_ERR_BADCRC;
 325                 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
 326                 sc->lm_req->done(sc->lm_req);
 327                 sc->lm_req = NULL;
 328                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDCRCFAIL);
 329         }
 330
 331         if (status & LPC_SD_STATUS_CMDACTIVE)
 332         {
 333                 debugf("command active\n");
 334                 cmd = sc->lm_req->cmd;
 335                 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
 336                 sc->lm_req->done(sc->lm_req);
 337                 sc->lm_req = NULL;
 338         }
 339
 340         if (status & LPC_SD_STATUS_DATATIMEOUT) {
 341                 device_printf(sc->lm_dev, "data timeout\n");
 342                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATATIMEOUT);
 343         }
 344
 345         if (status & LPC_SD_STATUS_TXUNDERRUN) {
 346                 device_printf(sc->lm_dev, "TX underrun\n");
 347                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_TXUNDERRUN);
 348         }
 349
 350         if (status & LPC_SD_STATUS_CMDRESPEND) {
 351                 debugf("command response\n");
 352                 cmd = sc->lm_req->cmd;
 353
 354                 if (cmd->flags & MMC_RSP_136) {
 355                         cmd->resp[3] = lpc_mmc_read_4(sc, LPC_SD_RESP3);
 356                         cmd->resp[2] = lpc_mmc_read_4(sc, LPC_SD_RESP2);
 357                         cmd->resp[1] = lpc_mmc_read_4(sc, LPC_SD_RESP1);
 358                 }
 359
 360                 cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0);
 361                 cmd->error = MMC_ERR_NONE;
 362
 363                 if (cmd->data && (cmd->data->flags & MMC_DATA_WRITE))
 364                         lpc_mmc_setup_xfer(sc, sc->lm_req->cmd->data);
 365
 366                 if (!cmd->data) {
 367                         sc->lm_req->done(sc->lm_req);
 368                         sc->lm_req = NULL;
 369                 }
 370
 371                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDRESPEND);
 372         }
 373
 374         if (status & LPC_SD_STATUS_CMDSENT) {
 375                 debugf("command sent\n");
 376                 cmd = sc->lm_req->cmd;
 377                 cmd->error = MMC_ERR_NONE;
 378                 sc->lm_req->done(sc->lm_req);
 379                 sc->lm_req = NULL;
 380                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDSENT);
 381         }
 382
 383         if (status & LPC_SD_STATUS_DATAEND) {
 384                 if (sc->lm_xfer_direction == DIRECTION_READ)
 385                         lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
 386
 387                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATAEND);
 388         }
 389
 390         if (status & LPC_SD_STATUS_CMDTIMEOUT) {
 391                 device_printf(sc->lm_dev, "command response timeout\n");
 392                 cmd = sc->lm_req->cmd;
 393                 cmd->error = MMC_ERR_TIMEOUT;
 394                 sc->lm_req->done(sc->lm_req);
 395                 sc->lm_req = NULL;
 396                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDTIMEOUT);
 397                 return;
 398         }
 399
 400         if (status & LPC_SD_STATUS_STARTBITERR) {
 401                 device_printf(sc->lm_dev, "start bit error\n");
 402                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_STARTBITERR);
 403         }
 404
 405         if (status & LPC_SD_STATUS_DATACRCFAIL) {
 406                 device_printf(sc->lm_dev, "data CRC error\n");
 407                 debugf("data buffer: %p\n", sc->lm_buffer);
 408                 cmd = sc->lm_req->cmd;
 409                 cmd->error = MMC_ERR_BADCRC;
 410                 sc->lm_req->done(sc->lm_req);
 411                 sc->lm_req = NULL;
 412
 413                 if (sc->lm_xfer_direction == DIRECTION_READ)
 414                         lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID);
 415
 416                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATACRCFAIL);
 417         }
 418
 419         if (status & LPC_SD_STATUS_DATABLOCKEND) {
 420                 debugf("data block end\n");
 421                 if (sc->lm_xfer_direction == DIRECTION_READ)
 422                         memcpy(sc->lm_data->data, sc->lm_buffer, sc->lm_data->len);
 423
 424                 if (sc->lm_xfer_direction == DIRECTION_WRITE) {
 425                         lpc_dmac_disable_channel(sc->lm_dev, LPC_MMC_DMACH_WRITE);
 426                         lpc_mmc_write_4(sc, LPC_SD_DATACTRL, 0);
 427                 }
 428
 429                 sc->lm_req->done(sc->lm_req);
 430                 sc->lm_req = NULL;
 431                 lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATABLOCKEND);
 432         }
 433
 434         debugf("done\n");
 435 }
 436
 437 static int
 438 lpc_mmc_request(device_t bus, device_t child, struct mmc_request *req)
 439 {
 440         struct lpc_mmc_softc *sc = device_get_softc(bus);
 441
 442         debugf("request: %p\n", req);
 443
 444         lpc_mmc_lock(sc);
 445         if (sc->lm_req)
 446                 return (EBUSY);
 447
 448         sc->lm_req = req;
 449
 450         if (req->cmd->data && req->cmd->data->flags & MMC_DATA_WRITE) {
 451                 memcpy(sc->lm_buffer, req->cmd->data->data, req->cmd->data->len);
 452                 lpc_mmc_cmd(sc, req->cmd);
 453                 lpc_mmc_unlock(sc);
 454                 return (0);
 455         }
 456
 457         if (req->cmd->data)
 458                 lpc_mmc_setup_xfer(sc, req->cmd->data);
 459
 460         lpc_mmc_cmd(sc, req->cmd);
 461         lpc_mmc_unlock(sc);
 462
 463         return (0);
 464 }
 465
 466 static void
 467 lpc_mmc_cmd(struct lpc_mmc_softc *sc, struct mmc_command *cmd)
 468 {
 469         uint32_t cmdreg = 0;
 470
 471         debugf("cmd: %d arg: 0x%08x\n", cmd->opcode, cmd->arg);
 472
 473         if (lpc_mmc_read_4(sc, LPC_SD_COMMAND) & LPC_SD_COMMAND_ENABLE) {
 474                 lpc_mmc_write_4(sc, LPC_SD_COMMAND, 0);
 475                 DELAY(1000);
 476         }
 477
 478         sc->lm_flags &= ~LPC_SD_FLAGS_IGNORECRC;
 479
 480         if (cmd->flags & MMC_RSP_PRESENT)
 481                 cmdreg |= LPC_SD_COMMAND_RESPONSE;
 482
 483         if (MMC_RSP(cmd->flags) == MMC_RSP_R2)
 484                 cmdreg |= LPC_SD_COMMAND_LONGRSP;
 485
 486         if (MMC_RSP(cmd->flags) == MMC_RSP_R3)
 487                 sc->lm_flags |= LPC_SD_FLAGS_IGNORECRC;
 488
 489         cmdreg |= LPC_SD_COMMAND_ENABLE;
 490         cmdreg |= (cmd->opcode & LPC_SD_COMMAND_CMDINDEXMASK);
 491
 492         lpc_mmc_write_4(sc, LPC_SD_MASK0, 0xffffffff);
 493         lpc_mmc_write_4(sc, LPC_SD_MASK1, 0xffffffff);
 494         lpc_mmc_write_4(sc, LPC_SD_ARGUMENT, cmd->arg);
 495         lpc_mmc_write_4(sc, LPC_SD_COMMAND, cmdreg);
 496 }
 497
 498 static void
 499 lpc_mmc_setup_xfer(struct lpc_mmc_softc *sc, struct mmc_data *data)
 500 {
 501         uint32_t datactrl = 0;
 502         int data_words = data->len / 4;
 503
 504         sc->lm_data = data;
 505         sc->lm_xfer_done = 0;
 506
 507         debugf("data: %p, len: %d, %s\n", data,
 508             data->len, (data->flags & MMC_DATA_READ) ? "read" : "write");
 509
 510         if (data->flags & MMC_DATA_READ) {
 511                 sc->lm_xfer_direction = DIRECTION_READ;
 512                 lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_READ,
 513                     LPC_SD_BASE + LPC_SD_FIFO, sc->lm_buffer_phys,
 514                     data_words, 0);
 515         }
 516
 517         if (data->flags & MMC_DATA_WRITE) {
 518                 sc->lm_xfer_direction = DIRECTION_WRITE;
 519                 lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_WRITE,
 520                     sc->lm_buffer_phys, LPC_SD_BASE + LPC_SD_FIFO,
 521                     data_words, 0);
 522         }
 523
 524         datactrl |= (sc->lm_xfer_direction
 525             ? LPC_SD_DATACTRL_WRITE
 526             : LPC_SD_DATACTRL_READ);
 527
 528         datactrl |= LPC_SD_DATACTRL_DMAENABLE | LPC_SD_DATACTRL_ENABLE;
 529         datactrl |= (ffs(data->len) - 1) << 4;
 530
 531         debugf("datactrl: 0x%08x\n", datactrl);
 532
 533         lpc_mmc_write_4(sc, LPC_SD_DATATIMER, 0xFFFF0000);
 534         lpc_mmc_write_4(sc, LPC_SD_DATALENGTH, data->len);
 535         lpc_mmc_write_4(sc, LPC_SD_DATACTRL, datactrl);
 536 }
 537
 538 static int
 539 lpc_mmc_read_ivar(device_t bus, device_t child, int which,
 540     uintptr_t *result)
 541 {
 542         struct lpc_mmc_softc *sc = device_get_softc(bus);
 543
 544         switch (which) {
 545         default:
 546                 return (EINVAL);
 547         case MMCBR_IVAR_BUS_MODE:
 548                 *(int *)result = sc->lm_host.ios.bus_mode;
 549                 break;
 550         case MMCBR_IVAR_BUS_WIDTH:
 551                 *(int *)result = sc->lm_host.ios.bus_width;
 552                 break;
 553         case MMCBR_IVAR_CHIP_SELECT:
 554                 *(int *)result = sc->lm_host.ios.chip_select;
 555                 break;
 556         case MMCBR_IVAR_CLOCK:
 557                 *(int *)result = sc->lm_host.ios.clock;
 558                 break;
 559         case MMCBR_IVAR_F_MIN:
 560                 *(int *)result = sc->lm_host.f_min;
 561                 break;
 562         case MMCBR_IVAR_F_MAX:
 563                 *(int *)result = sc->lm_host.f_max;
 564                 break;
 565         case MMCBR_IVAR_HOST_OCR:
 566                 *(int *)result = sc->lm_host.host_ocr;
 567                 break;
 568         case MMCBR_IVAR_MODE:
 569                 *(int *)result = sc->lm_host.mode;
 570                 break;
 571         case MMCBR_IVAR_OCR:
 572                 *(int *)result = sc->lm_host.ocr;
 573                 break;
 574         case MMCBR_IVAR_POWER_MODE:
 575                 *(int *)result = sc->lm_host.ios.power_mode;
 576                 break;
 577         case MMCBR_IVAR_VDD:
 578                 *(int *)result = sc->lm_host.ios.vdd;
 579                 break;
 580         case MMCBR_IVAR_CAPS:
 581                 *(int *)result = sc->lm_host.caps;
 582                 break;
 583         case MMCBR_IVAR_MAX_DATA:
 584                 *(int *)result = 1;
 585                 break;
 586         }
 587
 588         return (0);
 589 }
 590
 591 static int
 592 lpc_mmc_write_ivar(device_t bus, device_t child, int which,
 593     uintptr_t value)
 594 {
 595         struct lpc_mmc_softc *sc = device_get_softc(bus);
 596
 597         switch (which) {
 598         default:
 599                 return (EINVAL);
 600         case MMCBR_IVAR_BUS_MODE:
 601                 sc->lm_host.ios.bus_mode = value;
 602                 break;
 603         case MMCBR_IVAR_BUS_WIDTH:
 604                 sc->lm_host.ios.bus_width = value;
 605                 break;
 606         case MMCBR_IVAR_CHIP_SELECT:
 607                 sc->lm_host.ios.chip_select = value;
 608                 break;
 609         case MMCBR_IVAR_CLOCK:
 610                 sc->lm_host.ios.clock = value;
 611                 break;
 612         case MMCBR_IVAR_MODE:
 613                 sc->lm_host.mode = value;
 614                 break;
 615         case MMCBR_IVAR_OCR:
 616                 sc->lm_host.ocr = value;
 617                 break;
 618         case MMCBR_IVAR_POWER_MODE:
 619                 sc->lm_host.ios.power_mode = value;
 620                 break;
 621         case MMCBR_IVAR_VDD:
 622                 sc->lm_host.ios.vdd = value;
 623                 break;
 624         /* These are read-only */
 625         case MMCBR_IVAR_CAPS:
 626         case MMCBR_IVAR_HOST_OCR:
 627         case MMCBR_IVAR_F_MIN:
 628         case MMCBR_IVAR_F_MAX:
 629         case MMCBR_IVAR_MAX_DATA:
 630                 return (EINVAL);
 631         }
 632         return (0);
 633 }
 634
 635 static int
 636 lpc_mmc_update_ios(device_t bus, device_t child)
 637 {
 638         struct lpc_mmc_softc *sc = device_get_softc(bus);
 639         struct mmc_ios *ios = &sc->lm_host.ios;
 640         uint32_t clkdiv = 0, pwr = 0;
 641
 642         if (ios->bus_width == bus_width_4)
 643                 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
 644
 645         /* Calculate clock divider */
 646         clkdiv = (LPC_SD_CLK / (2 * ios->clock)) - 1;
 647
 648         /* Clock rate should not exceed rate requested in ios */
 649         if ((LPC_SD_CLK / (2 * (clkdiv + 1))) > ios->clock)
 650                 clkdiv++;
 651
 652         debugf("clock: %dHz, clkdiv: %d\n", ios->clock, clkdiv);
 653
 654         if (ios->bus_width == bus_width_4) {
 655                 debugf("using wide bus mode\n");
 656                 clkdiv |= LPC_SD_CLOCK_WIDEBUS;
 657         }
 658
 659         lpc_mmc_write_4(sc, LPC_SD_CLOCK, clkdiv | LPC_SD_CLOCK_ENABLE);
 660
 661         switch (ios->power_mode) {
 662         case power_off:
 663                 pwr |= LPC_SD_POWER_CTRL_OFF;
 664                 break;
 665         case power_up:
 666                 pwr |= LPC_SD_POWER_CTRL_UP;
 667                 break;
 668         case power_on:
 669                 pwr |= LPC_SD_POWER_CTRL_ON;
 670                 break;
 671         }
 672
 673         if (ios->bus_mode == opendrain)
 674                 pwr |= LPC_SD_POWER_OPENDRAIN;
 675
 676         lpc_mmc_write_4(sc, LPC_SD_POWER, pwr);
 677
 678         return (0);
 679 }
 680
 681 static int
 682 lpc_mmc_get_ro(device_t bus, device_t child)
 683 {
 684
 685         return (0);
 686 }
 687
 688 static int
 689 lpc_mmc_acquire_host(device_t bus, device_t child)
 690 {
 691         struct lpc_mmc_softc *sc = device_get_softc(bus);
 692         int error = 0;
 693
 694         lpc_mmc_lock(sc);
 695         while (sc->lm_bus_busy)
 696                 error = mtx_sleep(sc, &sc->lm_mtx, PZERO, "mmcah", 0);
 697
 698         sc->lm_bus_busy++;
 699         lpc_mmc_unlock(sc);
 700         return (error);
 701 }
 702
 703 static int
 704 lpc_mmc_release_host(device_t bus, device_t child)
 705 {
 706         struct lpc_mmc_softc *sc = device_get_softc(bus);
 707
 708         lpc_mmc_lock(sc);
 709         sc->lm_bus_busy--;
 710         wakeup(sc);
 711         lpc_mmc_unlock(sc);
 712         return (0);
 713 }
 714
 715 static void lpc_mmc_dma_rxfinish(void *arg)
 716 {
 717 }
 718
 719 static void lpc_mmc_dma_rxerror(void *arg)
 720 {
 721         struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
 722         device_printf(sc->lm_dev, "DMA RX error\n");
 723 }
 724
 725 static void lpc_mmc_dma_txfinish(void *arg)
 726 {
 727 }
 728
 729 static void lpc_mmc_dma_txerror(void *arg)
 730 {
 731         struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg;
 732         device_printf(sc->lm_dev, "DMA TX error\n");
 733 }
 734
 735 static void
 736 lpc_mmc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
 737 {
 738         struct lpc_mmc_dmamap_arg *ctx;
 739
 740         if (err)
 741                 return;
 742
 743         ctx = (struct lpc_mmc_dmamap_arg *)arg;
 744         ctx->lm_dma_busaddr = segs[0].ds_addr;
 745 }
 746
 747 static device_method_t lpc_mmc_methods[] = {
 748         /* Device interface */
 749         DEVMETHOD(device_probe,         lpc_mmc_probe),
 750         DEVMETHOD(device_attach,        lpc_mmc_attach),
 751         DEVMETHOD(device_detach,        lpc_mmc_detach),
 752
 753         /* Bus interface */
 754         DEVMETHOD(bus_read_ivar,        lpc_mmc_read_ivar),
 755         DEVMETHOD(bus_write_ivar,       lpc_mmc_write_ivar),
 756         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 757
 758         /* MMC bridge interface */
 759         DEVMETHOD(mmcbr_update_ios,     lpc_mmc_update_ios),
 760         DEVMETHOD(mmcbr_request,        lpc_mmc_request),
 761         DEVMETHOD(mmcbr_get_ro,         lpc_mmc_get_ro),
 762         DEVMETHOD(mmcbr_acquire_host,   lpc_mmc_acquire_host),
 763         DEVMETHOD(mmcbr_release_host,   lpc_mmc_release_host),
 764
 765         { 0, 0 }
 766 };
 767
 768 static devclass_t lpc_mmc_devclass;
 769
 770 static driver_t lpc_mmc_driver = {
 771         "lpcmmc",
 772         lpc_mmc_methods,
 773         sizeof(struct lpc_mmc_softc),
 774 };
 775
 776 DRIVER_MODULE(lpcmmc, simplebus, lpc_mmc_driver, lpc_mmc_devclass, 0, 0);