3 * Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Driver for the MMC/SD/SDIO module on the TI OMAP series of SoCs.
31 * This driver is heavily based on the SD/MMC driver for the AT91 (at91_mci.c).
33 * It's important to realise that the MMC state machine is already in the kernel
34 * and this driver only exposes the specific interfaces of the controller.
36 * This driver is still very much a work in progress, I've verified that basic
37 * sector reading can be performed. But I've yet to test it with a file system
38 * or even writing. In addition I've only tested the driver with an SD card,
39 * I've no idea if MMC cards work.
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
50 #include <sys/endian.h>
51 #include <sys/kernel.h>
52 #include <sys/kthread.h>
54 #include <sys/malloc.h>
55 #include <sys/module.h>
56 #include <sys/mutex.h>
57 #include <sys/queue.h>
58 #include <sys/resource.h>
61 #include <sys/timetc.h>
64 #include <machine/bus.h>
65 #include <machine/cpu.h>
66 #include <machine/cpufunc.h>
67 #include <machine/resource.h>
68 #include <machine/frame.h>
69 #include <machine/intr.h>
71 #include <dev/mmc/bridge.h>
72 #include <dev/mmc/mmcreg.h>
73 #include <dev/mmc/mmcbrvar.h>
75 #include <dev/fdt/fdt_common.h>
76 #include <dev/ofw/openfirm.h>
77 #include <dev/ofw/ofw_bus.h>
78 #include <dev/ofw/ofw_bus_subr.h>
83 #include "mmcbus_if.h"
85 #include <arm/ti/ti_sdma.h>
86 #include <arm/ti/ti_edma3.h>
87 #include <arm/ti/ti_mmchs.h>
88 #include <arm/ti/ti_cpuid.h>
89 #include <arm/ti/ti_prcm.h>
91 #include <arm/ti/twl/twl.h>
92 #include <arm/ti/twl/twl_vreg.h>
95 #define ti_mmchs_dbg(sc, fmt, args...) \
96 device_printf((sc)->sc_dev, fmt, ## args);
98 #define ti_mmchs_dbg(sc, fmt, args...)
102 * Structure that stores the driver context
104 struct ti_mmchs_softc {
107 struct resource* sc_irq_res;
108 struct resource* sc_mem_res;
112 bus_dma_tag_t sc_dmatag;
113 bus_dmamap_t sc_dmamap;
116 unsigned int sc_dmach_rd;
117 unsigned int sc_dmach_wr;
121 device_t sc_gpio_dev;
122 int sc_wp_gpio_pin; /* GPIO pin for MMC write protect */
124 device_t sc_vreg_dev;
125 const char* sc_vreg_name;
129 struct mmc_host host;
130 struct mmc_request* req;
131 struct mmc_command* curcmd;
134 #define CMD_STARTED 1
135 #define STOP_STARTED 2
137 int bus_busy; /* TODO: Needed ? */
139 void* sc_cmd_data_vaddr;
142 /* The offset applied to each of the register base addresses, OMAP4
143 * register sets are offset 0x100 from the OMAP3 series.
145 unsigned long sc_reg_off;
147 /* The physical address of the MMCHS_DATA register, used for the DMA xfers */
148 unsigned long sc_data_reg_paddr;
150 /* The reference clock frequency */
151 unsigned int sc_ref_freq;
153 enum mmc_power_mode sc_cur_power_mode;
157 * Macros for driver mutex locking
159 #define TI_MMCHS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
160 #define TI_MMCHS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
161 #define TI_MMCHS_LOCK_INIT(_sc) \
162 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
164 #define TI_MMCHS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
165 #define TI_MMCHS_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
166 #define TI_MMCHS_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
168 static void ti_mmchs_start(struct ti_mmchs_softc *sc);
171 * ti_mmchs_read_4 - reads a 32-bit value from a register
172 * ti_mmchs_write_4 - writes a 32-bit value to a register
173 * @sc: pointer to the driver context
174 * @off: register offset to read from
175 * @val: the value to write into the register
181 * The 32-bit value read from the register
183 static inline uint32_t
184 ti_mmchs_read_4(struct ti_mmchs_softc *sc, bus_size_t off)
186 return bus_read_4(sc->sc_mem_res, (sc->sc_reg_off + off));
190 ti_mmchs_write_4(struct ti_mmchs_softc *sc, bus_size_t off, uint32_t val)
192 bus_write_4(sc->sc_mem_res, (sc->sc_reg_off + off), val);
196 * ti_mmchs_reset_controller -
197 * @arg: caller supplied arg
198 * @segs: array of segments (although in our case should only be one)
199 * @nsegs: number of segments (in our case should be 1)
206 ti_mmchs_reset_controller(struct ti_mmchs_softc *sc, uint32_t bit)
208 unsigned long attempts;
211 ti_mmchs_dbg(sc, "reseting controller - bit 0x%08x\n", bit);
213 sysctl = ti_mmchs_read_4(sc, MMCHS_SYSCTL);
214 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl | bit);
216 * AM335x and OMAP4 >= ES2 have an updated reset logic.
217 * Monitor a 0->1 transition first.
219 if ((ti_chip() == CHIP_AM335X) ||
220 ((ti_chip() == CHIP_OMAP_4) && (ti_revision() > OMAP4430_REV_ES1_0))) {
222 while (!(ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) && (attempts-- > 0))
227 while ((ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit) && (attempts-- > 0))
230 if (ti_mmchs_read_4(sc, MMCHS_SYSCTL) & bit)
231 device_printf(sc->sc_dev, "Error - Timeout waiting on controller reset\n");
235 * ti_mmchs_getaddr - called by the DMA function to simply return the phys addr
236 * @arg: caller supplied arg
237 * @segs: array of segments (although in our case should only be one)
238 * @nsegs: number of segments (in our case should be 1)
241 * This function is called by bus_dmamap_load() after it has compiled an array
242 * of segments, each segment is a phsyical chunk of memory. However in our case
243 * we should only have one segment, because we don't (yet?) support DMA scatter
244 * gather. To ensure we only have one segment, the DMA tag was created by
245 * bus_dma_tag_create() (called from ti_mmchs_attach) with nsegments set to 1.
249 ti_mmchs_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
254 *(bus_addr_t *)arg = segs[0].ds_addr;
257 #ifndef SOC_TI_AM335X
259 * ti_mmchs_dma_intr - interrupt handler for DMA events triggered by the controller
260 * @ch: the dma channel number
261 * @status: bit field of the status bytes
262 * @data: callback data, in this case a pointer to the controller struct
266 * Called from interrupt context
270 ti_mmchs_dma_intr(unsigned int ch, uint32_t status, void *data)
272 /* Ignore for now ... we don't need this interrupt as we already have the
273 * interrupt from the MMC controller.
279 * ti_mmchs_intr_xfer_compl - called if a 'transfer complete' IRQ was received
280 * @sc: pointer to the driver context
281 * @cmd: the command that was sent previously
283 * This function is simply responsible for syncing up the DMA buffer.
286 * Called from interrupt context
289 * Return value indicates if the transaction is complete, not done = 0, done != 0
292 ti_mmchs_intr_xfer_compl(struct ti_mmchs_softc *sc, struct mmc_command *cmd)
296 /* Read command register to test whether this command was a read or write. */
297 cmd_reg = ti_mmchs_read_4(sc, MMCHS_CMD);
299 /* Sync-up the DMA buffer so the caller can access the new memory */
300 if (cmd_reg & MMCHS_CMD_DDIR) {
301 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_POSTREAD);
302 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
305 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_POSTWRITE);
306 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
310 /* Debugging dump of the data received */
314 uint8_t *p = (uint8_t*) sc->sc_cmd_data_vaddr;
315 for (i=0; i<sc->sc_cmd_data_len; i++) {
317 printf("\n0x%04x : ", i);
318 printf("%02X ", *p++);
324 /* We are done, transfer complete */
329 * ti_mmchs_intr_cmd_compl - called if a 'command complete' IRQ was received
330 * @sc: pointer to the driver context
331 * @cmd: the command that was sent previously
335 * Called from interrupt context
338 * Return value indicates if the transaction is complete, not done = 0, done != 0
341 ti_mmchs_intr_cmd_compl(struct ti_mmchs_softc *sc, struct mmc_command *cmd)
345 /* Copy the response into the request struct ... if a response was
347 if (cmd != NULL && (cmd->flags & MMC_RSP_PRESENT)) {
348 if (cmd->flags & MMC_RSP_136) {
349 cmd->resp[3] = ti_mmchs_read_4(sc, MMCHS_RSP10);
350 cmd->resp[2] = ti_mmchs_read_4(sc, MMCHS_RSP32);
351 cmd->resp[1] = ti_mmchs_read_4(sc, MMCHS_RSP54);
352 cmd->resp[0] = ti_mmchs_read_4(sc, MMCHS_RSP76);
354 cmd->resp[0] = ti_mmchs_read_4(sc, MMCHS_RSP10);
358 /* Check if the command was expecting some data transfer, if not
360 cmd_reg = ti_mmchs_read_4(sc, MMCHS_CMD);
361 return ((cmd_reg & MMCHS_CMD_DP) == 0);
365 * ti_mmchs_intr_error - handles error interrupts
366 * @sc: pointer to the driver context
367 * @cmd: the command that was sent previously
368 * @stat_reg: the value that was in the status register
372 * Called from interrupt context
375 * Return value indicates if the transaction is complete, not done = 0, done != 0
378 ti_mmchs_intr_error(struct ti_mmchs_softc *sc, struct mmc_command *cmd,
381 ti_mmchs_dbg(sc, "error in xfer - stat 0x%08x\n", stat_reg);
383 /* Ignore CRC errors on CMD2 and ACMD47, per relevant standards */
384 if ((stat_reg & MMCHS_STAT_CCRC) && (cmd->opcode == MMC_SEND_OP_COND ||
385 cmd->opcode == ACMD_SD_SEND_OP_COND))
386 cmd->error = MMC_ERR_NONE;
387 else if (stat_reg & (MMCHS_STAT_CTO | MMCHS_STAT_DTO))
388 cmd->error = MMC_ERR_TIMEOUT;
389 else if (stat_reg & (MMCHS_STAT_CCRC | MMCHS_STAT_DCRC))
390 cmd->error = MMC_ERR_BADCRC;
392 cmd->error = MMC_ERR_FAILED;
394 /* If a dma transaction we should also stop the dma transfer */
395 if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DE) {
397 /* Abort the DMA transfer (DDIR bit tells direction) */
398 if (ti_mmchs_read_4(sc, MMCHS_CMD) & MMCHS_CMD_DDIR)
400 printf("%s: DMA unimplemented\n", __func__);
402 ti_sdma_stop_xfer(sc->sc_dmach_rd);
406 printf("%s: DMA unimplemented\n", __func__);
408 ti_sdma_stop_xfer(sc->sc_dmach_wr);
411 /* If an error occure abort the DMA operation and free the dma map */
412 if ((sc->sc_dmamapped > 0) && (cmd->error != MMC_ERR_NONE)) {
413 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
418 /* Command error occured? ... if so issue a soft reset for the cmd fsm */
419 if (stat_reg & (MMCHS_STAT_CCRC | MMCHS_STAT_CTO)) {
420 ti_mmchs_reset_controller(sc, MMCHS_SYSCTL_SRC);
423 /* Data error occured? ... if so issue a soft reset for the data line */
424 if (stat_reg & (MMCHS_STAT_DEB | MMCHS_STAT_DCRC | MMCHS_STAT_DTO)) {
425 ti_mmchs_reset_controller(sc, MMCHS_SYSCTL_SRD);
428 /* On any error the command is cancelled ... so we are done */
433 * ti_mmchs_intr - interrupt handler for MMC/SD/SDIO controller
434 * @arg: pointer to the driver context
436 * Interrupt handler for the MMC/SD/SDIO controller, responsible for handling
437 * the IRQ and clearing the status flags.
440 * Called from interrupt context
446 ti_mmchs_intr(void *arg)
448 struct ti_mmchs_softc *sc = (struct ti_mmchs_softc *) arg;
454 stat_reg = ti_mmchs_read_4(sc, MMCHS_STAT) & (ti_mmchs_read_4(sc,
455 MMCHS_IE) | MMCHS_STAT_ERRI);
457 if (sc->curcmd == NULL) {
458 device_printf(sc->sc_dev, "Error: current cmd NULL, already done?\n");
459 ti_mmchs_write_4(sc, MMCHS_STAT, stat_reg);
464 if (stat_reg & MMCHS_STAT_ERRI) {
465 /* An error has been tripped in the status register */
466 done = ti_mmchs_intr_error(sc, sc->curcmd, stat_reg);
470 /* NOTE: This implementation could be a bit inefficent, I don't think
471 * it is necessary to handle both the 'command complete' and 'transfer
472 * complete' for data transfers ... presumably just transfer complete
477 sc->curcmd->error = MMC_ERR_NONE;
479 /* Check if the command completed */
480 if (stat_reg & MMCHS_STAT_CC) {
481 done = ti_mmchs_intr_cmd_compl(sc, sc->curcmd);
484 /* Check if the transfer has completed */
485 if (stat_reg & MMCHS_STAT_TC) {
486 done = ti_mmchs_intr_xfer_compl(sc, sc->curcmd);
491 /* Clear all the interrupt status bits by writing the value back */
492 ti_mmchs_write_4(sc, MMCHS_STAT, stat_reg);
494 /* This may mark the command as done if there is no stop request */
495 /* TODO: This is a bit ugly, needs fix-up */
505 ti_mmchs_edma3_rx_xfer_setup(struct ti_mmchs_softc *sc, uint32_t src_paddr,
506 uint32_t dst_paddr, uint16_t blk_size, uint16_t num_blks)
508 struct ti_edma3cc_param_set ps;
510 bzero(&ps, sizeof(struct ti_edma3cc_param_set));
514 ps.dstcidx = blk_size;
516 ps.bcnt = blk_size/4;
519 ps.opt.tcc = sc->dma_rx_trig;
521 ps.opt.fwid = 2; /* fifo width is 32 */
525 ti_edma3_param_write(sc->dma_rx_trig, &ps);
526 ti_edma3_enable_transfer_event(sc->dma_rx_trig);
530 ti_mmchs_edma3_tx_xfer_setup(struct ti_mmchs_softc *sc, uint32_t src_paddr,
531 uint32_t dst_paddr, uint16_t blk_size, uint16_t num_blks)
533 struct ti_edma3cc_param_set ps;
535 bzero(&ps, sizeof(struct ti_edma3cc_param_set));
538 ps.srccidx = blk_size;
539 ps.bcnt = blk_size/4;
544 ps.opt.tcc = sc->dma_tx_trig;
546 ps.opt.fwid = 2; /* fifo width is 32 */
550 ti_edma3_param_write(sc->dma_tx_trig, &ps);
551 ti_edma3_enable_transfer_event(sc->dma_tx_trig);
556 * ti_mmchs_start_cmd - starts the given command
557 * @sc: pointer to the driver context
558 * @cmd: the command to start
560 * The call tree for this function is
561 * - ti_mmchs_start_cmd
566 * Caller should be holding the OMAP_MMC lock.
572 ti_mmchs_start_cmd(struct ti_mmchs_softc *sc, struct mmc_command *cmd)
574 uint32_t cmd_reg, con_reg, ise_reg;
575 struct mmc_data *data;
576 struct mmc_request *req;
579 #ifndef SOC_TI_AM335X
586 /* Ensure the STR and MIT bits are cleared, these are only used for special
589 con_reg = ti_mmchs_read_4(sc, MMCHS_CON);
590 con_reg &= ~(MMCHS_CON_STR | MMCHS_CON_MIT);
592 /* Load the command into bits 29:24 of the CMD register */
593 cmd_reg = (uint32_t)(cmd->opcode & 0x3F) << 24;
595 /* Set the default set of interrupts */
596 ise_reg = (MMCHS_STAT_CERR | MMCHS_STAT_CTO | MMCHS_STAT_CC | MMCHS_STAT_CEB);
598 /* Enable CRC checking if requested */
599 if (cmd->flags & MMC_RSP_CRC)
600 ise_reg |= MMCHS_STAT_CCRC;
602 /* Enable reply index checking if the response supports it */
603 if (cmd->flags & MMC_RSP_OPCODE)
604 ise_reg |= MMCHS_STAT_CIE;
606 /* Set the expected response length */
607 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE) {
608 cmd_reg |= MMCHS_CMD_RSP_TYPE_NO;
610 if (cmd->flags & MMC_RSP_136)
611 cmd_reg |= MMCHS_CMD_RSP_TYPE_136;
612 else if (cmd->flags & MMC_RSP_BUSY)
613 cmd_reg |= MMCHS_CMD_RSP_TYPE_48_BSY;
615 cmd_reg |= MMCHS_CMD_RSP_TYPE_48;
617 /* Enable command index/crc checks if necessary expected */
618 if (cmd->flags & MMC_RSP_CRC)
619 cmd_reg |= MMCHS_CMD_CCCE;
620 if (cmd->flags & MMC_RSP_OPCODE)
621 cmd_reg |= MMCHS_CMD_CICE;
624 /* Set the bits for the special commands CMD12 (MMC_STOP_TRANSMISSION) and
625 * CMD52 (SD_IO_RW_DIRECT) */
626 if (cmd->opcode == MMC_STOP_TRANSMISSION)
627 cmd_reg |= MMCHS_CMD_CMD_TYPE_IO_ABORT;
629 /* Check if there is any data to write */
631 /* Clear the block count */
632 ti_mmchs_write_4(sc, MMCHS_BLK, 0);
634 /* The no data case is fairly simple */
635 ti_mmchs_write_4(sc, MMCHS_CON, con_reg);
636 ti_mmchs_write_4(sc, MMCHS_IE, ise_reg);
637 ti_mmchs_write_4(sc, MMCHS_ISE, ise_reg);
638 ti_mmchs_write_4(sc, MMCHS_ARG, cmd->arg);
639 ti_mmchs_write_4(sc, MMCHS_CMD, cmd_reg);
643 /* Indicate that data is present */
644 cmd_reg |= MMCHS_CMD_DP | MMCHS_CMD_MSBS | MMCHS_CMD_BCE;
646 /* Indicate a read operation */
647 if (data->flags & MMC_DATA_READ)
648 cmd_reg |= MMCHS_CMD_DDIR;
651 if (data->flags & MMC_DATA_STREAM) {
652 con_reg |= MMCHS_CON_STR;
655 /* Multi-block mode */
656 if (data->flags & MMC_DATA_MULTI) {
657 cmd_reg |= MMCHS_CMD_MSBS;
660 /* Enable extra interrupt sources for the transfer */
661 ise_reg |= (MMCHS_STAT_TC | MMCHS_STAT_DTO | MMCHS_STAT_DEB | MMCHS_STAT_CEB);
662 if (cmd->flags & MMC_RSP_CRC)
663 ise_reg |= MMCHS_STAT_DCRC;
665 /* Enable the DMA transfer bit */
666 cmd_reg |= MMCHS_CMD_DE;
668 /* Set the block size and block count */
669 ti_mmchs_write_4(sc, MMCHS_BLK, (1 << 16) | data->len);
671 /* Setup the DMA stuff */
672 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) {
677 /* Map the buffer buf into bus space using the dmamap map. */
678 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap, vaddr, data->len,
679 ti_mmchs_getaddr, &paddr, 0) != 0) {
681 if (req->cmd->flags & STOP_STARTED)
682 req->stop->error = MMC_ERR_NO_MEMORY;
684 req->cmd->error = MMC_ERR_NO_MEMORY;
691 #ifndef SOC_TI_AM335X
692 /* Calculate the packet size, the max packet size is 512 bytes
693 * (or 128 32-bit elements).
695 pktsize = min((data->len / 4), (512 / 4));
697 /* Sync the DMA buffer and setup the DMA controller */
698 if (data->flags & MMC_DATA_READ) {
699 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_PREREAD);
701 ti_mmchs_edma3_rx_xfer_setup(sc, sc->sc_data_reg_paddr,
702 paddr, data->len, 1);
704 ti_sdma_start_xfer_packet(sc->sc_dmach_rd, sc->sc_data_reg_paddr,
705 paddr, 1, (data->len / 4), pktsize);
708 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, BUS_DMASYNC_PREWRITE);
710 ti_mmchs_edma3_tx_xfer_setup(sc, paddr,
711 sc->sc_data_reg_paddr, data->len, 1);
713 ti_sdma_start_xfer_packet(sc->sc_dmach_wr, paddr,
714 sc->sc_data_reg_paddr, 1, (data->len / 4), pktsize);
718 /* Increase the mapped count */
721 sc->sc_cmd_data_vaddr = vaddr;
722 sc->sc_cmd_data_len = data->len;
725 /* Finally kick off the command */
726 ti_mmchs_write_4(sc, MMCHS_CON, con_reg);
727 ti_mmchs_write_4(sc, MMCHS_IE, ise_reg);
728 ti_mmchs_write_4(sc, MMCHS_ISE, ise_reg);
729 ti_mmchs_write_4(sc, MMCHS_ARG, cmd->arg);
730 ti_mmchs_write_4(sc, MMCHS_CMD, cmd_reg);
736 * ti_mmchs_start - starts a request stored in the driver context
737 * @sc: pointer to the driver context
739 * This function is called by ti_mmchs_request() in response to a read/write
740 * request from the MMC core module.
743 * Caller should be holding the OMAP_MMC lock.
749 ti_mmchs_start(struct ti_mmchs_softc *sc)
751 struct mmc_request *req;
753 /* Sanity check we have a request */
759 if (!(sc->flags & CMD_STARTED)) {
760 sc->flags |= CMD_STARTED;
761 ti_mmchs_start_cmd(sc, req->cmd);
765 if (!(sc->flags & STOP_STARTED) && req->stop) {
766 sc->flags |= STOP_STARTED;
767 ti_mmchs_start_cmd(sc, req->stop);
771 /* We must be done -- bad idea to do this while locked? */
778 * ti_mmchs_request - entry point for all read/write/cmd requests
779 * @brdev: mmc bridge device handle
780 * @reqdev: the device doing the requesting ?
781 * @req: the action requested
784 * None, internally takes the OMAP_MMC lock.
788 * EBUSY if the driver is already performing a request
791 ti_mmchs_request(device_t brdev, device_t reqdev, struct mmc_request *req)
793 struct ti_mmchs_softc *sc = device_get_softc(brdev);
798 * XXX do we want to be able to queue up multiple commands?
799 * XXX sounds like a good idea, but all protocols are sync, so
800 * XXX maybe the idea is naive...
802 if (sc->req != NULL) {
807 /* Store the request and start the command */
818 * ti_mmchs_get_ro - returns the status of the read-only setting
819 * @brdev: mmc bridge device handle
820 * @reqdev: device doing the request
822 * This function is relies on hint'ed values to determine which GPIO is used
823 * to determine if the write protect is enabled. On the BeagleBoard the pin
834 ti_mmchs_get_ro(device_t brdev, device_t reqdev)
836 struct ti_mmchs_softc *sc = device_get_softc(brdev);
837 unsigned int readonly = 0;
841 if ((sc->sc_wp_gpio_pin != -1) && (sc->sc_gpio_dev != NULL)) {
842 if (GPIO_PIN_GET(sc->sc_gpio_dev, sc->sc_wp_gpio_pin, &readonly) != 0)
845 readonly = (readonly == 0) ? 0 : 1;
854 * ti_mmchs_send_init_stream - sets bus/controller settings
855 * @brdev: mmc bridge device handle
856 * @reqdev: device doing the request
858 * Send init stream sequence to card before sending IDLE command
864 * 0 if function succeeded
867 ti_mmchs_send_init_stream(struct ti_mmchs_softc *sc)
869 unsigned long timeout;
870 uint32_t ie, ise, con;
872 ti_mmchs_dbg(sc, "Performing init sequence\n");
874 /* Prior to issuing any command, the MMCHS controller has to execute a
875 * special INIT procedure. The MMCHS controller has to generate a clock
876 * during 1ms. During the INIT procedure, the MMCHS controller generates 80
877 * clock periods. In order to keep the 1ms gap, the MMCHS controller should
878 * be configured to generate a clock whose frequency is smaller or equal to
879 * 80 KHz. If the MMCHS controller divider bitfield width doesn't allow to
880 * choose big values, the MMCHS controller driver should perform the INIT
881 * procedure twice or three times. Twice is generally enough.
883 * The INIt procedure is executed by setting MMCHS1.MMCHS_CON[1] INIT
884 * bitfield to 1 and by sending a dummy command, writing 0x00000000 in
885 * MMCHS1.MMCHS_CMD register.
888 /* Disable interrupt status events but enable interrupt generation.
889 * This doesn't seem right to me, but if the interrupt generation is not
890 * enabled the CC bit doesn't seem to be set in the STAT register.
893 /* Enable interrupt generation */
894 ie = ti_mmchs_read_4(sc, MMCHS_IE);
895 ti_mmchs_write_4(sc, MMCHS_IE, 0x307F0033);
897 /* Disable generation of status events (stops interrupt triggering) */
898 ise = ti_mmchs_read_4(sc, MMCHS_ISE);
899 ti_mmchs_write_4(sc, MMCHS_ISE, 0);
901 /* Set the initialise stream bit */
902 con = ti_mmchs_read_4(sc, MMCHS_CON);
903 con |= MMCHS_CON_INIT;
904 ti_mmchs_write_4(sc, MMCHS_CON, con);
906 /* Write a dummy command 0x00 */
907 ti_mmchs_write_4(sc, MMCHS_CMD, 0x00000000);
909 /* Loop waiting for the command to finish */
913 if (timeout-- == 0) {
914 device_printf(sc->sc_dev, "Error: first stream init timed out\n");
917 } while (!(ti_mmchs_read_4(sc, MMCHS_STAT) & MMCHS_STAT_CC));
919 /* Clear the command complete status bit */
920 ti_mmchs_write_4(sc, MMCHS_STAT, MMCHS_STAT_CC);
922 /* Write another dummy command 0x00 */
923 ti_mmchs_write_4(sc, MMCHS_CMD, 0x00000000);
925 /* Loop waiting for the second command to finish */
929 if (timeout-- == 0) {
930 device_printf(sc->sc_dev, "Error: second stream init timed out\n");
933 } while (!(ti_mmchs_read_4(sc, MMCHS_STAT) & MMCHS_STAT_CC));
935 /* Clear the stream init bit */
936 con &= ~MMCHS_CON_INIT;
937 ti_mmchs_write_4(sc, MMCHS_CON, con);
939 /* Clear the status register, then restore the IE and ISE registers */
940 ti_mmchs_write_4(sc, MMCHS_STAT, 0xffffffff);
941 ti_mmchs_read_4(sc, MMCHS_STAT);
943 ti_mmchs_write_4(sc, MMCHS_ISE, ise);
944 ti_mmchs_write_4(sc, MMCHS_IE, ie);
948 * ti_mmchs_update_ios - sets bus/controller settings
949 * @brdev: mmc bridge device handle
950 * @reqdev: device doing the request
952 * Called to set the bus and controller settings that need to be applied to
953 * the actual HW. Currently this function just sets the bus width and the
960 * 0 if function succeeded
963 ti_mmchs_update_ios(device_t brdev, device_t reqdev)
965 struct ti_mmchs_softc *sc;
966 struct mmc_host *host;
972 #ifndef SOC_TI_AM335X
975 unsigned long timeout;
976 int do_card_init = 0;
978 sc = device_get_softc(brdev);
982 /* Read the initial values of the registers */
983 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL);
984 con_reg = ti_mmchs_read_4(sc, MMCHS_CON);
986 /* Set the bus width */
987 switch (ios->bus_width) {
989 hctl_reg &= ~MMCHS_HCTL_DTW;
990 con_reg &= ~MMCHS_CON_DW8;
993 hctl_reg |= MMCHS_HCTL_DTW;
994 con_reg &= ~MMCHS_CON_DW8;
997 con_reg |= MMCHS_CON_DW8;
1001 /* Finally write all these settings back to the registers */
1002 ti_mmchs_write_4(sc, MMCHS_HCTL, hctl_reg);
1003 ti_mmchs_write_4(sc, MMCHS_CON, con_reg);
1005 /* Check if we need to change the external voltage regulator */
1006 if (sc->sc_cur_power_mode != ios->power_mode) {
1008 if (ios->power_mode == power_up) {
1010 /* Set the power level */
1011 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL);
1012 hctl_reg &= ~(MMCHS_HCTL_SDVS_MASK | MMCHS_HCTL_SDBP);
1014 if ((ios->vdd == -1) || (ios->vdd >= vdd_240)) {
1015 #ifndef SOC_TI_AM335X
1018 hctl_reg |= MMCHS_HCTL_SDVS_V30;
1020 #ifndef SOC_TI_AM335X
1023 hctl_reg |= MMCHS_HCTL_SDVS_V18;
1026 ti_mmchs_write_4(sc, MMCHS_HCTL, hctl_reg);
1028 #ifdef SOC_TI_AM335X
1029 printf("%s: TWL unimplemented\n", __func__);
1031 /* Set the desired voltage on the regulator */
1032 if (sc->sc_vreg_dev && sc->sc_vreg_name)
1033 twl_vreg_set_voltage(sc->sc_vreg_dev, sc->sc_vreg_name, mv);
1035 /* Enable the bus power */
1036 ti_mmchs_write_4(sc, MMCHS_HCTL, (hctl_reg | MMCHS_HCTL_SDBP));
1038 while (!(ti_mmchs_read_4(sc, MMCHS_HCTL) & MMCHS_HCTL_SDBP)) {
1041 pause("MMC_PWRON", 1);
1044 } else if (ios->power_mode == power_off) {
1045 /* Disable the bus power */
1046 hctl_reg = ti_mmchs_read_4(sc, MMCHS_HCTL);
1047 ti_mmchs_write_4(sc, MMCHS_HCTL, (hctl_reg & ~MMCHS_HCTL_SDBP));
1049 #ifdef SOC_TI_AM335X
1050 printf("%s: TWL unimplemented\n", __func__);
1052 /* Turn the power off on the voltage regulator */
1053 if (sc->sc_vreg_dev && sc->sc_vreg_name)
1054 twl_vreg_set_voltage(sc->sc_vreg_dev, sc->sc_vreg_name, 0);
1056 } else if (ios->power_mode == power_on) {
1057 /* Force a card re-initialisation sequence */
1061 /* Save the new power state */
1062 sc->sc_cur_power_mode = ios->power_mode;
1065 /* need the MMCHS_SYSCTL register */
1066 sysctl_reg = ti_mmchs_read_4(sc, MMCHS_SYSCTL);
1068 /* Just in case this hasn't been setup before, set the timeout to the default */
1069 sysctl_reg &= ~MMCHS_SYSCTL_DTO_MASK;
1070 sysctl_reg |= MMCHS_SYSCTL_DTO(0xe);
1072 /* Disable the clock output while configuring the new clock */
1073 sysctl_reg &= ~(MMCHS_SYSCTL_ICE | MMCHS_SYSCTL_CEN);
1074 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg);
1077 if (ios->clock == 0) {
1080 clkdiv = sc->sc_ref_freq / ios->clock;
1083 if ((sc->sc_ref_freq / clkdiv) > ios->clock)
1089 /* Set the new clock divider */
1090 sysctl_reg &= ~MMCHS_SYSCTL_CLKD_MASK;
1091 sysctl_reg |= MMCHS_SYSCTL_CLKD(clkdiv);
1093 /* Write the new settings ... */
1094 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg);
1095 /* ... write the internal clock enable bit ... */
1096 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg | MMCHS_SYSCTL_ICE);
1097 /* ... wait for the clock to stablise ... */
1098 while (((sysctl_reg = ti_mmchs_read_4(sc, MMCHS_SYSCTL)) &
1099 MMCHS_SYSCTL_ICS) == 0) {
1102 /* ... then enable */
1103 sysctl_reg |= MMCHS_SYSCTL_CEN;
1104 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl_reg);
1106 /* If the power state has changed to 'power_on' then run the init sequence*/
1108 ti_mmchs_send_init_stream(sc);
1111 /* Set the bus mode (opendrain or normal) */
1112 con_reg = ti_mmchs_read_4(sc, MMCHS_CON);
1113 if (ios->bus_mode == opendrain)
1114 con_reg |= MMCHS_CON_OD;
1116 con_reg &= ~MMCHS_CON_OD;
1117 ti_mmchs_write_4(sc, MMCHS_CON, con_reg);
1123 * ti_mmchs_acquire_host -
1124 * @brdev: mmc bridge device handle
1125 * @reqdev: device doing the request
1127 * TODO: Is this function needed ?
1133 * 0 function succeeded
1137 ti_mmchs_acquire_host(device_t brdev, device_t reqdev)
1139 struct ti_mmchs_softc *sc = device_get_softc(brdev);
1144 while (sc->bus_busy) {
1145 msleep(sc, &sc->sc_mtx, PZERO, "mmc", hz / 5);
1150 TI_MMCHS_UNLOCK(sc);
1156 * ti_mmchs_release_host -
1157 * @brdev: mmc bridge device handle
1158 * @reqdev: device doing the request
1160 * TODO: Is this function needed ?
1166 * 0 function succeeded
1170 ti_mmchs_release_host(device_t brdev, device_t reqdev)
1172 struct ti_mmchs_softc *sc = device_get_softc(brdev);
1179 TI_MMCHS_UNLOCK(sc);
1185 * ti_mmchs_read_ivar - returns driver conf variables
1188 * @which: The variable to get the result for
1189 * @result: Upon return will store the variable value
1194 * None, caller must hold locks
1198 * EINVAL if the variable requested is invalid
1201 ti_mmchs_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1203 struct ti_mmchs_softc *sc = device_get_softc(bus);
1206 case MMCBR_IVAR_BUS_MODE:
1207 *(int *)result = sc->host.ios.bus_mode;
1209 case MMCBR_IVAR_BUS_WIDTH:
1210 *(int *)result = sc->host.ios.bus_width;
1212 case MMCBR_IVAR_CHIP_SELECT:
1213 *(int *)result = sc->host.ios.chip_select;
1215 case MMCBR_IVAR_CLOCK:
1216 *(int *)result = sc->host.ios.clock;
1218 case MMCBR_IVAR_F_MIN:
1219 *(int *)result = sc->host.f_min;
1221 case MMCBR_IVAR_F_MAX:
1222 *(int *)result = sc->host.f_max;
1224 case MMCBR_IVAR_HOST_OCR:
1225 *(int *)result = sc->host.host_ocr;
1227 case MMCBR_IVAR_MODE:
1228 *(int *)result = sc->host.mode;
1230 case MMCBR_IVAR_OCR:
1231 *(int *)result = sc->host.ocr;
1233 case MMCBR_IVAR_POWER_MODE:
1234 *(int *)result = sc->host.ios.power_mode;
1236 case MMCBR_IVAR_VDD:
1237 *(int *)result = sc->host.ios.vdd;
1239 case MMCBR_IVAR_CAPS:
1240 *(int *)result = sc->host.caps;
1242 case MMCBR_IVAR_MAX_DATA:
1252 * ti_mmchs_write_ivar - writes a driver conf variables
1255 * @which: The variable to set
1256 * @value: The value to write into the variable
1261 * None, caller must hold locks
1265 * EINVAL if the variable requested is invalid
1268 ti_mmchs_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1270 struct ti_mmchs_softc *sc = device_get_softc(bus);
1273 case MMCBR_IVAR_BUS_MODE:
1274 sc->host.ios.bus_mode = value;
1276 case MMCBR_IVAR_BUS_WIDTH:
1277 sc->host.ios.bus_width = value;
1279 case MMCBR_IVAR_CHIP_SELECT:
1280 sc->host.ios.chip_select = value;
1282 case MMCBR_IVAR_CLOCK:
1283 sc->host.ios.clock = value;
1285 case MMCBR_IVAR_MODE:
1286 sc->host.mode = value;
1288 case MMCBR_IVAR_OCR:
1289 sc->host.ocr = value;
1291 case MMCBR_IVAR_POWER_MODE:
1292 sc->host.ios.power_mode = value;
1294 case MMCBR_IVAR_VDD:
1295 sc->host.ios.vdd = value;
1297 /* These are read-only */
1298 case MMCBR_IVAR_CAPS:
1299 case MMCBR_IVAR_HOST_OCR:
1300 case MMCBR_IVAR_F_MIN:
1301 case MMCBR_IVAR_F_MAX:
1302 case MMCBR_IVAR_MAX_DATA:
1311 * ti_mmchs_hw_init - initialises the MMC/SD/SIO controller
1312 * @dev: mmc device handle
1314 * Called by the driver attach function during driver initialisation. This
1315 * function is responsibly to setup the controller ready for transactions.
1318 * No locking, assumed to only be called during initialisation.
1324 ti_mmchs_hw_init(device_t dev)
1326 struct ti_mmchs_softc *sc = device_get_softc(dev);
1328 unsigned long timeout;
1331 uint32_t con, sysconfig;
1333 /* 1: Enable the controller and interface/functional clocks */
1334 clk = MMC0_CLK + sc->device_id;
1336 if (ti_prcm_clk_enable(clk) != 0) {
1337 device_printf(dev, "Error: failed to enable MMC clock\n");
1341 /* 1a: Get the frequency of the source clock */
1342 if (ti_prcm_clk_get_source_freq(clk, &sc->sc_ref_freq) != 0) {
1343 device_printf(dev, "Error: failed to get source clock freq\n");
1347 /* 2: Issue a softreset to the controller */
1348 sysconfig = ti_mmchs_read_4(sc, MMCHS_SYSCONFIG);
1349 sysconfig |= MMCHS_SYSCONFIG_SRST;
1350 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, sysconfig);
1352 while ((ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 0x01) == 0x0) {
1354 if (timeout-- == 0) {
1355 device_printf(dev, "Error: reset operation timed out\n");
1360 /* 3: Reset both the command and data state machines */
1361 sysctl = ti_mmchs_read_4(sc, MMCHS_SYSCTL);
1362 ti_mmchs_write_4(sc, MMCHS_SYSCTL, sysctl | MMCHS_SYSCTL_SRA);
1364 while ((ti_mmchs_read_4(sc, MMCHS_SYSCTL) & MMCHS_SYSCTL_SRA) != 0x0) {
1366 if (timeout-- == 0) {
1367 device_printf(dev, "Error: reset operation timed out\n");
1372 /* 4: Set initial host configuration (1-bit mode, pwroff) and capabilities */
1373 ti_mmchs_write_4(sc, MMCHS_HCTL, MMCHS_HCTL_SDVS_V30);
1375 capa = ti_mmchs_read_4(sc, MMCHS_CAPA);
1376 ti_mmchs_write_4(sc, MMCHS_CAPA, capa | MMCHS_CAPA_VS30 | MMCHS_CAPA_VS18);
1378 /* 5: Set the initial bus configuration
1379 * 0 CTPL_MMC_SD : Control Power for DAT1 line
1380 * 0 WPP_ACTIVE_HIGH : Write protect polarity
1381 * 0 CDP_ACTIVE_HIGH : Card detect polarity
1382 * 0 CTO_ENABLED : MMC interrupt command
1383 * 0 DW8_DISABLED : 8-bit mode MMC select
1384 * 0 MODE_FUNC : Mode select
1385 * 0 STREAM_DISABLED : Stream command
1386 * 0 HR_DISABLED : Broadcast host response
1387 * 0 INIT_DISABLED : Send initialization stream
1388 * 0 OD_DISABLED : No Open Drain
1390 con = ti_mmchs_read_4(sc, MMCHS_CON) & MMCHS_CON_DVAL_MASK;
1391 ti_mmchs_write_4(sc, MMCHS_CON, con);
1396 * ti_mmchs_fini - shutdown the MMC/SD/SIO controller
1397 * @dev: mmc device handle
1399 * Responsible for shutting done the MMC controller, this function may be
1400 * called as part of a reset sequence.
1403 * No locking, assumed to be called during tear-down/reset.
1409 ti_mmchs_hw_fini(device_t dev)
1411 struct ti_mmchs_softc *sc = device_get_softc(dev);
1413 /* Disable all interrupts */
1414 ti_mmchs_write_4(sc, MMCHS_ISE, 0x00000000);
1415 ti_mmchs_write_4(sc, MMCHS_IE, 0x00000000);
1417 /* Disable the functional and interface clocks */
1418 ti_prcm_clk_disable(MMC0_CLK + sc->device_id);
1422 * ti_mmchs_init_dma_channels - initalise the DMA channels
1423 * @sc: driver soft context
1425 * Attempts to activate an RX and TX DMA channel for the MMC device.
1428 * No locking, assumed to be called during tear-down/reset.
1431 * 0 on success, a negative error code on failure.
1434 ti_mmchs_init_dma_channels(struct ti_mmchs_softc *sc)
1436 #ifdef SOC_TI_AM335X
1437 switch (sc->device_id) {
1439 sc->dma_tx_trig = TI_EDMA3_EVENT_SDTXEVT0;
1440 sc->dma_rx_trig = TI_EDMA3_EVENT_SDRXEVT0;
1443 sc->dma_tx_trig = TI_EDMA3_EVENT_SDTXEVT1;
1444 sc->dma_rx_trig = TI_EDMA3_EVENT_SDRXEVT1;
1451 /* TODO EDMA3 have 3 queues, so we need some queue allocation call */
1452 ti_edma3_init(EVTQNUM);
1453 ti_edma3_request_dma_ch(sc->dma_tx_trig, sc->dma_tx_trig, EVTQNUM);
1454 ti_edma3_request_dma_ch(sc->dma_rx_trig, sc->dma_rx_trig, EVTQNUM);
1459 /* Get the current chip revision */
1460 rev = ti_revision();
1461 if ((OMAP_REV_DEVICE(rev) != OMAP4430_DEV) && (sc->device_id > 3))
1464 /* Get the DMA MMC triggers */
1465 switch (sc->device_id) {
1467 sc->dma_tx_trig = 60;
1468 sc->dma_rx_trig = 61;
1471 sc->dma_tx_trig = 46;
1472 sc->dma_rx_trig = 47;
1475 sc->dma_tx_trig = 76;
1476 sc->dma_rx_trig = 77;
1478 /* The following are OMAP4 only */
1480 sc->dma_tx_trig = 56;
1481 sc->dma_rx_trig = 57;
1484 sc->dma_tx_trig = 58;
1485 sc->dma_rx_trig = 59;
1491 /* Activate a RX channel from the OMAP DMA driver */
1492 err = ti_sdma_activate_channel(&sc->sc_dmach_rd, ti_mmchs_dma_intr, sc);
1496 /* Setup the RX channel for MMC data transfers */
1497 ti_sdma_set_xfer_burst(sc->sc_dmach_rd, TI_SDMA_BURST_NONE,
1499 ti_sdma_set_xfer_data_type(sc->sc_dmach_rd, TI_SDMA_DATA_32BITS_SCALAR);
1500 ti_sdma_sync_params(sc->sc_dmach_rd, sc->dma_rx_trig,
1501 TI_SDMA_SYNC_PACKET | TI_SDMA_SYNC_TRIG_ON_SRC);
1502 ti_sdma_set_addr_mode(sc->sc_dmach_rd, TI_SDMA_ADDR_CONSTANT,
1503 TI_SDMA_ADDR_POST_INCREMENT);
1505 /* Activate and configure the TX DMA channel */
1506 err = ti_sdma_activate_channel(&sc->sc_dmach_wr, ti_mmchs_dma_intr, sc);
1510 /* Setup the TX channel for MMC data transfers */
1511 ti_sdma_set_xfer_burst(sc->sc_dmach_wr, TI_SDMA_BURST_64,
1512 TI_SDMA_BURST_NONE);
1513 ti_sdma_set_xfer_data_type(sc->sc_dmach_wr, TI_SDMA_DATA_32BITS_SCALAR);
1514 ti_sdma_sync_params(sc->sc_dmach_wr, sc->dma_tx_trig,
1515 TI_SDMA_SYNC_PACKET | TI_SDMA_SYNC_TRIG_ON_DST);
1516 ti_sdma_set_addr_mode(sc->sc_dmach_wr, TI_SDMA_ADDR_POST_INCREMENT,
1517 TI_SDMA_ADDR_CONSTANT);
1523 * ti_mmchs_deactivate - deactivates the driver
1524 * @dev: mmc device handle
1526 * Unmaps the register set and releases the IRQ resource.
1535 ti_mmchs_deactivate(device_t dev)
1537 struct ti_mmchs_softc *sc= device_get_softc(dev);
1539 /* Remove the IRQ handler */
1540 if (sc->sc_irq_h != NULL) {
1541 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
1542 sc->sc_irq_h = NULL;
1545 /* Do the generic detach */
1546 bus_generic_detach(sc->sc_dev);
1548 #ifdef SOC_TI_AM335X
1549 printf("%s: DMA unimplemented\n", __func__);
1551 /* Deactivate the DMA channels */
1552 ti_sdma_deactivate_channel(sc->sc_dmach_rd);
1553 ti_sdma_deactivate_channel(sc->sc_dmach_wr);
1556 /* Unmap the MMC controller registers */
1557 if (sc->sc_mem_res != 0) {
1558 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->sc_irq_res),
1560 sc->sc_mem_res = NULL;
1563 /* Release the IRQ resource */
1564 if (sc->sc_irq_res != NULL) {
1565 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->sc_irq_res),
1567 sc->sc_irq_res = NULL;
1574 * ti_mmchs_activate - activates the driver
1575 * @dev: mmc device handle
1577 * Maps in the register set and requests an IRQ handler for the MMC controller.
1584 * ENOMEM if failed to map register set
1587 ti_mmchs_activate(device_t dev)
1589 struct ti_mmchs_softc *sc = device_get_softc(dev);
1593 /* Get the memory resource for the register mapping */
1595 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1597 if (sc->sc_mem_res == NULL)
1598 panic("%s: Cannot map registers", device_get_name(dev));
1600 /* Allocate an IRQ resource for the MMC controller */
1602 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1603 RF_ACTIVE | RF_SHAREABLE);
1604 if (sc->sc_irq_res == NULL)
1607 /* Allocate DMA tags and maps */
1608 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1609 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1610 NULL, MAXPHYS, 1, MAXPHYS, BUS_DMA_ALLOCNOW, NULL,
1611 NULL, &sc->sc_dmatag);
1615 err = bus_dmamap_create(sc->sc_dmatag, 0, &sc->sc_dmamap);
1619 /* Initialise the DMA channels to be used by the controller */
1620 err = ti_mmchs_init_dma_channels(sc);
1624 /* Set the register offset */
1625 if (ti_chip() == CHIP_OMAP_3)
1626 sc->sc_reg_off = OMAP3_MMCHS_REG_OFFSET;
1627 else if (ti_chip() == CHIP_OMAP_4)
1628 sc->sc_reg_off = OMAP4_MMCHS_REG_OFFSET;
1629 else if (ti_chip() == CHIP_AM335X)
1630 sc->sc_reg_off = AM335X_MMCHS_REG_OFFSET;
1632 panic("Unknown OMAP device\n");
1634 /* Get the physical address of the MMC data register, needed for DMA */
1635 sc->sc_data_reg_paddr = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
1636 sc->sc_reg_off + MMCHS_DATA);
1638 /* Set the initial power state to off */
1639 sc->sc_cur_power_mode = power_off;
1644 ti_mmchs_deactivate(dev);
1649 * ti_mmchs_probe - probe function for the driver
1650 * @dev: mmc device handle
1658 ti_mmchs_probe(device_t dev)
1660 if (!ofw_bus_is_compatible(dev, "ti,mmchs"))
1663 device_set_desc(dev, "TI MMC/SD/SDIO High Speed Interface");
1668 * ti_mmchs_attach - attach function for the driver
1669 * @dev: mmc device handle
1671 * Driver initialisation, sets-up the bus mappings, DMA mapping/channels and
1672 * the actual controller by calling ti_mmchs_init().
1675 * Returns 0 on success or a negative error code.
1678 ti_mmchs_attach(device_t dev)
1680 struct ti_mmchs_softc *sc = device_get_softc(dev);
1681 int unit = device_get_unit(dev);
1686 /* Save the device and bus tag */
1689 /* Get the mmchs device id from FDT */
1690 node = ofw_bus_get_node(dev);
1691 if ((OF_getprop(node, "mmchs-device-id", &did, sizeof(did))) <= 0) {
1692 device_printf(dev, "missing mmchs-device-id attribute in FDT\n");
1695 sc->device_id = fdt32_to_cpu(did);
1697 /* Initiate the mtex lock */
1698 TI_MMCHS_LOCK_INIT(sc);
1700 /* Indicate the DMA channels haven't yet been allocated */
1701 sc->sc_dmach_rd = (unsigned int)-1;
1702 sc->sc_dmach_wr = (unsigned int)-1;
1704 /* Get the hint'ed write detect pin */
1705 /* TODO: take this from FDT */
1706 if (resource_int_value("ti_mmchs", unit, "wp_gpio", &sc->sc_wp_gpio_pin) != 0){
1707 sc->sc_wp_gpio_pin = -1;
1709 /* Get the GPIO device, we need this for the write protect pin */
1710 sc->sc_gpio_dev = devclass_get_device(devclass_find("gpio"), 0);
1711 if (sc->sc_gpio_dev == NULL)
1712 device_printf(dev, "Error: failed to get the GPIO device\n");
1714 GPIO_PIN_SETFLAGS(sc->sc_gpio_dev, sc->sc_wp_gpio_pin,
1718 /* Get the TWL voltage regulator device, we need this to for setting the
1719 * voltage of the bus on certain OMAP platforms.
1721 sc->sc_vreg_name = NULL;
1723 /* TODO: add voltage regulator knob to FDT */
1725 sc->sc_vreg_dev = devclass_get_device(devclass_find("twl_vreg"), 0);
1726 if (sc->sc_vreg_dev == NULL) {
1727 device_printf(dev, "Error: failed to get the votlage regulator"
1729 sc->sc_vreg_name = NULL;
1733 /* Activate the device */
1734 err = ti_mmchs_activate(dev);
1738 /* Initialise the controller */
1739 ti_mmchs_hw_init(dev);
1741 /* Activate the interrupt and attach a handler */
1742 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
1743 NULL, ti_mmchs_intr, sc, &sc->sc_irq_h);
1747 /* Add host details */
1748 sc->host.f_min = sc->sc_ref_freq / 1023;
1749 sc->host.f_max = sc->sc_ref_freq;
1750 sc->host.host_ocr = MMC_OCR_290_300 | MMC_OCR_300_310;
1751 sc->host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
1753 device_add_child(dev, "mmc", 0);
1755 device_set_ivars(dev, &sc->host);
1756 err = bus_generic_attach(dev);
1760 TI_MMCHS_LOCK_DESTROY(sc);
1761 ti_mmchs_deactivate(dev);
1763 #ifdef SOC_TI_AM335X
1764 printf("%s: DMA unimplemented\n", __func__);
1766 if (sc->sc_dmach_rd != (unsigned int)-1)
1767 ti_sdma_deactivate_channel(sc->sc_dmach_rd);
1768 if (sc->sc_dmach_wr != (unsigned int)-1)
1769 ti_sdma_deactivate_channel(sc->sc_dmach_wr);
1777 * ti_mmchs_detach - dettach function for the driver
1778 * @dev: mmc device handle
1780 * Shutdowns the controll and release resources allocated by the driver.
1786 ti_mmchs_detach(device_t dev)
1788 #ifndef SOC_TI_AM335X
1789 struct ti_mmchs_softc *sc = device_get_softc(dev);
1792 ti_mmchs_hw_fini(dev);
1793 ti_mmchs_deactivate(dev);
1795 #ifdef SOC_TI_AM335X
1796 printf("%s: DMA unimplemented\n", __func__);
1798 ti_sdma_deactivate_channel(sc->sc_dmach_wr);
1799 ti_sdma_deactivate_channel(sc->sc_dmach_rd);
1805 static device_method_t ti_mmchs_methods[] = {
1807 DEVMETHOD(device_probe, ti_mmchs_probe),
1808 DEVMETHOD(device_attach, ti_mmchs_attach),
1809 DEVMETHOD(device_detach, ti_mmchs_detach),
1812 DEVMETHOD(bus_read_ivar, ti_mmchs_read_ivar),
1813 DEVMETHOD(bus_write_ivar, ti_mmchs_write_ivar),
1815 /* mmcbr_if - MMC state machine callbacks */
1816 DEVMETHOD(mmcbr_update_ios, ti_mmchs_update_ios),
1817 DEVMETHOD(mmcbr_request, ti_mmchs_request),
1818 DEVMETHOD(mmcbr_get_ro, ti_mmchs_get_ro),
1819 DEVMETHOD(mmcbr_acquire_host, ti_mmchs_acquire_host),
1820 DEVMETHOD(mmcbr_release_host, ti_mmchs_release_host),
1825 static driver_t ti_mmchs_driver = {
1828 sizeof(struct ti_mmchs_softc),
1830 static devclass_t ti_mmchs_devclass;
1832 DRIVER_MODULE(ti_mmchs, simplebus, ti_mmchs_driver, ti_mmchs_devclass, 0, 0);
1833 MODULE_DEPEND(ti_mmchs, ti_prcm, 1, 1, 1);
1834 #ifdef SOC_TI_AM335X
1835 MODULE_DEPEND(ti_mmchs, ti_edma, 1, 1, 1);
1837 MODULE_DEPEND(ti_mmchs, ti_sdma, 1, 1, 1);
1839 MODULE_DEPEND(ti_mmchs, ti_gpio, 1, 1, 1);
1841 /* FIXME: MODULE_DEPEND(ti_mmchs, twl_vreg, 1, 1, 1); */