2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/intr.h>
47 #include <dev/fdt/fdt_common.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/mmc/bridge.h>
52 #include <dev/mmc/mmcreg.h>
53 #include <dev/mmc/mmcbrvar.h>
55 #include <dev/sdhci/sdhci.h>
58 #include <arm/ti/ti_cpuid.h>
59 #include <arm/ti/ti_prcm.h>
62 struct ti_sdhci_softc {
65 struct resource * mem_res;
66 struct resource * irq_res;
68 struct sdhci_slot slot;
69 uint32_t mmchs_device_id;
70 uint32_t mmchs_reg_off;
71 uint32_t sdhci_reg_off;
74 uint32_t cmd_and_mode;
75 uint32_t sdhci_clkdiv;
76 boolean_t disable_highspeed;
77 boolean_t force_card_present;
81 * Table of supported FDT compat strings.
83 * Note that "ti,mmchs" is our own invention, and should be phased out in favor
84 * of the documented names.
86 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
88 static struct ofw_compat_data compat_data[] = {
89 {"ti,omap3-hsmmc", 1},
90 {"ti,omap4-hsmmc", 1},
96 * The MMCHS hardware has a few control and status registers at the beginning of
97 * the device's memory map, followed by the standard sdhci register block.
98 * Different SoCs have the register blocks at different offsets from the
99 * beginning of the device. Define some constants to map out the registers we
100 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
101 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs.
103 #define OMAP3_MMCHS_REG_OFFSET 0x000
104 #define OMAP4_MMCHS_REG_OFFSET 0x100
105 #define AM335X_MMCHS_REG_OFFSET 0x100
106 #define SDHCI_REG_OFFSET 0x100
108 #define MMCHS_SYSCONFIG 0x010
109 #define MMCHS_SYSCONFIG_RESET (1 << 1)
110 #define MMCHS_SYSSTATUS 0x014
111 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
112 #define MMCHS_CON 0x02C
113 #define MMCHS_CON_DW8 (1 << 5)
114 #define MMCHS_CON_DVAL_8_4MS (3 << 9)
115 #define MMCHS_CON_OD (1 << 0)
116 #define MMCHS_SYSCTL 0x12C
117 #define MMCHS_SYSCTL_CLKD_MASK 0x3FF
118 #define MMCHS_SYSCTL_CLKD_SHIFT 6
119 #define MMCHS_SD_CAPA 0x140
120 #define MMCHS_SD_CAPA_VS18 (1 << 26)
121 #define MMCHS_SD_CAPA_VS30 (1 << 25)
122 #define MMCHS_SD_CAPA_VS33 (1 << 24)
124 static inline uint32_t
125 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off)
128 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));
132 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
135 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);
138 static inline uint32_t
139 RD4(struct ti_sdhci_softc *sc, bus_size_t off)
142 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));
146 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
149 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);
153 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
155 struct ti_sdhci_softc *sc = device_get_softc(dev);
157 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
161 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
163 struct ti_sdhci_softc *sc = device_get_softc(dev);
164 uint32_t clkdiv, val32;
167 * The MMCHS hardware has a non-standard interpretation of the sdclock
168 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6)
169 * but doesn't split them into low:high fields. Instead they're a
170 * single number in the range 0..1023 and the number is exactly the
171 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI
172 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking
173 * here extracts the MMCHS representation from the hardware word, cleans
174 * those bits out, applies the 2N adjustment, and plugs the result into
175 * the bit positions for the 2.0 or 3.0 divisor in the returned register
176 * value. The ti_sdhci_write_2() routine performs the opposite
177 * transformation when the SDHCI driver writes to the register.
179 if (off == SDHCI_CLOCK_CONTROL) {
180 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
181 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) &
182 MMCHS_SYSCTL_CLKD_MASK) / 2;
183 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT);
184 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
185 if (slot->version >= SDHCI_SPEC_300)
186 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) &
187 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT;
188 return (val32 & 0xffff);
192 * Standard 32-bit handling of command and transfer mode.
194 if (off == SDHCI_TRANSFER_MODE) {
195 return (sc->cmd_and_mode >> 16);
196 } else if (off == SDHCI_COMMAND_FLAGS) {
197 return (sc->cmd_and_mode & 0x0000ffff);
200 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
204 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
206 struct ti_sdhci_softc *sc = device_get_softc(dev);
209 val32 = RD4(sc, off);
212 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip
213 * that flag from the returned capabilities.
215 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed)
216 val32 &= ~SDHCI_CAN_DO_HISPD;
219 * Force the card-present state if necessary.
221 if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
222 val32 |= SDHCI_CARD_PRESENT;
228 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
229 uint32_t *data, bus_size_t count)
231 struct ti_sdhci_softc *sc = device_get_softc(dev);
233 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
237 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
240 struct ti_sdhci_softc *sc = device_get_softc(dev);
243 val32 = RD4(sc, off & ~3);
244 val32 &= ~(0xff << (off & 3) * 8);
245 val32 |= (val << (off & 3) * 8);
247 WR4(sc, off & ~3, val32);
251 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
254 struct ti_sdhci_softc *sc = device_get_softc(dev);
255 uint32_t clkdiv, val32;
258 * Translate between the hardware and SDHCI 2.0 or 3.0 representations
259 * of the clock divisor. See the comments in ti_sdhci_read_2() for
262 if (off == SDHCI_CLOCK_CONTROL) {
263 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
264 if (slot->version >= SDHCI_SPEC_300)
265 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) &
266 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
268 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK)
269 clkdiv = MMCHS_SYSCTL_CLKD_MASK;
270 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
272 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK <<
273 MMCHS_SYSCTL_CLKD_SHIFT);
274 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT;
275 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
280 * Standard 32-bit handling of command and transfer mode.
282 if (off == SDHCI_TRANSFER_MODE) {
283 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) |
284 ((uint32_t)val & 0x0000ffff);
286 } else if (off == SDHCI_COMMAND_FLAGS) {
287 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) |
288 ((uint32_t)val << 16);
289 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
293 val32 = RD4(sc, off & ~3);
294 val32 &= ~(0xffff << (off & 3) * 8);
295 val32 |= ((val & 0xffff) << (off & 3) * 8);
296 WR4(sc, off & ~3, val32);
300 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
303 struct ti_sdhci_softc *sc = device_get_softc(dev);
309 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
310 uint32_t *data, bus_size_t count)
312 struct ti_sdhci_softc *sc = device_get_softc(dev);
314 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
318 ti_sdhci_intr(void *arg)
320 struct ti_sdhci_softc *sc = arg;
322 sdhci_generic_intr(&sc->slot);
326 ti_sdhci_update_ios(device_t brdev, device_t reqdev)
328 struct ti_sdhci_softc *sc = device_get_softc(brdev);
329 struct sdhci_slot *slot;
331 uint32_t val32, newval32;
333 slot = device_get_ivars(reqdev);
334 ios = &slot->host.ios;
337 * There is an 8-bit-bus bit in the MMCHS control register which, when
338 * set, overrides the 1 vs 4 bit setting in the standard SDHCI
339 * registers. Set that bit first according to whether an 8-bit bus is
340 * requested, then let the standard driver handle everything else.
342 val32 = ti_mmchs_read_4(sc, MMCHS_CON);
345 if (ios->bus_width == bus_width_8)
346 newval32 |= MMCHS_CON_DW8;
348 newval32 &= ~MMCHS_CON_DW8;
350 if (ios->bus_mode == opendrain)
351 newval32 |= MMCHS_CON_OD;
352 else /* if (ios->bus_mode == pushpull) */
353 newval32 &= ~MMCHS_CON_OD;
355 if (newval32 != val32)
356 ti_mmchs_write_4(sc, MMCHS_CON, newval32);
358 return (sdhci_generic_update_ios(brdev, reqdev));
362 ti_sdhci_get_ro(device_t brdev, device_t reqdev)
364 struct ti_sdhci_softc *sc = device_get_softc(brdev);
365 unsigned int readonly = 0;
367 /* If a gpio pin is configured, read it. */
368 if (sc->gpio_dev != NULL) {
369 GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly);
376 ti_sdhci_detach(device_t dev)
383 ti_sdhci_hw_init(device_t dev)
385 struct ti_sdhci_softc *sc = device_get_softc(dev);
388 unsigned long timeout;
390 /* Enable the controller and interface/functional clocks */
391 clk = MMC0_CLK + sc->mmchs_device_id;
392 if (ti_prcm_clk_enable(clk) != 0) {
393 device_printf(dev, "Error: failed to enable MMC clock\n");
397 /* Get the frequency of the source clock */
398 if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) {
399 device_printf(dev, "Error: failed to get source clock freq\n");
403 /* Issue a softreset to the controller */
404 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET);
406 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) &
407 MMCHS_SYSSTATUS_RESETDONE)) {
408 if (--timeout == 0) {
410 "Error: Controller reset operation timed out\n");
417 * Reset the command and data state machines and also other aspects of
418 * the controller such as bus clock and power.
420 * If we read the software reset register too fast after writing it we
421 * can get back a zero that means the reset hasn't started yet rather
422 * than that the reset is complete. Per TI recommendations, work around
423 * it by reading until we see the reset bit asserted, then read until
424 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk
425 * so that the main sdhci driver uses this same logic in its resets.
427 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL);
429 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
430 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) {
431 if (--timeout == 0) {
437 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) &
439 if (--timeout == 0) {
441 "Error: Software reset operation timed out\n");
448 * The attach() routine has examined fdt data and set flags in
449 * slot.host.caps to reflect what voltages we can handle. Set those
450 * values in the CAPA register. The manual says that these values can
451 * only be set once, "before initialization" whatever that means, and
452 * that they survive a reset. So maybe doing this will be a no-op if
453 * u-boot has already initialized the hardware.
455 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA);
456 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE)
457 regval |= MMCHS_SD_CAPA_VS18;
458 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310))
459 regval |= MMCHS_SD_CAPA_VS30;
460 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval);
462 /* Set initial host configuration (1-bit, std speed, pwr off). */
463 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0);
464 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0);
466 /* Set the initial controller configuration. */
467 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS);
471 ti_sdhci_attach(device_t dev)
473 struct ti_sdhci_softc *sc = device_get_softc(dev);
481 * Get the MMCHS device id from FDT. If it's not there use the newbus
482 * unit number (which will work as long as the devices are in order and
483 * none are skipped in the fdt). Note that this is a property we made
484 * up and added in freebsd, it doesn't exist in the published bindings.
486 node = ofw_bus_get_node(dev);
487 if ((OF_getprop(node, "mmchs-device-id", &prop, sizeof(prop))) <= 0) {
488 sc->mmchs_device_id = device_get_unit(dev);
489 device_printf(dev, "missing mmchs-device-id attribute in FDT, "
490 "using unit number (%d)", sc->mmchs_device_id);
492 sc->mmchs_device_id = fdt32_to_cpu(prop);
495 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first
496 * device, and only 1p8v on other devices unless an external transceiver
497 * is used. The only way we could know about a transceiver is fdt data.
498 * Note that we have to do this before calling ti_sdhci_hw_init() so
499 * that it can set the right values in the CAPA register, which can only
500 * be done once and never reset.
502 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE;
503 if (sc->mmchs_device_id == 0 || OF_hasprop(node, "ti,dual-volt")) {
504 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310;
508 * See if we've got a GPIO-based write detect pin. This is not the
509 * standard documented property for this, we added it in freebsd.
511 if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0)
512 sc->wp_gpio_pin = 0xffffffff;
514 sc->wp_gpio_pin = fdt32_to_cpu(prop);
516 if (sc->wp_gpio_pin != 0xffffffff) {
517 sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0);
518 if (sc->gpio_dev == NULL)
519 device_printf(dev, "Error: No GPIO device, "
520 "Write Protect pin will not function\n");
522 GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin,
527 * Set the offset from the device's memory start to the MMCHS registers.
528 * Also for OMAP4 disable high speed mode due to erratum ID i626.
530 if (ti_chip() == CHIP_OMAP_3)
531 sc->mmchs_reg_off = OMAP3_MMCHS_REG_OFFSET;
532 else if (ti_chip() == CHIP_OMAP_4) {
533 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
534 sc->disable_highspeed = true;
535 } else if (ti_chip() == CHIP_AM335X)
536 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
538 panic("Unknown OMAP device\n");
541 * The standard SDHCI registers are at a fixed offset (the same on all
542 * SoCs) beyond the MMCHS registers.
544 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET;
546 /* Resource setup. */
548 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
551 device_printf(dev, "cannot allocate memory window\n");
557 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
560 device_printf(dev, "cannot allocate interrupt\n");
565 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
566 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) {
567 device_printf(dev, "cannot setup interrupt handler\n");
572 /* Initialise the MMCHS hardware. */
573 ti_sdhci_hw_init(dev);
576 * The capabilities register can only express base clock frequencies in
577 * the range of 0-63MHz for a v2.0 controller. Since our clock runs
578 * faster than that, the hardware sets the frequency to zero in the
579 * register. When the register contains zero, the sdhci driver expects
580 * slot.max_clk to already have the right value in it.
582 sc->slot.max_clk = sc->baseclk_hz;
585 * The MMCHS timeout counter is based on the output sdclock. Tell the
586 * sdhci driver to recalculate the timeout clock whenever the output
587 * sdclock frequency changes.
589 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
592 * The MMCHS hardware shifts the 136-bit response data (in violation of
593 * the spec), so tell the sdhci driver not to do the same in software.
595 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE;
598 * Reset bits are broken, have to wait to see the bits asserted
599 * before waiting to see them de-asserted.
601 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED;
604 * The controller waits for busy responses.
606 sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY;
609 * DMA is not really broken, I just haven't implemented it yet.
611 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
614 * Set up the hardware and go. Note that this sets many of the
615 * slot.host.* fields, so we have to do this before overriding any of
616 * those values based on fdt data, below.
618 sdhci_init_slot(dev, &sc->slot, 0);
621 * The SDHCI controller doesn't realize it, but we can support 8-bit
622 * even though we're not a v3.0 controller. If there's an fdt bus-width
623 * property, honor it.
625 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
626 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA |
630 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA;
633 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA;
638 device_printf(dev, "Bad bus-width value %u\n", prop);
644 * If the slot is flagged with the non-removable property, set our flag
645 * to always force the SDHCI_CARD_PRESENT bit on.
647 node = ofw_bus_get_node(dev);
648 if (OF_hasprop(node, "non-removable"))
649 sc->force_card_present = true;
651 bus_generic_probe(dev);
652 bus_generic_attach(dev);
654 sdhci_start_slot(&sc->slot);
660 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
662 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
664 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
670 ti_sdhci_probe(device_t dev)
673 if (!ofw_bus_status_okay(dev))
676 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
677 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)");
678 return (BUS_PROBE_DEFAULT);
684 static device_method_t ti_sdhci_methods[] = {
685 /* Device interface */
686 DEVMETHOD(device_probe, ti_sdhci_probe),
687 DEVMETHOD(device_attach, ti_sdhci_attach),
688 DEVMETHOD(device_detach, ti_sdhci_detach),
691 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
692 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
694 /* MMC bridge interface */
695 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios),
696 DEVMETHOD(mmcbr_request, sdhci_generic_request),
697 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro),
698 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
699 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
701 /* SDHCI registers accessors */
702 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1),
703 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2),
704 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4),
705 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4),
706 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1),
707 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2),
708 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4),
709 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4),
714 static devclass_t ti_sdhci_devclass;
716 static driver_t ti_sdhci_driver = {
719 sizeof(struct ti_sdhci_softc),
722 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL,
724 MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1);
725 MMC_DECLARE_BRIDGE(sdhci_ti);