sys/boot/fdt/dts/imx51x.dtsi

   1 /*
   2  * Copyright (c) 2012 The FreeBSD Foundation
   3  * All rights reserved.
   4  *
   5  * This software was developed by Semihalf under sponsorship from
   6  * the FreeBSD Foundation.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * Freescale i.MX515 Device Tree Source.
  30  *
  31  * $FreeBSD$
  32  */
  33
  34 / {
  35         #address-cells = <1>;
  36         #size-cells = <1>;
  37
  38         aliases {
  39                 soc = &SOC;
  40         };
  41
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "ARM,MCIMX515";
  50                         reg = <0x0>;
  51                         d-cache-line-size = <32>;
  52                         i-cache-line-size = <32>;
  53                         d-cache-size = <0x8000>;
  54                         i-cache-size = <0x8000>;
  55                         /* TODO: describe L2 cache also */
  56                         timebase-frequency = <0>;
  57                         bus-frequency = <0>;
  58                         clock-frequency = <0>;
  59                 };
  60         };
  61
  62         localbus@e0000000 {
  63                 compatible = "simple-bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66
  67                 /* This reflects CPU decode windows setup. */
  68                 ranges;
  69
  70                 tzic: tz-interrupt-controller@e0000000 {
  71                         compatible = "fsl,imx51-tzic", "fsl,tzic";
  72                         interrupt-controller;
  73                         #interrupt-cells = <1>;
  74                         reg = <0xe0000000 0x00004000>;
  75                 };
  76                 /*
  77                  * 60000000 60000FFF 4K Debug ROM
  78                  * 60001000 60001FFF 4K ETB
  79                  * 60002000 60002FFF 4K ETM
  80                  * 60003000 60003FFF 4K TPIU
  81                  * 60004000 60004FFF 4K CTI0
  82                  * 60005000 60005FFF 4K CTI1
  83                  * 60006000 60006FFF 4K CTI2
  84                  * 60007000 60007FFF 4K CTI3
  85                  * 60008000 60008FFF 4K Cortex Debug Unit
  86                  *
  87                  * E0000000 E0003FFF 0x4000 TZIC
  88                  */
  89         };
  90
  91         SOC: soc@70000000 {
  92                 compatible = "simple-bus";
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 interrupt-parent = <&tzic>;
  96                 ranges = <0x70000000 0x70000000 0x14000000>;
  97
  98                 aips@70000000 { /* AIPS1 */
  99                         compatible = "fsl,aips-bus", "simple-bus";
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         interrupt-parent = <&tzic>;
 103                         ranges;
 104
 105                         /* Required by many devices, so better to stay first */
 106                         /* 73FD4000 0x4000 CCM */
 107                         clock@73fd4000 {
 108                                 compatible = "fsl,imx51-ccm";
 109                         /* 83F80000 0x4000 DPLLIP1 */
 110                         /* 83F84000 0x4000 DPLLIP2 */
 111                         /* 83F88000 0x4000 DPLLIP3 */
 112                                 reg = <0x73fd4000 0x4000
 113                                         0x83F80000 0x4000
 114                                         0x83F84000 0x4000
 115                                         0x83F88000 0x4000>;
 116                                 interrupt-parent = <&tzic>;
 117                                 interrupts = <71 72>;
 118                                 status = "disabled";
 119                         };
 120
 121                         /*
 122                          * GPIO modules moved up - to have it attached for
 123                          * drivers which rely on GPIO
 124                          */
 125                         /* 73F84000 0x4000 GPIO1 */
 126                         gpio1: gpio@73f84000 {
 127                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 128                                 reg = <0x73f84000 0x4000>;
 129                                 interrupt-parent = <&tzic>;
 130                                 interrupts = <50 51 42 43 44 45 46 47 48 49>;
 131                                 /* TODO: use <> also */
 132                                 gpio-controller;
 133                                 #gpio-cells = <2>;
 134                                 interrupt-controller;
 135                                 #interrupt-cells = <1>;
 136                         };
 137
 138                         /* 73F88000 0x4000 GPIO2 */
 139                         gpio2: gpio@73f88000 {
 140                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 141                                 reg = <0x73f88000 0x4000>;
 142                                 interrupt-parent = <&tzic>;
 143                                 interrupts = <52 53>;
 144                                 gpio-controller;
 145                                 #gpio-cells = <2>;
 146                                 interrupt-controller;
 147                                 #interrupt-cells = <1>;
 148                         };
 149
 150                         /* 73F8C000 0x4000 GPIO3 */
 151                         gpio3: gpio@73f8c000 {
 152                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 153                                 reg = <0x73f8c000 0x4000>;
 154                                 interrupt-parent = <&tzic>;
 155                                 interrupts = <54 55>;
 156                                 gpio-controller;
 157                                 #gpio-cells = <2>;
 158                                 interrupt-controller;
 159                                 #interrupt-cells = <1>;
 160                         };
 161
 162                         /* 73F90000 0x4000 GPIO4 */
 163                         gpio4: gpio@73f90000 {
 164                                 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
 165                                 reg = <0x73f90000 0x4000>;
 166                                 interrupt-parent = <&tzic>;
 167                                 interrupts = <56 57>;
 168                                 gpio-controller;
 169                                 #gpio-cells = <2>;
 170                                 interrupt-controller;
 171                                 #interrupt-cells = <1>;
 172                         };
 173
 174                         spba@70000000 {
 175                                 compatible = "fsl,spba-bus", "simple-bus";
 176                                 #address-cells = <1>;
 177                                 #size-cells = <1>;
 178                                 interrupt-parent = <&tzic>;
 179                                 ranges;
 180
 181                                 /* 70004000 0x4000 ESDHC 1 */
 182                                 esdhc@70004000 {
 183                                         compatible = "fsl,imx51-esdhc";
 184                                         reg = <0x70004000 0x4000>;
 185                                         interrupt-parent = <&tzic>; interrupts = <1>;
 186                                         status = "disabled";
 187                                 };
 188
 189                                 /* 70008000 0x4000 ESDHC 2 */
 190                                 esdhc@70008000 {
 191                                         compatible = "fsl,imx51-esdhc";
 192                                         reg = <0x70008000 0x4000>;
 193                                         interrupt-parent = <&tzic>; interrupts = <2>;
 194                                         status = "disabled";
 195                                 };
 196
 197                                 /* 7000C000 0x4000 UART 3 */
 198                                 uart3: serial@7000c000 {
 199                                         compatible = "fsl,imx51-uart", "fsl,imx-uart";
 200                                         reg = <0x7000c000 0x4000>;
 201                                         interrupt-parent = <&tzic>; interrupts = <33>;
 202                                         status = "disabled";
 203                                 };
 204
 205                                 /* 70010000 0x4000 eCSPI1 */
 206                                 ecspi@70010000 {
 207                                         #address-cells = <1>;
 208                                         #size-cells = <0>;
 209                                         compatible = "fsl,imx51-ecspi";
 210                                         reg = <0x70010000 0x4000>;
 211                                         interrupt-parent = <&tzic>; interrupts = <36>;
 212                                         status = "disabled";
 213                                 };
 214
 215                                 /* 70014000 0x4000 SSI2 irq30 */
 216                                 SSI2: ssi@70014000 {
 217                                         compatible = "fsl,imx51-ssi";
 218                                         reg = <0x70014000 0x4000>;
 219                                         interrupt-parent = <&tzic>; interrupts = <30>;
 220                                         status = "disabled";
 221                                 };
 222
 223                                 /* 70020000 0x4000 ESDHC 3 */
 224                                 esdhc@70020000 {
 225                                         compatible = "fsl,imx51-esdhc";
 226                                         reg = <0x70020000 0x4000>;
 227                                         interrupt-parent = <&tzic>; interrupts = <3>;
 228                                         status = "disabled";
 229                                 };
 230
 231                                 /* 70024000 0x4000 ESDHC 4 */
 232                                 esdhc@70024000 {
 233                                         compatible = "fsl,imx51-esdhc";
 234                                         reg = <0x70024000 0x4000>;
 235                                         interrupt-parent = <&tzic>; interrupts = <4>;
 236                                         status = "disabled";
 237                                 };
 238
 239                                 /* 70028000 0x4000 SPDIF */
 240                                     /* 91 SPDIF */
 241
 242                                 /* 70030000 0x4000 PATA (PORT UDMA) irq70 */
 243
 244                                 /* 70034000 0x4000 SLM */
 245                                 /* 70038000 0x4000 HSI2C */ /* 64 HS-I2C */
 246                                 /* 7003C000 0x4000 SPBA */
 247                         };
 248
 249                         /* 73F80000 0x4000 USBOH3 */
 250                         /* irq14 USBOH3 USB Host 1 */
 251                         /* irq16 USBOH3 USB Host 2 */
 252                         /* irq17 USBOH3 USB Host 3 */
 253                         /* irq18 USBOH3 USB OTG */
 254                         usb1: usb@73F80000 {
 255                                 compatible = "fsl,usb-4core";
 256                                 reg = <0x73f80000 0x4000>;
 257                                 interrupt-parent = <&tzic>;
 258                                 interrupts = <18 14 16 17>;
 259                         };
 260
 261                         /* 73F98000 0x4000 WDOG1 */
 262                         wdog@73f98000 {
 263                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 264                                 reg = <0x73f98000 0x4000>;
 265                                 interrupt-parent = <&tzic>; interrupts = <58>;
 266                                 status = "disabled";
 267                         };
 268
 269                         /* 73F9C000 0x4000 WDOG2 (TZ) */
 270                         wdog@73f9c000 {
 271                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 272                                 reg = <0x73f9c000 0x4000>;
 273                                 interrupt-parent = <&tzic>; interrupts = <59>;
 274                                 status = "disabled";
 275                         };
 276
 277                         /* 73F94000 0x4000 KPP */
 278                         keyboard@73f94000 {
 279                                 compatible = "fsl,imx51-kpp";
 280                                 reg = <0x73f94000 0x4000>;
 281                                 interrupt-parent = <&tzic>; interrupts = <60>;
 282                                 status = "disabled";
 283                         };
 284
 285                         /* 73FA0000 0x4000 GPT */
 286                         timer@73fa0000 {
 287                                 compatible = "fsl,imx51-gpt";
 288                                 reg = <0x73fa0000 0x4000>;
 289                                 interrupt-parent = <&tzic>; interrupts = <39>;
 290                                 status = "disabled";
 291                         };
 292
 293                         /* 73FA4000 0x4000 SRTC */
 294
 295                         rtc@73fa4000 {
 296                                 compatible = "fsl,imx51-srtc";
 297                                 reg = <0x73fa4000 0x4000>;
 298                                 interrupt-parent = <&tzic>; interrupts = <24 25>;
 299                                 status = "disabled";
 300                         };
 301
 302                         /* 73FA8000 0x4000 IOMUXC */
 303                         iomux@73fa8000 {
 304                                 compatible = "fsl,imx51-iomux";
 305                                 reg = <0x73fa8000 0x4000>;
 306                                 interrupt-parent = <&tzic>; interrupts = <7>;
 307                         };
 308
 309                         /* 73FAC000 0x4000 EPIT1 */
 310                         epit1: timer@73fac000 {
 311                                 compatible = "fsl,imx51-epit";
 312                                 reg = <0x73fac000 0x4000>;
 313                                 interrupt-parent = <&tzic>; interrupts = <40>;
 314                                 status = "disabled";
 315                         };
 316
 317                         /* 73FB0000 0x4000 EPIT2 */
 318                         epit2: timer@73fb0000 {
 319                                 compatible = "fsl,imx51-epit";
 320                                 reg = <0x73fb0000 0x4000>;
 321                                 interrupt-parent = <&tzic>; interrupts = <41>;
 322                                 status = "disabled";
 323                         };
 324
 325                         /* 73FB4000 0x4000 PWM1 */
 326                         pwm@73fb4000 {
 327                                 compatible = "fsl,imx51-pwm";
 328                                 reg = <0x73fb4000 0x4000>;
 329                                 interrupt-parent = <&tzic>; interrupts = <61>;
 330                                 status = "disabled";
 331                         };
 332
 333                         /* 73FB8000 0x4000 PWM2 */
 334                         pwm@73fb8000 {
 335                                 compatible = "fsl,imx51-pwm";
 336                                 reg = <0x73fb8000 0x4000>;
 337                                 interrupt-parent = <&tzic>; interrupts = <94>;
 338                                 status = "disabled";
 339                         };
 340
 341                         /* 73FBC000 0x4000 UART 1 */
 342                         uart1: serial@73fbc000 {
 343                                 compatible = "fsl,imx51-uart", "fsl,imx-uart";
 344                                 reg = <0x73fbc000 0x4000>;
 345                                 interrupt-parent = <&tzic>; interrupts = <31>;
 346                                 status = "disabled";
 347                         };
 348
 349                         /* 73FC0000 0x4000 UART 2 */
 350                         uart2: serial@73fc0000 {
 351                                 compatible = "fsl,imx51-uart", "fsl,imx-uart";
 352                                 reg = <0x73fc0000 0x4000>;
 353                                 interrupt-parent = <&tzic>; interrupts = <32>;
 354                                 status = "disabled";
 355                         };
 356
 357                         /* 73FC4000 0x4000 USBOH3 */
 358                         /* NOTYET
 359                         usb@73fc4000 {
 360                                 compatible = "fsl,imx51-otg";
 361                                 reg = <0x73fc4000 0x4000>;
 362                                 interrupt-parent = <&tzic>; interrupts = <>;
 363                                 status = "disabled";
 364                         };
 365                         */
 366                         /* 73FD0000 0x4000 SRC */
 367                         reset@73fd0000 {
 368                                 compatible = "fsl,imx51-src";
 369                                 reg = <0x73fd0000 0x4000>;
 370                                 interrupt-parent = <&tzic>; interrupts = <75>;
 371                                 status = "disabled";
 372                         };
 373                         /* 73FD8000 0x4000 GPC */
 374                         power@73fd8000 {
 375                                 compatible = "fsl,imx51-gpc";
 376                                 reg = <0x73fd8000 0x4000>;
 377                                 interrupt-parent = <&tzic>; interrupts = <73 74>;
 378                                 status = "disabled";
 379                         };
 380
 381                 };
 382
 383                 aips@80000000 { /* AIPS2 */
 384                         compatible = "fsl,aips-bus", "simple-bus";
 385                         #address-cells = <1>;
 386                         #size-cells = <1>;
 387                         interrupt-parent = <&tzic>;
 388                         ranges;
 389
 390                         /* 83F94000 0x4000 AHBMAX */
 391                         /* 83F98000 0x4000 IIM */
 392                             /*
 393                              * 69 IIM Interrupt request to the processor.
 394                              * Indicates to the processor that program or
 395                              * explicit.
 396                              */
 397                         /* 83F9C000 0x4000 CSU */
 398                             /*
 399                              * 27 CSU Interrupt Request 1. Indicates to the
 400                              * processor that one or more alarm inputs were.
 401                              */
 402
 403                         /* 83FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
 404                         /* irq76 Neon Monitor Interrupt */
 405                         /* irq77 Performance Unit Interrupt */
 406                         /* irq78 CTI IRQ */
 407                         /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */
 408                         /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */
 409                         /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */
 410                         /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */
 411
 412                         /* 83FA4000 0x4000 OWIRE irq88 */
 413                         /* 83FA8000 0x4000 FIRI irq93 */
 414                         /* 83FAC000 0x4000 eCSPI2 */
 415                         ecspi@83fac000 {
 416                                 #address-cells = <1>;
 417                                 #size-cells = <0>;
 418                                 compatible = "fsl,imx51-ecspi";
 419                                 reg = <0x83fac000 0x4000>;
 420                                 interrupt-parent = <&tzic>; interrupts = <37>;
 421                                 status = "disabled";
 422                         };
 423
 424                         /* 83FB0000 0x4000 SDMA */
 425                         sdma@83fb0000 {
 426                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 427                                 reg = <0x83fb0000 0x4000>;
 428                                 interrupt-parent = <&tzic>; interrupts = <6>;
 429                         };
 430
 431                         /* 83FB4000 0x4000 SCC */
 432                         /* 21 SCC Security Monitor High Priority Interrupt. */
 433                         /* 22 SCC Secure (TrustZone) Interrupt. */
 434                         /* 23 SCC Regular (Non-Secure) Interrupt. */
 435
 436                         /* 83FB8000 0x4000 ROMCP */
 437                         /* 83FBC000 0x4000 RTIC */
 438                         /*
 439                          * 26 RTIC RTIC (Trust Zone) Interrupt Request.
 440                          * Indicates that the RTIC has completed hashing the
 441                          */
 442
 443                         /* 83FC0000 0x4000 CSPI */
 444                         cspi@83fc0000 {
 445                                 #address-cells = <1>;
 446                                 #size-cells = <0>;
 447                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 448                                 reg = <0x83fc0000 0x4000>;
 449                                 interrupt-parent = <&tzic>; interrupts = <38>;
 450                                 status = "disabled";
 451                         };
 452
 453                         /* 83FC4000 0x4000 I2C2 */
 454                         i2c@83fc4000 {
 455                                 #address-cells = <1>;
 456                                 #size-cells = <0>;
 457                                 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
 458                                 reg = <0x83fc4000 0x4000>;
 459                                 interrupt-parent = <&tzic>; interrupts = <63>;
 460                                 status = "disabled";
 461                         };
 462
 463                         /* 83FC8000 0x4000 I2C1 */
 464                         i2c@83fc8000 {
 465                                 #address-cells = <1>;
 466                                 #size-cells = <0>;
 467                                 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
 468                                 reg = <0x83fc8000 0x4000>;
 469                                 interrupt-parent = <&tzic>; interrupts = <62>;
 470                                 status = "disabled";
 471                         };
 472
 473                         /* 83FCC000 0x4000 SSI1 */
 474                         /* 29 SSI1 SSI-1 Interrupt Request */
 475                         SSI1: ssi@83fcc000 {
 476                                 compatible = "fsl,imx51-ssi";
 477                                 reg = <0x83fcc000 0x4000>;
 478                                 interrupt-parent = <&tzic>; interrupts = <29>;
 479                                 status = "disabled";
 480                         };
 481
 482                         /* 83FD0000 0x4000 AUDMUX */
 483                         audmux@83fd4000 {
 484                                 compatible = "fsl,imx51-audmux";
 485                                 reg = <0x83fd4000 0x4000>;
 486                                 status = "disabled";
 487                         };
 488
 489                         /* 83FD8000 0x4000 EMI1 */
 490                         /* 8 EMI (NFC) */
 491                         /* 15 EMI */
 492                         /* 97 EMI Boot sequence completed interrupt */
 493                         /*
 494                          * 101 EMI Indicates all pages have been transferred
 495                          * to NFC during an auto program operation.
 496                          */
 497
 498                         /* 83FE0000 0x4000 PATA (PORT PIO) */
 499                         /* 70 PATA Parallel ATA host controller interrupt */
 500                         ide@83fe0000 {
 501                                 compatible = "fsl,imx51-ata";
 502                                 reg = <0x83fe0000 0x4000>;
 503                                 interrupt-parent = <&tzic>;
 504                                 interrupts = <70>;
 505                                 status = "disabled";
 506                         };
 507
 508                         /* 83FE4000 0x4000 SIM */
 509                         /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */
 510                         /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
 511
 512                         /* 83FE8000 0x4000 SSI3 */
 513                         /* 96 SSI3 SSI-3 Interrupt Request */
 514                         SSI3: ssi@83fe8000 {
 515                                 compatible = "fsl,imx51-ssi";
 516                                 reg = <0x83fe8000 0x4000>;
 517                                 interrupt-parent = <&tzic>; interrupts = <96>;
 518                                 status = "disabled";
 519                         };
 520
 521                         /* 83FEC000 0x4000 FEC */
 522                         ethernet@83fec000 {
 523                                 compatible = "fsl,imx51-fec";
 524                                 reg = <0x83fec000 0x4000>;
 525                                 interrupt-parent = <&tzic>; interrupts = <87>;
 526                                 status = "disabled";
 527                         };
 528
 529                         /* 83FF0000 0x4000 TVE */
 530                         /* 92 TVE */
 531                         /* 83FF4000 0x4000 VPU */
 532                         /* 9 VPU */
 533                         /* 100 VPU Idle interrupt from VPU */
 534
 535                         /* 83FF8000 0x4000 SAHARA Lite */
 536                         /* 19 SAHARA SAHARA host 0 (TrustZone) Intr Lite */
 537                         /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr Lite */
 538                 };
 539         };
 540
 541         localbus@5e000000 {
 542                 compatible = "simple-bus";
 543                 #address-cells = <1>;
 544                 #size-cells = <1>;
 545
 546                 ranges;
 547
 548                 vga: ipu3@5e000000 {
 549                         compatible = "fsl,ipu3";
 550                         reg = <
 551                                 0x5e000000 0x08000      /* CM */
 552                                 0x5e008000 0x08000      /* IDMAC */
 553                                 0x5e018000 0x08000      /* DP */
 554                                 0x5e020000 0x08000      /* IC */
 555                                 0x5e028000 0x08000      /* IRT */
 556                                 0x5e030000 0x08000      /* CSI0 */
 557                                 0x5e038000 0x08000      /* CSI1 */
 558                                 0x5e040000 0x08000      /* DI0 */
 559                                 0x5e048000 0x08000      /* DI1 */
 560                                 0x5e050000 0x08000      /* SMFC */
 561                                 0x5e058000 0x08000      /* DC */
 562                                 0x5e060000 0x08000      /* DMFC */
 563                                 0x5e068000 0x08000      /* VDI */
 564                                 0x5f000000 0x20000      /* CPMEM */
 565                                 0x5f020000 0x20000      /* LUT */
 566                                 0x5f040000 0x20000      /* SRM */
 567                                 0x5f060000 0x20000      /* TPM */
 568                                 0x5f080000 0x20000      /* DCTMPL */
 569                         >;
 570                         interrupt-parent = <&tzic>;
 571                         interrupts = <
 572                                 10      /* IPUEX Error */
 573                                 11      /* IPUEX Sync */
 574                         >;
 575                         status = "disabled";
 576                 };
 577         };
 578 };
 579
 580 /*
 581
 582 TODO: Not mapped interrupts
 583
 584 5       DAP
 585 84      GPU2D (OpenVG) general interrupt
 586 85      GPU2D (OpenVG) busy signal (for S/W power gating feasibility)
 587 12      GPU3D
 588 102     GPU3D Idle interrupt from GPU3D (for S/W power gating)
 589 90      SJC
 590 */