2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #define ATA_LEGACY_SUPPORT /* Enable obsolete features that break
31 * some modern devices */
34 /* ATA register defines */
35 #define ATA_DATA 0 /* (RW) data */
37 #define ATA_FEATURE 1 /* (W) feature */
38 #define ATA_F_DMA 0x01 /* enable DMA */
39 #define ATA_F_OVL 0x02 /* enable overlap */
41 #define ATA_COUNT 2 /* (W) sector count */
43 #define ATA_SECTOR 3 /* (RW) sector # */
44 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
45 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
46 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
47 #define ATA_D_LBA 0x40 /* use LBA addressing */
48 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
50 #define ATA_COMMAND 7 /* (W) command */
52 #define ATA_ERROR 8 /* (R) error */
53 #define ATA_E_ILI 0x01 /* illegal length */
54 #define ATA_E_NM 0x02 /* no media */
55 #define ATA_E_ABORT 0x04 /* command aborted */
56 #define ATA_E_MCR 0x08 /* media change request */
57 #define ATA_E_IDNF 0x10 /* ID not found */
58 #define ATA_E_MC 0x20 /* media changed */
59 #define ATA_E_UNC 0x40 /* uncorrectable data */
60 #define ATA_E_ICRC 0x80 /* UDMA crc error */
61 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
63 #define ATA_IREASON 9 /* (R) interrupt reason */
64 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
65 #define ATA_I_IN 0x02 /* read (1) | write (0) */
66 #define ATA_I_RELEASE 0x04 /* released bus (1) */
67 #define ATA_I_TAGMASK 0xf8 /* tag mask */
69 #define ATA_STATUS 10 /* (R) status */
70 #define ATA_ALTSTAT 11 /* (R) alternate status */
71 #define ATA_S_ERROR 0x01 /* error */
72 #define ATA_S_INDEX 0x02 /* index */
73 #define ATA_S_CORR 0x04 /* data corrected */
74 #define ATA_S_DRQ 0x08 /* data request */
75 #define ATA_S_DSC 0x10 /* drive seek completed */
76 #define ATA_S_SERVICE 0x10 /* drive needs service */
77 #define ATA_S_DWF 0x20 /* drive write fault */
78 #define ATA_S_DMA 0x20 /* DMA ready */
79 #define ATA_S_READY 0x40 /* drive ready */
80 #define ATA_S_BUSY 0x80 /* busy */
82 #define ATA_CONTROL 12 /* (W) control */
84 #define ATA_CTLOFFSET 0x206 /* control register offset */
85 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
86 #define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */
87 #define ATA_A_IDS 0x02 /* disable interrupts */
88 #define ATA_A_RESET 0x04 /* RESET controller */
89 #ifdef ATA_LEGACY_SUPPORT
90 #define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */
92 #define ATA_A_4BIT 0x00
94 #define ATA_A_HOB 0x80 /* High Order Byte enable */
96 /* SATA register defines */
97 #define ATA_SSTATUS 13
98 #define ATA_SS_DET_MASK 0x0000000f
99 #define ATA_SS_DET_NO_DEVICE 0x00000000
100 #define ATA_SS_DET_DEV_PRESENT 0x00000001
101 #define ATA_SS_DET_PHY_ONLINE 0x00000003
102 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
104 #define ATA_SS_SPD_MASK 0x000000f0
105 #define ATA_SS_SPD_NO_SPEED 0x00000000
106 #define ATA_SS_SPD_GEN1 0x00000010
107 #define ATA_SS_SPD_GEN2 0x00000020
108 #define ATA_SS_SPD_GEN3 0x00000030
110 #define ATA_SS_IPM_MASK 0x00000f00
111 #define ATA_SS_IPM_NO_DEVICE 0x00000000
112 #define ATA_SS_IPM_ACTIVE 0x00000100
113 #define ATA_SS_IPM_PARTIAL 0x00000200
114 #define ATA_SS_IPM_SLUMBER 0x00000600
116 #define ATA_SERROR 14
117 #define ATA_SE_DATA_CORRECTED 0x00000001
118 #define ATA_SE_COMM_CORRECTED 0x00000002
119 #define ATA_SE_DATA_ERR 0x00000100
120 #define ATA_SE_COMM_ERR 0x00000200
121 #define ATA_SE_PROT_ERR 0x00000400
122 #define ATA_SE_HOST_ERR 0x00000800
123 #define ATA_SE_PHY_CHANGED 0x00010000
124 #define ATA_SE_PHY_IERROR 0x00020000
125 #define ATA_SE_COMM_WAKE 0x00040000
126 #define ATA_SE_DECODE_ERR 0x00080000
127 #define ATA_SE_PARITY_ERR 0x00100000
128 #define ATA_SE_CRC_ERR 0x00200000
129 #define ATA_SE_HANDSHAKE_ERR 0x00400000
130 #define ATA_SE_LINKSEQ_ERR 0x00800000
131 #define ATA_SE_TRANSPORT_ERR 0x01000000
132 #define ATA_SE_UNKNOWN_FIS 0x02000000
134 #define ATA_SCONTROL 15
135 #define ATA_SC_DET_MASK 0x0000000f
136 #define ATA_SC_DET_IDLE 0x00000000
137 #define ATA_SC_DET_RESET 0x00000001
138 #define ATA_SC_DET_DISABLE 0x00000004
140 #define ATA_SC_SPD_MASK 0x000000f0
141 #define ATA_SC_SPD_NO_SPEED 0x00000000
142 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
143 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
144 #define ATA_SC_SPD_SPEED_GEN3 0x00000030
146 #define ATA_SC_IPM_MASK 0x00000f00
147 #define ATA_SC_IPM_NONE 0x00000000
148 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
149 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
151 #define ATA_SACTIVE 16
153 /* DMA register defines */
154 #define ATA_DMA_ENTRIES 256
155 #define ATA_DMA_EOT 0x80000000
157 #define ATA_BMCMD_PORT 17
158 #define ATA_BMCMD_START_STOP 0x01
159 #define ATA_BMCMD_WRITE_READ 0x08
161 #define ATA_BMDEVSPEC_0 18
162 #define ATA_BMSTAT_PORT 19
163 #define ATA_BMSTAT_ACTIVE 0x01
164 #define ATA_BMSTAT_ERROR 0x02
165 #define ATA_BMSTAT_INTERRUPT 0x04
166 #define ATA_BMSTAT_MASK 0x07
167 #define ATA_BMSTAT_DMA_MASTER 0x20
168 #define ATA_BMSTAT_DMA_SLAVE 0x40
169 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
171 #define ATA_BMDEVSPEC_1 20
172 #define ATA_BMDTP_PORT 21
174 #define ATA_IDX_ADDR 22
175 #define ATA_IDX_DATA 23
176 #define ATA_MAX_RES 24
179 #define ATA_PRIMARY 0x1f0
180 #define ATA_SECONDARY 0x170
181 #define ATA_PC98_BANK 0x432
182 #define ATA_IOSIZE 0x08
183 #define ATA_PC98_IOSIZE 0x10
184 #define ATA_CTLIOSIZE 0x01
185 #define ATA_BMIOSIZE 0x08
186 #define ATA_PC98_BANKIOSIZE 0x01
187 #define ATA_IOADDR_RID 0
188 #define ATA_CTLADDR_RID 1
189 #define ATA_BMADDR_RID 0x20
190 #define ATA_PC98_CTLADDR_RID 8
191 #define ATA_PC98_BANKADDR_RID 9
192 #define ATA_IRQ_RID 0
193 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0)
194 #define ATA_CFA_MAGIC1 0x844A
195 #define ATA_CFA_MAGIC2 0x848A
196 #define ATA_CFA_MAGIC3 0x8400
197 #define ATAPI_MAGIC_LSB 0x14
198 #define ATAPI_MAGIC_MSB 0xeb
199 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
200 #define ATAPI_P_WRITE (ATA_S_DRQ)
201 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
202 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
203 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
204 #define ATAPI_P_ABORT 0
205 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
206 #define ATA_OP_CONTINUES 0
207 #define ATA_OP_FINISHED 1
208 #define ATA_MAX_28BIT_LBA 268435455UL
210 /* structure used for composite atomic operations */
211 #define MAX_COMPOSITES 32 /* u_int32_t bits */
212 struct ata_composite {
213 struct mtx lock; /* control lock */
214 u_int32_t rd_needed; /* needed read subdisks */
215 u_int32_t rd_done; /* done read subdisks */
216 u_int32_t wr_needed; /* needed write subdisks */
217 u_int32_t wr_depend; /* write depends on subdisks */
218 u_int32_t wr_done; /* done write subdisks */
219 struct ata_request *request[MAX_COMPOSITES];
220 u_int32_t residual; /* bytes still to transfer */
225 /* structure used to queue an ATA/ATAPI request */
227 device_t dev; /* device handle */
228 device_t parent; /* channel handle */
229 int unit; /* physical unit */
232 u_int8_t command; /* command reg */
233 u_int16_t feature; /* feature reg */
234 u_int16_t count; /* count reg */
235 u_int64_t lba; /* lba reg */
238 u_int8_t ccb[16]; /* ATAPI command block */
239 struct atapi_sense sense; /* ATAPI request sense data */
240 u_int8_t saved_cmd; /* ATAPI saved command */
243 u_int32_t bytecount; /* bytes to transfer */
244 u_int32_t transfersize; /* bytes pr transfer */
245 caddr_t data; /* pointer to data buf */
246 u_int32_t tag; /* HW tag of this request */
248 #define ATA_R_CONTROL 0x00000001
249 #define ATA_R_READ 0x00000002
250 #define ATA_R_WRITE 0x00000004
251 #define ATA_R_ATAPI 0x00000008
252 #define ATA_R_DMA 0x00000010
253 #define ATA_R_QUIET 0x00000020
254 #define ATA_R_TIMEOUT 0x00000040
255 #define ATA_R_48BIT 0x00000080
257 #define ATA_R_ORDERED 0x00000100
258 #define ATA_R_AT_HEAD 0x00000200
259 #define ATA_R_REQUEUE 0x00000400
260 #define ATA_R_THREAD 0x00000800
261 #define ATA_R_DIRECT 0x00001000
262 #define ATA_R_NEEDRESULT 0x00002000
263 #define ATA_R_DATA_IN_CCB 0x00004000
265 #define ATA_R_ATAPI16 0x00010000
266 #define ATA_R_ATAPI_INTR 0x00020000
268 #define ATA_R_DEBUG 0x10000000
269 #define ATA_R_DANGER1 0x20000000
270 #define ATA_R_DANGER2 0x40000000
272 struct ata_dmaslot *dma; /* DMA slot of this request */
273 u_int8_t status; /* ATA status */
274 u_int8_t error; /* ATA error */
275 u_int32_t donecount; /* bytes transferred */
276 int result; /* result error code */
277 void (*callback)(struct ata_request *request);
278 struct sema done; /* request done sema */
279 int retries; /* retry count */
280 int timeout; /* timeout for this cmd */
281 struct callout callout; /* callout management */
282 struct task task; /* task management */
283 struct bio *bio; /* bio for this request */
284 int this; /* this request ID */
285 struct ata_composite *composite; /* for composite atomic ops */
286 void *driver; /* driver specific */
287 TAILQ_ENTRY(ata_request) chain; /* list management */
291 /* define this for debugging request processing */
293 #define ATA_DEBUG_RQ(request, string) \
295 if (request->flags & ATA_R_DEBUG) \
296 device_printf(request->parent, "req=%p %s " string "\n", \
297 request, ata_cmd2str(request)); \
300 #define ATA_DEBUG_RQ(request, string)
304 /* structure describing an ATA/ATAPI device */
306 device_t dev; /* device handle */
307 int unit; /* physical unit */
308 #define ATA_MASTER 0x00
309 #define ATA_SLAVE 0x01
312 struct ata_params param; /* ata param structure */
313 int mode; /* current transfermode */
314 u_int32_t max_iosize; /* max IO size */
315 int spindown; /* idle spindown timeout */
316 struct callout spindown_timer;
319 #define ATA_D_USE_CHS 0x0001
320 #define ATA_D_MEDIA_CHANGED 0x0002
321 #define ATA_D_ENC_PRESENT 0x0004
324 /* structure for holding DMA Physical Region Descriptors (PRD) entries */
325 struct ata_dma_prdentry {
330 /* structure used by the setprd function */
331 struct ata_dmasetprd_args {
338 u_int8_t status; /* DMA status */
339 bus_dma_tag_t sg_tag; /* SG list DMA tag */
340 bus_dmamap_t sg_map; /* SG list DMA map */
341 void *sg; /* DMA transfer table */
342 bus_addr_t sg_bus; /* bus address of dmatab */
343 bus_dma_tag_t data_tag; /* data DMA tag */
344 bus_dmamap_t data_map; /* data DMA map */
347 /* structure holding DMA related information */
349 bus_dma_tag_t dmatag; /* parent DMA tag */
350 bus_dma_tag_t work_tag; /* workspace DMA tag */
351 bus_dmamap_t work_map; /* workspace DMA map */
352 u_int8_t *work; /* workspace */
353 bus_addr_t work_bus; /* bus address of dmatab */
355 #define ATA_DMA_SLOTS 1
356 int dma_slots; /* DMA slots allocated */
357 struct ata_dmaslot slot[ATA_DMA_SLOTS];
358 u_int32_t alignment; /* DMA SG list alignment */
359 u_int32_t boundary; /* DMA SG list boundary */
360 u_int32_t segsize; /* DMA SG list segment size */
361 u_int32_t max_iosize; /* DMA data max IO size */
362 u_int64_t max_address; /* highest DMA'able address */
364 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */
366 void (*alloc)(device_t dev);
367 void (*free)(device_t dev);
368 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
369 int (*load)(struct ata_request *request, void *addr, int *nsegs);
370 int (*unload)(struct ata_request *request);
371 int (*start)(struct ata_request *request);
372 int (*stop)(struct ata_request *request);
373 void (*reset)(device_t dev);
376 /* structure holding lowlevel functions */
377 struct ata_lowlevel {
378 u_int32_t (*softreset)(device_t dev, int pmport);
379 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result);
380 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value);
381 int (*status)(device_t dev);
382 int (*begin_transaction)(struct ata_request *request);
383 int (*end_transaction)(struct ata_request *request);
384 int (*command)(struct ata_request *request);
385 void (*tf_read)(struct ata_request *request);
386 void (*tf_write)(struct ata_request *request);
389 /* structure holding resources for an ATA channel */
390 struct ata_resource {
391 struct resource *res;
395 struct ata_cam_device {
403 /* structure describing an ATA channel */
405 device_t dev; /* device handle */
406 int unit; /* physical channel */
407 int attached; /* channel is attached */
408 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
409 struct resource *r_irq; /* interrupt of this channel */
410 void *ih; /* interrupt handle */
411 struct ata_lowlevel hw; /* lowlevel HW functions */
412 struct ata_dma dma; /* DMA data / functions */
413 int flags; /* channel flags */
414 #define ATA_NO_SLAVE 0x01
415 #define ATA_USE_16BIT 0x02
416 #define ATA_ATAPI_DMA_RO 0x04
417 #define ATA_NO_48BIT_DMA 0x08
418 #define ATA_ALWAYS_DMASTAT 0x10
419 #define ATA_CHECKS_CABLE 0x20
420 #define ATA_NO_ATAPI_DMA 0x40
421 #define ATA_SATA 0x80
422 #define ATA_DMA_BEFORE_CMD 0x100
423 #define ATA_KNOWN_PRESENCE 0x200
424 #define ATA_STATUS_IS_LONG 0x400
425 #define ATA_PERIODIC_POLL 0x800
427 int pm_level; /* power management level */
428 int devices; /* what is present */
429 #define ATA_ATA_MASTER 0x00000001
430 #define ATA_ATA_SLAVE 0x00000002
431 #define ATA_PORTMULTIPLIER 0x00008000
432 #define ATA_ATAPI_MASTER 0x00010000
433 #define ATA_ATAPI_SLAVE 0x00020000
435 struct mtx state_mtx; /* state lock */
436 int state; /* ATA channel state */
437 #define ATA_IDLE 0x0000
438 #define ATA_ACTIVE 0x0001
439 #define ATA_STALL_QUEUE 0x0002
441 struct ata_request *running; /* currently running request */
442 struct task conntask; /* PHY events handling task */
444 struct cam_path *path;
445 struct ata_cam_device user[16]; /* User-specified settings */
446 struct ata_cam_device curr[16]; /* Current settings */
447 int requestsense; /* CCB waiting for SENSE. */
448 struct callout poll_callout; /* Periodic status poll. */
449 struct ata_request request;
452 /* disk bay/enclosure related */
453 #define ATA_LED_OFF 0x00
454 #define ATA_LED_RED 0x01
455 #define ATA_LED_GREEN 0x02
456 #define ATA_LED_ORANGE 0x03
457 #define ATA_LED_MASK 0x03
460 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data);
461 extern struct intr_config_hook *ata_delayed_attach;
462 extern devclass_t ata_devclass;
464 extern int ata_setmax;
465 extern int ata_dma_check_80pin;
467 /* public prototypes */
469 int ata_probe(device_t dev);
470 int ata_attach(device_t dev);
471 int ata_detach(device_t dev);
472 int ata_reinit(device_t dev);
473 int ata_suspend(device_t dev);
474 int ata_resume(device_t dev);
475 void ata_interrupt(void *data);
476 int ata_getparam(struct ata_device *atadev, int init);
477 void ata_default_registers(device_t dev);
478 void ata_udelay(int interval);
479 const char *ata_cmd2str(struct ata_request *request);
480 const char *ata_mode2str(int mode);
481 void ata_setmode(device_t dev);
482 void ata_print_cable(device_t dev, u_int8_t *who);
483 int ata_atapi(device_t dev, int target);
484 void ata_timeout(struct ata_request *);
486 /* ata-lowlevel.c: */
487 void ata_generic_hw(device_t dev);
488 int ata_begin_transaction(struct ata_request *);
489 int ata_end_transaction(struct ata_request *);
490 void ata_generic_reset(device_t dev);
491 int ata_generic_command(struct ata_request *request);
494 void ata_dmainit(device_t);
495 void ata_dmafini(device_t dev);
498 void ata_sata_phy_check_events(device_t dev, int port);
499 int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val);
500 int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val);
501 int ata_sata_phy_reset(device_t dev, int port, int quick);
502 int ata_sata_setmode(device_t dev, int target, int mode);
503 int ata_sata_getrev(device_t dev, int target);
504 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
505 void ata_pm_identify(device_t dev);
507 MALLOC_DECLARE(M_ATA);
509 /* misc newbus defines */
510 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
512 /* macros to hide busspace uglyness */
513 #define ATA_INB(res, offset) \
514 bus_read_1((res), (offset))
516 #define ATA_INW(res, offset) \
517 bus_read_2((res), (offset))
518 #define ATA_INW_STRM(res, offset) \
519 bus_read_stream_2((res), (offset))
520 #define ATA_INL(res, offset) \
521 bus_read_4((res), (offset))
522 #define ATA_INSW(res, offset, addr, count) \
523 bus_read_multi_2((res), (offset), (addr), (count))
524 #define ATA_INSW_STRM(res, offset, addr, count) \
525 bus_read_multi_stream_2((res), (offset), (addr), (count))
526 #define ATA_INSL(res, offset, addr, count) \
527 bus_read_multi_4((res), (offset), (addr), (count))
528 #define ATA_INSL_STRM(res, offset, addr, count) \
529 bus_read_multi_stream_4((res), (offset), (addr), (count))
530 #define ATA_OUTB(res, offset, value) \
531 bus_write_1((res), (offset), (value))
532 #define ATA_OUTW(res, offset, value) \
533 bus_write_2((res), (offset), (value))
534 #define ATA_OUTW_STRM(res, offset, value) \
535 bus_write_stream_2((res), (offset), (value))
536 #define ATA_OUTL(res, offset, value) \
537 bus_write_4((res), (offset), (value))
538 #define ATA_OUTSW(res, offset, addr, count) \
539 bus_write_multi_2((res), (offset), (addr), (count))
540 #define ATA_OUTSW_STRM(res, offset, addr, count) \
541 bus_write_multi_stream_2((res), (offset), (addr), (count))
542 #define ATA_OUTSL(res, offset, addr, count) \
543 bus_write_multi_4((res), (offset), (addr), (count))
544 #define ATA_OUTSL_STRM(res, offset, addr, count) \
545 bus_write_multi_stream_4((res), (offset), (addr), (count))
547 #define ATA_IDX_INB(ch, idx) \
548 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
550 #define ATA_IDX_INW(ch, idx) \
551 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
553 #define ATA_IDX_INW_STRM(ch, idx) \
554 ATA_INW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset)
556 #define ATA_IDX_INL(ch, idx) \
557 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
559 #define ATA_IDX_INSW(ch, idx, addr, count) \
560 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
562 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
563 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
565 #define ATA_IDX_INSL(ch, idx, addr, count) \
566 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
568 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
569 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
571 #define ATA_IDX_OUTB(ch, idx, value) \
572 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
574 #define ATA_IDX_OUTW(ch, idx, value) \
575 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
577 #define ATA_IDX_OUTW_STRM(ch, idx, value) \
578 ATA_OUTW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, value)
580 #define ATA_IDX_OUTL(ch, idx, value) \
581 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
583 #define ATA_IDX_OUTSW(ch, idx, addr, count) \
584 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
586 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
587 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
589 #define ATA_IDX_OUTSL(ch, idx, addr, count) \
590 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
592 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
593 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)