sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
  42  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717C },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5725 },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5727 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5762 },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
 223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57762 },
 224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57764 },
 225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
 226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57766 },
 227         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57767 },
 228         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 229         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
 230         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57782 },
 231         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
 232         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57786 },
 233         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57787 },
 234         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 235         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 236         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
 237         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
 238
 239         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 240
 241         { TC_VENDORID,          TC_DEVICEID_3C996 },
 242
 243         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 244         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 245         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 246
 247         { 0, 0 }
 248 };
 249
 250 static const struct bge_vendor {
 251         uint16_t        v_id;
 252         const char      *v_name;
 253 } bge_vendors[] = {
 254         { ALTEON_VENDORID,      "Alteon" },
 255         { ALTIMA_VENDORID,      "Altima" },
 256         { APPLE_VENDORID,       "Apple" },
 257         { BCOM_VENDORID,        "Broadcom" },
 258         { SK_VENDORID,          "SysKonnect" },
 259         { TC_VENDORID,          "3Com" },
 260         { FJTSU_VENDORID,       "Fujitsu" },
 261
 262         { 0, NULL }
 263 };
 264
 265 static const struct bge_revision {
 266         uint32_t        br_chipid;
 267         const char      *br_name;
 268 } bge_revisions[] = {
 269         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 270         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 271         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 272         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 273         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 274         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 275         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 276         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 277         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 278         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 279         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 280         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 281         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 282         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 283         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 284         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 285         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 286         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 287         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 288         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 289         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 290         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 291         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 292         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 293         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 294         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 295         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 296         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 297         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 298         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 299         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 300         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 301         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 302         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 303         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 304         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 305         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 306         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 307         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 308         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 309         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 310         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 311         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 312         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
 313         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
 314         { BGE_CHIPID_BCM5717_C0,        "BCM5717 C0" },
 315         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
 316         { BGE_CHIPID_BCM5720_A0,        "BCM5720 A0" },
 317         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 318         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 319         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 320         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 321         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 322         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 323         { BGE_CHIPID_BCM5762_A0,        "BCM5762 A0" },
 324         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 325         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 326         /* 5754 and 5787 share the same ASIC ID */
 327         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 328         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 329         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 330         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 331         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 332         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
 333         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
 334         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 335         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 336
 337         { 0, NULL }
 338 };
 339
 340 /*
 341  * Some defaults for major revisions, so that newer steppings
 342  * that we don't know about have a shot at working.
 343  */
 344 static const struct bge_revision bge_majorrevs[] = {
 345         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 346         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 347         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 348         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 349         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 350         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 351         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 352         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 353         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 354         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 355         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 356         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 357         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 358         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 359         /* 5754 and 5787 share the same ASIC ID */
 360         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 361         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 362         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
 363         { BGE_ASICREV_BCM57766,         "unknown BCM57766" },
 364         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 365         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
 366         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
 367         { BGE_ASICREV_BCM5720,          "unknown BCM5720" },
 368         { BGE_ASICREV_BCM5762,          "unknown BCM5762" },
 369
 370         { 0, NULL }
 371 };
 372
 373 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 374 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 375 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 376 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 377 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 378 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 379 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
 380 #define BGE_IS_57765_PLUS(sc)           ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
 381
 382 static uint32_t bge_chipid(device_t);
 383 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
 384 static const struct bge_revision * bge_lookup_rev(uint32_t);
 385
 386 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 387
 388 static int bge_probe(device_t);
 389 static int bge_attach(device_t);
 390 static int bge_detach(device_t);
 391 static int bge_suspend(device_t);
 392 static int bge_resume(device_t);
 393 static void bge_release_resources(struct bge_softc *);
 394 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 395 static int bge_dma_alloc(struct bge_softc *);
 396 static void bge_dma_free(struct bge_softc *);
 397 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
 398     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
 399
 400 static void bge_devinfo(struct bge_softc *);
 401 static int bge_mbox_reorder(struct bge_softc *);
 402
 403 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 404 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 405 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 406 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 407 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 408
 409 static void bge_txeof(struct bge_softc *, uint16_t);
 410 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
 411 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 412
 413 static void bge_asf_driver_up (struct bge_softc *);
 414 static void bge_tick(void *);
 415 static void bge_stats_clear_regs(struct bge_softc *);
 416 static void bge_stats_update(struct bge_softc *);
 417 static void bge_stats_update_regs(struct bge_softc *);
 418 static struct mbuf *bge_check_short_dma(struct mbuf *);
 419 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 420     uint16_t *, uint16_t *);
 421 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 422
 423 static void bge_intr(void *);
 424 static int bge_msi_intr(void *);
 425 static void bge_intr_task(void *, int);
 426 static void bge_start_locked(struct ifnet *);
 427 static void bge_start(struct ifnet *);
 428 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 429 static void bge_init_locked(struct bge_softc *);
 430 static void bge_init(void *);
 431 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 432 static void bge_stop(struct bge_softc *);
 433 static void bge_watchdog(struct bge_softc *);
 434 static int bge_shutdown(device_t);
 435 static int bge_ifmedia_upd_locked(struct ifnet *);
 436 static int bge_ifmedia_upd(struct ifnet *);
 437 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 438
 439 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 440 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 441
 442 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 443 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 444
 445 static void bge_setpromisc(struct bge_softc *);
 446 static void bge_setmulti(struct bge_softc *);
 447 static void bge_setvlan(struct bge_softc *);
 448
 449 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 450 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 451 static int bge_newbuf_std(struct bge_softc *, int);
 452 static int bge_newbuf_jumbo(struct bge_softc *, int);
 453 static int bge_init_rx_ring_std(struct bge_softc *);
 454 static void bge_free_rx_ring_std(struct bge_softc *);
 455 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 456 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 457 static void bge_free_tx_ring(struct bge_softc *);
 458 static int bge_init_tx_ring(struct bge_softc *);
 459
 460 static int bge_chipinit(struct bge_softc *);
 461 static int bge_blockinit(struct bge_softc *);
 462 static uint32_t bge_dma_swap_options(struct bge_softc *);
 463
 464 static int bge_has_eaddr(struct bge_softc *);
 465 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 466 static void bge_writemem_ind(struct bge_softc *, int, int);
 467 static void bge_writembx(struct bge_softc *, int, int);
 468 #ifdef notdef
 469 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 470 #endif
 471 static void bge_writemem_direct(struct bge_softc *, int, int);
 472 static void bge_writereg_ind(struct bge_softc *, int, int);
 473
 474 static int bge_miibus_readreg(device_t, int, int);
 475 static int bge_miibus_writereg(device_t, int, int, int);
 476 static void bge_miibus_statchg(device_t);
 477 #ifdef DEVICE_POLLING
 478 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 479 #endif
 480
 481 #define BGE_RESET_SHUTDOWN      0
 482 #define BGE_RESET_START         1
 483 #define BGE_RESET_SUSPEND       2
 484 static void bge_sig_post_reset(struct bge_softc *, int);
 485 static void bge_sig_legacy(struct bge_softc *, int);
 486 static void bge_sig_pre_reset(struct bge_softc *, int);
 487 static void bge_stop_fw(struct bge_softc *);
 488 static int bge_reset(struct bge_softc *);
 489 static void bge_link_upd(struct bge_softc *);
 490
 491 static void bge_ape_lock_init(struct bge_softc *);
 492 static void bge_ape_read_fw_ver(struct bge_softc *);
 493 static int bge_ape_lock(struct bge_softc *, int);
 494 static void bge_ape_unlock(struct bge_softc *, int);
 495 static void bge_ape_send_event(struct bge_softc *, uint32_t);
 496 static void bge_ape_driver_state_change(struct bge_softc *, int);
 497
 498 /*
 499  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 500  * leak information to untrusted users.  It is also known to cause alignment
 501  * traps on certain architectures.
 502  */
 503 #ifdef BGE_REGISTER_DEBUG
 504 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 505 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 506 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
 507 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 508 #endif
 509 static void bge_add_sysctls(struct bge_softc *);
 510 static void bge_add_sysctl_stats_regs(struct bge_softc *,
 511     struct sysctl_ctx_list *, struct sysctl_oid_list *);
 512 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
 513     struct sysctl_oid_list *);
 514 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 515
 516 static device_method_t bge_methods[] = {
 517         /* Device interface */
 518         DEVMETHOD(device_probe,         bge_probe),
 519         DEVMETHOD(device_attach,        bge_attach),
 520         DEVMETHOD(device_detach,        bge_detach),
 521         DEVMETHOD(device_shutdown,      bge_shutdown),
 522         DEVMETHOD(device_suspend,       bge_suspend),
 523         DEVMETHOD(device_resume,        bge_resume),
 524
 525         /* MII interface */
 526         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 527         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 528         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 529
 530         DEVMETHOD_END
 531 };
 532
 533 static driver_t bge_driver = {
 534         "bge",
 535         bge_methods,
 536         sizeof(struct bge_softc)
 537 };
 538
 539 static devclass_t bge_devclass;
 540
 541 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 542 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 543
 544 static int bge_allow_asf = 1;
 545
 546 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 547
 548 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 549 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 550         "Allow ASF mode if available");
 551
 552 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 553 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 554 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 555 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 556 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 557
 558 static int
 559 bge_has_eaddr(struct bge_softc *sc)
 560 {
 561 #ifdef __sparc64__
 562         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 563         device_t dev;
 564         uint32_t subvendor;
 565
 566         dev = sc->bge_dev;
 567
 568         /*
 569          * The on-board BGEs found in sun4u machines aren't fitted with
 570          * an EEPROM which means that we have to obtain the MAC address
 571          * via OFW and that some tests will always fail.  We distinguish
 572          * such BGEs by the subvendor ID, which also has to be obtained
 573          * from OFW instead of the PCI configuration space as the latter
 574          * indicates Broadcom as the subvendor of the netboot interface.
 575          * For early Blade 1500 and 2500 we even have to check the OFW
 576          * device path as the subvendor ID always defaults to Broadcom
 577          * there.
 578          */
 579         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 580             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 581             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 582                 return (0);
 583         memset(buf, 0, sizeof(buf));
 584         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 585                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 586                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 587                         return (0);
 588                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 589                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 590                         return (0);
 591         }
 592 #endif
 593         return (1);
 594 }
 595
 596 static uint32_t
 597 bge_readmem_ind(struct bge_softc *sc, int off)
 598 {
 599         device_t dev;
 600         uint32_t val;
 601
 602         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 603             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 604                 return (0);
 605
 606         dev = sc->bge_dev;
 607
 608         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 609         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 610         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 611         return (val);
 612 }
 613
 614 static void
 615 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 616 {
 617         device_t dev;
 618
 619         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 620             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 621                 return;
 622
 623         dev = sc->bge_dev;
 624
 625         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 626         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 627         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 628 }
 629
 630 #ifdef notdef
 631 static uint32_t
 632 bge_readreg_ind(struct bge_softc *sc, int off)
 633 {
 634         device_t dev;
 635
 636         dev = sc->bge_dev;
 637
 638         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 639         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 640 }
 641 #endif
 642
 643 static void
 644 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 645 {
 646         device_t dev;
 647
 648         dev = sc->bge_dev;
 649
 650         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 651         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 652 }
 653
 654 static void
 655 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 656 {
 657         CSR_WRITE_4(sc, off, val);
 658 }
 659
 660 static void
 661 bge_writembx(struct bge_softc *sc, int off, int val)
 662 {
 663         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 664                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 665
 666         CSR_WRITE_4(sc, off, val);
 667         if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
 668                 CSR_READ_4(sc, off);
 669 }
 670
 671 /*
 672  * Clear all stale locks and select the lock for this driver instance.
 673  */
 674 static void
 675 bge_ape_lock_init(struct bge_softc *sc)
 676 {
 677         uint32_t bit, regbase;
 678         int i;
 679
 680         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 681                 regbase = BGE_APE_LOCK_GRANT;
 682         else
 683                 regbase = BGE_APE_PER_LOCK_GRANT;
 684
 685         /* Clear any stale locks. */
 686         for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
 687                 switch (i) {
 688                 case BGE_APE_LOCK_PHY0:
 689                 case BGE_APE_LOCK_PHY1:
 690                 case BGE_APE_LOCK_PHY2:
 691                 case BGE_APE_LOCK_PHY3:
 692                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 693                         break;
 694                 default:
 695                         if (sc->bge_func_addr == 0)
 696                                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 697                         else
 698                                 bit = (1 << sc->bge_func_addr);
 699                 }
 700                 APE_WRITE_4(sc, regbase + 4 * i, bit);
 701         }
 702
 703         /* Select the PHY lock based on the device's function number. */
 704         switch (sc->bge_func_addr) {
 705         case 0:
 706                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
 707                 break;
 708         case 1:
 709                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
 710                 break;
 711         case 2:
 712                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
 713                 break;
 714         case 3:
 715                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
 716                 break;
 717         default:
 718                 device_printf(sc->bge_dev,
 719                     "PHY lock not supported on this function\n");
 720         }
 721 }
 722
 723 /*
 724  * Check for APE firmware, set flags, and print version info.
 725  */
 726 static void
 727 bge_ape_read_fw_ver(struct bge_softc *sc)
 728 {
 729         const char *fwtype;
 730         uint32_t apedata, features;
 731
 732         /* Check for a valid APE signature in shared memory. */
 733         apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
 734         if (apedata != BGE_APE_SEG_SIG_MAGIC) {
 735                 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
 736                 return;
 737         }
 738
 739         /* Check if APE firmware is running. */
 740         apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
 741         if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
 742                 device_printf(sc->bge_dev, "APE signature found "
 743                     "but FW status not ready! 0x%08x\n", apedata);
 744                 return;
 745         }
 746
 747         sc->bge_mfw_flags |= BGE_MFW_ON_APE;
 748
 749         /* Fetch the APE firwmare type and version. */
 750         apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
 751         features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
 752         if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
 753                 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
 754                 fwtype = "NCSI";
 755         } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
 756                 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
 757                 fwtype = "DASH";
 758         } else
 759                 fwtype = "UNKN";
 760
 761         /* Print the APE firmware version. */
 762         device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
 763             fwtype,
 764             (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
 765             (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
 766             (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
 767             (apedata & BGE_APE_FW_VERSION_BLDMSK));
 768 }
 769
 770 static int
 771 bge_ape_lock(struct bge_softc *sc, int locknum)
 772 {
 773         uint32_t bit, gnt, req, status;
 774         int i, off;
 775
 776         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 777                 return (0);
 778
 779         /* Lock request/grant registers have different bases. */
 780         if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
 781                 req = BGE_APE_LOCK_REQ;
 782                 gnt = BGE_APE_LOCK_GRANT;
 783         } else {
 784                 req = BGE_APE_PER_LOCK_REQ;
 785                 gnt = BGE_APE_PER_LOCK_GRANT;
 786         }
 787
 788         off = 4 * locknum;
 789
 790         switch (locknum) {
 791         case BGE_APE_LOCK_GPIO:
 792                 /* Lock required when using GPIO. */
 793                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 794                         return (0);
 795                 if (sc->bge_func_addr == 0)
 796                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 797                 else
 798                         bit = (1 << sc->bge_func_addr);
 799                 break;
 800         case BGE_APE_LOCK_GRC:
 801                 /* Lock required to reset the device. */
 802                 if (sc->bge_func_addr == 0)
 803                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 804                 else
 805                         bit = (1 << sc->bge_func_addr);
 806                 break;
 807         case BGE_APE_LOCK_MEM:
 808                 /* Lock required when accessing certain APE memory. */
 809                 if (sc->bge_func_addr == 0)
 810                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 811                 else
 812                         bit = (1 << sc->bge_func_addr);
 813                 break;
 814         case BGE_APE_LOCK_PHY0:
 815         case BGE_APE_LOCK_PHY1:
 816         case BGE_APE_LOCK_PHY2:
 817         case BGE_APE_LOCK_PHY3:
 818                 /* Lock required when accessing PHYs. */
 819                 bit = BGE_APE_LOCK_REQ_DRIVER0;
 820                 break;
 821         default:
 822                 return (EINVAL);
 823         }
 824
 825         /* Request a lock. */
 826         APE_WRITE_4(sc, req + off, bit);
 827
 828         /* Wait up to 1 second to acquire lock. */
 829         for (i = 0; i < 20000; i++) {
 830                 status = APE_READ_4(sc, gnt + off);
 831                 if (status == bit)
 832                         break;
 833                 DELAY(50);
 834         }
 835
 836         /* Handle any errors. */
 837         if (status != bit) {
 838                 device_printf(sc->bge_dev, "APE lock %d request failed! "
 839                     "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
 840                     locknum, req + off, bit & 0xFFFF, gnt + off,
 841                     status & 0xFFFF);
 842                 /* Revoke the lock request. */
 843                 APE_WRITE_4(sc, gnt + off, bit);
 844                 return (EBUSY);
 845         }
 846
 847         return (0);
 848 }
 849
 850 static void
 851 bge_ape_unlock(struct bge_softc *sc, int locknum)
 852 {
 853         uint32_t bit, gnt;
 854         int off;
 855
 856         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 857                 return;
 858
 859         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 860                 gnt = BGE_APE_LOCK_GRANT;
 861         else
 862                 gnt = BGE_APE_PER_LOCK_GRANT;
 863
 864         off = 4 * locknum;
 865
 866         switch (locknum) {
 867         case BGE_APE_LOCK_GPIO:
 868                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 869                         return;
 870                 if (sc->bge_func_addr == 0)
 871                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 872                 else
 873                         bit = (1 << sc->bge_func_addr);
 874                 break;
 875         case BGE_APE_LOCK_GRC:
 876                 if (sc->bge_func_addr == 0)
 877                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 878                 else
 879                         bit = (1 << sc->bge_func_addr);
 880                 break;
 881         case BGE_APE_LOCK_MEM:
 882                 if (sc->bge_func_addr == 0)
 883                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 884                 else
 885                         bit = (1 << sc->bge_func_addr);
 886                 break;
 887         case BGE_APE_LOCK_PHY0:
 888         case BGE_APE_LOCK_PHY1:
 889         case BGE_APE_LOCK_PHY2:
 890         case BGE_APE_LOCK_PHY3:
 891                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 892                 break;
 893         default:
 894                 return;
 895         }
 896
 897         APE_WRITE_4(sc, gnt + off, bit);
 898 }
 899
 900 /*
 901  * Send an event to the APE firmware.
 902  */
 903 static void
 904 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
 905 {
 906         uint32_t apedata;
 907         int i;
 908
 909         /* NCSI does not support APE events. */
 910         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 911                 return;
 912
 913         /* Wait up to 1ms for APE to service previous event. */
 914         for (i = 10; i > 0; i--) {
 915                 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
 916                         break;
 917                 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
 918                 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
 919                         APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
 920                             BGE_APE_EVENT_STATUS_EVENT_PENDING);
 921                         bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 922                         APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
 923                         break;
 924                 }
 925                 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 926                 DELAY(100);
 927         }
 928         if (i == 0)
 929                 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
 930                     event);
 931 }
 932
 933 static void
 934 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
 935 {
 936         uint32_t apedata, event;
 937
 938         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 939                 return;
 940
 941         switch (kind) {
 942         case BGE_RESET_START:
 943                 /* If this is the first load, clear the load counter. */
 944                 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
 945                 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
 946                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
 947                 else {
 948                         apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
 949                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
 950                 }
 951                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
 952                     BGE_APE_HOST_SEG_SIG_MAGIC);
 953                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
 954                     BGE_APE_HOST_SEG_LEN_MAGIC);
 955
 956                 /* Add some version info if bge(4) supports it. */
 957                 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
 958                     BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
 959                 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
 960                     BGE_APE_HOST_BEHAV_NO_PHYLOCK);
 961                 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
 962                     BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
 963                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 964                     BGE_APE_HOST_DRVR_STATE_START);
 965                 event = BGE_APE_EVENT_STATUS_STATE_START;
 966                 break;
 967         case BGE_RESET_SHUTDOWN:
 968                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 969                     BGE_APE_HOST_DRVR_STATE_UNLOAD);
 970                 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
 971                 break;
 972         case BGE_RESET_SUSPEND:
 973                 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
 974                 break;
 975         default:
 976                 return;
 977         }
 978
 979         bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
 980             BGE_APE_EVENT_STATUS_STATE_CHNGE);
 981 }
 982
 983 /*
 984  * Map a single buffer address.
 985  */
 986
 987 static void
 988 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 989 {
 990         struct bge_dmamap_arg *ctx;
 991
 992         if (error)
 993                 return;
 994
 995         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 996
 997         ctx = arg;
 998         ctx->bge_busaddr = segs->ds_addr;
 999 }
1000
1001 static uint8_t
1002 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1003 {
1004         uint32_t access, byte = 0;
1005         int i;
1006
1007         /* Lock. */
1008         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1009         for (i = 0; i < 8000; i++) {
1010                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1011                         break;
1012                 DELAY(20);
1013         }
1014         if (i == 8000)
1015                 return (1);
1016
1017         /* Enable access. */
1018         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1019         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1020
1021         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1022         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1023         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1024                 DELAY(10);
1025                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1026                         DELAY(10);
1027                         break;
1028                 }
1029         }
1030
1031         if (i == BGE_TIMEOUT * 10) {
1032                 if_printf(sc->bge_ifp, "nvram read timed out\n");
1033                 return (1);
1034         }
1035
1036         /* Get result. */
1037         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1038
1039         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1040
1041         /* Disable access. */
1042         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1043
1044         /* Unlock. */
1045         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1046         CSR_READ_4(sc, BGE_NVRAM_SWARB);
1047
1048         return (0);
1049 }
1050
1051 /*
1052  * Read a sequence of bytes from NVRAM.
1053  */
1054 static int
1055 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1056 {
1057         int err = 0, i;
1058         uint8_t byte = 0;
1059
1060         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1061                 return (1);
1062
1063         for (i = 0; i < cnt; i++) {
1064                 err = bge_nvram_getbyte(sc, off + i, &byte);
1065                 if (err)
1066                         break;
1067                 *(dest + i) = byte;
1068         }
1069
1070         return (err ? 1 : 0);
1071 }
1072
1073 /*
1074  * Read a byte of data stored in the EEPROM at address 'addr.' The
1075  * BCM570x supports both the traditional bitbang interface and an
1076  * auto access interface for reading the EEPROM. We use the auto
1077  * access method.
1078  */
1079 static uint8_t
1080 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1081 {
1082         int i;
1083         uint32_t byte = 0;
1084
1085         /*
1086          * Enable use of auto EEPROM access so we can avoid
1087          * having to use the bitbang method.
1088          */
1089         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1090
1091         /* Reset the EEPROM, load the clock period. */
1092         CSR_WRITE_4(sc, BGE_EE_ADDR,
1093             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1094         DELAY(20);
1095
1096         /* Issue the read EEPROM command. */
1097         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1098
1099         /* Wait for completion */
1100         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1101                 DELAY(10);
1102                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1103                         break;
1104         }
1105
1106         if (i == BGE_TIMEOUT * 10) {
1107                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1108                 return (1);
1109         }
1110
1111         /* Get result. */
1112         byte = CSR_READ_4(sc, BGE_EE_DATA);
1113
1114         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1115
1116         return (0);
1117 }
1118
1119 /*
1120  * Read a sequence of bytes from the EEPROM.
1121  */
1122 static int
1123 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1124 {
1125         int i, error = 0;
1126         uint8_t byte = 0;
1127
1128         for (i = 0; i < cnt; i++) {
1129                 error = bge_eeprom_getbyte(sc, off + i, &byte);
1130                 if (error)
1131                         break;
1132                 *(dest + i) = byte;
1133         }
1134
1135         return (error ? 1 : 0);
1136 }
1137
1138 static int
1139 bge_miibus_readreg(device_t dev, int phy, int reg)
1140 {
1141         struct bge_softc *sc;
1142         uint32_t val;
1143         int i;
1144
1145         sc = device_get_softc(dev);
1146
1147         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1148                 return (0);
1149
1150         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1151         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1152                 CSR_WRITE_4(sc, BGE_MI_MODE,
1153                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1154                 DELAY(80);
1155         }
1156
1157         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1158             BGE_MIPHY(phy) | BGE_MIREG(reg));
1159
1160         /* Poll for the PHY register access to complete. */
1161         for (i = 0; i < BGE_TIMEOUT; i++) {
1162                 DELAY(10);
1163                 val = CSR_READ_4(sc, BGE_MI_COMM);
1164                 if ((val & BGE_MICOMM_BUSY) == 0) {
1165                         DELAY(5);
1166                         val = CSR_READ_4(sc, BGE_MI_COMM);
1167                         break;
1168                 }
1169         }
1170
1171         if (i == BGE_TIMEOUT) {
1172                 device_printf(sc->bge_dev,
1173                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1174                     phy, reg, val);
1175                 val = 0;
1176         }
1177
1178         /* Restore the autopoll bit if necessary. */
1179         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1180                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1181                 DELAY(80);
1182         }
1183
1184         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1185
1186         if (val & BGE_MICOMM_READFAIL)
1187                 return (0);
1188
1189         return (val & 0xFFFF);
1190 }
1191
1192 static int
1193 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1194 {
1195         struct bge_softc *sc;
1196         int i;
1197
1198         sc = device_get_softc(dev);
1199
1200         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1201             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1202                 return (0);
1203
1204         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1205                 return (0);
1206
1207         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1208         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1209                 CSR_WRITE_4(sc, BGE_MI_MODE,
1210                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1211                 DELAY(80);
1212         }
1213
1214         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1215             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1216
1217         for (i = 0; i < BGE_TIMEOUT; i++) {
1218                 DELAY(10);
1219                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1220                         DELAY(5);
1221                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1222                         break;
1223                 }
1224         }
1225
1226         /* Restore the autopoll bit if necessary. */
1227         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1228                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1229                 DELAY(80);
1230         }
1231
1232         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1233
1234         if (i == BGE_TIMEOUT)
1235                 device_printf(sc->bge_dev,
1236                     "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1237                     phy, reg, val);
1238
1239         return (0);
1240 }
1241
1242 static void
1243 bge_miibus_statchg(device_t dev)
1244 {
1245         struct bge_softc *sc;
1246         struct mii_data *mii;
1247         uint32_t mac_mode, rx_mode, tx_mode;
1248
1249         sc = device_get_softc(dev);
1250         if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1251                 return;
1252         mii = device_get_softc(sc->bge_miibus);
1253
1254         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1255             (IFM_ACTIVE | IFM_AVALID)) {
1256                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1257                 case IFM_10_T:
1258                 case IFM_100_TX:
1259                         sc->bge_link = 1;
1260                         break;
1261                 case IFM_1000_T:
1262                 case IFM_1000_SX:
1263                 case IFM_2500_SX:
1264                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1265                                 sc->bge_link = 1;
1266                         else
1267                                 sc->bge_link = 0;
1268                         break;
1269                 default:
1270                         sc->bge_link = 0;
1271                         break;
1272                 }
1273         } else
1274                 sc->bge_link = 0;
1275         if (sc->bge_link == 0)
1276                 return;
1277
1278         /*
1279          * APE firmware touches these registers to keep the MAC
1280          * connected to the outside world.  Try to keep the
1281          * accesses atomic.
1282          */
1283
1284         /* Set the port mode (MII/GMII) to match the link speed. */
1285         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1286             ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1287         tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1288         rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1289
1290         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1291             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1292                 mac_mode |= BGE_PORTMODE_GMII;
1293         else
1294                 mac_mode |= BGE_PORTMODE_MII;
1295
1296         /* Set MAC flow control behavior to match link flow control settings. */
1297         tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1298         rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1299         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1300                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1301                         tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1302                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1303                         rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1304         } else
1305                 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1306
1307         CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1308         DELAY(40);
1309         CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1310         CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1311 }
1312
1313 /*
1314  * Intialize a standard receive ring descriptor.
1315  */
1316 static int
1317 bge_newbuf_std(struct bge_softc *sc, int i)
1318 {
1319         struct mbuf *m;
1320         struct bge_rx_bd *r;
1321         bus_dma_segment_t segs[1];
1322         bus_dmamap_t map;
1323         int error, nsegs;
1324
1325         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1326             (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
1327             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1328                 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1329                 if (m == NULL)
1330                         return (ENOBUFS);
1331                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1332         } else {
1333                 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1334                 if (m == NULL)
1335                         return (ENOBUFS);
1336                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1337         }
1338         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1339                 m_adj(m, ETHER_ALIGN);
1340
1341         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1342             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1343         if (error != 0) {
1344                 m_freem(m);
1345                 return (error);
1346         }
1347         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1348                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1349                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1350                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1351                     sc->bge_cdata.bge_rx_std_dmamap[i]);
1352         }
1353         map = sc->bge_cdata.bge_rx_std_dmamap[i];
1354         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1355         sc->bge_cdata.bge_rx_std_sparemap = map;
1356         sc->bge_cdata.bge_rx_std_chain[i] = m;
1357         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1358         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1359         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1360         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1361         r->bge_flags = BGE_RXBDFLAG_END;
1362         r->bge_len = segs[0].ds_len;
1363         r->bge_idx = i;
1364
1365         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1366             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1367
1368         return (0);
1369 }
1370
1371 /*
1372  * Initialize a jumbo receive ring descriptor. This allocates
1373  * a jumbo buffer from the pool managed internally by the driver.
1374  */
1375 static int
1376 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1377 {
1378         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1379         bus_dmamap_t map;
1380         struct bge_extrx_bd *r;
1381         struct mbuf *m;
1382         int error, nsegs;
1383
1384         MGETHDR(m, M_NOWAIT, MT_DATA);
1385         if (m == NULL)
1386                 return (ENOBUFS);
1387
1388         m_cljget(m, M_NOWAIT, MJUM9BYTES);
1389         if (!(m->m_flags & M_EXT)) {
1390                 m_freem(m);
1391                 return (ENOBUFS);
1392         }
1393         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1394         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1395                 m_adj(m, ETHER_ALIGN);
1396
1397         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1398             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1399         if (error != 0) {
1400                 m_freem(m);
1401                 return (error);
1402         }
1403
1404         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1405                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1406                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1407                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1408                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1409         }
1410         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1411         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1412             sc->bge_cdata.bge_rx_jumbo_sparemap;
1413         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1414         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1415         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1416         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1417         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1418         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1419
1420         /*
1421          * Fill in the extended RX buffer descriptor.
1422          */
1423         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1424         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1425         r->bge_idx = i;
1426         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1427         switch (nsegs) {
1428         case 4:
1429                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1430                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1431                 r->bge_len3 = segs[3].ds_len;
1432                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1433         case 3:
1434                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1435                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1436                 r->bge_len2 = segs[2].ds_len;
1437                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1438         case 2:
1439                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1440                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1441                 r->bge_len1 = segs[1].ds_len;
1442                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1443         case 1:
1444                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1445                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1446                 r->bge_len0 = segs[0].ds_len;
1447                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1448                 break;
1449         default:
1450                 panic("%s: %d segments\n", __func__, nsegs);
1451         }
1452
1453         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1454             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1455
1456         return (0);
1457 }
1458
1459 static int
1460 bge_init_rx_ring_std(struct bge_softc *sc)
1461 {
1462         int error, i;
1463
1464         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1465         sc->bge_std = 0;
1466         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1467                 if ((error = bge_newbuf_std(sc, i)) != 0)
1468                         return (error);
1469                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1470         }
1471
1472         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1473             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1474
1475         sc->bge_std = 0;
1476         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1477
1478         return (0);
1479 }
1480
1481 static void
1482 bge_free_rx_ring_std(struct bge_softc *sc)
1483 {
1484         int i;
1485
1486         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1487                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1488                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1489                             sc->bge_cdata.bge_rx_std_dmamap[i],
1490                             BUS_DMASYNC_POSTREAD);
1491                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1492                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1493                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1494                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1495                 }
1496                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1497                     sizeof(struct bge_rx_bd));
1498         }
1499 }
1500
1501 static int
1502 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1503 {
1504         struct bge_rcb *rcb;
1505         int error, i;
1506
1507         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1508         sc->bge_jumbo = 0;
1509         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1510                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1511                         return (error);
1512                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1513         }
1514
1515         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1516             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1517
1518         sc->bge_jumbo = 0;
1519
1520         /* Enable the jumbo receive producer ring. */
1521         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1522         rcb->bge_maxlen_flags =
1523             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1524         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1525
1526         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1527
1528         return (0);
1529 }
1530
1531 static void
1532 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1533 {
1534         int i;
1535
1536         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1537                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1538                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1539                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1540                             BUS_DMASYNC_POSTREAD);
1541                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1542                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1543                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1544                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1545                 }
1546                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1547                     sizeof(struct bge_extrx_bd));
1548         }
1549 }
1550
1551 static void
1552 bge_free_tx_ring(struct bge_softc *sc)
1553 {
1554         int i;
1555
1556         if (sc->bge_ldata.bge_tx_ring == NULL)
1557                 return;
1558
1559         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1560                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1561                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1562                             sc->bge_cdata.bge_tx_dmamap[i],
1563                             BUS_DMASYNC_POSTWRITE);
1564                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1565                             sc->bge_cdata.bge_tx_dmamap[i]);
1566                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1567                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1568                 }
1569                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1570                     sizeof(struct bge_tx_bd));
1571         }
1572 }
1573
1574 static int
1575 bge_init_tx_ring(struct bge_softc *sc)
1576 {
1577         sc->bge_txcnt = 0;
1578         sc->bge_tx_saved_considx = 0;
1579
1580         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1581         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1582             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1583
1584         /* Initialize transmit producer index for host-memory send ring. */
1585         sc->bge_tx_prodidx = 0;
1586         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1587
1588         /* 5700 b2 errata */
1589         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1590                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1591
1592         /* NIC-memory send ring not used; initialize to zero. */
1593         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1594         /* 5700 b2 errata */
1595         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1596                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1597
1598         return (0);
1599 }
1600
1601 static void
1602 bge_setpromisc(struct bge_softc *sc)
1603 {
1604         struct ifnet *ifp;
1605
1606         BGE_LOCK_ASSERT(sc);
1607
1608         ifp = sc->bge_ifp;
1609
1610         /* Enable or disable promiscuous mode as needed. */
1611         if (ifp->if_flags & IFF_PROMISC)
1612                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1613         else
1614                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1615 }
1616
1617 static void
1618 bge_setmulti(struct bge_softc *sc)
1619 {
1620         struct ifnet *ifp;
1621         struct ifmultiaddr *ifma;
1622         uint32_t hashes[4] = { 0, 0, 0, 0 };
1623         int h, i;
1624
1625         BGE_LOCK_ASSERT(sc);
1626
1627         ifp = sc->bge_ifp;
1628
1629         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1630                 for (i = 0; i < 4; i++)
1631                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1632                 return;
1633         }
1634
1635         /* First, zot all the existing filters. */
1636         for (i = 0; i < 4; i++)
1637                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1638
1639         /* Now program new ones. */
1640         if_maddr_rlock(ifp);
1641         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1642                 if (ifma->ifma_addr->sa_family != AF_LINK)
1643                         continue;
1644                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1645                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1646                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1647         }
1648         if_maddr_runlock(ifp);
1649
1650         for (i = 0; i < 4; i++)
1651                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1652 }
1653
1654 static void
1655 bge_setvlan(struct bge_softc *sc)
1656 {
1657         struct ifnet *ifp;
1658
1659         BGE_LOCK_ASSERT(sc);
1660
1661         ifp = sc->bge_ifp;
1662
1663         /* Enable or disable VLAN tag stripping as needed. */
1664         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1665                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1666         else
1667                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1668 }
1669
1670 static void
1671 bge_sig_pre_reset(struct bge_softc *sc, int type)
1672 {
1673
1674         /*
1675          * Some chips don't like this so only do this if ASF is enabled
1676          */
1677         if (sc->bge_asf_mode)
1678                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1679
1680         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1681                 switch (type) {
1682                 case BGE_RESET_START:
1683                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1684                             BGE_FW_DRV_STATE_START);
1685                         break;
1686                 case BGE_RESET_SHUTDOWN:
1687                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1688                             BGE_FW_DRV_STATE_UNLOAD);
1689                         break;
1690                 case BGE_RESET_SUSPEND:
1691                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1692                             BGE_FW_DRV_STATE_SUSPEND);
1693                         break;
1694                 }
1695         }
1696
1697         if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1698                 bge_ape_driver_state_change(sc, type);
1699 }
1700
1701 static void
1702 bge_sig_post_reset(struct bge_softc *sc, int type)
1703 {
1704
1705         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1706                 switch (type) {
1707                 case BGE_RESET_START:
1708                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1709                             BGE_FW_DRV_STATE_START_DONE);
1710                         /* START DONE */
1711                         break;
1712                 case BGE_RESET_SHUTDOWN:
1713                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1714                             BGE_FW_DRV_STATE_UNLOAD_DONE);
1715                         break;
1716                 }
1717         }
1718         if (type == BGE_RESET_SHUTDOWN)
1719                 bge_ape_driver_state_change(sc, type);
1720 }
1721
1722 static void
1723 bge_sig_legacy(struct bge_softc *sc, int type)
1724 {
1725
1726         if (sc->bge_asf_mode) {
1727                 switch (type) {
1728                 case BGE_RESET_START:
1729                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1730                             BGE_FW_DRV_STATE_START);
1731                         break;
1732                 case BGE_RESET_SHUTDOWN:
1733                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1734                             BGE_FW_DRV_STATE_UNLOAD);
1735                         break;
1736                 }
1737         }
1738 }
1739
1740 static void
1741 bge_stop_fw(struct bge_softc *sc)
1742 {
1743         int i;
1744
1745         if (sc->bge_asf_mode) {
1746                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1747                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1748                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1749
1750                 for (i = 0; i < 100; i++ ) {
1751                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1752                             BGE_RX_CPU_DRV_EVENT))
1753                                 break;
1754                         DELAY(10);
1755                 }
1756         }
1757 }
1758
1759 static uint32_t
1760 bge_dma_swap_options(struct bge_softc *sc)
1761 {
1762         uint32_t dma_options;
1763
1764         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1765             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1766 #if BYTE_ORDER == BIG_ENDIAN
1767         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1768 #endif
1769         return (dma_options);
1770 }
1771
1772 /*
1773  * Do endian, PCI and DMA initialization.
1774  */
1775 static int
1776 bge_chipinit(struct bge_softc *sc)
1777 {
1778         uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1779         uint16_t val;
1780         int i;
1781
1782         /* Set endianness before we access any non-PCI registers. */
1783         misc_ctl = BGE_INIT;
1784         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1785                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1786         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1787
1788         /*
1789          * Clear the MAC statistics block in the NIC's
1790          * internal memory.
1791          */
1792         for (i = BGE_STATS_BLOCK;
1793             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1794                 BGE_MEMWIN_WRITE(sc, i, 0);
1795
1796         for (i = BGE_STATUS_BLOCK;
1797             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1798                 BGE_MEMWIN_WRITE(sc, i, 0);
1799
1800         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1801                 /*
1802                  *  Fix data corruption caused by non-qword write with WB.
1803                  *  Fix master abort in PCI mode.
1804                  *  Fix PCI latency timer.
1805                  */
1806                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1807                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1808                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1809         }
1810
1811         if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1812             sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1813                 /*
1814                  * For the 57766 and non Ax versions of 57765, bootcode
1815                  * needs to setup the PCIE Fast Training Sequence (FTS)
1816                  * value to prevent transmit hangs.
1817                  */
1818                 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1819                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1820                             CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1821                             BGE_CPMU_PADRNG_CTL_RDIV2);
1822                 }
1823         }
1824
1825         /*
1826          * Set up the PCI DMA control register.
1827          */
1828         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1829             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1830         if (sc->bge_flags & BGE_FLAG_PCIE) {
1831                 if (sc->bge_mps >= 256)
1832                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1833                 else
1834                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1835         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1836                 if (BGE_IS_5714_FAMILY(sc)) {
1837                         /* 256 bytes for read and write. */
1838                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1839                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1840                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1841                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1842                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1843                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1844                         /*
1845                          * In the BCM5703, the DMA read watermark should
1846                          * be set to less than or equal to the maximum
1847                          * memory read byte count of the PCI-X command
1848                          * register.
1849                          */
1850                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1851                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1852                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1853                         /* 1536 bytes for read, 384 bytes for write. */
1854                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1855                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1856                 } else {
1857                         /* 384 bytes for read and write. */
1858                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1859                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1860                             0x0F;
1861                 }
1862                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1863                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1864                         uint32_t tmp;
1865
1866                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1867                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1868                         if (tmp == 6 || tmp == 7)
1869                                 dma_rw_ctl |=
1870                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1871
1872                         /* Set PCI-X DMA write workaround. */
1873                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1874                 }
1875         } else {
1876                 /* Conventional PCI bus: 256 bytes for read and write. */
1877                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1878                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1879
1880                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1881                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1882                         dma_rw_ctl |= 0x0F;
1883         }
1884         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1885             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1886                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1887                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1888         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1889             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1890                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1891         if (BGE_IS_5717_PLUS(sc)) {
1892                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1893                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1894                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1895                 /*
1896                  * Enable HW workaround for controllers that misinterpret
1897                  * a status tag update and leave interrupts permanently
1898                  * disabled.
1899                  */
1900                 if (!BGE_IS_57765_PLUS(sc) &&
1901                     sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1902                     sc->bge_asicrev != BGE_ASICREV_BCM5762)
1903                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1904         }
1905         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1906
1907         /*
1908          * Set up general mode register.
1909          */
1910         mode_ctl = bge_dma_swap_options(sc);
1911         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1912             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1913                 /* Retain Host-2-BMC settings written by APE firmware. */
1914                 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1915                     (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1916                     BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1917                     BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1918         }
1919         mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1920             BGE_MODECTL_TX_NO_PHDR_CSUM;
1921
1922         /*
1923          * BCM5701 B5 have a bug causing data corruption when using
1924          * 64-bit DMA reads, which can be terminated early and then
1925          * completed later as 32-bit accesses, in combination with
1926          * certain bridges.
1927          */
1928         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1929             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1930                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1931
1932         /*
1933          * Tell the firmware the driver is running
1934          */
1935         if (sc->bge_asf_mode & ASF_STACKUP)
1936                 mode_ctl |= BGE_MODECTL_STACKUP;
1937
1938         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1939
1940         /*
1941          * Disable memory write invalidate.  Apparently it is not supported
1942          * properly by these devices.
1943          */
1944         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1945
1946         /* Set the timer prescaler (always 66 MHz). */
1947         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1948
1949         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1950         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1951                 DELAY(40);      /* XXX */
1952
1953                 /* Put PHY into ready state */
1954                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1955                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1956                 DELAY(40);
1957         }
1958
1959         return (0);
1960 }
1961
1962 static int
1963 bge_blockinit(struct bge_softc *sc)
1964 {
1965         struct bge_rcb *rcb;
1966         bus_size_t vrcb;
1967         bge_hostaddr taddr;
1968         uint32_t dmactl, rdmareg, val;
1969         int i, limit;
1970
1971         /*
1972          * Initialize the memory window pointer register so that
1973          * we can access the first 32K of internal NIC RAM. This will
1974          * allow us to set up the TX send ring RCBs and the RX return
1975          * ring RCBs, plus other things which live in NIC memory.
1976          */
1977         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1978
1979         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1980
1981         if (!(BGE_IS_5705_PLUS(sc))) {
1982                 /* Configure mbuf memory pool */
1983                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1984                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1985                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1986                 else
1987                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1988
1989                 /* Configure DMA resource pool */
1990                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1991                     BGE_DMA_DESCRIPTORS);
1992                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1993         }
1994
1995         /* Configure mbuf pool watermarks */
1996         if (BGE_IS_5717_PLUS(sc)) {
1997                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1998                 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1999                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2000                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2001                 } else {
2002                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2003                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2004                 }
2005         } else if (!BGE_IS_5705_PLUS(sc)) {
2006                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2007                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2008                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2009         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2010                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2011                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2012                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2013         } else {
2014                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2015                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2016                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2017         }
2018
2019         /* Configure DMA resource watermarks */
2020         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2021         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2022
2023         /* Enable buffer manager */
2024         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2025         /*
2026          * Change the arbitration algorithm of TXMBUF read request to
2027          * round-robin instead of priority based for BCM5719.  When
2028          * TXFIFO is almost empty, RDMA will hold its request until
2029          * TXFIFO is not almost empty.
2030          */
2031         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2032                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2033         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2034
2035         /* Poll for buffer manager start indication */
2036         for (i = 0; i < BGE_TIMEOUT; i++) {
2037                 DELAY(10);
2038                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2039                         break;
2040         }
2041
2042         if (i == BGE_TIMEOUT) {
2043                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2044                 return (ENXIO);
2045         }
2046
2047         /* Enable flow-through queues */
2048         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2049         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2050
2051         /* Wait until queue initialization is complete */
2052         for (i = 0; i < BGE_TIMEOUT; i++) {
2053                 DELAY(10);
2054                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2055                         break;
2056         }
2057
2058         if (i == BGE_TIMEOUT) {
2059                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2060                 return (ENXIO);
2061         }
2062
2063         /*
2064          * Summary of rings supported by the controller:
2065          *
2066          * Standard Receive Producer Ring
2067          * - This ring is used to feed receive buffers for "standard"
2068          *   sized frames (typically 1536 bytes) to the controller.
2069          *
2070          * Jumbo Receive Producer Ring
2071          * - This ring is used to feed receive buffers for jumbo sized
2072          *   frames (i.e. anything bigger than the "standard" frames)
2073          *   to the controller.
2074          *
2075          * Mini Receive Producer Ring
2076          * - This ring is used to feed receive buffers for "mini"
2077          *   sized frames to the controller.
2078          * - This feature required external memory for the controller
2079          *   but was never used in a production system.  Should always
2080          *   be disabled.
2081          *
2082          * Receive Return Ring
2083          * - After the controller has placed an incoming frame into a
2084          *   receive buffer that buffer is moved into a receive return
2085          *   ring.  The driver is then responsible to passing the
2086          *   buffer up to the stack.  Many versions of the controller
2087          *   support multiple RR rings.
2088          *
2089          * Send Ring
2090          * - This ring is used for outgoing frames.  Many versions of
2091          *   the controller support multiple send rings.
2092          */
2093
2094         /* Initialize the standard receive producer ring control block. */
2095         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2096         rcb->bge_hostaddr.bge_addr_lo =
2097             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2098         rcb->bge_hostaddr.bge_addr_hi =
2099             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2100         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2101             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2102         if (BGE_IS_5717_PLUS(sc)) {
2103                 /*
2104                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2105                  * Bits 15-2 : Maximum RX frame size
2106                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
2107                  * Bit 0     : Reserved
2108                  */
2109                 rcb->bge_maxlen_flags =
2110                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2111         } else if (BGE_IS_5705_PLUS(sc)) {
2112                 /*
2113                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2114                  * Bits 15-2 : Reserved (should be 0)
2115                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2116                  * Bit 0     : Reserved
2117                  */
2118                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2119         } else {
2120                 /*
2121                  * Ring size is always XXX entries
2122                  * Bits 31-16: Maximum RX frame size
2123                  * Bits 15-2 : Reserved (should be 0)
2124                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2125                  * Bit 0     : Reserved
2126                  */
2127                 rcb->bge_maxlen_flags =
2128                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2129         }
2130         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2131             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2132             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2133                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2134         else
2135                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2136         /* Write the standard receive producer ring control block. */
2137         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2138         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2139         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2140         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2141
2142         /* Reset the standard receive producer ring producer index. */
2143         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2144
2145         /*
2146          * Initialize the jumbo RX producer ring control
2147          * block.  We set the 'ring disabled' bit in the
2148          * flags field until we're actually ready to start
2149          * using this ring (i.e. once we set the MTU
2150          * high enough to require it).
2151          */
2152         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2153                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2154                 /* Get the jumbo receive producer ring RCB parameters. */
2155                 rcb->bge_hostaddr.bge_addr_lo =
2156                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2157                 rcb->bge_hostaddr.bge_addr_hi =
2158                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2159                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2160                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2161                     BUS_DMASYNC_PREREAD);
2162                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2163                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2164                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2165                     sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2166                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
2167                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2168                 else
2169                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2170                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2171                     rcb->bge_hostaddr.bge_addr_hi);
2172                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2173                     rcb->bge_hostaddr.bge_addr_lo);
2174                 /* Program the jumbo receive producer ring RCB parameters. */
2175                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2176                     rcb->bge_maxlen_flags);
2177                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2178                 /* Reset the jumbo receive producer ring producer index. */
2179                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2180         }
2181
2182         /* Disable the mini receive producer ring RCB. */
2183         if (BGE_IS_5700_FAMILY(sc)) {
2184                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2185                 rcb->bge_maxlen_flags =
2186                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2187                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2188                     rcb->bge_maxlen_flags);
2189                 /* Reset the mini receive producer ring producer index. */
2190                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2191         }
2192
2193         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2194         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2195                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2196                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2197                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2198                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2199                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2200         }
2201         /*
2202          * The BD ring replenish thresholds control how often the
2203          * hardware fetches new BD's from the producer rings in host
2204          * memory.  Setting the value too low on a busy system can
2205          * starve the hardware and recue the throughpout.
2206          *
2207          * Set the BD ring replentish thresholds. The recommended
2208          * values are 1/8th the number of descriptors allocated to
2209          * each ring.
2210          * XXX The 5754 requires a lower threshold, so it might be a
2211          * requirement of all 575x family chips.  The Linux driver sets
2212          * the lower threshold for all 5705 family chips as well, but there
2213          * are reports that it might not need to be so strict.
2214          *
2215          * XXX Linux does some extra fiddling here for the 5906 parts as
2216          * well.
2217          */
2218         if (BGE_IS_5705_PLUS(sc))
2219                 val = 8;
2220         else
2221                 val = BGE_STD_RX_RING_CNT / 8;
2222         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2223         if (BGE_IS_JUMBO_CAPABLE(sc))
2224                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2225                     BGE_JUMBO_RX_RING_CNT/8);
2226         if (BGE_IS_5717_PLUS(sc)) {
2227                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2228                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2229         }
2230
2231         /*
2232          * Disable all send rings by setting the 'ring disabled' bit
2233          * in the flags field of all the TX send ring control blocks,
2234          * located in NIC memory.
2235          */
2236         if (!BGE_IS_5705_PLUS(sc))
2237                 /* 5700 to 5704 had 16 send rings. */
2238                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2239         else if (BGE_IS_57765_PLUS(sc) ||
2240             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2241                 limit = 2;
2242         else if (BGE_IS_5717_PLUS(sc))
2243                 limit = 4;
2244         else
2245                 limit = 1;
2246         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2247         for (i = 0; i < limit; i++) {
2248                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2249                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2250                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2251                 vrcb += sizeof(struct bge_rcb);
2252         }
2253
2254         /* Configure send ring RCB 0 (we use only the first ring) */
2255         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2256         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2257         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2258         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2259         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2260             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2261             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2262                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2263         else
2264                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2265                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2266         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2267             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2268
2269         /*
2270          * Disable all receive return rings by setting the
2271          * 'ring diabled' bit in the flags field of all the receive
2272          * return ring control blocks, located in NIC memory.
2273          */
2274         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2275             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2276             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2277                 /* Should be 17, use 16 until we get an SRAM map. */
2278                 limit = 16;
2279         } else if (!BGE_IS_5705_PLUS(sc))
2280                 limit = BGE_RX_RINGS_MAX;
2281         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2282             sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2283             BGE_IS_57765_PLUS(sc))
2284                 limit = 4;
2285         else
2286                 limit = 1;
2287         /* Disable all receive return rings. */
2288         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2289         for (i = 0; i < limit; i++) {
2290                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2291                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2292                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2293                     BGE_RCB_FLAG_RING_DISABLED);
2294                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2295                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2296                     (i * (sizeof(uint64_t))), 0);
2297                 vrcb += sizeof(struct bge_rcb);
2298         }
2299
2300         /*
2301          * Set up receive return ring 0.  Note that the NIC address
2302          * for RX return rings is 0x0.  The return rings live entirely
2303          * within the host, so the nicaddr field in the RCB isn't used.
2304          */
2305         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2306         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2307         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2308         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2309         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2310         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2311             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2312
2313         /* Set random backoff seed for TX */
2314         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2315             (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2316             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2317             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2318             BGE_TX_BACKOFF_SEED_MASK);
2319
2320         /* Set inter-packet gap */
2321         val = 0x2620;
2322         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2323             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2324                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2325                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2326         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2327
2328         /*
2329          * Specify which ring to use for packets that don't match
2330          * any RX rules.
2331          */
2332         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2333
2334         /*
2335          * Configure number of RX lists. One interrupt distribution
2336          * list, sixteen active lists, one bad frames class.
2337          */
2338         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2339
2340         /* Inialize RX list placement stats mask. */
2341         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2342         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2343
2344         /* Disable host coalescing until we get it set up */
2345         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2346
2347         /* Poll to make sure it's shut down. */
2348         for (i = 0; i < BGE_TIMEOUT; i++) {
2349                 DELAY(10);
2350                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2351                         break;
2352         }
2353
2354         if (i == BGE_TIMEOUT) {
2355                 device_printf(sc->bge_dev,
2356                     "host coalescing engine failed to idle\n");
2357                 return (ENXIO);
2358         }
2359
2360         /* Set up host coalescing defaults */
2361         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2362         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2363         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2364         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2365         if (!(BGE_IS_5705_PLUS(sc))) {
2366                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2367                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2368         }
2369         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2370         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2371
2372         /* Set up address of statistics block */
2373         if (!(BGE_IS_5705_PLUS(sc))) {
2374                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2375                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2376                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2377                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2378                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2379                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2380                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2381         }
2382
2383         /* Set up address of status block */
2384         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2385             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2386         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2387             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2388
2389         /* Set up status block size. */
2390         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2391             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2392                 val = BGE_STATBLKSZ_FULL;
2393                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2394         } else {
2395                 val = BGE_STATBLKSZ_32BYTE;
2396                 bzero(sc->bge_ldata.bge_status_block, 32);
2397         }
2398         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2399             sc->bge_cdata.bge_status_map,
2400             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2401
2402         /* Turn on host coalescing state machine */
2403         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2404
2405         /* Turn on RX BD completion state machine and enable attentions */
2406         CSR_WRITE_4(sc, BGE_RBDC_MODE,
2407             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2408
2409         /* Turn on RX list placement state machine */
2410         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2411
2412         /* Turn on RX list selector state machine. */
2413         if (!(BGE_IS_5705_PLUS(sc)))
2414                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2415
2416         /* Turn on DMA, clear stats. */
2417         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2418             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2419             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2420             BGE_MACMODE_FRMHDR_DMA_ENB;
2421
2422         if (sc->bge_flags & BGE_FLAG_TBI)
2423                 val |= BGE_PORTMODE_TBI;
2424         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2425                 val |= BGE_PORTMODE_GMII;
2426         else
2427                 val |= BGE_PORTMODE_MII;
2428
2429         /* Allow APE to send/receive frames. */
2430         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2431                 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2432
2433         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2434         DELAY(40);
2435
2436         /* Set misc. local control, enable interrupts on attentions */
2437         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2438
2439 #ifdef notdef
2440         /* Assert GPIO pins for PHY reset */
2441         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2442             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2443         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2444             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2445 #endif
2446
2447         /* Turn on DMA completion state machine */
2448         if (!(BGE_IS_5705_PLUS(sc)))
2449                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2450
2451         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2452
2453         /* Enable host coalescing bug fix. */
2454         if (BGE_IS_5755_PLUS(sc))
2455                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2456
2457         /* Request larger DMA burst size to get better performance. */
2458         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2459                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2460
2461         /* Turn on write DMA state machine */
2462         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2463         DELAY(40);
2464
2465         /* Turn on read DMA state machine */
2466         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2467
2468         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2469                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2470
2471         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2472             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2473             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2474                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2475                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2476                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2477         if (sc->bge_flags & BGE_FLAG_PCIE)
2478                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2479         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2480                 val |= BGE_RDMAMODE_TSO4_ENABLE;
2481                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2482                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2483                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
2484                         val |= BGE_RDMAMODE_TSO6_ENABLE;
2485         }
2486
2487         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2488             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2489                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2490                         BGE_RDMAMODE_H2BNC_VLAN_DET;
2491                 /*
2492                  * Allow multiple outstanding read requests from
2493                  * non-LSO read DMA engine.
2494                  */
2495                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2496         }
2497
2498         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2499             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2500             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2501             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2502             BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2503                 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2504                         rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2505                 else
2506                         rdmareg = BGE_RDMA_RSRVCTRL;
2507                 dmactl = CSR_READ_4(sc, rdmareg);
2508                 /*
2509                  * Adjust tx margin to prevent TX data corruption and
2510                  * fix internal FIFO overflow.
2511                  */
2512                 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2513                     sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2514                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2515                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2516                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2517                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2518                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2519                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2520                 }
2521                 /*
2522                  * Enable fix for read DMA FIFO overruns.
2523                  * The fix is to limit the number of RX BDs
2524                  * the hardware would fetch at a fime.
2525                  */
2526                 CSR_WRITE_4(sc, rdmareg, dmactl |
2527                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2528         }
2529
2530         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2531                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2532                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2533                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2534                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2535         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2536                 /*
2537                  * Allow 4KB burst length reads for non-LSO frames.
2538                  * Enable 512B burst length reads for buffer descriptors.
2539                  */
2540                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2541                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2542                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2543                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2544         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2545                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2546                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2547                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2548                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2549         }
2550
2551         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2552         DELAY(40);
2553
2554         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2555                 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2556                         val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2557                         if ((val & 0xFFFF) > BGE_FRAMELEN)
2558                                 break;
2559                         if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2560                                 break;
2561                 }
2562                 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2563                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2564                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2565                                 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2566                         else
2567                                 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2568                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2569                 }
2570         }
2571
2572         /* Turn on RX data completion state machine */
2573         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2574
2575         /* Turn on RX BD initiator state machine */
2576         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2577
2578         /* Turn on RX data and RX BD initiator state machine */
2579         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2580
2581         /* Turn on Mbuf cluster free state machine */
2582         if (!(BGE_IS_5705_PLUS(sc)))
2583                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2584
2585         /* Turn on send BD completion state machine */
2586         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2587
2588         /* Turn on send data completion state machine */
2589         val = BGE_SDCMODE_ENABLE;
2590         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2591                 val |= BGE_SDCMODE_CDELAY;
2592         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2593
2594         /* Turn on send data initiator state machine */
2595         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2596                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2597                     BGE_SDIMODE_HW_LSO_PRE_DMA);
2598         else
2599                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2600
2601         /* Turn on send BD initiator state machine */
2602         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2603
2604         /* Turn on send BD selector state machine */
2605         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2606
2607         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2608         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2609             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2610
2611         /* ack/clear link change events */
2612         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2613             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2614             BGE_MACSTAT_LINK_CHANGED);
2615         CSR_WRITE_4(sc, BGE_MI_STS, 0);
2616
2617         /*
2618          * Enable attention when the link has changed state for
2619          * devices that use auto polling.
2620          */
2621         if (sc->bge_flags & BGE_FLAG_TBI) {
2622                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2623         } else {
2624                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2625                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2626                         DELAY(80);
2627                 }
2628                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2629                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2630                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2631                             BGE_EVTENB_MI_INTERRUPT);
2632         }
2633
2634         /*
2635          * Clear any pending link state attention.
2636          * Otherwise some link state change events may be lost until attention
2637          * is cleared by bge_intr() -> bge_link_upd() sequence.
2638          * It's not necessary on newer BCM chips - perhaps enabling link
2639          * state change attentions implies clearing pending attention.
2640          */
2641         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2642             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2643             BGE_MACSTAT_LINK_CHANGED);
2644
2645         /* Enable link state change attentions. */
2646         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2647
2648         return (0);
2649 }
2650
2651 static const struct bge_revision *
2652 bge_lookup_rev(uint32_t chipid)
2653 {
2654         const struct bge_revision *br;
2655
2656         for (br = bge_revisions; br->br_name != NULL; br++) {
2657                 if (br->br_chipid == chipid)
2658                         return (br);
2659         }
2660
2661         for (br = bge_majorrevs; br->br_name != NULL; br++) {
2662                 if (br->br_chipid == BGE_ASICREV(chipid))
2663                         return (br);
2664         }
2665
2666         return (NULL);
2667 }
2668
2669 static const struct bge_vendor *
2670 bge_lookup_vendor(uint16_t vid)
2671 {
2672         const struct bge_vendor *v;
2673
2674         for (v = bge_vendors; v->v_name != NULL; v++)
2675                 if (v->v_id == vid)
2676                         return (v);
2677
2678         return (NULL);
2679 }
2680
2681 static uint32_t
2682 bge_chipid(device_t dev)
2683 {
2684         uint32_t id;
2685
2686         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2687             BGE_PCIMISCCTL_ASICREV_SHIFT;
2688         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2689                 /*
2690                  * Find the ASCI revision.  Different chips use different
2691                  * registers.
2692                  */
2693                 switch (pci_get_device(dev)) {
2694                 case BCOM_DEVICEID_BCM5717C:
2695                         /* 5717 C0 seems to belong to 5720 line. */
2696                         id = BGE_CHIPID_BCM5720_A0;
2697                         break;
2698                 case BCOM_DEVICEID_BCM5717:
2699                 case BCOM_DEVICEID_BCM5718:
2700                 case BCOM_DEVICEID_BCM5719:
2701                 case BCOM_DEVICEID_BCM5720:
2702                 case BCOM_DEVICEID_BCM5725:
2703                 case BCOM_DEVICEID_BCM5727:
2704                 case BCOM_DEVICEID_BCM5762:
2705                 case BCOM_DEVICEID_BCM57764:
2706                 case BCOM_DEVICEID_BCM57767:
2707                 case BCOM_DEVICEID_BCM57787:
2708                         id = pci_read_config(dev,
2709                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2710                         break;
2711                 case BCOM_DEVICEID_BCM57761:
2712                 case BCOM_DEVICEID_BCM57762:
2713                 case BCOM_DEVICEID_BCM57765:
2714                 case BCOM_DEVICEID_BCM57766:
2715                 case BCOM_DEVICEID_BCM57781:
2716                 case BCOM_DEVICEID_BCM57782:
2717                 case BCOM_DEVICEID_BCM57785:
2718                 case BCOM_DEVICEID_BCM57786:
2719                 case BCOM_DEVICEID_BCM57791:
2720                 case BCOM_DEVICEID_BCM57795:
2721                         id = pci_read_config(dev,
2722                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2723                         break;
2724                 default:
2725                         id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2726                 }
2727         }
2728         return (id);
2729 }
2730
2731 /*
2732  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2733  * against our list and return its name if we find a match.
2734  *
2735  * Note that since the Broadcom controller contains VPD support, we
2736  * try to get the device name string from the controller itself instead
2737  * of the compiled-in string. It guarantees we'll always announce the
2738  * right product name. We fall back to the compiled-in string when
2739  * VPD is unavailable or corrupt.
2740  */
2741 static int
2742 bge_probe(device_t dev)
2743 {
2744         char buf[96];
2745         char model[64];
2746         const struct bge_revision *br;
2747         const char *pname;
2748         struct bge_softc *sc;
2749         const struct bge_type *t = bge_devs;
2750         const struct bge_vendor *v;
2751         uint32_t id;
2752         uint16_t did, vid;
2753
2754         sc = device_get_softc(dev);
2755         sc->bge_dev = dev;
2756         vid = pci_get_vendor(dev);
2757         did = pci_get_device(dev);
2758         while(t->bge_vid != 0) {
2759                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2760                         id = bge_chipid(dev);
2761                         br = bge_lookup_rev(id);
2762                         if (bge_has_eaddr(sc) &&
2763                             pci_get_vpd_ident(dev, &pname) == 0)
2764                                 snprintf(model, sizeof(model), "%s", pname);
2765                         else {
2766                                 v = bge_lookup_vendor(vid);
2767                                 snprintf(model, sizeof(model), "%s %s",
2768                                     v != NULL ? v->v_name : "Unknown",
2769                                     br != NULL ? br->br_name :
2770                                     "NetXtreme/NetLink Ethernet Controller");
2771                         }
2772                         snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2773                             model, br != NULL ? "" : "unknown ", id);
2774                         device_set_desc_copy(dev, buf);
2775                         return (BUS_PROBE_DEFAULT);
2776                 }
2777                 t++;
2778         }
2779
2780         return (ENXIO);
2781 }
2782
2783 static void
2784 bge_dma_free(struct bge_softc *sc)
2785 {
2786         int i;
2787
2788         /* Destroy DMA maps for RX buffers. */
2789         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2790                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2791                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2792                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2793         }
2794         if (sc->bge_cdata.bge_rx_std_sparemap)
2795                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2796                     sc->bge_cdata.bge_rx_std_sparemap);
2797
2798         /* Destroy DMA maps for jumbo RX buffers. */
2799         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2800                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2801                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2802                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2803         }
2804         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2805                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2806                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2807
2808         /* Destroy DMA maps for TX buffers. */
2809         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2810                 if (sc->bge_cdata.bge_tx_dmamap[i])
2811                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2812                             sc->bge_cdata.bge_tx_dmamap[i]);
2813         }
2814
2815         if (sc->bge_cdata.bge_rx_mtag)
2816                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2817         if (sc->bge_cdata.bge_mtag_jumbo)
2818                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2819         if (sc->bge_cdata.bge_tx_mtag)
2820                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2821
2822         /* Destroy standard RX ring. */
2823         if (sc->bge_cdata.bge_rx_std_ring_map)
2824                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2825                     sc->bge_cdata.bge_rx_std_ring_map);
2826         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2827                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2828                     sc->bge_ldata.bge_rx_std_ring,
2829                     sc->bge_cdata.bge_rx_std_ring_map);
2830
2831         if (sc->bge_cdata.bge_rx_std_ring_tag)
2832                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2833
2834         /* Destroy jumbo RX ring. */
2835         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2836                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2837                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2838
2839         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2840             sc->bge_ldata.bge_rx_jumbo_ring)
2841                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2842                     sc->bge_ldata.bge_rx_jumbo_ring,
2843                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2844
2845         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2846                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2847
2848         /* Destroy RX return ring. */
2849         if (sc->bge_cdata.bge_rx_return_ring_map)
2850                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2851                     sc->bge_cdata.bge_rx_return_ring_map);
2852
2853         if (sc->bge_cdata.bge_rx_return_ring_map &&
2854             sc->bge_ldata.bge_rx_return_ring)
2855                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2856                     sc->bge_ldata.bge_rx_return_ring,
2857                     sc->bge_cdata.bge_rx_return_ring_map);
2858
2859         if (sc->bge_cdata.bge_rx_return_ring_tag)
2860                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2861
2862         /* Destroy TX ring. */
2863         if (sc->bge_cdata.bge_tx_ring_map)
2864                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2865                     sc->bge_cdata.bge_tx_ring_map);
2866
2867         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2868                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2869                     sc->bge_ldata.bge_tx_ring,
2870                     sc->bge_cdata.bge_tx_ring_map);
2871
2872         if (sc->bge_cdata.bge_tx_ring_tag)
2873                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2874
2875         /* Destroy status block. */
2876         if (sc->bge_cdata.bge_status_map)
2877                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2878                     sc->bge_cdata.bge_status_map);
2879
2880         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2881                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2882                     sc->bge_ldata.bge_status_block,
2883                     sc->bge_cdata.bge_status_map);
2884
2885         if (sc->bge_cdata.bge_status_tag)
2886                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2887
2888         /* Destroy statistics block. */
2889         if (sc->bge_cdata.bge_stats_map)
2890                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2891                     sc->bge_cdata.bge_stats_map);
2892
2893         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2894                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2895                     sc->bge_ldata.bge_stats,
2896                     sc->bge_cdata.bge_stats_map);
2897
2898         if (sc->bge_cdata.bge_stats_tag)
2899                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2900
2901         if (sc->bge_cdata.bge_buffer_tag)
2902                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2903
2904         /* Destroy the parent tag. */
2905         if (sc->bge_cdata.bge_parent_tag)
2906                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2907 }
2908
2909 static int
2910 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2911     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2912     bus_addr_t *paddr, const char *msg)
2913 {
2914         struct bge_dmamap_arg ctx;
2915         int error;
2916
2917         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2918             alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2919             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2920         if (error != 0) {
2921                 device_printf(sc->bge_dev,
2922                     "could not create %s dma tag\n", msg);
2923                 return (ENOMEM);
2924         }
2925         /* Allocate DMA'able memory for ring. */
2926         error = bus_dmamem_alloc(*tag, (void **)ring,
2927             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2928         if (error != 0) {
2929                 device_printf(sc->bge_dev,
2930                     "could not allocate DMA'able memory for %s\n", msg);
2931                 return (ENOMEM);
2932         }
2933         /* Load the address of the ring. */
2934         ctx.bge_busaddr = 0;
2935         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2936             &ctx, BUS_DMA_NOWAIT);
2937         if (error != 0) {
2938                 device_printf(sc->bge_dev,
2939                     "could not load DMA'able memory for %s\n", msg);
2940                 return (ENOMEM);
2941         }
2942         *paddr = ctx.bge_busaddr;
2943         return (0);
2944 }
2945
2946 static int
2947 bge_dma_alloc(struct bge_softc *sc)
2948 {
2949         bus_addr_t lowaddr;
2950         bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2951         int i, error;
2952
2953         lowaddr = BUS_SPACE_MAXADDR;
2954         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2955                 lowaddr = BGE_DMA_MAXADDR;
2956         /*
2957          * Allocate the parent bus DMA tag appropriate for PCI.
2958          */
2959         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2960             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2961             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2962             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2963         if (error != 0) {
2964                 device_printf(sc->bge_dev,
2965                     "could not allocate parent dma tag\n");
2966                 return (ENOMEM);
2967         }
2968
2969         /* Create tag for standard RX ring. */
2970         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2971             &sc->bge_cdata.bge_rx_std_ring_tag,
2972             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2973             &sc->bge_cdata.bge_rx_std_ring_map,
2974             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2975         if (error)
2976                 return (error);
2977
2978         /* Create tag for RX return ring. */
2979         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2980             &sc->bge_cdata.bge_rx_return_ring_tag,
2981             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2982             &sc->bge_cdata.bge_rx_return_ring_map,
2983             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2984         if (error)
2985                 return (error);
2986
2987         /* Create tag for TX ring. */
2988         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2989             &sc->bge_cdata.bge_tx_ring_tag,
2990             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2991             &sc->bge_cdata.bge_tx_ring_map,
2992             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2993         if (error)
2994                 return (error);
2995
2996         /*
2997          * Create tag for status block.
2998          * Because we only use single Tx/Rx/Rx return ring, use
2999          * minimum status block size except BCM5700 AX/BX which
3000          * seems to want to see full status block size regardless
3001          * of configured number of ring.
3002          */
3003         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3004             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3005                 sbsz = BGE_STATUS_BLK_SZ;
3006         else
3007                 sbsz = 32;
3008         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3009             &sc->bge_cdata.bge_status_tag,
3010             (uint8_t **)&sc->bge_ldata.bge_status_block,
3011             &sc->bge_cdata.bge_status_map,
3012             &sc->bge_ldata.bge_status_block_paddr, "status block");
3013         if (error)
3014                 return (error);
3015
3016         /* Create tag for statistics block. */
3017         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3018             &sc->bge_cdata.bge_stats_tag,
3019             (uint8_t **)&sc->bge_ldata.bge_stats,
3020             &sc->bge_cdata.bge_stats_map,
3021             &sc->bge_ldata.bge_stats_paddr, "statistics block");
3022         if (error)
3023                 return (error);
3024
3025         /* Create tag for jumbo RX ring. */
3026         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3027                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3028                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3029                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3030                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
3031                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3032                 if (error)
3033                         return (error);
3034         }
3035
3036         /* Create parent tag for buffers. */
3037         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3038                 /*
3039                  * XXX
3040                  * watchdog timeout issue was observed on BCM5704 which
3041                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3042                  * Both limiting DMA address space to 32bits and flushing
3043                  * mailbox write seem to address the issue.
3044                  */
3045                 if (sc->bge_pcixcap != 0)
3046                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
3047         }
3048         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
3049             BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
3050             BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3051             &sc->bge_cdata.bge_buffer_tag);
3052         if (error != 0) {
3053                 device_printf(sc->bge_dev,
3054                     "could not allocate buffer dma tag\n");
3055                 return (ENOMEM);
3056         }
3057         /* Create tag for Tx mbufs. */
3058         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3059                 txsegsz = BGE_TSOSEG_SZ;
3060                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3061         } else {
3062                 txsegsz = MCLBYTES;
3063                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3064         }
3065         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3066             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3067             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3068             &sc->bge_cdata.bge_tx_mtag);
3069
3070         if (error) {
3071                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3072                 return (ENOMEM);
3073         }
3074
3075         /* Create tag for Rx mbufs. */
3076         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3077                 rxmaxsegsz = MJUM9BYTES;
3078         else
3079                 rxmaxsegsz = MCLBYTES;
3080         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3081             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3082             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3083
3084         if (error) {
3085                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3086                 return (ENOMEM);
3087         }
3088
3089         /* Create DMA maps for RX buffers. */
3090         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3091             &sc->bge_cdata.bge_rx_std_sparemap);
3092         if (error) {
3093                 device_printf(sc->bge_dev,
3094                     "can't create spare DMA map for RX\n");
3095                 return (ENOMEM);
3096         }
3097         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3098                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3099                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
3100                 if (error) {
3101                         device_printf(sc->bge_dev,
3102                             "can't create DMA map for RX\n");
3103                         return (ENOMEM);
3104                 }
3105         }
3106
3107         /* Create DMA maps for TX buffers. */
3108         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3109                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3110                             &sc->bge_cdata.bge_tx_dmamap[i]);
3111                 if (error) {
3112                         device_printf(sc->bge_dev,
3113                             "can't create DMA map for TX\n");
3114                         return (ENOMEM);
3115                 }
3116         }
3117
3118         /* Create tags for jumbo RX buffers. */
3119         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3120                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3121                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3122                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3123                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3124                 if (error) {
3125                         device_printf(sc->bge_dev,
3126                             "could not allocate jumbo dma tag\n");
3127                         return (ENOMEM);
3128                 }
3129                 /* Create DMA maps for jumbo RX buffers. */
3130                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3131                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3132                 if (error) {
3133                         device_printf(sc->bge_dev,
3134                             "can't create spare DMA map for jumbo RX\n");
3135                         return (ENOMEM);
3136                 }
3137                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3138                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3139                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3140                         if (error) {
3141                                 device_printf(sc->bge_dev,
3142                                     "can't create DMA map for jumbo RX\n");
3143                                 return (ENOMEM);
3144                         }
3145                 }
3146         }
3147
3148         return (0);
3149 }
3150
3151 /*
3152  * Return true if this device has more than one port.
3153  */
3154 static int
3155 bge_has_multiple_ports(struct bge_softc *sc)
3156 {
3157         device_t dev = sc->bge_dev;
3158         u_int b, d, f, fscan, s;
3159
3160         d = pci_get_domain(dev);
3161         b = pci_get_bus(dev);
3162         s = pci_get_slot(dev);
3163         f = pci_get_function(dev);
3164         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3165                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3166                         return (1);
3167         return (0);
3168 }
3169
3170 /*
3171  * Return true if MSI can be used with this device.
3172  */
3173 static int
3174 bge_can_use_msi(struct bge_softc *sc)
3175 {
3176         int can_use_msi = 0;
3177
3178         if (sc->bge_msi == 0)
3179                 return (0);
3180
3181         /* Disable MSI for polling(4). */
3182 #ifdef DEVICE_POLLING
3183         return (0);
3184 #endif
3185         switch (sc->bge_asicrev) {
3186         case BGE_ASICREV_BCM5714_A0:
3187         case BGE_ASICREV_BCM5714:
3188                 /*
3189                  * Apparently, MSI doesn't work when these chips are
3190                  * configured in single-port mode.
3191                  */
3192                 if (bge_has_multiple_ports(sc))
3193                         can_use_msi = 1;
3194                 break;
3195         case BGE_ASICREV_BCM5750:
3196                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3197                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3198                         can_use_msi = 1;
3199                 break;
3200         default:
3201                 if (BGE_IS_575X_PLUS(sc))
3202                         can_use_msi = 1;
3203         }
3204         return (can_use_msi);
3205 }
3206
3207 static int
3208 bge_mbox_reorder(struct bge_softc *sc)
3209 {
3210         /* Lists of PCI bridges that are known to reorder mailbox writes. */
3211         static const struct mbox_reorder {
3212                 const uint16_t vendor;
3213                 const uint16_t device;
3214                 const char *desc;
3215         } mbox_reorder_lists[] = {
3216                 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3217         };
3218         devclass_t pci, pcib;
3219         device_t bus, dev;
3220         int i;
3221
3222         pci = devclass_find("pci");
3223         pcib = devclass_find("pcib");
3224         dev = sc->bge_dev;
3225         bus = device_get_parent(dev);
3226         for (;;) {
3227                 dev = device_get_parent(bus);
3228                 bus = device_get_parent(dev);
3229                 if (device_get_devclass(dev) != pcib)
3230                         break;
3231                 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3232                         if (pci_get_vendor(dev) ==
3233                             mbox_reorder_lists[i].vendor &&
3234                             pci_get_device(dev) ==
3235                             mbox_reorder_lists[i].device) {
3236                                 device_printf(sc->bge_dev,
3237                                     "enabling MBOX workaround for %s\n",
3238                                     mbox_reorder_lists[i].desc);
3239                                 return (1);
3240                         }
3241                 }
3242                 if (device_get_devclass(bus) != pci)
3243                         break;
3244         }
3245         return (0);
3246 }
3247
3248 static void
3249 bge_devinfo(struct bge_softc *sc)
3250 {
3251         uint32_t cfg, clk;
3252
3253         device_printf(sc->bge_dev,
3254             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3255             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3256         if (sc->bge_flags & BGE_FLAG_PCIE)
3257                 printf("PCI-E\n");
3258         else if (sc->bge_flags & BGE_FLAG_PCIX) {
3259                 printf("PCI-X ");
3260                 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3261                 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3262                         clk = 133;
3263                 else {
3264                         clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3265                         switch (clk) {
3266                         case 0:
3267                                 clk = 33;
3268                                 break;
3269                         case 2:
3270                                 clk = 50;
3271                                 break;
3272                         case 4:
3273                                 clk = 66;
3274                                 break;
3275                         case 6:
3276                                 clk = 100;
3277                                 break;
3278                         case 7:
3279                                 clk = 133;
3280                                 break;
3281                         }
3282                 }
3283                 printf("%u MHz\n", clk);
3284         } else {
3285                 if (sc->bge_pcixcap != 0)
3286                         printf("PCI on PCI-X ");
3287                 else
3288                         printf("PCI ");
3289                 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3290                 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3291                         clk = 66;
3292                 else
3293                         clk = 33;
3294                 if (cfg & BGE_PCISTATE_32BIT_BUS)
3295                         printf("%u MHz; 32bit\n", clk);
3296                 else
3297                         printf("%u MHz; 64bit\n", clk);
3298         }
3299 }
3300
3301 static int
3302 bge_attach(device_t dev)
3303 {
3304         struct ifnet *ifp;
3305         struct bge_softc *sc;
3306         uint32_t hwcfg = 0, misccfg, pcistate;
3307         u_char eaddr[ETHER_ADDR_LEN];
3308         int capmask, error, reg, rid, trys;
3309
3310         sc = device_get_softc(dev);
3311         sc->bge_dev = dev;
3312
3313         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3314         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3315         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3316
3317         pci_enable_busmaster(dev);
3318
3319         /*
3320          * Allocate control/status registers.
3321          */
3322         rid = PCIR_BAR(0);
3323         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3324             RF_ACTIVE);
3325
3326         if (sc->bge_res == NULL) {
3327                 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3328                 error = ENXIO;
3329                 goto fail;
3330         }
3331
3332         /* Save various chip information. */
3333         sc->bge_func_addr = pci_get_function(dev);
3334         sc->bge_chipid = bge_chipid(dev);
3335         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3336         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3337
3338         /* Set default PHY address. */
3339         sc->bge_phy_addr = 1;
3340          /*
3341           * PHY address mapping for various devices.
3342           *
3343           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3344           * ---------+-------+-------+-------+-------+
3345           * BCM57XX  |   1   |   X   |   X   |   X   |
3346           * BCM5704  |   1   |   X   |   1   |   X   |
3347           * BCM5717  |   1   |   8   |   2   |   9   |
3348           * BCM5719  |   1   |   8   |   2   |   9   |
3349           * BCM5720  |   1   |   8   |   2   |   9   |
3350           *
3351           *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3352           * ---------+-------+-------+-------+-------+
3353           * BCM57XX  |   X   |   X   |   X   |   X   |
3354           * BCM5704  |   X   |   X   |   X   |   X   |
3355           * BCM5717  |   X   |   X   |   X   |   X   |
3356           * BCM5719  |   3   |   10  |   4   |   11  |
3357           * BCM5720  |   X   |   X   |   X   |   X   |
3358           *
3359           * Other addresses may respond but they are not
3360           * IEEE compliant PHYs and should be ignored.
3361           */
3362         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3363             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3364             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3365                 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3366                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3367                             BGE_SGDIGSTS_IS_SERDES)
3368                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3369                         else
3370                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3371                 } else {
3372                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3373                             BGE_CPMU_PHY_STRAP_IS_SERDES)
3374                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3375                         else
3376                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3377                 }
3378         }
3379
3380         if (bge_has_eaddr(sc))
3381                 sc->bge_flags |= BGE_FLAG_EADDR;
3382
3383         /* Save chipset family. */
3384         switch (sc->bge_asicrev) {
3385         case BGE_ASICREV_BCM5762:
3386         case BGE_ASICREV_BCM57765:
3387         case BGE_ASICREV_BCM57766:
3388                 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3389                 /* FALLTHROUGH */
3390         case BGE_ASICREV_BCM5717:
3391         case BGE_ASICREV_BCM5719:
3392         case BGE_ASICREV_BCM5720:
3393                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3394                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3395                     BGE_FLAG_JUMBO_FRAME;
3396                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3397                     sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3398                         /*
3399                          * Enable work around for DMA engine miscalculation
3400                          * of TXMBUF available space.
3401                          */
3402                         sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3403                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3404                             sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3405                                 /* Jumbo frame on BCM5719 A0 does not work. */
3406                                 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3407                         }
3408                 }
3409                 break;
3410         case BGE_ASICREV_BCM5755:
3411         case BGE_ASICREV_BCM5761:
3412         case BGE_ASICREV_BCM5784:
3413         case BGE_ASICREV_BCM5785:
3414         case BGE_ASICREV_BCM5787:
3415         case BGE_ASICREV_BCM57780:
3416                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3417                     BGE_FLAG_5705_PLUS;
3418                 break;
3419         case BGE_ASICREV_BCM5700:
3420         case BGE_ASICREV_BCM5701:
3421         case BGE_ASICREV_BCM5703:
3422         case BGE_ASICREV_BCM5704:
3423                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3424                 break;
3425         case BGE_ASICREV_BCM5714_A0:
3426         case BGE_ASICREV_BCM5780:
3427         case BGE_ASICREV_BCM5714:
3428                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3429                 /* FALLTHROUGH */
3430         case BGE_ASICREV_BCM5750:
3431         case BGE_ASICREV_BCM5752:
3432         case BGE_ASICREV_BCM5906:
3433                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3434                 /* FALLTHROUGH */
3435         case BGE_ASICREV_BCM5705:
3436                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3437                 break;
3438         }
3439
3440         /* Identify chips with APE processor. */
3441         switch (sc->bge_asicrev) {
3442         case BGE_ASICREV_BCM5717:
3443         case BGE_ASICREV_BCM5719:
3444         case BGE_ASICREV_BCM5720:
3445         case BGE_ASICREV_BCM5761:
3446         case BGE_ASICREV_BCM5762:
3447                 sc->bge_flags |= BGE_FLAG_APE;
3448                 break;
3449         }
3450
3451         /* Chips with APE need BAR2 access for APE registers/memory. */
3452         if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3453                 rid = PCIR_BAR(2);
3454                 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3455                     RF_ACTIVE);
3456                 if (sc->bge_res2 == NULL) {
3457                         device_printf (sc->bge_dev,
3458                             "couldn't map BAR2 memory\n");
3459                         error = ENXIO;
3460                         goto fail;
3461                 }
3462
3463                 /* Enable APE register/memory access by host driver. */
3464                 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3465                 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3466                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3467                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3468                 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3469
3470                 bge_ape_lock_init(sc);
3471                 bge_ape_read_fw_ver(sc);
3472         }
3473
3474         /* Add SYSCTLs, requires the chipset family to be set. */
3475         bge_add_sysctls(sc);
3476
3477         /* Identify the chips that use an CPMU. */
3478         if (BGE_IS_5717_PLUS(sc) ||
3479             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3480             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3481             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3482             sc->bge_asicrev == BGE_ASICREV_BCM57780)
3483                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3484         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3485                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3486         else
3487                 sc->bge_mi_mode = BGE_MIMODE_BASE;
3488         /* Enable auto polling for BCM570[0-5]. */
3489         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3490                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3491
3492         /*
3493          * All Broadcom controllers have 4GB boundary DMA bug.
3494          * Whenever an address crosses a multiple of the 4GB boundary
3495          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3496          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3497          * state machine will lockup and cause the device to hang.
3498          */
3499         sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3500
3501         /* BCM5755 or higher and BCM5906 have short DMA bug. */
3502         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3503                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3504
3505         /*
3506          * BCM5719 cannot handle DMA requests for DMA segments that
3507          * have larger than 4KB in size.  However the maximum DMA
3508          * segment size created in DMA tag is 4KB for TSO, so we
3509          * wouldn't encounter the issue here.
3510          */
3511         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3512                 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3513
3514         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3515         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3516                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3517                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3518                         sc->bge_flags |= BGE_FLAG_5788;
3519         }
3520
3521         capmask = BMSR_DEFCAPMASK;
3522         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3523             (misccfg == 0x4000 || misccfg == 0x8000)) ||
3524             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3525             pci_get_vendor(dev) == BCOM_VENDORID &&
3526             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3527             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3528             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3529             (pci_get_vendor(dev) == BCOM_VENDORID &&
3530             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3531             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3532             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3533             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3534             pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3535             pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3536             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3537                 /* These chips are 10/100 only. */
3538                 capmask &= ~BMSR_EXTSTAT;
3539                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3540         }
3541
3542         /*
3543          * Some controllers seem to require a special firmware to use
3544          * TSO. But the firmware is not available to FreeBSD and Linux
3545          * claims that the TSO performed by the firmware is slower than
3546          * hardware based TSO. Moreover the firmware based TSO has one
3547          * known bug which can't handle TSO if Ethernet header + IP/TCP
3548          * header is greater than 80 bytes. A workaround for the TSO
3549          * bug exist but it seems it's too expensive than not using
3550          * TSO at all. Some hardwares also have the TSO bug so limit
3551          * the TSO to the controllers that are not affected TSO issues
3552          * (e.g. 5755 or higher).
3553          */
3554         if (BGE_IS_5717_PLUS(sc)) {
3555                 /* BCM5717 requires different TSO configuration. */
3556                 sc->bge_flags |= BGE_FLAG_TSO3;
3557                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3558                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3559                         /* TSO on BCM5719 A0 does not work. */
3560                         sc->bge_flags &= ~BGE_FLAG_TSO3;
3561                 }
3562         } else if (BGE_IS_5755_PLUS(sc)) {
3563                 /*
3564                  * BCM5754 and BCM5787 shares the same ASIC id so
3565                  * explicit device id check is required.
3566                  * Due to unknown reason TSO does not work on BCM5755M.
3567                  */
3568                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3569                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3570                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3571                         sc->bge_flags |= BGE_FLAG_TSO;
3572         }
3573
3574         /*
3575          * Check if this is a PCI-X or PCI Express device.
3576          */
3577         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3578                 /*
3579                  * Found a PCI Express capabilities register, this
3580                  * must be a PCI Express device.
3581                  */
3582                 sc->bge_flags |= BGE_FLAG_PCIE;
3583                 sc->bge_expcap = reg;
3584                 /* Extract supported maximum payload size. */
3585                 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3586                     PCIER_DEVICE_CAP, 2);
3587                 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3588                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3589                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
3590                         sc->bge_expmrq = 2048;
3591                 else
3592                         sc->bge_expmrq = 4096;
3593                 pci_set_max_read_req(dev, sc->bge_expmrq);
3594         } else {
3595                 /*
3596                  * Check if the device is in PCI-X Mode.
3597                  * (This bit is not valid on PCI Express controllers.)
3598                  */
3599                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3600                         sc->bge_pcixcap = reg;
3601                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3602                     BGE_PCISTATE_PCI_BUSMODE) == 0)
3603                         sc->bge_flags |= BGE_FLAG_PCIX;
3604         }
3605
3606         /*
3607          * The 40bit DMA bug applies to the 5714/5715 controllers and is
3608          * not actually a MAC controller bug but an issue with the embedded
3609          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3610          */
3611         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3612                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3613         /*
3614          * Some PCI-X bridges are known to trigger write reordering to
3615          * the mailbox registers. Typical phenomena is watchdog timeouts
3616          * caused by out-of-order TX completions.  Enable workaround for
3617          * PCI-X devices that live behind these bridges.
3618          * Note, PCI-X controllers can run in PCI mode so we can't use
3619          * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3620          */
3621         if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3622                 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3623         /*
3624          * Allocate the interrupt, using MSI if possible.  These devices
3625          * support 8 MSI messages, but only the first one is used in
3626          * normal operation.
3627          */
3628         rid = 0;
3629         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3630                 sc->bge_msicap = reg;
3631                 reg = 1;
3632                 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, &reg) == 0) {
3633                         rid = 1;
3634                         sc->bge_flags |= BGE_FLAG_MSI;
3635                 }
3636         }
3637
3638         /*
3639          * All controllers except BCM5700 supports tagged status but
3640          * we use tagged status only for MSI case on BCM5717. Otherwise
3641          * MSI on BCM5717 does not work.
3642          */
3643 #ifndef DEVICE_POLLING
3644         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3645                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3646 #endif
3647
3648         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3649             RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3650
3651         if (sc->bge_irq == NULL) {
3652                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3653                 error = ENXIO;
3654                 goto fail;
3655         }
3656
3657         bge_devinfo(sc);
3658
3659         sc->bge_asf_mode = 0;
3660         /* No ASF if APE present. */
3661         if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3662                 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3663                     BGE_SRAM_DATA_SIG_MAGIC)) {
3664                         if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3665                             BGE_HWCFG_ASF) {
3666                                 sc->bge_asf_mode |= ASF_ENABLE;
3667                                 sc->bge_asf_mode |= ASF_STACKUP;
3668                                 if (BGE_IS_575X_PLUS(sc))
3669                                         sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3670                         }
3671                 }
3672         }
3673
3674         bge_stop_fw(sc);
3675         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3676         if (bge_reset(sc)) {
3677                 device_printf(sc->bge_dev, "chip reset failed\n");
3678                 error = ENXIO;
3679                 goto fail;
3680         }
3681
3682         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3683         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3684
3685         if (bge_chipinit(sc)) {
3686                 device_printf(sc->bge_dev, "chip initialization failed\n");
3687                 error = ENXIO;
3688                 goto fail;
3689         }
3690
3691         error = bge_get_eaddr(sc, eaddr);
3692         if (error) {
3693                 device_printf(sc->bge_dev,
3694                     "failed to read station address\n");
3695                 error = ENXIO;
3696                 goto fail;
3697         }
3698
3699         /* 5705 limits RX return ring to 512 entries. */
3700         if (BGE_IS_5717_PLUS(sc))
3701                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3702         else if (BGE_IS_5705_PLUS(sc))
3703                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3704         else
3705                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3706
3707         if (bge_dma_alloc(sc)) {
3708                 device_printf(sc->bge_dev,
3709                     "failed to allocate DMA resources\n");
3710                 error = ENXIO;
3711                 goto fail;
3712         }
3713
3714         /* Set default tuneable values. */
3715         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3716         sc->bge_rx_coal_ticks = 150;
3717         sc->bge_tx_coal_ticks = 150;
3718         sc->bge_rx_max_coal_bds = 10;
3719         sc->bge_tx_max_coal_bds = 10;
3720
3721         /* Initialize checksum features to use. */
3722         sc->bge_csum_features = BGE_CSUM_FEATURES;
3723         if (sc->bge_forced_udpcsum != 0)
3724                 sc->bge_csum_features |= CSUM_UDP;
3725
3726         /* Set up ifnet structure */
3727         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3728         if (ifp == NULL) {
3729                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3730                 error = ENXIO;
3731                 goto fail;
3732         }
3733         ifp->if_softc = sc;
3734         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3735         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3736         ifp->if_ioctl = bge_ioctl;
3737         ifp->if_start = bge_start;
3738         ifp->if_init = bge_init;
3739         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3740         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3741         IFQ_SET_READY(&ifp->if_snd);
3742         ifp->if_hwassist = sc->bge_csum_features;
3743         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3744             IFCAP_VLAN_MTU;
3745         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3746                 ifp->if_hwassist |= CSUM_TSO;
3747                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3748         }
3749 #ifdef IFCAP_VLAN_HWCSUM
3750         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3751 #endif
3752         ifp->if_capenable = ifp->if_capabilities;
3753 #ifdef DEVICE_POLLING
3754         ifp->if_capabilities |= IFCAP_POLLING;
3755 #endif
3756
3757         /*
3758          * 5700 B0 chips do not support checksumming correctly due
3759          * to hardware bugs.
3760          */
3761         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3762                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3763                 ifp->if_capenable &= ~IFCAP_HWCSUM;
3764                 ifp->if_hwassist = 0;
3765         }
3766
3767         /*
3768          * Figure out what sort of media we have by checking the
3769          * hardware config word in the first 32k of NIC internal memory,
3770          * or fall back to examining the EEPROM if necessary.
3771          * Note: on some BCM5700 cards, this value appears to be unset.
3772          * If that's the case, we have to rely on identifying the NIC
3773          * by its PCI subsystem ID, as we do below for the SysKonnect
3774          * SK-9D41.
3775          */
3776         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3777                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3778         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3779             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3780                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3781                     sizeof(hwcfg))) {
3782                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
3783                         error = ENXIO;
3784                         goto fail;
3785                 }
3786                 hwcfg = ntohl(hwcfg);
3787         }
3788
3789         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3790         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3791             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3792                 if (BGE_IS_5705_PLUS(sc)) {
3793                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
3794                         sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3795                 } else
3796                         sc->bge_flags |= BGE_FLAG_TBI;
3797         }
3798
3799         /* Set various PHY bug flags. */
3800         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3801             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3802                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3803         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3804             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3805                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3806         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3807                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3808         if (pci_get_subvendor(dev) == DELL_VENDORID)
3809                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3810         if ((BGE_IS_5705_PLUS(sc)) &&
3811             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3812             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3813             sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3814             !BGE_IS_5717_PLUS(sc)) {
3815                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3816                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3817                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3818                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3819                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3820                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3821                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3822                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3823                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3824                 } else
3825                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3826         }
3827
3828         /*
3829          * Don't enable Ethernet@WireSpeed for the 5700 or the
3830          * 5705 A0 and A1 chips.
3831          */
3832         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3833             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3834             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3835             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3836                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3837
3838         if (sc->bge_flags & BGE_FLAG_TBI) {
3839                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3840                     bge_ifmedia_sts);
3841                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3842                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3843                     0, NULL);
3844                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3845                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3846                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3847         } else {
3848                 /*
3849                  * Do transceiver setup and tell the firmware the
3850                  * driver is down so we can try to get access the
3851                  * probe if ASF is running.  Retry a couple of times
3852                  * if we get a conflict with the ASF firmware accessing
3853                  * the PHY.
3854                  */
3855                 trys = 0;
3856                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3857 again:
3858                 bge_asf_driver_up(sc);
3859
3860                 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3861                     bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY,
3862                     MIIF_DOPAUSE);
3863                 if (error != 0) {
3864                         if (trys++ < 4) {
3865                                 device_printf(sc->bge_dev, "Try again\n");
3866                                 bge_miibus_writereg(sc->bge_dev,
3867                                     sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3868                                 goto again;
3869                         }
3870                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
3871                         goto fail;
3872                 }
3873
3874                 /*
3875                  * Now tell the firmware we are going up after probing the PHY
3876                  */
3877                 if (sc->bge_asf_mode & ASF_STACKUP)
3878                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3879         }
3880
3881         /*
3882          * When using the BCM5701 in PCI-X mode, data corruption has
3883          * been observed in the first few bytes of some received packets.
3884          * Aligning the packet buffer in memory eliminates the corruption.
3885          * Unfortunately, this misaligns the packet payloads.  On platforms
3886          * which do not support unaligned accesses, we will realign the
3887          * payloads by copying the received packets.
3888          */
3889         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3890             sc->bge_flags & BGE_FLAG_PCIX)
3891                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3892
3893         /*
3894          * Call MI attach routine.
3895          */
3896         ether_ifattach(ifp, eaddr);
3897
3898         /* Tell upper layer we support long frames. */
3899         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3900
3901         /*
3902          * Hookup IRQ last.
3903          */
3904         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3905                 /* Take advantage of single-shot MSI. */
3906                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3907                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3908                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3909                     taskqueue_thread_enqueue, &sc->bge_tq);
3910                 if (sc->bge_tq == NULL) {
3911                         device_printf(dev, "could not create taskqueue.\n");
3912                         ether_ifdetach(ifp);
3913                         error = ENOMEM;
3914                         goto fail;
3915                 }
3916                 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3917                     "%s taskq", device_get_nameunit(sc->bge_dev));
3918                 if (error != 0) {
3919                         device_printf(dev, "could not start threads.\n");
3920                         ether_ifdetach(ifp);
3921                         goto fail;
3922                 }
3923                 error = bus_setup_intr(dev, sc->bge_irq,
3924                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3925                     &sc->bge_intrhand);
3926         } else
3927                 error = bus_setup_intr(dev, sc->bge_irq,
3928                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3929                     &sc->bge_intrhand);
3930
3931         if (error) {
3932                 ether_ifdetach(ifp);
3933                 device_printf(sc->bge_dev, "couldn't set up irq\n");
3934         }
3935
3936 fail:
3937         if (error)
3938                 bge_detach(dev);
3939         return (error);
3940 }
3941
3942 static int
3943 bge_detach(device_t dev)
3944 {
3945         struct bge_softc *sc;
3946         struct ifnet *ifp;
3947
3948         sc = device_get_softc(dev);
3949         ifp = sc->bge_ifp;
3950
3951 #ifdef DEVICE_POLLING
3952         if (ifp->if_capenable & IFCAP_POLLING)
3953                 ether_poll_deregister(ifp);
3954 #endif
3955
3956         if (device_is_attached(dev)) {
3957                 ether_ifdetach(ifp);
3958                 BGE_LOCK(sc);
3959                 bge_stop(sc);
3960                 BGE_UNLOCK(sc);
3961                 callout_drain(&sc->bge_stat_ch);
3962         }
3963
3964         if (sc->bge_tq)
3965                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3966
3967         if (sc->bge_flags & BGE_FLAG_TBI)
3968                 ifmedia_removeall(&sc->bge_ifmedia);
3969         else if (sc->bge_miibus != NULL) {
3970                 bus_generic_detach(dev);
3971                 device_delete_child(dev, sc->bge_miibus);
3972         }
3973
3974         bge_release_resources(sc);
3975
3976         return (0);
3977 }
3978
3979 static void
3980 bge_release_resources(struct bge_softc *sc)
3981 {
3982         device_t dev;
3983
3984         dev = sc->bge_dev;
3985
3986         if (sc->bge_tq != NULL)
3987                 taskqueue_free(sc->bge_tq);
3988
3989         if (sc->bge_intrhand != NULL)
3990                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3991
3992         if (sc->bge_irq != NULL) {
3993                 bus_release_resource(dev, SYS_RES_IRQ,
3994                     rman_get_rid(sc->bge_irq), sc->bge_irq);
3995                 pci_release_msi(dev);
3996         }
3997
3998         if (sc->bge_res != NULL)
3999                 bus_release_resource(dev, SYS_RES_MEMORY,
4000                     rman_get_rid(sc->bge_res), sc->bge_res);
4001
4002         if (sc->bge_res2 != NULL)
4003                 bus_release_resource(dev, SYS_RES_MEMORY,
4004                     rman_get_rid(sc->bge_res2), sc->bge_res2);
4005
4006         if (sc->bge_ifp != NULL)
4007                 if_free(sc->bge_ifp);
4008
4009         bge_dma_free(sc);
4010
4011         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
4012                 BGE_LOCK_DESTROY(sc);
4013 }
4014
4015 static int
4016 bge_reset(struct bge_softc *sc)
4017 {
4018         device_t dev;
4019         uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4020         void (*write_op)(struct bge_softc *, int, int);
4021         uint16_t devctl;
4022         int i;
4023
4024         dev = sc->bge_dev;
4025
4026         mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4027         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4028                 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4029         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4030
4031         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4032             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4033                 if (sc->bge_flags & BGE_FLAG_PCIE)
4034                         write_op = bge_writemem_direct;
4035                 else
4036                         write_op = bge_writemem_ind;
4037         } else
4038                 write_op = bge_writereg_ind;
4039
4040         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4041             sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4042                 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4043                 for (i = 0; i < 8000; i++) {
4044                         if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4045                             BGE_NVRAMSWARB_GNT1)
4046                                 break;
4047                         DELAY(20);
4048                 }
4049                 if (i == 8000) {
4050                         if (bootverbose)
4051                                 device_printf(dev, "NVRAM lock timedout!\n");
4052                 }
4053         }
4054         /* Take APE lock when performing reset. */
4055         bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4056
4057         /* Save some important PCI state. */
4058         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4059         command = pci_read_config(dev, BGE_PCI_CMD, 4);
4060
4061         pci_write_config(dev, BGE_PCI_MISC_CTL,
4062             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4063             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4064
4065         /* Disable fastboot on controllers that support it. */
4066         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4067             BGE_IS_5755_PLUS(sc)) {
4068                 if (bootverbose)
4069                         device_printf(dev, "Disabling fastboot\n");
4070                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4071         }
4072
4073         /*
4074          * Write the magic number to SRAM at offset 0xB50.
4075          * When firmware finishes its initialization it will
4076          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4077          */
4078         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4079
4080         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4081
4082         /* XXX: Broadcom Linux driver. */
4083         if (sc->bge_flags & BGE_FLAG_PCIE) {
4084                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4085                     (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4086                         if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
4087                                 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4088                 }
4089                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4090                         /* Prevent PCIE link training during global reset */
4091                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4092                         reset |= 1 << 29;
4093                 }
4094         }
4095
4096         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4097                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4098                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4099                     val | BGE_VCPU_STATUS_DRV_RESET);
4100                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4101                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4102                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4103         }
4104
4105         /*
4106          * Set GPHY Power Down Override to leave GPHY
4107          * powered up in D0 uninitialized.
4108          */
4109         if (BGE_IS_5705_PLUS(sc) &&
4110             (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4111                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4112
4113         /* Issue global reset */
4114         write_op(sc, BGE_MISC_CFG, reset);
4115
4116         if (sc->bge_flags & BGE_FLAG_PCIE)
4117                 DELAY(100 * 1000);
4118         else
4119                 DELAY(1000);
4120
4121         /* XXX: Broadcom Linux driver. */
4122         if (sc->bge_flags & BGE_FLAG_PCIE) {
4123                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4124                         DELAY(500000); /* wait for link training to complete */
4125                         val = pci_read_config(dev, 0xC4, 4);
4126                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4127                 }
4128                 devctl = pci_read_config(dev,
4129                     sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4130                 /* Clear enable no snoop and disable relaxed ordering. */
4131                 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4132                     PCIEM_CTL_NOSNOOP_ENABLE);
4133                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4134                     devctl, 2);
4135                 pci_set_max_read_req(dev, sc->bge_expmrq);
4136                 /* Clear error status. */
4137                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4138                     PCIEM_STA_CORRECTABLE_ERROR |
4139                     PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4140                     PCIEM_STA_UNSUPPORTED_REQ, 2);
4141         }
4142
4143         /* Reset some of the PCI state that got zapped by reset. */
4144         pci_write_config(dev, BGE_PCI_MISC_CTL,
4145             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4146             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4147         val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4148         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4149             (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4150                 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4151         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4152                 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4153                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4154                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4155         pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4156         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4157         pci_write_config(dev, BGE_PCI_CMD, command, 4);
4158         /*
4159          * Disable PCI-X relaxed ordering to ensure status block update
4160          * comes first then packet buffer DMA. Otherwise driver may
4161          * read stale status block.
4162          */
4163         if (sc->bge_flags & BGE_FLAG_PCIX) {
4164                 devctl = pci_read_config(dev,
4165                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
4166                 devctl &= ~PCIXM_COMMAND_ERO;
4167                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4168                         devctl &= ~PCIXM_COMMAND_MAX_READ;
4169                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4170                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4171                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4172                             PCIXM_COMMAND_MAX_READ);
4173                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4174                 }
4175                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4176                     devctl, 2);
4177         }
4178         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4179         if (BGE_IS_5714_FAMILY(sc)) {
4180                 /* This chip disables MSI on reset. */
4181                 if (sc->bge_flags & BGE_FLAG_MSI) {
4182                         val = pci_read_config(dev,
4183                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
4184                         pci_write_config(dev,
4185                             sc->bge_msicap + PCIR_MSI_CTRL,
4186                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
4187                         val = CSR_READ_4(sc, BGE_MSI_MODE);
4188                         CSR_WRITE_4(sc, BGE_MSI_MODE,
4189                             val | BGE_MSIMODE_ENABLE);
4190                 }
4191                 val = CSR_READ_4(sc, BGE_MARB_MODE);
4192                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4193         } else
4194                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4195
4196         /* Fix up byte swapping. */
4197         CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4198
4199         val = CSR_READ_4(sc, BGE_MAC_MODE);
4200         val = (val & ~mac_mode_mask) | mac_mode;
4201         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4202         DELAY(40);
4203
4204         bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4205
4206         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4207                 for (i = 0; i < BGE_TIMEOUT; i++) {
4208                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4209                         if (val & BGE_VCPU_STATUS_INIT_DONE)
4210                                 break;
4211                         DELAY(100);
4212                 }
4213                 if (i == BGE_TIMEOUT) {
4214                         device_printf(dev, "reset timed out\n");
4215                         return (1);
4216                 }
4217         } else {
4218                 /*
4219                  * Poll until we see the 1's complement of the magic number.
4220                  * This indicates that the firmware initialization is complete.
4221                  * We expect this to fail if no chip containing the Ethernet
4222                  * address is fitted though.
4223                  */
4224                 for (i = 0; i < BGE_TIMEOUT; i++) {
4225                         DELAY(10);
4226                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4227                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
4228                                 break;
4229                 }
4230
4231                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4232                         device_printf(dev,
4233                             "firmware handshake timed out, found 0x%08x\n",
4234                             val);
4235                 /* BCM57765 A0 needs additional time before accessing. */
4236                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4237                         DELAY(10 * 1000);       /* XXX */
4238         }
4239
4240         /*
4241          * The 5704 in TBI mode apparently needs some special
4242          * adjustment to insure the SERDES drive level is set
4243          * to 1.2V.
4244          */
4245         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4246             sc->bge_flags & BGE_FLAG_TBI) {
4247                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4248                 val = (val & ~0xFFF) | 0x880;
4249                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4250         }
4251
4252         /* XXX: Broadcom Linux driver. */
4253         if (sc->bge_flags & BGE_FLAG_PCIE &&
4254             !BGE_IS_5717_PLUS(sc) &&
4255             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4256             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4257                 /* Enable Data FIFO protection. */
4258                 val = CSR_READ_4(sc, 0x7C00);
4259                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4260         }
4261
4262         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4263                 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4264                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4265
4266         return (0);
4267 }
4268
4269 static __inline void
4270 bge_rxreuse_std(struct bge_softc *sc, int i)
4271 {
4272         struct bge_rx_bd *r;
4273
4274         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4275         r->bge_flags = BGE_RXBDFLAG_END;
4276         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4277         r->bge_idx = i;
4278         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4279 }
4280
4281 static __inline void
4282 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4283 {
4284         struct bge_extrx_bd *r;
4285
4286         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4287         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4288         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4289         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4290         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4291         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4292         r->bge_idx = i;
4293         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4294 }
4295
4296 /*
4297  * Frame reception handling. This is called if there's a frame
4298  * on the receive return list.
4299  *
4300  * Note: we have to be able to handle two possibilities here:
4301  * 1) the frame is from the jumbo receive ring
4302  * 2) the frame is from the standard receive ring
4303  */
4304
4305 static int
4306 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4307 {
4308         struct ifnet *ifp;
4309         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4310         uint16_t rx_cons;
4311
4312         rx_cons = sc->bge_rx_saved_considx;
4313
4314         /* Nothing to do. */
4315         if (rx_cons == rx_prod)
4316                 return (rx_npkts);
4317
4318         ifp = sc->bge_ifp;
4319
4320         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4321             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4322         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4323             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4324         if (BGE_IS_JUMBO_CAPABLE(sc) &&
4325             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4326             (MCLBYTES - ETHER_ALIGN))
4327                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4328                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4329
4330         while (rx_cons != rx_prod) {
4331                 struct bge_rx_bd        *cur_rx;
4332                 uint32_t                rxidx;
4333                 struct mbuf             *m = NULL;
4334                 uint16_t                vlan_tag = 0;
4335                 int                     have_tag = 0;
4336
4337 #ifdef DEVICE_POLLING
4338                 if (ifp->if_capenable & IFCAP_POLLING) {
4339                         if (sc->rxcycles <= 0)
4340                                 break;
4341                         sc->rxcycles--;
4342                 }
4343 #endif
4344
4345                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4346
4347                 rxidx = cur_rx->bge_idx;
4348                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4349
4350                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
4351                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4352                         have_tag = 1;
4353                         vlan_tag = cur_rx->bge_vlan_tag;
4354                 }
4355
4356                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4357                         jumbocnt++;
4358                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4359                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4360                                 bge_rxreuse_jumbo(sc, rxidx);
4361                                 continue;
4362                         }
4363                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4364                                 bge_rxreuse_jumbo(sc, rxidx);
4365                                 ifp->if_iqdrops++;
4366                                 continue;
4367                         }
4368                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4369                 } else {
4370                         stdcnt++;
4371                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4372                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4373                                 bge_rxreuse_std(sc, rxidx);
4374                                 continue;
4375                         }
4376                         if (bge_newbuf_std(sc, rxidx) != 0) {
4377                                 bge_rxreuse_std(sc, rxidx);
4378                                 ifp->if_iqdrops++;
4379                                 continue;
4380                         }
4381                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4382                 }
4383
4384                 ifp->if_ipackets++;
4385 #ifndef __NO_STRICT_ALIGNMENT
4386                 /*
4387                  * For architectures with strict alignment we must make sure
4388                  * the payload is aligned.
4389                  */
4390                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4391                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4392                             cur_rx->bge_len);
4393                         m->m_data += ETHER_ALIGN;
4394                 }
4395 #endif
4396                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4397                 m->m_pkthdr.rcvif = ifp;
4398
4399                 if (ifp->if_capenable & IFCAP_RXCSUM)
4400                         bge_rxcsum(sc, cur_rx, m);
4401
4402                 /*
4403                  * If we received a packet with a vlan tag,
4404                  * attach that information to the packet.
4405                  */
4406                 if (have_tag) {
4407                         m->m_pkthdr.ether_vtag = vlan_tag;
4408                         m->m_flags |= M_VLANTAG;
4409                 }
4410
4411                 if (holdlck != 0) {
4412                         BGE_UNLOCK(sc);
4413                         (*ifp->if_input)(ifp, m);
4414                         BGE_LOCK(sc);
4415                 } else
4416                         (*ifp->if_input)(ifp, m);
4417                 rx_npkts++;
4418
4419                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
4420                         return (rx_npkts);
4421         }
4422
4423         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4424             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4425         if (stdcnt > 0)
4426                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4427                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4428
4429         if (jumbocnt > 0)
4430                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4431                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4432
4433         sc->bge_rx_saved_considx = rx_cons;
4434         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4435         if (stdcnt)
4436                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4437                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4438         if (jumbocnt)
4439                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4440                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4441 #ifdef notyet
4442         /*
4443          * This register wraps very quickly under heavy packet drops.
4444          * If you need correct statistics, you can enable this check.
4445          */
4446         if (BGE_IS_5705_PLUS(sc))
4447                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4448 #endif
4449         return (rx_npkts);
4450 }
4451
4452 static void
4453 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4454 {
4455
4456         if (BGE_IS_5717_PLUS(sc)) {
4457                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4458                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4459                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4460                                 if ((cur_rx->bge_error_flag &
4461                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4462                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4463                         }
4464                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4465                                 m->m_pkthdr.csum_data =
4466                                     cur_rx->bge_tcp_udp_csum;
4467                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4468                                     CSUM_PSEUDO_HDR;
4469                         }
4470                 }
4471         } else {
4472                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4473                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4474                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4475                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4476                 }
4477                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4478                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4479                         m->m_pkthdr.csum_data =
4480                             cur_rx->bge_tcp_udp_csum;
4481                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4482                             CSUM_PSEUDO_HDR;
4483                 }
4484         }
4485 }
4486
4487 static void
4488 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4489 {
4490         struct bge_tx_bd *cur_tx;
4491         struct ifnet *ifp;
4492
4493         BGE_LOCK_ASSERT(sc);
4494
4495         /* Nothing to do. */
4496         if (sc->bge_tx_saved_considx == tx_cons)
4497                 return;
4498
4499         ifp = sc->bge_ifp;
4500
4501         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4502             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4503         /*
4504          * Go through our tx ring and free mbufs for those
4505          * frames that have been sent.
4506          */
4507         while (sc->bge_tx_saved_considx != tx_cons) {
4508                 uint32_t                idx;
4509
4510                 idx = sc->bge_tx_saved_considx;
4511                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4512                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4513                         ifp->if_opackets++;
4514                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4515                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4516                             sc->bge_cdata.bge_tx_dmamap[idx],
4517                             BUS_DMASYNC_POSTWRITE);
4518                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4519                             sc->bge_cdata.bge_tx_dmamap[idx]);
4520                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4521                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
4522                 }
4523                 sc->bge_txcnt--;
4524                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4525         }
4526
4527         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4528         if (sc->bge_txcnt == 0)
4529                 sc->bge_timer = 0;
4530 }
4531
4532 #ifdef DEVICE_POLLING
4533 static int
4534 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4535 {
4536         struct bge_softc *sc = ifp->if_softc;
4537         uint16_t rx_prod, tx_cons;
4538         uint32_t statusword;
4539         int rx_npkts = 0;
4540
4541         BGE_LOCK(sc);
4542         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4543                 BGE_UNLOCK(sc);
4544                 return (rx_npkts);
4545         }
4546
4547         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4548             sc->bge_cdata.bge_status_map,
4549             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4550         /* Fetch updates from the status block. */
4551         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4552         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4553
4554         statusword = sc->bge_ldata.bge_status_block->bge_status;
4555         /* Clear the status so the next pass only sees the changes. */
4556         sc->bge_ldata.bge_status_block->bge_status = 0;
4557
4558         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4559             sc->bge_cdata.bge_status_map,
4560             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4561
4562         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4563         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4564                 sc->bge_link_evt++;
4565
4566         if (cmd == POLL_AND_CHECK_STATUS)
4567                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4568                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4569                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4570                         bge_link_upd(sc);
4571
4572         sc->rxcycles = count;
4573         rx_npkts = bge_rxeof(sc, rx_prod, 1);
4574         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4575                 BGE_UNLOCK(sc);
4576                 return (rx_npkts);
4577         }
4578         bge_txeof(sc, tx_cons);
4579         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4580                 bge_start_locked(ifp);
4581
4582         BGE_UNLOCK(sc);
4583         return (rx_npkts);
4584 }
4585 #endif /* DEVICE_POLLING */
4586
4587 static int
4588 bge_msi_intr(void *arg)
4589 {
4590         struct bge_softc *sc;
4591
4592         sc = (struct bge_softc *)arg;
4593         /*
4594          * This interrupt is not shared and controller already
4595          * disabled further interrupt.
4596          */
4597         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4598         return (FILTER_HANDLED);
4599 }
4600
4601 static void
4602 bge_intr_task(void *arg, int pending)
4603 {
4604         struct bge_softc *sc;
4605         struct ifnet *ifp;
4606         uint32_t status, status_tag;
4607         uint16_t rx_prod, tx_cons;
4608
4609         sc = (struct bge_softc *)arg;
4610         ifp = sc->bge_ifp;
4611
4612         BGE_LOCK(sc);
4613         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4614                 BGE_UNLOCK(sc);
4615                 return;
4616         }
4617
4618         /* Get updated status block. */
4619         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4620             sc->bge_cdata.bge_status_map,
4621             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4622
4623         /* Save producer/consumer indices. */
4624         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4625         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4626         status = sc->bge_ldata.bge_status_block->bge_status;
4627         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4628         /* Dirty the status flag. */
4629         sc->bge_ldata.bge_status_block->bge_status = 0;
4630         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4631             sc->bge_cdata.bge_status_map,
4632             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4633         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4634                 status_tag = 0;
4635
4636         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4637                 bge_link_upd(sc);
4638
4639         /* Let controller work. */
4640         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4641
4642         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4643             sc->bge_rx_saved_considx != rx_prod) {
4644                 /* Check RX return ring producer/consumer. */
4645                 BGE_UNLOCK(sc);
4646                 bge_rxeof(sc, rx_prod, 0);
4647                 BGE_LOCK(sc);
4648         }
4649         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4650                 /* Check TX ring producer/consumer. */
4651                 bge_txeof(sc, tx_cons);
4652                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4653                         bge_start_locked(ifp);
4654         }
4655         BGE_UNLOCK(sc);
4656 }
4657
4658 static void
4659 bge_intr(void *xsc)
4660 {
4661         struct bge_softc *sc;
4662         struct ifnet *ifp;
4663         uint32_t statusword;
4664         uint16_t rx_prod, tx_cons;
4665
4666         sc = xsc;
4667
4668         BGE_LOCK(sc);
4669
4670         ifp = sc->bge_ifp;
4671
4672 #ifdef DEVICE_POLLING
4673         if (ifp->if_capenable & IFCAP_POLLING) {
4674                 BGE_UNLOCK(sc);
4675                 return;
4676         }
4677 #endif
4678
4679         /*
4680          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4681          * disable interrupts by writing nonzero like we used to, since with
4682          * our current organization this just gives complications and
4683          * pessimizations for re-enabling interrupts.  We used to have races
4684          * instead of the necessary complications.  Disabling interrupts
4685          * would just reduce the chance of a status update while we are
4686          * running (by switching to the interrupt-mode coalescence
4687          * parameters), but this chance is already very low so it is more
4688          * efficient to get another interrupt than prevent it.
4689          *
4690          * We do the ack first to ensure another interrupt if there is a
4691          * status update after the ack.  We don't check for the status
4692          * changing later because it is more efficient to get another
4693          * interrupt than prevent it, not quite as above (not checking is
4694          * a smaller optimization than not toggling the interrupt enable,
4695          * since checking doesn't involve PCI accesses and toggling require
4696          * the status check).  So toggling would probably be a pessimization
4697          * even with MSI.  It would only be needed for using a task queue.
4698          */
4699         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4700
4701         /*
4702          * Do the mandatory PCI flush as well as get the link status.
4703          */
4704         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4705
4706         /* Make sure the descriptor ring indexes are coherent. */
4707         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4708             sc->bge_cdata.bge_status_map,
4709             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4710         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4711         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4712         sc->bge_ldata.bge_status_block->bge_status = 0;
4713         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4714             sc->bge_cdata.bge_status_map,
4715             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4716
4717         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4718             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4719             statusword || sc->bge_link_evt)
4720                 bge_link_upd(sc);
4721
4722         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4723                 /* Check RX return ring producer/consumer. */
4724                 bge_rxeof(sc, rx_prod, 1);
4725         }
4726
4727         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4728                 /* Check TX ring producer/consumer. */
4729                 bge_txeof(sc, tx_cons);
4730         }
4731
4732         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4733             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4734                 bge_start_locked(ifp);
4735
4736         BGE_UNLOCK(sc);
4737 }
4738
4739 static void
4740 bge_asf_driver_up(struct bge_softc *sc)
4741 {
4742         if (sc->bge_asf_mode & ASF_STACKUP) {
4743                 /* Send ASF heartbeat aprox. every 2s */
4744                 if (sc->bge_asf_count)
4745                         sc->bge_asf_count --;
4746                 else {
4747                         sc->bge_asf_count = 2;
4748                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4749                             BGE_FW_CMD_DRV_ALIVE);
4750                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4751                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4752                             BGE_FW_HB_TIMEOUT_SEC);
4753                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4754                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4755                             BGE_RX_CPU_DRV_EVENT);
4756                 }
4757         }
4758 }
4759
4760 static void
4761 bge_tick(void *xsc)
4762 {
4763         struct bge_softc *sc = xsc;
4764         struct mii_data *mii = NULL;
4765
4766         BGE_LOCK_ASSERT(sc);
4767
4768         /* Synchronize with possible callout reset/stop. */
4769         if (callout_pending(&sc->bge_stat_ch) ||
4770             !callout_active(&sc->bge_stat_ch))
4771                 return;
4772
4773         if (BGE_IS_5705_PLUS(sc))
4774                 bge_stats_update_regs(sc);
4775         else
4776                 bge_stats_update(sc);
4777
4778         /* XXX Add APE heartbeat check here? */
4779
4780         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4781                 mii = device_get_softc(sc->bge_miibus);
4782                 /*
4783                  * Do not touch PHY if we have link up. This could break
4784                  * IPMI/ASF mode or produce extra input errors
4785                  * (extra errors was reported for bcm5701 & bcm5704).
4786                  */
4787                 if (!sc->bge_link)
4788                         mii_tick(mii);
4789         } else {
4790                 /*
4791                  * Since in TBI mode auto-polling can't be used we should poll
4792                  * link status manually. Here we register pending link event
4793                  * and trigger interrupt.
4794                  */
4795 #ifdef DEVICE_POLLING
4796                 /* In polling mode we poll link state in bge_poll(). */
4797                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4798 #endif
4799                 {
4800                 sc->bge_link_evt++;
4801                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4802                     sc->bge_flags & BGE_FLAG_5788)
4803                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4804                 else
4805                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4806                 }
4807         }
4808
4809         bge_asf_driver_up(sc);
4810         bge_watchdog(sc);
4811
4812         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4813 }
4814
4815 static void
4816 bge_stats_update_regs(struct bge_softc *sc)
4817 {
4818         struct ifnet *ifp;
4819         struct bge_mac_stats *stats;
4820         uint32_t val;
4821
4822         ifp = sc->bge_ifp;
4823         stats = &sc->bge_mac_stats;
4824
4825         stats->ifHCOutOctets +=
4826             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4827         stats->etherStatsCollisions +=
4828             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4829         stats->outXonSent +=
4830             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4831         stats->outXoffSent +=
4832             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4833         stats->dot3StatsInternalMacTransmitErrors +=
4834             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4835         stats->dot3StatsSingleCollisionFrames +=
4836             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4837         stats->dot3StatsMultipleCollisionFrames +=
4838             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4839         stats->dot3StatsDeferredTransmissions +=
4840             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4841         stats->dot3StatsExcessiveCollisions +=
4842             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4843         stats->dot3StatsLateCollisions +=
4844             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4845         stats->ifHCOutUcastPkts +=
4846             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4847         stats->ifHCOutMulticastPkts +=
4848             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4849         stats->ifHCOutBroadcastPkts +=
4850             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4851
4852         stats->ifHCInOctets +=
4853             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4854         stats->etherStatsFragments +=
4855             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4856         stats->ifHCInUcastPkts +=
4857             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4858         stats->ifHCInMulticastPkts +=
4859             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4860         stats->ifHCInBroadcastPkts +=
4861             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4862         stats->dot3StatsFCSErrors +=
4863             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4864         stats->dot3StatsAlignmentErrors +=
4865             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4866         stats->xonPauseFramesReceived +=
4867             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4868         stats->xoffPauseFramesReceived +=
4869             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4870         stats->macControlFramesReceived +=
4871             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4872         stats->xoffStateEntered +=
4873             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4874         stats->dot3StatsFramesTooLong +=
4875             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4876         stats->etherStatsJabbers +=
4877             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4878         stats->etherStatsUndersizePkts +=
4879             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4880
4881         stats->FramesDroppedDueToFilters +=
4882             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4883         stats->DmaWriteQueueFull +=
4884             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4885         stats->DmaWriteHighPriQueueFull +=
4886             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4887         stats->NoMoreRxBDs +=
4888             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4889         /*
4890          * XXX
4891          * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4892          * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4893          * includes number of unwanted multicast frames.  This comes
4894          * from silicon bug and known workaround to get rough(not
4895          * exact) counter is to enable interrupt on MBUF low water
4896          * attention.  This can be accomplished by setting
4897          * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4898          * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4899          * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4900          * However that change would generate more interrupts and
4901          * there are still possibilities of losing multiple frames
4902          * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4903          * Given that the workaround still would not get correct
4904          * counter I don't think it's worth to implement it.  So
4905          * ignore reading the counter on controllers that have the
4906          * silicon bug.
4907          */
4908         if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4909             sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4910             sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4911                 stats->InputDiscards +=
4912                     CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4913         stats->InputErrors +=
4914             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4915         stats->RecvThresholdHit +=
4916             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4917
4918         ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4919         ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4920             stats->InputErrors);
4921
4922         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4923                 /*
4924                  * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4925                  * frames, it's safe to disable workaround for DMA engine's
4926                  * miscalculation of TXMBUF space.
4927                  */
4928                 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4929                     stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4930                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4931                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4932                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4933                         else
4934                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4935                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4936                         sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4937                 }
4938         }
4939 }
4940
4941 static void
4942 bge_stats_clear_regs(struct bge_softc *sc)
4943 {
4944
4945         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4946         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4947         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4948         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4949         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4950         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4951         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4952         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4953         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4954         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4955         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4956         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4957         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4958
4959         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4960         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4961         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4962         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4963         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4964         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4965         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4966         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4967         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4968         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4969         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4970         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4971         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4972         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4973
4974         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4975         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4976         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4977         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4978         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4979         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4980         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4981 }
4982
4983 static void
4984 bge_stats_update(struct bge_softc *sc)
4985 {
4986         struct ifnet *ifp;
4987         bus_size_t stats;
4988         uint32_t cnt;   /* current register value */
4989
4990         ifp = sc->bge_ifp;
4991
4992         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4993
4994 #define READ_STAT(sc, stats, stat) \
4995         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4996
4997         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4998         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4999         sc->bge_tx_collisions = cnt;
5000
5001         cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
5002         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds);
5003         sc->bge_rx_nobds = cnt;
5004         cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5005         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs);
5006         sc->bge_rx_inerrs = cnt;
5007         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5008         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
5009         sc->bge_rx_discards = cnt;
5010
5011         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5012         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
5013         sc->bge_tx_discards = cnt;
5014
5015 #undef  READ_STAT
5016 }
5017
5018 /*
5019  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5020  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5021  * but when such padded frames employ the bge IP/TCP checksum offload,
5022  * the hardware checksum assist gives incorrect results (possibly
5023  * from incorporating its own padding into the UDP/TCP checksum; who knows).
5024  * If we pad such runts with zeros, the onboard checksum comes out correct.
5025  */
5026 static __inline int
5027 bge_cksum_pad(struct mbuf *m)
5028 {
5029         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5030         struct mbuf *last;
5031
5032         /* If there's only the packet-header and we can pad there, use it. */
5033         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5034             M_TRAILINGSPACE(m) >= padlen) {
5035                 last = m;
5036         } else {
5037                 /*
5038                  * Walk packet chain to find last mbuf. We will either
5039                  * pad there, or append a new mbuf and pad it.
5040                  */
5041                 for (last = m; last->m_next != NULL; last = last->m_next);
5042                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5043                         /* Allocate new empty mbuf, pad it. Compact later. */
5044                         struct mbuf *n;
5045
5046                         MGET(n, M_NOWAIT, MT_DATA);
5047                         if (n == NULL)
5048                                 return (ENOBUFS);
5049                         n->m_len = 0;
5050                         last->m_next = n;
5051                         last = n;
5052                 }
5053         }
5054
5055         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5056         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5057         last->m_len += padlen;
5058         m->m_pkthdr.len += padlen;
5059
5060         return (0);
5061 }
5062
5063 static struct mbuf *
5064 bge_check_short_dma(struct mbuf *m)
5065 {
5066         struct mbuf *n;
5067         int found;
5068
5069         /*
5070          * If device receive two back-to-back send BDs with less than
5071          * or equal to 8 total bytes then the device may hang.  The two
5072          * back-to-back send BDs must in the same frame for this failure
5073          * to occur.  Scan mbuf chains and see whether two back-to-back
5074          * send BDs are there. If this is the case, allocate new mbuf
5075          * and copy the frame to workaround the silicon bug.
5076          */
5077         for (n = m, found = 0; n != NULL; n = n->m_next) {
5078                 if (n->m_len < 8) {
5079                         found++;
5080                         if (found > 1)
5081                                 break;
5082                         continue;
5083                 }
5084                 found = 0;
5085         }
5086
5087         if (found > 1) {
5088                 n = m_defrag(m, M_NOWAIT);
5089                 if (n == NULL)
5090                         m_freem(m);
5091         } else
5092                 n = m;
5093         return (n);
5094 }
5095
5096 static struct mbuf *
5097 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5098     uint16_t *flags)
5099 {
5100         struct ip *ip;
5101         struct tcphdr *tcp;
5102         struct mbuf *n;
5103         uint16_t hlen;
5104         uint32_t poff;
5105
5106         if (M_WRITABLE(m) == 0) {
5107                 /* Get a writable copy. */
5108                 n = m_dup(m, M_NOWAIT);
5109                 m_freem(m);
5110                 if (n == NULL)
5111                         return (NULL);
5112                 m = n;
5113         }
5114         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5115         if (m == NULL)
5116                 return (NULL);
5117         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5118         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5119         m = m_pullup(m, poff + sizeof(struct tcphdr));
5120         if (m == NULL)
5121                 return (NULL);
5122         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5123         m = m_pullup(m, poff + (tcp->th_off << 2));
5124         if (m == NULL)
5125                 return (NULL);
5126         /*
5127          * It seems controller doesn't modify IP length and TCP pseudo
5128          * checksum. These checksum computed by upper stack should be 0.
5129          */
5130         *mss = m->m_pkthdr.tso_segsz;
5131         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5132         ip->ip_sum = 0;
5133         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5134         /* Clear pseudo checksum computed by TCP stack. */
5135         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5136         tcp->th_sum = 0;
5137         /*
5138          * Broadcom controllers uses different descriptor format for
5139          * TSO depending on ASIC revision. Due to TSO-capable firmware
5140          * license issue and lower performance of firmware based TSO
5141          * we only support hardware based TSO.
5142          */
5143         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5144         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5145         if (sc->bge_flags & BGE_FLAG_TSO3) {
5146                 /*
5147                  * For BCM5717 and newer controllers, hardware based TSO
5148                  * uses the 14 lower bits of the bge_mss field to store the
5149                  * MSS and the upper 2 bits to store the lowest 2 bits of
5150                  * the IP/TCP header length.  The upper 6 bits of the header
5151                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
5152                  * frames are supported.
5153                  */
5154                 *mss |= ((hlen & 0x3) << 14);
5155                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5156         } else {
5157                 /*
5158                  * For BCM5755 and newer controllers, hardware based TSO uses
5159                  * the lower 11 bits to store the MSS and the upper 5 bits to
5160                  * store the IP/TCP header length. Jumbo frames are not
5161                  * supported.
5162                  */
5163                 *mss |= (hlen << 11);
5164         }
5165         return (m);
5166 }
5167
5168 /*
5169  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
5170  * pointers to descriptors.
5171  */
5172 static int
5173 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5174 {
5175         bus_dma_segment_t       segs[BGE_NSEG_NEW];
5176         bus_dmamap_t            map;
5177         struct bge_tx_bd        *d;
5178         struct mbuf             *m = *m_head;
5179         uint32_t                idx = *txidx;
5180         uint16_t                csum_flags, mss, vlan_tag;
5181         int                     nsegs, i, error;
5182
5183         csum_flags = 0;
5184         mss = 0;
5185         vlan_tag = 0;
5186         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5187             m->m_next != NULL) {
5188                 *m_head = bge_check_short_dma(m);
5189                 if (*m_head == NULL)
5190                         return (ENOBUFS);
5191                 m = *m_head;
5192         }
5193         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5194                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5195                 if (*m_head == NULL)
5196                         return (ENOBUFS);
5197                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5198                     BGE_TXBDFLAG_CPU_POST_DMA;
5199         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5200                 if (m->m_pkthdr.csum_flags & CSUM_IP)
5201                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5202                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5203                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5204                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5205                             (error = bge_cksum_pad(m)) != 0) {
5206                                 m_freem(m);
5207                                 *m_head = NULL;
5208                                 return (error);
5209                         }
5210                 }
5211         }
5212
5213         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5214                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5215                     m->m_pkthdr.len > ETHER_MAX_LEN)
5216                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5217                 if (sc->bge_forced_collapse > 0 &&
5218                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5219                         /*
5220                          * Forcedly collapse mbuf chains to overcome hardware
5221                          * limitation which only support a single outstanding
5222                          * DMA read operation.
5223                          */
5224                         if (sc->bge_forced_collapse == 1)
5225                                 m = m_defrag(m, M_NOWAIT);
5226                         else
5227                                 m = m_collapse(m, M_NOWAIT,
5228                                     sc->bge_forced_collapse);
5229                         if (m == NULL)
5230                                 m = *m_head;
5231                         *m_head = m;
5232                 }
5233         }
5234
5235         map = sc->bge_cdata.bge_tx_dmamap[idx];
5236         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5237             &nsegs, BUS_DMA_NOWAIT);
5238         if (error == EFBIG) {
5239                 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5240                 if (m == NULL) {
5241                         m_freem(*m_head);
5242                         *m_head = NULL;
5243                         return (ENOBUFS);
5244                 }
5245                 *m_head = m;
5246                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5247                     m, segs, &nsegs, BUS_DMA_NOWAIT);
5248                 if (error) {
5249                         m_freem(m);
5250                         *m_head = NULL;
5251                         return (error);
5252                 }
5253         } else if (error != 0)
5254                 return (error);
5255
5256         /* Check if we have enough free send BDs. */
5257         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5258                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5259                 return (ENOBUFS);
5260         }
5261
5262         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5263
5264         if (m->m_flags & M_VLANTAG) {
5265                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5266                 vlan_tag = m->m_pkthdr.ether_vtag;
5267         }
5268
5269         if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5270             (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5271                 /*
5272                  * 5725 family of devices corrupts TSO packets when TSO DMA
5273                  * buffers cross into regions which are within MSS bytes of
5274                  * a 4GB boundary.  If we encounter the condition, drop the
5275                  * packet.
5276                  */
5277                 for (i = 0; ; i++) {
5278                         d = &sc->bge_ldata.bge_tx_ring[idx];
5279                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5280                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5281                         d->bge_len = segs[i].ds_len;
5282                         if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5283                             d->bge_addr.bge_addr_lo)
5284                                 break;
5285                         d->bge_flags = csum_flags;
5286                         d->bge_vlan_tag = vlan_tag;
5287                         d->bge_mss = mss;
5288                         if (i == nsegs - 1)
5289                                 break;
5290                         BGE_INC(idx, BGE_TX_RING_CNT);
5291                 }
5292                 if (i != nsegs - 1) {
5293                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5294                             BUS_DMASYNC_POSTWRITE);
5295                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5296                         m_freem(*m_head);
5297                         *m_head = NULL;
5298                         return (EIO);
5299                 }
5300         } else {
5301                 for (i = 0; ; i++) {
5302                         d = &sc->bge_ldata.bge_tx_ring[idx];
5303                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5304                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5305                         d->bge_len = segs[i].ds_len;
5306                         d->bge_flags = csum_flags;
5307                         d->bge_vlan_tag = vlan_tag;
5308                         d->bge_mss = mss;
5309                         if (i == nsegs - 1)
5310                                 break;
5311                         BGE_INC(idx, BGE_TX_RING_CNT);
5312                 }
5313         }
5314
5315         /* Mark the last segment as end of packet... */
5316         d->bge_flags |= BGE_TXBDFLAG_END;
5317
5318         /*
5319          * Insure that the map for this transmission
5320          * is placed at the array index of the last descriptor
5321          * in this chain.
5322          */
5323         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5324         sc->bge_cdata.bge_tx_dmamap[idx] = map;
5325         sc->bge_cdata.bge_tx_chain[idx] = m;
5326         sc->bge_txcnt += nsegs;
5327
5328         BGE_INC(idx, BGE_TX_RING_CNT);
5329         *txidx = idx;
5330
5331         return (0);
5332 }
5333
5334 /*
5335  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5336  * to the mbuf data regions directly in the transmit descriptors.
5337  */
5338 static void
5339 bge_start_locked(struct ifnet *ifp)
5340 {
5341         struct bge_softc *sc;
5342         struct mbuf *m_head;
5343         uint32_t prodidx;
5344         int count;
5345
5346         sc = ifp->if_softc;
5347         BGE_LOCK_ASSERT(sc);
5348
5349         if (!sc->bge_link ||
5350             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5351             IFF_DRV_RUNNING)
5352                 return;
5353
5354         prodidx = sc->bge_tx_prodidx;
5355
5356         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
5357                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5358                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5359                         break;
5360                 }
5361                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
5362                 if (m_head == NULL)
5363                         break;
5364
5365                 /*
5366                  * Pack the data into the transmit ring. If we
5367                  * don't have room, set the OACTIVE flag and wait
5368                  * for the NIC to drain the ring.
5369                  */
5370                 if (bge_encap(sc, &m_head, &prodidx)) {
5371                         if (m_head == NULL)
5372                                 break;
5373                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
5374                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5375                         break;
5376                 }
5377                 ++count;
5378
5379                 /*
5380                  * If there's a BPF listener, bounce a copy of this frame
5381                  * to him.
5382                  */
5383 #ifdef ETHER_BPF_MTAP
5384                 ETHER_BPF_MTAP(ifp, m_head);
5385 #else
5386                 BPF_MTAP(ifp, m_head);
5387 #endif
5388         }
5389
5390         if (count > 0) {
5391                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5392                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5393                 /* Transmit. */
5394                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5395                 /* 5700 b2 errata */
5396                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5397                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5398
5399                 sc->bge_tx_prodidx = prodidx;
5400
5401                 /*
5402                  * Set a timeout in case the chip goes out to lunch.
5403                  */
5404                 sc->bge_timer = BGE_TX_TIMEOUT;
5405         }
5406 }
5407
5408 /*
5409  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5410  * to the mbuf data regions directly in the transmit descriptors.
5411  */
5412 static void
5413 bge_start(struct ifnet *ifp)
5414 {
5415         struct bge_softc *sc;
5416
5417         sc = ifp->if_softc;
5418         BGE_LOCK(sc);
5419         bge_start_locked(ifp);
5420         BGE_UNLOCK(sc);
5421 }
5422
5423 static void
5424 bge_init_locked(struct bge_softc *sc)
5425 {
5426         struct ifnet *ifp;
5427         uint16_t *m;
5428         uint32_t mode;
5429
5430         BGE_LOCK_ASSERT(sc);
5431
5432         ifp = sc->bge_ifp;
5433
5434         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5435                 return;
5436
5437         /* Cancel pending I/O and flush buffers. */
5438         bge_stop(sc);
5439
5440         bge_stop_fw(sc);
5441         bge_sig_pre_reset(sc, BGE_RESET_START);
5442         bge_reset(sc);
5443         bge_sig_legacy(sc, BGE_RESET_START);
5444         bge_sig_post_reset(sc, BGE_RESET_START);
5445
5446         bge_chipinit(sc);
5447
5448         /*
5449          * Init the various state machines, ring
5450          * control blocks and firmware.
5451          */
5452         if (bge_blockinit(sc)) {
5453                 device_printf(sc->bge_dev, "initialization failure\n");
5454                 return;
5455         }
5456
5457         ifp = sc->bge_ifp;
5458
5459         /* Specify MTU. */
5460         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5461             ETHER_HDR_LEN + ETHER_CRC_LEN +
5462             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5463
5464         /* Load our MAC address. */
5465         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5466         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5467         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5468
5469         /* Program promiscuous mode. */
5470         bge_setpromisc(sc);
5471
5472         /* Program multicast filter. */
5473         bge_setmulti(sc);
5474
5475         /* Program VLAN tag stripping. */
5476         bge_setvlan(sc);
5477
5478         /* Override UDP checksum offloading. */
5479         if (sc->bge_forced_udpcsum == 0)
5480                 sc->bge_csum_features &= ~CSUM_UDP;
5481         else
5482                 sc->bge_csum_features |= CSUM_UDP;
5483         if (ifp->if_capabilities & IFCAP_TXCSUM &&
5484             ifp->if_capenable & IFCAP_TXCSUM) {
5485                 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
5486                 ifp->if_hwassist |= sc->bge_csum_features;
5487         }
5488
5489         /* Init RX ring. */
5490         if (bge_init_rx_ring_std(sc) != 0) {
5491                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5492                 bge_stop(sc);
5493                 return;
5494         }
5495
5496         /*
5497          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5498          * memory to insure that the chip has in fact read the first
5499          * entry of the ring.
5500          */
5501         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5502                 uint32_t                v, i;
5503                 for (i = 0; i < 10; i++) {
5504                         DELAY(20);
5505                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5506                         if (v == (MCLBYTES - ETHER_ALIGN))
5507                                 break;
5508                 }
5509                 if (i == 10)
5510                         device_printf (sc->bge_dev,
5511                             "5705 A0 chip failed to load RX ring\n");
5512         }
5513
5514         /* Init jumbo RX ring. */
5515         if (BGE_IS_JUMBO_CAPABLE(sc) &&
5516             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
5517             (MCLBYTES - ETHER_ALIGN)) {
5518                 if (bge_init_rx_ring_jumbo(sc) != 0) {
5519                         device_printf(sc->bge_dev,
5520                             "no memory for jumbo Rx buffers.\n");
5521                         bge_stop(sc);
5522                         return;
5523                 }
5524         }
5525
5526         /* Init our RX return ring index. */
5527         sc->bge_rx_saved_considx = 0;
5528
5529         /* Init our RX/TX stat counters. */
5530         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5531
5532         /* Init TX ring. */
5533         bge_init_tx_ring(sc);
5534
5535         /* Enable TX MAC state machine lockup fix. */
5536         mode = CSR_READ_4(sc, BGE_TX_MODE);
5537         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5538                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5539         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5540             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5541                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5542                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5543                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5544         }
5545         /* Turn on transmitter. */
5546         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5547         DELAY(100);
5548
5549         /* Turn on receiver. */
5550         mode = CSR_READ_4(sc, BGE_RX_MODE);
5551         if (BGE_IS_5755_PLUS(sc))
5552                 mode |= BGE_RXMODE_IPV6_ENABLE;
5553         if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5554                 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5555         CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5556         DELAY(10);
5557
5558         /*
5559          * Set the number of good frames to receive after RX MBUF
5560          * Low Watermark has been reached. After the RX MAC receives
5561          * this number of frames, it will drop subsequent incoming
5562          * frames until the MBUF High Watermark is reached.
5563          */
5564         if (BGE_IS_57765_PLUS(sc))
5565                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5566         else
5567                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5568
5569         /* Clear MAC statistics. */
5570         if (BGE_IS_5705_PLUS(sc))
5571                 bge_stats_clear_regs(sc);
5572
5573         /* Tell firmware we're alive. */
5574         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5575
5576 #ifdef DEVICE_POLLING
5577         /* Disable interrupts if we are polling. */
5578         if (ifp->if_capenable & IFCAP_POLLING) {
5579                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5580                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5581                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5582         } else
5583 #endif
5584
5585         /* Enable host interrupts. */
5586         {
5587         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5588         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5589         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5590         }
5591
5592         ifp->if_drv_flags |= IFF_DRV_RUNNING;
5593         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5594
5595         bge_ifmedia_upd_locked(ifp);
5596
5597         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5598 }
5599
5600 static void
5601 bge_init(void *xsc)
5602 {
5603         struct bge_softc *sc = xsc;
5604
5605         BGE_LOCK(sc);
5606         bge_init_locked(sc);
5607         BGE_UNLOCK(sc);
5608 }
5609
5610 /*
5611  * Set media options.
5612  */
5613 static int
5614 bge_ifmedia_upd(struct ifnet *ifp)
5615 {
5616         struct bge_softc *sc = ifp->if_softc;
5617         int res;
5618
5619         BGE_LOCK(sc);
5620         res = bge_ifmedia_upd_locked(ifp);
5621         BGE_UNLOCK(sc);
5622
5623         return (res);
5624 }
5625
5626 static int
5627 bge_ifmedia_upd_locked(struct ifnet *ifp)
5628 {
5629         struct bge_softc *sc = ifp->if_softc;
5630         struct mii_data *mii;
5631         struct mii_softc *miisc;
5632         struct ifmedia *ifm;
5633
5634         BGE_LOCK_ASSERT(sc);
5635
5636         ifm = &sc->bge_ifmedia;
5637
5638         /* If this is a 1000baseX NIC, enable the TBI port. */
5639         if (sc->bge_flags & BGE_FLAG_TBI) {
5640                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5641                         return (EINVAL);
5642                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5643                 case IFM_AUTO:
5644                         /*
5645                          * The BCM5704 ASIC appears to have a special
5646                          * mechanism for programming the autoneg
5647                          * advertisement registers in TBI mode.
5648                          */
5649                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5650                                 uint32_t sgdig;
5651                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5652                                 if (sgdig & BGE_SGDIGSTS_DONE) {
5653                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5654                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5655                                         sgdig |= BGE_SGDIGCFG_AUTO |
5656                                             BGE_SGDIGCFG_PAUSE_CAP |
5657                                             BGE_SGDIGCFG_ASYM_PAUSE;
5658                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5659                                             sgdig | BGE_SGDIGCFG_SEND);
5660                                         DELAY(5);
5661                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5662                                 }
5663                         }
5664                         break;
5665                 case IFM_1000_SX:
5666                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5667                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
5668                                     BGE_MACMODE_HALF_DUPLEX);
5669                         } else {
5670                                 BGE_SETBIT(sc, BGE_MAC_MODE,
5671                                     BGE_MACMODE_HALF_DUPLEX);
5672                         }
5673                         DELAY(40);
5674                         break;
5675                 default:
5676                         return (EINVAL);
5677                 }
5678                 return (0);
5679         }
5680
5681         sc->bge_link_evt++;
5682         mii = device_get_softc(sc->bge_miibus);
5683         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5684                 PHY_RESET(miisc);
5685         mii_mediachg(mii);
5686
5687         /*
5688          * Force an interrupt so that we will call bge_link_upd
5689          * if needed and clear any pending link state attention.
5690          * Without this we are not getting any further interrupts
5691          * for link state changes and thus will not UP the link and
5692          * not be able to send in bge_start_locked. The only
5693          * way to get things working was to receive a packet and
5694          * get an RX intr.
5695          * bge_tick should help for fiber cards and we might not
5696          * need to do this here if BGE_FLAG_TBI is set but as
5697          * we poll for fiber anyway it should not harm.
5698          */
5699         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5700             sc->bge_flags & BGE_FLAG_5788)
5701                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5702         else
5703                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5704
5705         return (0);
5706 }
5707
5708 /*
5709  * Report current media status.
5710  */
5711 static void
5712 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5713 {
5714         struct bge_softc *sc = ifp->if_softc;
5715         struct mii_data *mii;
5716
5717         BGE_LOCK(sc);
5718
5719         if ((ifp->if_flags & IFF_UP) == 0) {
5720                 BGE_UNLOCK(sc);
5721                 return;
5722         }
5723         if (sc->bge_flags & BGE_FLAG_TBI) {
5724                 ifmr->ifm_status = IFM_AVALID;
5725                 ifmr->ifm_active = IFM_ETHER;
5726                 if (CSR_READ_4(sc, BGE_MAC_STS) &
5727                     BGE_MACSTAT_TBI_PCS_SYNCHED)
5728                         ifmr->ifm_status |= IFM_ACTIVE;
5729                 else {
5730                         ifmr->ifm_active |= IFM_NONE;
5731                         BGE_UNLOCK(sc);
5732                         return;
5733                 }
5734                 ifmr->ifm_active |= IFM_1000_SX;
5735                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5736                         ifmr->ifm_active |= IFM_HDX;
5737                 else
5738                         ifmr->ifm_active |= IFM_FDX;
5739                 BGE_UNLOCK(sc);
5740                 return;
5741         }
5742
5743         mii = device_get_softc(sc->bge_miibus);
5744         mii_pollstat(mii);
5745         ifmr->ifm_active = mii->mii_media_active;
5746         ifmr->ifm_status = mii->mii_media_status;
5747
5748         BGE_UNLOCK(sc);
5749 }
5750
5751 static int
5752 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5753 {
5754         struct bge_softc *sc = ifp->if_softc;
5755         struct ifreq *ifr = (struct ifreq *) data;
5756         struct mii_data *mii;
5757         int flags, mask, error = 0;
5758
5759         switch (command) {
5760         case SIOCSIFMTU:
5761                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5762                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5763                         if (ifr->ifr_mtu < ETHERMIN ||
5764                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
5765                                 error = EINVAL;
5766                                 break;
5767                         }
5768                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5769                         error = EINVAL;
5770                         break;
5771                 }
5772                 BGE_LOCK(sc);
5773                 if (ifp->if_mtu != ifr->ifr_mtu) {
5774                         ifp->if_mtu = ifr->ifr_mtu;
5775                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5776                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5777                                 bge_init_locked(sc);
5778                         }
5779                 }
5780                 BGE_UNLOCK(sc);
5781                 break;
5782         case SIOCSIFFLAGS:
5783                 BGE_LOCK(sc);
5784                 if (ifp->if_flags & IFF_UP) {
5785                         /*
5786                          * If only the state of the PROMISC flag changed,
5787                          * then just use the 'set promisc mode' command
5788                          * instead of reinitializing the entire NIC. Doing
5789                          * a full re-init means reloading the firmware and
5790                          * waiting for it to start up, which may take a
5791                          * second or two.  Similarly for ALLMULTI.
5792                          */
5793                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5794                                 flags = ifp->if_flags ^ sc->bge_if_flags;
5795                                 if (flags & IFF_PROMISC)
5796                                         bge_setpromisc(sc);
5797                                 if (flags & IFF_ALLMULTI)
5798                                         bge_setmulti(sc);
5799                         } else
5800                                 bge_init_locked(sc);
5801                 } else {
5802                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5803                                 bge_stop(sc);
5804                         }
5805                 }
5806                 sc->bge_if_flags = ifp->if_flags;
5807                 BGE_UNLOCK(sc);
5808                 error = 0;
5809                 break;
5810         case SIOCADDMULTI:
5811         case SIOCDELMULTI:
5812                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5813                         BGE_LOCK(sc);
5814                         bge_setmulti(sc);
5815                         BGE_UNLOCK(sc);
5816                         error = 0;
5817                 }
5818                 break;
5819         case SIOCSIFMEDIA:
5820         case SIOCGIFMEDIA:
5821                 if (sc->bge_flags & BGE_FLAG_TBI) {
5822                         error = ifmedia_ioctl(ifp, ifr,
5823                             &sc->bge_ifmedia, command);
5824                 } else {
5825                         mii = device_get_softc(sc->bge_miibus);
5826                         error = ifmedia_ioctl(ifp, ifr,
5827                             &mii->mii_media, command);
5828                 }
5829                 break;
5830         case SIOCSIFCAP:
5831                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5832 #ifdef DEVICE_POLLING
5833                 if (mask & IFCAP_POLLING) {
5834                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
5835                                 error = ether_poll_register(bge_poll, ifp);
5836                                 if (error)
5837                                         return (error);
5838                                 BGE_LOCK(sc);
5839                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5840                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5841                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5842                                 ifp->if_capenable |= IFCAP_POLLING;
5843                                 BGE_UNLOCK(sc);
5844                         } else {
5845                                 error = ether_poll_deregister(ifp);
5846                                 /* Enable interrupt even in error case */
5847                                 BGE_LOCK(sc);
5848                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5849                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5850                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5851                                 ifp->if_capenable &= ~IFCAP_POLLING;
5852                                 BGE_UNLOCK(sc);
5853                         }
5854                 }
5855 #endif
5856                 if ((mask & IFCAP_TXCSUM) != 0 &&
5857                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5858                         ifp->if_capenable ^= IFCAP_TXCSUM;
5859                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5860                                 ifp->if_hwassist |= sc->bge_csum_features;
5861                         else
5862                                 ifp->if_hwassist &= ~sc->bge_csum_features;
5863                 }
5864
5865                 if ((mask & IFCAP_RXCSUM) != 0 &&
5866                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5867                         ifp->if_capenable ^= IFCAP_RXCSUM;
5868
5869                 if ((mask & IFCAP_TSO4) != 0 &&
5870                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5871                         ifp->if_capenable ^= IFCAP_TSO4;
5872                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5873                                 ifp->if_hwassist |= CSUM_TSO;
5874                         else
5875                                 ifp->if_hwassist &= ~CSUM_TSO;
5876                 }
5877
5878                 if (mask & IFCAP_VLAN_MTU) {
5879                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
5880                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5881                         bge_init(sc);
5882                 }
5883
5884                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5885                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5886                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5887                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5888                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5889                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5890                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5891                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5892                         BGE_LOCK(sc);
5893                         bge_setvlan(sc);
5894                         BGE_UNLOCK(sc);
5895                 }
5896 #ifdef VLAN_CAPABILITIES
5897                 VLAN_CAPABILITIES(ifp);
5898 #endif
5899                 break;
5900         default:
5901                 error = ether_ioctl(ifp, command, data);
5902                 break;
5903         }
5904
5905         return (error);
5906 }
5907
5908 static void
5909 bge_watchdog(struct bge_softc *sc)
5910 {
5911         struct ifnet *ifp;
5912         uint32_t status;
5913
5914         BGE_LOCK_ASSERT(sc);
5915
5916         if (sc->bge_timer == 0 || --sc->bge_timer)
5917                 return;
5918
5919         /* If pause frames are active then don't reset the hardware. */
5920         if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5921                 status = CSR_READ_4(sc, BGE_RX_STS);
5922                 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5923                         /*
5924                          * If link partner has us in XOFF state then wait for
5925                          * the condition to clear.
5926                          */
5927                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5928                         sc->bge_timer = BGE_TX_TIMEOUT;
5929                         return;
5930                 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5931                     (status & BGE_RXSTAT_RCVD_XON) != 0) {
5932                         /*
5933                          * If link partner has us in XOFF state then wait for
5934                          * the condition to clear.
5935                          */
5936                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5937                         sc->bge_timer = BGE_TX_TIMEOUT;
5938                         return;
5939                 }
5940                 /*
5941                  * Any other condition is unexpected and the controller
5942                  * should be reset.
5943                  */
5944         }
5945
5946         ifp = sc->bge_ifp;
5947
5948         if_printf(ifp, "watchdog timeout -- resetting\n");
5949
5950         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5951         bge_init_locked(sc);
5952
5953         ifp->if_oerrors++;
5954 }
5955
5956 static void
5957 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5958 {
5959         int i;
5960
5961         BGE_CLRBIT(sc, reg, bit);
5962
5963         for (i = 0; i < BGE_TIMEOUT; i++) {
5964                 if ((CSR_READ_4(sc, reg) & bit) == 0)
5965                         return;
5966                 DELAY(100);
5967         }
5968 }
5969
5970 /*
5971  * Stop the adapter and free any mbufs allocated to the
5972  * RX and TX lists.
5973  */
5974 static void
5975 bge_stop(struct bge_softc *sc)
5976 {
5977         struct ifnet *ifp;
5978
5979         BGE_LOCK_ASSERT(sc);
5980
5981         ifp = sc->bge_ifp;
5982
5983         callout_stop(&sc->bge_stat_ch);
5984
5985         /* Disable host interrupts. */
5986         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5987         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5988
5989         /*
5990          * Tell firmware we're shutting down.
5991          */
5992         bge_stop_fw(sc);
5993         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5994
5995         /*
5996          * Disable all of the receiver blocks.
5997          */
5998         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5999         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
6000         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
6001         if (BGE_IS_5700_FAMILY(sc))
6002                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6003         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6004         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6005         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6006
6007         /*
6008          * Disable all of the transmit blocks.
6009          */
6010         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6011         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6012         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6013         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6014         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6015         if (BGE_IS_5700_FAMILY(sc))
6016                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6017         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6018
6019         /*
6020          * Shut down all of the memory managers and related
6021          * state machines.
6022          */
6023         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6024         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6025         if (BGE_IS_5700_FAMILY(sc))
6026                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6027
6028         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6029         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6030         if (!(BGE_IS_5705_PLUS(sc))) {
6031                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6032                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6033         }
6034         /* Update MAC statistics. */
6035         if (BGE_IS_5705_PLUS(sc))
6036                 bge_stats_update_regs(sc);
6037
6038         bge_reset(sc);
6039         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6040         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6041
6042         /*
6043          * Keep the ASF firmware running if up.
6044          */
6045         if (sc->bge_asf_mode & ASF_STACKUP)
6046                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6047         else
6048                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6049
6050         /* Free the RX lists. */
6051         bge_free_rx_ring_std(sc);
6052
6053         /* Free jumbo RX list. */
6054         if (BGE_IS_JUMBO_CAPABLE(sc))
6055                 bge_free_rx_ring_jumbo(sc);
6056
6057         /* Free TX buffers. */
6058         bge_free_tx_ring(sc);
6059
6060         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6061
6062         /* Clear MAC's link state (PHY may still have link UP). */
6063         if (bootverbose && sc->bge_link)
6064                 if_printf(sc->bge_ifp, "link DOWN\n");
6065         sc->bge_link = 0;
6066
6067         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
6068 }
6069
6070 /*
6071  * Stop all chip I/O so that the kernel's probe routines don't
6072  * get confused by errant DMAs when rebooting.
6073  */
6074 static int
6075 bge_shutdown(device_t dev)
6076 {
6077         struct bge_softc *sc;
6078
6079         sc = device_get_softc(dev);
6080         BGE_LOCK(sc);
6081         bge_stop(sc);
6082         BGE_UNLOCK(sc);
6083
6084         return (0);
6085 }
6086
6087 static int
6088 bge_suspend(device_t dev)
6089 {
6090         struct bge_softc *sc;
6091
6092         sc = device_get_softc(dev);
6093         BGE_LOCK(sc);
6094         bge_stop(sc);
6095         BGE_UNLOCK(sc);
6096
6097         return (0);
6098 }
6099
6100 static int
6101 bge_resume(device_t dev)
6102 {
6103         struct bge_softc *sc;
6104         struct ifnet *ifp;
6105
6106         sc = device_get_softc(dev);
6107         BGE_LOCK(sc);
6108         ifp = sc->bge_ifp;
6109         if (ifp->if_flags & IFF_UP) {
6110                 bge_init_locked(sc);
6111                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6112                         bge_start_locked(ifp);
6113         }
6114         BGE_UNLOCK(sc);
6115
6116         return (0);
6117 }
6118
6119 static void
6120 bge_link_upd(struct bge_softc *sc)
6121 {
6122         struct mii_data *mii;
6123         uint32_t link, status;
6124
6125         BGE_LOCK_ASSERT(sc);
6126
6127         /* Clear 'pending link event' flag. */
6128         sc->bge_link_evt = 0;
6129
6130         /*
6131          * Process link state changes.
6132          * Grrr. The link status word in the status block does
6133          * not work correctly on the BCM5700 rev AX and BX chips,
6134          * according to all available information. Hence, we have
6135          * to enable MII interrupts in order to properly obtain
6136          * async link changes. Unfortunately, this also means that
6137          * we have to read the MAC status register to detect link
6138          * changes, thereby adding an additional register access to
6139          * the interrupt handler.
6140          *
6141          * XXX: perhaps link state detection procedure used for
6142          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6143          */
6144
6145         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6146             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6147                 status = CSR_READ_4(sc, BGE_MAC_STS);
6148                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6149                         mii = device_get_softc(sc->bge_miibus);
6150                         mii_pollstat(mii);
6151                         if (!sc->bge_link &&
6152                             mii->mii_media_status & IFM_ACTIVE &&
6153                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6154                                 sc->bge_link++;
6155                                 if (bootverbose)
6156                                         if_printf(sc->bge_ifp, "link UP\n");
6157                         } else if (sc->bge_link &&
6158                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6159                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6160                                 sc->bge_link = 0;
6161                                 if (bootverbose)
6162                                         if_printf(sc->bge_ifp, "link DOWN\n");
6163                         }
6164
6165                         /* Clear the interrupt. */
6166                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6167                             BGE_EVTENB_MI_INTERRUPT);
6168                         bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6169                             BRGPHY_MII_ISR);
6170                         bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6171                             BRGPHY_MII_IMR, BRGPHY_INTRS);
6172                 }
6173                 return;
6174         }
6175
6176         if (sc->bge_flags & BGE_FLAG_TBI) {
6177                 status = CSR_READ_4(sc, BGE_MAC_STS);
6178                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6179                         if (!sc->bge_link) {
6180                                 sc->bge_link++;
6181                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6182                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
6183                                             BGE_MACMODE_TBI_SEND_CFGS);
6184                                         DELAY(40);
6185                                 }
6186                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6187                                 if (bootverbose)
6188                                         if_printf(sc->bge_ifp, "link UP\n");
6189                                 if_link_state_change(sc->bge_ifp,
6190                                     LINK_STATE_UP);
6191                         }
6192                 } else if (sc->bge_link) {
6193                         sc->bge_link = 0;
6194                         if (bootverbose)
6195                                 if_printf(sc->bge_ifp, "link DOWN\n");
6196                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6197                 }
6198         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6199                 /*
6200                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6201                  * in status word always set. Workaround this bug by reading
6202                  * PHY link status directly.
6203                  */
6204                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6205
6206                 if (link != sc->bge_link ||
6207                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6208                         mii = device_get_softc(sc->bge_miibus);
6209                         mii_pollstat(mii);
6210                         if (!sc->bge_link &&
6211                             mii->mii_media_status & IFM_ACTIVE &&
6212                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6213                                 sc->bge_link++;
6214                                 if (bootverbose)
6215                                         if_printf(sc->bge_ifp, "link UP\n");
6216                         } else if (sc->bge_link &&
6217                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6218                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6219                                 sc->bge_link = 0;
6220                                 if (bootverbose)
6221                                         if_printf(sc->bge_ifp, "link DOWN\n");
6222                         }
6223                 }
6224         } else {
6225                 /*
6226                  * For controllers that call mii_tick, we have to poll
6227                  * link status.
6228                  */
6229                 mii = device_get_softc(sc->bge_miibus);
6230                 mii_pollstat(mii);
6231                 bge_miibus_statchg(sc->bge_dev);
6232         }
6233
6234         /* Disable MAC attention when link is up. */
6235         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6236             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6237             BGE_MACSTAT_LINK_CHANGED);
6238 }
6239
6240 static void
6241 bge_add_sysctls(struct bge_softc *sc)
6242 {
6243         struct sysctl_ctx_list *ctx;
6244         struct sysctl_oid_list *children;
6245         char tn[32];
6246         int unit;
6247
6248         ctx = device_get_sysctl_ctx(sc->bge_dev);
6249         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6250
6251 #ifdef BGE_REGISTER_DEBUG
6252         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6253             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6254             "Debug Information");
6255
6256         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6257             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6258             "MAC Register Read");
6259
6260         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6261             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6262             "APE Register Read");
6263
6264         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6265             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6266             "Memory Read");
6267
6268 #endif
6269
6270         unit = device_get_unit(sc->bge_dev);
6271         /*
6272          * A common design characteristic for many Broadcom client controllers
6273          * is that they only support a single outstanding DMA read operation
6274          * on the PCIe bus. This means that it will take twice as long to fetch
6275          * a TX frame that is split into header and payload buffers as it does
6276          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6277          * these controllers, coalescing buffers to reduce the number of memory
6278          * reads is effective way to get maximum performance(about 940Mbps).
6279          * Without collapsing TX buffers the maximum TCP bulk transfer
6280          * performance is about 850Mbps. However forcing coalescing mbufs
6281          * consumes a lot of CPU cycles, so leave it off by default.
6282          */
6283         sc->bge_forced_collapse = 0;
6284         snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
6285         TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
6286         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6287             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
6288             "Number of fragmented TX buffers of a frame allowed before "
6289             "forced collapsing");
6290
6291         sc->bge_msi = 1;
6292         snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit);
6293         TUNABLE_INT_FETCH(tn, &sc->bge_msi);
6294         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6295             CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
6296
6297         /*
6298          * It seems all Broadcom controllers have a bug that can generate UDP
6299          * datagrams with checksum value 0 when TX UDP checksum offloading is
6300          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
6301          * Even though the probability of generating such UDP datagrams is
6302          * low, I don't want to see FreeBSD boxes to inject such datagrams
6303          * into network so disable UDP checksum offloading by default.  Users
6304          * still override this behavior by setting a sysctl variable,
6305          * dev.bge.0.forced_udpcsum.
6306          */
6307         sc->bge_forced_udpcsum = 0;
6308         snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
6309         TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
6310         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6311             CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
6312             "Enable UDP checksum offloading even if controller can "
6313             "generate UDP checksum value 0");
6314
6315         if (BGE_IS_5705_PLUS(sc))
6316                 bge_add_sysctl_stats_regs(sc, ctx, children);
6317         else
6318                 bge_add_sysctl_stats(sc, ctx, children);
6319 }
6320
6321 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6322         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6323             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6324             desc)
6325
6326 static void
6327 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6328     struct sysctl_oid_list *parent)
6329 {
6330         struct sysctl_oid *tree;
6331         struct sysctl_oid_list *children, *schildren;
6332
6333         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6334             NULL, "BGE Statistics");
6335         schildren = children = SYSCTL_CHILDREN(tree);
6336         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6337             children, COSFramesDroppedDueToFilters,
6338             "FramesDroppedDueToFilters");
6339         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6340             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6341         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6342             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6343         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6344             children, nicNoMoreRxBDs, "NoMoreRxBDs");
6345         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6346             children, ifInDiscards, "InputDiscards");
6347         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6348             children, ifInErrors, "InputErrors");
6349         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6350             children, nicRecvThresholdHit, "RecvThresholdHit");
6351         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6352             children, nicDmaReadQueueFull, "DmaReadQueueFull");
6353         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6354             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6355         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6356             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6357         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6358             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6359         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6360             children, nicRingStatusUpdate, "RingStatusUpdate");
6361         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6362             children, nicInterrupts, "Interrupts");
6363         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6364             children, nicAvoidedInterrupts, "AvoidedInterrupts");
6365         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6366             children, nicSendThresholdHit, "SendThresholdHit");
6367
6368         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6369             NULL, "BGE RX Statistics");
6370         children = SYSCTL_CHILDREN(tree);
6371         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6372             children, rxstats.ifHCInOctets, "ifHCInOctets");
6373         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6374             children, rxstats.etherStatsFragments, "Fragments");
6375         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6376             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6377         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6378             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6379         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6380             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6381         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6382             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6383         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6384             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6385         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6386             children, rxstats.xoffPauseFramesReceived,
6387             "xoffPauseFramesReceived");
6388         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6389             children, rxstats.macControlFramesReceived,
6390             "ControlFramesReceived");
6391         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6392             children, rxstats.xoffStateEntered, "xoffStateEntered");
6393         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6394             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6395         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6396             children, rxstats.etherStatsJabbers, "Jabbers");
6397         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6398             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6399         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6400             children, rxstats.inRangeLengthError, "inRangeLengthError");
6401         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6402             children, rxstats.outRangeLengthError, "outRangeLengthError");
6403
6404         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6405             NULL, "BGE TX Statistics");
6406         children = SYSCTL_CHILDREN(tree);
6407         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6408             children, txstats.ifHCOutOctets, "ifHCOutOctets");
6409         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6410             children, txstats.etherStatsCollisions, "Collisions");
6411         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6412             children, txstats.outXonSent, "XonSent");
6413         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6414             children, txstats.outXoffSent, "XoffSent");
6415         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6416             children, txstats.flowControlDone, "flowControlDone");
6417         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6418             children, txstats.dot3StatsInternalMacTransmitErrors,
6419             "InternalMacTransmitErrors");
6420         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6421             children, txstats.dot3StatsSingleCollisionFrames,
6422             "SingleCollisionFrames");
6423         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6424             children, txstats.dot3StatsMultipleCollisionFrames,
6425             "MultipleCollisionFrames");
6426         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6427             children, txstats.dot3StatsDeferredTransmissions,
6428             "DeferredTransmissions");
6429         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6430             children, txstats.dot3StatsExcessiveCollisions,
6431             "ExcessiveCollisions");
6432         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6433             children, txstats.dot3StatsLateCollisions,
6434             "LateCollisions");
6435         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6436             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6437         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6438             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6439         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6440             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6441         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6442             children, txstats.dot3StatsCarrierSenseErrors,
6443             "CarrierSenseErrors");
6444         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6445             children, txstats.ifOutDiscards, "Discards");
6446         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6447             children, txstats.ifOutErrors, "Errors");
6448 }
6449
6450 #undef BGE_SYSCTL_STAT
6451
6452 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
6453             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6454
6455 static void
6456 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6457     struct sysctl_oid_list *parent)
6458 {
6459         struct sysctl_oid *tree;
6460         struct sysctl_oid_list *child, *schild;
6461         struct bge_mac_stats *stats;
6462
6463         stats = &sc->bge_mac_stats;
6464         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6465             NULL, "BGE Statistics");
6466         schild = child = SYSCTL_CHILDREN(tree);
6467         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6468             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6469         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6470             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6471         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6472             &stats->DmaWriteHighPriQueueFull,
6473             "NIC DMA Write High Priority Queue Full");
6474         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6475             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6476         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6477             &stats->InputDiscards, "Discarded Input Frames");
6478         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6479             &stats->InputErrors, "Input Errors");
6480         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6481             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6482
6483         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6484             NULL, "BGE RX Statistics");
6485         child = SYSCTL_CHILDREN(tree);
6486         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6487             &stats->ifHCInOctets, "Inbound Octets");
6488         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6489             &stats->etherStatsFragments, "Fragments");
6490         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6491             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6492         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6493             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6494         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6495             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6496         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6497             &stats->dot3StatsFCSErrors, "FCS Errors");
6498         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6499             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6500         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6501             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6502         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6503             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6504         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6505             &stats->macControlFramesReceived, "MAC Control Frames Received");
6506         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6507             &stats->xoffStateEntered, "XOFF State Entered");
6508         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6509             &stats->dot3StatsFramesTooLong, "Frames Too Long");
6510         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6511             &stats->etherStatsJabbers, "Jabbers");
6512         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6513             &stats->etherStatsUndersizePkts, "Undersized Packets");
6514
6515         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6516             NULL, "BGE TX Statistics");
6517         child = SYSCTL_CHILDREN(tree);
6518         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6519             &stats->ifHCOutOctets, "Outbound Octets");
6520         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6521             &stats->etherStatsCollisions, "TX Collisions");
6522         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6523             &stats->outXonSent, "XON Sent");
6524         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6525             &stats->outXoffSent, "XOFF Sent");
6526         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6527             &stats->dot3StatsInternalMacTransmitErrors,
6528             "Internal MAC TX Errors");
6529         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6530             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6531         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6532             &stats->dot3StatsMultipleCollisionFrames,
6533             "Multiple Collision Frames");
6534         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6535             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6536         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6537             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6538         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6539             &stats->dot3StatsLateCollisions, "Late Collisions");
6540         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6541             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6542         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6543             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6544         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6545             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6546 }
6547
6548 #undef  BGE_SYSCTL_STAT_ADD64
6549
6550 static int
6551 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6552 {
6553         struct bge_softc *sc;
6554         uint32_t result;
6555         int offset;
6556
6557         sc = (struct bge_softc *)arg1;
6558         offset = arg2;
6559         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6560             offsetof(bge_hostaddr, bge_addr_lo));
6561         return (sysctl_handle_int(oidp, &result, 0, req));
6562 }
6563
6564 #ifdef BGE_REGISTER_DEBUG
6565 static int
6566 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6567 {
6568         struct bge_softc *sc;
6569         uint16_t *sbdata;
6570         int error, result, sbsz;
6571         int i, j;
6572
6573         result = -1;
6574         error = sysctl_handle_int(oidp, &result, 0, req);
6575         if (error || (req->newptr == NULL))
6576                 return (error);
6577
6578         if (result == 1) {
6579                 sc = (struct bge_softc *)arg1;
6580
6581                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6582                     sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6583                         sbsz = BGE_STATUS_BLK_SZ;
6584                 else
6585                         sbsz = 32;
6586                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6587                 printf("Status Block:\n");
6588                 BGE_LOCK(sc);
6589                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6590                     sc->bge_cdata.bge_status_map,
6591                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6592                 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6593                         printf("%06x:", i);
6594                         for (j = 0; j < 8; j++)
6595                                 printf(" %04x", sbdata[i++]);
6596                         printf("\n");
6597                 }
6598
6599                 printf("Registers:\n");
6600                 for (i = 0x800; i < 0xA00; ) {
6601                         printf("%06x:", i);
6602                         for (j = 0; j < 8; j++) {
6603                                 printf(" %08x", CSR_READ_4(sc, i));
6604                                 i += 4;
6605                         }
6606                         printf("\n");
6607                 }
6608                 BGE_UNLOCK(sc);
6609
6610                 printf("Hardware Flags:\n");
6611                 if (BGE_IS_5717_PLUS(sc))
6612                         printf(" - 5717 Plus\n");
6613                 if (BGE_IS_5755_PLUS(sc))
6614                         printf(" - 5755 Plus\n");
6615                 if (BGE_IS_575X_PLUS(sc))
6616                         printf(" - 575X Plus\n");
6617                 if (BGE_IS_5705_PLUS(sc))
6618                         printf(" - 5705 Plus\n");
6619                 if (BGE_IS_5714_FAMILY(sc))
6620                         printf(" - 5714 Family\n");
6621                 if (BGE_IS_5700_FAMILY(sc))
6622                         printf(" - 5700 Family\n");
6623                 if (sc->bge_flags & BGE_FLAG_JUMBO)
6624                         printf(" - Supports Jumbo Frames\n");
6625                 if (sc->bge_flags & BGE_FLAG_PCIX)
6626                         printf(" - PCI-X Bus\n");
6627                 if (sc->bge_flags & BGE_FLAG_PCIE)
6628                         printf(" - PCI Express Bus\n");
6629                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6630                         printf(" - No 3 LEDs\n");
6631                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6632                         printf(" - RX Alignment Bug\n");
6633         }
6634
6635         return (error);
6636 }
6637
6638 static int
6639 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6640 {
6641         struct bge_softc *sc;
6642         int error;
6643         uint16_t result;
6644         uint32_t val;
6645
6646         result = -1;
6647         error = sysctl_handle_int(oidp, &result, 0, req);
6648         if (error || (req->newptr == NULL))
6649                 return (error);
6650
6651         if (result < 0x8000) {
6652                 sc = (struct bge_softc *)arg1;
6653                 val = CSR_READ_4(sc, result);
6654                 printf("reg 0x%06X = 0x%08X\n", result, val);
6655         }
6656
6657         return (error);
6658 }
6659
6660 static int
6661 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6662 {
6663         struct bge_softc *sc;
6664         int error;
6665         uint16_t result;
6666         uint32_t val;
6667
6668         result = -1;
6669         error = sysctl_handle_int(oidp, &result, 0, req);
6670         if (error || (req->newptr == NULL))
6671                 return (error);
6672
6673         if (result < 0x8000) {
6674                 sc = (struct bge_softc *)arg1;
6675                 val = APE_READ_4(sc, result);
6676                 printf("reg 0x%06X = 0x%08X\n", result, val);
6677         }
6678
6679         return (error);
6680 }
6681
6682 static int
6683 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6684 {
6685         struct bge_softc *sc;
6686         int error;
6687         uint16_t result;
6688         uint32_t val;
6689
6690         result = -1;
6691         error = sysctl_handle_int(oidp, &result, 0, req);
6692         if (error || (req->newptr == NULL))
6693                 return (error);
6694
6695         if (result < 0x8000) {
6696                 sc = (struct bge_softc *)arg1;
6697                 val = bge_readmem_ind(sc, result);
6698                 printf("mem 0x%06X = 0x%08X\n", result, val);
6699         }
6700
6701         return (error);
6702 }
6703 #endif
6704
6705 static int
6706 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6707 {
6708
6709         if (sc->bge_flags & BGE_FLAG_EADDR)
6710                 return (1);
6711
6712 #ifdef __sparc64__
6713         OF_getetheraddr(sc->bge_dev, ether_addr);
6714         return (0);
6715 #endif
6716         return (1);
6717 }
6718
6719 static int
6720 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6721 {
6722         uint32_t mac_addr;
6723
6724         mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6725         if ((mac_addr >> 16) == 0x484b) {
6726                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6727                 ether_addr[1] = (uint8_t)mac_addr;
6728                 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6729                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6730                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6731                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6732                 ether_addr[5] = (uint8_t)mac_addr;
6733                 return (0);
6734         }
6735         return (1);
6736 }
6737
6738 static int
6739 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6740 {
6741         int mac_offset = BGE_EE_MAC_OFFSET;
6742
6743         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6744                 mac_offset = BGE_EE_MAC_OFFSET_5906;
6745
6746         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6747             ETHER_ADDR_LEN));
6748 }
6749
6750 static int
6751 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6752 {
6753
6754         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6755                 return (1);
6756
6757         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6758            ETHER_ADDR_LEN));
6759 }
6760
6761 static int
6762 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6763 {
6764         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6765                 /* NOTE: Order is critical */
6766                 bge_get_eaddr_fw,
6767                 bge_get_eaddr_mem,
6768                 bge_get_eaddr_nvram,
6769                 bge_get_eaddr_eeprom,
6770                 NULL
6771         };
6772         const bge_eaddr_fcn_t *func;
6773
6774         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6775                 if ((*func)(sc, eaddr) == 0)
6776                         break;
6777         }
6778         return (*func == NULL ? ENXIO : 0);
6779 }