2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written consent.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/kernel.h>
42 #include <sys/systm.h>
44 #include <sys/mutex.h>
46 #include <sys/module.h>
47 #include <sys/endian.h>
48 #include <sys/types.h>
49 #include <sys/malloc.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
57 #include <sys/bitstring.h>
58 #include <sys/limits.h>
59 #include <sys/queue.h>
60 #include <sys/taskqueue.h>
63 #include <net/if_types.h>
64 #include <net/if_arp.h>
65 #include <net/ethernet.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_var.h>
69 #include <net/if_vlan_var.h>
73 #include <netinet/in.h>
74 #include <netinet/ip.h>
75 #include <netinet/ip6.h>
76 #include <netinet/tcp.h>
77 #include <netinet/udp.h>
79 #include <dev/pci/pcireg.h>
80 #include <dev/pci/pcivar.h>
82 #include <machine/atomic.h>
83 #include <machine/resource.h>
84 #include <machine/endian.h>
85 #include <machine/bus.h>
86 #include <machine/in_cksum.h>
88 #include "device_if.h"
92 #if _BYTE_ORDER == _LITTLE_ENDIAN
96 #ifndef __LITTLE_ENDIAN
97 #define __LITTLE_ENDIAN
101 #else /* _BIG_ENDIAN */
109 #undef __LITTLE_ENDIAN
112 #include "ecore_mfw_req.h"
113 #include "ecore_fw_defs.h"
114 #include "ecore_hsi.h"
115 #include "ecore_reg.h"
117 #include "bxe_stats.h"
119 #include "bxe_elink.h"
121 #if __FreeBSD_version < 800054
122 #if defined(__i386__) || defined(__amd64__)
123 #define mb() __asm volatile("mfence;" : : : "memory")
124 #define wmb() __asm volatile("sfence;" : : : "memory")
125 #define rmb() __asm volatile("lfence;" : : : "memory")
126 static __inline void prefetch(void *x)
128 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
138 #if __FreeBSD_version >= 1000000
139 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
140 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
141 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
142 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
143 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
144 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
145 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
146 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
150 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
153 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
156 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
159 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
166 while (x >>= 1) log++;
169 #define ilog2(x) bxe_ilog2(x)
172 #include "ecore_sp.h"
174 #define BRCM_VENDORID 0x14e4
175 #define PCI_ANY_ID (uint16_t)(~0U)
177 struct bxe_device_type
186 #define BCM_PAGE_SHIFT 12
187 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
188 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
189 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
191 #if BCM_PAGE_SIZE != 4096
192 #error Page sizes other than 4KB are unsupported!
195 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
196 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
197 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
199 #define U64_LO(addr) ((uint32_t)(addr))
200 #define U64_HI(addr) (0)
202 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
204 #define SET_FLAG(value, mask, flag) \
206 (value) &= ~(mask); \
207 (value) |= ((flag) << (mask##_SHIFT)); \
210 #define GET_FLAG(value, mask) \
211 (((value) & (mask)) >> (mask##_SHIFT))
213 #define GET_FIELD(value, fname) \
214 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
216 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */
217 #define BXE_TSO_MAX_SEGMENTS 32
218 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header))
219 #define BXE_TSO_MAX_SEG_SIZE 4096
221 /* dropless fc FW/HW related params */
222 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
223 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \
224 ETH_MAX_AGGREGATION_QUEUES_E1 : \
225 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
226 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
227 #define FW_PREFETCH_CNT 16
228 #define DROPLESS_FC_HEADROOM 100
234 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */
235 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
236 #define RX_SGE_NEXT_PAGE_DESC_CNT 2
237 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT)
238 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1)
239 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES)
240 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)
241 #define RX_SGE_MAX (RX_SGE_TOTAL - 1)
242 #define RX_SGE(x) ((x) & RX_SGE_MAX)
244 #define RX_SGE_NEXT(x) \
245 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \
246 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1)
248 #define RX_SGE_MASK_ELEM_SZ 64
249 #define RX_SGE_MASK_ELEM_SHIFT 6
250 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1)
253 * Creates a bitmask of all ones in less significant bits.
254 * idx - index of the most significant bit in the created mask.
256 #define RX_SGE_ONES_MASK(idx) \
257 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
258 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0))
260 /* Number of uint64_t elements in SGE mask array. */
261 #define RX_SGE_MASK_LEN \
262 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ)
263 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
264 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
267 * dropless fc calculations for SGEs
268 * Number of required SGEs is the sum of two:
269 * 1. Number of possible opened aggregations (next packet for
270 * these aggregations will probably consume SGE immidiatelly)
271 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
272 * after placement on BD for new TPA aggregation)
273 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page
275 #define NUM_SGE_REQ(sc) \
276 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2)
277 #define NUM_SGE_PG_REQ(sc) \
278 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE)
279 #define SGE_TH_LO(sc) \
280 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT)
281 #define SGE_TH_HI(sc) \
282 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM)
284 #define PAGES_PER_SGE_SHIFT 0
285 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
286 #define SGE_PAGE_SIZE BCM_PAGE_SIZE
287 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT
288 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr)
289 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
290 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff)
296 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */
297 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
298 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1)
299 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES)
300 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES)
301 #define TX_BD_MAX (TX_BD_TOTAL - 1)
303 #define TX_BD_NEXT(x) \
304 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \
305 ((x) + 2) : ((x) + 1))
306 #define TX_BD(x) ((x) & TX_BD_MAX)
307 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8)
308 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE)
311 * Trigger pending transmits when the number of available BDs is greater
312 * than 1/8 of the total number of usable BDs.
314 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8)
315 #define BXE_TX_TIMEOUT 5
321 #define RX_BD_NUM_PAGES 8 /* power of 2 */
322 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
323 #define RX_BD_NEXT_PAGE_DESC_CNT 2
324 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT)
325 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1)
326 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES)
327 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES)
328 #define RX_BD_MAX (RX_BD_TOTAL - 1)
331 #define NUM_RX_RINGS RX_BD_NUM_PAGES
332 #define NUM_RX_BD RX_BD_TOTAL
333 #define MAX_RX_BD RX_BD_MAX
334 #define MAX_RX_AVAIL RX_BD_USABLE
337 #define RX_BD_NEXT(x) \
338 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \
339 ((x) + 3) : ((x) + 1))
340 #define RX_BD(x) ((x) & RX_BD_MAX)
341 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
342 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
345 * dropless fc calculations for BDs
346 * Number of BDs should be as number of buffers in BRB:
347 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
348 * "next" elements on each page
350 #define NUM_BD_REQ(sc) \
352 #define NUM_BD_PG_REQ(sc) \
353 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE)
354 #define BD_TH_LO(sc) \
356 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
358 #define BD_TH_HI(sc) \
359 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
360 #define MIN_RX_AVAIL(sc) \
361 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
362 #define MIN_RX_SIZE_TPA_HW(sc) \
363 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \
364 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
365 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
366 #define MIN_RX_SIZE_TPA(sc) \
367 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc)))
368 #define MIN_RX_SIZE_NONTPA(sc) \
369 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc)))
376 * As long as CQE is X times bigger than BD entry we have to allocate X times
377 * more pages for CQ ring in order to keep it balanced with BD ring
379 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \
380 sizeof(struct eth_rx_bd))
381 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */
382 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
383 #define RCQ_NEXT_PAGE_DESC_CNT 1
384 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT)
385 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES)
386 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES)
387 #define RCQ_MAX (RCQ_TOTAL - 1)
389 #define RCQ_NEXT(x) \
390 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \
391 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1))
392 #define RCQ(x) ((x) & RCQ_MAX)
393 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7)
394 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE)
397 #define NUM_RCQ_RINGS RCQ_NUM_PAGES
398 #define NUM_RCQ_BD RCQ_TOTAL
399 #define MAX_RCQ_BD RCQ_MAX
400 #define MAX_RCQ_AVAIL RCQ_USABLE
404 * dropless fc calculations for RCQs
405 * Number of RCQs should be as number of buffers in BRB:
406 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
407 * "next" elements on each page
409 #define NUM_RCQ_REQ(sc) \
411 #define NUM_RCQ_PG_REQ(sc) \
412 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE)
413 #define RCQ_TH_LO(sc) \
415 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
417 #define RCQ_TH_HI(sc) \
418 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
420 /* This is needed for determening of last_max */
421 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b))
423 #define __SGE_MASK_SET_BIT(el, bit) \
425 (el) = ((el) | ((uint64_t)0x1 << (bit))); \
428 #define __SGE_MASK_CLEAR_BIT(el, bit) \
430 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \
433 #define SGE_MASK_SET_BIT(fp, idx) \
434 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
435 ((idx) & RX_SGE_MASK_ELEM_MASK))
437 #define SGE_MASK_CLEAR_BIT(fp, idx) \
438 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
439 ((idx) & RX_SGE_MASK_ELEM_MASK))
441 /* Load / Unload modes */
442 #define LOAD_NORMAL 0
445 #define LOAD_LOOPBACK_EXT 3
446 #define UNLOAD_NORMAL 0
447 #define UNLOAD_CLOSE 1
448 #define UNLOAD_RECOVERY 2
450 /* Some constants... */
451 //#define MAX_PATH_NUM 2
452 //#define E2_MAX_NUM_OF_VFS 64
453 //#define E1H_FUNC_MAX 8
454 //#define E2_FUNC_MAX 4 /* per path */
455 #define MAX_VNIC_NUM 4
456 #define MAX_FUNC_NUM 8 /* common to all chips */
457 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
458 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
459 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
461 #define ILT_NUM_PAGE_ENTRIES 3072
463 * 57710/11 we use whole table since we have 8 functions.
464 * 57712 we have only 4 functions, but use same size per func, so only half
465 * of the table is used.
467 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
468 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
470 * the phys address is shifted right 12 bits and has an added
471 * 1=valid bit added to the 53rd bit
472 * then since this is a wide register(TM)
473 * we split it into two 32 bit writes
475 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
476 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
478 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
480 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
481 #define ETH_MIN_PACKET_SIZE 60
482 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
483 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
484 /* TCP with Timestamp Option (32) + IPv6 (40) */
485 #define ETH_MAX_TPA_HEADER_SIZE 72
487 /* max supported alignment is 256 (8 shift) */
488 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8)
489 #define BXE_RX_ALIGN_SHIFT 8
490 /* FW uses 2 cache lines alignment for start packet and size */
491 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT)
492 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT)
494 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */
497 struct resource *resource;
500 bus_space_handle_t handle;
505 struct resource *resource;
510 /* Used to manage DMA allocations. */
512 struct bxe_softc *sc;
517 bus_dma_segment_t seg;
523 /* attn group wiring */
524 #define MAX_DYNAMIC_ATTN_GRPS 8
538 union bxe_host_hc_status_block {
539 /* pointer to fp status block e2 */
540 struct host_hc_status_block_e2 *e2_sb;
541 /* pointer to fp status block e1x */
542 struct host_hc_status_block_e1x *e1x_sb;
546 struct doorbell_set_prod data;
550 struct bxe_sw_tx_bd {
555 /* set on the first BD descriptor when there is a split BD */
556 #define BXE_TSO_SPLIT_BD (1 << 0)
559 struct bxe_sw_rx_bd {
564 struct bxe_sw_tpa_info {
565 struct bxe_sw_rx_bd bd;
566 bus_dma_segment_t seg;
568 #define BXE_TPA_STATE_START 1
569 #define BXE_TPA_STATE_STOP 2
570 uint8_t placement_offset;
571 uint16_t parsing_flags;
577 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
578 * instances of the fastpath structure when using multiple queues.
580 struct bxe_fastpath {
581 /* pointer back to parent structure */
582 struct bxe_softc *sc;
585 char tx_mtx_name[32];
587 char rx_mtx_name[32];
589 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx)
590 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx)
591 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED)
593 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx)
594 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx)
595 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED)
598 struct bxe_dma sb_dma;
599 union bxe_host_hc_status_block status_block;
601 /* transmit chain (tx bds) */
602 struct bxe_dma tx_dma;
603 union eth_tx_bd_types *tx_chain;
605 /* receive chain (rx bds) */
606 struct bxe_dma rx_dma;
607 struct eth_rx_bd *rx_chain;
609 /* receive completion queue chain (rcq bds) */
610 struct bxe_dma rcq_dma;
611 union eth_rx_cqe *rcq_chain;
613 /* receive scatter/gather entry chain (for TPA) */
614 struct bxe_dma rx_sge_dma;
615 struct eth_rx_sge *rx_sge_chain;
618 bus_dma_tag_t tx_mbuf_tag;
619 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL];
622 bus_dma_tag_t rx_mbuf_tag;
623 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL];
624 bus_dmamap_t rx_mbuf_spare_map;
627 bus_dma_tag_t rx_sge_mbuf_tag;
628 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL];
629 bus_dmamap_t rx_sge_mbuf_spare_map;
631 /* rx tpa mbufs (use the larger size for TPA queue length) */
632 int tpa_enable; /* disabled per fastpath upon error */
633 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
634 bus_dmamap_t rx_tpa_info_mbuf_spare_map;
635 uint64_t rx_tpa_queue_used;
637 bus_dmamap_t rx_tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
638 bus_dmamap_t rx_tpa_mbuf_spare_map;
639 struct mbuf *rx_tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
640 bus_dma_segment_t rx_tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
642 uint8_t tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
645 uint16_t *sb_index_values;
646 uint16_t *sb_running_index;
647 uint32_t ustorm_rx_prods_offset;
649 uint8_t igu_sb_id; /* status block number in HW */
650 uint8_t fw_sb_id; /* status block number in FW */
652 uint32_t rx_buf_size;
656 #define BXE_FP_STATE_CLOSED 0x01
657 #define BXE_FP_STATE_IRQ 0x02
658 #define BXE_FP_STATE_OPENING 0x04
659 #define BXE_FP_STATE_OPEN 0x08
660 #define BXE_FP_STATE_HALTING 0x10
661 #define BXE_FP_STATE_HALTED 0x20
663 /* reference back to this fastpath queue number */
664 uint8_t index; /* this is also the 'cid' */
665 #define FP_IDX(fp) (fp->index)
667 /* interrupt taskqueue (fast) */
669 struct taskqueue *tq;
672 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
674 #define FP_CL_ID(fp) (fp->cl_id)
679 /* driver copy of the receive buffer descriptor prod/cons indices */
683 /* driver copy of the receive completion queue prod/cons indices */
687 union bxe_db_prod tx_db;
689 /* Transmit packet producer index (used in eth_tx_bd). */
690 uint16_t tx_pkt_prod;
691 uint16_t tx_pkt_cons;
693 /* Transmit buffer descriptor producer index. */
698 /* status block number in hardware */
700 #define FP_SB_ID(fp) (fp->sb_id)
702 /* driver copy of the fastpath CSTORM/USTORM indices */
707 uint64_t sge_mask[RX_SGE_MASK_LEN];
708 uint16_t rx_sge_prod;
710 struct tstorm_per_queue_stats old_tclient;
711 struct ustorm_per_queue_stats old_uclient;
712 struct xstorm_per_queue_stats old_xclient;
713 struct bxe_eth_q_stats eth_q_stats;
714 struct bxe_eth_q_stats_old eth_q_stats_old;
716 /* Pointer to the receive consumer in the status block */
717 uint16_t *rx_cq_cons_sb;
719 /* Pointer to the transmit consumer in the status block */
720 uint16_t *tx_cons_sb;
722 /* transmit timeout until chip reset */
725 /* Free/used buffer descriptor counters. */
726 //uint16_t used_tx_bd;
728 /* Last maximal completed SGE */
729 uint16_t last_max_sge;
731 //uint16_t rx_sge_free_idx;
735 #if __FreeBSD_version >= 800000
736 #define BXE_BR_SIZE 4096
737 struct buf_ring *tx_br;
739 }; /* struct bxe_fastpath */
742 #define BXE_MAX_NUM_OF_VFS 64
743 #define BXE_VF_CID_WND 0
744 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND)
745 #define BXE_CLIENTS_PER_VF 1
746 #define BXE_FIRST_VF_CID 256
747 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF)
748 #define BXE_VF_ID_INVALID 0xFF
749 #define IS_SRIOV(sc) 0
751 /* maximum number of fast-path interrupt contexts */
752 #define FP_SB_MAX_E1x 16
753 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
756 struct eth_context eth;
760 /* CDU host DB constants */
761 #define CDU_ILT_PAGE_SZ_HW 2
762 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
763 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
765 #define CNIC_ISCSI_CID_MAX 256
766 #define CNIC_FCOE_CID_MAX 2048
767 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
768 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
770 #define QM_ILT_PAGE_SZ_HW 0
771 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
772 #define QM_CID_ROUND 1024
774 /* TM (timers) host DB constants */
775 #define TM_ILT_PAGE_SZ_HW 0
776 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
777 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
778 #define TM_CONN_NUM 1024
779 #define TM_ILT_SZ (8 * TM_CONN_NUM)
780 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
782 /* SRC (Searcher) host DB constants */
783 #define SRC_ILT_PAGE_SZ_HW 0
784 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
785 #define SRC_HASH_BITS 10
786 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
787 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
788 #define SRC_T2_SZ SRC_ILT_SZ
789 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
792 struct bxe_dma vcxt_dma;
793 union cdu_context *vcxt;
794 //bus_addr_t cxt_mapping;
801 /* defines for multiple tx priority indices */
802 #define FIRST_TX_ONLY_COS_INDEX 1
803 #define FIRST_TX_COS_INDEX 0
805 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc))
807 #define HC_INDEX_ETH_RX_CQ_CONS 1
808 #define HC_INDEX_OOO_TX_CQ_CONS 4
809 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
810 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
811 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
812 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
814 /* congestion management fairness mode */
815 #define CMNG_FNS_NONE 0
816 #define CMNG_FNS_MINMAX 1
818 /* CMNG constants, as derived from system spec calculations */
819 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
820 #define DEF_MIN_RATE 100
821 /* resolution of the rate shaping timer - 400 usec */
822 #define RS_PERIODIC_TIMEOUT_USEC 400
823 /* number of bytes in single QM arbitration cycle -
824 * coefficient for calculating the fairness timer */
825 #define QM_ARB_BYTES 160000
826 /* resolution of Min algorithm 1:100 */
828 /* how many bytes above threshold for the minimal credit of Min algorithm*/
829 #define MIN_ABOVE_THRESH 32768
830 /* fairness algorithm integration time coefficient -
831 * for calculating the actual Tfair */
832 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
833 /* memory of fairness algorithm - 2 cycles */
836 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
837 #define HC_SEG_ACCESS_ATTN 4
838 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
841 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
842 * control by the number of fast-path status blocks supported by the
843 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
844 * status block represents an independent interrupts context that can
845 * serve a regular L2 networking queue. However special L2 queues such
846 * as the FCoE queue do not require a FP-SB and other components like
847 * the CNIC may consume FP-SB reducing the number of possible L2 queues
849 * If the maximum number of FP-SB available is X then:
850 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
851 * regular L2 queues is Y=X-1
852 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
853 * c. If the FCoE L2 queue is supported the actual number of L2 queues
855 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
856 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
857 * FP interrupt context for the CNIC).
858 * e. The number of HW context (CID count) is always X or X+1 if FCoE
859 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
861 * So this is quite simple for now as no ULPs are supported yet. :-)
863 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues)
864 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc)
865 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc)
866 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc)
868 #define FOR_EACH_QUEUE(sc, var) \
869 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++)
871 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
872 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++)
874 #define FOR_EACH_ETH_QUEUE(sc, var) \
875 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
877 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
878 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
880 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
881 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
883 #define FOR_EACH_CNIC_QUEUE(sc, var) \
884 for ((var) = BXE_NUM_ETH_QUEUES(sc); \
885 (var) < BXE_NUM_QUEUES(sc); \
894 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
895 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
896 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var)
897 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
898 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var)
899 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
901 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
902 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
903 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var)
904 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
905 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var)
907 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
908 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
909 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var)
910 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
911 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var)
912 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
914 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc))
915 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
916 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
917 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
918 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
919 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
920 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
926 BXE_FIRST_QUEUE_QUERY_IDX,
929 struct bxe_fw_stats_req {
930 struct stats_query_header hdr;
931 struct stats_query_entry query[FP_SB_MAX_E1x +
932 BXE_FIRST_QUEUE_QUERY_IDX];
935 struct bxe_fw_stats_data {
936 struct stats_counter storm_counters;
937 struct per_port_stats port;
938 struct per_pf_stats pf;
939 //struct fcoe_statistics_params fcoe;
940 struct per_queue_stats queue_stats[1];
943 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
944 #define BXE_IGU_STAS_MSG_VF_CNT 64
945 #define BXE_IGU_STAS_MSG_PF_CNT 4
950 * For the main interface up/down code paths, a not-so-fine-grained CORE
951 * mutex lock is used. Inside this code are various calls to kernel routines
952 * that can cause a sleep to occur. Namely memory allocations and taskqueue
953 * handling. If using an MTX lock we are *not* allowed to sleep but we can
954 * with an SX lock. This define forces the CORE lock to use and SX lock.
955 * Undefine this and an MTX lock will be used instead. Note that the IOCTL
956 * path can cause problems since it's called by a non-sleepable thread. To
957 * alleviate a potential sleep, any IOCTL processing that results in the
958 * chip/interface being started/stopped/reinitialized, the actual work is
959 * offloaded to a taskqueue.
961 #define BXE_CORE_LOCK_SX
964 * This is the slowpath data structure. It is mapped into non-paged memory
965 * so that the hardware can access it's contents directly and must be page
968 struct bxe_slowpath {
972 * The cdu_context array MUST be the first element in this
973 * structure. It is used during the leading edge ramrod
976 union cdu_context context[MAX_CONTEXT];
978 /* Used as a DMA source for MAC configuration. */
979 struct mac_configuration_cmd mac_config;
980 struct mac_configuration_cmd mcast_config;
983 /* used by the DMAE command executer */
984 struct dmae_command dmae[MAX_DMAE_C];
986 /* statistics completion */
989 /* firmware defined statistics blocks */
990 union mac_stats mac_stats;
991 struct nig_stats nig_stats;
992 struct host_port_stats port_stats;
993 struct host_func_stats func_stats;
994 //struct host_func_stats func_stats_base;
996 /* DMAE completion value and data source/sink */
1001 struct mac_configuration_cmd e1x;
1002 struct eth_classify_rules_ramrod_data e2;
1006 struct tstorm_eth_mac_filter_config e1x;
1007 struct eth_filter_rules_ramrod_data e2;
1010 struct eth_rss_update_ramrod_data rss_rdata;
1013 struct mac_configuration_cmd e1;
1014 struct eth_multicast_rules_ramrod_data e2;
1018 struct function_start_data func_start;
1019 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
1022 /* Queue State related ramrods */
1024 struct client_init_ramrod_data init_data;
1025 struct client_update_ramrod_data update_data;
1029 * AFEX ramrod can not be a part of func_rdata union because these
1030 * events might arrive in parallel to other events from func_rdata.
1031 * If they were defined in the same union the data can get corrupted.
1033 struct afex_vif_list_ramrod_data func_afex_rdata;
1035 union drv_info_to_mcp drv_info_to_mcp;
1036 }; /* struct bxe_slowpath */
1039 * Port specifc data structure.
1043 * Port Management Function (for 57711E only).
1044 * When this field is set the driver instance is
1045 * responsible for managing port specifc
1046 * configurations such as handling link attentions.
1050 /* Ethernet maximum transmission unit. */
1053 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
1055 uint32_t ext_phy_config;
1057 /* Port feature config.*/
1060 /* Defines the features supported by the PHY. */
1061 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
1063 /* Defines the features advertised by the PHY. */
1064 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
1065 #define ADVERTISED_10baseT_Half (1 << 1)
1066 #define ADVERTISED_10baseT_Full (1 << 2)
1067 #define ADVERTISED_100baseT_Half (1 << 3)
1068 #define ADVERTISED_100baseT_Full (1 << 4)
1069 #define ADVERTISED_1000baseT_Half (1 << 5)
1070 #define ADVERTISED_1000baseT_Full (1 << 6)
1071 #define ADVERTISED_TP (1 << 7)
1072 #define ADVERTISED_FIBRE (1 << 8)
1073 #define ADVERTISED_Autoneg (1 << 9)
1074 #define ADVERTISED_Asym_Pause (1 << 10)
1075 #define ADVERTISED_Pause (1 << 11)
1076 #define ADVERTISED_2500baseX_Full (1 << 15)
1077 #define ADVERTISED_10000baseT_Full (1 << 16)
1081 /* Used to synchronize phy accesses. */
1083 char phy_mtx_name[32];
1085 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx)
1086 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx)
1087 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED)
1090 * MCP scratchpad address for port specific statistics.
1091 * The device is responsible for writing statistcss
1092 * back to the MCP for use with management firmware such
1097 struct nig_stats old_nig_stats;
1098 }; /* struct bxe_port */
1100 struct bxe_mf_info {
1101 uint32_t mf_config[E1HVN_MAX];
1103 uint32_t vnics_per_port; /* 1, 2 or 4 */
1104 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
1105 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
1107 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
1108 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
1109 #define VNICS_PER_PATH(sc) \
1110 ((sc)->devinfo.mf_info.vnics_per_port * \
1111 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
1113 uint8_t min_bw[MAX_VNIC_NUM];
1114 uint8_t max_bw[MAX_VNIC_NUM];
1116 uint16_t ext_id; /* vnic outer vlan or VIF ID */
1117 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
1118 #define INVALID_VIF_ID 0xFFFF
1119 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
1120 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
1122 uint16_t default_vlan;
1123 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
1125 uint8_t niv_allowed_priorities;
1126 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
1128 uint8_t niv_default_cos;
1129 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
1131 uint8_t niv_mba_enabled;
1133 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1134 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
1135 int afex_def_vlan_tag;
1136 uint32_t pending_max;
1139 #define MF_INFO_VALID_MAC 0x0001
1141 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
1143 (IS_MULTI_VNIC(sc) && \
1144 ((sc)->devinfo.mf_info.mf_mode != 0))
1145 #define IS_MF_SD(sc) \
1146 (IS_MULTI_VNIC(sc) && \
1147 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
1148 #define IS_MF_SI(sc) \
1149 (IS_MULTI_VNIC(sc) && \
1150 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
1151 #define IS_MF_AFEX(sc) \
1152 (IS_MULTI_VNIC(sc) && \
1153 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
1154 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
1155 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
1156 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
1158 uint32_t mf_protos_supported;
1159 #define MF_PROTO_SUPPORT_ETHERNET 0x1
1160 #define MF_PROTO_SUPPORT_ISCSI 0x2
1161 #define MF_PROTO_SUPPORT_FCOE 0x4
1162 }; /* struct bxe_mf_info */
1164 /* Device information data structure. */
1165 struct bxe_devinfo {
1169 uint16_t subvendor_id;
1170 uint16_t subdevice_id;
1173 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
1174 * C = Chip Number (bits 16-31)
1175 * R = Chip Revision (bits 12-15)
1176 * M = Chip Metal (bits 4-11)
1177 * B = Chip Bond ID (bits 0-3)
1180 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
1181 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
1183 #define CHIP_NUM_57710 0x164e
1184 #define CHIP_NUM_57711 0x164f
1185 #define CHIP_NUM_57711E 0x1650
1186 #define CHIP_NUM_57712 0x1662
1187 #define CHIP_NUM_57712_MF 0x1663
1188 #define CHIP_NUM_57712_VF 0x166f
1189 #define CHIP_NUM_57800 0x168a
1190 #define CHIP_NUM_57800_MF 0x16a5
1191 #define CHIP_NUM_57800_VF 0x16a9
1192 #define CHIP_NUM_57810 0x168e
1193 #define CHIP_NUM_57810_MF 0x16ae
1194 #define CHIP_NUM_57810_VF 0x16af
1195 #define CHIP_NUM_57811 0x163d
1196 #define CHIP_NUM_57811_MF 0x163e
1197 #define CHIP_NUM_57811_VF 0x163f
1198 #define CHIP_NUM_57840_OBS 0x168d
1199 #define CHIP_NUM_57840_OBS_MF 0x16ab
1200 #define CHIP_NUM_57840_4_10 0x16a1
1201 #define CHIP_NUM_57840_2_20 0x16a2
1202 #define CHIP_NUM_57840_MF 0x16a4
1203 #define CHIP_NUM_57840_VF 0x16ad
1205 #define CHIP_REV_SHIFT 12
1206 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1207 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
1209 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1210 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1211 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
1213 #define CHIP_REV_IS_SLOW(sc) \
1214 (CHIP_REV(sc) > 0x00005000)
1215 #define CHIP_REV_IS_FPGA(sc) \
1216 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
1217 #define CHIP_REV_IS_EMUL(sc) \
1218 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
1219 #define CHIP_REV_IS_ASIC(sc) \
1220 (!CHIP_REV_IS_SLOW(sc))
1222 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
1223 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
1225 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1226 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1227 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
1228 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
1229 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
1230 (CHIP_IS_57711E(sc)))
1231 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \
1234 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
1235 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
1236 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
1237 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
1238 CHIP_IS_57712_MF(sc))
1240 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
1241 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
1242 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
1243 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
1244 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
1245 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
1246 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
1247 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
1248 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
1249 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
1250 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
1251 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
1252 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
1253 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
1254 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
1256 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
1257 CHIP_IS_57800_MF(sc) || \
1258 CHIP_IS_57800_VF(sc) || \
1259 CHIP_IS_57810(sc) || \
1260 CHIP_IS_57810_MF(sc) || \
1261 CHIP_IS_57810_VF(sc) || \
1262 CHIP_IS_57811(sc) || \
1263 CHIP_IS_57811_MF(sc) || \
1264 CHIP_IS_57811_VF(sc) || \
1265 CHIP_IS_57840(sc) || \
1266 CHIP_IS_57840_MF(sc) || \
1267 CHIP_IS_57840_VF(sc))
1268 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
1269 (CHIP_REV(sc) == CHIP_REV_Ax))
1270 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
1271 (CHIP_REV(sc) == CHIP_REV_Bx))
1273 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
1274 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
1277 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
1278 CHIP_IS_57712_MF(sc) || \
1281 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \
1282 CHIP_IS_57800_VF(sc) || \
1283 CHIP_IS_57810_VF(sc) || \
1284 CHIP_IS_57840_VF(sc))
1285 #define IS_PF(sc) (!IS_VF(sc))
1288 * This define is used in two main places:
1289 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
1290 * to nic-only mode or to offload mode. Offload mode is configured if either
1291 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
1292 * already registered for this port (which means that the user wants storage
1294 * 2. During cnic-related load, to know if offload mode is already configured
1295 * in the HW or needs to be configrued. Since the transition from nic-mode to
1296 * offload-mode in HW causes traffic coruption, nic-mode is configured only
1297 * in ports on which storage services where never requested.
1299 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
1301 uint8_t chip_port_mode;
1302 #define CHIP_4_PORT_MODE 0x0
1303 #define CHIP_2_PORT_MODE 0x1
1304 #define CHIP_PORT_MODE_NONE 0x2
1305 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
1306 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
1309 #define INT_BLOCK_HC 0
1310 #define INT_BLOCK_IGU 1
1311 #define INT_BLOCK_MODE_NORMAL 0
1312 #define INT_BLOCK_MODE_BW_COMP 2
1313 #define CHIP_INT_MODE_IS_NBC(sc) \
1314 (!CHIP_IS_E1x(sc) && \
1315 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
1316 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
1318 uint32_t shmem_base;
1319 uint32_t shmem2_base;
1321 char bc_ver_str[32];
1322 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
1323 struct bxe_mf_info mf_info;
1326 #define NVRAM_1MB_SIZE 0x20000
1327 #define NVRAM_TIMEOUT_COUNT 30000
1328 #define NVRAM_PAGE_SIZE 256
1330 /* PCIe capability information */
1331 uint32_t pcie_cap_flags;
1332 #define BXE_PM_CAPABLE_FLAG 0x00000001
1333 #define BXE_PCIE_CAPABLE_FLAG 0x00000002
1334 #define BXE_MSI_CAPABLE_FLAG 0x00000004
1335 #define BXE_MSIX_CAPABLE_FLAG 0x00000008
1336 uint16_t pcie_pm_cap_reg;
1337 uint16_t pcie_pcie_cap_reg;
1338 //uint16_t pcie_devctl;
1339 uint16_t pcie_link_width;
1340 uint16_t pcie_link_speed;
1341 uint16_t pcie_msi_cap_reg;
1342 uint16_t pcie_msix_cap_reg;
1344 /* device configuration read from bootcode shared memory */
1346 uint32_t hw_config2;
1347 }; /* struct bxe_devinfo */
1349 struct bxe_sp_objs {
1350 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
1351 struct ecore_queue_sp_obj q_obj; /* Queue State object */
1352 }; /* struct bxe_sp_objs */
1355 * Data that will be used to create a link report message. We will keep the
1356 * data used for the last link report in order to prevent reporting the same
1357 * link parameters twice.
1359 struct bxe_link_report_data {
1360 uint16_t line_speed; /* Effective line speed */
1361 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */
1364 BXE_LINK_REPORT_FULL_DUPLEX,
1365 BXE_LINK_REPORT_LINK_DOWN,
1366 BXE_LINK_REPORT_RX_FC_ON,
1367 BXE_LINK_REPORT_TX_FC_ON
1370 /* Top level device private data structure. */
1373 * First entry must be a pointer to the BSD ifnet struct which
1374 * has a first element of 'void *if_softc' (which is us).
1376 struct ifnet *ifnet;
1377 struct ifmedia ifmedia; /* network interface media structure */
1380 int state; /* device state */
1381 #define BXE_STATE_CLOSED 0x0000
1382 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000
1383 #define BXE_STATE_OPENING_WAITING_PORT 0x2000
1384 #define BXE_STATE_OPEN 0x3000
1385 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000
1386 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000
1387 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000
1388 #define BXE_STATE_DISABLED 0xD000
1389 #define BXE_STATE_DIAG 0xE000
1390 #define BXE_STATE_ERROR 0xF000
1393 #define BXE_ONE_PORT_FLAG 0x00000001
1394 #define BXE_NO_ISCSI 0x00000002
1395 #define BXE_NO_FCOE 0x00000004
1396 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG)
1397 //#define BXE_NO_WOL_FLAG 0x00000008
1398 //#define BXE_USING_DAC_FLAG 0x00000010
1399 //#define BXE_USING_MSIX_FLAG 0x00000020
1400 //#define BXE_USING_MSI_FLAG 0x00000040
1401 //#define BXE_DISABLE_MSI_FLAG 0x00000080
1402 #define BXE_NO_MCP_FLAG 0x00000200
1403 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG)
1404 //#define BXE_SAFC_TX_FLAG 0x00000400
1405 #define BXE_MF_FUNC_DIS 0x00000800
1406 #define BXE_TX_SWITCHING 0x00001000
1408 uint32_t debug; /* per-instance debug logging config */
1411 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1413 uint16_t doorbell_size;
1415 /* periodic timer callout */
1416 #define PERIODIC_STOP 0
1417 #define PERIODIC_GO 1
1418 volatile unsigned long periodic_flags;
1419 struct callout periodic_callout;
1421 /* chip start/stop/reset taskqueue */
1422 #define CHIP_TQ_NONE 0
1423 #define CHIP_TQ_START 1
1424 #define CHIP_TQ_STOP 2
1425 #define CHIP_TQ_REINIT 3
1426 volatile unsigned long chip_tq_flags;
1427 struct task chip_tq_task;
1428 struct taskqueue *chip_tq;
1429 char chip_tq_name[32];
1431 /* slowpath interrupt taskqueue */
1432 struct task sp_tq_task;
1433 struct taskqueue *sp_tq;
1434 char sp_tq_name[32];
1436 /* set rx_mode asynchronous taskqueue */
1437 struct task rx_mode_tq_task;
1438 struct taskqueue *rx_mode_tq;
1439 char rx_mode_tq_name[32];
1441 struct bxe_fastpath fp[MAX_RSS_CHAINS];
1442 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS];
1444 device_t dev; /* parent device handle */
1445 uint8_t unit; /* driver instance number */
1447 int pcie_bus; /* PCIe bus number */
1448 int pcie_device; /* PCIe device/slot number */
1449 int pcie_func; /* PCIe function number */
1451 uint8_t pfunc_rel; /* function relative */
1452 uint8_t pfunc_abs; /* function absolute */
1453 uint8_t path_id; /* function absolute */
1454 #define SC_PATH(sc) (sc->path_id)
1455 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1456 #define SC_FUNC(sc) (sc->pfunc_rel)
1457 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1458 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1459 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1460 #define PORT_ID(sc) SC_PORT(sc)
1461 #define PATH_ID(sc) SC_PATH(sc)
1462 #define VNIC_ID(sc) SC_VN(sc)
1463 #define FUNC_ID(sc) SC_FUNC(sc)
1464 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1465 #define SC_FW_MB_IDX_VN(sc, vn) \
1466 (SC_PORT(sc) + (vn) * \
1467 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1468 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1470 int if_capen; /* enabled interface capabilities */
1472 struct bxe_devinfo devinfo;
1473 char fw_ver_str[32];
1474 char mf_mode_str[32];
1475 char pci_link_str[32];
1477 const struct iro *iro_array;
1479 #ifdef BXE_CORE_LOCK_SX
1481 char core_sx_name[32];
1483 struct mtx core_mtx;
1484 char core_mtx_name[32];
1487 char sp_mtx_name[32];
1488 struct mtx dmae_mtx;
1489 char dmae_mtx_name[32];
1490 struct mtx fwmb_mtx;
1491 char fwmb_mtx_name[32];
1492 struct mtx print_mtx;
1493 char print_mtx_name[32];
1494 struct mtx stats_mtx;
1495 char stats_mtx_name[32];
1496 struct mtx mcast_mtx;
1497 char mcast_mtx_name[32];
1499 #ifdef BXE_CORE_LOCK_SX
1500 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx)
1501 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx)
1502 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx)
1503 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED)
1505 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx)
1506 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx)
1507 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx)
1508 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED)
1511 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx)
1512 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx)
1513 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED)
1515 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx)
1516 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx)
1517 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED)
1519 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx)
1520 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx)
1521 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED)
1523 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx)
1524 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx)
1525 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED)
1527 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx)
1528 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx)
1529 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED)
1531 #if __FreeBSD_version < 800000
1532 #define BXE_MCAST_LOCK(sc) \
1534 mtx_lock(&sc->mcast_mtx); \
1535 IF_ADDR_LOCK(sc->ifnet); \
1537 #define BXE_MCAST_UNLOCK(sc) \
1539 IF_ADDR_UNLOCK(sc->ifnet); \
1540 mtx_unlock(&sc->mcast_mtx); \
1543 #define BXE_MCAST_LOCK(sc) \
1545 mtx_lock(&sc->mcast_mtx); \
1546 if_maddr_rlock(sc->ifnet); \
1548 #define BXE_MCAST_UNLOCK(sc) \
1550 if_maddr_runlock(sc->ifnet); \
1551 mtx_unlock(&sc->mcast_mtx); \
1554 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED)
1557 #define DMAE_READY(sc) (sc->dmae_ready)
1559 struct ecore_credit_pool_obj vlans_pool;
1560 struct ecore_credit_pool_obj macs_pool;
1561 struct ecore_rx_mode_obj rx_mode_obj;
1562 struct ecore_mcast_obj mcast_obj;
1563 struct ecore_rss_config_obj rss_conf_obj;
1564 struct ecore_func_sp_obj func_obj;
1567 uint16_t fw_drv_pulse_wr_seq;
1570 struct elink_params link_params;
1571 struct elink_vars link_vars;
1573 struct bxe_link_report_data last_reported_link;
1574 char mac_addr_str[32];
1576 int last_reported_link_state;
1584 #define BXE_RECOVERY_DONE 1
1585 #define BXE_RECOVERY_INIT 2
1586 #define BXE_RECOVERY_WAIT 3
1587 #define BXE_RECOVERY_FAILED 4
1588 #define BXE_RECOVERY_NIC_LOADING 5
1591 #define BXE_RX_MODE_NONE 0
1592 #define BXE_RX_MODE_NORMAL 1
1593 #define BXE_RX_MODE_ALLMULTI 2
1594 #define BXE_RX_MODE_PROMISC 3
1595 #define BXE_MAX_MULTICAST 64
1597 struct bxe_port port;
1599 struct cmng_init cmng;
1607 int max_aggregation_size;
1610 #define AUTO_GREEN_HW_DEFAULT 0
1611 #define AUTO_GREEN_FORCE_ON 1
1612 #define AUTO_GREEN_FORCE_OFF 2
1614 #define INTR_MODE_INTX 0
1615 #define INTR_MODE_MSI 1
1616 #define INTR_MODE_MSIX 2
1619 /* interrupt allocations */
1620 struct bxe_intr intr[MAX_RSS_CHAINS+1];
1623 uint8_t igu_base_sb;
1625 //uint8_t min_msix_vec_cnt;
1626 uint32_t igu_base_addr;
1627 //bus_addr_t def_status_blk_mapping;
1628 uint8_t base_fw_ndsb;
1629 #define DEF_SB_IGU_ID 16
1630 #define DEF_SB_ID HC_SP_SB_ID
1632 /* parent bus DMA tag */
1633 bus_dma_tag_t parent_dma_tag;
1635 /* default status block */
1636 struct bxe_dma def_sb_dma;
1637 struct host_sp_status_block *def_sb;
1639 uint16_t def_att_idx;
1640 uint32_t attn_state;
1641 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1643 /* general SP events - stats query, cfc delete, etc */
1644 #define HC_SP_INDEX_ETH_DEF_CONS 3
1645 /* EQ completions */
1646 #define HC_SP_INDEX_EQ_CONS 7
1647 /* FCoE L2 connection completions */
1648 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1649 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1651 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1652 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1655 struct bxe_dma eq_dma;
1656 union event_ring_elem *eq;
1659 uint16_t *eq_cons_sb;
1660 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1661 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1662 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1663 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1664 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1665 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1666 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1667 #define NEXT_EQ_IDX(x) \
1668 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1669 ((x) + 2) : ((x) + 1))
1670 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1671 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1674 struct bxe_dma sp_dma;
1675 struct bxe_slowpath *sp;
1676 unsigned long sp_state;
1678 /* slow path queue */
1679 struct bxe_dma spq_dma;
1680 struct eth_spe *spq;
1681 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1682 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1683 #define MAX_SPQ_PENDING 8
1685 uint16_t spq_prod_idx;
1686 struct eth_spe *spq_prod_bd;
1687 struct eth_spe *spq_last_bd;
1688 uint16_t *dsb_sp_prod;
1689 //uint16_t *spq_hw_con;
1690 //uint16_t spq_left;
1692 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1693 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1695 /* fw decompression buffer */
1696 struct bxe_dma gz_buf_dma;
1700 #define GUNZIP_BUF(sc) (sc->gz_buf)
1701 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1702 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr)
1703 #define FW_BUF_SIZE 0x40000
1705 const struct raw_op *init_ops;
1706 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1707 const uint32_t *init_data; /* data blob, 32 bit granularity */
1708 uint32_t init_mode_flags;
1709 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1710 /* PRAM blobs - raw data */
1711 const uint8_t *tsem_int_table_data;
1712 const uint8_t *tsem_pram_data;
1713 const uint8_t *usem_int_table_data;
1714 const uint8_t *usem_pram_data;
1715 const uint8_t *xsem_int_table_data;
1716 const uint8_t *xsem_pram_data;
1717 const uint8_t *csem_int_table_data;
1718 const uint8_t *csem_pram_data;
1719 #define INIT_OPS(sc) (sc->init_ops)
1720 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1721 #define INIT_DATA(sc) (sc->init_data)
1722 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1723 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1724 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1725 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1726 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1727 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1728 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1729 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1732 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1733 * context size we need 8 ILT entries.
1735 #define ILT_MAX_L2_LINES 8
1736 struct hw_context context[ILT_MAX_L2_LINES];
1737 struct ecore_ilt *ilt;
1738 #define ILT_MAX_LINES 256
1740 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1741 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1742 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1744 #define BXE_L2_MAX_CID(sc) \
1745 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1747 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \
1748 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1751 #define BXE_L2_CID_COUNT(sc) \
1752 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1754 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \
1755 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1757 #define L2_ILT_LINES(sc) \
1758 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1762 uint8_t dropless_fc;
1768 /* total number of FW statistics requests */
1769 uint8_t fw_stats_num;
1771 * This is a memory buffer that will contain both statistics ramrod
1774 struct bxe_dma fw_stats_dma;
1776 * FW statistics request shortcut (points at the beginning of fw_stats
1779 int fw_stats_req_size;
1780 struct bxe_fw_stats_req *fw_stats_req;
1781 bus_addr_t fw_stats_req_mapping;
1783 * FW statistics data shortcut (points at the beginning of fw_stats
1784 * buffer + fw_stats_req_size).
1786 int fw_stats_data_size;
1787 struct bxe_fw_stats_data *fw_stats_data;
1788 bus_addr_t fw_stats_data_mapping;
1790 /* tracking a pending STAT_QUERY ramrod */
1791 uint16_t stats_pending;
1792 /* number of completed statistics ramrods */
1793 uint16_t stats_comp;
1794 uint16_t stats_counter;
1798 struct bxe_eth_stats eth_stats;
1799 struct host_func_stats func_stats;
1800 struct bxe_eth_stats_old eth_stats_old;
1801 struct bxe_net_stats_old net_stats_old;
1802 struct bxe_fw_port_stats_old fw_stats_old;
1804 struct dmae_command stats_dmae; /* used by dmae command loader */
1810 struct bxe_config_lldp_params lldp_config_params;
1811 /* DCB support on/off */
1813 #define BXE_DCB_STATE_OFF 0
1814 #define BXE_DCB_STATE_ON 1
1815 /* DCBX engine mode */
1817 #define BXE_DCBX_ENABLED_OFF 0
1818 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1
1819 #define BXE_DCBX_ENABLED_ON_NEG_ON 2
1820 #define BXE_DCBX_ENABLED_INVALID -1
1821 uint8_t dcbx_mode_uset;
1822 struct bxe_config_dcbx_params dcbx_config_params;
1823 struct bxe_dcbx_port_params dcbx_port_params;
1826 uint8_t cnic_support;
1827 uint8_t cnic_enabled;
1828 uint8_t cnic_loaded;
1829 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1830 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1831 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1833 /* multiple tx classes of service */
1835 #define BXE_MAX_PRIORITY 8
1836 /* priority to cos mapping */
1837 uint8_t prio_to_cos[BXE_MAX_PRIORITY];
1840 }; /* struct bxe_softc */
1842 /* IOCTL sub-commands for edebug and firmware upgrade */
1843 #define BXE_IOC_RD_NVRAM 1
1844 #define BXE_IOC_WR_NVRAM 2
1845 #define BXE_IOC_STATS_SHOW_NUM 3
1846 #define BXE_IOC_STATS_SHOW_STR 4
1847 #define BXE_IOC_STATS_SHOW_CNT 5
1849 struct bxe_nvram_data {
1850 uint32_t op; /* ioctl sub-command */
1853 uint32_t value[1]; /* variable */
1856 union bxe_stats_show_data {
1857 uint32_t op; /* ioctl sub-command */
1860 uint32_t num; /* return number of stats */
1861 uint32_t len; /* length of each string item */
1864 /* variable length... */
1865 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1867 /* variable length... */
1868 uint64_t stats[1]; /* holds all stats */
1871 /* function init flags */
1872 #define FUNC_FLG_RSS 0x0001
1873 #define FUNC_FLG_STATS 0x0002
1874 /* FUNC_FLG_UNMATCHED 0x0004 */
1875 #define FUNC_FLG_TPA 0x0008
1876 #define FUNC_FLG_SPQ 0x0010
1877 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1879 struct bxe_func_init_params {
1880 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1881 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1883 uint16_t func_id; /* abs function id */
1885 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1888 /* memory resources reside at BARs 0, 2, 4 */
1889 /* Run `pciconf -lb` to see mappings */
1894 #ifdef BXE_REG_NO_INLINE
1896 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset);
1897 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset);
1898 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset);
1900 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val);
1901 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val);
1902 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val);
1904 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset)
1905 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset)
1906 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset)
1908 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val)
1909 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val)
1910 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val)
1912 #else /* not BXE_REG_NO_INLINE */
1914 #define REG_WR8(sc, offset, val) \
1915 bus_space_write_1(sc->bar[BAR0].tag, \
1916 sc->bar[BAR0].handle, \
1919 #define REG_WR16(sc, offset, val) \
1920 bus_space_write_2(sc->bar[BAR0].tag, \
1921 sc->bar[BAR0].handle, \
1924 #define REG_WR32(sc, offset, val) \
1925 bus_space_write_4(sc->bar[BAR0].tag, \
1926 sc->bar[BAR0].handle, \
1929 #define REG_RD8(sc, offset) \
1930 bus_space_read_1(sc->bar[BAR0].tag, \
1931 sc->bar[BAR0].handle, \
1934 #define REG_RD16(sc, offset) \
1935 bus_space_read_2(sc->bar[BAR0].tag, \
1936 sc->bar[BAR0].handle, \
1939 #define REG_RD32(sc, offset) \
1940 bus_space_read_4(sc->bar[BAR0].tag, \
1941 sc->bar[BAR0].handle, \
1944 #endif /* BXE_REG_NO_INLINE */
1946 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1947 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1949 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset)
1950 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val)
1952 #define BXE_SP(sc, var) (&(sc)->sp->var)
1953 #define BXE_SP_MAPPING(sc, var) \
1954 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var))
1956 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1957 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1960 #define bxe_fp(sc, nr, var) ((sc)->fp[nr].var)
1961 #define bxe_sp_obj(sc, fp) ((sc)->sp_objs[(fp)->index])
1962 #define bxe_fp_stats(sc, fp) (&(sc)->fp_stats[(fp)->index])
1963 #define bxe_fp_qstats(sc, fp) (&(sc)->fp_stats[(fp)->index].eth_q_stats)
1966 #define REG_RD_DMAE(sc, offset, valp, len32) \
1968 bxe_read_dmae(sc, offset, len32); \
1969 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \
1972 #define REG_WR_DMAE(sc, offset, valp, len32) \
1974 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \
1975 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \
1978 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1979 REG_WR_DMAE(sc, offset, valp, len32)
1981 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1982 REG_RD_DMAE(sc, offset, valp, len32)
1984 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1986 /* if (le32_swap) { */ \
1987 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \
1989 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1990 ecore_write_big_buf_wb(sc, addr, len32); \
1993 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */
1994 #define BXE_DB_SHIFT 7 /* 128 bytes */
1995 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT)
1996 #error "Minimum DB doorbell stride is 8"
1998 #define DPM_TRIGGER_TYPE 0x40
1999 #define DOORBELL(sc, cid, val) \
2001 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \
2002 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \
2006 #define SHMEM_ADDR(sc, field) \
2007 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
2008 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
2009 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
2010 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
2012 #define SHMEM2_ADDR(sc, field) \
2013 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
2014 #define SHMEM2_HAS(sc, field) \
2015 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
2016 offsetof(struct shmem2_region, field)))
2017 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
2018 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
2020 #define MFCFG_ADDR(sc, field) \
2021 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
2022 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
2023 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
2024 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
2026 /* DMAE command defines */
2028 #define DMAE_TIMEOUT -1
2029 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2030 #define DMAE_NOT_RDY -3
2031 #define DMAE_PCI_ERR_FLAG 0x80000000
2033 #define DMAE_SRC_PCI 0
2034 #define DMAE_SRC_GRC 1
2036 #define DMAE_DST_NONE 0
2037 #define DMAE_DST_PCI 1
2038 #define DMAE_DST_GRC 2
2040 #define DMAE_COMP_PCI 0
2041 #define DMAE_COMP_GRC 1
2043 #define DMAE_COMP_REGULAR 0
2044 #define DMAE_COM_SET_ERR 1
2046 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
2047 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
2048 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
2049 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
2051 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
2052 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
2054 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2055 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2056 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2057 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2059 #define DMAE_CMD_PORT_0 0
2060 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2062 #define DMAE_SRC_PF 0
2063 #define DMAE_SRC_VF 1
2065 #define DMAE_DST_PF 0
2066 #define DMAE_DST_VF 1
2068 #define DMAE_C_SRC 0
2069 #define DMAE_C_DST 1
2071 #define DMAE_LEN32_RD_MAX 0x80
2072 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000)
2074 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
2076 #define MAX_DMAE_C_PER_PORT 8
2077 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
2078 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
2080 static const uint32_t dmae_reg_go_c[] = {
2081 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2082 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2083 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2084 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2087 #define ATTN_NIG_FOR_FUNC (1L << 8)
2088 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2089 #define GPIO_2_FUNC (1L << 10)
2090 #define GPIO_3_FUNC (1L << 11)
2091 #define GPIO_4_FUNC (1L << 12)
2092 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2093 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2094 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2095 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2096 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2097 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2098 #define ATTN_HARD_WIRED_MASK 0xff00
2099 #define ATTENTION_ID 4
2101 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
2102 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
2104 #define MAX_IGU_ATTN_ACK_TO 100
2106 #define STORM_ASSERT_ARRAY_SIZE 50
2108 #define BXE_PMF_LINK_ASSERT(sc) \
2109 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
2111 #define BXE_MC_ASSERT_BITS \
2112 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2113 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2114 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2115 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2117 #define BXE_MCP_ASSERT \
2118 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2120 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2121 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2122 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2123 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2124 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2125 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2126 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2128 #define MULTI_MASK 0x7f
2130 #define PFS_PER_PORT(sc) \
2131 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
2132 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
2134 #define FIRST_ABS_FUNC_IN_PORT(sc) \
2135 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
2136 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
2138 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
2139 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
2140 (i) < MAX_FUNC_NUM; \
2141 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
2143 #define BXE_SWCID_SHIFT 17
2144 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1)
2146 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK)
2147 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
2149 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
2150 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
2151 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
2152 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
2153 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
2155 /* must be used on a CID before placing it on a HW ring */
2156 #define HW_CID(sc, x) \
2157 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x))
2160 #define SPEED_100 100
2161 #define SPEED_1000 1000
2162 #define SPEED_2500 2500
2163 #define SPEED_10000 10000
2166 #define PCI_PM_D3hot 2
2168 int bxe_test_bit(int nr, volatile unsigned long * addr);
2169 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr);
2170 void bxe_clear_bit(int nr, volatile unsigned long * addr);
2171 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr);
2172 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr);
2173 int bxe_cmpxchg(volatile int *addr, int old, int new);
2175 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr,
2177 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr);
2180 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size,
2181 struct bxe_dma *dma, const char *msg);
2182 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma);
2184 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
2185 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode);
2186 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type,
2187 uint8_t dst_type, uint8_t with_comp,
2189 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int idx);
2190 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32);
2191 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr,
2192 uint32_t dst_addr, uint32_t len32);
2193 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr,
2194 uint32_t addr, uint32_t len);
2196 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt,
2198 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id,
2199 uint8_t sb_index, uint8_t disable,
2202 int bxe_sp_post(struct bxe_softc *sc, int command, int cid,
2203 uint32_t data_hi, uint32_t data_lo, int cmd_type);
2205 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id,
2206 uint8_t segment, uint16_t index, uint8_t op,
2209 void ecore_init_e1_firmware(struct bxe_softc *sc);
2210 void ecore_init_e1h_firmware(struct bxe_softc *sc);
2211 void ecore_init_e2_firmware(struct bxe_softc *sc);
2213 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr,
2214 size_t size, uint32_t *data);
2216 /*********************/
2217 /* LOGGING AND DEBUG */
2218 /*********************/
2220 /* debug logging codepaths */
2221 #define DBG_LOAD 0x00000001 /* load and unload */
2222 #define DBG_INTR 0x00000002 /* interrupt handling */
2223 #define DBG_SP 0x00000004 /* slowpath handling */
2224 #define DBG_STATS 0x00000008 /* stats updates */
2225 #define DBG_TX 0x00000010 /* packet transmit */
2226 #define DBG_RX 0x00000020 /* packet receive */
2227 #define DBG_PHY 0x00000040 /* phy/link handling */
2228 #define DBG_IOCTL 0x00000080 /* ioctl handling */
2229 #define DBG_MBUF 0x00000100 /* dumping mbuf info */
2230 #define DBG_REGS 0x00000200 /* register access */
2231 #define DBG_LRO 0x00000400 /* lro processing */
2232 #define DBG_ASSERT 0x80000000 /* debug assert */
2233 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */
2235 #define DBASSERT(sc, exp, msg) \
2237 if (__predict_false(sc->debug & DBG_ASSERT)) { \
2238 if (__predict_false(!(exp))) { \
2244 /* log a debug message */
2245 #define BLOGD(sc, codepath, format, args...) \
2247 if (__predict_false(sc->debug & (codepath))) { \
2248 device_printf((sc)->dev, \
2249 "%s(%s:%d) " format, \
2257 /* log a info message */
2258 #define BLOGI(sc, format, args...) \
2260 if (__predict_false(sc->debug)) { \
2261 device_printf((sc)->dev, \
2262 "%s(%s:%d) " format, \
2268 device_printf((sc)->dev, \
2274 /* log a warning message */
2275 #define BLOGW(sc, format, args...) \
2277 if (__predict_false(sc->debug)) { \
2278 device_printf((sc)->dev, \
2279 "%s(%s:%d) WARNING: " format, \
2285 device_printf((sc)->dev, \
2286 "WARNING: " format, \
2291 /* log a error message */
2292 #define BLOGE(sc, format, args...) \
2294 if (__predict_false(sc->debug)) { \
2295 device_printf((sc)->dev, \
2296 "%s(%s:%d) ERROR: " format, \
2302 device_printf((sc)->dev, \
2308 #define bxe_panic(sc, msg) \
2313 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
2314 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
2316 void bxe_dump_mem(struct bxe_softc *sc, char *tag,
2317 uint8_t *mem, uint32_t len);
2318 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag,
2319 struct mbuf *m, uint8_t contents);
2325 static inline uint32_t
2326 reg_poll(struct bxe_softc *sc,
2335 val = REG_RD(sc, reg);
2336 if (val == expected) {
2347 bxe_update_fp_sb_idx(struct bxe_fastpath *fp)
2349 mb(); /* status block is written to by the chip */
2350 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
2354 bxe_igu_ack_sb_gen(struct bxe_softc *sc,
2362 struct igu_regular cmd_data = {0};
2364 cmd_data.sb_id_and_flags =
2365 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
2366 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2367 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2368 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
2370 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n",
2371 cmd_data.sb_id_and_flags, igu_addr);
2372 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
2374 /* Make sure that ACK is written */
2375 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2376 BUS_SPACE_BARRIER_WRITE);
2381 bxe_hc_ack_sb(struct bxe_softc *sc,
2388 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2389 COMMAND_REG_INT_ACK);
2390 struct igu_ack_register igu_ack;
2392 igu_ack.status_block_index = index;
2393 igu_ack.sb_id_and_flags =
2394 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2395 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2396 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2397 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2399 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack));
2401 /* Make sure that ACK is written */
2402 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2403 BUS_SPACE_BARRIER_WRITE);
2408 bxe_ack_sb(struct bxe_softc *sc,
2415 if (sc->devinfo.int_block == INT_BLOCK_HC)
2416 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
2419 if (CHIP_INT_MODE_IS_BC(sc)) {
2421 } else if (igu_sb_id != sc->igu_dsb_id) {
2422 segment = IGU_SEG_ACCESS_DEF;
2423 } else if (storm == ATTENTION_ID) {
2424 segment = IGU_SEG_ACCESS_ATTN;
2426 segment = IGU_SEG_ACCESS_DEF;
2428 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
2432 static inline uint16_t
2433 bxe_hc_ack_int(struct bxe_softc *sc)
2435 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2436 COMMAND_REG_SIMD_MASK);
2437 uint32_t result = REG_RD(sc, hc_addr);
2443 static inline uint16_t
2444 bxe_igu_ack_int(struct bxe_softc *sc)
2446 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
2447 uint32_t result = REG_RD(sc, igu_addr);
2449 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n",
2456 static inline uint16_t
2457 bxe_ack_int(struct bxe_softc *sc)
2460 if (sc->devinfo.int_block == INT_BLOCK_HC) {
2461 return (bxe_hc_ack_int(sc));
2463 return (bxe_igu_ack_int(sc));
2468 func_by_vn(struct bxe_softc *sc,
2471 return (2 * vn + SC_PORT(sc));
2475 * Statistics ID are global per chip/path, while Client IDs for E1x
2478 static inline uint8_t
2479 bxe_stats_id(struct bxe_fastpath *fp)
2481 struct bxe_softc *sc = fp->sc;
2483 if (!CHIP_IS_E1x(sc)) {
2485 /* there are special statistics counters for FCoE 136..140 */
2486 if (IS_FCOE_FP(fp)) {
2487 return (sc->cnic_base_cl_id + (sc->pf_num >> 1));
2493 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);
2496 #endif /* __BXE_H__ */