2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written consent.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 #include "bxe_elink.h"
39 #include "ecore_mfw_req.h"
40 #include "ecore_fw_defs.h"
41 #include "ecore_hsi.h"
42 #include "ecore_reg.h"
45 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
46 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
47 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
48 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
49 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
51 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
52 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
53 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
54 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
55 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
56 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
57 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
58 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
59 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
60 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
61 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
62 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
63 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
64 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
65 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
66 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
67 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
69 #define MDIO_REG_BANK_RX0 0x80b0
70 #define MDIO_RX0_RX_STATUS 0x10
71 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
72 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
73 #define MDIO_RX0_RX_EQ_BOOST 0x1c
74 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
75 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
77 #define MDIO_REG_BANK_RX1 0x80c0
78 #define MDIO_RX1_RX_EQ_BOOST 0x1c
79 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
80 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
82 #define MDIO_REG_BANK_RX2 0x80d0
83 #define MDIO_RX2_RX_EQ_BOOST 0x1c
84 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
85 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
87 #define MDIO_REG_BANK_RX3 0x80e0
88 #define MDIO_RX3_RX_EQ_BOOST 0x1c
89 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
90 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
92 #define MDIO_REG_BANK_RX_ALL 0x80f0
93 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
94 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
95 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
97 #define MDIO_REG_BANK_TX0 0x8060
98 #define MDIO_TX0_TX_DRIVER 0x17
99 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
100 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
101 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
102 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
103 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
104 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
105 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
106 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
107 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
109 #define MDIO_REG_BANK_TX1 0x8070
110 #define MDIO_TX1_TX_DRIVER 0x17
111 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
112 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
113 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
114 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
115 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
116 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
117 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
118 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
119 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
121 #define MDIO_REG_BANK_TX2 0x8080
122 #define MDIO_TX2_TX_DRIVER 0x17
123 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
124 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
125 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
126 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
127 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
128 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
129 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
130 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
131 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
133 #define MDIO_REG_BANK_TX3 0x8090
134 #define MDIO_TX3_TX_DRIVER 0x17
135 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
136 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
137 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
138 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
139 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
140 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
141 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
142 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
143 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
145 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
146 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
148 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
149 #define MDIO_BLOCK1_LANE_CTRL0 0x15
150 #define MDIO_BLOCK1_LANE_CTRL1 0x16
151 #define MDIO_BLOCK1_LANE_CTRL2 0x17
152 #define MDIO_BLOCK1_LANE_PRBS 0x19
154 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
155 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
156 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
157 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
158 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
159 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
160 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
161 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
162 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
163 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
165 #define MDIO_REG_BANK_GP_STATUS 0x8120
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
183 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
184 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
185 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
186 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
187 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
188 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
189 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
190 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
191 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
192 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
193 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
194 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
195 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
198 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
199 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
200 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
201 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
202 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
203 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
204 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
206 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
207 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
208 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
209 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
210 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
211 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
212 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
213 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
214 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
215 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
216 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
217 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
218 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
219 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
220 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
221 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
222 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
223 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
224 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
225 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
226 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
227 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
228 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
229 #define MDIO_SERDES_DIGITAL_MISC1 0x18
230 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
231 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
232 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
233 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
234 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
235 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
236 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
237 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
238 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
239 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
240 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
241 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
242 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
243 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
244 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
245 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
246 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
247 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
249 #define MDIO_REG_BANK_OVER_1G 0x8320
250 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
251 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
252 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
253 #define MDIO_OVER_1G_UP1 0x19
254 #define MDIO_OVER_1G_UP1_2_5G 0x0001
255 #define MDIO_OVER_1G_UP1_5G 0x0002
256 #define MDIO_OVER_1G_UP1_6G 0x0004
257 #define MDIO_OVER_1G_UP1_10G 0x0010
258 #define MDIO_OVER_1G_UP1_10GH 0x0008
259 #define MDIO_OVER_1G_UP1_12G 0x0020
260 #define MDIO_OVER_1G_UP1_12_5G 0x0040
261 #define MDIO_OVER_1G_UP1_13G 0x0080
262 #define MDIO_OVER_1G_UP1_15G 0x0100
263 #define MDIO_OVER_1G_UP1_16G 0x0200
264 #define MDIO_OVER_1G_UP2 0x1A
265 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
266 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
267 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
268 #define MDIO_OVER_1G_UP3 0x1B
269 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
270 #define MDIO_OVER_1G_LP_UP1 0x1C
271 #define MDIO_OVER_1G_LP_UP2 0x1D
272 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
273 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
274 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
275 #define MDIO_OVER_1G_LP_UP3 0x1E
277 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
278 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
279 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
280 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
282 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
283 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
284 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
285 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
287 #define MDIO_REG_BANK_CL73_USERB0 0x8370
288 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
289 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
290 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
291 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
292 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
293 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
294 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
295 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
296 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
297 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
298 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
300 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
301 #define MDIO_AER_BLOCK_AER_REG 0x1E
303 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
304 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
305 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
306 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
307 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
308 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
309 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
310 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
311 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
312 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
313 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
314 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
315 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
316 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
320 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
321 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
322 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
324 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
325 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
326 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
327 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
328 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
329 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
330 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
331 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
332 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
333 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
334 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
335 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
336 Theotherbitsarereservedandshouldbezero*/
337 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
340 #define MDIO_PMA_DEVAD 0x1
342 #define MDIO_PMA_REG_CTRL 0x0
343 #define MDIO_PMA_REG_STATUS 0x1
344 #define MDIO_PMA_REG_10G_CTRL2 0x7
345 #define MDIO_PMA_REG_TX_DISABLE 0x0009
346 #define MDIO_PMA_REG_RX_SD 0xa
348 #define MDIO_PMA_REG_BCM_CTRL 0x0096
349 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
350 #define MDIO_PMA_LASI_RXCTRL 0x9000
351 #define MDIO_PMA_LASI_TXCTRL 0x9001
352 #define MDIO_PMA_LASI_CTRL 0x9002
353 #define MDIO_PMA_LASI_RXSTAT 0x9003
354 #define MDIO_PMA_LASI_TXSTAT 0x9004
355 #define MDIO_PMA_LASI_STAT 0x9005
356 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
357 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
358 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
359 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
360 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
361 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
362 #define MDIO_PMA_REG_GEN_CTRL 0xca10
363 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
364 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
365 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
366 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
367 #define MDIO_PMA_REG_ROM_VER1 0xca19
368 #define MDIO_PMA_REG_ROM_VER2 0xca1a
369 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
370 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
371 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
372 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
373 #define MDIO_PMA_REG_LRM_MODE 0xca3f
374 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
375 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
377 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
378 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
379 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
380 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
381 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
382 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
383 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
384 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
385 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
386 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
387 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
388 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
390 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
391 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
392 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
393 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
394 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
395 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
396 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
397 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
398 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
399 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
401 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
402 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
403 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
404 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
405 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
407 #define MDIO_PMA_REG_7101_RESET 0xc000
408 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
409 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
410 #define MDIO_PMA_REG_7101_VER1 0xc026
411 #define MDIO_PMA_REG_7101_VER2 0xc027
413 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
414 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
415 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
416 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
417 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
418 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
419 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
420 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
421 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
422 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
426 #define MDIO_WIS_DEVAD 0x2
428 #define MDIO_WIS_REG_LASI_CNTL 0x9002
429 #define MDIO_WIS_REG_LASI_STATUS 0x9005
431 #define MDIO_PCS_DEVAD 0x3
432 #define MDIO_PCS_REG_STATUS 0x0020
433 #define MDIO_PCS_REG_LASI_STATUS 0x9005
434 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
435 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
436 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
437 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
438 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
439 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
440 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
441 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
442 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
446 #define MDIO_XS_DEVAD 0x4
447 #define MDIO_XS_REG_STATUS 0x0001
448 #define MDIO_XS_PLL_SEQUENCER 0x8000
449 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
451 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
452 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
453 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
454 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
455 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
457 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
459 #define MDIO_AN_DEVAD 0x7
461 #define MDIO_AN_REG_CTRL 0x0000
462 #define MDIO_AN_REG_STATUS 0x0001
463 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
464 #define MDIO_AN_REG_ADV_PAUSE 0x0010
465 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
466 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
467 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
468 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
469 #define MDIO_AN_REG_ADV 0x0011
470 #define MDIO_AN_REG_ADV2 0x0012
471 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
472 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
473 #define MDIO_AN_REG_MASTER_STATUS 0x0021
474 #define MDIO_AN_REG_EEE_ADV 0x003c
475 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
477 #define MDIO_AN_REG_LINK_STATUS 0x8304
478 #define MDIO_AN_REG_CL37_CL73 0x8370
479 #define MDIO_AN_REG_CL37_AN 0xffe0
480 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
481 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
482 #define MDIO_AN_REG_1000T_STATUS 0xffea
484 #define MDIO_AN_REG_8073_2_5G 0x8329
485 #define MDIO_AN_REG_8073_BAM 0x8350
487 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
488 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
489 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
490 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
491 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
492 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
493 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
494 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
495 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
496 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
497 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
498 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
499 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
502 #define MDIO_CTL_DEVAD 0x1e
503 #define MDIO_CTL_REG_84823_MEDIA 0x401a
504 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
505 /* These pins configure the BCM84823 interface to MAC after reset. */
506 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
507 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
508 /* These pins configure the BCM84823 interface to Line after reset. */
509 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
510 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
511 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
512 /* When this pin is active high during reset, 10GBASE-T core is power
513 * down, When it is active low the 10GBASE-T is power up
515 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
516 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
517 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
518 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
519 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
520 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
521 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
522 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
523 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
524 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
525 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
526 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
529 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
530 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
531 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
532 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
533 #define MDIO_84833_SUPER_ISOLATE 0x8000
534 /* These are mailbox register set used by 84833. */
535 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
536 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
537 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
538 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
539 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
540 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
541 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
542 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
543 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
544 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
545 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
546 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
547 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
548 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
549 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
550 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
551 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
552 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
554 /* Mailbox command set used by 84833. */
555 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
556 #define PHY84833_CMD_GET_EEE_MODE 0x8008
557 #define PHY84833_CMD_SET_EEE_MODE 0x8009
558 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
559 /* Mailbox status set used by 84833. */
560 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
561 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
562 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
563 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
564 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
565 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
566 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
567 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
568 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
571 /* Warpcore clause 45 addressing */
572 #define MDIO_WC_DEVAD 0x3
573 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
574 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
575 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
576 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
577 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
578 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
579 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
580 #define MDIO_WC_REG_PCS_STATUS2 0x0021
581 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
582 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
583 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
584 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
585 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
586 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
587 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
588 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
589 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
590 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
591 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
592 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
593 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
594 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
595 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
596 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
597 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
598 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
599 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
600 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
601 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
602 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
603 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
604 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
605 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
606 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
607 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
608 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
609 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
610 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
611 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
612 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
613 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
614 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
615 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
616 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
617 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
618 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
619 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
620 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
621 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
622 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
623 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
624 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
625 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
626 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
627 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
628 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
629 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
630 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
631 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
632 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
633 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
634 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
635 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
636 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
637 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
638 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
639 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
640 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
641 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
642 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
643 #define MDIO_WC_REG_DSC_SMC 0x8213
644 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
645 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
646 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
647 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
648 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
649 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
650 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
651 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
652 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
653 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
654 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
655 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
656 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
657 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
658 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
659 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
660 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
661 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
662 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
663 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
664 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
665 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
666 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
667 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
668 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
669 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
670 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
671 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
672 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
673 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
674 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
675 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
676 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
677 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
678 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
679 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
680 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
681 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
682 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
683 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
684 #define MDIO_WC_REG_RX66_SCW0 0x83c2
685 #define MDIO_WC_REG_RX66_SCW1 0x83c3
686 #define MDIO_WC_REG_RX66_SCW2 0x83c4
687 #define MDIO_WC_REG_RX66_SCW3 0x83c5
688 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
689 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
690 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
691 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
692 #define MDIO_WC_REG_FX100_CTRL1 0x8400
693 #define MDIO_WC_REG_FX100_CTRL3 0x8402
694 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
695 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
696 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
697 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
698 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
699 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
700 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
701 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
702 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
703 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
704 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
705 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
706 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
707 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
709 #define MDIO_WC_REG_AERBLK_AER 0xffde
710 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
711 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
713 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
714 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
715 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
717 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
719 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
722 #define MDIO_REG_GPHY_MII_STATUS 0x1
723 #define MDIO_REG_GPHY_PHYID_LSB 0x3
724 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
725 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
726 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
727 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
728 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
729 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
730 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
731 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
732 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
733 #define MDIO_REG_GPHY_AUX_STATUS 0x19
734 #define MDIO_REG_INTR_STATUS 0x1a
735 #define MDIO_REG_INTR_MASK 0x1b
736 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
737 #define MDIO_REG_GPHY_SHADOW 0x1c
738 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
739 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
740 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
741 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
742 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
745 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
746 struct elink_params *params,
747 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
748 uint8_t *o_buf, uint8_t);
749 /********************************************************/
750 #define ELINK_ETH_HLEN 14
751 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
752 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
753 #define ELINK_ETH_MIN_PACKET_SIZE 60
754 #define ELINK_ETH_MAX_PACKET_SIZE 1500
755 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
756 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
757 #define WC_LANE_MAX 4
758 #define I2C_SWITCH_WIDTH 2
761 #define I2C_WA_RETRY_CNT 3
762 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
763 #define MCPR_IMC_COMMAND_READ_OP 1
764 #define MCPR_IMC_COMMAND_WRITE_OP 2
766 /* LED Blink rate that will achieve ~15.9Hz */
767 #define LED_BLINK_RATE_VAL_E3 354
768 #define LED_BLINK_RATE_VAL_E1X_E2 480
769 /***********************************************************/
770 /* Shortcut definitions */
771 /***********************************************************/
773 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
775 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
776 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
777 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
778 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
779 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
780 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
781 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
782 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
783 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
784 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
785 #define ELINK_NIG_MASK_MI_INT \
786 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
787 #define ELINK_NIG_MASK_XGXS0_LINK10G \
788 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
789 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
790 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
791 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
792 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
794 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
795 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
796 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
798 #define ELINK_XGXS_RESET_BITS \
799 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
800 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
801 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
802 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
803 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
805 #define ELINK_SERDES_RESET_BITS \
806 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
807 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
808 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
809 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
811 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
812 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
813 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
814 #define ELINK_AUTONEG_PARALLEL \
815 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
816 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
817 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
818 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
820 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
821 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
822 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
823 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
824 #define ELINK_GP_STATUS_SPEED_MASK \
825 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
826 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
827 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
828 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
829 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
830 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
831 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
832 #define ELINK_GP_STATUS_10G_HIG \
833 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
834 #define ELINK_GP_STATUS_10G_CX4 \
835 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
836 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
837 #define ELINK_GP_STATUS_10G_KX4 \
838 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
839 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
840 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
841 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
842 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
843 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
844 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
845 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
846 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
847 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
848 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
849 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
850 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
851 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
852 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
853 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
854 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
855 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
856 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
857 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
858 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
860 #define ELINK_LINK_UPDATE_MASK \
861 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
862 LINK_STATUS_LINK_UP | \
863 LINK_STATUS_PHYSICAL_LINK_FLAG | \
864 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
865 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
866 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
867 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
868 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
869 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
871 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
872 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
873 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
874 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
877 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
878 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
879 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
880 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
882 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
883 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
884 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
886 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
887 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
888 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
890 #define ELINK_EDC_MODE_LINEAR 0x0022
891 #define ELINK_EDC_MODE_LIMITING 0x0044
892 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
893 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
896 #define DCBX_INVALID_COS (0xFF)
898 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
899 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
900 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
901 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
902 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
904 #define ELINK_MAX_PACKET_SIZE (9700)
905 #define MAX_KR_LINK_RETRY 4
907 /**********************************************************/
909 /**********************************************************/
911 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
912 elink_cl45_write(_sc, _phy, \
913 (_phy)->def_md_devad, \
914 (_bank + (_addr & 0xf)), \
917 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
918 elink_cl45_read(_sc, _phy, \
919 (_phy)->def_md_devad, \
920 (_bank + (_addr & 0xf)), \
923 static uint32_t elink_bits_en(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
925 uint32_t val = REG_RD(sc, reg);
928 REG_WR(sc, reg, val);
932 static uint32_t elink_bits_dis(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
934 uint32_t val = REG_RD(sc, reg);
937 REG_WR(sc, reg, val);
942 * elink_check_lfa - This function checks if link reinitialization is required,
943 * or link flap can be avoided.
945 * @params: link parameters
946 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
949 static int elink_check_lfa(struct elink_params *params)
951 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
952 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
953 uint32_t saved_val, req_val, eee_status;
954 struct bxe_softc *sc = params->sc;
957 REG_RD(sc, params->lfa_base +
958 offsetof(struct shmem_lfa, additional_config));
960 /* NOTE: must be first condition checked -
961 * to verify DCC bit is cleared in any case!
963 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
964 ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit\n");
965 REG_WR(sc, params->lfa_base +
966 offsetof(struct shmem_lfa, additional_config),
967 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
968 return LFA_DCC_LFA_DISABLED;
971 /* Verify that link is up */
972 link_status = REG_RD(sc, params->shmem_base +
973 offsetof(struct shmem_region,
974 port_mb[params->port].link_status));
975 if (!(link_status & LINK_STATUS_LINK_UP))
976 return LFA_LINK_DOWN;
978 /* if loaded after BOOT from SAN, don't flap the link in any case and
979 * rely on link set by preboot driver
981 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
984 /* Verify that loopback mode is not set */
985 if (params->loopback_mode)
986 return LFA_LOOPBACK_ENABLED;
988 /* Verify that MFW supports LFA */
989 if (!params->lfa_base)
990 return LFA_MFW_IS_TOO_OLD;
992 if (params->num_phys == 3) {
994 lfa_mask = 0xffffffff;
1000 /* Compare Duplex */
1001 saved_val = REG_RD(sc, params->lfa_base +
1002 offsetof(struct shmem_lfa, req_duplex));
1003 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
1004 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1005 ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x\n",
1006 (saved_val & lfa_mask), (req_val & lfa_mask));
1007 return LFA_DUPLEX_MISMATCH;
1009 /* Compare Flow Control */
1010 saved_val = REG_RD(sc, params->lfa_base +
1011 offsetof(struct shmem_lfa, req_flow_ctrl));
1012 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
1013 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1014 ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x\n",
1015 (saved_val & lfa_mask), (req_val & lfa_mask));
1016 return LFA_FLOW_CTRL_MISMATCH;
1018 /* Compare Link Speed */
1019 saved_val = REG_RD(sc, params->lfa_base +
1020 offsetof(struct shmem_lfa, req_line_speed));
1021 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1022 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1023 ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x\n",
1024 (saved_val & lfa_mask), (req_val & lfa_mask));
1025 return LFA_LINK_SPEED_MISMATCH;
1028 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1029 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1030 offsetof(struct shmem_lfa,
1031 speed_cap_mask[cfg_idx]));
1033 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1034 ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x\n",
1036 params->speed_cap_mask[cfg_idx]);
1037 return LFA_SPEED_CAP_MISMATCH;
1041 cur_req_fc_auto_adv =
1042 REG_RD(sc, params->lfa_base +
1043 offsetof(struct shmem_lfa, additional_config)) &
1044 REQ_FC_AUTO_ADV_MASK;
1046 if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1047 ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x\n",
1048 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1049 return LFA_FLOW_CTRL_MISMATCH;
1052 eee_status = REG_RD(sc, params->shmem2_base +
1053 offsetof(struct shmem2_region,
1054 eee_status[params->port]));
1056 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1057 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1058 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1059 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1060 ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x\n", params->eee_mode,
1062 return LFA_EEE_MISMATCH;
1065 /* LFA conditions are met */
1068 /******************************************************************/
1069 /* EPIO/GPIO section */
1070 /******************************************************************/
1071 static void elink_get_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t *en)
1073 uint32_t epio_mask, gp_oenable;
1076 if (epio_pin > 31) {
1077 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get\n", epio_pin);
1081 epio_mask = 1 << epio_pin;
1082 /* Set this EPIO to output */
1083 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1084 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1086 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1088 static void elink_set_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t en)
1090 uint32_t epio_mask, gp_output, gp_oenable;
1093 if (epio_pin > 31) {
1094 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set\n", epio_pin);
1097 ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d\n", epio_pin, en);
1098 epio_mask = 1 << epio_pin;
1099 /* Set this EPIO to output */
1100 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1102 gp_output |= epio_mask;
1104 gp_output &= ~epio_mask;
1106 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1108 /* Set the value for this EPIO */
1109 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1110 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1113 static void elink_set_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t val)
1115 if (pin_cfg == PIN_CFG_NA)
1117 if (pin_cfg >= PIN_CFG_EPIO0) {
1118 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1120 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1121 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1122 elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port);
1126 static uint32_t elink_get_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t *val)
1128 if (pin_cfg == PIN_CFG_NA)
1129 return ELINK_STATUS_ERROR;
1130 if (pin_cfg >= PIN_CFG_EPIO0) {
1131 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1133 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1134 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1135 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1137 return ELINK_STATUS_OK;
1140 /******************************************************************/
1142 /******************************************************************/
1143 static void elink_ets_e2e3a0_disabled(struct elink_params *params)
1145 /* ETS disabled configuration*/
1146 struct bxe_softc *sc = params->sc;
1148 ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration\n");
1150 /* mapping between entry priority to client number (0,1,2 -debug and
1151 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1153 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1154 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
1157 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
1158 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1159 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1160 * COS0 entry, 4 - COS1 entry.
1161 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1162 * bit4 bit3 bit2 bit1 bit0
1163 * MCP and debug are strict
1166 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1167 /* defines which entries (clients) are subjected to WFQ arbitration */
1168 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1169 /* For strict priority entries defines the number of consecutive
1170 * slots for the highest priority.
1172 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1173 /* mapping between the CREDIT_WEIGHT registers and actual client
1176 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
1177 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
1178 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
1180 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
1181 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
1182 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
1183 /* ETS mode disable */
1184 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
1185 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
1186 * weight for COS0/COS1.
1188 REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);
1189 REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);
1190 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
1191 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);
1192 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);
1193 /* Defines the number of consecutive slots for the strict priority */
1194 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1196 /******************************************************************************
1198 * Getting min_w_val will be set according to line speed .
1200 ******************************************************************************/
1201 static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars)
1203 uint32_t min_w_val = 0;
1204 /* Calculate min_w_val.*/
1205 if (vars->link_up) {
1206 if (vars->line_speed == ELINK_SPEED_20000)
1207 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1209 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
1211 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1212 /* If the link isn't up (static configuration for example ) The
1213 * link will be according to 20GBPS.
1217 /******************************************************************************
1219 * Getting credit upper bound form min_w_val.
1221 ******************************************************************************/
1222 static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val)
1224 const uint32_t credit_upper_bound = (uint32_t)ELINK_MAXVAL((150 * min_w_val),
1225 ELINK_MAX_PACKET_SIZE);
1226 return credit_upper_bound;
1228 /******************************************************************************
1230 * Set credit upper bound for NIG.
1232 ******************************************************************************/
1233 static void elink_ets_e3b0_set_credit_upper_bound_nig(
1234 const struct elink_params *params,
1235 const uint32_t min_w_val)
1237 struct bxe_softc *sc = params->sc;
1238 const uint8_t port = params->port;
1239 const uint32_t credit_upper_bound =
1240 elink_ets_get_credit_upper_bound(min_w_val);
1242 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
1243 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
1244 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
1245 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
1246 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
1247 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
1248 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
1249 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
1250 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
1251 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
1252 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
1253 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
1256 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
1257 credit_upper_bound);
1258 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
1259 credit_upper_bound);
1260 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
1261 credit_upper_bound);
1264 /******************************************************************************
1266 * Will return the NIG ETS registers to init values.Except
1267 * credit_upper_bound.
1268 * That isn't used in this configuration (No WFQ is enabled) and will be
1269 * configured acording to spec
1271 ******************************************************************************/
1272 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params,
1273 const struct elink_vars *vars)
1275 struct bxe_softc *sc = params->sc;
1276 const uint8_t port = params->port;
1277 const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars);
1278 /* Mapping between entry priority to client number (0,1,2 -debug and
1279 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
1280 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
1281 * reset value or init tool
1284 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
1285 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
1287 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
1288 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
1290 /* For strict priority entries defines the number of consecutive
1291 * slots for the highest priority.
1293 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
1294 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1295 /* Mapping between the CREDIT_WEIGHT registers and actual client
1299 /*Port 1 has 6 COS*/
1300 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
1301 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
1303 /*Port 0 has 9 COS*/
1304 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
1306 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
1309 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1310 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1311 * COS0 entry, 4 - COS1 entry.
1312 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1313 * bit4 bit3 bit2 bit1 bit0
1314 * MCP and debug are strict
1317 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
1319 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
1320 /* defines which entries (clients) are subjected to WFQ arbitration */
1321 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1322 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1324 /* Please notice the register address are note continuous and a
1325 * for here is note appropriate.In 2 port mode port0 only COS0-5
1326 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
1327 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
1328 * are never used for WFQ
1330 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1331 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
1332 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1333 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
1334 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1335 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
1336 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
1337 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
1338 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
1339 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
1340 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
1341 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
1343 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
1344 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
1345 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
1348 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
1350 /******************************************************************************
1352 * Set credit upper bound for PBF.
1354 ******************************************************************************/
1355 static void elink_ets_e3b0_set_credit_upper_bound_pbf(
1356 const struct elink_params *params,
1357 const uint32_t min_w_val)
1359 struct bxe_softc *sc = params->sc;
1360 const uint32_t credit_upper_bound =
1361 elink_ets_get_credit_upper_bound(min_w_val);
1362 const uint8_t port = params->port;
1363 uint32_t base_upper_bound = 0;
1364 uint8_t max_cos = 0;
1366 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
1367 * port mode port1 has COS0-2 that can be used for WFQ.
1370 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
1371 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1373 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
1374 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1377 for (i = 0; i < max_cos; i++)
1378 REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);
1381 /******************************************************************************
1383 * Will return the PBF ETS registers to init values.Except
1384 * credit_upper_bound.
1385 * That isn't used in this configuration (No WFQ is enabled) and will be
1386 * configured acording to spec
1388 ******************************************************************************/
1389 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)
1391 struct bxe_softc *sc = params->sc;
1392 const uint8_t port = params->port;
1393 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1395 uint32_t base_weight = 0;
1396 uint8_t max_cos = 0;
1398 /* Mapping between entry priority to client number 0 - COS0
1399 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
1400 * TODO_ETS - Should be done by reset value or init tool
1403 /* 0x688 (|011|0 10|00 1|000) */
1404 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
1406 /* (10 1|100 |011|0 10|00 1|000) */
1407 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
1409 /* TODO_ETS - Should be done by reset value or init tool */
1411 /* 0x688 (|011|0 10|00 1|000)*/
1412 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
1414 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
1415 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
1417 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
1418 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
1421 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1422 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
1424 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1425 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
1426 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
1427 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
1430 base_weight = PBF_REG_COS0_WEIGHT_P0;
1431 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1433 base_weight = PBF_REG_COS0_WEIGHT_P1;
1434 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1437 for (i = 0; i < max_cos; i++)
1438 REG_WR(sc, base_weight + (0x4 * i), 0);
1440 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1442 /******************************************************************************
1444 * E3B0 disable will return basicly the values to init values.
1446 ******************************************************************************/
1447 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,
1448 const struct elink_vars *vars)
1450 struct bxe_softc *sc = params->sc;
1452 if (!CHIP_IS_E3B0(sc)) {
1454 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1455 return ELINK_STATUS_ERROR;
1458 elink_ets_e3b0_nig_disabled(params, vars);
1460 elink_ets_e3b0_pbf_disabled(params);
1462 return ELINK_STATUS_OK;
1465 /******************************************************************************
1467 * Disable will return basicly the values to init values.
1469 ******************************************************************************/
1470 elink_status_t elink_ets_disabled(struct elink_params *params,
1471 struct elink_vars *vars)
1473 struct bxe_softc *sc = params->sc;
1474 elink_status_t elink_status = ELINK_STATUS_OK;
1476 if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc)))
1477 elink_ets_e2e3a0_disabled(params);
1478 else if (CHIP_IS_E3B0(sc))
1479 elink_status = elink_ets_e3b0_disabled(params, vars);
1481 ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported\n");
1482 return ELINK_STATUS_ERROR;
1485 return elink_status;
1488 /******************************************************************************
1490 * Set the COS mappimg to SP and BW until this point all the COS are not
1492 ******************************************************************************/
1493 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,
1494 const struct elink_ets_params *ets_params,
1495 const uint8_t cos_sp_bitmap,
1496 const uint8_t cos_bw_bitmap)
1498 struct bxe_softc *sc = params->sc;
1499 const uint8_t port = params->port;
1500 const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
1501 const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap;
1502 const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
1503 const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
1505 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
1506 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
1508 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1509 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
1511 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1512 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
1513 nig_cli_subject2wfq_bitmap);
1515 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1516 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
1517 pbf_cli_subject2wfq_bitmap);
1519 return ELINK_STATUS_OK;
1522 /******************************************************************************
1524 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1525 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1526 ******************************************************************************/
1527 static elink_status_t elink_ets_e3b0_set_cos_bw(struct bxe_softc *sc,
1528 const uint8_t cos_entry,
1529 const uint32_t min_w_val_nig,
1530 const uint32_t min_w_val_pbf,
1531 const uint16_t total_bw,
1535 uint32_t nig_reg_adress_crd_weight = 0;
1536 uint32_t pbf_reg_adress_crd_weight = 0;
1537 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
1538 const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
1539 const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
1541 switch (cos_entry) {
1543 nig_reg_adress_crd_weight =
1544 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1545 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
1546 pbf_reg_adress_crd_weight = (port) ?
1547 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
1550 nig_reg_adress_crd_weight = (port) ?
1551 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1552 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
1553 pbf_reg_adress_crd_weight = (port) ?
1554 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
1557 nig_reg_adress_crd_weight = (port) ?
1558 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1559 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
1561 pbf_reg_adress_crd_weight = (port) ?
1562 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
1566 return ELINK_STATUS_ERROR;
1567 nig_reg_adress_crd_weight =
1568 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
1569 pbf_reg_adress_crd_weight =
1570 PBF_REG_COS3_WEIGHT_P0;
1574 return ELINK_STATUS_ERROR;
1575 nig_reg_adress_crd_weight =
1576 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
1577 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
1581 return ELINK_STATUS_ERROR;
1582 nig_reg_adress_crd_weight =
1583 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
1584 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
1588 REG_WR(sc, nig_reg_adress_crd_weight, cos_bw_nig);
1590 REG_WR(sc, pbf_reg_adress_crd_weight, cos_bw_pbf);
1592 return ELINK_STATUS_OK;
1594 /******************************************************************************
1596 * Calculate the total BW.A value of 0 isn't legal.
1598 ******************************************************************************/
1599 static elink_status_t elink_ets_e3b0_get_total_bw(
1600 const struct elink_params *params,
1601 struct elink_ets_params *ets_params,
1604 struct bxe_softc *sc = params->sc;
1605 uint8_t cos_idx = 0;
1606 uint8_t is_bw_cos_exist = 0;
1609 /* Calculate total BW requested */
1610 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
1611 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) {
1612 is_bw_cos_exist = 1;
1613 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
1614 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW"
1616 /* This is to prevent a state when ramrods
1619 ets_params->cos[cos_idx].params.bw_params.bw
1623 ets_params->cos[cos_idx].params.bw_params.bw;
1627 /* Check total BW is valid */
1628 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
1629 if (*total_bw == 0) {
1631 "elink_ets_E3B0_config total BW shouldn't be 0\n");
1632 return ELINK_STATUS_ERROR;
1635 "elink_ets_E3B0_config total BW should be 100\n");
1636 /* We can handle a case whre the BW isn't 100 this can happen
1637 * if the TC are joined.
1640 return ELINK_STATUS_OK;
1643 /******************************************************************************
1645 * Invalidate all the sp_pri_to_cos.
1647 ******************************************************************************/
1648 static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos)
1651 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)
1652 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
1654 /******************************************************************************
1656 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1657 * according to sp_pri_to_cos.
1659 ******************************************************************************/
1660 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params,
1661 uint8_t *sp_pri_to_cos, const uint8_t pri,
1662 const uint8_t cos_entry)
1664 struct bxe_softc *sc = params->sc;
1665 const uint8_t port = params->port;
1666 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1667 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1669 if (pri >= max_num_of_cos) {
1670 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1671 "parameter Illegal strict priority\n");
1672 return ELINK_STATUS_ERROR;
1675 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
1676 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1677 "parameter There can't be two COS's with "
1678 "the same strict pri\n");
1679 return ELINK_STATUS_ERROR;
1682 sp_pri_to_cos[pri] = cos_entry;
1683 return ELINK_STATUS_OK;
1687 /******************************************************************************
1689 * Returns the correct value according to COS and priority in
1690 * the sp_pri_cli register.
1692 ******************************************************************************/
1693 static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos, const uint8_t cos_offset,
1694 const uint8_t pri_set,
1695 const uint8_t pri_offset,
1696 const uint8_t entry_size)
1698 uint64_t pri_cli_nig = 0;
1699 pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size *
1700 (pri_set + pri_offset));
1704 /******************************************************************************
1706 * Returns the correct value according to COS and priority in the
1707 * sp_pri_cli register for NIG.
1709 ******************************************************************************/
1710 static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos, const uint8_t pri_set)
1712 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1713 const uint8_t nig_cos_offset = 3;
1714 const uint8_t nig_pri_offset = 3;
1716 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1720 /******************************************************************************
1722 * Returns the correct value according to COS and priority in the
1723 * sp_pri_cli register for PBF.
1725 ******************************************************************************/
1726 static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos, const uint8_t pri_set)
1728 const uint8_t pbf_cos_offset = 0;
1729 const uint8_t pbf_pri_offset = 0;
1731 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1736 /******************************************************************************
1738 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1739 * according to sp_pri_to_cos.(which COS has higher priority)
1741 ******************************************************************************/
1742 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params,
1743 uint8_t *sp_pri_to_cos)
1745 struct bxe_softc *sc = params->sc;
1747 const uint8_t port = params->port;
1748 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1749 uint64_t pri_cli_nig = 0x210;
1750 uint32_t pri_cli_pbf = 0x0;
1751 uint8_t pri_set = 0;
1752 uint8_t pri_bitmask = 0;
1753 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1754 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1756 uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1;
1758 /* Set all the strict priority first */
1759 for (i = 0; i < max_num_of_cos; i++) {
1760 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1761 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {
1763 "elink_ets_e3b0_sp_set_pri_cli_reg "
1764 "invalid cos entry\n");
1765 return ELINK_STATUS_ERROR;
1768 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1769 sp_pri_to_cos[i], pri_set);
1771 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1772 sp_pri_to_cos[i], pri_set);
1773 pri_bitmask = 1 << sp_pri_to_cos[i];
1774 /* COS is used remove it from bitmap.*/
1775 if (!(pri_bitmask & cos_bit_to_set)) {
1777 "elink_ets_e3b0_sp_set_pri_cli_reg "
1778 "invalid There can't be two COS's with"
1779 " the same strict pri\n");
1780 return ELINK_STATUS_ERROR;
1782 cos_bit_to_set &= ~pri_bitmask;
1787 /* Set all the Non strict priority i= COS*/
1788 for (i = 0; i < max_num_of_cos; i++) {
1789 pri_bitmask = 1 << i;
1790 /* Check if COS was already used for SP */
1791 if (pri_bitmask & cos_bit_to_set) {
1792 /* COS wasn't used for SP */
1793 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1796 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1798 /* COS is used remove it from bitmap.*/
1799 cos_bit_to_set &= ~pri_bitmask;
1804 if (pri_set != max_num_of_cos) {
1805 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
1806 "entries were set\n");
1807 return ELINK_STATUS_ERROR;
1811 /* Only 6 usable clients*/
1812 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1813 (uint32_t)pri_cli_nig);
1815 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1817 /* Only 9 usable clients*/
1818 const uint32_t pri_cli_nig_lsb = (uint32_t) (pri_cli_nig);
1819 const uint32_t pri_cli_nig_msb = (uint32_t) ((pri_cli_nig >> 32) & 0xF);
1821 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1823 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1826 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1828 return ELINK_STATUS_OK;
1831 /******************************************************************************
1833 * Configure the COS to ETS according to BW and SP settings.
1834 ******************************************************************************/
1835 elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
1836 const struct elink_vars *vars,
1837 struct elink_ets_params *ets_params)
1839 struct bxe_softc *sc = params->sc;
1840 elink_status_t elink_status = ELINK_STATUS_OK;
1841 const uint8_t port = params->port;
1842 uint16_t total_bw = 0;
1843 const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars);
1844 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1845 uint8_t cos_bw_bitmap = 0;
1846 uint8_t cos_sp_bitmap = 0;
1847 uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};
1848 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1849 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1850 uint8_t cos_entry = 0;
1852 if (!CHIP_IS_E3B0(sc)) {
1854 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1855 return ELINK_STATUS_ERROR;
1858 if ((ets_params->num_of_cos > max_num_of_cos)) {
1859 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS "
1860 "isn't supported\n");
1861 return ELINK_STATUS_ERROR;
1864 /* Prepare sp strict priority parameters*/
1865 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1867 /* Prepare BW parameters*/
1868 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params,
1870 if (elink_status != ELINK_STATUS_OK) {
1872 "elink_ets_E3B0_config get_total_bw failed\n");
1873 return ELINK_STATUS_ERROR;
1876 /* Upper bound is set according to current link speed (min_w_val
1877 * should be the same for upper bound and COS credit val).
1879 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1880 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1883 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1884 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) {
1885 cos_bw_bitmap |= (1 << cos_entry);
1886 /* The function also sets the BW in HW(not the mappin
1889 elink_status = elink_ets_e3b0_set_cos_bw(
1890 sc, cos_entry, min_w_val_nig, min_w_val_pbf,
1892 ets_params->cos[cos_entry].params.bw_params.bw,
1894 } else if (elink_cos_state_strict ==
1895 ets_params->cos[cos_entry].state){
1896 cos_sp_bitmap |= (1 << cos_entry);
1898 elink_status = elink_ets_e3b0_sp_pri_to_cos_set(
1901 ets_params->cos[cos_entry].params.sp_params.pri,
1906 "elink_ets_e3b0_config cos state not valid\n");
1907 return ELINK_STATUS_ERROR;
1909 if (elink_status != ELINK_STATUS_OK) {
1911 "elink_ets_e3b0_config set cos bw failed\n");
1912 return elink_status;
1916 /* Set SP register (which COS has higher priority) */
1917 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,
1920 if (elink_status != ELINK_STATUS_OK) {
1922 "elink_ets_E3B0_config set_pri_cli_reg failed\n");
1923 return elink_status;
1926 /* Set client mapping of BW and strict */
1927 elink_status = elink_ets_e3b0_cli_map(params, ets_params,
1931 if (elink_status != ELINK_STATUS_OK) {
1932 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed\n");
1933 return elink_status;
1935 return ELINK_STATUS_OK;
1937 static void elink_ets_bw_limit_common(const struct elink_params *params)
1939 /* ETS disabled configuration */
1940 struct bxe_softc *sc = params->sc;
1941 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
1942 /* Defines which entries (clients) are subjected to WFQ arbitration
1946 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1947 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1948 * client numbers (WEIGHT_0 does not actually have to represent
1950 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1951 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1953 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1955 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1956 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1957 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1958 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1960 /* ETS mode enabled*/
1961 REG_WR(sc, PBF_REG_ETS_ENABLED, 1);
1963 /* Defines the number of consecutive slots for the strict priority */
1964 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1965 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1966 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1967 * entry, 4 - COS1 entry.
1968 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1969 * bit4 bit3 bit2 bit1 bit0
1970 * MCP and debug are strict
1972 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1974 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1975 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND,
1976 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1977 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND,
1978 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1981 void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw,
1982 const uint32_t cos1_bw)
1984 /* ETS disabled configuration*/
1985 struct bxe_softc *sc = params->sc;
1986 const uint32_t total_bw = cos0_bw + cos1_bw;
1987 uint32_t cos0_credit_weight = 0;
1988 uint32_t cos1_credit_weight = 0;
1990 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
1995 ELINK_DEBUG_P0(sc, "Total BW can't be zero\n");
1999 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
2001 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
2004 elink_ets_bw_limit_common(params);
2006 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
2007 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
2009 REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
2010 REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
2013 elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos)
2015 /* ETS disabled configuration*/
2016 struct bxe_softc *sc = params->sc;
2019 ELINK_DEBUG_P0(sc, "ETS enabled strict configuration\n");
2020 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
2021 * as strict. Bits 0,1,2 - debug and management entries,
2022 * 3 - COS0 entry, 4 - COS1 entry.
2023 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
2024 * bit4 bit3 bit2 bit1 bit0
2025 * MCP and debug are strict
2027 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
2028 /* For strict priority entries defines the number of consecutive slots
2029 * for the highest priority.
2031 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
2032 /* ETS mode disable */
2033 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
2034 /* Defines the number of consecutive slots for the strict priority */
2035 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
2037 /* Defines the number of consecutive slots for the strict priority */
2038 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
2040 /* Mapping between entry priority to client number (0,1,2 -debug and
2041 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
2043 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
2044 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
2045 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
2047 val = (!strict_cos) ? 0x2318 : 0x22E0;
2048 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
2050 return ELINK_STATUS_OK;
2053 /******************************************************************/
2055 /******************************************************************/
2056 static void elink_update_pfc_xmac(struct elink_params *params,
2057 struct elink_vars *vars,
2060 struct bxe_softc *sc = params->sc;
2062 uint32_t pause_val, pfc0_val, pfc1_val;
2064 /* XMAC base adrr */
2065 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2067 /* Initialize pause and pfc registers */
2068 pause_val = 0x18000;
2069 pfc0_val = 0xFFFF8000;
2072 /* No PFC support */
2073 if (!(params->feature_config_flags &
2074 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2076 /* RX flow control - Process pause frame in receive direction
2078 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2079 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
2081 /* TX flow control - Send pause packet when buffer is full */
2082 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2083 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
2084 } else {/* PFC support */
2085 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
2086 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
2087 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
2088 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
2089 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2090 /* Write pause and PFC registers */
2091 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2092 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2093 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2094 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2098 /* Write pause and PFC registers */
2099 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2100 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2101 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2104 /* Set MAC address for source TX Pause/PFC frames */
2105 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
2106 ((params->mac_addr[2] << 24) |
2107 (params->mac_addr[3] << 16) |
2108 (params->mac_addr[4] << 8) |
2109 (params->mac_addr[5])));
2110 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
2111 ((params->mac_addr[0] << 8) |
2112 (params->mac_addr[1])));
2118 static void elink_emac_get_pfc_stat(struct elink_params *params,
2119 uint32_t pfc_frames_sent[2],
2120 uint32_t pfc_frames_received[2])
2122 /* Read pfc statistic */
2123 struct bxe_softc *sc = params->sc;
2124 uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2125 uint32_t val_xon = 0;
2126 uint32_t val_xoff = 0;
2128 ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC\n");
2130 /* PFC received frames */
2131 val_xoff = REG_RD(sc, emac_base +
2132 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
2133 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
2134 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
2135 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
2137 pfc_frames_received[0] = val_xon + val_xoff;
2139 /* PFC received sent */
2140 val_xoff = REG_RD(sc, emac_base +
2141 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
2142 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
2143 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
2144 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
2146 pfc_frames_sent[0] = val_xon + val_xoff;
2149 /* Read pfc statistic*/
2150 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
2151 uint32_t pfc_frames_sent[2],
2152 uint32_t pfc_frames_received[2])
2154 /* Read pfc statistic */
2155 struct bxe_softc *sc = params->sc;
2157 ELINK_DEBUG_P0(sc, "pfc statistic\n");
2162 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) {
2163 ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC\n");
2164 elink_emac_get_pfc_stat(params, pfc_frames_sent,
2165 pfc_frames_received);
2168 /******************************************************************/
2169 /* MAC/PBF section */
2170 /******************************************************************/
2171 static void elink_set_mdio_clk(struct bxe_softc *sc, uint32_t chip_id,
2174 uint32_t new_mode, cur_mode;
2176 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
2177 * (a value of 49==0x31) and make sure that the AUTO poll is off
2179 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
2181 if (USES_WARPCORE(sc))
2182 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2184 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2186 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
2187 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
2190 new_mode = cur_mode &
2191 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
2192 new_mode |= clc_cnt;
2193 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
2195 ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x\n",
2196 cur_mode, new_mode);
2197 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
2201 static void elink_set_mdio_emac_per_phy(struct bxe_softc *sc,
2202 struct elink_params *params)
2205 /* Set mdio clock per phy */
2206 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
2208 elink_set_mdio_clk(sc, params->chip_id,
2209 params->phy[phy_index].mdio_ctrl);
2212 static uint8_t elink_is_4_port_mode(struct bxe_softc *sc)
2214 uint32_t port4mode_ovwr_val;
2215 /* Check 4-port override enabled */
2216 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
2217 if (port4mode_ovwr_val & (1<<0)) {
2218 /* Return 4-port mode override value */
2219 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
2221 /* Return 4-port mode from input pin */
2222 return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);
2225 static void elink_emac_init(struct elink_params *params,
2226 struct elink_vars *vars)
2228 /* reset and unreset the emac core */
2229 struct bxe_softc *sc = params->sc;
2230 uint8_t port = params->port;
2231 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2235 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2236 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2238 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2239 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2241 /* init emac - use read-modify-write */
2242 /* self clear reset */
2243 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2244 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2248 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2249 ELINK_DEBUG_P1(sc, "EMAC reset reg is %u\n", val);
2251 ELINK_DEBUG_P0(sc, "EMAC timeout!\n");
2255 } while (val & EMAC_MODE_RESET);
2257 elink_set_mdio_emac_per_phy(sc, params);
2258 /* Set mac address */
2259 val = ((params->mac_addr[0] << 8) |
2260 params->mac_addr[1]);
2261 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
2263 val = ((params->mac_addr[2] << 24) |
2264 (params->mac_addr[3] << 16) |
2265 (params->mac_addr[4] << 8) |
2266 params->mac_addr[5]);
2267 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
2270 static void elink_set_xumac_nig(struct elink_params *params,
2271 uint16_t tx_pause_en,
2274 struct bxe_softc *sc = params->sc;
2276 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
2278 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
2280 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
2281 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
2284 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
2286 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2288 struct bxe_softc *sc = params->sc;
2289 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
2290 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
2292 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
2294 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
2295 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2297 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
2298 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2299 /* Disable RX and TX */
2300 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2303 static void elink_umac_enable(struct elink_params *params,
2304 struct elink_vars *vars, uint8_t lb)
2307 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2308 struct bxe_softc *sc = params->sc;
2310 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2311 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2314 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2315 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2317 ELINK_DEBUG_P0(sc, "enabling UMAC\n");
2319 /* This register opens the gate for the UMAC despite its name */
2320 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
2322 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
2323 UMAC_COMMAND_CONFIG_REG_PAD_EN |
2324 UMAC_COMMAND_CONFIG_REG_SW_RESET |
2325 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
2326 switch (vars->line_speed) {
2327 case ELINK_SPEED_10:
2330 case ELINK_SPEED_100:
2333 case ELINK_SPEED_1000:
2336 case ELINK_SPEED_2500:
2340 ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d\n",
2344 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2345 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
2347 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2348 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
2350 if (vars->duplex == DUPLEX_HALF)
2351 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
2353 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2356 /* Configure UMAC for EEE */
2357 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2358 ELINK_DEBUG_P0(sc, "configured UMAC for EEE\n");
2359 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
2360 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
2361 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
2363 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
2366 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
2367 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
2368 ((params->mac_addr[2] << 24) |
2369 (params->mac_addr[3] << 16) |
2370 (params->mac_addr[4] << 8) |
2371 (params->mac_addr[5])));
2372 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
2373 ((params->mac_addr[0] << 8) |
2374 (params->mac_addr[1])));
2376 /* Enable RX and TX */
2377 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
2378 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
2379 UMAC_COMMAND_CONFIG_REG_RX_ENA;
2380 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2383 /* Remove SW Reset */
2384 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
2386 /* Check loopback mode */
2388 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
2389 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2391 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
2392 * length used by the MAC receive logic to check frames.
2394 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
2395 elink_set_xumac_nig(params,
2396 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2397 vars->mac_type = ELINK_MAC_TYPE_UMAC;
2401 /* Define the XMAC mode */
2402 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
2404 struct bxe_softc *sc = params->sc;
2405 uint32_t is_port4mode = elink_is_4_port_mode(sc);
2407 /* In 4-port mode, need to set the mode only once, so if XMAC is
2408 * already out of reset, it means the mode has already been set,
2409 * and it must not* reset the XMAC again, since it controls both
2413 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
2414 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
2415 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
2417 (REG_RD(sc, MISC_REG_RESET_REG_2) &
2418 MISC_REGISTERS_RESET_REG_2_XMAC)) {
2420 "XMAC already out of reset in 4-port mode\n");
2425 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2426 MISC_REGISTERS_RESET_REG_2_XMAC);
2429 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2430 MISC_REGISTERS_RESET_REG_2_XMAC);
2432 ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path\n");
2434 /* Set the number of ports on the system side to up to 2 */
2435 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
2437 /* Set the number of ports on the Warp Core to 10G */
2438 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2440 /* Set the number of ports on the system side to 1 */
2441 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
2442 if (max_speed == ELINK_SPEED_10000) {
2444 "Init XMAC to 10G x 1 port per path\n");
2445 /* Set the number of ports on the Warp Core to 10G */
2446 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2449 "Init XMAC to 20G x 2 ports per path\n");
2450 /* Set the number of ports on the Warp Core to 20G */
2451 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
2455 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2456 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2459 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2460 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2464 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
2466 uint8_t port = params->port;
2467 struct bxe_softc *sc = params->sc;
2468 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2471 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2472 MISC_REGISTERS_RESET_REG_2_XMAC) {
2473 /* Send an indication to change the state in the NIG back to XON
2474 * Clearing this bit enables the next set of this bit to get
2477 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
2478 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2479 (pfc_ctrl & ~(1<<1)));
2480 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2481 (pfc_ctrl | (1<<1)));
2482 ELINK_DEBUG_P1(sc, "Disable XMAC on port %x\n", port);
2483 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
2485 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2487 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2488 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2492 static elink_status_t elink_xmac_enable(struct elink_params *params,
2493 struct elink_vars *vars, uint8_t lb)
2495 uint32_t val, xmac_base;
2496 struct bxe_softc *sc = params->sc;
2497 ELINK_DEBUG_P0(sc, "enabling XMAC\n");
2499 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2501 elink_xmac_init(params, vars->line_speed);
2503 /* This register determines on which events the MAC will assert
2504 * error on the i/f to the NIG along w/ EOP.
2507 /* This register tells the NIG whether to send traffic to UMAC
2510 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
2512 /* When XMAC is in XLGMII mode, disable sending idles for fault
2515 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
2516 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
2517 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
2518 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
2519 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
2520 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
2521 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
2522 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
2524 /* Set Max packet size */
2525 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
2527 /* CRC append for Tx packets */
2528 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
2531 elink_update_pfc_xmac(params, vars, 0);
2533 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2534 ELINK_DEBUG_P0(sc, "Setting XMAC for EEE\n");
2535 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
2536 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
2538 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
2541 /* Enable TX and RX */
2542 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
2544 /* Set MAC in XLGMII mode for dual-mode */
2545 if ((vars->line_speed == ELINK_SPEED_20000) &&
2546 (params->phy[ELINK_INT_PHY].supported &
2547 ELINK_SUPPORTED_20000baseKR2_Full))
2548 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
2550 /* Check loopback mode */
2552 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
2553 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2554 elink_set_xumac_nig(params,
2555 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2557 vars->mac_type = ELINK_MAC_TYPE_XMAC;
2559 return ELINK_STATUS_OK;
2562 static elink_status_t elink_emac_enable(struct elink_params *params,
2563 struct elink_vars *vars, uint8_t lb)
2565 struct bxe_softc *sc = params->sc;
2566 uint8_t port = params->port;
2567 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2570 ELINK_DEBUG_P0(sc, "enabling EMAC\n");
2573 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2574 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2576 /* enable emac and not bmac */
2577 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2579 #ifdef ELINK_INCLUDE_EMUL
2581 if (CHIP_REV_IS_EMUL(sc)) {
2582 /* Use lane 1 (of lanes 0-3) */
2583 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2584 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2589 #ifdef ELINK_INCLUDE_FPGA
2590 if (CHIP_REV_IS_FPGA(sc)) {
2591 /* Use lane 1 (of lanes 0-3) */
2592 ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA\n");
2594 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2595 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2599 if (vars->phy_flags & PHY_XGXS_FLAG) {
2600 uint32_t ser_lane = ((params->lane_config &
2601 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2602 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2604 ELINK_DEBUG_P0(sc, "XGXS\n");
2605 /* select the master lanes (out of 0-3) */
2606 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
2608 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2610 } else { /* SerDes */
2611 ELINK_DEBUG_P0(sc, "SerDes\n");
2613 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2616 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2617 EMAC_RX_MODE_RESET);
2618 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2619 EMAC_TX_MODE_RESET);
2621 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2622 if (CHIP_REV_IS_SLOW(sc)) {
2623 /* config GMII mode */
2624 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2625 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2628 /* pause enable/disable */
2629 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2630 EMAC_RX_MODE_FLOW_EN);
2632 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2633 (EMAC_TX_MODE_EXT_PAUSE_EN |
2634 EMAC_TX_MODE_FLOW_EN));
2635 if (!(params->feature_config_flags &
2636 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2637 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2638 elink_bits_en(sc, emac_base +
2639 EMAC_REG_EMAC_RX_MODE,
2640 EMAC_RX_MODE_FLOW_EN);
2642 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2643 elink_bits_en(sc, emac_base +
2644 EMAC_REG_EMAC_TX_MODE,
2645 (EMAC_TX_MODE_EXT_PAUSE_EN |
2646 EMAC_TX_MODE_FLOW_EN));
2648 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2649 EMAC_TX_MODE_FLOW_EN);
2650 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2654 /* KEEP_VLAN_TAG, promiscuous */
2655 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
2656 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2658 /* Setting this bit causes MAC control frames (except for pause
2659 * frames) to be passed on for processing. This setting has no
2660 * affect on the operation of the pause frames. This bit effects
2661 * all packets regardless of RX Parser packet sorting logic.
2662 * Turn the PFC off to make sure we are in Xon state before
2665 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
2666 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2667 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2668 /* Enable PFC again */
2669 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
2670 EMAC_REG_RX_PFC_MODE_RX_EN |
2671 EMAC_REG_RX_PFC_MODE_TX_EN |
2672 EMAC_REG_RX_PFC_MODE_PRIORITIES);
2674 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
2676 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
2678 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
2679 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
2681 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
2684 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2689 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
2692 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1);
2694 /* Enable emac for jumbo packets */
2695 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
2696 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2697 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));
2700 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2702 /* Disable the NIG in/out to the bmac */
2703 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2704 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2705 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2707 /* Enable the NIG in/out to the emac */
2708 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2710 if ((params->feature_config_flags &
2711 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2712 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2715 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2716 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2718 #ifdef ELINK_INCLUDE_EMUL
2719 if (CHIP_REV_IS_EMUL(sc)) {
2720 /* Take the BigMac out of reset */
2721 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2722 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2724 /* Enable access for bmac registers */
2725 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2728 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
2730 vars->mac_type = ELINK_MAC_TYPE_EMAC;
2731 return ELINK_STATUS_OK;
2734 static void elink_update_pfc_bmac1(struct elink_params *params,
2735 struct elink_vars *vars)
2737 uint32_t wb_data[2];
2738 struct bxe_softc *sc = params->sc;
2739 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2740 NIG_REG_INGRESS_BMAC0_MEM;
2742 uint32_t val = 0x14;
2743 if ((!(params->feature_config_flags &
2744 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2745 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2746 /* Enable BigMAC to react on received Pause packets */
2750 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2754 if (!(params->feature_config_flags &
2755 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2756 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2760 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2763 static void elink_update_pfc_bmac2(struct elink_params *params,
2764 struct elink_vars *vars,
2767 /* Set rx control: Strip CRC and enable BigMAC to relay
2768 * control packets to the system as well
2770 uint32_t wb_data[2];
2771 struct bxe_softc *sc = params->sc;
2772 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2773 NIG_REG_INGRESS_BMAC0_MEM;
2774 uint32_t val = 0x14;
2776 if ((!(params->feature_config_flags &
2777 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2778 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2779 /* Enable BigMAC to react on received Pause packets */
2783 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2788 if (!(params->feature_config_flags &
2789 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2790 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2794 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2796 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2797 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2798 /* Enable PFC RX & TX & STATS and set 8 COS */
2800 wb_data[0] |= (1<<0); /* RX */
2801 wb_data[0] |= (1<<1); /* TX */
2802 wb_data[0] |= (1<<2); /* Force initial Xon */
2803 wb_data[0] |= (1<<3); /* 8 cos */
2804 wb_data[0] |= (1<<5); /* STATS */
2806 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2808 /* Clear the force Xon */
2809 wb_data[0] &= ~(1<<2);
2811 ELINK_DEBUG_P0(sc, "PFC is disabled\n");
2812 /* Disable PFC RX & TX & STATS and set 8 COS */
2817 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2819 /* Set Time (based unit is 512 bit time) between automatic
2820 * re-sending of PP packets amd enable automatic re-send of
2821 * Per-Priroity Packet as long as pp_gen is asserted and
2822 * pp_disable is low.
2825 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2826 val |= (1<<16); /* enable automatic re-send */
2830 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2834 val = 0x3; /* Enable RX and TX */
2836 val |= 0x4; /* Local loopback */
2837 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
2839 /* When PFC enabled, Pass pause frames towards the NIG. */
2840 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2841 val |= ((1<<6)|(1<<5));
2845 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2848 /******************************************************************************
2850 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2851 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2852 ******************************************************************************/
2853 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bxe_softc *sc,
2855 uint32_t priority_mask, uint8_t port)
2857 uint32_t nig_reg_rx_priority_mask_add = 0;
2859 switch (cos_entry) {
2861 nig_reg_rx_priority_mask_add = (port) ?
2862 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2863 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2866 nig_reg_rx_priority_mask_add = (port) ?
2867 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2868 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2871 nig_reg_rx_priority_mask_add = (port) ?
2872 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2873 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2877 return ELINK_STATUS_ERROR;
2878 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2882 return ELINK_STATUS_ERROR;
2883 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2887 return ELINK_STATUS_ERROR;
2888 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2892 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
2894 return ELINK_STATUS_OK;
2896 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
2898 struct bxe_softc *sc = params->sc;
2900 REG_WR(sc, params->shmem_base +
2901 offsetof(struct shmem_region,
2902 port_mb[params->port].link_status), link_status);
2905 static void elink_update_link_attr(struct elink_params *params, uint32_t link_attr)
2907 struct bxe_softc *sc = params->sc;
2909 if (SHMEM2_HAS(sc, link_attr_sync))
2910 REG_WR(sc, params->shmem2_base +
2911 offsetof(struct shmem2_region,
2912 link_attr_sync[params->port]), link_attr);
2915 static void elink_update_pfc_nig(struct elink_params *params,
2916 struct elink_vars *vars,
2917 struct elink_nig_brb_pfc_port_params *nig_params)
2919 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2920 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2921 uint32_t pkt_priority_to_cos = 0;
2922 struct bxe_softc *sc = params->sc;
2923 uint8_t port = params->port;
2925 int set_pfc = params->feature_config_flags &
2926 ELINK_FEATURE_CONFIG_PFC_ENABLED;
2927 ELINK_DEBUG_P0(sc, "updating pfc nig parameters\n");
2929 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2930 * MAC control frames (that are not pause packets)
2931 * will be forwarded to the XCM.
2933 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
2934 NIG_REG_LLH0_XCM_MASK);
2935 /* NIG params will override non PFC params, since it's possible to
2936 * do transition from PFC to SAFC
2946 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2947 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2952 llfc_out_en = nig_params->llfc_out_en;
2953 llfc_enable = nig_params->llfc_enable;
2954 pause_enable = nig_params->pause_enable;
2955 } else /* Default non PFC mode - PAUSE */
2958 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2959 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2964 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2965 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2966 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
2967 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2968 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
2969 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2970 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
2971 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2973 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
2974 NIG_REG_PPP_ENABLE_0, ppp_enable);
2976 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
2977 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2979 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2980 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2982 /* Output enable for RX_XCM # IF */
2983 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
2984 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2986 /* HW PFC TX enable */
2987 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
2988 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2992 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2994 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2995 elink_pfc_nig_rx_priority_mask(sc, i,
2996 nig_params->rx_cos_priority_mask[i], port);
2998 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2999 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
3000 nig_params->llfc_high_priority_classes);
3002 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
3003 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
3004 nig_params->llfc_low_priority_classes);
3006 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
3007 NIG_REG_P0_PKT_PRIORITY_TO_COS,
3008 pkt_priority_to_cos);
3011 elink_status_t elink_update_pfc(struct elink_params *params,
3012 struct elink_vars *vars,
3013 struct elink_nig_brb_pfc_port_params *pfc_params)
3015 /* The PFC and pause are orthogonal to one another, meaning when
3016 * PFC is enabled, the pause are disabled, and when PFC is
3017 * disabled, pause are set according to the pause result.
3020 struct bxe_softc *sc = params->sc;
3021 elink_status_t elink_status = ELINK_STATUS_OK;
3022 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
3024 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
3025 vars->link_status |= LINK_STATUS_PFC_ENABLED;
3027 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
3029 elink_update_mng(params, vars->link_status);
3031 /* Update NIG params */
3032 elink_update_pfc_nig(params, vars, pfc_params);
3035 return elink_status;
3037 ELINK_DEBUG_P0(sc, "About to update PFC in BMAC\n");
3039 if (CHIP_IS_E3(sc)) {
3040 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
3041 elink_update_pfc_xmac(params, vars, 0);
3043 val = REG_RD(sc, MISC_REG_RESET_REG_2);
3045 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
3047 ELINK_DEBUG_P0(sc, "About to update PFC in EMAC\n");
3048 elink_emac_enable(params, vars, 0);
3049 return elink_status;
3052 elink_update_pfc_bmac2(params, vars, bmac_loopback);
3054 elink_update_pfc_bmac1(params, vars);
3057 if ((params->feature_config_flags &
3058 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3059 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3061 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
3063 return elink_status;
3066 static elink_status_t elink_bmac1_enable(struct elink_params *params,
3067 struct elink_vars *vars,
3070 struct bxe_softc *sc = params->sc;
3071 uint8_t port = params->port;
3072 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3073 NIG_REG_INGRESS_BMAC0_MEM;
3074 uint32_t wb_data[2];
3077 ELINK_DEBUG_P0(sc, "Enabling BigMAC1\n");
3082 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
3086 wb_data[0] = ((params->mac_addr[2] << 24) |
3087 (params->mac_addr[3] << 16) |
3088 (params->mac_addr[4] << 8) |
3089 params->mac_addr[5]);
3090 wb_data[1] = ((params->mac_addr[0] << 8) |
3091 params->mac_addr[1]);
3092 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
3098 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
3102 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
3105 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3107 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
3109 elink_update_pfc_bmac1(params, vars);
3112 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3114 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
3116 /* Set cnt max size */
3117 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3119 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3121 /* Configure SAFC */
3122 wb_data[0] = 0x1000200;
3124 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
3126 #ifdef ELINK_INCLUDE_EMUL
3127 /* Fix for emulation */
3128 if (CHIP_REV_IS_EMUL(sc)) {
3129 wb_data[0] = 0xf000;
3131 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
3136 return ELINK_STATUS_OK;
3139 static elink_status_t elink_bmac2_enable(struct elink_params *params,
3140 struct elink_vars *vars,
3143 struct bxe_softc *sc = params->sc;
3144 uint8_t port = params->port;
3145 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3146 NIG_REG_INGRESS_BMAC0_MEM;
3147 uint32_t wb_data[2];
3149 ELINK_DEBUG_P0(sc, "Enabling BigMAC2\n");
3153 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3156 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
3159 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
3165 wb_data[0] = ((params->mac_addr[2] << 24) |
3166 (params->mac_addr[3] << 16) |
3167 (params->mac_addr[4] << 8) |
3168 params->mac_addr[5]);
3169 wb_data[1] = ((params->mac_addr[0] << 8) |
3170 params->mac_addr[1]);
3171 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
3176 /* Configure SAFC */
3177 wb_data[0] = 0x1000200;
3179 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
3184 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3186 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
3190 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3192 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
3194 /* Set cnt max size */
3195 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
3197 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3199 elink_update_pfc_bmac2(params, vars, is_lb);
3201 return ELINK_STATUS_OK;
3204 static elink_status_t elink_bmac_enable(struct elink_params *params,
3205 struct elink_vars *vars,
3206 uint8_t is_lb, uint8_t reset_bmac)
3208 elink_status_t rc = ELINK_STATUS_OK;
3209 uint8_t port = params->port;
3210 struct bxe_softc *sc = params->sc;
3212 /* Reset and unreset the BigMac */
3214 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3215 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3219 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
3220 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3222 /* Enable access for bmac registers */
3223 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
3225 /* Enable BMAC according to BMAC type*/
3227 rc = elink_bmac2_enable(params, vars, is_lb);
3229 rc = elink_bmac1_enable(params, vars, is_lb);
3230 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
3231 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
3232 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
3234 if ((params->feature_config_flags &
3235 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3236 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3238 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
3239 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
3240 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
3241 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
3242 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
3243 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
3245 vars->mac_type = ELINK_MAC_TYPE_BMAC;
3249 static void elink_set_bmac_rx(struct bxe_softc *sc, uint32_t chip_id, uint8_t port, uint8_t en)
3251 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3252 NIG_REG_INGRESS_BMAC0_MEM;
3253 uint32_t wb_data[2];
3254 uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
3257 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
3259 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
3260 /* Only if the bmac is out of reset */
3261 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
3262 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
3264 /* Clear Rx Enable bit in BMAC_CONTROL register */
3265 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
3267 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
3269 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
3270 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
3275 static elink_status_t elink_pbf_update(struct elink_params *params, uint32_t flow_ctrl,
3276 uint32_t line_speed)
3278 struct bxe_softc *sc = params->sc;
3279 uint8_t port = params->port;
3280 uint32_t init_crd, crd;
3281 uint32_t count = 1000;
3284 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
3286 /* Wait for init credit */
3287 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);
3288 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3289 ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
3291 while ((init_crd != crd) && count) {
3293 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3296 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3297 if (init_crd != crd) {
3298 ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x\n",
3300 return ELINK_STATUS_ERROR;
3303 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
3304 line_speed == ELINK_SPEED_10 ||
3305 line_speed == ELINK_SPEED_100 ||
3306 line_speed == ELINK_SPEED_1000 ||
3307 line_speed == ELINK_SPEED_2500) {
3308 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
3309 /* Update threshold */
3310 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0);
3311 /* Update init credit */
3312 init_crd = 778; /* (800-18-4) */
3315 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
3316 ELINK_ETH_OVREHEAD)/16;
3317 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
3318 /* Update threshold */
3319 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh);
3320 /* Update init credit */
3321 switch (line_speed) {
3322 case ELINK_SPEED_10000:
3323 init_crd = thresh + 553 - 22;
3326 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
3328 return ELINK_STATUS_ERROR;
3331 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd);
3332 ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d\n",
3333 line_speed, init_crd);
3335 /* Probe the credit changes */
3336 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1);
3338 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0);
3341 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
3342 return ELINK_STATUS_OK;
3346 * elink_get_emac_base - retrive emac base address
3348 * @bp: driver handle
3349 * @mdc_mdio_access: access type
3352 * This function selects the MDC/MDIO access (through emac0 or
3353 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
3354 * phy has a default access mode, which could also be overridden
3355 * by nvram configuration. This parameter, whether this is the
3356 * default phy configuration, or the nvram overrun
3357 * configuration, is passed here as mdc_mdio_access and selects
3358 * the emac_base for the CL45 read/writes operations
3360 static uint32_t elink_get_emac_base(struct bxe_softc *sc,
3361 uint32_t mdc_mdio_access, uint8_t port)
3363 uint32_t emac_base = 0;
3364 switch (mdc_mdio_access) {
3365 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
3367 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
3368 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3369 emac_base = GRCBASE_EMAC1;
3371 emac_base = GRCBASE_EMAC0;
3373 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
3374 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3375 emac_base = GRCBASE_EMAC0;
3377 emac_base = GRCBASE_EMAC1;
3379 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
3380 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3382 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
3383 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3392 /******************************************************************/
3393 /* CL22 access functions */
3394 /******************************************************************/
3395 static elink_status_t elink_cl22_write(struct bxe_softc *sc,
3396 struct elink_phy *phy,
3397 uint16_t reg, uint16_t val)
3401 elink_status_t rc = ELINK_STATUS_OK;
3402 /* Switch to CL22 */
3403 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3404 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3405 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3408 tmp = ((phy->addr << 21) | (reg << 16) | val |
3409 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3410 EMAC_MDIO_COMM_START_BUSY);
3411 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3413 for (i = 0; i < 50; i++) {
3416 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3417 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3422 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3423 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3424 rc = ELINK_STATUS_TIMEOUT;
3426 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3430 static elink_status_t elink_cl22_read(struct bxe_softc *sc,
3431 struct elink_phy *phy,
3432 uint16_t reg, uint16_t *ret_val)
3436 elink_status_t rc = ELINK_STATUS_OK;
3438 /* Switch to CL22 */
3439 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3440 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3441 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3444 val = ((phy->addr << 21) | (reg << 16) |
3445 EMAC_MDIO_COMM_COMMAND_READ_22 |
3446 EMAC_MDIO_COMM_START_BUSY);
3447 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3449 for (i = 0; i < 50; i++) {
3452 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3453 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3454 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3459 if (val & EMAC_MDIO_COMM_START_BUSY) {
3460 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3463 rc = ELINK_STATUS_TIMEOUT;
3465 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3469 /******************************************************************/
3470 /* CL45 access functions */
3471 /******************************************************************/
3472 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,
3473 uint8_t devad, uint16_t reg, uint16_t *ret_val)
3477 elink_status_t rc = ELINK_STATUS_OK;
3479 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3480 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3481 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3482 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3485 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3486 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3487 EMAC_MDIO_STATUS_10MB);
3489 val = ((phy->addr << 21) | (devad << 16) | reg |
3490 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3491 EMAC_MDIO_COMM_START_BUSY);
3492 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3494 for (i = 0; i < 50; i++) {
3497 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3498 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3503 if (val & EMAC_MDIO_COMM_START_BUSY) {
3504 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3505 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3508 rc = ELINK_STATUS_TIMEOUT;
3511 val = ((phy->addr << 21) | (devad << 16) |
3512 EMAC_MDIO_COMM_COMMAND_READ_45 |
3513 EMAC_MDIO_COMM_START_BUSY);
3514 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3516 for (i = 0; i < 50; i++) {
3519 val = REG_RD(sc, phy->mdio_ctrl +
3520 EMAC_REG_EMAC_MDIO_COMM);
3521 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3522 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3526 if (val & EMAC_MDIO_COMM_START_BUSY) {
3527 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3528 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3531 rc = ELINK_STATUS_TIMEOUT;
3534 /* Work around for E3 A0 */
3535 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3536 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3537 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3539 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3543 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3544 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3545 EMAC_MDIO_STATUS_10MB);
3549 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,
3550 uint8_t devad, uint16_t reg, uint16_t val)
3554 elink_status_t rc = ELINK_STATUS_OK;
3556 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3557 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3558 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3559 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3562 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3563 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3564 EMAC_MDIO_STATUS_10MB);
3567 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3568 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3569 EMAC_MDIO_COMM_START_BUSY);
3570 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3572 for (i = 0; i < 50; i++) {
3575 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3576 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3581 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3582 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3583 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3585 rc = ELINK_STATUS_TIMEOUT;
3588 tmp = ((phy->addr << 21) | (devad << 16) | val |
3589 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3590 EMAC_MDIO_COMM_START_BUSY);
3591 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3593 for (i = 0; i < 50; i++) {
3596 tmp = REG_RD(sc, phy->mdio_ctrl +
3597 EMAC_REG_EMAC_MDIO_COMM);
3598 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3603 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3604 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3605 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3607 rc = ELINK_STATUS_TIMEOUT;
3610 /* Work around for E3 A0 */
3611 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3612 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3613 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3615 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3618 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3619 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3620 EMAC_MDIO_STATUS_10MB);
3624 /******************************************************************/
3626 /******************************************************************/
3627 static uint8_t elink_eee_has_cap(struct elink_params *params)
3629 struct bxe_softc *sc = params->sc;
3631 if (REG_RD(sc, params->shmem2_base) <=
3632 offsetof(struct shmem2_region, eee_status[params->port]))
3638 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, uint32_t *idle_timer)
3640 switch (nvram_mode) {
3641 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
3642 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
3644 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
3645 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
3647 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
3648 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
3655 return ELINK_STATUS_OK;
3658 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, uint32_t *nvram_mode)
3660 switch (idle_timer) {
3661 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
3662 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
3664 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
3665 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
3667 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
3668 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
3671 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
3675 return ELINK_STATUS_OK;
3678 static uint32_t elink_eee_calc_timer(struct elink_params *params)
3680 uint32_t eee_mode, eee_idle;
3681 struct bxe_softc *sc = params->sc;
3683 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
3684 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3685 /* time value in eee_mode --> used directly*/
3686 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
3688 /* hsi value in eee_mode --> time */
3689 if (elink_eee_nvram_to_time(params->eee_mode &
3690 ELINK_EEE_MODE_NVRAM_MASK,
3695 /* hsi values in nvram --> time*/
3696 eee_mode = ((REG_RD(sc, params->shmem_base +
3697 offsetof(struct shmem_region, dev_info.
3698 port_feature_config[params->port].
3700 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
3701 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
3703 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
3710 static elink_status_t elink_eee_set_timers(struct elink_params *params,
3711 struct elink_vars *vars)
3713 uint32_t eee_idle = 0, eee_mode;
3714 struct bxe_softc *sc = params->sc;
3716 eee_idle = elink_eee_calc_timer(params);
3719 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3721 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
3722 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
3723 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
3724 ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0\n");
3725 return ELINK_STATUS_ERROR;
3728 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
3729 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3730 /* eee_idle in 1u --> eee_status in 16u */
3732 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
3733 SHMEM_EEE_TIME_OUTPUT_BIT;
3735 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
3736 return ELINK_STATUS_ERROR;
3737 vars->eee_status |= eee_mode;
3740 return ELINK_STATUS_OK;
3743 static elink_status_t elink_eee_initial_config(struct elink_params *params,
3744 struct elink_vars *vars, uint8_t mode)
3746 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
3748 /* Propogate params' bits --> vars (for migration exposure) */
3749 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
3750 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
3752 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
3754 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
3755 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
3757 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
3759 return elink_eee_set_timers(params, vars);
3762 static elink_status_t elink_eee_disable(struct elink_phy *phy,
3763 struct elink_params *params,
3764 struct elink_vars *vars)
3766 struct bxe_softc *sc = params->sc;
3768 /* Make Certain LPI is disabled */
3769 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3771 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3773 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3775 return ELINK_STATUS_OK;
3778 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
3779 struct elink_params *params,
3780 struct elink_vars *vars, uint8_t modes)
3782 struct bxe_softc *sc = params->sc;
3785 /* Mask events preventing LPI generation */
3786 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3788 if (modes & SHMEM_EEE_10G_ADV) {
3789 ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE\n");
3792 if (modes & SHMEM_EEE_1G_ADV) {
3793 ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE\n");
3797 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3799 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3800 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3802 return ELINK_STATUS_OK;
3805 static void elink_update_mng_eee(struct elink_params *params, uint32_t eee_status)
3807 struct bxe_softc *sc = params->sc;
3809 if (elink_eee_has_cap(params))
3810 REG_WR(sc, params->shmem2_base +
3811 offsetof(struct shmem2_region,
3812 eee_status[params->port]), eee_status);
3815 static void elink_eee_an_resolve(struct elink_phy *phy,
3816 struct elink_params *params,
3817 struct elink_vars *vars)
3819 struct bxe_softc *sc = params->sc;
3820 uint16_t adv = 0, lp = 0;
3821 uint32_t lp_adv = 0;
3824 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3825 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3828 lp_adv |= SHMEM_EEE_100M_ADV;
3830 if (vars->line_speed == ELINK_SPEED_100)
3832 ELINK_DEBUG_P0(sc, "EEE negotiated - 100M\n");
3836 lp_adv |= SHMEM_EEE_1G_ADV;
3838 if (vars->line_speed == ELINK_SPEED_1000)
3840 ELINK_DEBUG_P0(sc, "EEE negotiated - 1G\n");
3844 lp_adv |= SHMEM_EEE_10G_ADV;
3846 if (vars->line_speed == ELINK_SPEED_10000)
3848 ELINK_DEBUG_P0(sc, "EEE negotiated - 10G\n");
3852 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3853 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3856 ELINK_DEBUG_P0(sc, "EEE is active\n");
3857 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3861 /******************************************************************/
3862 /* BSC access functions from E3 */
3863 /******************************************************************/
3864 static void elink_bsc_module_sel(struct elink_params *params)
3867 uint32_t board_cfg, sfp_ctrl;
3868 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3869 struct bxe_softc *sc = params->sc;
3870 uint8_t port = params->port;
3871 /* Read I2C output PINs */
3872 board_cfg = REG_RD(sc, params->shmem_base +
3873 offsetof(struct shmem_region,
3874 dev_info.shared_hw_config.board));
3875 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3876 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3877 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3879 /* Read I2C output value */
3880 sfp_ctrl = REG_RD(sc, params->shmem_base +
3881 offsetof(struct shmem_region,
3882 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3883 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3884 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3885 ELINK_DEBUG_P0(sc, "Setting BSC switch\n");
3886 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3887 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
3890 static elink_status_t elink_bsc_read(struct elink_params *params,
3891 struct bxe_softc *sc,
3896 uint32_t *data_array)
3899 elink_status_t rc = ELINK_STATUS_OK;
3901 if (xfer_cnt > 16) {
3902 ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes\n",
3904 return ELINK_STATUS_ERROR;
3907 elink_bsc_module_sel(params);
3909 xfer_cnt = 16 - lc_addr;
3911 /* Enable the engine */
3912 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3913 val |= MCPR_IMC_COMMAND_ENABLE;
3914 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3916 /* Program slave device ID */
3917 val = (sl_devid << 16) | sl_addr;
3918 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3920 /* Start xfer with 0 byte to update the address pointer ???*/
3921 val = (MCPR_IMC_COMMAND_ENABLE) |
3922 (MCPR_IMC_COMMAND_WRITE_OP <<
3923 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3924 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3925 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3927 /* Poll for completion */
3929 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3930 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3932 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3934 ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try\n",
3936 rc = ELINK_STATUS_TIMEOUT;
3940 if (rc == ELINK_STATUS_TIMEOUT)
3943 /* Start xfer with read op */
3944 val = (MCPR_IMC_COMMAND_ENABLE) |
3945 (MCPR_IMC_COMMAND_READ_OP <<
3946 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3947 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3949 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3951 /* Poll for completion */
3953 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3954 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3956 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3958 ELINK_DEBUG_P1(sc, "rd op timed out after %d try\n", i);
3959 rc = ELINK_STATUS_TIMEOUT;
3963 if (rc == ELINK_STATUS_TIMEOUT)
3966 for (i = (lc_addr >> 2); i < 4; i++) {
3967 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3969 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3970 ((data_array[i] & 0x0000ff00) << 8) |
3971 ((data_array[i] & 0x00ff0000) >> 8) |
3972 ((data_array[i] & 0xff000000) >> 24);
3978 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,
3979 uint8_t devad, uint16_t reg, uint16_t or_val)
3982 elink_cl45_read(sc, phy, devad, reg, &val);
3983 elink_cl45_write(sc, phy, devad, reg, val | or_val);
3986 static void elink_cl45_read_and_write(struct bxe_softc *sc,
3987 struct elink_phy *phy,
3988 uint8_t devad, uint16_t reg, uint16_t and_val)
3991 elink_cl45_read(sc, phy, devad, reg, &val);
3992 elink_cl45_write(sc, phy, devad, reg, val & and_val);
3995 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
3996 uint8_t devad, uint16_t reg, uint16_t *ret_val)
3999 /* Probe for the phy according to the given phy_addr, and execute
4000 * the read request on it
4002 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4003 if (params->phy[phy_index].addr == phy_addr) {
4004 return elink_cl45_read(params->sc,
4005 ¶ms->phy[phy_index], devad,
4009 return ELINK_STATUS_ERROR;
4012 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
4013 uint8_t devad, uint16_t reg, uint16_t val)
4016 /* Probe for the phy according to the given phy_addr, and execute
4017 * the write request on it
4019 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4020 if (params->phy[phy_index].addr == phy_addr) {
4021 return elink_cl45_write(params->sc,
4022 ¶ms->phy[phy_index], devad,
4026 return ELINK_STATUS_ERROR;
4028 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,
4029 struct elink_params *params)
4032 struct bxe_softc *sc = params->sc;
4033 uint32_t path_swap, path_swap_ovr;
4037 port = params->port;
4039 if (elink_is_4_port_mode(sc)) {
4040 uint32_t port_swap, port_swap_ovr;
4042 /* Figure out path swap value */
4043 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
4044 if (path_swap_ovr & 0x1)
4045 path_swap = (path_swap_ovr & 0x2);
4047 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
4052 /* Figure out port swap value */
4053 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
4054 if (port_swap_ovr & 0x1)
4055 port_swap = (port_swap_ovr & 0x2);
4057 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
4062 lane = (port<<1) + path;
4063 } else { /* Two port mode - no port swap */
4065 /* Figure out path swap value */
4067 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
4068 if (path_swap_ovr & 0x1) {
4069 path_swap = (path_swap_ovr & 0x2);
4072 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
4082 static void elink_set_aer_mmd(struct elink_params *params,
4083 struct elink_phy *phy)
4086 uint16_t offset, aer_val;
4087 struct bxe_softc *sc = params->sc;
4088 ser_lane = ((params->lane_config &
4089 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4090 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4092 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
4093 (phy->addr + ser_lane) : 0;
4095 if (USES_WARPCORE(sc)) {
4096 aer_val = elink_get_warpcore_lane(phy, params);
4097 /* In Dual-lane mode, two lanes are joined together,
4098 * so in order to configure them, the AER broadcast method is
4100 * 0x200 is the broadcast address for lanes 0,1
4101 * 0x201 is the broadcast address for lanes 2,3
4103 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4104 aer_val = (aer_val >> 1) | 0x200;
4105 } else if (CHIP_IS_E2(sc))
4106 aer_val = 0x3800 + offset - 1;
4108 aer_val = 0x3800 + offset;
4110 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4111 MDIO_AER_BLOCK_AER_REG, aer_val);
4115 /******************************************************************/
4116 /* Internal phy section */
4117 /******************************************************************/
4119 static void elink_set_serdes_access(struct bxe_softc *sc, uint8_t port)
4121 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
4124 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
4125 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
4127 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
4130 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
4133 static void elink_serdes_deassert(struct bxe_softc *sc, uint8_t port)
4137 ELINK_DEBUG_P0(sc, "elink_serdes_deassert\n");
4139 val = ELINK_SERDES_RESET_BITS << (port*16);
4141 /* Reset and unreset the SerDes/XGXS */
4142 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4144 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4146 elink_set_serdes_access(sc, port);
4148 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
4149 ELINK_DEFAULT_PHY_DEV_ADDR);
4152 static void elink_xgxs_specific_func(struct elink_phy *phy,
4153 struct elink_params *params,
4156 struct bxe_softc *sc = params->sc;
4158 case ELINK_PHY_INIT:
4159 /* Set correct devad */
4160 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
4161 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
4167 static void elink_xgxs_deassert(struct elink_params *params)
4169 struct bxe_softc *sc = params->sc;
4172 ELINK_DEBUG_P0(sc, "elink_xgxs_deassert\n");
4173 port = params->port;
4175 val = ELINK_XGXS_RESET_BITS << (port*16);
4177 /* Reset and unreset the SerDes/XGXS */
4178 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4180 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4181 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
4185 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
4186 struct elink_params *params, uint16_t *ieee_fc)
4188 struct bxe_softc *sc = params->sc;
4189 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
4190 /* Resolve pause mode and advertisement Please refer to Table
4191 * 28B-3 of the 802.3ab-1999 spec
4194 switch (phy->req_flow_ctrl) {
4195 case ELINK_FLOW_CTRL_AUTO:
4196 switch (params->req_fc_auto_adv) {
4197 case ELINK_FLOW_CTRL_BOTH:
4198 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4200 case ELINK_FLOW_CTRL_RX:
4201 case ELINK_FLOW_CTRL_TX:
4203 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4209 case ELINK_FLOW_CTRL_TX:
4210 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4213 case ELINK_FLOW_CTRL_RX:
4214 case ELINK_FLOW_CTRL_BOTH:
4215 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4218 case ELINK_FLOW_CTRL_NONE:
4220 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
4223 ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x\n", *ieee_fc);
4226 static void set_phy_vars(struct elink_params *params,
4227 struct elink_vars *vars)
4229 struct bxe_softc *sc = params->sc;
4230 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
4231 uint8_t phy_config_swapped = params->multi_phy_config &
4232 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
4233 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
4235 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
4236 actual_phy_idx = phy_index;
4237 if (phy_config_swapped) {
4238 if (phy_index == ELINK_EXT_PHY1)
4239 actual_phy_idx = ELINK_EXT_PHY2;
4240 else if (phy_index == ELINK_EXT_PHY2)
4241 actual_phy_idx = ELINK_EXT_PHY1;
4243 params->phy[actual_phy_idx].req_flow_ctrl =
4244 params->req_flow_ctrl[link_cfg_idx];
4246 params->phy[actual_phy_idx].req_line_speed =
4247 params->req_line_speed[link_cfg_idx];
4249 params->phy[actual_phy_idx].speed_cap_mask =
4250 params->speed_cap_mask[link_cfg_idx];
4252 params->phy[actual_phy_idx].req_duplex =
4253 params->req_duplex[link_cfg_idx];
4255 if (params->req_line_speed[link_cfg_idx] ==
4256 ELINK_SPEED_AUTO_NEG)
4257 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
4259 ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x,"
4260 " speed_cap_mask %x\n",
4261 params->phy[actual_phy_idx].req_flow_ctrl,
4262 params->phy[actual_phy_idx].req_line_speed,
4263 params->phy[actual_phy_idx].speed_cap_mask);
4267 static void elink_ext_phy_set_pause(struct elink_params *params,
4268 struct elink_phy *phy,
4269 struct elink_vars *vars)
4272 struct bxe_softc *sc = params->sc;
4273 /* Read modify write pause advertizing */
4274 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
4276 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
4278 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4279 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4280 if ((vars->ieee_fc &
4281 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4282 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4283 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
4285 if ((vars->ieee_fc &
4286 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4287 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4288 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
4290 ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x\n", val);
4291 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
4294 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
4296 switch (pause_result) { /* ASYM P ASYM P */
4297 case 0xb: /* 1 0 1 1 */
4298 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
4301 case 0xe: /* 1 1 1 0 */
4302 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
4305 case 0x5: /* 0 1 0 1 */
4306 case 0x7: /* 0 1 1 1 */
4307 case 0xd: /* 1 1 0 1 */
4308 case 0xf: /* 1 1 1 1 */
4309 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
4315 if (pause_result & (1<<0))
4316 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
4317 if (pause_result & (1<<1))
4318 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
4322 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
4323 struct elink_params *params,
4324 struct elink_vars *vars)
4326 uint16_t ld_pause; /* local */
4327 uint16_t lp_pause; /* link partner */
4328 uint16_t pause_result;
4329 struct bxe_softc *sc = params->sc;
4330 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
4331 elink_cl22_read(sc, phy, 0x4, &ld_pause);
4332 elink_cl22_read(sc, phy, 0x5, &lp_pause);
4333 } else if (CHIP_IS_E3(sc) &&
4334 ELINK_SINGLE_MEDIA_DIRECT(params)) {
4335 uint8_t lane = elink_get_warpcore_lane(phy, params);
4336 uint16_t gp_status, gp_mask;
4337 elink_cl45_read(sc, phy,
4338 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
4340 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
4341 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
4343 if ((gp_status & gp_mask) == gp_mask) {
4344 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4345 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4346 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4347 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4349 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4350 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
4351 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4352 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
4353 ld_pause = ((ld_pause &
4354 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4356 lp_pause = ((lp_pause &
4357 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4361 elink_cl45_read(sc, phy,
4363 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4364 elink_cl45_read(sc, phy,
4366 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4368 pause_result = (ld_pause &
4369 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
4370 pause_result |= (lp_pause &
4371 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
4372 ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x\n", pause_result);
4373 elink_pause_resolve(vars, pause_result);
4377 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
4378 struct elink_params *params,
4379 struct elink_vars *vars)
4382 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4383 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
4384 /* Update the advertised flow-controled of LD/LP in AN */
4385 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
4386 elink_ext_phy_update_adv_fc(phy, params, vars);
4387 /* But set the flow-control result as the requested one */
4388 vars->flow_ctrl = phy->req_flow_ctrl;
4389 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4390 vars->flow_ctrl = params->req_fc_auto_adv;
4391 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
4393 elink_ext_phy_update_adv_fc(phy, params, vars);
4397 /******************************************************************/
4398 /* Warpcore section */
4399 /******************************************************************/
4400 /* The init_internal_warpcore should mirror the xgxs,
4401 * i.e. reset the lane (if needed), set aer for the
4402 * init configuration, and set/clear SGMII flag. Internal
4403 * phy init is done purely in phy_init stage.
4405 #define WC_TX_DRIVER(post2, idriver, ipre) \
4406 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
4407 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
4408 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
4410 #define WC_TX_FIR(post, main, pre) \
4411 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
4412 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
4413 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
4415 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
4416 struct elink_params *params,
4417 struct elink_vars *vars)
4419 struct bxe_softc *sc = params->sc;
4421 static struct elink_reg_set reg_set[] = {
4422 /* Step 1 - Program the TX/RX alignment markers */
4423 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
4424 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
4425 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
4426 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
4427 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
4428 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
4429 /* Step 2 - Configure the NP registers */
4430 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
4431 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
4432 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
4433 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
4434 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
4435 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
4436 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
4437 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
4438 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
4440 ELINK_DEBUG_P0(sc, "Enabling 20G-KR2\n");
4442 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4443 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
4445 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4446 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4449 /* Start KR2 work-around timer which handles BCM8073 link-parner */
4450 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
4451 elink_update_link_attr(params, vars->link_attr_sync);
4454 static void elink_disable_kr2(struct elink_params *params,
4455 struct elink_vars *vars,
4456 struct elink_phy *phy)
4458 struct bxe_softc *sc = params->sc;
4460 static struct elink_reg_set reg_set[] = {
4461 /* Step 1 - Program the TX/RX alignment markers */
4462 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
4463 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
4464 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
4465 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
4466 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
4467 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
4468 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
4469 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
4470 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
4471 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
4472 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
4473 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
4474 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
4475 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
4476 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
4478 ELINK_DEBUG_P0(sc, "Disabling 20G-KR2\n");
4480 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4481 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4483 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
4484 elink_update_link_attr(params, vars->link_attr_sync);
4486 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
4489 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
4490 struct elink_params *params)
4492 struct bxe_softc *sc = params->sc;
4494 ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through\n");
4495 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4496 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
4497 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4498 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
4501 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
4502 struct elink_params *params)
4504 /* Restart autoneg on the leading lane only */
4505 struct bxe_softc *sc = params->sc;
4506 uint16_t lane = elink_get_warpcore_lane(phy, params);
4507 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4508 MDIO_AER_BLOCK_AER_REG, lane);
4509 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4510 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4513 elink_set_aer_mmd(params, phy);
4516 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
4517 struct elink_params *params,
4518 struct elink_vars *vars) {
4519 uint16_t lane, i, cl72_ctrl, an_adv = 0;
4520 struct bxe_softc *sc = params->sc;
4521 static struct elink_reg_set reg_set[] = {
4522 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4523 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
4524 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
4525 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
4526 /* Disable Autoneg: re-enable it after adv is done. */
4527 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
4528 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
4529 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
4531 ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR\n");
4532 /* Set to default registers that may be overriden by 10G force */
4533 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4534 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4537 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4538 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
4539 cl72_ctrl &= 0x08ff;
4540 cl72_ctrl |= 0x3800;
4541 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4542 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
4544 /* Check adding advertisement for 1G KX */
4545 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4546 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
4547 (vars->line_speed == ELINK_SPEED_1000)) {
4548 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
4551 /* Enable CL37 1G Parallel Detect */
4552 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
4553 ELINK_DEBUG_P0(sc, "Advertize 1G\n");
4555 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4556 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4557 (vars->line_speed == ELINK_SPEED_10000)) {
4558 /* Check adding advertisement for 10G KR */
4560 /* Enable 10G Parallel Detect */
4561 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4562 MDIO_AER_BLOCK_AER_REG, 0);
4564 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4565 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
4566 elink_set_aer_mmd(params, phy);
4567 ELINK_DEBUG_P0(sc, "Advertize 10G\n");
4570 /* Set Transmit PMD settings */
4571 lane = elink_get_warpcore_lane(phy, params);
4572 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4573 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4574 WC_TX_DRIVER(0x02, 0x06, 0x09));
4575 /* Configure the next lane if dual mode */
4576 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4577 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4578 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
4579 WC_TX_DRIVER(0x02, 0x06, 0x09));
4580 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4581 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
4583 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4584 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
4587 /* Advertised speeds */
4588 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4589 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
4591 /* Advertised and set FEC (Forward Error Correction) */
4592 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4593 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
4594 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
4595 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
4597 /* Enable CL37 BAM */
4598 if (REG_RD(sc, params->shmem_base +
4599 offsetof(struct shmem_region, dev_info.
4600 port_hw_config[params->port].default_cfg)) &
4601 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4602 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4603 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
4605 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
4608 /* Advertise pause */
4609 elink_ext_phy_set_pause(params, phy, vars);
4610 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
4611 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4612 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
4614 /* Over 1G - AN local device user page 1 */
4615 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4616 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
4618 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
4619 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
4620 (phy->req_line_speed == ELINK_SPEED_20000)) {
4622 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4623 MDIO_AER_BLOCK_AER_REG, lane);
4625 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4626 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
4629 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4630 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
4631 elink_set_aer_mmd(params, phy);
4633 elink_warpcore_enable_AN_KR2(phy, params, vars);
4635 elink_disable_kr2(params, vars, phy);
4638 /* Enable Autoneg: only on the main lane */
4639 elink_warpcore_restart_AN_KR(phy, params);
4642 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
4643 struct elink_params *params,
4644 struct elink_vars *vars)
4646 struct bxe_softc *sc = params->sc;
4647 uint16_t val16, i, lane;
4648 static struct elink_reg_set reg_set[] = {
4649 /* Disable Autoneg */
4650 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4651 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
4653 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
4654 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
4655 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
4656 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
4657 /* Leave cl72 training enable, needed for KR */
4658 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
4661 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4662 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4665 lane = elink_get_warpcore_lane(phy, params);
4666 /* Global registers */
4667 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4668 MDIO_AER_BLOCK_AER_REG, 0);
4669 /* Disable CL36 PCS Tx */
4670 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4671 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4672 val16 &= ~(0x0011 << lane);
4673 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4674 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4676 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4677 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4678 val16 |= (0x0303 << (lane << 1));
4679 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4680 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4682 elink_set_aer_mmd(params, phy);
4683 /* Set speed via PMA/PMD register */
4684 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4685 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4687 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4688 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
4690 /* Enable encoded forced speed */
4691 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4692 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
4694 /* Turn TX scramble payload only the 64/66 scrambler */
4695 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4696 MDIO_WC_REG_TX66_CONTROL, 0x9);
4698 /* Turn RX scramble payload only the 64/66 scrambler */
4699 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4700 MDIO_WC_REG_RX66_CONTROL, 0xF9);
4702 /* Set and clear loopback to cause a reset to 64/66 decoder */
4703 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4704 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
4705 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4706 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
4710 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
4711 struct elink_params *params,
4714 struct bxe_softc *sc = params->sc;
4715 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
4716 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
4718 /* Hold rxSeqStart */
4719 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4720 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
4722 /* Hold tx_fifo_reset */
4723 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4724 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
4726 /* Disable CL73 AN */
4727 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4729 /* Disable 100FX Enable and Auto-Detect */
4730 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4731 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
4733 /* Disable 100FX Idle detect */
4734 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4735 MDIO_WC_REG_FX100_CTRL3, 0x0080);
4737 /* Set Block address to Remote PHY & Clear forced_speed[5] */
4738 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4739 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
4741 /* Turn off auto-detect & fiber mode */
4742 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4743 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4746 /* Set filter_force_link, disable_false_link and parallel_detect */
4747 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4748 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
4749 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4750 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4751 ((val | 0x0006) & 0xFFFE));
4754 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4755 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4757 misc1_val &= ~(0x1f);
4761 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4762 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
4764 cfg_tap_val = REG_RD(sc, params->shmem_base +
4765 offsetof(struct shmem_region, dev_info.
4766 port_hw_config[params->port].
4769 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4771 tx_drv_brdct = (cfg_tap_val &
4772 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4773 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4777 /* TAP values are controlled by nvram, if value there isn't 0 */
4779 tap_val = (uint16_t)tx_equal;
4781 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4784 tx_driver_val = WC_TX_DRIVER(0x03, (uint16_t)tx_drv_brdct,
4787 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
4789 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4790 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4792 /* Set Transmit PMD settings */
4793 lane = elink_get_warpcore_lane(phy, params);
4794 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4795 MDIO_WC_REG_TX_FIR_TAP,
4796 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4797 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4798 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4801 /* Enable fiber mode, enable and invert sig_det */
4802 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4803 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4805 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4806 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4807 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4809 elink_warpcore_set_lpi_passthrough(phy, params);
4811 /* 10G XFI Full Duplex */
4812 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4813 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4815 /* Release tx_fifo_reset */
4816 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4817 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4819 /* Release rxSeqStart */
4820 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4821 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4824 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
4825 struct elink_params *params)
4828 struct bxe_softc *sc = params->sc;
4829 /* Set global registers, so set AER lane to 0 */
4830 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4831 MDIO_AER_BLOCK_AER_REG, 0);
4833 /* Disable sequencer */
4834 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4835 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4837 elink_set_aer_mmd(params, phy);
4839 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
4840 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4841 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4842 MDIO_AN_REG_CTRL, 0);
4844 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4845 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4848 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4849 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4851 /* Set 20G KR2 force speed */
4852 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4853 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4855 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4856 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4858 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4859 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4862 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4863 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4864 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4865 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4867 /* Enable sequencer (over lane 0) */
4868 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4869 MDIO_AER_BLOCK_AER_REG, 0);
4871 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4872 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4874 elink_set_aer_mmd(params, phy);
4877 static void elink_warpcore_set_20G_DXGXS(struct bxe_softc *sc,
4878 struct elink_phy *phy,
4881 /* Rx0 anaRxControl1G */
4882 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4883 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4885 /* Rx2 anaRxControl1G */
4886 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4887 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4889 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4890 MDIO_WC_REG_RX66_SCW0, 0xE070);
4892 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4893 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4895 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4896 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4898 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4899 MDIO_WC_REG_RX66_SCW3, 0x8090);
4901 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4902 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4904 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4905 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4907 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4908 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4910 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4911 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4913 /* Serdes Digital Misc1 */
4914 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4915 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4917 /* Serdes Digital4 Misc3 */
4918 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4919 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4921 /* Set Transmit PMD settings */
4922 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4923 MDIO_WC_REG_TX_FIR_TAP,
4924 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4925 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4926 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4927 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4928 WC_TX_DRIVER(0x02, 0x02, 0x02));
4931 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
4932 struct elink_params *params,
4934 uint8_t always_autoneg)
4936 struct bxe_softc *sc = params->sc;
4937 uint16_t val16, digctrl_kx1, digctrl_kx2;
4939 /* Clear XFI clock comp in non-10G single lane mode. */
4940 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4941 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4943 elink_warpcore_set_lpi_passthrough(phy, params);
4945 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
4947 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4948 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4950 ELINK_DEBUG_P0(sc, "set SGMII AUTONEG\n");
4952 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4953 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4955 switch (phy->req_line_speed) {
4956 case ELINK_SPEED_10:
4958 case ELINK_SPEED_100:
4961 case ELINK_SPEED_1000:
4966 "Speed not supported: 0x%x\n", phy->req_line_speed);
4970 if (phy->req_duplex == DUPLEX_FULL)
4973 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4974 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4976 ELINK_DEBUG_P1(sc, "set SGMII force speed %d\n",
4977 phy->req_line_speed);
4978 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4979 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4980 ELINK_DEBUG_P1(sc, " (readback) %x\n", val16);
4983 /* SGMII Slave mode and disable signal detect */
4984 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4985 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4989 digctrl_kx1 &= 0xff4a;
4991 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4992 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4995 /* Turn off parallel detect */
4996 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4997 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4998 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4999 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5000 (digctrl_kx2 & ~(1<<2)));
5002 /* Re-enable parallel detect */
5003 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5004 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5005 (digctrl_kx2 | (1<<2)));
5007 /* Enable autodet */
5008 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5009 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5010 (digctrl_kx1 | 0x10));
5014 static void elink_warpcore_reset_lane(struct bxe_softc *sc,
5015 struct elink_phy *phy,
5019 /* Take lane out of reset after configuration is finished */
5020 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5021 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5026 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5027 MDIO_WC_REG_DIGITAL5_MISC6, val);
5028 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5029 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5032 /* Clear SFI/XFI link settings registers */
5033 static void elink_warpcore_clear_regs(struct elink_phy *phy,
5034 struct elink_params *params,
5037 struct bxe_softc *sc = params->sc;
5039 static struct elink_reg_set wc_regs[] = {
5040 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
5041 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
5042 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
5043 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
5044 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5046 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5048 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
5050 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
5051 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
5052 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
5053 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
5055 /* Set XFI clock comp as default. */
5056 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5057 MDIO_WC_REG_RX66_CONTROL, (3<<13));
5059 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
5060 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
5063 lane = elink_get_warpcore_lane(phy, params);
5064 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5065 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
5069 static elink_status_t elink_get_mod_abs_int_cfg(struct bxe_softc *sc,
5071 uint32_t shmem_base, uint8_t port,
5072 uint8_t *gpio_num, uint8_t *gpio_port)
5077 if (CHIP_IS_E3(sc)) {
5078 cfg_pin = (REG_RD(sc, shmem_base +
5079 offsetof(struct shmem_region,
5080 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5081 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
5082 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
5084 /* Should not happen. This function called upon interrupt
5085 * triggered by GPIO ( since EPIO can only generate interrupts
5087 * So if this function was called and none of the GPIOs was set,
5088 * it means the shit hit the fan.
5090 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
5091 (cfg_pin > PIN_CFG_GPIO3_P1)) {
5093 "No cfg pin %x for module detect indication\n",
5095 return ELINK_STATUS_ERROR;
5098 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
5099 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
5101 *gpio_num = MISC_REGISTERS_GPIO_3;
5105 return ELINK_STATUS_OK;
5108 static int elink_is_sfp_module_plugged(struct elink_phy *phy,
5109 struct elink_params *params)
5111 struct bxe_softc *sc = params->sc;
5112 uint8_t gpio_num, gpio_port;
5114 if (elink_get_mod_abs_int_cfg(sc, params->chip_id,
5115 params->shmem_base, params->port,
5116 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
5118 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
5120 /* Call the handling function in case module is detected */
5126 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
5127 struct elink_params *params)
5129 uint16_t gp2_status_reg0, lane;
5130 struct bxe_softc *sc = params->sc;
5132 lane = elink_get_warpcore_lane(phy, params);
5134 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
5137 return (gp2_status_reg0 >> (8+lane)) & 0x1;
5140 static void elink_warpcore_config_runtime(struct elink_phy *phy,
5141 struct elink_params *params,
5142 struct elink_vars *vars)
5144 struct bxe_softc *sc = params->sc;
5145 uint32_t serdes_net_if;
5146 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
5148 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
5150 if (!vars->turn_to_run_wc_rt)
5153 if (vars->rx_tx_asic_rst) {
5154 uint16_t lane = elink_get_warpcore_lane(phy, params);
5155 serdes_net_if = (REG_RD(sc, params->shmem_base +
5156 offsetof(struct shmem_region, dev_info.
5157 port_hw_config[params->port].default_cfg)) &
5158 PORT_HW_CFG_NET_SERDES_IF_MASK);
5160 switch (serdes_net_if) {
5161 case PORT_HW_CFG_NET_SERDES_IF_KR:
5162 /* Do we get link yet? */
5163 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
5165 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
5167 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
5169 if (lnkup_kr || lnkup) {
5170 vars->rx_tx_asic_rst = 0;
5172 /* Reset the lane to see if link comes up.*/
5173 elink_warpcore_reset_lane(sc, phy, 1);
5174 elink_warpcore_reset_lane(sc, phy, 0);
5176 /* Restart Autoneg */
5177 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
5178 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
5180 vars->rx_tx_asic_rst--;
5181 ELINK_DEBUG_P1(sc, "0x%x retry left\n",
5182 vars->rx_tx_asic_rst);
5190 } /*params->rx_tx_asic_rst*/
5193 static void elink_warpcore_config_sfi(struct elink_phy *phy,
5194 struct elink_params *params)
5196 uint16_t lane = elink_get_warpcore_lane(phy, params);
5197 struct bxe_softc *sc = params->sc;
5198 elink_warpcore_clear_regs(phy, params, lane);
5199 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
5200 ELINK_SPEED_10000) &&
5201 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
5202 ELINK_DEBUG_P0(sc, "Setting 10G SFI\n");
5203 elink_warpcore_set_10G_XFI(phy, params, 0);
5205 ELINK_DEBUG_P0(sc, "Setting 1G Fiber\n");
5206 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
5210 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
5211 struct elink_phy *phy,
5214 struct bxe_softc *sc = params->sc;
5216 uint8_t port = params->port;
5218 cfg_pin = REG_RD(sc, params->shmem_base +
5219 offsetof(struct shmem_region,
5220 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5221 PORT_HW_CFG_E3_TX_LASER_MASK;
5222 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
5223 ELINK_DEBUG_P1(sc, "Setting WC TX to %d\n", tx_en);
5225 /* For 20G, the expected pin to be used is 3 pins after the current */
5226 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
5227 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
5228 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
5231 static void elink_warpcore_config_init(struct elink_phy *phy,
5232 struct elink_params *params,
5233 struct elink_vars *vars)
5235 struct bxe_softc *sc = params->sc;
5236 uint32_t serdes_net_if;
5238 uint16_t lane = elink_get_warpcore_lane(phy, params);
5239 serdes_net_if = (REG_RD(sc, params->shmem_base +
5240 offsetof(struct shmem_region, dev_info.
5241 port_hw_config[params->port].default_cfg)) &
5242 PORT_HW_CFG_NET_SERDES_IF_MASK);
5243 ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, "
5244 "serdes_net_if = 0x%x\n",
5245 vars->line_speed, serdes_net_if);
5246 elink_set_aer_mmd(params, phy);
5247 elink_warpcore_reset_lane(sc, phy, 1);
5248 vars->phy_flags |= PHY_XGXS_FLAG;
5249 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
5250 (phy->req_line_speed &&
5251 ((phy->req_line_speed == ELINK_SPEED_100) ||
5252 (phy->req_line_speed == ELINK_SPEED_10)))) {
5253 vars->phy_flags |= PHY_SGMII_FLAG;
5254 ELINK_DEBUG_P0(sc, "Setting SGMII mode\n");
5255 elink_warpcore_clear_regs(phy, params, lane);
5256 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
5258 switch (serdes_net_if) {
5259 case PORT_HW_CFG_NET_SERDES_IF_KR:
5260 /* Enable KR Auto Neg */
5261 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
5262 elink_warpcore_enable_AN_KR(phy, params, vars);
5264 ELINK_DEBUG_P0(sc, "Setting KR 10G-Force\n");
5265 elink_warpcore_set_10G_KR(phy, params, vars);
5269 case PORT_HW_CFG_NET_SERDES_IF_XFI:
5270 elink_warpcore_clear_regs(phy, params, lane);
5271 if (vars->line_speed == ELINK_SPEED_10000) {
5272 ELINK_DEBUG_P0(sc, "Setting 10G XFI\n");
5273 elink_warpcore_set_10G_XFI(phy, params, 1);
5275 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5276 ELINK_DEBUG_P0(sc, "1G Fiber\n");
5279 ELINK_DEBUG_P0(sc, "10/100/1G SGMII\n");
5282 elink_warpcore_set_sgmii_speed(phy,
5290 case PORT_HW_CFG_NET_SERDES_IF_SFI:
5291 /* Issue Module detection if module is plugged, or
5292 * enabled transmitter to avoid current leakage in case
5293 * no module is connected
5295 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
5296 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5297 if (elink_is_sfp_module_plugged(phy, params))
5298 elink_sfp_module_detection(phy, params);
5300 elink_sfp_e3_set_transmitter(params,
5304 elink_warpcore_config_sfi(phy, params);
5307 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
5308 if (vars->line_speed != ELINK_SPEED_20000) {
5309 ELINK_DEBUG_P0(sc, "Speed not supported yet\n");
5312 ELINK_DEBUG_P0(sc, "Setting 20G DXGXS\n");
5313 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
5314 /* Issue Module detection */
5316 elink_sfp_module_detection(phy, params);
5318 case PORT_HW_CFG_NET_SERDES_IF_KR2:
5319 if (!params->loopback_mode) {
5320 elink_warpcore_enable_AN_KR(phy, params, vars);
5322 ELINK_DEBUG_P0(sc, "Setting KR 20G-Force\n");
5323 elink_warpcore_set_20G_force_KR2(phy, params);
5328 "Unsupported Serdes Net Interface 0x%x\n",
5334 /* Take lane out of reset after configuration is finished */
5335 elink_warpcore_reset_lane(sc, phy, 0);
5336 ELINK_DEBUG_P0(sc, "Exit config init\n");
5339 static void elink_warpcore_link_reset(struct elink_phy *phy,
5340 struct elink_params *params)
5342 struct bxe_softc *sc = params->sc;
5343 uint16_t val16, lane;
5344 elink_sfp_e3_set_transmitter(params, phy, 0);
5345 elink_set_mdio_emac_per_phy(sc, params);
5346 elink_set_aer_mmd(params, phy);
5347 /* Global register */
5348 elink_warpcore_reset_lane(sc, phy, 1);
5350 /* Clear loopback settings (if any) */
5352 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5353 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
5355 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5356 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
5358 /* Update those 1-copy registers */
5359 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5360 MDIO_AER_BLOCK_AER_REG, 0);
5361 /* Enable 1G MDIO (1-copy) */
5362 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5363 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5366 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5367 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
5368 lane = elink_get_warpcore_lane(phy, params);
5369 /* Disable CL36 PCS Tx */
5370 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5371 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
5372 val16 |= (0x11 << lane);
5373 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5374 val16 |= (0x22 << lane);
5375 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5376 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
5378 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5379 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
5380 val16 &= ~(0x0303 << (lane << 1));
5381 val16 |= (0x0101 << (lane << 1));
5382 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
5383 val16 &= ~(0x0c0c << (lane << 1));
5384 val16 |= (0x0404 << (lane << 1));
5387 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5388 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
5390 elink_set_aer_mmd(params, phy);
5394 static void elink_set_warpcore_loopback(struct elink_phy *phy,
5395 struct elink_params *params)
5397 struct bxe_softc *sc = params->sc;
5400 ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d\n",
5401 params->loopback_mode, phy->req_line_speed);
5403 if (phy->req_line_speed < ELINK_SPEED_10000 ||
5404 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5405 /* 10/100/1000/20G-KR2 */
5407 /* Update those 1-copy registers */
5408 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5409 MDIO_AER_BLOCK_AER_REG, 0);
5410 /* Enable 1G MDIO (1-copy) */
5411 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5412 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5414 /* Set 1G loopback based on lane (1-copy) */
5415 lane = elink_get_warpcore_lane(phy, params);
5416 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5417 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
5419 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5421 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5422 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
5425 /* Switch back to 4-copy registers */
5426 elink_set_aer_mmd(params, phy);
5428 /* 10G / 20G-DXGXS */
5429 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5430 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
5432 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5433 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
5439 static void elink_sync_link(struct elink_params *params,
5440 struct elink_vars *vars)
5442 struct bxe_softc *sc = params->sc;
5443 uint8_t link_10g_plus;
5444 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5445 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
5446 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
5447 if (vars->link_up) {
5448 ELINK_DEBUG_P0(sc, "phy link up\n");
5450 vars->phy_link_up = 1;
5451 vars->duplex = DUPLEX_FULL;
5452 switch (vars->link_status &
5453 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
5454 case ELINK_LINK_10THD:
5455 vars->duplex = DUPLEX_HALF;
5457 case ELINK_LINK_10TFD:
5458 vars->line_speed = ELINK_SPEED_10;
5461 case ELINK_LINK_100TXHD:
5462 vars->duplex = DUPLEX_HALF;
5464 case ELINK_LINK_100T4:
5465 case ELINK_LINK_100TXFD:
5466 vars->line_speed = ELINK_SPEED_100;
5469 case ELINK_LINK_1000THD:
5470 vars->duplex = DUPLEX_HALF;
5472 case ELINK_LINK_1000TFD:
5473 vars->line_speed = ELINK_SPEED_1000;
5476 case ELINK_LINK_2500THD:
5477 vars->duplex = DUPLEX_HALF;
5479 case ELINK_LINK_2500TFD:
5480 vars->line_speed = ELINK_SPEED_2500;
5483 case ELINK_LINK_10GTFD:
5484 vars->line_speed = ELINK_SPEED_10000;
5486 case ELINK_LINK_20GTFD:
5487 vars->line_speed = ELINK_SPEED_20000;
5492 vars->flow_ctrl = 0;
5493 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
5494 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
5496 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
5497 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
5499 if (!vars->flow_ctrl)
5500 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5502 if (vars->line_speed &&
5503 ((vars->line_speed == ELINK_SPEED_10) ||
5504 (vars->line_speed == ELINK_SPEED_100))) {
5505 vars->phy_flags |= PHY_SGMII_FLAG;
5507 vars->phy_flags &= ~PHY_SGMII_FLAG;
5509 if (vars->line_speed &&
5510 USES_WARPCORE(sc) &&
5511 (vars->line_speed == ELINK_SPEED_1000))
5512 vars->phy_flags |= PHY_SGMII_FLAG;
5513 /* Anything 10 and over uses the bmac */
5514 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
5516 if (link_10g_plus) {
5517 if (USES_WARPCORE(sc))
5518 vars->mac_type = ELINK_MAC_TYPE_XMAC;
5520 vars->mac_type = ELINK_MAC_TYPE_BMAC;
5522 if (USES_WARPCORE(sc))
5523 vars->mac_type = ELINK_MAC_TYPE_UMAC;
5525 vars->mac_type = ELINK_MAC_TYPE_EMAC;
5527 } else { /* Link down */
5528 ELINK_DEBUG_P0(sc, "phy link down\n");
5530 vars->phy_link_up = 0;
5532 vars->line_speed = 0;
5533 vars->duplex = DUPLEX_FULL;
5534 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5536 /* Indicate no mac active */
5537 vars->mac_type = ELINK_MAC_TYPE_NONE;
5538 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5539 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
5540 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
5541 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
5545 void elink_link_status_update(struct elink_params *params,
5546 struct elink_vars *vars)
5548 struct bxe_softc *sc = params->sc;
5549 uint8_t port = params->port;
5550 uint32_t sync_offset, media_types;
5551 /* Update PHY configuration */
5552 set_phy_vars(params, vars);
5554 vars->link_status = REG_RD(sc, params->shmem_base +
5555 offsetof(struct shmem_region,
5556 port_mb[port].link_status));
5558 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
5559 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
5560 params->loopback_mode != ELINK_LOOPBACK_EXT)
5561 vars->link_status |= LINK_STATUS_LINK_UP;
5563 if (elink_eee_has_cap(params))
5564 vars->eee_status = REG_RD(sc, params->shmem2_base +
5565 offsetof(struct shmem2_region,
5566 eee_status[params->port]));
5568 vars->phy_flags = PHY_XGXS_FLAG;
5569 elink_sync_link(params, vars);
5570 /* Sync media type */
5571 sync_offset = params->shmem_base +
5572 offsetof(struct shmem_region,
5573 dev_info.port_hw_config[port].media_type);
5574 media_types = REG_RD(sc, sync_offset);
5576 params->phy[ELINK_INT_PHY].media_type =
5577 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
5578 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
5579 params->phy[ELINK_EXT_PHY1].media_type =
5580 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
5581 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
5582 params->phy[ELINK_EXT_PHY2].media_type =
5583 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
5584 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
5585 ELINK_DEBUG_P1(sc, "media_types = 0x%x\n", media_types);
5587 /* Sync AEU offset */
5588 sync_offset = params->shmem_base +
5589 offsetof(struct shmem_region,
5590 dev_info.port_hw_config[port].aeu_int_mask);
5592 vars->aeu_int_mask = REG_RD(sc, sync_offset);
5594 /* Sync PFC status */
5595 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
5596 params->feature_config_flags |=
5597 ELINK_FEATURE_CONFIG_PFC_ENABLED;
5599 params->feature_config_flags &=
5600 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
5602 if (SHMEM2_HAS(sc, link_attr_sync))
5603 vars->link_attr_sync = SHMEM2_RD(sc,
5604 link_attr_sync[params->port]);
5606 ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
5607 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
5608 ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x\n",
5609 vars->line_speed, vars->duplex, vars->flow_ctrl);
5612 static void elink_set_master_ln(struct elink_params *params,
5613 struct elink_phy *phy)
5615 struct bxe_softc *sc = params->sc;
5616 uint16_t new_master_ln, ser_lane;
5617 ser_lane = ((params->lane_config &
5618 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5619 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5621 /* Set the master_ln for AN */
5622 CL22_RD_OVER_CL45(sc, phy,
5623 MDIO_REG_BANK_XGXS_BLOCK2,
5624 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5627 CL22_WR_OVER_CL45(sc, phy,
5628 MDIO_REG_BANK_XGXS_BLOCK2 ,
5629 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5630 (new_master_ln | ser_lane));
5633 static elink_status_t elink_reset_unicore(struct elink_params *params,
5634 struct elink_phy *phy,
5637 struct bxe_softc *sc = params->sc;
5638 uint16_t mii_control;
5640 CL22_RD_OVER_CL45(sc, phy,
5641 MDIO_REG_BANK_COMBO_IEEE0,
5642 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
5644 /* Reset the unicore */
5645 CL22_WR_OVER_CL45(sc, phy,
5646 MDIO_REG_BANK_COMBO_IEEE0,
5647 MDIO_COMBO_IEEE0_MII_CONTROL,
5649 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
5651 elink_set_serdes_access(sc, params->port);
5653 /* Wait for the reset to self clear */
5654 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
5657 /* The reset erased the previous bank value */
5658 CL22_RD_OVER_CL45(sc, phy,
5659 MDIO_REG_BANK_COMBO_IEEE0,
5660 MDIO_COMBO_IEEE0_MII_CONTROL,
5663 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
5665 return ELINK_STATUS_OK;
5669 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5672 ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!\n");
5673 return ELINK_STATUS_ERROR;
5677 static void elink_set_swap_lanes(struct elink_params *params,
5678 struct elink_phy *phy)
5680 struct bxe_softc *sc = params->sc;
5681 /* Each two bits represents a lane number:
5682 * No swap is 0123 => 0x1b no need to enable the swap
5684 uint16_t rx_lane_swap, tx_lane_swap;
5686 rx_lane_swap = ((params->lane_config &
5687 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
5688 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
5689 tx_lane_swap = ((params->lane_config &
5690 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
5691 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
5693 if (rx_lane_swap != 0x1b) {
5694 CL22_WR_OVER_CL45(sc, phy,
5695 MDIO_REG_BANK_XGXS_BLOCK2,
5696 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
5698 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
5699 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
5701 CL22_WR_OVER_CL45(sc, phy,
5702 MDIO_REG_BANK_XGXS_BLOCK2,
5703 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
5706 if (tx_lane_swap != 0x1b) {
5707 CL22_WR_OVER_CL45(sc, phy,
5708 MDIO_REG_BANK_XGXS_BLOCK2,
5709 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
5711 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
5713 CL22_WR_OVER_CL45(sc, phy,
5714 MDIO_REG_BANK_XGXS_BLOCK2,
5715 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
5719 static void elink_set_parallel_detection(struct elink_phy *phy,
5720 struct elink_params *params)
5722 struct bxe_softc *sc = params->sc;
5724 CL22_RD_OVER_CL45(sc, phy,
5725 MDIO_REG_BANK_SERDES_DIGITAL,
5726 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5728 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5729 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5731 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5732 ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
5733 phy->speed_cap_mask, control2);
5734 CL22_WR_OVER_CL45(sc, phy,
5735 MDIO_REG_BANK_SERDES_DIGITAL,
5736 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5739 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5740 (phy->speed_cap_mask &
5741 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5742 ELINK_DEBUG_P0(sc, "XGXS\n");
5744 CL22_WR_OVER_CL45(sc, phy,
5745 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5746 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5747 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5749 CL22_RD_OVER_CL45(sc, phy,
5750 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5751 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5756 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5758 CL22_WR_OVER_CL45(sc, phy,
5759 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5760 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5763 /* Disable parallel detection of HiG */
5764 CL22_WR_OVER_CL45(sc, phy,
5765 MDIO_REG_BANK_XGXS_BLOCK2,
5766 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5767 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5768 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5772 static void elink_set_autoneg(struct elink_phy *phy,
5773 struct elink_params *params,
5774 struct elink_vars *vars,
5775 uint8_t enable_cl73)
5777 struct bxe_softc *sc = params->sc;
5781 CL22_RD_OVER_CL45(sc, phy,
5782 MDIO_REG_BANK_COMBO_IEEE0,
5783 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5785 /* CL37 Autoneg Enabled */
5786 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5787 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5788 else /* CL37 Autoneg Disabled */
5789 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5790 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5792 CL22_WR_OVER_CL45(sc, phy,
5793 MDIO_REG_BANK_COMBO_IEEE0,
5794 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5796 /* Enable/Disable Autodetection */
5798 CL22_RD_OVER_CL45(sc, phy,
5799 MDIO_REG_BANK_SERDES_DIGITAL,
5800 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5801 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5802 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5803 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5804 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5805 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5807 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5809 CL22_WR_OVER_CL45(sc, phy,
5810 MDIO_REG_BANK_SERDES_DIGITAL,
5811 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5813 /* Enable TetonII and BAM autoneg */
5814 CL22_RD_OVER_CL45(sc, phy,
5815 MDIO_REG_BANK_BAM_NEXT_PAGE,
5816 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5818 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
5819 /* Enable BAM aneg Mode and TetonII aneg Mode */
5820 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5821 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5823 /* TetonII and BAM Autoneg Disabled */
5824 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5825 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5827 CL22_WR_OVER_CL45(sc, phy,
5828 MDIO_REG_BANK_BAM_NEXT_PAGE,
5829 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5833 /* Enable Cl73 FSM status bits */
5834 CL22_WR_OVER_CL45(sc, phy,
5835 MDIO_REG_BANK_CL73_USERB0,
5836 MDIO_CL73_USERB0_CL73_UCTRL,
5839 /* Enable BAM Station Manager*/
5840 CL22_WR_OVER_CL45(sc, phy,
5841 MDIO_REG_BANK_CL73_USERB0,
5842 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5843 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5844 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5845 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5847 /* Advertise CL73 link speeds */
5848 CL22_RD_OVER_CL45(sc, phy,
5849 MDIO_REG_BANK_CL73_IEEEB1,
5850 MDIO_CL73_IEEEB1_AN_ADV2,
5852 if (phy->speed_cap_mask &
5853 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5854 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5855 if (phy->speed_cap_mask &
5856 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5857 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5859 CL22_WR_OVER_CL45(sc, phy,
5860 MDIO_REG_BANK_CL73_IEEEB1,
5861 MDIO_CL73_IEEEB1_AN_ADV2,
5864 /* CL73 Autoneg Enabled */
5865 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5867 } else /* CL73 Autoneg Disabled */
5870 CL22_WR_OVER_CL45(sc, phy,
5871 MDIO_REG_BANK_CL73_IEEEB0,
5872 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5875 /* Program SerDes, forced speed */
5876 static void elink_program_serdes(struct elink_phy *phy,
5877 struct elink_params *params,
5878 struct elink_vars *vars)
5880 struct bxe_softc *sc = params->sc;
5883 /* Program duplex, disable autoneg and sgmii*/
5884 CL22_RD_OVER_CL45(sc, phy,
5885 MDIO_REG_BANK_COMBO_IEEE0,
5886 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5887 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5888 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5889 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5890 if (phy->req_duplex == DUPLEX_FULL)
5891 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5892 CL22_WR_OVER_CL45(sc, phy,
5893 MDIO_REG_BANK_COMBO_IEEE0,
5894 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5897 * - needed only if the speed is greater than 1G (2.5G or 10G)
5899 CL22_RD_OVER_CL45(sc, phy,
5900 MDIO_REG_BANK_SERDES_DIGITAL,
5901 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5902 /* Clearing the speed value before setting the right speed */
5903 ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5905 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5906 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5908 if (!((vars->line_speed == ELINK_SPEED_1000) ||
5909 (vars->line_speed == ELINK_SPEED_100) ||
5910 (vars->line_speed == ELINK_SPEED_10))) {
5912 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5913 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5914 if (vars->line_speed == ELINK_SPEED_10000)
5916 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5919 CL22_WR_OVER_CL45(sc, phy,
5920 MDIO_REG_BANK_SERDES_DIGITAL,
5921 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5925 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
5926 struct elink_params *params)
5928 struct bxe_softc *sc = params->sc;
5931 /* Set extended capabilities */
5932 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5933 val |= MDIO_OVER_1G_UP1_2_5G;
5934 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5935 val |= MDIO_OVER_1G_UP1_10G;
5936 CL22_WR_OVER_CL45(sc, phy,
5937 MDIO_REG_BANK_OVER_1G,
5938 MDIO_OVER_1G_UP1, val);
5940 CL22_WR_OVER_CL45(sc, phy,
5941 MDIO_REG_BANK_OVER_1G,
5942 MDIO_OVER_1G_UP3, 0x400);
5945 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
5946 struct elink_params *params,
5949 struct bxe_softc *sc = params->sc;
5951 /* For AN, we are always publishing full duplex */
5953 CL22_WR_OVER_CL45(sc, phy,
5954 MDIO_REG_BANK_COMBO_IEEE0,
5955 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5956 CL22_RD_OVER_CL45(sc, phy,
5957 MDIO_REG_BANK_CL73_IEEEB1,
5958 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5959 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5960 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5961 CL22_WR_OVER_CL45(sc, phy,
5962 MDIO_REG_BANK_CL73_IEEEB1,
5963 MDIO_CL73_IEEEB1_AN_ADV1, val);
5966 static void elink_restart_autoneg(struct elink_phy *phy,
5967 struct elink_params *params,
5968 uint8_t enable_cl73)
5970 struct bxe_softc *sc = params->sc;
5971 uint16_t mii_control;
5973 ELINK_DEBUG_P0(sc, "elink_restart_autoneg\n");
5974 /* Enable and restart BAM/CL37 aneg */
5977 CL22_RD_OVER_CL45(sc, phy,
5978 MDIO_REG_BANK_CL73_IEEEB0,
5979 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5982 CL22_WR_OVER_CL45(sc, phy,
5983 MDIO_REG_BANK_CL73_IEEEB0,
5984 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5986 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5987 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5990 CL22_RD_OVER_CL45(sc, phy,
5991 MDIO_REG_BANK_COMBO_IEEE0,
5992 MDIO_COMBO_IEEE0_MII_CONTROL,
5995 "elink_restart_autoneg mii_control before = 0x%x\n",
5997 CL22_WR_OVER_CL45(sc, phy,
5998 MDIO_REG_BANK_COMBO_IEEE0,
5999 MDIO_COMBO_IEEE0_MII_CONTROL,
6001 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6002 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
6006 static void elink_initialize_sgmii_process(struct elink_phy *phy,
6007 struct elink_params *params,
6008 struct elink_vars *vars)
6010 struct bxe_softc *sc = params->sc;
6013 /* In SGMII mode, the unicore is always slave */
6015 CL22_RD_OVER_CL45(sc, phy,
6016 MDIO_REG_BANK_SERDES_DIGITAL,
6017 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6019 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
6020 /* Set sgmii mode (and not fiber) */
6021 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
6022 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
6023 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
6024 CL22_WR_OVER_CL45(sc, phy,
6025 MDIO_REG_BANK_SERDES_DIGITAL,
6026 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6029 /* If forced speed */
6030 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
6031 /* Set speed, disable autoneg */
6032 uint16_t mii_control;
6034 CL22_RD_OVER_CL45(sc, phy,
6035 MDIO_REG_BANK_COMBO_IEEE0,
6036 MDIO_COMBO_IEEE0_MII_CONTROL,
6038 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6039 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
6040 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
6042 switch (vars->line_speed) {
6043 case ELINK_SPEED_100:
6045 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
6047 case ELINK_SPEED_1000:
6049 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
6051 case ELINK_SPEED_10:
6052 /* There is nothing to set for 10M */
6055 /* Invalid speed for SGMII */
6056 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6061 /* Setting the full duplex */
6062 if (phy->req_duplex == DUPLEX_FULL)
6064 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
6065 CL22_WR_OVER_CL45(sc, phy,
6066 MDIO_REG_BANK_COMBO_IEEE0,
6067 MDIO_COMBO_IEEE0_MII_CONTROL,
6070 } else { /* AN mode */
6071 /* Enable and restart AN */
6072 elink_restart_autoneg(phy, params, 0);
6078 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
6079 struct elink_params *params)
6081 struct bxe_softc *sc = params->sc;
6082 uint16_t pd_10g, status2_1000x;
6083 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6084 return ELINK_STATUS_OK;
6085 CL22_RD_OVER_CL45(sc, phy,
6086 MDIO_REG_BANK_SERDES_DIGITAL,
6087 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6089 CL22_RD_OVER_CL45(sc, phy,
6090 MDIO_REG_BANK_SERDES_DIGITAL,
6091 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6093 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
6094 ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d\n",
6099 CL22_RD_OVER_CL45(sc, phy,
6100 MDIO_REG_BANK_10G_PARALLEL_DETECT,
6101 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
6104 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
6105 ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d\n",
6109 return ELINK_STATUS_OK;
6112 static void elink_update_adv_fc(struct elink_phy *phy,
6113 struct elink_params *params,
6114 struct elink_vars *vars,
6117 uint16_t ld_pause; /* local driver */
6118 uint16_t lp_pause; /* link partner */
6119 uint16_t pause_result;
6120 struct bxe_softc *sc = params->sc;
6122 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6123 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
6124 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6125 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
6127 CL22_RD_OVER_CL45(sc, phy,
6128 MDIO_REG_BANK_CL73_IEEEB1,
6129 MDIO_CL73_IEEEB1_AN_ADV1,
6131 CL22_RD_OVER_CL45(sc, phy,
6132 MDIO_REG_BANK_CL73_IEEEB1,
6133 MDIO_CL73_IEEEB1_AN_LP_ADV1,
6135 pause_result = (ld_pause &
6136 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
6137 pause_result |= (lp_pause &
6138 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
6139 ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x\n", pause_result);
6141 CL22_RD_OVER_CL45(sc, phy,
6142 MDIO_REG_BANK_COMBO_IEEE0,
6143 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
6145 CL22_RD_OVER_CL45(sc, phy,
6146 MDIO_REG_BANK_COMBO_IEEE0,
6147 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
6149 pause_result = (ld_pause &
6150 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
6151 pause_result |= (lp_pause &
6152 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
6153 ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x\n", pause_result);
6155 elink_pause_resolve(vars, pause_result);
6159 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
6160 struct elink_params *params,
6161 struct elink_vars *vars,
6164 struct bxe_softc *sc = params->sc;
6165 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6167 /* Resolve from gp_status in case of AN complete and not sgmii */
6168 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
6169 /* Update the advertised flow-controled of LD/LP in AN */
6170 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6171 elink_update_adv_fc(phy, params, vars, gp_status);
6172 /* But set the flow-control result as the requested one */
6173 vars->flow_ctrl = phy->req_flow_ctrl;
6174 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6175 vars->flow_ctrl = params->req_fc_auto_adv;
6176 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
6177 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
6178 if (elink_direct_parallel_detect_used(phy, params)) {
6179 vars->flow_ctrl = params->req_fc_auto_adv;
6182 elink_update_adv_fc(phy, params, vars, gp_status);
6184 ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x\n", vars->flow_ctrl);
6187 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
6188 struct elink_params *params)
6190 struct bxe_softc *sc = params->sc;
6191 uint16_t rx_status, ustat_val, cl37_fsm_received;
6192 ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37\n");
6193 /* Step 1: Make sure signal is detected */
6194 CL22_RD_OVER_CL45(sc, phy,
6198 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
6199 (MDIO_RX0_RX_STATUS_SIGDET)) {
6200 ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73."
6201 "rx_status(0x80b0) = 0x%x\n", rx_status);
6202 CL22_WR_OVER_CL45(sc, phy,
6203 MDIO_REG_BANK_CL73_IEEEB0,
6204 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6205 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
6208 /* Step 2: Check CL73 state machine */
6209 CL22_RD_OVER_CL45(sc, phy,
6210 MDIO_REG_BANK_CL73_USERB0,
6211 MDIO_CL73_USERB0_CL73_USTAT1,
6214 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6215 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
6216 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6217 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
6218 ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. "
6219 "ustat_val(0x8371) = 0x%x\n", ustat_val);
6222 /* Step 3: Check CL37 Message Pages received to indicate LP
6223 * supports only CL37
6225 CL22_RD_OVER_CL45(sc, phy,
6226 MDIO_REG_BANK_REMOTE_PHY,
6227 MDIO_REMOTE_PHY_MISC_RX_STATUS,
6228 &cl37_fsm_received);
6229 if ((cl37_fsm_received &
6230 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6231 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
6232 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6233 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
6234 ELINK_DEBUG_P1(sc, "No CL37 FSM were received. "
6235 "misc_rx_status(0x8330) = 0x%x\n",
6239 /* The combined cl37/cl73 fsm state information indicating that
6240 * we are connected to a device which does not support cl73, but
6241 * does support cl37 BAM. In this case we disable cl73 and
6242 * restart cl37 auto-neg
6246 CL22_WR_OVER_CL45(sc, phy,
6247 MDIO_REG_BANK_CL73_IEEEB0,
6248 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6250 /* Restart CL37 autoneg */
6251 elink_restart_autoneg(phy, params, 0);
6252 ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg\n");
6255 static void elink_xgxs_an_resolve(struct elink_phy *phy,
6256 struct elink_params *params,
6257 struct elink_vars *vars,
6260 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
6261 vars->link_status |=
6262 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6264 if (elink_direct_parallel_detect_used(phy, params))
6265 vars->link_status |=
6266 LINK_STATUS_PARALLEL_DETECTION_USED;
6268 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
6269 struct elink_params *params,
6270 struct elink_vars *vars,
6271 uint16_t is_link_up,
6272 uint16_t speed_mask,
6275 struct bxe_softc *sc = params->sc;
6276 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6277 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
6279 ELINK_DEBUG_P0(sc, "phy link up\n");
6281 vars->phy_link_up = 1;
6282 vars->link_status |= LINK_STATUS_LINK_UP;
6284 switch (speed_mask) {
6285 case ELINK_GP_STATUS_10M:
6286 vars->line_speed = ELINK_SPEED_10;
6287 if (is_duplex == DUPLEX_FULL)
6288 vars->link_status |= ELINK_LINK_10TFD;
6290 vars->link_status |= ELINK_LINK_10THD;
6293 case ELINK_GP_STATUS_100M:
6294 vars->line_speed = ELINK_SPEED_100;
6295 if (is_duplex == DUPLEX_FULL)
6296 vars->link_status |= ELINK_LINK_100TXFD;
6298 vars->link_status |= ELINK_LINK_100TXHD;
6301 case ELINK_GP_STATUS_1G:
6302 case ELINK_GP_STATUS_1G_KX:
6303 vars->line_speed = ELINK_SPEED_1000;
6304 if (is_duplex == DUPLEX_FULL)
6305 vars->link_status |= ELINK_LINK_1000TFD;
6307 vars->link_status |= ELINK_LINK_1000THD;
6310 case ELINK_GP_STATUS_2_5G:
6311 vars->line_speed = ELINK_SPEED_2500;
6312 if (is_duplex == DUPLEX_FULL)
6313 vars->link_status |= ELINK_LINK_2500TFD;
6315 vars->link_status |= ELINK_LINK_2500THD;
6318 case ELINK_GP_STATUS_5G:
6319 case ELINK_GP_STATUS_6G:
6321 "link speed unsupported gp_status 0x%x\n",
6323 return ELINK_STATUS_ERROR;
6325 case ELINK_GP_STATUS_10G_KX4:
6326 case ELINK_GP_STATUS_10G_HIG:
6327 case ELINK_GP_STATUS_10G_CX4:
6328 case ELINK_GP_STATUS_10G_KR:
6329 case ELINK_GP_STATUS_10G_SFI:
6330 case ELINK_GP_STATUS_10G_XFI:
6331 vars->line_speed = ELINK_SPEED_10000;
6332 vars->link_status |= ELINK_LINK_10GTFD;
6334 case ELINK_GP_STATUS_20G_DXGXS:
6335 case ELINK_GP_STATUS_20G_KR2:
6336 vars->line_speed = ELINK_SPEED_20000;
6337 vars->link_status |= ELINK_LINK_20GTFD;
6341 "link speed unsupported gp_status 0x%x\n",
6343 return ELINK_STATUS_ERROR;
6345 } else { /* link_down */
6346 ELINK_DEBUG_P0(sc, "phy link down\n");
6348 vars->phy_link_up = 0;
6350 vars->duplex = DUPLEX_FULL;
6351 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6352 vars->mac_type = ELINK_MAC_TYPE_NONE;
6354 ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d\n",
6355 vars->phy_link_up, vars->line_speed);
6356 return ELINK_STATUS_OK;
6359 static elink_status_t elink_link_settings_status(struct elink_phy *phy,
6360 struct elink_params *params,
6361 struct elink_vars *vars)
6363 struct bxe_softc *sc = params->sc;
6365 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
6366 elink_status_t rc = ELINK_STATUS_OK;
6368 /* Read gp_status */
6369 CL22_RD_OVER_CL45(sc, phy,
6370 MDIO_REG_BANK_GP_STATUS,
6371 MDIO_GP_STATUS_TOP_AN_STATUS1,
6373 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
6374 duplex = DUPLEX_FULL;
6375 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
6377 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
6378 ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
6379 gp_status, link_up, speed_mask);
6380 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
6382 if (rc == ELINK_STATUS_ERROR)
6385 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
6386 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
6387 vars->duplex = duplex;
6388 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
6389 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6390 elink_xgxs_an_resolve(phy, params, vars,
6393 } else { /* Link_down */
6394 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
6395 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6396 /* Check signal is detected */
6397 elink_check_fallback_to_cl37(phy, params);
6401 /* Read LP advertised speeds*/
6402 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6403 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
6406 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
6407 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
6409 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6410 vars->link_status |=
6411 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6412 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6413 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6414 vars->link_status |=
6415 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6417 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
6418 MDIO_OVER_1G_LP_UP1, &val);
6420 if (val & MDIO_OVER_1G_UP1_2_5G)
6421 vars->link_status |=
6422 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6423 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6424 vars->link_status |=
6425 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6428 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6429 vars->duplex, vars->flow_ctrl, vars->link_status);
6433 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
6434 struct elink_params *params,
6435 struct elink_vars *vars)
6437 struct bxe_softc *sc = params->sc;
6439 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
6440 elink_status_t rc = ELINK_STATUS_OK;
6441 lane = elink_get_warpcore_lane(phy, params);
6442 /* Read gp_status */
6443 if ((params->loopback_mode) &&
6444 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
6445 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6446 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6447 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6448 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6450 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
6451 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
6452 uint16_t temp_link_up;
6453 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6455 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6457 ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x\n",
6458 temp_link_up, link_up);
6461 elink_ext_phy_resolve_fc(phy, params, vars);
6463 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6464 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6466 ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x\n", gp_status1);
6467 /* Check for either KR, 1G, or AN up. */
6468 link_up = ((gp_status1 >> 8) |
6469 (gp_status1 >> 12) |
6472 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
6474 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6475 MDIO_AN_REG_STATUS, &an_link);
6476 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6477 MDIO_AN_REG_STATUS, &an_link);
6478 link_up |= (an_link & (1<<2));
6480 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
6481 uint16_t pd, gp_status4;
6482 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
6483 /* Check Autoneg complete */
6484 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6485 MDIO_WC_REG_GP2_STATUS_GP_2_4,
6487 if (gp_status4 & ((1<<12)<<lane))
6488 vars->link_status |=
6489 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6491 /* Check parallel detect used */
6492 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6493 MDIO_WC_REG_PAR_DET_10G_STATUS,
6496 vars->link_status |=
6497 LINK_STATUS_PARALLEL_DETECTION_USED;
6499 elink_ext_phy_resolve_fc(phy, params, vars);
6500 vars->duplex = duplex;
6504 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
6505 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6508 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6509 MDIO_AN_REG_LP_AUTO_NEG2, &val);
6511 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6512 vars->link_status |=
6513 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6514 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6515 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6516 vars->link_status |=
6517 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6519 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6520 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
6522 if (val & MDIO_OVER_1G_UP1_2_5G)
6523 vars->link_status |=
6524 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6525 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6526 vars->link_status |=
6527 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6533 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6534 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
6536 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6537 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
6539 ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed);
6541 if ((lane & 1) == 0)
6544 link_up = !!link_up;
6546 /* Reset the TX FIFO to fix SGMII issue */
6547 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
6550 /* In case of KR link down, start up the recovering procedure */
6551 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
6552 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
6553 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
6555 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6556 vars->duplex, vars->flow_ctrl, vars->link_status);
6559 static void elink_set_gmii_tx_driver(struct elink_params *params)
6561 struct bxe_softc *sc = params->sc;
6562 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6568 CL22_RD_OVER_CL45(sc, phy,
6569 MDIO_REG_BANK_OVER_1G,
6570 MDIO_OVER_1G_LP_UP2, &lp_up2);
6572 /* Bits [10:7] at lp_up2, positioned at [15:12] */
6573 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
6574 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
6575 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
6580 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
6581 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
6582 CL22_RD_OVER_CL45(sc, phy,
6584 MDIO_TX0_TX_DRIVER, &tx_driver);
6586 /* Replace tx_driver bits [15:12] */
6588 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
6589 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
6590 tx_driver |= lp_up2;
6591 CL22_WR_OVER_CL45(sc, phy,
6593 MDIO_TX0_TX_DRIVER, tx_driver);
6598 static elink_status_t elink_emac_program(struct elink_params *params,
6599 struct elink_vars *vars)
6601 struct bxe_softc *sc = params->sc;
6602 uint8_t port = params->port;
6605 ELINK_DEBUG_P0(sc, "setting link speed & duplex\n");
6606 elink_bits_dis(sc, GRCBASE_EMAC0 + port*0x400 +
6608 (EMAC_MODE_25G_MODE |
6609 EMAC_MODE_PORT_MII_10M |
6610 EMAC_MODE_HALF_DUPLEX));
6611 switch (vars->line_speed) {
6612 case ELINK_SPEED_10:
6613 mode |= EMAC_MODE_PORT_MII_10M;
6616 case ELINK_SPEED_100:
6617 mode |= EMAC_MODE_PORT_MII;
6620 case ELINK_SPEED_1000:
6621 mode |= EMAC_MODE_PORT_GMII;
6624 case ELINK_SPEED_2500:
6625 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
6629 /* 10G not valid for EMAC */
6630 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6632 return ELINK_STATUS_ERROR;
6635 if (vars->duplex == DUPLEX_HALF)
6636 mode |= EMAC_MODE_HALF_DUPLEX;
6638 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
6641 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
6642 return ELINK_STATUS_OK;
6645 static void elink_set_preemphasis(struct elink_phy *phy,
6646 struct elink_params *params)
6649 uint16_t bank, i = 0;
6650 struct bxe_softc *sc = params->sc;
6652 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
6653 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
6654 CL22_WR_OVER_CL45(sc, phy,
6656 MDIO_RX0_RX_EQ_BOOST,
6657 phy->rx_preemphasis[i]);
6660 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
6661 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
6662 CL22_WR_OVER_CL45(sc, phy,
6665 phy->tx_preemphasis[i]);
6669 static void elink_xgxs_config_init(struct elink_phy *phy,
6670 struct elink_params *params,
6671 struct elink_vars *vars)
6673 struct bxe_softc *sc = params->sc;
6674 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6675 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6676 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
6677 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6678 (params->feature_config_flags &
6679 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
6680 elink_set_preemphasis(phy, params);
6682 /* Forced speed requested? */
6683 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
6684 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6685 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
6686 ELINK_DEBUG_P0(sc, "not SGMII, no AN\n");
6688 /* Disable autoneg */
6689 elink_set_autoneg(phy, params, vars, 0);
6691 /* Program speed and duplex */
6692 elink_program_serdes(phy, params, vars);
6694 } else { /* AN_mode */
6695 ELINK_DEBUG_P0(sc, "not SGMII, AN\n");
6698 elink_set_brcm_cl37_advertisement(phy, params);
6700 /* Program duplex & pause advertisement (for aneg) */
6701 elink_set_ieee_aneg_advertisement(phy, params,
6704 /* Enable autoneg */
6705 elink_set_autoneg(phy, params, vars, enable_cl73);
6707 /* Enable and restart AN */
6708 elink_restart_autoneg(phy, params, enable_cl73);
6711 } else { /* SGMII mode */
6712 ELINK_DEBUG_P0(sc, "SGMII\n");
6714 elink_initialize_sgmii_process(phy, params, vars);
6718 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
6719 struct elink_params *params,
6720 struct elink_vars *vars)
6723 vars->phy_flags |= PHY_XGXS_FLAG;
6724 if ((phy->req_line_speed &&
6725 ((phy->req_line_speed == ELINK_SPEED_100) ||
6726 (phy->req_line_speed == ELINK_SPEED_10))) ||
6727 (!phy->req_line_speed &&
6728 (phy->speed_cap_mask >=
6729 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
6730 (phy->speed_cap_mask <
6731 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6732 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
6733 vars->phy_flags |= PHY_SGMII_FLAG;
6735 vars->phy_flags &= ~PHY_SGMII_FLAG;
6737 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6738 elink_set_aer_mmd(params, phy);
6739 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6740 elink_set_master_ln(params, phy);
6742 rc = elink_reset_unicore(params, phy, 0);
6743 /* Reset the SerDes and wait for reset bit return low */
6744 if (rc != ELINK_STATUS_OK)
6747 elink_set_aer_mmd(params, phy);
6748 /* Setting the masterLn_def again after the reset */
6749 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6750 elink_set_master_ln(params, phy);
6751 elink_set_swap_lanes(params, phy);
6757 static uint16_t elink_wait_reset_complete(struct bxe_softc *sc,
6758 struct elink_phy *phy,
6759 struct elink_params *params)
6762 /* Wait for soft reset to get cleared up to 1 sec */
6763 for (cnt = 0; cnt < 1000; cnt++) {
6764 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6765 elink_cl22_read(sc, phy,
6766 MDIO_PMA_REG_CTRL, &ctrl);
6768 elink_cl45_read(sc, phy,
6770 MDIO_PMA_REG_CTRL, &ctrl);
6771 if (!(ctrl & (1<<15)))
6777 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
6780 ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6784 static void elink_link_int_enable(struct elink_params *params)
6786 uint8_t port = params->port;
6788 struct bxe_softc *sc = params->sc;
6790 /* Setting the status to report on link up for either XGXS or SerDes */
6791 if (CHIP_IS_E3(sc)) {
6792 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
6793 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
6794 mask |= ELINK_NIG_MASK_MI_INT;
6795 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6796 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
6797 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
6798 ELINK_DEBUG_P0(sc, "enabled XGXS interrupt\n");
6799 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6800 params->phy[ELINK_INT_PHY].type !=
6801 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6802 mask |= ELINK_NIG_MASK_MI_INT;
6803 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6806 } else { /* SerDes */
6807 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
6808 ELINK_DEBUG_P0(sc, "enabled SerDes interrupt\n");
6809 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6810 params->phy[ELINK_INT_PHY].type !=
6811 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6812 mask |= ELINK_NIG_MASK_MI_INT;
6813 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6817 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6820 ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6821 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
6822 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6823 ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6824 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6825 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6826 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6827 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
6828 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6829 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6832 static void elink_rearm_latch_signal(struct bxe_softc *sc, uint8_t port,
6835 uint32_t latch_status = 0;
6837 /* Disable the MI INT ( external phy int ) by writing 1 to the
6838 * status register. Link down indication is high-active-signal,
6839 * so in this case we need to write the status to clear the XOR
6841 /* Read Latched signals */
6842 latch_status = REG_RD(sc,
6843 NIG_REG_LATCH_STATUS_0 + port*8);
6844 ELINK_DEBUG_P1(sc, "latch_status = 0x%x\n", latch_status);
6845 /* Handle only those with latched-signal=up.*/
6848 NIG_REG_STATUS_INTERRUPT_PORT0
6850 ELINK_NIG_STATUS_EMAC0_MI_INT);
6853 NIG_REG_STATUS_INTERRUPT_PORT0
6855 ELINK_NIG_STATUS_EMAC0_MI_INT);
6857 if (latch_status & 1) {
6859 /* For all latched-signal=up : Re-Arm Latch signals */
6860 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8,
6861 (latch_status & 0xfffe) | (latch_status & 1));
6863 /* For all latched-signal=up,Write original_signal to status */
6866 static void elink_link_int_ack(struct elink_params *params,
6867 struct elink_vars *vars, uint8_t is_10g_plus)
6869 struct bxe_softc *sc = params->sc;
6870 uint8_t port = params->port;
6872 /* First reset all status we assume only one line will be
6875 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6876 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6877 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6878 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
6879 if (vars->phy_link_up) {
6880 if (USES_WARPCORE(sc))
6881 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
6884 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
6885 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6886 /* Disable the link interrupt by writing 1 to
6887 * the relevant lane in the status register
6890 ((params->lane_config &
6891 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6892 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6893 mask = ((1 << ser_lane) <<
6894 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6896 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
6898 ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x\n",
6901 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6906 static elink_status_t elink_format_ver(uint32_t num, uint8_t *str, uint16_t *len)
6908 uint8_t *str_ptr = str;
6909 uint32_t mask = 0xf0000000;
6910 uint8_t shift = 8*4;
6912 uint8_t remove_leading_zeros = 1;
6914 /* Need more than 10chars for this format */
6917 return ELINK_STATUS_ERROR;
6922 digit = ((num & mask) >> shift);
6923 if (digit == 0 && remove_leading_zeros) {
6926 } else if (digit < 0xa)
6927 *str_ptr = digit + '0';
6929 *str_ptr = digit - 0xa + 'a';
6930 remove_leading_zeros = 0;
6938 remove_leading_zeros = 1;
6941 return ELINK_STATUS_OK;
6945 static elink_status_t elink_null_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
6949 return ELINK_STATUS_OK;
6952 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version,
6955 struct bxe_softc *sc;
6956 uint32_t spirom_ver = 0;
6957 elink_status_t status = ELINK_STATUS_OK;
6958 uint8_t *ver_p = version;
6959 uint16_t remain_len = len;
6960 if (version == NULL || params == NULL)
6961 return ELINK_STATUS_ERROR;
6964 /* Extract first external phy*/
6966 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
6968 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
6969 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
6972 ver_p += (len - remain_len);
6974 if ((params->num_phys == ELINK_MAX_PHYS) &&
6975 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
6976 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
6977 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
6981 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
6985 ver_p = version + (len - remain_len);
6992 static void elink_set_xgxs_loopback(struct elink_phy *phy,
6993 struct elink_params *params)
6995 uint8_t port = params->port;
6996 struct bxe_softc *sc = params->sc;
6998 if (phy->req_line_speed != ELINK_SPEED_1000) {
6999 uint32_t md_devad = 0;
7001 ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable\n");
7003 if (!CHIP_IS_E3(sc)) {
7004 /* Change the uni_phy_addr in the nig */
7005 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
7008 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7012 elink_cl45_write(sc, phy,
7014 (MDIO_REG_BANK_AER_BLOCK +
7015 (MDIO_AER_BLOCK_AER_REG & 0xf)),
7018 elink_cl45_write(sc, phy,
7020 (MDIO_REG_BANK_CL73_IEEEB0 +
7021 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
7024 /* Set aer mmd back */
7025 elink_set_aer_mmd(params, phy);
7027 if (!CHIP_IS_E3(sc)) {
7029 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7034 ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable\n");
7035 elink_cl45_read(sc, phy, 5,
7036 (MDIO_REG_BANK_COMBO_IEEE0 +
7037 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7039 elink_cl45_write(sc, phy, 5,
7040 (MDIO_REG_BANK_COMBO_IEEE0 +
7041 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7043 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
7047 elink_status_t elink_set_led(struct elink_params *params,
7048 struct elink_vars *vars, uint8_t mode, uint32_t speed)
7050 uint8_t port = params->port;
7051 uint16_t hw_led_mode = params->hw_led_mode;
7052 elink_status_t rc = ELINK_STATUS_OK;
7055 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7056 struct bxe_softc *sc = params->sc;
7057 ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d\n", port, mode);
7058 ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x\n",
7059 speed, hw_led_mode);
7061 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7062 if (params->phy[phy_idx].set_link_led) {
7063 params->phy[phy_idx].set_link_led(
7064 ¶ms->phy[phy_idx], params, mode);
7067 #ifdef ELINK_INCLUDE_EMUL
7068 if (params->feature_config_flags &
7069 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
7074 case ELINK_LED_MODE_FRONT_PANEL_OFF:
7075 case ELINK_LED_MODE_OFF:
7076 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0);
7077 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7078 SHARED_HW_CFG_LED_MAC1);
7080 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7081 if (params->phy[ELINK_EXT_PHY1].type ==
7082 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
7083 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
7084 EMAC_LED_100MB_OVERRIDE |
7085 EMAC_LED_10MB_OVERRIDE);
7087 tmp |= EMAC_LED_OVERRIDE;
7089 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
7092 case ELINK_LED_MODE_OPER:
7093 /* For all other phys, OPER mode is same as ON, so in case
7094 * link is down, do nothing
7098 case ELINK_LED_MODE_ON:
7099 if (((params->phy[ELINK_EXT_PHY1].type ==
7100 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
7101 (params->phy[ELINK_EXT_PHY1].type ==
7102 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
7103 CHIP_IS_E2(sc) && params->num_phys == 2) {
7104 /* This is a work-around for E2+8727 Configurations */
7105 if (mode == ELINK_LED_MODE_ON ||
7106 speed == ELINK_SPEED_10000){
7107 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7108 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7110 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7111 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7112 (tmp | EMAC_LED_OVERRIDE));
7113 /* Return here without enabling traffic
7114 * LED blink and setting rate in ON mode.
7115 * In oper mode, enabling LED blink
7116 * and setting rate is needed.
7118 if (mode == ELINK_LED_MODE_ON)
7121 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
7122 /* This is a work-around for HW issue found when link
7125 if ((!CHIP_IS_E3(sc)) ||
7127 mode == ELINK_LED_MODE_ON))
7128 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7130 if (CHIP_IS_E1x(sc) ||
7132 (mode == ELINK_LED_MODE_ON))
7133 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7135 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7137 } else if ((params->phy[ELINK_EXT_PHY1].type ==
7138 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
7139 (mode == ELINK_LED_MODE_ON)) {
7140 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7141 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7142 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp |
7143 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
7144 /* Break here; otherwise, it'll disable the
7145 * intended override.
7149 uint32_t nig_led_mode = ((params->hw_led_mode <<
7150 SHARED_HW_CFG_LED_MODE_SHIFT) ==
7151 SHARED_HW_CFG_LED_EXTPHY2) ?
7152 (SHARED_HW_CFG_LED_PHY1 >>
7153 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
7154 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7158 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
7159 /* Set blinking rate to ~15.9Hz */
7161 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7162 LED_BLINK_RATE_VAL_E3);
7164 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7165 LED_BLINK_RATE_VAL_E1X_E2);
7166 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
7168 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7169 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7170 (tmp & (~EMAC_LED_OVERRIDE)));
7172 if (CHIP_IS_E1(sc) &&
7173 ((speed == ELINK_SPEED_2500) ||
7174 (speed == ELINK_SPEED_1000) ||
7175 (speed == ELINK_SPEED_100) ||
7176 (speed == ELINK_SPEED_10))) {
7177 /* For speeds less than 10G LED scheme is different */
7178 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
7180 REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
7182 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
7188 rc = ELINK_STATUS_ERROR;
7189 ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d\n",
7197 /* This function comes to reflect the actual link state read DIRECTLY from the
7200 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
7203 struct bxe_softc *sc = params->sc;
7204 uint16_t gp_status = 0, phy_index = 0;
7205 uint8_t ext_phy_link_up = 0, serdes_phy_type;
7206 struct elink_vars temp_vars;
7207 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
7208 #ifdef ELINK_INCLUDE_FPGA
7209 if (CHIP_REV_IS_FPGA(sc))
7210 return ELINK_STATUS_OK;
7212 #ifdef ELINK_INCLUDE_EMUL
7213 if (CHIP_REV_IS_EMUL(sc))
7214 return ELINK_STATUS_OK;
7217 if (CHIP_IS_E3(sc)) {
7219 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]
7220 > ELINK_SPEED_10000) {
7221 /* Check 20G link */
7222 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7224 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7228 /* Check 10G link and below*/
7229 uint8_t lane = elink_get_warpcore_lane(int_phy, params);
7230 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7231 MDIO_WC_REG_GP2_STATUS_GP_2_1,
7233 gp_status = ((gp_status >> 8) & 0xf) |
7234 ((gp_status >> 12) & 0xf);
7235 link_up = gp_status & (1 << lane);
7238 return ELINK_STATUS_NO_LINK;
7240 CL22_RD_OVER_CL45(sc, int_phy,
7241 MDIO_REG_BANK_GP_STATUS,
7242 MDIO_GP_STATUS_TOP_AN_STATUS1,
7244 /* Link is up only if both local phy and external phy are up */
7245 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
7246 return ELINK_STATUS_NO_LINK;
7248 /* In XGXS loopback mode, do not check external PHY */
7249 if (params->loopback_mode == ELINK_LOOPBACK_XGXS)
7250 return ELINK_STATUS_OK;
7252 switch (params->num_phys) {
7254 /* No external PHY */
7255 return ELINK_STATUS_OK;
7257 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
7258 ¶ms->phy[ELINK_EXT_PHY1],
7259 params, &temp_vars);
7261 case 3: /* Dual Media */
7262 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7264 serdes_phy_type = ((params->phy[phy_index].media_type ==
7265 ELINK_ETH_PHY_SFPP_10G_FIBER) ||
7266 (params->phy[phy_index].media_type ==
7267 ELINK_ETH_PHY_SFP_1G_FIBER) ||
7268 (params->phy[phy_index].media_type ==
7269 ELINK_ETH_PHY_XFP_FIBER) ||
7270 (params->phy[phy_index].media_type ==
7271 ELINK_ETH_PHY_DA_TWINAX));
7273 if (is_serdes != serdes_phy_type)
7275 if (params->phy[phy_index].read_status) {
7277 params->phy[phy_index].read_status(
7278 ¶ms->phy[phy_index],
7279 params, &temp_vars);
7284 if (ext_phy_link_up)
7285 return ELINK_STATUS_OK;
7286 return ELINK_STATUS_NO_LINK;
7289 static elink_status_t elink_link_initialize(struct elink_params *params,
7290 struct elink_vars *vars)
7292 elink_status_t rc = ELINK_STATUS_OK;
7293 uint8_t phy_index, non_ext_phy;
7294 struct bxe_softc *sc = params->sc;
7295 /* In case of external phy existence, the line speed would be the
7296 * line speed linked up by the external phy. In case it is direct
7297 * only, then the line_speed during initialization will be
7298 * equal to the req_line_speed
7300 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7302 /* Initialize the internal phy in case this is a direct board
7303 * (no external phys), or this board has external phy which requires
7306 if (!USES_WARPCORE(sc))
7307 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
7308 /* init ext phy and enable link state int */
7309 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
7310 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
7313 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
7314 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
7315 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
7316 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
7319 elink_set_parallel_detection(phy, params);
7320 if (params->phy[ELINK_INT_PHY].config_init)
7321 params->phy[ELINK_INT_PHY].config_init(phy,
7326 /* Re-read this value in case it was changed inside config_init due to
7327 * limitations of optic module
7329 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7331 /* Init external phy*/
7333 if (params->phy[ELINK_INT_PHY].supported &
7334 ELINK_SUPPORTED_FIBRE)
7335 vars->link_status |= LINK_STATUS_SERDES_LINK;
7337 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7339 /* No need to initialize second phy in case of first
7340 * phy only selection. In case of second phy, we do
7341 * need to initialize the first phy, since they are
7344 if (params->phy[phy_index].supported &
7345 ELINK_SUPPORTED_FIBRE)
7346 vars->link_status |= LINK_STATUS_SERDES_LINK;
7348 if (phy_index == ELINK_EXT_PHY2 &&
7349 (elink_phy_selection(params) ==
7350 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
7352 "Not initializing second phy\n");
7355 params->phy[phy_index].config_init(
7356 ¶ms->phy[phy_index],
7360 /* Reset the interrupt indication after phy was initialized */
7361 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
7363 (ELINK_NIG_STATUS_XGXS0_LINK10G |
7364 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
7365 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
7366 ELINK_NIG_MASK_MI_INT));
7370 static void elink_int_link_reset(struct elink_phy *phy,
7371 struct elink_params *params)
7373 /* Reset the SerDes/XGXS */
7374 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
7375 (0x1ff << (params->port*16)));
7378 static void elink_common_ext_link_reset(struct elink_phy *phy,
7379 struct elink_params *params)
7381 struct bxe_softc *sc = params->sc;
7385 gpio_port = SC_PATH(sc);
7387 gpio_port = params->port;
7388 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7389 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7391 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7392 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7394 ELINK_DEBUG_P0(sc, "reset external PHY\n");
7397 static elink_status_t elink_update_link_down(struct elink_params *params,
7398 struct elink_vars *vars)
7400 struct bxe_softc *sc = params->sc;
7401 uint8_t port = params->port;
7403 ELINK_DEBUG_P1(sc, "Port %x: Link is down\n", port);
7404 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
7405 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
7406 /* Indicate no mac active */
7407 vars->mac_type = ELINK_MAC_TYPE_NONE;
7409 /* Update shared memory */
7410 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7411 vars->line_speed = 0;
7412 elink_update_mng(params, vars->link_status);
7414 /* Activate nig drain */
7415 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7418 if (!CHIP_IS_E3(sc))
7419 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7422 /* Reset BigMac/Xmac */
7423 if (CHIP_IS_E1x(sc) ||
7425 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
7427 if (CHIP_IS_E3(sc)) {
7428 /* Prevent LPI Generation by chip */
7429 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
7431 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
7433 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
7434 SHMEM_EEE_ACTIVE_BIT);
7436 elink_update_mng_eee(params, vars->eee_status);
7437 elink_set_xmac_rxtx(params, 0);
7438 elink_set_umac_rxtx(params, 0);
7441 return ELINK_STATUS_OK;
7444 static elink_status_t elink_update_link_up(struct elink_params *params,
7445 struct elink_vars *vars,
7448 struct bxe_softc *sc = params->sc;
7449 uint8_t phy_idx, port = params->port;
7450 elink_status_t rc = ELINK_STATUS_OK;
7452 vars->link_status |= (LINK_STATUS_LINK_UP |
7453 LINK_STATUS_PHYSICAL_LINK_FLAG);
7454 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
7456 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
7457 vars->link_status |=
7458 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
7460 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
7461 vars->link_status |=
7462 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
7463 if (USES_WARPCORE(sc)) {
7465 if (elink_xmac_enable(params, vars, 0) ==
7466 ELINK_STATUS_NO_LINK) {
7467 ELINK_DEBUG_P0(sc, "Found errors on XMAC\n");
7469 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7470 vars->link_status &= ~LINK_STATUS_LINK_UP;
7473 elink_umac_enable(params, vars, 0);
7474 elink_set_led(params, vars,
7475 ELINK_LED_MODE_OPER, vars->line_speed);
7477 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
7478 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
7479 ELINK_DEBUG_P0(sc, "Enabling LPI assertion\n");
7480 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
7481 (params->port << 2), 1);
7482 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
7483 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
7484 (params->port << 2), 0xfc20);
7487 if ((CHIP_IS_E1x(sc) ||
7490 if (elink_bmac_enable(params, vars, 0, 1) ==
7491 ELINK_STATUS_NO_LINK) {
7492 ELINK_DEBUG_P0(sc, "Found errors on BMAC\n");
7494 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7495 vars->link_status &= ~LINK_STATUS_LINK_UP;
7498 elink_set_led(params, vars,
7499 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
7501 rc = elink_emac_program(params, vars);
7502 elink_emac_enable(params, vars, 0);
7505 if ((vars->link_status &
7506 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
7507 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
7508 ELINK_SINGLE_MEDIA_DIRECT(params))
7509 elink_set_gmii_tx_driver(params);
7514 if (CHIP_IS_E1x(sc))
7515 rc |= elink_pbf_update(params, vars->flow_ctrl,
7519 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
7521 /* Update shared memory */
7522 elink_update_mng(params, vars->link_status);
7523 elink_update_mng_eee(params, vars->eee_status);
7524 /* Check remote fault */
7525 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7526 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
7527 elink_check_half_open_conn(params, vars, 0);
7534 /* The elink_link_update function should be called upon link
7536 * Link is considered up as follows:
7537 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
7539 * - SINGLE_MEDIA - The link between the 577xx and the external
7540 * phy (XGXS) need to up as well as the external link of the
7542 * - DUAL_MEDIA - The link between the 577xx and the first
7543 * external phy needs to be up, and at least one of the 2
7544 * external phy link must be up.
7546 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars)
7548 struct bxe_softc *sc = params->sc;
7549 struct elink_vars phy_vars[ELINK_MAX_PHYS];
7550 uint8_t port = params->port;
7551 uint8_t link_10g_plus, phy_index;
7552 uint8_t ext_phy_link_up = 0, cur_link_up;
7553 elink_status_t rc = ELINK_STATUS_OK;
7554 uint8_t is_mi_int = 0;
7555 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
7556 uint8_t active_external_phy = ELINK_INT_PHY;
7557 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
7558 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7559 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
7561 phy_vars[phy_index].flow_ctrl = 0;
7562 phy_vars[phy_index].link_status = 0;
7563 phy_vars[phy_index].line_speed = 0;
7564 phy_vars[phy_index].duplex = DUPLEX_FULL;
7565 phy_vars[phy_index].phy_link_up = 0;
7566 phy_vars[phy_index].link_up = 0;
7567 phy_vars[phy_index].fault_detected = 0;
7568 /* different consideration, since vars holds inner state */
7569 phy_vars[phy_index].eee_status = vars->eee_status;
7572 if (USES_WARPCORE(sc))
7573 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
7575 ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x\n",
7576 port, (vars->phy_flags & PHY_XGXS_FLAG),
7577 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
7579 is_mi_int = (uint8_t)(REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
7581 ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
7582 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
7584 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
7586 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
7587 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
7588 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
7591 if (!CHIP_IS_E3(sc))
7592 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7595 * Check external link change only for external phys, and apply
7596 * priority selection between them in case the link on both phys
7597 * is up. Note that instead of the common vars, a temporary
7598 * vars argument is used since each phy may have different link/
7599 * speed/duplex result
7601 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7603 struct elink_phy *phy = ¶ms->phy[phy_index];
7604 if (!phy->read_status)
7606 /* Read link status and params of this ext phy */
7607 cur_link_up = phy->read_status(phy, params,
7608 &phy_vars[phy_index]);
7610 ELINK_DEBUG_P1(sc, "phy in index %d link is up\n",
7613 ELINK_DEBUG_P1(sc, "phy in index %d link is down\n",
7618 if (!ext_phy_link_up) {
7619 ext_phy_link_up = 1;
7620 active_external_phy = phy_index;
7622 switch (elink_phy_selection(params)) {
7623 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
7624 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7625 /* In this option, the first PHY makes sure to pass the
7626 * traffic through itself only.
7627 * Its not clear how to reset the link on the second phy
7629 active_external_phy = ELINK_EXT_PHY1;
7631 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7632 /* In this option, the first PHY makes sure to pass the
7633 * traffic through the second PHY.
7635 active_external_phy = ELINK_EXT_PHY2;
7638 /* Link indication on both PHYs with the following cases
7640 * - FIRST_PHY means that second phy wasn't initialized,
7641 * hence its link is expected to be down
7642 * - SECOND_PHY means that first phy should not be able
7643 * to link up by itself (using configuration)
7644 * - DEFAULT should be overriden during initialiazation
7646 ELINK_DEBUG_P1(sc, "Invalid link indication"
7647 "mpc=0x%x. DISABLING LINK !!!\n",
7648 params->multi_phy_config);
7649 ext_phy_link_up = 0;
7654 prev_line_speed = vars->line_speed;
7656 * Read the status of the internal phy. In case of
7657 * DIRECT_SINGLE_MEDIA board, this link is the external link,
7658 * otherwise this is the link between the 577xx and the first
7661 if (params->phy[ELINK_INT_PHY].read_status)
7662 params->phy[ELINK_INT_PHY].read_status(
7663 ¶ms->phy[ELINK_INT_PHY],
7665 /* The INT_PHY flow control reside in the vars. This include the
7666 * case where the speed or flow control are not set to AUTO.
7667 * Otherwise, the active external phy flow control result is set
7668 * to the vars. The ext_phy_line_speed is needed to check if the
7669 * speed is different between the internal phy and external phy.
7670 * This case may be result of intermediate link speed change.
7672 if (active_external_phy > ELINK_INT_PHY) {
7673 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
7674 /* Link speed is taken from the XGXS. AN and FC result from
7677 vars->link_status |= phy_vars[active_external_phy].link_status;
7679 /* if active_external_phy is first PHY and link is up - disable
7680 * disable TX on second external PHY
7682 if (active_external_phy == ELINK_EXT_PHY1) {
7683 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
7685 "Disabling TX on EXT_PHY2\n");
7686 params->phy[ELINK_EXT_PHY2].phy_specific_func(
7687 ¶ms->phy[ELINK_EXT_PHY2],
7688 params, ELINK_DISABLE_TX);
7692 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
7693 vars->duplex = phy_vars[active_external_phy].duplex;
7694 if (params->phy[active_external_phy].supported &
7695 ELINK_SUPPORTED_FIBRE)
7696 vars->link_status |= LINK_STATUS_SERDES_LINK;
7698 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
7700 vars->eee_status = phy_vars[active_external_phy].eee_status;
7702 ELINK_DEBUG_P1(sc, "Active external phy selected: %x\n",
7703 active_external_phy);
7706 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7708 if (params->phy[phy_index].flags &
7709 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
7710 elink_rearm_latch_signal(sc, port,
7712 active_external_phy);
7716 ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
7717 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
7718 vars->link_status, ext_phy_line_speed);
7719 /* Upon link speed change set the NIG into drain mode. Comes to
7720 * deals with possible FIFO glitch due to clk change when speed
7721 * is decreased without link down indicator
7724 if (vars->phy_link_up) {
7725 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
7726 (ext_phy_line_speed != vars->line_speed)) {
7727 ELINK_DEBUG_P2(sc, "Internal link speed %d is"
7728 " different than the external"
7729 " link speed %d\n", vars->line_speed,
7730 ext_phy_line_speed);
7731 vars->phy_link_up = 0;
7732 } else if (prev_line_speed != vars->line_speed) {
7733 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7739 /* Anything 10 and over uses the bmac */
7740 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
7742 elink_link_int_ack(params, vars, link_10g_plus);
7744 /* In case external phy link is up, and internal link is down
7745 * (not initialized yet probably after link initialization, it
7746 * needs to be initialized.
7747 * Note that after link down-up as result of cable plug, the xgxs
7748 * link would probably become up again without the need
7751 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
7752 ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d,"
7753 " init_preceding = %d\n", ext_phy_link_up,
7755 params->phy[ELINK_EXT_PHY1].flags &
7756 ELINK_FLAGS_INIT_XGXS_FIRST);
7757 if (!(params->phy[ELINK_EXT_PHY1].flags &
7758 ELINK_FLAGS_INIT_XGXS_FIRST)
7759 && ext_phy_link_up && !vars->phy_link_up) {
7760 vars->line_speed = ext_phy_line_speed;
7761 if (vars->line_speed < ELINK_SPEED_1000)
7762 vars->phy_flags |= PHY_SGMII_FLAG;
7764 vars->phy_flags &= ~PHY_SGMII_FLAG;
7766 if (params->phy[ELINK_INT_PHY].config_init)
7767 params->phy[ELINK_INT_PHY].config_init(
7768 ¶ms->phy[ELINK_INT_PHY], params,
7772 /* Link is up only if both local phy and external phy (in case of
7773 * non-direct board) are up and no fault detected on active PHY.
7775 vars->link_up = (vars->phy_link_up &&
7777 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
7778 (phy_vars[active_external_phy].fault_detected == 0));
7780 /* Update the PFC configuration in case it was changed */
7781 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
7782 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7784 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7787 rc = elink_update_link_up(params, vars, link_10g_plus);
7789 rc = elink_update_link_down(params, vars);
7791 /* Update MCP link status was changed */
7792 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7793 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7798 /*****************************************************************************/
7799 /* External Phy section */
7800 /*****************************************************************************/
7801 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port)
7803 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7804 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7806 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7807 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7810 static void elink_save_spirom_version(struct bxe_softc *sc, uint8_t port,
7811 uint32_t spirom_ver, uint32_t ver_addr)
7813 ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d\n",
7814 (uint16_t)(spirom_ver>>16), (uint16_t)spirom_ver, port);
7817 REG_WR(sc, ver_addr, spirom_ver);
7820 static void elink_save_bcm_spirom_ver(struct bxe_softc *sc,
7821 struct elink_phy *phy,
7824 uint16_t fw_ver1, fw_ver2;
7826 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7827 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7828 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7829 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7830 elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1<<16 | fw_ver2),
7834 static void elink_ext_phy_10G_an_resolve(struct bxe_softc *sc,
7835 struct elink_phy *phy,
7836 struct elink_vars *vars)
7839 elink_cl45_read(sc, phy,
7841 MDIO_AN_REG_STATUS, &val);
7842 elink_cl45_read(sc, phy,
7844 MDIO_AN_REG_STATUS, &val);
7846 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7847 if ((val & (1<<0)) == 0)
7848 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7851 /******************************************************************/
7852 /* common BCM8073/BCM8727 PHY SECTION */
7853 /******************************************************************/
7854 static void elink_8073_resolve_fc(struct elink_phy *phy,
7855 struct elink_params *params,
7856 struct elink_vars *vars)
7858 struct bxe_softc *sc = params->sc;
7859 if (phy->req_line_speed == ELINK_SPEED_10 ||
7860 phy->req_line_speed == ELINK_SPEED_100) {
7861 vars->flow_ctrl = phy->req_flow_ctrl;
7865 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
7866 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
7867 uint16_t pause_result;
7868 uint16_t ld_pause; /* local */
7869 uint16_t lp_pause; /* link partner */
7870 elink_cl45_read(sc, phy,
7872 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7874 elink_cl45_read(sc, phy,
7876 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7877 pause_result = (ld_pause &
7878 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7879 pause_result |= (lp_pause &
7880 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7882 elink_pause_resolve(vars, pause_result);
7883 ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x\n",
7887 static elink_status_t elink_8073_8727_external_rom_boot(struct bxe_softc *sc,
7888 struct elink_phy *phy,
7892 uint16_t fw_ver1, fw_msgout;
7893 elink_status_t rc = ELINK_STATUS_OK;
7895 /* Boot port from external ROM */
7897 elink_cl45_write(sc, phy,
7899 MDIO_PMA_REG_GEN_CTRL,
7902 /* Ucode reboot and rst */
7903 elink_cl45_write(sc, phy,
7905 MDIO_PMA_REG_GEN_CTRL,
7908 elink_cl45_write(sc, phy,
7910 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7912 /* Reset internal microprocessor */
7913 elink_cl45_write(sc, phy,
7915 MDIO_PMA_REG_GEN_CTRL,
7916 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7918 /* Release srst bit */
7919 elink_cl45_write(sc, phy,
7921 MDIO_PMA_REG_GEN_CTRL,
7922 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7924 /* Delay 100ms per the PHY specifications */
7927 /* 8073 sometimes taking longer to download */
7932 "elink_8073_8727_external_rom_boot port %x:"
7933 "Download failed. fw version = 0x%x\n",
7935 rc = ELINK_STATUS_ERROR;
7939 elink_cl45_read(sc, phy,
7941 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7942 elink_cl45_read(sc, phy,
7944 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7947 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7948 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7949 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7951 /* Clear ser_boot_ctl bit */
7952 elink_cl45_write(sc, phy,
7954 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7955 elink_save_bcm_spirom_ver(sc, phy, port);
7958 "elink_8073_8727_external_rom_boot port %x:"
7959 "Download complete. fw version = 0x%x\n",
7965 /******************************************************************/
7966 /* BCM8073 PHY SECTION */
7967 /******************************************************************/
7968 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)
7970 /* This is only required for 8073A1, version 102 only */
7973 /* Read 8073 HW revision*/
7974 elink_cl45_read(sc, phy,
7976 MDIO_PMA_REG_8073_CHIP_REV, &val);
7979 /* No need to workaround in 8073 A1 */
7980 return ELINK_STATUS_OK;
7983 elink_cl45_read(sc, phy,
7985 MDIO_PMA_REG_ROM_VER2, &val);
7987 /* SNR should be applied only for version 0x102 */
7989 return ELINK_STATUS_OK;
7994 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)
7996 uint16_t val, cnt, cnt1 ;
7998 elink_cl45_read(sc, phy,
8000 MDIO_PMA_REG_8073_CHIP_REV, &val);
8003 /* No need to workaround in 8073 A1 */
8004 return ELINK_STATUS_OK;
8006 /* XAUI workaround in 8073 A0: */
8008 /* After loading the boot ROM and restarting Autoneg, poll
8012 for (cnt = 0; cnt < 1000; cnt++) {
8013 elink_cl45_read(sc, phy,
8015 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8017 /* If bit [14] = 0 or bit [13] = 0, continue on with
8018 * system initialization (XAUI work-around not required, as
8019 * these bits indicate 2.5G or 1G link up).
8021 if (!(val & (1<<14)) || !(val & (1<<13))) {
8022 ELINK_DEBUG_P0(sc, "XAUI work-around not required\n");
8023 return ELINK_STATUS_OK;
8024 } else if (!(val & (1<<15))) {
8025 ELINK_DEBUG_P0(sc, "bit 15 went off\n");
8026 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
8027 * MSB (bit15) goes to 1 (indicating that the XAUI
8028 * workaround has completed), then continue on with
8029 * system initialization.
8031 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
8032 elink_cl45_read(sc, phy,
8034 MDIO_PMA_REG_8073_XAUI_WA, &val);
8035 if (val & (1<<15)) {
8037 "XAUI workaround has completed\n");
8038 return ELINK_STATUS_OK;
8046 ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!\n");
8047 return ELINK_STATUS_ERROR;
8050 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)
8052 /* Force KR or KX */
8053 elink_cl45_write(sc, phy,
8054 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8055 elink_cl45_write(sc, phy,
8056 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
8057 elink_cl45_write(sc, phy,
8058 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
8059 elink_cl45_write(sc, phy,
8060 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
8063 static void elink_8073_set_pause_cl37(struct elink_params *params,
8064 struct elink_phy *phy,
8065 struct elink_vars *vars)
8068 struct bxe_softc *sc = params->sc;
8069 elink_cl45_read(sc, phy,
8070 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
8072 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8073 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
8074 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
8075 if ((vars->ieee_fc &
8076 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
8077 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
8078 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
8080 if ((vars->ieee_fc &
8081 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
8082 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
8083 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
8085 if ((vars->ieee_fc &
8086 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
8087 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
8088 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8091 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
8093 elink_cl45_write(sc, phy,
8094 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
8098 static void elink_8073_specific_func(struct elink_phy *phy,
8099 struct elink_params *params,
8102 struct bxe_softc *sc = params->sc;
8104 case ELINK_PHY_INIT:
8106 elink_cl45_write(sc, phy,
8107 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
8108 elink_cl45_write(sc, phy,
8109 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8114 static elink_status_t elink_8073_config_init(struct elink_phy *phy,
8115 struct elink_params *params,
8116 struct elink_vars *vars)
8118 struct bxe_softc *sc = params->sc;
8119 uint16_t val = 0, tmp1;
8121 ELINK_DEBUG_P0(sc, "Init 8073\n");
8124 gpio_port = SC_PATH(sc);
8126 gpio_port = params->port;
8127 /* Restore normal power mode*/
8128 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8129 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8131 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8132 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8134 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
8135 elink_8073_set_pause_cl37(params, phy, vars);
8137 elink_cl45_read(sc, phy,
8138 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8140 elink_cl45_read(sc, phy,
8141 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8143 ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
8145 /* Swap polarity if required - Must be done only in non-1G mode */
8146 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8147 /* Configure the 8073 to swap _P and _N of the KR lines */
8148 ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073\n");
8149 /* 10G Rx/Tx and 1G Tx signal polarity swap */
8150 elink_cl45_read(sc, phy,
8152 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
8153 elink_cl45_write(sc, phy,
8155 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
8160 /* Enable CL37 BAM */
8161 if (REG_RD(sc, params->shmem_base +
8162 offsetof(struct shmem_region, dev_info.
8163 port_hw_config[params->port].default_cfg)) &
8164 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
8166 elink_cl45_read(sc, phy,
8168 MDIO_AN_REG_8073_BAM, &val);
8169 elink_cl45_write(sc, phy,
8171 MDIO_AN_REG_8073_BAM, val | 1);
8172 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
8174 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
8175 elink_807x_force_10G(sc, phy);
8176 ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X\n");
8177 return ELINK_STATUS_OK;
8179 elink_cl45_write(sc, phy,
8180 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
8182 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
8183 if (phy->req_line_speed == ELINK_SPEED_10000) {
8185 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
8187 /* Note that 2.5G works only when used with 1G
8194 if (phy->speed_cap_mask &
8195 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
8198 /* Note that 2.5G works only when used with 1G advertisement */
8199 if (phy->speed_cap_mask &
8200 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
8201 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8203 ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x\n", val);
8206 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
8207 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
8209 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
8210 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
8211 (phy->req_line_speed == ELINK_SPEED_2500)) {
8213 /* Allow 2.5G for A1 and above */
8214 elink_cl45_read(sc, phy,
8215 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
8217 ELINK_DEBUG_P0(sc, "Add 2.5G\n");
8223 ELINK_DEBUG_P0(sc, "Disable 2.5G\n");
8227 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
8228 /* Add support for CL37 (passive mode) II */
8230 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
8231 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
8232 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
8235 /* Add support for CL37 (passive mode) III */
8236 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8238 /* The SNR will improve about 2db by changing BW and FEE main
8239 * tap. Rest commands are executed after link is up
8240 * Change FFE main cursor to 5 in EDC register
8242 if (elink_8073_is_snr_needed(sc, phy))
8243 elink_cl45_write(sc, phy,
8244 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
8247 /* Enable FEC (Forware Error Correction) Request in the AN */
8248 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
8250 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
8252 elink_ext_phy_set_pause(params, phy, vars);
8254 /* Restart autoneg */
8256 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8257 ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
8258 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
8259 return ELINK_STATUS_OK;
8262 static uint8_t elink_8073_read_status(struct elink_phy *phy,
8263 struct elink_params *params,
8264 struct elink_vars *vars)
8266 struct bxe_softc *sc = params->sc;
8267 uint8_t link_up = 0;
8268 uint16_t val1, val2;
8269 uint16_t link_status = 0;
8270 uint16_t an1000_status = 0;
8272 elink_cl45_read(sc, phy,
8273 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8275 ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x\n", val1);
8277 /* Clear the interrupt LASI status register */
8278 elink_cl45_read(sc, phy,
8279 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8280 elink_cl45_read(sc, phy,
8281 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
8282 ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x\n", val2, val1);
8284 elink_cl45_read(sc, phy,
8285 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8287 /* Check the LASI */
8288 elink_cl45_read(sc, phy,
8289 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8291 ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x\n", val2);
8293 /* Check the link status */
8294 elink_cl45_read(sc, phy,
8295 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8296 ELINK_DEBUG_P1(sc, "KR PCS status 0x%x\n", val2);
8298 elink_cl45_read(sc, phy,
8299 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8300 elink_cl45_read(sc, phy,
8301 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8302 link_up = ((val1 & 4) == 4);
8303 ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x\n", val1);
8306 ((phy->req_line_speed != ELINK_SPEED_10000))) {
8307 if (elink_8073_xaui_wa(sc, phy) != 0)
8310 elink_cl45_read(sc, phy,
8311 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8312 elink_cl45_read(sc, phy,
8313 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8315 /* Check the link status on 1.1.2 */
8316 elink_cl45_read(sc, phy,
8317 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8318 elink_cl45_read(sc, phy,
8319 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8320 ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x,"
8321 "an_link_status=0x%x\n", val2, val1, an1000_status);
8323 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
8324 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
8325 /* The SNR will improve about 2dbby changing the BW and FEE main
8326 * tap. The 1st write to change FFE main tap is set before
8327 * restart AN. Change PLL Bandwidth in EDC register
8329 elink_cl45_write(sc, phy,
8330 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
8333 /* Change CDR Bandwidth in EDC register */
8334 elink_cl45_write(sc, phy,
8335 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
8338 elink_cl45_read(sc, phy,
8339 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8342 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
8343 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8345 vars->line_speed = ELINK_SPEED_10000;
8346 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
8348 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
8350 vars->line_speed = ELINK_SPEED_2500;
8351 ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n",
8353 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8355 vars->line_speed = ELINK_SPEED_1000;
8356 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
8360 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
8365 /* Swap polarity if required */
8366 if (params->lane_config &
8367 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8368 /* Configure the 8073 to swap P and N of the KR lines */
8369 elink_cl45_read(sc, phy,
8371 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
8372 /* Set bit 3 to invert Rx in 1G mode and clear this bit
8373 * when it`s in 10G mode.
8375 if (vars->line_speed == ELINK_SPEED_1000) {
8376 ELINK_DEBUG_P0(sc, "Swapping 1G polarity for"
8382 elink_cl45_write(sc, phy,
8384 MDIO_XS_REG_8073_RX_CTRL_PCIE,
8387 elink_ext_phy_10G_an_resolve(sc, phy, vars);
8388 elink_8073_resolve_fc(phy, params, vars);
8389 vars->duplex = DUPLEX_FULL;
8392 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
8393 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
8394 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
8397 vars->link_status |=
8398 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
8400 vars->link_status |=
8401 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
8407 static void elink_8073_link_reset(struct elink_phy *phy,
8408 struct elink_params *params)
8410 struct bxe_softc *sc = params->sc;
8413 gpio_port = SC_PATH(sc);
8415 gpio_port = params->port;
8416 ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode\n",
8418 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8419 MISC_REGISTERS_GPIO_OUTPUT_LOW,
8423 /******************************************************************/
8424 /* BCM8705 PHY SECTION */
8425 /******************************************************************/
8426 static elink_status_t elink_8705_config_init(struct elink_phy *phy,
8427 struct elink_params *params,
8428 struct elink_vars *vars)
8430 struct bxe_softc *sc = params->sc;
8431 ELINK_DEBUG_P0(sc, "init 8705\n");
8432 /* Restore normal power mode*/
8433 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8434 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8436 elink_ext_phy_hw_reset(sc, params->port);
8437 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8438 elink_wait_reset_complete(sc, phy, params);
8440 elink_cl45_write(sc, phy,
8441 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
8442 elink_cl45_write(sc, phy,
8443 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
8444 elink_cl45_write(sc, phy,
8445 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
8446 elink_cl45_write(sc, phy,
8447 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
8448 /* BCM8705 doesn't have microcode, hence the 0 */
8449 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
8450 return ELINK_STATUS_OK;
8453 static uint8_t elink_8705_read_status(struct elink_phy *phy,
8454 struct elink_params *params,
8455 struct elink_vars *vars)
8457 uint8_t link_up = 0;
8458 uint16_t val1, rx_sd;
8459 struct bxe_softc *sc = params->sc;
8460 ELINK_DEBUG_P0(sc, "read status 8705\n");
8461 elink_cl45_read(sc, phy,
8462 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8463 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8465 elink_cl45_read(sc, phy,
8466 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8467 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8469 elink_cl45_read(sc, phy,
8470 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8472 elink_cl45_read(sc, phy,
8473 MDIO_PMA_DEVAD, 0xc809, &val1);
8474 elink_cl45_read(sc, phy,
8475 MDIO_PMA_DEVAD, 0xc809, &val1);
8477 ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x\n", val1);
8478 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
8480 vars->line_speed = ELINK_SPEED_10000;
8481 elink_ext_phy_resolve_fc(phy, params, vars);
8486 /******************************************************************/
8487 /* SFP+ module Section */
8488 /******************************************************************/
8489 static void elink_set_disable_pmd_transmit(struct elink_params *params,
8490 struct elink_phy *phy,
8493 struct bxe_softc *sc = params->sc;
8494 /* Disable transmitter only for bootcodes which can enable it afterwards
8498 if (params->feature_config_flags &
8499 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
8500 ELINK_DEBUG_P0(sc, "Disabling PMD transmitter\n");
8502 ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter\n");
8506 ELINK_DEBUG_P0(sc, "Enabling PMD transmitter\n");
8507 elink_cl45_write(sc, phy,
8509 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
8512 static uint8_t elink_get_gpio_port(struct elink_params *params)
8515 uint32_t swap_val, swap_override;
8516 struct bxe_softc *sc = params->sc;
8518 gpio_port = SC_PATH(sc);
8520 gpio_port = params->port;
8521 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8522 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8523 return gpio_port ^ (swap_val && swap_override);
8526 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
8527 struct elink_phy *phy,
8531 uint8_t port = params->port;
8532 struct bxe_softc *sc = params->sc;
8533 uint32_t tx_en_mode;
8535 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
8536 tx_en_mode = REG_RD(sc, params->shmem_base +
8537 offsetof(struct shmem_region,
8538 dev_info.port_hw_config[port].sfp_ctrl)) &
8539 PORT_HW_CFG_TX_LASER_MASK;
8540 ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x "
8541 "mode = %x\n", tx_en, port, tx_en_mode);
8542 switch (tx_en_mode) {
8543 case PORT_HW_CFG_TX_LASER_MDIO:
8545 elink_cl45_read(sc, phy,
8547 MDIO_PMA_REG_PHY_IDENTIFIER,
8555 elink_cl45_write(sc, phy,
8557 MDIO_PMA_REG_PHY_IDENTIFIER,
8560 case PORT_HW_CFG_TX_LASER_GPIO0:
8561 case PORT_HW_CFG_TX_LASER_GPIO1:
8562 case PORT_HW_CFG_TX_LASER_GPIO2:
8563 case PORT_HW_CFG_TX_LASER_GPIO3:
8566 uint8_t gpio_port, gpio_mode;
8568 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
8570 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
8572 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
8573 gpio_port = elink_get_gpio_port(params);
8574 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
8578 ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
8583 static void elink_sfp_set_transmitter(struct elink_params *params,
8584 struct elink_phy *phy,
8587 struct bxe_softc *sc = params->sc;
8588 ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d\n", tx_en);
8590 elink_sfp_e3_set_transmitter(params, phy, tx_en);
8592 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
8595 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
8596 struct elink_params *params,
8597 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8598 uint8_t *o_buf, uint8_t is_init)
8600 struct bxe_softc *sc = params->sc;
8603 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8605 "Reading from eeprom is limited to 0xf\n");
8606 return ELINK_STATUS_ERROR;
8608 /* Set the read command byte count */
8609 elink_cl45_write(sc, phy,
8610 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8611 (byte_cnt | (dev_addr << 8)));
8613 /* Set the read command address */
8614 elink_cl45_write(sc, phy,
8615 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8618 /* Activate read command */
8619 elink_cl45_write(sc, phy,
8620 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8623 /* Wait up to 500us for command complete status */
8624 for (i = 0; i < 100; i++) {
8625 elink_cl45_read(sc, phy,
8627 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8628 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8629 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8634 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8635 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8637 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8638 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8639 return ELINK_STATUS_ERROR;
8642 /* Read the buffer */
8643 for (i = 0; i < byte_cnt; i++) {
8644 elink_cl45_read(sc, phy,
8646 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
8647 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
8650 for (i = 0; i < 100; i++) {
8651 elink_cl45_read(sc, phy,
8653 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8654 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8655 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8656 return ELINK_STATUS_OK;
8659 return ELINK_STATUS_ERROR;
8662 static void elink_warpcore_power_module(struct elink_params *params,
8666 struct bxe_softc *sc = params->sc;
8668 pin_cfg = (REG_RD(sc, params->shmem_base +
8669 offsetof(struct shmem_region,
8670 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8671 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8672 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8674 if (pin_cfg == PIN_CFG_NA)
8676 ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d\n",
8678 /* Low ==> corresponding SFP+ module is powered
8679 * high ==> the SFP+ module is powered down
8681 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
8683 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,
8684 struct elink_params *params,
8686 uint16_t addr, uint8_t byte_cnt,
8687 uint8_t *o_buf, uint8_t is_init)
8689 elink_status_t rc = ELINK_STATUS_OK;
8690 uint8_t i, j = 0, cnt = 0;
8691 uint32_t data_array[4];
8693 struct bxe_softc *sc = params->sc;
8695 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8697 "Reading from eeprom is limited to 16 bytes\n");
8698 return ELINK_STATUS_ERROR;
8701 /* 4 byte aligned address */
8702 addr32 = addr & (~0x3);
8704 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
8705 elink_warpcore_power_module(params, 0);
8706 /* Note that 100us are not enough here */
8708 elink_warpcore_power_module(params, 1);
8710 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
8712 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
8714 if (rc == ELINK_STATUS_OK) {
8715 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
8716 o_buf[j] = *((uint8_t *)data_array + i);
8724 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
8725 struct elink_params *params,
8726 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8727 uint8_t *o_buf, uint8_t is_init)
8729 struct bxe_softc *sc = params->sc;
8732 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8734 "Reading from eeprom is limited to 0xf\n");
8735 return ELINK_STATUS_ERROR;
8738 /* Set 2-wire transfer rate of SFP+ module EEPROM
8739 * to 100Khz since some DACs(direct attached cables) do
8740 * not work at 400Khz.
8742 elink_cl45_write(sc, phy,
8744 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8745 ((dev_addr << 8) | 1));
8747 /* Need to read from 1.8000 to clear it */
8748 elink_cl45_read(sc, phy,
8750 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8753 /* Set the read command byte count */
8754 elink_cl45_write(sc, phy,
8756 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8757 ((byte_cnt < 2) ? 2 : byte_cnt));
8759 /* Set the read command address */
8760 elink_cl45_write(sc, phy,
8762 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8764 /* Set the destination address */
8765 elink_cl45_write(sc, phy,
8768 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8770 /* Activate read command */
8771 elink_cl45_write(sc, phy,
8773 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8775 /* Wait appropriate time for two-wire command to finish before
8776 * polling the status register
8780 /* Wait up to 500us for command complete status */
8781 for (i = 0; i < 100; i++) {
8782 elink_cl45_read(sc, phy,
8784 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8785 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8786 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8791 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8792 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8794 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8795 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8796 return ELINK_STATUS_TIMEOUT;
8799 /* Read the buffer */
8800 for (i = 0; i < byte_cnt; i++) {
8801 elink_cl45_read(sc, phy,
8803 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8804 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8807 for (i = 0; i < 100; i++) {
8808 elink_cl45_read(sc, phy,
8810 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8811 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8812 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8813 return ELINK_STATUS_OK;
8817 return ELINK_STATUS_ERROR;
8819 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
8820 struct elink_params *params, uint8_t dev_addr,
8821 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf)
8823 elink_status_t rc = 0;
8824 struct bxe_softc *sc = params->sc;
8826 uint8_t *user_data = o_buf;
8827 read_sfp_module_eeprom_func_p read_func;
8828 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8829 ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x\n", dev_addr);
8830 return ELINK_STATUS_ERROR;
8833 switch (phy->type) {
8834 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8835 read_func = elink_8726_read_sfp_module_eeprom;
8837 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8838 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8839 read_func = elink_8727_read_sfp_module_eeprom;
8841 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8842 read_func = elink_warpcore_read_sfp_module_eeprom;
8845 return ELINK_OP_NOT_SUPPORTED;
8848 while (!rc && (byte_cnt > 0)) {
8849 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
8850 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
8851 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8853 byte_cnt -= xfer_size;
8854 user_data += xfer_size;
8860 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
8861 struct elink_params *params,
8864 struct bxe_softc *sc = params->sc;
8865 uint32_t sync_offset = 0, phy_idx, media_types;
8866 uint8_t gport, val[2], check_limiting_mode = 0;
8867 *edc_mode = ELINK_EDC_MODE_LIMITING;
8868 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
8869 /* First check for copper cable */
8870 if (elink_read_sfp_module_eeprom(phy,
8872 ELINK_I2C_DEV_ADDR_A0,
8873 ELINK_SFP_EEPROM_CON_TYPE_ADDR,
8875 (uint8_t *)val) != 0) {
8876 ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM\n");
8877 return ELINK_STATUS_ERROR;
8881 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
8883 uint8_t copper_module_type;
8884 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
8885 /* Check if its active cable (includes SFP+ module)
8888 if (elink_read_sfp_module_eeprom(phy,
8890 ELINK_I2C_DEV_ADDR_A0,
8891 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
8893 &copper_module_type) != 0) {
8895 "Failed to read copper-cable-type"
8896 " from SFP+ EEPROM\n");
8897 return ELINK_STATUS_ERROR;
8900 if (copper_module_type &
8901 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8902 ELINK_DEBUG_P0(sc, "Active Copper cable detected\n");
8903 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8904 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
8906 check_limiting_mode = 1;
8907 } else if (copper_module_type &
8908 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8910 "Passive Copper cable detected\n");
8912 ELINK_EDC_MODE_PASSIVE_DAC;
8915 "Unknown copper-cable-type 0x%x !!!\n",
8916 copper_module_type);
8917 return ELINK_STATUS_ERROR;
8921 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
8922 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
8923 check_limiting_mode = 1;
8924 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
8925 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
8926 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8927 ELINK_DEBUG_P0(sc, "1G SFP module detected\n");
8928 gport = params->port;
8929 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
8930 if (phy->req_line_speed != ELINK_SPEED_1000) {
8931 phy->req_line_speed = ELINK_SPEED_1000;
8932 if (!CHIP_IS_E1x(sc)) {
8933 gport = SC_PATH(sc) +
8934 (params->port << 1);
8936 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
8937 // " Current SFP module in port %d is not"
8938 // " compliant with 10G Ethernet\n",
8942 int idx, cfg_idx = 0;
8943 ELINK_DEBUG_P0(sc, "10G Optic module detected\n");
8944 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
8945 if (params->phy[idx].type == phy->type) {
8946 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
8950 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
8951 phy->req_line_speed = params->req_line_speed[cfg_idx];
8955 ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!\n",
8957 return ELINK_STATUS_ERROR;
8959 sync_offset = params->shmem_base +
8960 offsetof(struct shmem_region,
8961 dev_info.port_hw_config[params->port].media_type);
8962 media_types = REG_RD(sc, sync_offset);
8963 /* Update media type for non-PMF sync */
8964 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
8965 if (&(params->phy[phy_idx]) == phy) {
8966 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8967 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8968 media_types |= ((phy->media_type &
8969 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8970 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8974 REG_WR(sc, sync_offset, media_types);
8975 if (check_limiting_mode) {
8976 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
8977 if (elink_read_sfp_module_eeprom(phy,
8979 ELINK_I2C_DEV_ADDR_A0,
8980 ELINK_SFP_EEPROM_OPTIONS_ADDR,
8981 ELINK_SFP_EEPROM_OPTIONS_SIZE,
8984 "Failed to read Option field from module EEPROM\n");
8985 return ELINK_STATUS_ERROR;
8987 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8988 *edc_mode = ELINK_EDC_MODE_LINEAR;
8990 *edc_mode = ELINK_EDC_MODE_LIMITING;
8992 ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x\n", *edc_mode);
8993 return ELINK_STATUS_OK;
8995 /* This function read the relevant field from the module (SFP+), and verify it
8996 * is compliant with this board
8998 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
8999 struct elink_params *params)
9001 struct bxe_softc *sc = params->sc;
9003 uint32_t fw_resp, fw_cmd_param;
9004 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1];
9005 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1];
9006 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
9007 val = REG_RD(sc, params->shmem_base +
9008 offsetof(struct shmem_region, dev_info.
9009 port_feature_config[params->port].config));
9010 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9011 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
9012 ELINK_DEBUG_P0(sc, "NOT enforcing module verification\n");
9013 return ELINK_STATUS_OK;
9016 if (params->feature_config_flags &
9017 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
9018 /* Use specific phy request */
9019 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
9020 } else if (params->feature_config_flags &
9021 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
9022 /* Use first phy request only in case of non-dual media*/
9023 if (ELINK_DUAL_MEDIA(params)) {
9025 "FW does not support OPT MDL verification\n");
9026 return ELINK_STATUS_ERROR;
9028 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
9030 /* No support in OPT MDL detection */
9032 "FW does not support OPT MDL verification\n");
9033 return ELINK_STATUS_ERROR;
9036 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
9037 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
9038 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
9039 ELINK_DEBUG_P0(sc, "Approved module\n");
9040 return ELINK_STATUS_OK;
9043 /* Format the warning message */
9044 if (elink_read_sfp_module_eeprom(phy,
9046 ELINK_I2C_DEV_ADDR_A0,
9047 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
9048 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
9049 (uint8_t *)vendor_name))
9050 vendor_name[0] = '\0';
9052 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
9053 if (elink_read_sfp_module_eeprom(phy,
9055 ELINK_I2C_DEV_ADDR_A0,
9056 ELINK_SFP_EEPROM_PART_NO_ADDR,
9057 ELINK_SFP_EEPROM_PART_NO_SIZE,
9058 (uint8_t *)vendor_pn))
9059 vendor_pn[0] = '\0';
9061 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
9063 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
9064 // " Port %d from %s part number %s\n",
9066 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
9067 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
9068 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
9069 return ELINK_STATUS_ERROR;
9072 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,
9073 struct elink_params *params)
9078 struct bxe_softc *sc = params->sc;
9080 /* Initialization time after hot-plug may take up to 300ms for
9081 * some phys type ( e.g. JDSU )
9084 for (timeout = 0; timeout < 60; timeout++) {
9085 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9086 rc = elink_warpcore_read_sfp_module_eeprom(
9087 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
9090 rc = elink_read_sfp_module_eeprom(phy, params,
9091 ELINK_I2C_DEV_ADDR_A0,
9095 "SFP+ module initialization took %d ms\n",
9097 return ELINK_STATUS_OK;
9101 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
9106 static void elink_8727_power_module(struct bxe_softc *sc,
9107 struct elink_phy *phy,
9108 uint8_t is_power_up) {
9109 /* Make sure GPIOs are not using for LED mode */
9111 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
9112 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
9114 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
9115 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
9116 * where the 1st bit is the over-current(only input), and 2nd bit is
9117 * for power( only output )
9119 * In case of NOC feature is disabled and power is up, set GPIO control
9120 * as input to enable listening of over-current indication
9122 if (phy->flags & ELINK_FLAGS_NOC)
9127 /* Set GPIO control to OUTPUT, and set the power bit
9128 * to according to the is_power_up
9132 elink_cl45_write(sc, phy,
9134 MDIO_PMA_REG_8727_GPIO_CTRL,
9138 static elink_status_t elink_8726_set_limiting_mode(struct bxe_softc *sc,
9139 struct elink_phy *phy,
9142 uint16_t cur_limiting_mode;
9144 elink_cl45_read(sc, phy,
9146 MDIO_PMA_REG_ROM_VER2,
9147 &cur_limiting_mode);
9148 ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x\n",
9151 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
9152 ELINK_DEBUG_P0(sc, "Setting LIMITING MODE\n");
9153 elink_cl45_write(sc, phy,
9155 MDIO_PMA_REG_ROM_VER2,
9156 ELINK_EDC_MODE_LIMITING);
9157 } else { /* LRM mode ( default )*/
9159 ELINK_DEBUG_P0(sc, "Setting LRM MODE\n");
9161 /* Changing to LRM mode takes quite few seconds. So do it only
9162 * if current mode is limiting (default is LRM)
9164 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
9165 return ELINK_STATUS_OK;
9167 elink_cl45_write(sc, phy,
9169 MDIO_PMA_REG_LRM_MODE,
9171 elink_cl45_write(sc, phy,
9173 MDIO_PMA_REG_ROM_VER2,
9175 elink_cl45_write(sc, phy,
9177 MDIO_PMA_REG_MISC_CTRL0,
9179 elink_cl45_write(sc, phy,
9181 MDIO_PMA_REG_LRM_MODE,
9184 return ELINK_STATUS_OK;
9187 static elink_status_t elink_8727_set_limiting_mode(struct bxe_softc *sc,
9188 struct elink_phy *phy,
9191 uint16_t phy_identifier;
9192 uint16_t rom_ver2_val;
9193 elink_cl45_read(sc, phy,
9195 MDIO_PMA_REG_PHY_IDENTIFIER,
9198 elink_cl45_write(sc, phy,
9200 MDIO_PMA_REG_PHY_IDENTIFIER,
9201 (phy_identifier & ~(1<<9)));
9203 elink_cl45_read(sc, phy,
9205 MDIO_PMA_REG_ROM_VER2,
9207 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
9208 elink_cl45_write(sc, phy,
9210 MDIO_PMA_REG_ROM_VER2,
9211 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
9213 elink_cl45_write(sc, phy,
9215 MDIO_PMA_REG_PHY_IDENTIFIER,
9216 (phy_identifier | (1<<9)));
9218 return ELINK_STATUS_OK;
9221 static void elink_8727_specific_func(struct elink_phy *phy,
9222 struct elink_params *params,
9225 struct bxe_softc *sc = params->sc;
9228 case ELINK_DISABLE_TX:
9229 elink_sfp_set_transmitter(params, phy, 0);
9231 case ELINK_ENABLE_TX:
9232 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
9233 elink_sfp_set_transmitter(params, phy, 1);
9235 case ELINK_PHY_INIT:
9236 elink_cl45_write(sc, phy,
9237 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9239 elink_cl45_write(sc, phy,
9240 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9242 elink_cl45_write(sc, phy,
9243 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
9244 /* Make MOD_ABS give interrupt on change */
9245 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9246 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9249 if (phy->flags & ELINK_FLAGS_NOC)
9251 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9252 * status which reflect SFP+ module over-current
9254 if (!(phy->flags & ELINK_FLAGS_NOC))
9255 val &= 0xff8f; /* Reset bits 4-6 */
9256 elink_cl45_write(sc, phy,
9257 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9261 ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727\n",
9267 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
9270 struct bxe_softc *sc = params->sc;
9272 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
9273 offsetof(struct shmem_region,
9274 dev_info.port_hw_config[params->port].sfp_ctrl)) &
9275 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
9276 switch (fault_led_gpio) {
9277 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
9279 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
9280 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
9281 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
9282 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
9284 uint8_t gpio_port = elink_get_gpio_port(params);
9285 uint16_t gpio_pin = fault_led_gpio -
9286 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
9287 ELINK_DEBUG_P3(sc, "Set fault module-detected led "
9288 "pin %x port %x mode %x\n",
9289 gpio_pin, gpio_port, gpio_mode);
9290 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
9294 ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x\n",
9299 static void elink_set_e3_module_fault_led(struct elink_params *params,
9303 uint8_t port = params->port;
9304 struct bxe_softc *sc = params->sc;
9305 pin_cfg = (REG_RD(sc, params->shmem_base +
9306 offsetof(struct shmem_region,
9307 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
9308 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
9309 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
9310 ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d\n",
9311 gpio_mode, pin_cfg);
9312 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
9315 static void elink_set_sfp_module_fault_led(struct elink_params *params,
9318 struct bxe_softc *sc = params->sc;
9319 ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d\n", gpio_mode);
9320 if (CHIP_IS_E3(sc)) {
9321 /* Low ==> if SFP+ module is supported otherwise
9322 * High ==> if SFP+ module is not on the approved vendor list
9324 elink_set_e3_module_fault_led(params, gpio_mode);
9326 elink_set_e1e2_module_fault_led(params, gpio_mode);
9329 static void elink_warpcore_hw_reset(struct elink_phy *phy,
9330 struct elink_params *params)
9332 struct bxe_softc *sc = params->sc;
9333 elink_warpcore_power_module(params, 0);
9334 /* Put Warpcore in low power mode */
9335 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
9337 /* Put LCPLL in low power mode */
9338 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
9339 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
9340 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
9343 static void elink_power_sfp_module(struct elink_params *params,
9344 struct elink_phy *phy,
9347 struct bxe_softc *sc = params->sc;
9348 ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x\n", power);
9350 switch (phy->type) {
9351 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9352 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9353 elink_8727_power_module(params->sc, phy, power);
9355 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9356 elink_warpcore_power_module(params, power);
9362 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
9363 struct elink_phy *phy,
9367 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9368 struct bxe_softc *sc = params->sc;
9370 uint8_t lane = elink_get_warpcore_lane(phy, params);
9371 /* This is a global register which controls all lanes */
9372 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9373 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9374 val &= ~(0xf << (lane << 2));
9377 case ELINK_EDC_MODE_LINEAR:
9378 case ELINK_EDC_MODE_LIMITING:
9379 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9381 case ELINK_EDC_MODE_PASSIVE_DAC:
9382 case ELINK_EDC_MODE_ACTIVE_DAC:
9383 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
9389 val |= (mode << (lane << 2));
9390 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
9391 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
9393 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9394 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9396 /* Restart microcode to re-read the new mode */
9397 elink_warpcore_reset_lane(sc, phy, 1);
9398 elink_warpcore_reset_lane(sc, phy, 0);
9402 static void elink_set_limiting_mode(struct elink_params *params,
9403 struct elink_phy *phy,
9406 switch (phy->type) {
9407 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
9408 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
9410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9411 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9412 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
9414 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9415 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
9420 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
9421 struct elink_params *params)
9423 struct bxe_softc *sc = params->sc;
9425 elink_status_t rc = ELINK_STATUS_OK;
9427 uint32_t val = REG_RD(sc, params->shmem_base +
9428 offsetof(struct shmem_region, dev_info.
9429 port_feature_config[params->port].config));
9430 /* Enabled transmitter by default */
9431 elink_sfp_set_transmitter(params, phy, 1);
9432 ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d\n",
9434 /* Power up module */
9435 elink_power_sfp_module(params, phy, 1);
9436 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
9437 ELINK_DEBUG_P0(sc, "Failed to get valid module type\n");
9438 return ELINK_STATUS_ERROR;
9439 } else if (elink_verify_sfp_module(phy, params) != 0) {
9440 /* Check SFP+ module compatibility */
9441 ELINK_DEBUG_P0(sc, "Module verification failed!!\n");
9442 rc = ELINK_STATUS_ERROR;
9443 /* Turn on fault module-detected led */
9444 elink_set_sfp_module_fault_led(params,
9445 MISC_REGISTERS_GPIO_HIGH);
9447 /* Check if need to power down the SFP+ module */
9448 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9449 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
9450 ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!\n");
9451 elink_power_sfp_module(params, phy, 0);
9455 /* Turn off fault module-detected led */
9456 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
9459 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
9460 * is done automatically
9462 elink_set_limiting_mode(params, phy, edc_mode);
9464 /* Disable transmit for this module if the module is not approved, and
9465 * laser needs to be disabled.
9468 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9469 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
9470 elink_sfp_set_transmitter(params, phy, 0);
9475 void elink_handle_module_detect_int(struct elink_params *params)
9477 struct bxe_softc *sc = params->sc;
9478 struct elink_phy *phy;
9480 uint8_t gpio_num, gpio_port;
9481 if (CHIP_IS_E3(sc)) {
9482 phy = ¶ms->phy[ELINK_INT_PHY];
9483 /* Always enable TX laser,will be disabled in case of fault */
9484 elink_sfp_set_transmitter(params, phy, 1);
9486 phy = ¶ms->phy[ELINK_EXT_PHY1];
9488 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base,
9489 params->port, &gpio_num, &gpio_port) ==
9490 ELINK_STATUS_ERROR) {
9491 ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config\n");
9495 /* Set valid module led off */
9496 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
9498 /* Get current gpio val reflecting module plugged in / out*/
9499 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
9501 /* Call the handling function in case module is detected */
9502 if (gpio_val == 0) {
9503 elink_set_mdio_emac_per_phy(sc, params);
9504 elink_set_aer_mmd(params, phy);
9506 elink_power_sfp_module(params, phy, 1);
9507 elink_cb_gpio_int_write(sc, gpio_num,
9508 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
9510 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
9511 elink_sfp_module_detection(phy, params);
9512 if (CHIP_IS_E3(sc)) {
9513 uint16_t rx_tx_in_reset;
9514 /* In case WC is out of reset, reconfigure the
9515 * link speed while taking into account 1G
9516 * module limitation.
9518 elink_cl45_read(sc, phy,
9520 MDIO_WC_REG_DIGITAL5_MISC6,
9522 if ((!rx_tx_in_reset) &&
9523 (params->link_flags &
9524 ELINK_PHY_INITIALIZED)) {
9525 elink_warpcore_reset_lane(sc, phy, 1);
9526 elink_warpcore_config_sfi(phy, params);
9527 elink_warpcore_reset_lane(sc, phy, 0);
9531 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
9534 elink_cb_gpio_int_write(sc, gpio_num,
9535 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
9537 /* Module was plugged out.
9538 * Disable transmit for this module
9540 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
9544 /******************************************************************/
9545 /* Used by 8706 and 8727 */
9546 /******************************************************************/
9547 static void elink_sfp_mask_fault(struct bxe_softc *sc,
9548 struct elink_phy *phy,
9549 uint16_t alarm_status_offset,
9550 uint16_t alarm_ctrl_offset)
9552 uint16_t alarm_status, val;
9553 elink_cl45_read(sc, phy,
9554 MDIO_PMA_DEVAD, alarm_status_offset,
9556 elink_cl45_read(sc, phy,
9557 MDIO_PMA_DEVAD, alarm_status_offset,
9559 /* Mask or enable the fault event. */
9560 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
9561 if (alarm_status & (1<<0))
9565 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
9567 /******************************************************************/
9568 /* common BCM8706/BCM8726 PHY SECTION */
9569 /******************************************************************/
9570 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
9571 struct elink_params *params,
9572 struct elink_vars *vars)
9574 uint8_t link_up = 0;
9575 uint16_t val1, val2, rx_sd, pcs_status;
9576 struct bxe_softc *sc = params->sc;
9577 ELINK_DEBUG_P0(sc, "XGXS 8706/8726\n");
9579 elink_cl45_read(sc, phy,
9580 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
9582 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
9583 MDIO_PMA_LASI_TXCTRL);
9585 /* Clear LASI indication*/
9586 elink_cl45_read(sc, phy,
9587 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9588 elink_cl45_read(sc, phy,
9589 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
9590 ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
9592 elink_cl45_read(sc, phy,
9593 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
9594 elink_cl45_read(sc, phy,
9595 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
9596 elink_cl45_read(sc, phy,
9597 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9598 elink_cl45_read(sc, phy,
9599 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9601 ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
9602 " link_status 0x%x\n", rx_sd, pcs_status, val2);
9603 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
9604 * are set, or if the autoneg bit 1 is set
9606 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
9609 vars->line_speed = ELINK_SPEED_1000;
9611 vars->line_speed = ELINK_SPEED_10000;
9612 elink_ext_phy_resolve_fc(phy, params, vars);
9613 vars->duplex = DUPLEX_FULL;
9616 /* Capture 10G link fault. Read twice to clear stale value. */
9617 if (vars->line_speed == ELINK_SPEED_10000) {
9618 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9619 MDIO_PMA_LASI_TXSTAT, &val1);
9620 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9621 MDIO_PMA_LASI_TXSTAT, &val1);
9623 vars->fault_detected = 1;
9629 /******************************************************************/
9630 /* BCM8706 PHY SECTION */
9631 /******************************************************************/
9632 static uint8_t elink_8706_config_init(struct elink_phy *phy,
9633 struct elink_params *params,
9634 struct elink_vars *vars)
9636 uint32_t tx_en_mode;
9637 uint16_t cnt, val, tmp1;
9638 struct bxe_softc *sc = params->sc;
9640 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9641 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9643 elink_ext_phy_hw_reset(sc, params->port);
9644 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
9645 elink_wait_reset_complete(sc, phy, params);
9647 /* Wait until fw is loaded */
9648 for (cnt = 0; cnt < 100; cnt++) {
9649 elink_cl45_read(sc, phy,
9650 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
9655 ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms\n", cnt);
9656 if ((params->feature_config_flags &
9657 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9660 for (i = 0; i < 4; i++) {
9661 reg = MDIO_XS_8706_REG_BANK_RX0 +
9662 i*(MDIO_XS_8706_REG_BANK_RX1 -
9663 MDIO_XS_8706_REG_BANK_RX0);
9664 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
9665 /* Clear first 3 bits of the control */
9667 /* Set control bits according to configuration */
9668 val |= (phy->rx_preemphasis[i] & 0x7);
9669 ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BCM8706"
9670 " reg 0x%x <-- val 0x%x\n", reg, val);
9671 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
9675 if (phy->req_line_speed == ELINK_SPEED_10000) {
9676 ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps\n");
9678 elink_cl45_write(sc, phy,
9680 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
9681 elink_cl45_write(sc, phy,
9682 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9684 /* Arm LASI for link and Tx fault. */
9685 elink_cl45_write(sc, phy,
9686 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
9688 /* Force 1Gbps using autoneg with 1G advertisement */
9690 /* Allow CL37 through CL73 */
9691 ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg\n");
9692 elink_cl45_write(sc, phy,
9693 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9695 /* Enable Full-Duplex advertisement on CL37 */
9696 elink_cl45_write(sc, phy,
9697 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
9698 /* Enable CL37 AN */
9699 elink_cl45_write(sc, phy,
9700 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9702 elink_cl45_write(sc, phy,
9703 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
9705 /* Enable clause 73 AN */
9706 elink_cl45_write(sc, phy,
9707 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9708 elink_cl45_write(sc, phy,
9709 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9711 elink_cl45_write(sc, phy,
9712 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9715 elink_save_bcm_spirom_ver(sc, phy, params->port);
9717 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9718 * power mode, if TX Laser is disabled
9721 tx_en_mode = REG_RD(sc, params->shmem_base +
9722 offsetof(struct shmem_region,
9723 dev_info.port_hw_config[params->port].sfp_ctrl))
9724 & PORT_HW_CFG_TX_LASER_MASK;
9726 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9727 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
9728 elink_cl45_read(sc, phy,
9729 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
9731 elink_cl45_write(sc, phy,
9732 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
9735 return ELINK_STATUS_OK;
9738 static elink_status_t elink_8706_read_status(struct elink_phy *phy,
9739 struct elink_params *params,
9740 struct elink_vars *vars)
9742 return elink_8706_8726_read_status(phy, params, vars);
9745 /******************************************************************/
9746 /* BCM8726 PHY SECTION */
9747 /******************************************************************/
9748 static void elink_8726_config_loopback(struct elink_phy *phy,
9749 struct elink_params *params)
9751 struct bxe_softc *sc = params->sc;
9752 ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726\n");
9753 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9756 static void elink_8726_external_rom_boot(struct elink_phy *phy,
9757 struct elink_params *params)
9759 struct bxe_softc *sc = params->sc;
9760 /* Need to wait 100ms after reset */
9763 /* Micro controller re-boot */
9764 elink_cl45_write(sc, phy,
9765 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9767 /* Set soft reset */
9768 elink_cl45_write(sc, phy,
9770 MDIO_PMA_REG_GEN_CTRL,
9771 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9773 elink_cl45_write(sc, phy,
9775 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9777 elink_cl45_write(sc, phy,
9779 MDIO_PMA_REG_GEN_CTRL,
9780 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9782 /* Wait for 150ms for microcode load */
9785 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9786 elink_cl45_write(sc, phy,
9788 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9791 elink_save_bcm_spirom_ver(sc, phy, params->port);
9794 static uint8_t elink_8726_read_status(struct elink_phy *phy,
9795 struct elink_params *params,
9796 struct elink_vars *vars)
9798 struct bxe_softc *sc = params->sc;
9800 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
9802 elink_cl45_read(sc, phy,
9803 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9805 if (val1 & (1<<15)) {
9806 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
9808 vars->line_speed = 0;
9815 static elink_status_t elink_8726_config_init(struct elink_phy *phy,
9816 struct elink_params *params,
9817 struct elink_vars *vars)
9819 struct bxe_softc *sc = params->sc;
9820 ELINK_DEBUG_P0(sc, "Initializing BCM8726\n");
9822 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9823 elink_wait_reset_complete(sc, phy, params);
9825 elink_8726_external_rom_boot(phy, params);
9827 /* Need to call module detected on initialization since the module
9828 * detection triggered by actual module insertion might occur before
9829 * driver is loaded, and when driver is loaded, it reset all
9830 * registers, including the transmitter
9832 elink_sfp_module_detection(phy, params);
9834 if (phy->req_line_speed == ELINK_SPEED_1000) {
9835 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
9836 elink_cl45_write(sc, phy,
9837 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9838 elink_cl45_write(sc, phy,
9839 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9840 elink_cl45_write(sc, phy,
9841 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9842 elink_cl45_write(sc, phy,
9843 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9845 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9846 (phy->speed_cap_mask &
9847 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9848 ((phy->speed_cap_mask &
9849 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9850 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9851 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
9852 /* Set Flow control */
9853 elink_ext_phy_set_pause(params, phy, vars);
9854 elink_cl45_write(sc, phy,
9855 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9856 elink_cl45_write(sc, phy,
9857 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9858 elink_cl45_write(sc, phy,
9859 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9860 elink_cl45_write(sc, phy,
9861 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9862 elink_cl45_write(sc, phy,
9863 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9864 /* Enable RX-ALARM control to receive interrupt for 1G speed
9867 elink_cl45_write(sc, phy,
9868 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9869 elink_cl45_write(sc, phy,
9870 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9873 } else { /* Default 10G. Set only LASI control */
9874 elink_cl45_write(sc, phy,
9875 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9878 /* Set TX PreEmphasis if needed */
9879 if ((params->feature_config_flags &
9880 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9882 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9883 phy->tx_preemphasis[0],
9884 phy->tx_preemphasis[1]);
9885 elink_cl45_write(sc, phy,
9887 MDIO_PMA_REG_8726_TX_CTRL1,
9888 phy->tx_preemphasis[0]);
9890 elink_cl45_write(sc, phy,
9892 MDIO_PMA_REG_8726_TX_CTRL2,
9893 phy->tx_preemphasis[1]);
9896 return ELINK_STATUS_OK;
9900 static void elink_8726_link_reset(struct elink_phy *phy,
9901 struct elink_params *params)
9903 struct bxe_softc *sc = params->sc;
9904 ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d\n", params->port);
9905 /* Set serial boot control for external load */
9906 elink_cl45_write(sc, phy,
9908 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9911 /******************************************************************/
9912 /* BCM8727 PHY SECTION */
9913 /******************************************************************/
9915 static void elink_8727_set_link_led(struct elink_phy *phy,
9916 struct elink_params *params, uint8_t mode)
9918 struct bxe_softc *sc = params->sc;
9919 uint16_t led_mode_bitmask = 0;
9920 uint16_t gpio_pins_bitmask = 0;
9922 /* Only NOC flavor requires to set the LED specifically */
9923 if (!(phy->flags & ELINK_FLAGS_NOC))
9926 case ELINK_LED_MODE_FRONT_PANEL_OFF:
9927 case ELINK_LED_MODE_OFF:
9928 led_mode_bitmask = 0;
9929 gpio_pins_bitmask = 0x03;
9931 case ELINK_LED_MODE_ON:
9932 led_mode_bitmask = 0;
9933 gpio_pins_bitmask = 0x02;
9935 case ELINK_LED_MODE_OPER:
9936 led_mode_bitmask = 0x60;
9937 gpio_pins_bitmask = 0x11;
9940 elink_cl45_read(sc, phy,
9942 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9945 val |= led_mode_bitmask;
9946 elink_cl45_write(sc, phy,
9948 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9950 elink_cl45_read(sc, phy,
9952 MDIO_PMA_REG_8727_GPIO_CTRL,
9955 val |= gpio_pins_bitmask;
9956 elink_cl45_write(sc, phy,
9958 MDIO_PMA_REG_8727_GPIO_CTRL,
9961 static void elink_8727_hw_reset(struct elink_phy *phy,
9962 struct elink_params *params) {
9963 uint32_t swap_val, swap_override;
9965 /* The PHY reset is controlled by GPIO 1. Fake the port number
9966 * to cancel the swap done in set_gpio()
9968 struct bxe_softc *sc = params->sc;
9969 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
9970 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
9971 port = (swap_val && swap_override) ^ 1;
9972 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
9973 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9976 static void elink_8727_config_speed(struct elink_phy *phy,
9977 struct elink_params *params)
9979 struct bxe_softc *sc = params->sc;
9981 /* Set option 1G speed */
9982 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
9983 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
9984 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
9985 elink_cl45_write(sc, phy,
9986 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9987 elink_cl45_write(sc, phy,
9988 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9989 elink_cl45_read(sc, phy,
9990 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9991 ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1);
9992 /* Power down the XAUI until link is up in case of dual-media
9995 if (ELINK_DUAL_MEDIA(params)) {
9996 elink_cl45_read(sc, phy,
9998 MDIO_PMA_REG_8727_PCS_GP, &val);
10000 elink_cl45_write(sc, phy,
10002 MDIO_PMA_REG_8727_PCS_GP, val);
10004 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10005 ((phy->speed_cap_mask &
10006 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
10007 ((phy->speed_cap_mask &
10008 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
10009 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
10011 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
10012 elink_cl45_write(sc, phy,
10013 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
10014 elink_cl45_write(sc, phy,
10015 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
10017 /* Since the 8727 has only single reset pin, need to set the 10G
10018 * registers although it is default
10020 elink_cl45_write(sc, phy,
10021 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
10023 elink_cl45_write(sc, phy,
10024 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
10025 elink_cl45_write(sc, phy,
10026 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
10027 elink_cl45_write(sc, phy,
10028 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
10033 static elink_status_t elink_8727_config_init(struct elink_phy *phy,
10034 struct elink_params *params,
10035 struct elink_vars *vars)
10037 uint32_t tx_en_mode;
10038 uint16_t tmp1, mod_abs, tmp2;
10039 struct bxe_softc *sc = params->sc;
10040 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
10042 elink_wait_reset_complete(sc, phy, params);
10044 ELINK_DEBUG_P0(sc, "Initializing BCM8727\n");
10046 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
10047 /* Initially configure MOD_ABS to interrupt when module is
10050 elink_cl45_read(sc, phy,
10051 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10052 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
10053 * When the EDC is off it locks onto a reference clock and avoids
10056 mod_abs &= ~(1<<8);
10057 if (!(phy->flags & ELINK_FLAGS_NOC))
10058 mod_abs &= ~(1<<9);
10059 elink_cl45_write(sc, phy,
10060 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10062 /* Enable/Disable PHY transmitter output */
10063 elink_set_disable_pmd_transmit(params, phy, 0);
10065 elink_8727_power_module(sc, phy, 1);
10067 elink_cl45_read(sc, phy,
10068 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
10070 elink_cl45_read(sc, phy,
10071 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
10073 elink_8727_config_speed(phy, params);
10076 /* Set TX PreEmphasis if needed */
10077 if ((params->feature_config_flags &
10078 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
10079 ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
10080 phy->tx_preemphasis[0],
10081 phy->tx_preemphasis[1]);
10082 elink_cl45_write(sc, phy,
10083 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
10084 phy->tx_preemphasis[0]);
10086 elink_cl45_write(sc, phy,
10087 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
10088 phy->tx_preemphasis[1]);
10091 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
10092 * power mode, if TX Laser is disabled
10094 tx_en_mode = REG_RD(sc, params->shmem_base +
10095 offsetof(struct shmem_region,
10096 dev_info.port_hw_config[params->port].sfp_ctrl))
10097 & PORT_HW_CFG_TX_LASER_MASK;
10099 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
10101 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
10102 elink_cl45_read(sc, phy,
10103 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
10106 elink_cl45_write(sc, phy,
10107 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
10108 elink_cl45_read(sc, phy,
10109 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10111 elink_cl45_write(sc, phy,
10112 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10116 return ELINK_STATUS_OK;
10119 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
10120 struct elink_params *params)
10122 struct bxe_softc *sc = params->sc;
10123 uint16_t mod_abs, rx_alarm_status;
10124 uint32_t val = REG_RD(sc, params->shmem_base +
10125 offsetof(struct shmem_region, dev_info.
10126 port_feature_config[params->port].
10128 elink_cl45_read(sc, phy,
10130 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10131 if (mod_abs & (1<<8)) {
10133 /* Module is absent */
10135 "MOD_ABS indication show module is absent\n");
10136 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
10137 /* 1. Set mod_abs to detect next module
10139 * 2. Set EDC off by setting OPTXLOS signal input to low
10141 * When the EDC is off it locks onto a reference clock and
10142 * avoids becoming 'lost'.
10144 mod_abs &= ~(1<<8);
10145 if (!(phy->flags & ELINK_FLAGS_NOC))
10146 mod_abs &= ~(1<<9);
10147 elink_cl45_write(sc, phy,
10149 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10151 /* Clear RX alarm since it stays up as long as
10152 * the mod_abs wasn't changed
10154 elink_cl45_read(sc, phy,
10156 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10159 /* Module is present */
10161 "MOD_ABS indication show module is present\n");
10162 /* First disable transmitter, and if the module is ok, the
10163 * module_detection will enable it
10164 * 1. Set mod_abs to detect next module absent event ( bit 8)
10165 * 2. Restore the default polarity of the OPRXLOS signal and
10166 * this signal will then correctly indicate the presence or
10167 * absence of the Rx signal. (bit 9)
10170 if (!(phy->flags & ELINK_FLAGS_NOC))
10172 elink_cl45_write(sc, phy,
10174 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10176 /* Clear RX alarm since it stays up as long as the mod_abs
10177 * wasn't changed. This is need to be done before calling the
10178 * module detection, otherwise it will clear* the link update
10181 elink_cl45_read(sc, phy,
10183 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10186 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
10187 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
10188 elink_sfp_set_transmitter(params, phy, 0);
10190 if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
10191 elink_sfp_module_detection(phy, params);
10193 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
10195 /* Reconfigure link speed based on module type limitations */
10196 elink_8727_config_speed(phy, params);
10199 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n",
10201 /* No need to check link status in case of module plugged in/out */
10204 static uint8_t elink_8727_read_status(struct elink_phy *phy,
10205 struct elink_params *params,
10206 struct elink_vars *vars)
10209 struct bxe_softc *sc = params->sc;
10210 uint8_t link_up = 0, oc_port = params->port;
10211 uint16_t link_status = 0;
10212 uint16_t rx_alarm_status, lasi_ctrl, val1;
10214 /* If PHY is not initialized, do not check link status */
10215 elink_cl45_read(sc, phy,
10216 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
10221 /* Check the LASI on Rx */
10222 elink_cl45_read(sc, phy,
10223 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
10225 vars->line_speed = 0;
10226 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
10228 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
10229 MDIO_PMA_LASI_TXCTRL);
10231 elink_cl45_read(sc, phy,
10232 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10234 ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x\n", val1);
10236 /* Clear MSG-OUT */
10237 elink_cl45_read(sc, phy,
10238 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
10240 /* If a module is present and there is need to check
10243 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
10244 /* Check over-current using 8727 GPIO0 input*/
10245 elink_cl45_read(sc, phy,
10246 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
10249 if ((val1 & (1<<8)) == 0) {
10250 if (!CHIP_IS_E1x(sc))
10251 oc_port = SC_PATH(sc) + (params->port << 1);
10253 "8727 Power fault has been detected on port %d\n",
10255 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
10256 // "been detected and the power to "
10257 // "that SFP+ module has been removed "
10258 // "to prevent failure of the card. "
10259 // "Please remove the SFP+ module and "
10260 // "restart the system to clear this "
10262 /* Disable all RX_ALARMs except for mod_abs */
10263 elink_cl45_write(sc, phy,
10265 MDIO_PMA_LASI_RXCTRL, (1<<5));
10267 elink_cl45_read(sc, phy,
10269 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
10270 /* Wait for module_absent_event */
10272 elink_cl45_write(sc, phy,
10274 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
10275 /* Clear RX alarm */
10276 elink_cl45_read(sc, phy,
10278 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10279 elink_8727_power_module(params->sc, phy, 0);
10282 } /* Over current check */
10284 /* When module absent bit is set, check module */
10285 if (rx_alarm_status & (1<<5)) {
10286 elink_8727_handle_mod_abs(phy, params);
10287 /* Enable all mod_abs and link detection bits */
10288 elink_cl45_write(sc, phy,
10289 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
10290 ((1<<5) | (1<<2)));
10293 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
10294 ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser\n");
10295 elink_sfp_set_transmitter(params, phy, 1);
10297 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
10301 elink_cl45_read(sc, phy,
10303 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
10305 /* Bits 0..2 --> speed detected,
10306 * Bits 13..15--> link is down
10308 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
10310 vars->line_speed = ELINK_SPEED_10000;
10311 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
10313 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
10315 vars->line_speed = ELINK_SPEED_1000;
10316 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
10320 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
10324 /* Capture 10G link fault. */
10325 if (vars->line_speed == ELINK_SPEED_10000) {
10326 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10327 MDIO_PMA_LASI_TXSTAT, &val1);
10329 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10330 MDIO_PMA_LASI_TXSTAT, &val1);
10332 if (val1 & (1<<0)) {
10333 vars->fault_detected = 1;
10338 elink_ext_phy_resolve_fc(phy, params, vars);
10339 vars->duplex = DUPLEX_FULL;
10340 ELINK_DEBUG_P1(sc, "duplex = 0x%x\n", vars->duplex);
10343 if ((ELINK_DUAL_MEDIA(params)) &&
10344 (phy->req_line_speed == ELINK_SPEED_1000)) {
10345 elink_cl45_read(sc, phy,
10347 MDIO_PMA_REG_8727_PCS_GP, &val1);
10348 /* In case of dual-media board and 1G, power up the XAUI side,
10349 * otherwise power it down. For 10G it is done automatically
10355 elink_cl45_write(sc, phy,
10357 MDIO_PMA_REG_8727_PCS_GP, val1);
10362 static void elink_8727_link_reset(struct elink_phy *phy,
10363 struct elink_params *params)
10365 struct bxe_softc *sc = params->sc;
10367 /* Enable/Disable PHY transmitter output */
10368 elink_set_disable_pmd_transmit(params, phy, 1);
10370 /* Disable Transmitter */
10371 elink_sfp_set_transmitter(params, phy, 0);
10373 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
10377 /******************************************************************/
10378 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
10379 /******************************************************************/
10380 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
10381 struct bxe_softc *sc,
10384 uint16_t val, fw_ver2, cnt, i;
10385 static struct elink_reg_set reg_set[] = {
10386 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
10387 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
10388 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
10389 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
10390 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
10394 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10395 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10396 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
10397 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
10400 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
10401 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
10402 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10403 elink_cl45_write(sc, phy, reg_set[i].devad,
10404 reg_set[i].reg, reg_set[i].val);
10406 for (cnt = 0; cnt < 100; cnt++) {
10407 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10413 ELINK_DEBUG_P0(sc, "Unable to read 848xx "
10414 "phy fw version(1)\n");
10415 elink_save_spirom_version(sc, port, 0,
10421 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
10422 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
10423 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
10424 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
10425 for (cnt = 0; cnt < 100; cnt++) {
10426 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10432 ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw "
10434 elink_save_spirom_version(sc, port, 0,
10439 /* lower 16 bits of the register SPI_FW_STATUS */
10440 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
10441 /* upper 16 bits of register SPI_FW_STATUS */
10442 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
10444 elink_save_spirom_version(sc, port, (fw_ver2<<16) | fw_ver1,
10449 static void elink_848xx_set_led(struct bxe_softc *sc,
10450 struct elink_phy *phy)
10452 uint16_t val, offset, i;
10453 static struct elink_reg_set reg_set[] = {
10454 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
10455 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
10456 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
10457 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
10458 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
10459 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
10460 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
10462 /* PHYC_CTL_LED_CTL */
10463 elink_cl45_read(sc, phy,
10465 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10469 elink_cl45_write(sc, phy,
10471 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10473 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10474 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
10477 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10478 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10479 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
10481 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
10483 /* stretch_en for LED3*/
10484 elink_cl45_read_or_write(sc, phy,
10485 MDIO_PMA_DEVAD, offset,
10486 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
10489 static void elink_848xx_specific_func(struct elink_phy *phy,
10490 struct elink_params *params,
10493 struct bxe_softc *sc = params->sc;
10495 case ELINK_PHY_INIT:
10496 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10497 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10498 /* Save spirom version */
10499 elink_save_848xx_spirom_version(phy, sc, params->port);
10501 /* This phy uses the NIG latch mechanism since link indication
10502 * arrives through its LED4 and not via its LASI signal, so we
10503 * get steady signal instead of clear on read
10505 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port*4,
10506 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
10508 elink_848xx_set_led(sc, phy);
10513 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
10514 struct elink_params *params,
10515 struct elink_vars *vars)
10517 struct bxe_softc *sc = params->sc;
10518 uint16_t autoneg_val, an_1000_val, an_10_100_val;
10520 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
10521 elink_cl45_write(sc, phy,
10522 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
10524 /* set 1000 speed advertisement */
10525 elink_cl45_read(sc, phy,
10526 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10529 elink_ext_phy_set_pause(params, phy, vars);
10530 elink_cl45_read(sc, phy,
10532 MDIO_AN_REG_8481_LEGACY_AN_ADV,
10534 elink_cl45_read(sc, phy,
10535 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10537 /* Disable forced speed */
10538 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10539 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
10541 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10542 (phy->speed_cap_mask &
10543 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10544 (phy->req_line_speed == ELINK_SPEED_1000)) {
10545 an_1000_val |= (1<<8);
10546 autoneg_val |= (1<<9 | 1<<12);
10547 if (phy->req_duplex == DUPLEX_FULL)
10548 an_1000_val |= (1<<9);
10549 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
10551 an_1000_val &= ~((1<<8) | (1<<9));
10553 elink_cl45_write(sc, phy,
10554 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10557 /* Set 10/100 speed advertisement */
10558 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10559 if (phy->speed_cap_mask &
10560 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10561 /* Enable autoneg and restart autoneg for legacy speeds
10563 autoneg_val |= (1<<9 | 1<<12);
10564 an_10_100_val |= (1<<8);
10565 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
10568 if (phy->speed_cap_mask &
10569 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10570 /* Enable autoneg and restart autoneg for legacy speeds
10572 autoneg_val |= (1<<9 | 1<<12);
10573 an_10_100_val |= (1<<7);
10574 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
10577 if ((phy->speed_cap_mask &
10578 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
10579 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
10580 an_10_100_val |= (1<<6);
10581 autoneg_val |= (1<<9 | 1<<12);
10582 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
10585 if ((phy->speed_cap_mask &
10586 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
10587 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
10588 an_10_100_val |= (1<<5);
10589 autoneg_val |= (1<<9 | 1<<12);
10590 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
10594 /* Only 10/100 are allowed to work in FORCE mode */
10595 if ((phy->req_line_speed == ELINK_SPEED_100) &&
10597 (ELINK_SUPPORTED_100baseT_Half |
10598 ELINK_SUPPORTED_100baseT_Full))) {
10599 autoneg_val |= (1<<13);
10600 /* Enabled AUTO-MDIX when autoneg is disabled */
10601 elink_cl45_write(sc, phy,
10602 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10603 (1<<15 | 1<<9 | 7<<0));
10604 /* The PHY needs this set even for forced link. */
10605 an_10_100_val |= (1<<8) | (1<<7);
10606 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
10608 if ((phy->req_line_speed == ELINK_SPEED_10) &&
10610 (ELINK_SUPPORTED_10baseT_Half |
10611 ELINK_SUPPORTED_10baseT_Full))) {
10612 /* Enabled AUTO-MDIX when autoneg is disabled */
10613 elink_cl45_write(sc, phy,
10614 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10615 (1<<15 | 1<<9 | 7<<0));
10616 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
10619 elink_cl45_write(sc, phy,
10620 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
10623 if (phy->req_duplex == DUPLEX_FULL)
10624 autoneg_val |= (1<<8);
10626 /* Always write this if this is not 84833/4.
10627 * For 84833/4, write it only when it's a forced speed.
10629 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10630 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
10631 ((autoneg_val & (1<<12)) == 0))
10632 elink_cl45_write(sc, phy,
10634 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
10636 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10637 (phy->speed_cap_mask &
10638 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
10639 (phy->req_line_speed == ELINK_SPEED_10000)) {
10640 ELINK_DEBUG_P0(sc, "Advertising 10G\n");
10641 /* Restart autoneg for 10G*/
10643 elink_cl45_read_or_write(
10646 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10648 elink_cl45_write(sc, phy,
10649 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
10652 elink_cl45_write(sc, phy,
10654 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10657 return ELINK_STATUS_OK;
10660 static elink_status_t elink_8481_config_init(struct elink_phy *phy,
10661 struct elink_params *params,
10662 struct elink_vars *vars)
10664 struct bxe_softc *sc = params->sc;
10665 /* Restore normal power mode*/
10666 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10667 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10670 elink_ext_phy_hw_reset(sc, params->port);
10671 elink_wait_reset_complete(sc, phy, params);
10673 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
10674 return elink_848xx_cmn_config_init(phy, params, vars);
10677 #define PHY84833_CMDHDLR_WAIT 300
10678 #define PHY84833_CMDHDLR_MAX_ARGS 5
10679 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
10680 struct elink_params *params, uint16_t fw_cmd,
10681 uint16_t cmd_args[], int argc)
10685 struct bxe_softc *sc = params->sc;
10686 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10687 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10688 MDIO_84833_CMD_HDLR_STATUS,
10689 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10690 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
10691 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10692 MDIO_84833_CMD_HDLR_STATUS, &val);
10693 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10697 if (idx >= PHY84833_CMDHDLR_WAIT) {
10698 ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.\n");
10699 return ELINK_STATUS_ERROR;
10702 /* Prepare argument(s) and issue command */
10703 for (idx = 0; idx < argc; idx++) {
10704 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10705 MDIO_84833_CMD_HDLR_DATA1 + idx,
10708 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10709 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
10710 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
10711 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10712 MDIO_84833_CMD_HDLR_STATUS, &val);
10713 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10714 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10718 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
10719 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10720 ELINK_DEBUG_P0(sc, "FW cmd failed.\n");
10721 return ELINK_STATUS_ERROR;
10723 /* Gather returning data */
10724 for (idx = 0; idx < argc; idx++) {
10725 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10726 MDIO_84833_CMD_HDLR_DATA1 + idx,
10729 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10730 MDIO_84833_CMD_HDLR_STATUS,
10731 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10732 return ELINK_STATUS_OK;
10735 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
10736 struct elink_params *params,
10737 struct elink_vars *vars)
10739 uint32_t pair_swap;
10740 uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
10741 elink_status_t status;
10742 struct bxe_softc *sc = params->sc;
10744 /* Check for configuration. */
10745 pair_swap = REG_RD(sc, params->shmem_base +
10746 offsetof(struct shmem_region,
10747 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10748 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10750 if (pair_swap == 0)
10751 return ELINK_STATUS_OK;
10753 /* Only the second argument is used for this command */
10754 data[1] = (uint16_t)pair_swap;
10756 status = elink_84833_cmd_hdlr(phy, params,
10757 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
10758 if (status == ELINK_STATUS_OK)
10759 ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x\n", data[1]);
10764 static uint8_t elink_84833_get_reset_gpios(struct bxe_softc *sc,
10765 uint32_t shmem_base_path[],
10768 uint32_t reset_pin[2];
10770 uint8_t reset_gpios;
10771 if (CHIP_IS_E3(sc)) {
10772 /* Assume that these will be GPIOs, not EPIOs. */
10773 for (idx = 0; idx < 2; idx++) {
10774 /* Map config param to register bit. */
10775 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
10776 offsetof(struct shmem_region,
10777 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10778 reset_pin[idx] = (reset_pin[idx] &
10779 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10780 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10781 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10782 reset_pin[idx] = (1 << reset_pin[idx]);
10784 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
10786 /* E2, look from diff place of shmem. */
10787 for (idx = 0; idx < 2; idx++) {
10788 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
10789 offsetof(struct shmem_region,
10790 dev_info.port_hw_config[0].default_cfg));
10791 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10792 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10793 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10794 reset_pin[idx] = (1 << reset_pin[idx]);
10796 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
10799 return reset_gpios;
10802 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
10803 struct elink_params *params)
10805 struct bxe_softc *sc = params->sc;
10806 uint8_t reset_gpios;
10807 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
10808 offsetof(struct shmem2_region,
10809 other_shmem_base_addr));
10811 uint32_t shmem_base_path[2];
10813 /* Work around for 84833 LED failure inside RESET status */
10814 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10815 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10816 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10817 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10818 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10819 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10821 shmem_base_path[0] = params->shmem_base;
10822 shmem_base_path[1] = other_shmem_base_addr;
10824 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
10827 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10829 ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x\n",
10832 return ELINK_STATUS_OK;
10835 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
10836 struct elink_params *params,
10837 struct elink_vars *vars)
10840 struct bxe_softc *sc = params->sc;
10841 uint16_t cmd_args = 0;
10843 ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE\n");
10845 /* Prevent Phy from working in EEE and advertising it */
10846 rc = elink_84833_cmd_hdlr(phy, params,
10847 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10848 if (rc != ELINK_STATUS_OK) {
10849 ELINK_DEBUG_P0(sc, "EEE disable failed.\n");
10853 return elink_eee_disable(phy, params, vars);
10856 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
10857 struct elink_params *params,
10858 struct elink_vars *vars)
10861 struct bxe_softc *sc = params->sc;
10862 uint16_t cmd_args = 1;
10864 rc = elink_84833_cmd_hdlr(phy, params,
10865 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10866 if (rc != ELINK_STATUS_OK) {
10867 ELINK_DEBUG_P0(sc, "EEE enable failed.\n");
10871 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10874 #define PHY84833_CONSTANT_LATENCY 1193
10875 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
10876 struct elink_params *params,
10877 struct elink_vars *vars)
10879 struct bxe_softc *sc = params->sc;
10880 uint8_t port, initialize = 1;
10882 uint32_t actual_phy_selection;
10883 uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10884 elink_status_t rc = ELINK_STATUS_OK;
10888 if (!(CHIP_IS_E1x(sc)))
10889 port = SC_PATH(sc);
10891 port = params->port;
10893 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10894 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
10895 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10899 elink_cl45_write(sc, phy,
10901 MDIO_PMA_REG_CTRL, 0x8000);
10904 elink_wait_reset_complete(sc, phy, params);
10906 /* Wait for GPHY to come out of reset */
10908 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10909 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10910 /* BCM84823 requires that XGXS links up first @ 10G for normal
10914 temp = vars->line_speed;
10915 vars->line_speed = ELINK_SPEED_10000;
10916 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
10917 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
10918 vars->line_speed = temp;
10921 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10922 MDIO_CTL_REG_84823_MEDIA, &val);
10923 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10924 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10925 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10926 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10927 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10929 if (CHIP_IS_E3(sc)) {
10930 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10931 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10933 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10934 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10937 actual_phy_selection = elink_phy_selection(params);
10939 switch (actual_phy_selection) {
10940 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10941 /* Do nothing. Essentially this is like the priority copper */
10943 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10944 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10946 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10947 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10949 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10950 /* Do nothing here. The first PHY won't be initialized at all */
10952 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10953 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10957 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
10958 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10960 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10961 MDIO_CTL_REG_84823_MEDIA, val);
10962 ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10963 params->multi_phy_config, val);
10965 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10966 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10967 elink_84833_pair_swap_cfg(phy, params, vars);
10969 /* Keep AutogrEEEn disabled. */
10972 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10973 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10974 rc = elink_84833_cmd_hdlr(phy, params,
10975 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10976 PHY84833_CMDHDLR_MAX_ARGS);
10977 if (rc != ELINK_STATUS_OK)
10978 ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed.\n");
10981 rc = elink_848xx_cmn_config_init(phy, params, vars);
10983 elink_save_848xx_spirom_version(phy, sc, params->port);
10984 /* 84833 PHY has a better feature and doesn't need to support this. */
10985 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10986 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
10987 offsetof(struct shmem_region,
10988 dev_info.port_hw_config[params->port].default_cfg)) &
10989 PORT_HW_CFG_ENABLE_CMS_MASK;
10991 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10992 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10994 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10996 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10997 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10998 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
11001 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11002 MDIO_84833_TOP_CFG_FW_REV, &val);
11004 /* Configure EEE support */
11005 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
11006 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
11007 elink_eee_has_cap(params)) {
11008 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
11009 if (rc != ELINK_STATUS_OK) {
11010 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11011 elink_8483x_disable_eee(phy, params, vars);
11015 if ((phy->req_duplex == DUPLEX_FULL) &&
11016 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11017 (elink_eee_calc_timer(params) ||
11018 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
11019 rc = elink_8483x_enable_eee(phy, params, vars);
11021 rc = elink_8483x_disable_eee(phy, params, vars);
11022 if (rc != ELINK_STATUS_OK) {
11023 ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement\n");
11027 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
11030 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
11031 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11032 /* Bring PHY out of super isolate mode as the final step. */
11033 elink_cl45_read_and_write(sc, phy,
11035 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
11036 (uint16_t)~MDIO_84833_SUPER_ISOLATE);
11041 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
11042 struct elink_params *params,
11043 struct elink_vars *vars)
11045 struct bxe_softc *sc = params->sc;
11046 uint16_t val, val1, val2;
11047 uint8_t link_up = 0;
11050 /* Check 10G-BaseT link status */
11051 /* Check PMD signal ok */
11052 elink_cl45_read(sc, phy,
11053 MDIO_AN_DEVAD, 0xFFFA, &val1);
11054 elink_cl45_read(sc, phy,
11055 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
11057 ELINK_DEBUG_P1(sc, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
11059 /* Check link 10G */
11060 if (val2 & (1<<11)) {
11061 vars->line_speed = ELINK_SPEED_10000;
11062 vars->duplex = DUPLEX_FULL;
11064 elink_ext_phy_10G_an_resolve(sc, phy, vars);
11065 } else { /* Check Legacy speed link */
11066 uint16_t legacy_status, legacy_speed, mii_ctrl;
11068 /* Enable expansion register 0x42 (Operation mode status) */
11069 elink_cl45_write(sc, phy,
11071 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
11073 /* Get legacy speed operation status */
11074 elink_cl45_read(sc, phy,
11076 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
11079 ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x\n",
11081 link_up = ((legacy_status & (1<<11)) == (1<<11));
11082 legacy_speed = (legacy_status & (3<<9));
11083 if (legacy_speed == (0<<9))
11084 vars->line_speed = ELINK_SPEED_10;
11085 else if (legacy_speed == (1<<9))
11086 vars->line_speed = ELINK_SPEED_100;
11087 else if (legacy_speed == (2<<9))
11088 vars->line_speed = ELINK_SPEED_1000;
11089 else { /* Should not happen: Treat as link down */
11090 vars->line_speed = 0;
11094 if (params->feature_config_flags &
11095 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
11096 elink_cl45_read(sc, phy,
11098 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
11100 /* For IEEE testing, check for a fake link. */
11101 link_up |= ((mii_ctrl & 0x3040) == 0x40);
11105 if (legacy_status & (1<<8))
11106 vars->duplex = DUPLEX_FULL;
11108 vars->duplex = DUPLEX_HALF;
11111 "Link is up in %dMbps, is_duplex_full= %d\n",
11113 (vars->duplex == DUPLEX_FULL));
11114 /* Check legacy speed AN resolution */
11115 elink_cl45_read(sc, phy,
11117 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
11120 vars->link_status |=
11121 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11122 elink_cl45_read(sc, phy,
11124 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
11126 if ((val & (1<<0)) == 0)
11127 vars->link_status |=
11128 LINK_STATUS_PARALLEL_DETECTION_USED;
11132 ELINK_DEBUG_P1(sc, "BCM848x3: link speed is %d\n",
11134 elink_ext_phy_resolve_fc(phy, params, vars);
11136 /* Read LP advertised speeds */
11137 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11138 MDIO_AN_REG_CL37_FC_LP, &val);
11140 vars->link_status |=
11141 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11143 vars->link_status |=
11144 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11146 vars->link_status |=
11147 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11149 vars->link_status |=
11150 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11152 vars->link_status |=
11153 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11155 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11156 MDIO_AN_REG_1000T_STATUS, &val);
11159 vars->link_status |=
11160 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11162 vars->link_status |=
11163 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11165 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11166 MDIO_AN_REG_MASTER_STATUS, &val);
11169 vars->link_status |=
11170 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11172 /* Determine if EEE was negotiated */
11173 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
11174 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
11175 elink_eee_an_resolve(phy, params, vars);
11181 static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str, uint16_t *len)
11183 elink_status_t status = ELINK_STATUS_OK;
11184 uint32_t spirom_ver;
11185 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
11186 status = elink_format_ver(spirom_ver, str, len);
11190 static void elink_8481_hw_reset(struct elink_phy *phy,
11191 struct elink_params *params)
11193 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11194 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
11195 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11196 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
11199 static void elink_8481_link_reset(struct elink_phy *phy,
11200 struct elink_params *params)
11202 elink_cl45_write(params->sc, phy,
11203 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
11204 elink_cl45_write(params->sc, phy,
11205 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
11208 static void elink_848x3_link_reset(struct elink_phy *phy,
11209 struct elink_params *params)
11211 struct bxe_softc *sc = params->sc;
11215 if (!(CHIP_IS_E1x(sc)))
11216 port = SC_PATH(sc);
11218 port = params->port;
11220 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11221 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
11222 MISC_REGISTERS_GPIO_OUTPUT_LOW,
11225 elink_cl45_read(sc, phy,
11227 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
11228 val16 |= MDIO_84833_SUPER_ISOLATE;
11229 elink_cl45_write(sc, phy,
11231 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
11235 static void elink_848xx_set_link_led(struct elink_phy *phy,
11236 struct elink_params *params, uint8_t mode)
11238 struct bxe_softc *sc = params->sc;
11242 if (!(CHIP_IS_E1x(sc)))
11243 port = SC_PATH(sc);
11245 port = params->port;
11248 case ELINK_LED_MODE_OFF:
11250 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF\n", port);
11252 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11253 SHARED_HW_CFG_LED_EXTPHY1) {
11255 /* Set LED masks */
11256 elink_cl45_write(sc, phy,
11258 MDIO_PMA_REG_8481_LED1_MASK,
11261 elink_cl45_write(sc, phy,
11263 MDIO_PMA_REG_8481_LED2_MASK,
11266 elink_cl45_write(sc, phy,
11268 MDIO_PMA_REG_8481_LED3_MASK,
11271 elink_cl45_write(sc, phy,
11273 MDIO_PMA_REG_8481_LED5_MASK,
11277 elink_cl45_write(sc, phy,
11279 MDIO_PMA_REG_8481_LED1_MASK,
11283 case ELINK_LED_MODE_FRONT_PANEL_OFF:
11285 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
11288 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11289 SHARED_HW_CFG_LED_EXTPHY1) {
11291 /* Set LED masks */
11292 elink_cl45_write(sc, phy,
11294 MDIO_PMA_REG_8481_LED1_MASK,
11297 elink_cl45_write(sc, phy,
11299 MDIO_PMA_REG_8481_LED2_MASK,
11302 elink_cl45_write(sc, phy,
11304 MDIO_PMA_REG_8481_LED3_MASK,
11307 elink_cl45_write(sc, phy,
11309 MDIO_PMA_REG_8481_LED5_MASK,
11313 elink_cl45_write(sc, phy,
11315 MDIO_PMA_REG_8481_LED1_MASK,
11318 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11319 /* Disable MI_INT interrupt before setting LED4
11320 * source to constant off.
11322 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11324 ELINK_NIG_MASK_MI_INT) {
11325 params->link_flags |=
11326 ELINK_LINK_FLAGS_INT_DISABLED;
11330 NIG_REG_MASK_INTERRUPT_PORT0 +
11332 ELINK_NIG_MASK_MI_INT);
11334 elink_cl45_write(sc, phy,
11336 MDIO_PMA_REG_8481_SIGNAL_MASK,
11341 case ELINK_LED_MODE_ON:
11343 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON\n", port);
11345 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11346 SHARED_HW_CFG_LED_EXTPHY1) {
11347 /* Set control reg */
11348 elink_cl45_read(sc, phy,
11350 MDIO_PMA_REG_8481_LINK_SIGNAL,
11355 elink_cl45_write(sc, phy,
11357 MDIO_PMA_REG_8481_LINK_SIGNAL,
11360 /* Set LED masks */
11361 elink_cl45_write(sc, phy,
11363 MDIO_PMA_REG_8481_LED1_MASK,
11366 elink_cl45_write(sc, phy,
11368 MDIO_PMA_REG_8481_LED2_MASK,
11371 elink_cl45_write(sc, phy,
11373 MDIO_PMA_REG_8481_LED3_MASK,
11376 elink_cl45_write(sc, phy,
11378 MDIO_PMA_REG_8481_LED5_MASK,
11381 elink_cl45_write(sc, phy,
11383 MDIO_PMA_REG_8481_LED1_MASK,
11386 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11387 /* Disable MI_INT interrupt before setting LED4
11388 * source to constant on.
11390 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11392 ELINK_NIG_MASK_MI_INT) {
11393 params->link_flags |=
11394 ELINK_LINK_FLAGS_INT_DISABLED;
11398 NIG_REG_MASK_INTERRUPT_PORT0 +
11400 ELINK_NIG_MASK_MI_INT);
11402 elink_cl45_write(sc, phy,
11404 MDIO_PMA_REG_8481_SIGNAL_MASK,
11410 case ELINK_LED_MODE_OPER:
11412 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER\n", port);
11414 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11415 SHARED_HW_CFG_LED_EXTPHY1) {
11417 /* Set control reg */
11418 elink_cl45_read(sc, phy,
11420 MDIO_PMA_REG_8481_LINK_SIGNAL,
11424 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
11425 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
11426 ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL\n");
11427 elink_cl45_write(sc, phy,
11429 MDIO_PMA_REG_8481_LINK_SIGNAL,
11433 /* Set LED masks */
11434 elink_cl45_write(sc, phy,
11436 MDIO_PMA_REG_8481_LED1_MASK,
11439 elink_cl45_write(sc, phy,
11441 MDIO_PMA_REG_8481_LED2_MASK,
11444 elink_cl45_write(sc, phy,
11446 MDIO_PMA_REG_8481_LED3_MASK,
11449 elink_cl45_write(sc, phy,
11451 MDIO_PMA_REG_8481_LED5_MASK,
11455 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
11456 * sources are all wired through LED1, rather than only
11457 * 10G in other modes.
11459 val = ((params->hw_led_mode <<
11460 SHARED_HW_CFG_LED_MODE_SHIFT) ==
11461 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
11463 elink_cl45_write(sc, phy,
11465 MDIO_PMA_REG_8481_LED1_MASK,
11468 /* Tell LED3 to blink on source */
11469 elink_cl45_read(sc, phy,
11471 MDIO_PMA_REG_8481_LINK_SIGNAL,
11474 val |= (1<<6); /* A83B[8:6]= 1 */
11475 elink_cl45_write(sc, phy,
11477 MDIO_PMA_REG_8481_LINK_SIGNAL,
11480 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11481 /* Restore LED4 source to external link,
11482 * and re-enable interrupts.
11484 elink_cl45_write(sc, phy,
11486 MDIO_PMA_REG_8481_SIGNAL_MASK,
11488 if (params->link_flags &
11489 ELINK_LINK_FLAGS_INT_DISABLED) {
11490 elink_link_int_enable(params);
11491 params->link_flags &=
11492 ~ELINK_LINK_FLAGS_INT_DISABLED;
11499 /* This is a workaround for E3+84833 until autoneg
11500 * restart is fixed in f/w
11502 if (CHIP_IS_E3(sc)) {
11503 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
11504 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
11508 /******************************************************************/
11509 /* 54618SE PHY SECTION */
11510 /******************************************************************/
11511 static void elink_54618se_specific_func(struct elink_phy *phy,
11512 struct elink_params *params,
11515 struct bxe_softc *sc = params->sc;
11518 case ELINK_PHY_INIT:
11519 /* Configure LED4: set to INTR (0x6). */
11520 /* Accessing shadow register 0xe. */
11521 elink_cl22_write(sc, phy,
11522 MDIO_REG_GPHY_SHADOW,
11523 MDIO_REG_GPHY_SHADOW_LED_SEL2);
11524 elink_cl22_read(sc, phy,
11525 MDIO_REG_GPHY_SHADOW,
11527 temp &= ~(0xf << 4);
11528 temp |= (0x6 << 4);
11529 elink_cl22_write(sc, phy,
11530 MDIO_REG_GPHY_SHADOW,
11531 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11532 /* Configure INTR based on link status change. */
11533 elink_cl22_write(sc, phy,
11534 MDIO_REG_INTR_MASK,
11535 ~MDIO_REG_INTR_MASK_LINK_STATUS);
11540 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
11541 struct elink_params *params,
11542 struct elink_vars *vars)
11544 struct bxe_softc *sc = params->sc;
11546 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11549 ELINK_DEBUG_P0(sc, "54618SE cfg init\n");
11552 /* This works with E3 only, no need to check the chip
11553 * before determining the port.
11555 port = params->port;
11557 cfg_pin = (REG_RD(sc, params->shmem_base +
11558 offsetof(struct shmem_region,
11559 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11560 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11561 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11563 /* Drive pin high to bring the GPHY out of reset. */
11564 elink_set_cfg_pin(sc, cfg_pin, 1);
11566 /* wait for GPHY to reset */
11570 elink_cl22_write(sc, phy,
11571 MDIO_PMA_REG_CTRL, 0x8000);
11572 elink_wait_reset_complete(sc, phy, params);
11574 /* Wait for GPHY to reset */
11578 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
11579 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
11580 elink_cl22_write(sc, phy,
11581 MDIO_REG_GPHY_SHADOW,
11582 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11583 elink_cl22_read(sc, phy,
11584 MDIO_REG_GPHY_SHADOW,
11586 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11587 elink_cl22_write(sc, phy,
11588 MDIO_REG_GPHY_SHADOW,
11589 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11592 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
11593 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11595 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11596 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11597 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11599 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11600 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11601 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11603 /* Read all advertisement */
11604 elink_cl22_read(sc, phy,
11608 elink_cl22_read(sc, phy,
11612 elink_cl22_read(sc, phy,
11616 /* Disable forced speed */
11617 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11618 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11621 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
11622 (phy->speed_cap_mask &
11623 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11624 (phy->req_line_speed == ELINK_SPEED_1000)) {
11625 an_1000_val |= (1<<8);
11626 autoneg_val |= (1<<9 | 1<<12);
11627 if (phy->req_duplex == DUPLEX_FULL)
11628 an_1000_val |= (1<<9);
11629 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
11631 an_1000_val &= ~((1<<8) | (1<<9));
11633 elink_cl22_write(sc, phy,
11636 elink_cl22_read(sc, phy,
11640 /* Advertise 10/100 link speed */
11641 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
11642 if (phy->speed_cap_mask &
11643 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11644 an_10_100_val |= (1<<5);
11645 autoneg_val |= (1<<9 | 1<<12);
11646 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
11648 if (phy->speed_cap_mask &
11649 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11650 an_10_100_val |= (1<<6);
11651 autoneg_val |= (1<<9 | 1<<12);
11652 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
11654 if (phy->speed_cap_mask &
11655 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11656 an_10_100_val |= (1<<7);
11657 autoneg_val |= (1<<9 | 1<<12);
11658 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
11660 if (phy->speed_cap_mask &
11661 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11662 an_10_100_val |= (1<<8);
11663 autoneg_val |= (1<<9 | 1<<12);
11664 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
11668 /* Only 10/100 are allowed to work in FORCE mode */
11669 if (phy->req_line_speed == ELINK_SPEED_100) {
11670 autoneg_val |= (1<<13);
11671 /* Enabled AUTO-MDIX when autoneg is disabled */
11672 elink_cl22_write(sc, phy,
11674 (1<<15 | 1<<9 | 7<<0));
11675 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
11677 if (phy->req_line_speed == ELINK_SPEED_10) {
11678 /* Enabled AUTO-MDIX when autoneg is disabled */
11679 elink_cl22_write(sc, phy,
11681 (1<<15 | 1<<9 | 7<<0));
11682 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
11685 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
11688 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
11689 MDIO_REG_GPHY_EXP_ACCESS_TOP |
11690 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11691 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11693 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11695 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11696 if (rc != ELINK_STATUS_OK) {
11697 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11698 elink_eee_disable(phy, params, vars);
11699 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11700 (phy->req_duplex == DUPLEX_FULL) &&
11701 (elink_eee_calc_timer(params) ||
11702 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
11703 /* Need to advertise EEE only when requested,
11704 * and either no LPI assertion was requested,
11705 * or it was requested and a valid timer was set.
11706 * Also notice full duplex is required for EEE.
11708 elink_eee_advertise(phy, params, vars,
11711 ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE\n");
11712 elink_eee_disable(phy, params, vars);
11715 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
11716 SHMEM_EEE_SUPPORTED_SHIFT;
11718 if (phy->flags & ELINK_FLAGS_EEE) {
11719 /* Handle legacy auto-grEEEn */
11720 if (params->feature_config_flags &
11721 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11723 ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn\n");
11726 ELINK_DEBUG_P0(sc, "Don't Adv. EEE\n");
11728 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11729 MDIO_AN_REG_EEE_ADV, temp);
11733 elink_cl22_write(sc, phy,
11735 an_10_100_val | fc_val);
11737 if (phy->req_duplex == DUPLEX_FULL)
11738 autoneg_val |= (1<<8);
11740 elink_cl22_write(sc, phy,
11741 MDIO_PMA_REG_CTRL, autoneg_val);
11743 return ELINK_STATUS_OK;
11747 static void elink_5461x_set_link_led(struct elink_phy *phy,
11748 struct elink_params *params, uint8_t mode)
11750 struct bxe_softc *sc = params->sc;
11753 elink_cl22_write(sc, phy,
11754 MDIO_REG_GPHY_SHADOW,
11755 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11756 elink_cl22_read(sc, phy,
11757 MDIO_REG_GPHY_SHADOW,
11761 ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)\n", mode);
11763 case ELINK_LED_MODE_FRONT_PANEL_OFF:
11764 case ELINK_LED_MODE_OFF:
11767 case ELINK_LED_MODE_OPER:
11770 case ELINK_LED_MODE_ON:
11776 elink_cl22_write(sc, phy,
11777 MDIO_REG_GPHY_SHADOW,
11778 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11783 static void elink_54618se_link_reset(struct elink_phy *phy,
11784 struct elink_params *params)
11786 struct bxe_softc *sc = params->sc;
11790 /* In case of no EPIO routed to reset the GPHY, put it
11791 * in low power mode.
11793 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
11794 /* This works with E3 only, no need to check the chip
11795 * before determining the port.
11797 port = params->port;
11798 cfg_pin = (REG_RD(sc, params->shmem_base +
11799 offsetof(struct shmem_region,
11800 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11801 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11802 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11804 /* Drive pin low to put GPHY in reset. */
11805 elink_set_cfg_pin(sc, cfg_pin, 0);
11808 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
11809 struct elink_params *params,
11810 struct elink_vars *vars)
11812 struct bxe_softc *sc = params->sc;
11814 uint8_t link_up = 0;
11815 uint16_t legacy_status, legacy_speed;
11817 /* Get speed operation status */
11818 elink_cl22_read(sc, phy,
11819 MDIO_REG_GPHY_AUX_STATUS,
11821 ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x\n", legacy_status);
11823 /* Read status to clear the PHY interrupt. */
11824 elink_cl22_read(sc, phy,
11825 MDIO_REG_INTR_STATUS,
11828 link_up = ((legacy_status & (1<<2)) == (1<<2));
11831 legacy_speed = (legacy_status & (7<<8));
11832 if (legacy_speed == (7<<8)) {
11833 vars->line_speed = ELINK_SPEED_1000;
11834 vars->duplex = DUPLEX_FULL;
11835 } else if (legacy_speed == (6<<8)) {
11836 vars->line_speed = ELINK_SPEED_1000;
11837 vars->duplex = DUPLEX_HALF;
11838 } else if (legacy_speed == (5<<8)) {
11839 vars->line_speed = ELINK_SPEED_100;
11840 vars->duplex = DUPLEX_FULL;
11842 /* Omitting 100Base-T4 for now */
11843 else if (legacy_speed == (3<<8)) {
11844 vars->line_speed = ELINK_SPEED_100;
11845 vars->duplex = DUPLEX_HALF;
11846 } else if (legacy_speed == (2<<8)) {
11847 vars->line_speed = ELINK_SPEED_10;
11848 vars->duplex = DUPLEX_FULL;
11849 } else if (legacy_speed == (1<<8)) {
11850 vars->line_speed = ELINK_SPEED_10;
11851 vars->duplex = DUPLEX_HALF;
11852 } else /* Should not happen */
11853 vars->line_speed = 0;
11856 "Link is up in %dMbps, is_duplex_full= %d\n",
11858 (vars->duplex == DUPLEX_FULL));
11860 /* Check legacy speed AN resolution */
11861 elink_cl22_read(sc, phy,
11865 vars->link_status |=
11866 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11867 elink_cl22_read(sc, phy,
11870 if ((val & (1<<0)) == 0)
11871 vars->link_status |=
11872 LINK_STATUS_PARALLEL_DETECTION_USED;
11874 ELINK_DEBUG_P1(sc, "BCM54618SE: link speed is %d\n",
11877 elink_ext_phy_resolve_fc(phy, params, vars);
11879 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11880 /* Report LP advertised speeds */
11881 elink_cl22_read(sc, phy, 0x5, &val);
11884 vars->link_status |=
11885 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11887 vars->link_status |=
11888 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11890 vars->link_status |=
11891 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11893 vars->link_status |=
11894 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11896 vars->link_status |=
11897 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11899 elink_cl22_read(sc, phy, 0xa, &val);
11901 vars->link_status |=
11902 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11904 vars->link_status |=
11905 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11907 if ((phy->flags & ELINK_FLAGS_EEE) &&
11908 elink_eee_has_cap(params))
11909 elink_eee_an_resolve(phy, params, vars);
11915 static void elink_54618se_config_loopback(struct elink_phy *phy,
11916 struct elink_params *params)
11918 struct bxe_softc *sc = params->sc;
11920 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11922 ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se\n");
11924 /* Enable master/slave manual mmode and set to master */
11925 /* mii write 9 [bits set 11 12] */
11926 elink_cl22_write(sc, phy, 0x09, 3<<11);
11928 /* forced 1G and disable autoneg */
11929 /* set val [mii read 0] */
11930 /* set val [expr $val & [bits clear 6 12 13]] */
11931 /* set val [expr $val | [bits set 6 8]] */
11932 /* mii write 0 $val */
11933 elink_cl22_read(sc, phy, 0x00, &val);
11934 val &= ~((1<<6) | (1<<12) | (1<<13));
11935 val |= (1<<6) | (1<<8);
11936 elink_cl22_write(sc, phy, 0x00, val);
11938 /* Set external loopback and Tx using 6dB coding */
11939 /* mii write 0x18 7 */
11940 /* set val [mii read 0x18] */
11941 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11942 elink_cl22_write(sc, phy, 0x18, 7);
11943 elink_cl22_read(sc, phy, 0x18, &val);
11944 elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));
11946 /* This register opens the gate for the UMAC despite its name */
11947 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11949 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11950 * length used by the MAC receive logic to check frames.
11952 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
11955 /******************************************************************/
11956 /* SFX7101 PHY SECTION */
11957 /******************************************************************/
11958 static void elink_7101_config_loopback(struct elink_phy *phy,
11959 struct elink_params *params)
11961 struct bxe_softc *sc = params->sc;
11962 /* SFX7101_XGXS_TEST1 */
11963 elink_cl45_write(sc, phy,
11964 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11967 static elink_status_t elink_7101_config_init(struct elink_phy *phy,
11968 struct elink_params *params,
11969 struct elink_vars *vars)
11971 uint16_t fw_ver1, fw_ver2, val;
11972 struct bxe_softc *sc = params->sc;
11973 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication\n");
11975 /* Restore normal power mode*/
11976 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
11977 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11979 elink_ext_phy_hw_reset(sc, params->port);
11980 elink_wait_reset_complete(sc, phy, params);
11982 elink_cl45_write(sc, phy,
11983 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11984 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic\n");
11985 elink_cl45_write(sc, phy,
11986 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11988 elink_ext_phy_set_pause(params, phy, vars);
11989 /* Restart autoneg */
11990 elink_cl45_read(sc, phy,
11991 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11993 elink_cl45_write(sc, phy,
11994 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11996 /* Save spirom version */
11997 elink_cl45_read(sc, phy,
11998 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
12000 elink_cl45_read(sc, phy,
12001 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
12002 elink_save_spirom_version(sc, params->port,
12003 (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
12004 return ELINK_STATUS_OK;
12007 static uint8_t elink_7101_read_status(struct elink_phy *phy,
12008 struct elink_params *params,
12009 struct elink_vars *vars)
12011 struct bxe_softc *sc = params->sc;
12013 uint16_t val1, val2;
12014 elink_cl45_read(sc, phy,
12015 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
12016 elink_cl45_read(sc, phy,
12017 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
12018 ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x\n",
12020 elink_cl45_read(sc, phy,
12021 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
12022 elink_cl45_read(sc, phy,
12023 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
12024 ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x\n",
12026 link_up = ((val1 & 4) == 4);
12027 /* If link is up print the AN outcome of the SFX7101 PHY */
12029 elink_cl45_read(sc, phy,
12030 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
12032 vars->line_speed = ELINK_SPEED_10000;
12033 vars->duplex = DUPLEX_FULL;
12034 ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x\n",
12035 val2, (val2 & (1<<14)));
12036 elink_ext_phy_10G_an_resolve(sc, phy, vars);
12037 elink_ext_phy_resolve_fc(phy, params, vars);
12039 /* Read LP advertised speeds */
12040 if (val2 & (1<<11))
12041 vars->link_status |=
12042 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
12047 static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
12050 return ELINK_STATUS_ERROR;
12051 str[0] = (spirom_ver & 0xFF);
12052 str[1] = (spirom_ver & 0xFF00) >> 8;
12053 str[2] = (spirom_ver & 0xFF0000) >> 16;
12054 str[3] = (spirom_ver & 0xFF000000) >> 24;
12057 return ELINK_STATUS_OK;
12060 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)
12064 elink_cl45_read(sc, phy,
12066 MDIO_PMA_REG_7101_RESET, &val);
12068 for (cnt = 0; cnt < 10; cnt++) {
12070 /* Writes a self-clearing reset */
12071 elink_cl45_write(sc, phy,
12073 MDIO_PMA_REG_7101_RESET,
12075 /* Wait for clear */
12076 elink_cl45_read(sc, phy,
12078 MDIO_PMA_REG_7101_RESET, &val);
12080 if ((val & (1<<15)) == 0)
12085 static void elink_7101_hw_reset(struct elink_phy *phy,
12086 struct elink_params *params) {
12087 /* Low power mode is controlled by GPIO 2 */
12088 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
12089 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12090 /* The PHY reset is controlled by GPIO 1 */
12091 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
12092 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12095 static void elink_7101_set_link_led(struct elink_phy *phy,
12096 struct elink_params *params, uint8_t mode)
12099 struct bxe_softc *sc = params->sc;
12101 case ELINK_LED_MODE_FRONT_PANEL_OFF:
12102 case ELINK_LED_MODE_OFF:
12105 case ELINK_LED_MODE_ON:
12108 case ELINK_LED_MODE_OPER:
12112 elink_cl45_write(sc, phy,
12114 MDIO_PMA_REG_7107_LINK_LED_CNTL,
12118 /******************************************************************/
12119 /* STATIC PHY DECLARATION */
12120 /******************************************************************/
12122 static const struct elink_phy phy_null = {
12123 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
12126 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12127 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12128 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12131 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12133 .req_flow_ctrl = 0,
12134 .req_line_speed = 0,
12135 .speed_cap_mask = 0,
12138 .config_init = (config_init_t)NULL,
12139 .read_status = (read_status_t)NULL,
12140 .link_reset = (link_reset_t)NULL,
12141 .config_loopback = (config_loopback_t)NULL,
12142 .format_fw_ver = (format_fw_ver_t)NULL,
12143 .hw_reset = (hw_reset_t)NULL,
12144 .set_link_led = (set_link_led_t)NULL,
12145 .phy_specific_func = (phy_specific_func_t)NULL
12148 static const struct elink_phy phy_serdes = {
12149 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
12153 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12154 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12156 .supported = (ELINK_SUPPORTED_10baseT_Half |
12157 ELINK_SUPPORTED_10baseT_Full |
12158 ELINK_SUPPORTED_100baseT_Half |
12159 ELINK_SUPPORTED_100baseT_Full |
12160 ELINK_SUPPORTED_1000baseT_Full |
12161 ELINK_SUPPORTED_2500baseX_Full |
12162 ELINK_SUPPORTED_TP |
12163 ELINK_SUPPORTED_Autoneg |
12164 ELINK_SUPPORTED_Pause |
12165 ELINK_SUPPORTED_Asym_Pause),
12166 .media_type = ELINK_ETH_PHY_BASE_T,
12168 .req_flow_ctrl = 0,
12169 .req_line_speed = 0,
12170 .speed_cap_mask = 0,
12173 .config_init = (config_init_t)elink_xgxs_config_init,
12174 .read_status = (read_status_t)elink_link_settings_status,
12175 .link_reset = (link_reset_t)elink_int_link_reset,
12176 .config_loopback = (config_loopback_t)NULL,
12177 .format_fw_ver = (format_fw_ver_t)NULL,
12178 .hw_reset = (hw_reset_t)NULL,
12179 .set_link_led = (set_link_led_t)NULL,
12180 .phy_specific_func = (phy_specific_func_t)NULL
12183 static const struct elink_phy phy_xgxs = {
12184 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12188 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12189 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12191 .supported = (ELINK_SUPPORTED_10baseT_Half |
12192 ELINK_SUPPORTED_10baseT_Full |
12193 ELINK_SUPPORTED_100baseT_Half |
12194 ELINK_SUPPORTED_100baseT_Full |
12195 ELINK_SUPPORTED_1000baseT_Full |
12196 ELINK_SUPPORTED_2500baseX_Full |
12197 ELINK_SUPPORTED_10000baseT_Full |
12198 ELINK_SUPPORTED_FIBRE |
12199 ELINK_SUPPORTED_Autoneg |
12200 ELINK_SUPPORTED_Pause |
12201 ELINK_SUPPORTED_Asym_Pause),
12202 .media_type = ELINK_ETH_PHY_CX4,
12204 .req_flow_ctrl = 0,
12205 .req_line_speed = 0,
12206 .speed_cap_mask = 0,
12209 .config_init = (config_init_t)elink_xgxs_config_init,
12210 .read_status = (read_status_t)elink_link_settings_status,
12211 .link_reset = (link_reset_t)elink_int_link_reset,
12212 .config_loopback = (config_loopback_t)elink_set_xgxs_loopback,
12213 .format_fw_ver = (format_fw_ver_t)NULL,
12214 .hw_reset = (hw_reset_t)NULL,
12215 .set_link_led = (set_link_led_t)NULL,
12216 .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func
12218 static const struct elink_phy phy_warpcore = {
12219 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12222 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
12223 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12224 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12226 .supported = (ELINK_SUPPORTED_10baseT_Half |
12227 ELINK_SUPPORTED_10baseT_Full |
12228 ELINK_SUPPORTED_100baseT_Half |
12229 ELINK_SUPPORTED_100baseT_Full |
12230 ELINK_SUPPORTED_1000baseT_Full |
12231 ELINK_SUPPORTED_10000baseT_Full |
12232 ELINK_SUPPORTED_20000baseKR2_Full |
12233 ELINK_SUPPORTED_20000baseMLD2_Full |
12234 ELINK_SUPPORTED_FIBRE |
12235 ELINK_SUPPORTED_Autoneg |
12236 ELINK_SUPPORTED_Pause |
12237 ELINK_SUPPORTED_Asym_Pause),
12238 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
12240 .req_flow_ctrl = 0,
12241 .req_line_speed = 0,
12242 .speed_cap_mask = 0,
12243 /* req_duplex = */0,
12245 .config_init = (config_init_t)elink_warpcore_config_init,
12246 .read_status = (read_status_t)elink_warpcore_read_status,
12247 .link_reset = (link_reset_t)elink_warpcore_link_reset,
12248 .config_loopback = (config_loopback_t)elink_set_warpcore_loopback,
12249 .format_fw_ver = (format_fw_ver_t)NULL,
12250 .hw_reset = (hw_reset_t)elink_warpcore_hw_reset,
12251 .set_link_led = (set_link_led_t)NULL,
12252 .phy_specific_func = (phy_specific_func_t)NULL
12256 static const struct elink_phy phy_7101 = {
12257 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
12260 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
12261 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12262 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12264 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12265 ELINK_SUPPORTED_TP |
12266 ELINK_SUPPORTED_Autoneg |
12267 ELINK_SUPPORTED_Pause |
12268 ELINK_SUPPORTED_Asym_Pause),
12269 .media_type = ELINK_ETH_PHY_BASE_T,
12271 .req_flow_ctrl = 0,
12272 .req_line_speed = 0,
12273 .speed_cap_mask = 0,
12276 .config_init = (config_init_t)elink_7101_config_init,
12277 .read_status = (read_status_t)elink_7101_read_status,
12278 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12279 .config_loopback = (config_loopback_t)elink_7101_config_loopback,
12280 .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver,
12281 .hw_reset = (hw_reset_t)elink_7101_hw_reset,
12282 .set_link_led = (set_link_led_t)elink_7101_set_link_led,
12283 .phy_specific_func = (phy_specific_func_t)NULL
12285 static const struct elink_phy phy_8073 = {
12286 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
12290 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12291 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12293 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12294 ELINK_SUPPORTED_2500baseX_Full |
12295 ELINK_SUPPORTED_1000baseT_Full |
12296 ELINK_SUPPORTED_FIBRE |
12297 ELINK_SUPPORTED_Autoneg |
12298 ELINK_SUPPORTED_Pause |
12299 ELINK_SUPPORTED_Asym_Pause),
12300 .media_type = ELINK_ETH_PHY_KR,
12302 .req_flow_ctrl = 0,
12303 .req_line_speed = 0,
12304 .speed_cap_mask = 0,
12307 .config_init = (config_init_t)elink_8073_config_init,
12308 .read_status = (read_status_t)elink_8073_read_status,
12309 .link_reset = (link_reset_t)elink_8073_link_reset,
12310 .config_loopback = (config_loopback_t)NULL,
12311 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12312 .hw_reset = (hw_reset_t)NULL,
12313 .set_link_led = (set_link_led_t)NULL,
12314 .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func
12316 static const struct elink_phy phy_8705 = {
12317 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
12320 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12321 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12322 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12324 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12325 ELINK_SUPPORTED_FIBRE |
12326 ELINK_SUPPORTED_Pause |
12327 ELINK_SUPPORTED_Asym_Pause),
12328 .media_type = ELINK_ETH_PHY_XFP_FIBER,
12330 .req_flow_ctrl = 0,
12331 .req_line_speed = 0,
12332 .speed_cap_mask = 0,
12335 .config_init = (config_init_t)elink_8705_config_init,
12336 .read_status = (read_status_t)elink_8705_read_status,
12337 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12338 .config_loopback = (config_loopback_t)NULL,
12339 .format_fw_ver = (format_fw_ver_t)elink_null_format_ver,
12340 .hw_reset = (hw_reset_t)NULL,
12341 .set_link_led = (set_link_led_t)NULL,
12342 .phy_specific_func = (phy_specific_func_t)NULL
12344 static const struct elink_phy phy_8706 = {
12345 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
12348 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12349 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12350 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12352 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12353 ELINK_SUPPORTED_1000baseT_Full |
12354 ELINK_SUPPORTED_FIBRE |
12355 ELINK_SUPPORTED_Pause |
12356 ELINK_SUPPORTED_Asym_Pause),
12357 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
12359 .req_flow_ctrl = 0,
12360 .req_line_speed = 0,
12361 .speed_cap_mask = 0,
12364 .config_init = (config_init_t)elink_8706_config_init,
12365 .read_status = (read_status_t)elink_8706_read_status,
12366 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12367 .config_loopback = (config_loopback_t)NULL,
12368 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12369 .hw_reset = (hw_reset_t)NULL,
12370 .set_link_led = (set_link_led_t)NULL,
12371 .phy_specific_func = (phy_specific_func_t)NULL
12374 static const struct elink_phy phy_8726 = {
12375 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
12378 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST |
12379 ELINK_FLAGS_TX_ERROR_CHECK),
12380 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12381 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12383 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12384 ELINK_SUPPORTED_1000baseT_Full |
12385 ELINK_SUPPORTED_Autoneg |
12386 ELINK_SUPPORTED_FIBRE |
12387 ELINK_SUPPORTED_Pause |
12388 ELINK_SUPPORTED_Asym_Pause),
12389 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12391 .req_flow_ctrl = 0,
12392 .req_line_speed = 0,
12393 .speed_cap_mask = 0,
12396 .config_init = (config_init_t)elink_8726_config_init,
12397 .read_status = (read_status_t)elink_8726_read_status,
12398 .link_reset = (link_reset_t)elink_8726_link_reset,
12399 .config_loopback = (config_loopback_t)elink_8726_config_loopback,
12400 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12401 .hw_reset = (hw_reset_t)NULL,
12402 .set_link_led = (set_link_led_t)NULL,
12403 .phy_specific_func = (phy_specific_func_t)NULL
12406 static const struct elink_phy phy_8727 = {
12407 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
12410 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12411 ELINK_FLAGS_TX_ERROR_CHECK),
12412 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12413 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12415 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12416 ELINK_SUPPORTED_1000baseT_Full |
12417 ELINK_SUPPORTED_FIBRE |
12418 ELINK_SUPPORTED_Pause |
12419 ELINK_SUPPORTED_Asym_Pause),
12420 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12422 .req_flow_ctrl = 0,
12423 .req_line_speed = 0,
12424 .speed_cap_mask = 0,
12427 .config_init = (config_init_t)elink_8727_config_init,
12428 .read_status = (read_status_t)elink_8727_read_status,
12429 .link_reset = (link_reset_t)elink_8727_link_reset,
12430 .config_loopback = (config_loopback_t)NULL,
12431 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12432 .hw_reset = (hw_reset_t)elink_8727_hw_reset,
12433 .set_link_led = (set_link_led_t)elink_8727_set_link_led,
12434 .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func
12436 static const struct elink_phy phy_8481 = {
12437 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
12440 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12441 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12442 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12443 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12445 .supported = (ELINK_SUPPORTED_10baseT_Half |
12446 ELINK_SUPPORTED_10baseT_Full |
12447 ELINK_SUPPORTED_100baseT_Half |
12448 ELINK_SUPPORTED_100baseT_Full |
12449 ELINK_SUPPORTED_1000baseT_Full |
12450 ELINK_SUPPORTED_10000baseT_Full |
12451 ELINK_SUPPORTED_TP |
12452 ELINK_SUPPORTED_Autoneg |
12453 ELINK_SUPPORTED_Pause |
12454 ELINK_SUPPORTED_Asym_Pause),
12455 .media_type = ELINK_ETH_PHY_BASE_T,
12457 .req_flow_ctrl = 0,
12458 .req_line_speed = 0,
12459 .speed_cap_mask = 0,
12462 .config_init = (config_init_t)elink_8481_config_init,
12463 .read_status = (read_status_t)elink_848xx_read_status,
12464 .link_reset = (link_reset_t)elink_8481_link_reset,
12465 .config_loopback = (config_loopback_t)NULL,
12466 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12467 .hw_reset = (hw_reset_t)elink_8481_hw_reset,
12468 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12469 .phy_specific_func = (phy_specific_func_t)NULL
12472 static const struct elink_phy phy_84823 = {
12473 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
12476 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12477 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12478 ELINK_FLAGS_TX_ERROR_CHECK),
12479 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12480 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12482 .supported = (ELINK_SUPPORTED_10baseT_Half |
12483 ELINK_SUPPORTED_10baseT_Full |
12484 ELINK_SUPPORTED_100baseT_Half |
12485 ELINK_SUPPORTED_100baseT_Full |
12486 ELINK_SUPPORTED_1000baseT_Full |
12487 ELINK_SUPPORTED_10000baseT_Full |
12488 ELINK_SUPPORTED_TP |
12489 ELINK_SUPPORTED_Autoneg |
12490 ELINK_SUPPORTED_Pause |
12491 ELINK_SUPPORTED_Asym_Pause),
12492 .media_type = ELINK_ETH_PHY_BASE_T,
12494 .req_flow_ctrl = 0,
12495 .req_line_speed = 0,
12496 .speed_cap_mask = 0,
12499 .config_init = (config_init_t)elink_848x3_config_init,
12500 .read_status = (read_status_t)elink_848xx_read_status,
12501 .link_reset = (link_reset_t)elink_848x3_link_reset,
12502 .config_loopback = (config_loopback_t)NULL,
12503 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12504 .hw_reset = (hw_reset_t)NULL,
12505 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12506 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12509 static const struct elink_phy phy_84833 = {
12510 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12513 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12514 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12515 ELINK_FLAGS_TX_ERROR_CHECK |
12516 ELINK_FLAGS_TEMPERATURE),
12517 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12518 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12520 .supported = (ELINK_SUPPORTED_100baseT_Half |
12521 ELINK_SUPPORTED_100baseT_Full |
12522 ELINK_SUPPORTED_1000baseT_Full |
12523 ELINK_SUPPORTED_10000baseT_Full |
12524 ELINK_SUPPORTED_TP |
12525 ELINK_SUPPORTED_Autoneg |
12526 ELINK_SUPPORTED_Pause |
12527 ELINK_SUPPORTED_Asym_Pause),
12528 .media_type = ELINK_ETH_PHY_BASE_T,
12530 .req_flow_ctrl = 0,
12531 .req_line_speed = 0,
12532 .speed_cap_mask = 0,
12535 .config_init = (config_init_t)elink_848x3_config_init,
12536 .read_status = (read_status_t)elink_848xx_read_status,
12537 .link_reset = (link_reset_t)elink_848x3_link_reset,
12538 .config_loopback = (config_loopback_t)NULL,
12539 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12540 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12541 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12542 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12545 static const struct elink_phy phy_84834 = {
12546 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12549 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12550 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12551 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12552 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12554 .supported = (ELINK_SUPPORTED_100baseT_Half |
12555 ELINK_SUPPORTED_100baseT_Full |
12556 ELINK_SUPPORTED_1000baseT_Full |
12557 ELINK_SUPPORTED_10000baseT_Full |
12558 ELINK_SUPPORTED_TP |
12559 ELINK_SUPPORTED_Autoneg |
12560 ELINK_SUPPORTED_Pause |
12561 ELINK_SUPPORTED_Asym_Pause),
12562 .media_type = ELINK_ETH_PHY_BASE_T,
12564 .req_flow_ctrl = 0,
12565 .req_line_speed = 0,
12566 .speed_cap_mask = 0,
12569 .config_init = (config_init_t)elink_848x3_config_init,
12570 .read_status = (read_status_t)elink_848xx_read_status,
12571 .link_reset = (link_reset_t)elink_848x3_link_reset,
12572 .config_loopback = (config_loopback_t)NULL,
12573 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12574 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12575 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12576 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12579 static const struct elink_phy phy_54618se = {
12580 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12583 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12584 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12585 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12587 .supported = (ELINK_SUPPORTED_10baseT_Half |
12588 ELINK_SUPPORTED_10baseT_Full |
12589 ELINK_SUPPORTED_100baseT_Half |
12590 ELINK_SUPPORTED_100baseT_Full |
12591 ELINK_SUPPORTED_1000baseT_Full |
12592 ELINK_SUPPORTED_TP |
12593 ELINK_SUPPORTED_Autoneg |
12594 ELINK_SUPPORTED_Pause |
12595 ELINK_SUPPORTED_Asym_Pause),
12596 .media_type = ELINK_ETH_PHY_BASE_T,
12598 .req_flow_ctrl = 0,
12599 .req_line_speed = 0,
12600 .speed_cap_mask = 0,
12601 /* req_duplex = */0,
12603 .config_init = (config_init_t)elink_54618se_config_init,
12604 .read_status = (read_status_t)elink_54618se_read_status,
12605 .link_reset = (link_reset_t)elink_54618se_link_reset,
12606 .config_loopback = (config_loopback_t)elink_54618se_config_loopback,
12607 .format_fw_ver = (format_fw_ver_t)NULL,
12608 .hw_reset = (hw_reset_t)NULL,
12609 .set_link_led = (set_link_led_t)elink_5461x_set_link_led,
12610 .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func
12612 /*****************************************************************/
12614 /* Populate the phy according. Main function: elink_populate_phy */
12616 /*****************************************************************/
12618 static void elink_populate_preemphasis(struct bxe_softc *sc, uint32_t shmem_base,
12619 struct elink_phy *phy, uint8_t port,
12622 /* Get the 4 lanes xgxs config rx and tx */
12623 uint32_t rx = 0, tx = 0, i;
12624 for (i = 0; i < 2; i++) {
12625 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
12626 * the shmem. When num_phys is greater than 1, than this value
12627 * applies only to ELINK_EXT_PHY1
12629 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
12630 rx = REG_RD(sc, shmem_base +
12631 offsetof(struct shmem_region,
12632 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12634 tx = REG_RD(sc, shmem_base +
12635 offsetof(struct shmem_region,
12636 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12638 rx = REG_RD(sc, shmem_base +
12639 offsetof(struct shmem_region,
12640 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12642 tx = REG_RD(sc, shmem_base +
12643 offsetof(struct shmem_region,
12644 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12647 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12648 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12650 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12651 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12655 static uint32_t elink_get_ext_phy_config(struct bxe_softc *sc, uint32_t shmem_base,
12656 uint8_t phy_index, uint8_t port)
12658 uint32_t ext_phy_config = 0;
12659 switch (phy_index) {
12660 case ELINK_EXT_PHY1:
12661 ext_phy_config = REG_RD(sc, shmem_base +
12662 offsetof(struct shmem_region,
12663 dev_info.port_hw_config[port].external_phy_config));
12665 case ELINK_EXT_PHY2:
12666 ext_phy_config = REG_RD(sc, shmem_base +
12667 offsetof(struct shmem_region,
12668 dev_info.port_hw_config[port].external_phy_config2));
12671 ELINK_DEBUG_P1(sc, "Invalid phy_index %d\n", phy_index);
12672 return ELINK_STATUS_ERROR;
12675 return ext_phy_config;
12677 static elink_status_t elink_populate_int_phy(struct bxe_softc *sc, uint32_t shmem_base, uint8_t port,
12678 struct elink_phy *phy)
12682 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
12683 offsetof(struct shmem_region,
12684 dev_info.port_feature_config[port].link_config)) &
12685 PORT_FEATURE_CONNECTED_SWITCH_MASK);
12686 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
12687 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
12689 ELINK_DEBUG_P1(sc, ":chip_id = 0x%x\n", chip_id);
12690 if (USES_WARPCORE(sc)) {
12691 uint32_t serdes_net_if;
12692 phy_addr = REG_RD(sc,
12693 MISC_REG_WC0_CTRL_PHY_ADDR);
12694 *phy = phy_warpcore;
12695 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12696 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
12698 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
12699 /* Check Dual mode */
12700 serdes_net_if = (REG_RD(sc, shmem_base +
12701 offsetof(struct shmem_region, dev_info.
12702 port_hw_config[port].default_cfg)) &
12703 PORT_HW_CFG_NET_SERDES_IF_MASK);
12704 /* Set the appropriate supported and flags indications per
12705 * interface type of the chip
12707 switch (serdes_net_if) {
12708 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
12709 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
12710 ELINK_SUPPORTED_10baseT_Full |
12711 ELINK_SUPPORTED_100baseT_Half |
12712 ELINK_SUPPORTED_100baseT_Full |
12713 ELINK_SUPPORTED_1000baseT_Full |
12714 ELINK_SUPPORTED_FIBRE |
12715 ELINK_SUPPORTED_Autoneg |
12716 ELINK_SUPPORTED_Pause |
12717 ELINK_SUPPORTED_Asym_Pause);
12718 phy->media_type = ELINK_ETH_PHY_BASE_T;
12720 case PORT_HW_CFG_NET_SERDES_IF_XFI:
12721 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12722 ELINK_SUPPORTED_10000baseT_Full |
12723 ELINK_SUPPORTED_FIBRE |
12724 ELINK_SUPPORTED_Pause |
12725 ELINK_SUPPORTED_Asym_Pause);
12726 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
12728 case PORT_HW_CFG_NET_SERDES_IF_SFI:
12729 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12730 ELINK_SUPPORTED_10000baseT_Full |
12731 ELINK_SUPPORTED_FIBRE |
12732 ELINK_SUPPORTED_Pause |
12733 ELINK_SUPPORTED_Asym_Pause);
12734 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
12736 case PORT_HW_CFG_NET_SERDES_IF_KR:
12737 phy->media_type = ELINK_ETH_PHY_KR;
12738 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12739 ELINK_SUPPORTED_10000baseT_Full |
12740 ELINK_SUPPORTED_FIBRE |
12741 ELINK_SUPPORTED_Autoneg |
12742 ELINK_SUPPORTED_Pause |
12743 ELINK_SUPPORTED_Asym_Pause);
12745 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
12746 phy->media_type = ELINK_ETH_PHY_KR;
12747 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
12748 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
12749 ELINK_SUPPORTED_FIBRE |
12750 ELINK_SUPPORTED_Pause |
12751 ELINK_SUPPORTED_Asym_Pause);
12753 case PORT_HW_CFG_NET_SERDES_IF_KR2:
12754 phy->media_type = ELINK_ETH_PHY_KR;
12755 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
12756 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
12757 ELINK_SUPPORTED_10000baseT_Full |
12758 ELINK_SUPPORTED_1000baseT_Full |
12759 ELINK_SUPPORTED_Autoneg |
12760 ELINK_SUPPORTED_FIBRE |
12761 ELINK_SUPPORTED_Pause |
12762 ELINK_SUPPORTED_Asym_Pause);
12763 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
12766 ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x\n",
12771 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
12772 * was not set as expected. For B0, ECO will be enabled so there
12773 * won't be an issue there
12775 if (CHIP_REV(sc) == CHIP_REV_Ax)
12776 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
12778 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
12781 switch (switch_cfg) {
12782 case ELINK_SWITCH_CFG_1G:
12783 phy_addr = REG_RD(sc,
12784 NIG_REG_SERDES0_CTRL_PHY_ADDR +
12788 case ELINK_SWITCH_CFG_10G:
12789 phy_addr = REG_RD(sc,
12790 NIG_REG_XGXS0_CTRL_PHY_ADDR +
12795 ELINK_DEBUG_P0(sc, "Invalid switch_cfg\n");
12796 return ELINK_STATUS_ERROR;
12799 phy->addr = (uint8_t)phy_addr;
12800 phy->mdio_ctrl = elink_get_emac_base(sc,
12801 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12803 if (CHIP_IS_E2(sc))
12804 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
12806 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
12808 ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12809 port, phy->addr, phy->mdio_ctrl);
12811 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
12812 return ELINK_STATUS_OK;
12815 static elink_status_t elink_populate_ext_phy(struct bxe_softc *sc,
12817 uint32_t shmem_base,
12818 uint32_t shmem2_base,
12820 struct elink_phy *phy)
12822 uint32_t ext_phy_config, phy_type, config2;
12823 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12824 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
12826 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
12827 /* Select the phy type */
12828 switch (phy_type) {
12829 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12830 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12833 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12836 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12839 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12840 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12843 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12844 /* BCM8727_NOC => BCM8727 no over current */
12845 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12847 phy->flags |= ELINK_FLAGS_NOC;
12849 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12850 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12851 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12854 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12857 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12860 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12863 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12866 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12867 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12868 *phy = phy_54618se;
12869 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12870 phy->flags |= ELINK_FLAGS_EEE;
12872 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12875 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12877 return ELINK_STATUS_ERROR;
12880 /* In case external PHY wasn't found */
12881 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12882 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12883 return ELINK_STATUS_ERROR;
12884 return ELINK_STATUS_OK;
12887 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
12888 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
12890 /* The shmem address of the phy version is located on different
12891 * structures. In case this structure is too old, do not set
12894 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
12895 dev_info.shared_hw_config.config2));
12896 if (phy_index == ELINK_EXT_PHY1) {
12897 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12898 port_mb[port].ext_phy_fw_version);
12900 /* Check specific mdc mdio settings */
12901 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12902 mdc_mdio_access = config2 &
12903 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12905 uint32_t size = REG_RD(sc, shmem2_base);
12908 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12909 phy->ver_addr = shmem2_base +
12910 offsetof(struct shmem2_region,
12911 ext_phy_fw_version2[port]);
12913 /* Check specific mdc mdio settings */
12914 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12915 mdc_mdio_access = (config2 &
12916 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12917 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12918 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12920 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
12922 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12923 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12925 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12926 * version lower than or equal to 1.39
12928 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
12929 if (((raw_ver & 0x7F) <= 39) &&
12930 (((raw_ver & 0xF80) >> 7) <= 1))
12931 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
12932 ELINK_SUPPORTED_100baseT_Full);
12935 ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d\n",
12936 phy_type, port, phy_index);
12937 ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x\n",
12938 phy->addr, phy->mdio_ctrl);
12939 return ELINK_STATUS_OK;
12942 static elink_status_t elink_populate_phy(struct bxe_softc *sc, uint8_t phy_index, uint32_t shmem_base,
12943 uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)
12945 elink_status_t status = ELINK_STATUS_OK;
12946 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12947 if (phy_index == ELINK_INT_PHY)
12948 return elink_populate_int_phy(sc, shmem_base, port, phy);
12949 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
12954 static void elink_phy_def_cfg(struct elink_params *params,
12955 struct elink_phy *phy,
12958 struct bxe_softc *sc = params->sc;
12959 uint32_t link_config;
12960 /* Populate the default phy configuration for MF mode */
12961 if (phy_index == ELINK_EXT_PHY2) {
12962 link_config = REG_RD(sc, params->shmem_base +
12963 offsetof(struct shmem_region, dev_info.
12964 port_feature_config[params->port].link_config2));
12965 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
12966 offsetof(struct shmem_region,
12968 port_hw_config[params->port].speed_capability_mask2));
12970 link_config = REG_RD(sc, params->shmem_base +
12971 offsetof(struct shmem_region, dev_info.
12972 port_feature_config[params->port].link_config));
12973 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
12974 offsetof(struct shmem_region,
12976 port_hw_config[params->port].speed_capability_mask));
12979 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12980 phy_index, link_config, phy->speed_cap_mask);
12982 phy->req_duplex = DUPLEX_FULL;
12983 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12984 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12985 phy->req_duplex = DUPLEX_HALF;
12986 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12987 phy->req_line_speed = ELINK_SPEED_10;
12989 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12990 phy->req_duplex = DUPLEX_HALF;
12991 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12992 phy->req_line_speed = ELINK_SPEED_100;
12994 case PORT_FEATURE_LINK_SPEED_1G:
12995 phy->req_line_speed = ELINK_SPEED_1000;
12997 case PORT_FEATURE_LINK_SPEED_2_5G:
12998 phy->req_line_speed = ELINK_SPEED_2500;
13000 case PORT_FEATURE_LINK_SPEED_10G_CX4:
13001 phy->req_line_speed = ELINK_SPEED_10000;
13004 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
13008 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
13009 case PORT_FEATURE_FLOW_CONTROL_AUTO:
13010 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
13012 case PORT_FEATURE_FLOW_CONTROL_TX:
13013 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
13015 case PORT_FEATURE_FLOW_CONTROL_RX:
13016 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
13018 case PORT_FEATURE_FLOW_CONTROL_BOTH:
13019 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
13022 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
13027 uint32_t elink_phy_selection(struct elink_params *params)
13029 uint32_t phy_config_swapped, prio_cfg;
13030 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
13032 phy_config_swapped = params->multi_phy_config &
13033 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13035 prio_cfg = params->multi_phy_config &
13036 PORT_HW_CFG_PHY_SELECTION_MASK;
13038 if (phy_config_swapped) {
13039 switch (prio_cfg) {
13040 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
13041 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
13043 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
13044 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
13046 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
13047 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
13049 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
13050 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
13054 return_cfg = prio_cfg;
13059 elink_status_t elink_phy_probe(struct elink_params *params)
13061 uint8_t phy_index, actual_phy_idx;
13062 uint32_t phy_config_swapped, sync_offset, media_types;
13063 struct bxe_softc *sc = params->sc;
13064 struct elink_phy *phy;
13065 params->num_phys = 0;
13066 ELINK_DEBUG_P0(sc, "Begin phy probe\n");
13067 #ifdef ELINK_INCLUDE_EMUL
13068 if (CHIP_REV_IS_EMUL(sc))
13069 return ELINK_STATUS_OK;
13071 phy_config_swapped = params->multi_phy_config &
13072 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13074 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
13076 actual_phy_idx = phy_index;
13077 if (phy_config_swapped) {
13078 if (phy_index == ELINK_EXT_PHY1)
13079 actual_phy_idx = ELINK_EXT_PHY2;
13080 else if (phy_index == ELINK_EXT_PHY2)
13081 actual_phy_idx = ELINK_EXT_PHY1;
13083 ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x,"
13084 " actual_phy_idx %x\n", phy_config_swapped,
13085 phy_index, actual_phy_idx);
13086 phy = ¶ms->phy[actual_phy_idx];
13087 if (elink_populate_phy(sc, phy_index, params->shmem_base,
13088 params->shmem2_base, params->port,
13089 phy) != ELINK_STATUS_OK) {
13090 params->num_phys = 0;
13091 ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d\n",
13093 for (phy_index = ELINK_INT_PHY;
13094 phy_index < ELINK_MAX_PHYS;
13097 return ELINK_STATUS_ERROR;
13099 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
13102 if (params->feature_config_flags &
13103 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
13104 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13106 if (!(params->feature_config_flags &
13107 ELINK_FEATURE_CONFIG_MT_SUPPORT))
13108 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
13110 sync_offset = params->shmem_base +
13111 offsetof(struct shmem_region,
13112 dev_info.port_hw_config[params->port].media_type);
13113 media_types = REG_RD(sc, sync_offset);
13115 /* Update media type for non-PMF sync only for the first time
13116 * In case the media type changes afterwards, it will be updated
13117 * using the update_status function
13119 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
13120 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13121 actual_phy_idx))) == 0) {
13122 media_types |= ((phy->media_type &
13123 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
13124 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13127 REG_WR(sc, sync_offset, media_types);
13129 elink_phy_def_cfg(params, phy, phy_index);
13130 params->num_phys++;
13133 ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x\n", params->num_phys);
13134 return ELINK_STATUS_OK;
13137 #ifdef ELINK_INCLUDE_EMUL
13138 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
13139 struct elink_vars *vars)
13141 struct bxe_softc *sc = params->sc;
13142 vars->line_speed = params->req_line_speed[0];
13143 /* In case link speed is auto, set speed the highest as possible */
13144 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
13145 if (params->feature_config_flags &
13146 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
13147 vars->line_speed = ELINK_SPEED_2500;
13148 else if (elink_is_4_port_mode(sc))
13149 vars->line_speed = ELINK_SPEED_10000;
13151 vars->line_speed = ELINK_SPEED_20000;
13153 if (vars->line_speed < ELINK_SPEED_10000) {
13154 if ((params->feature_config_flags &
13155 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
13156 ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is"
13157 " disabled!\n", params->req_line_speed[0]);
13158 return ELINK_STATUS_ERROR;
13160 switch (vars->line_speed) {
13161 case ELINK_SPEED_10:
13162 vars->link_status = ELINK_LINK_10TFD;
13164 case ELINK_SPEED_100:
13165 vars->link_status = ELINK_LINK_100TXFD;
13167 case ELINK_SPEED_1000:
13168 vars->link_status = ELINK_LINK_1000TFD;
13170 case ELINK_SPEED_2500:
13171 vars->link_status = ELINK_LINK_2500TFD;
13174 ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC\n",
13176 return ELINK_STATUS_ERROR;
13178 vars->link_status |= LINK_STATUS_LINK_UP;
13180 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13181 elink_umac_enable(params, vars, 1);
13183 elink_umac_enable(params, vars, 0);
13185 /* Link speed >= 10000 requires XMAC enabled */
13186 if (params->feature_config_flags &
13187 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
13188 ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is"
13189 " disabled!\n", params->req_line_speed[0]);
13190 return ELINK_STATUS_ERROR;
13192 /* Check link speed */
13193 switch (vars->line_speed) {
13194 case ELINK_SPEED_10000:
13195 vars->link_status = ELINK_LINK_10GTFD;
13197 case ELINK_SPEED_20000:
13198 vars->link_status = ELINK_LINK_20GTFD;
13201 ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC\n",
13203 return ELINK_STATUS_ERROR;
13205 vars->link_status |= LINK_STATUS_LINK_UP;
13206 if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
13207 elink_xmac_enable(params, vars, 1);
13209 elink_xmac_enable(params, vars, 0);
13211 return ELINK_STATUS_OK;
13214 static elink_status_t elink_init_emul(struct elink_params *params,
13215 struct elink_vars *vars)
13217 struct bxe_softc *sc = params->sc;
13218 if (CHIP_IS_E3(sc)) {
13219 if (elink_init_e3_emul_mac(params, vars) !=
13221 return ELINK_STATUS_ERROR;
13223 if (params->feature_config_flags &
13224 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
13225 vars->line_speed = ELINK_SPEED_1000;
13226 vars->link_status = (LINK_STATUS_LINK_UP |
13227 ELINK_LINK_1000XFD);
13228 if (params->loopback_mode ==
13229 ELINK_LOOPBACK_EMAC)
13230 elink_emac_enable(params, vars, 1);
13232 elink_emac_enable(params, vars, 0);
13234 vars->line_speed = ELINK_SPEED_10000;
13235 vars->link_status = (LINK_STATUS_LINK_UP |
13236 ELINK_LINK_10GTFD);
13237 if (params->loopback_mode ==
13238 ELINK_LOOPBACK_BMAC)
13239 elink_bmac_enable(params, vars, 1, 1);
13241 elink_bmac_enable(params, vars, 0, 1);
13245 vars->duplex = DUPLEX_FULL;
13246 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13248 if (CHIP_IS_E1x(sc))
13249 elink_pbf_update(params, vars->flow_ctrl,
13251 /* Disable drain */
13252 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13254 /* update shared memory */
13255 elink_update_mng(params, vars->link_status);
13256 return ELINK_STATUS_OK;
13259 #ifdef ELINK_INCLUDE_FPGA
13260 static elink_status_t elink_init_fpga(struct elink_params *params,
13261 struct elink_vars *vars)
13263 /* Enable on E1.5 FPGA */
13264 struct bxe_softc *sc = params->sc;
13265 vars->duplex = DUPLEX_FULL;
13266 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13267 if (!(CHIP_IS_E1(sc))) {
13268 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX |
13269 ELINK_FLOW_CTRL_RX);
13270 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
13271 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
13273 if (CHIP_IS_E3(sc)) {
13274 vars->line_speed = params->req_line_speed[0];
13275 switch (vars->line_speed) {
13276 case ELINK_SPEED_AUTO_NEG:
13277 vars->line_speed = ELINK_SPEED_2500;
13278 case ELINK_SPEED_2500:
13279 vars->link_status = ELINK_LINK_2500TFD;
13281 case ELINK_SPEED_1000:
13282 vars->link_status = ELINK_LINK_1000XFD;
13284 case ELINK_SPEED_100:
13285 vars->link_status = ELINK_LINK_100TXFD;
13287 case ELINK_SPEED_10:
13288 vars->link_status = ELINK_LINK_10TFD;
13291 ELINK_DEBUG_P1(sc, "Invalid link speed %d\n",
13292 params->req_line_speed[0]);
13293 return ELINK_STATUS_ERROR;
13295 vars->link_status |= LINK_STATUS_LINK_UP;
13296 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13297 elink_umac_enable(params, vars, 1);
13299 elink_umac_enable(params, vars, 0);
13301 vars->line_speed = ELINK_SPEED_10000;
13302 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
13303 if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
13304 elink_emac_enable(params, vars, 1);
13306 elink_emac_enable(params, vars, 0);
13310 if (CHIP_IS_E1x(sc))
13311 elink_pbf_update(params, vars->flow_ctrl,
13313 /* Disable drain */
13314 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13316 /* Update shared memory */
13317 elink_update_mng(params, vars->link_status);
13318 return ELINK_STATUS_OK;
13321 static void elink_init_bmac_loopback(struct elink_params *params,
13322 struct elink_vars *vars)
13324 struct bxe_softc *sc = params->sc;
13326 vars->line_speed = ELINK_SPEED_10000;
13327 vars->duplex = DUPLEX_FULL;
13328 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13329 vars->mac_type = ELINK_MAC_TYPE_BMAC;
13331 vars->phy_flags = PHY_XGXS_FLAG;
13333 elink_xgxs_deassert(params);
13335 /* Set bmac loopback */
13336 elink_bmac_enable(params, vars, 1, 1);
13338 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13341 static void elink_init_emac_loopback(struct elink_params *params,
13342 struct elink_vars *vars)
13344 struct bxe_softc *sc = params->sc;
13346 vars->line_speed = ELINK_SPEED_1000;
13347 vars->duplex = DUPLEX_FULL;
13348 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13349 vars->mac_type = ELINK_MAC_TYPE_EMAC;
13351 vars->phy_flags = PHY_XGXS_FLAG;
13353 elink_xgxs_deassert(params);
13354 /* Set bmac loopback */
13355 elink_emac_enable(params, vars, 1);
13356 elink_emac_program(params, vars);
13357 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13360 static void elink_init_xmac_loopback(struct elink_params *params,
13361 struct elink_vars *vars)
13363 struct bxe_softc *sc = params->sc;
13365 if (!params->req_line_speed[0])
13366 vars->line_speed = ELINK_SPEED_10000;
13368 vars->line_speed = params->req_line_speed[0];
13369 vars->duplex = DUPLEX_FULL;
13370 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13371 vars->mac_type = ELINK_MAC_TYPE_XMAC;
13372 vars->phy_flags = PHY_XGXS_FLAG;
13373 /* Set WC to loopback mode since link is required to provide clock
13374 * to the XMAC in 20G mode
13376 elink_set_aer_mmd(params, ¶ms->phy[0]);
13377 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
13378 params->phy[ELINK_INT_PHY].config_loopback(
13379 ¶ms->phy[ELINK_INT_PHY],
13382 elink_xmac_enable(params, vars, 1);
13383 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13386 static void elink_init_umac_loopback(struct elink_params *params,
13387 struct elink_vars *vars)
13389 struct bxe_softc *sc = params->sc;
13391 vars->line_speed = ELINK_SPEED_1000;
13392 vars->duplex = DUPLEX_FULL;
13393 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13394 vars->mac_type = ELINK_MAC_TYPE_UMAC;
13395 vars->phy_flags = PHY_XGXS_FLAG;
13396 elink_umac_enable(params, vars, 1);
13398 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13401 static void elink_init_xgxs_loopback(struct elink_params *params,
13402 struct elink_vars *vars)
13404 struct bxe_softc *sc = params->sc;
13405 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
13407 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13408 vars->duplex = DUPLEX_FULL;
13409 if (params->req_line_speed[0] == ELINK_SPEED_1000)
13410 vars->line_speed = ELINK_SPEED_1000;
13411 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
13412 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
13413 vars->line_speed = ELINK_SPEED_20000;
13415 vars->line_speed = ELINK_SPEED_10000;
13417 if (!USES_WARPCORE(sc))
13418 elink_xgxs_deassert(params);
13419 elink_link_initialize(params, vars);
13421 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
13422 if (USES_WARPCORE(sc))
13423 elink_umac_enable(params, vars, 0);
13425 elink_emac_program(params, vars);
13426 elink_emac_enable(params, vars, 0);
13429 if (USES_WARPCORE(sc))
13430 elink_xmac_enable(params, vars, 0);
13432 elink_bmac_enable(params, vars, 0, 1);
13435 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
13436 /* Set 10G XGXS loopback */
13437 int_phy->config_loopback(int_phy, params);
13439 /* Set external phy loopback */
13441 for (phy_index = ELINK_EXT_PHY1;
13442 phy_index < params->num_phys; phy_index++)
13443 if (params->phy[phy_index].config_loopback)
13444 params->phy[phy_index].config_loopback(
13445 ¶ms->phy[phy_index],
13448 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13450 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
13453 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
13455 struct bxe_softc *sc = params->sc;
13456 uint8_t val = en * 0x1F;
13458 /* Open / close the gate between the NIG and the BRB */
13459 if (!CHIP_IS_E1x(sc))
13461 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
13463 if (!CHIP_IS_E1(sc)) {
13464 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
13468 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
13469 NIG_REG_LLH0_BRB1_NOT_MCP), en);
13471 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
13472 struct elink_vars *vars)
13475 uint32_t dont_clear_stat, lfa_sts;
13476 struct bxe_softc *sc = params->sc;
13478 /* Sync the link parameters */
13479 elink_link_status_update(params, vars);
13482 * The module verification was already done by previous link owner,
13483 * so this call is meant only to get warning message
13486 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
13487 struct elink_phy *phy = ¶ms->phy[phy_idx];
13488 if (phy->phy_specific_func) {
13489 ELINK_DEBUG_P0(sc, "Calling PHY specific func\n");
13490 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
13492 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
13493 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
13494 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
13495 elink_verify_sfp_module(phy, params);
13497 lfa_sts = REG_RD(sc, params->lfa_base +
13498 offsetof(struct shmem_lfa,
13501 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
13503 /* Re-enable the NIG/MAC */
13504 if (CHIP_IS_E3(sc)) {
13505 if (!dont_clear_stat) {
13506 REG_WR(sc, GRCBASE_MISC +
13507 MISC_REGISTERS_RESET_REG_2_CLEAR,
13508 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13510 REG_WR(sc, GRCBASE_MISC +
13511 MISC_REGISTERS_RESET_REG_2_SET,
13512 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13515 if (vars->line_speed < ELINK_SPEED_10000)
13516 elink_umac_enable(params, vars, 0);
13518 elink_xmac_enable(params, vars, 0);
13520 if (vars->line_speed < ELINK_SPEED_10000)
13521 elink_emac_enable(params, vars, 0);
13523 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
13526 /* Increment LFA count */
13527 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
13528 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
13529 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
13530 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
13531 /* Clear link flap reason */
13532 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13534 REG_WR(sc, params->lfa_base +
13535 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13537 /* Disable NIG DRAIN */
13538 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13540 /* Enable interrupts */
13541 elink_link_int_enable(params);
13542 return ELINK_STATUS_OK;
13545 static void elink_cannot_avoid_link_flap(struct elink_params *params,
13546 struct elink_vars *vars,
13549 uint32_t lfa_sts, cfg_idx, tmp_val;
13550 struct bxe_softc *sc = params->sc;
13552 elink_link_reset(params, vars, 1);
13554 if (!params->lfa_base)
13556 /* Store the new link parameters */
13557 REG_WR(sc, params->lfa_base +
13558 offsetof(struct shmem_lfa, req_duplex),
13559 params->req_duplex[0] | (params->req_duplex[1] << 16));
13561 REG_WR(sc, params->lfa_base +
13562 offsetof(struct shmem_lfa, req_flow_ctrl),
13563 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
13565 REG_WR(sc, params->lfa_base +
13566 offsetof(struct shmem_lfa, req_line_speed),
13567 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
13569 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
13570 REG_WR(sc, params->lfa_base +
13571 offsetof(struct shmem_lfa,
13572 speed_cap_mask[cfg_idx]),
13573 params->speed_cap_mask[cfg_idx]);
13576 tmp_val = REG_RD(sc, params->lfa_base +
13577 offsetof(struct shmem_lfa, additional_config));
13578 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
13579 tmp_val |= params->req_fc_auto_adv;
13581 REG_WR(sc, params->lfa_base +
13582 offsetof(struct shmem_lfa, additional_config), tmp_val);
13584 lfa_sts = REG_RD(sc, params->lfa_base +
13585 offsetof(struct shmem_lfa, lfa_sts));
13587 /* Clear the "Don't Clear Statistics" bit, and set reason */
13588 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
13590 /* Set link flap reason */
13591 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13592 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
13593 LFA_LINK_FLAP_REASON_OFFSET);
13595 /* Increment link flap counter */
13596 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
13597 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
13598 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
13599 << LINK_FLAP_COUNT_OFFSET));
13600 REG_WR(sc, params->lfa_base +
13601 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13602 /* Proceed with regular link initialization */
13605 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars)
13608 struct bxe_softc *sc = params->sc;
13609 ELINK_DEBUG_P0(sc, "Phy Initialization started\n");
13610 ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d\n",
13611 params->req_line_speed[0], params->req_flow_ctrl[0]);
13612 ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d\n",
13613 params->req_line_speed[1], params->req_flow_ctrl[1]);
13614 ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
13615 vars->link_status = 0;
13616 vars->phy_link_up = 0;
13618 vars->line_speed = 0;
13619 vars->duplex = DUPLEX_FULL;
13620 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13621 vars->mac_type = ELINK_MAC_TYPE_NONE;
13622 vars->phy_flags = 0;
13623 vars->check_kr2_recovery_cnt = 0;
13624 params->link_flags = ELINK_PHY_INITIALIZED;
13625 /* Driver opens NIG-BRB filters */
13626 elink_set_rx_filter(params, 1);
13627 /* Check if link flap can be avoided */
13628 lfa_status = elink_check_lfa(params);
13630 if (lfa_status == 0) {
13631 ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress\n");
13632 return elink_avoid_link_flap(params, vars);
13635 ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x\n",
13637 elink_cannot_avoid_link_flap(params, vars, lfa_status);
13639 /* Disable attentions */
13640 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13641 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13642 ELINK_NIG_MASK_XGXS0_LINK10G |
13643 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13644 ELINK_NIG_MASK_MI_INT));
13645 #ifdef ELINK_INCLUDE_EMUL
13646 if (!(params->feature_config_flags &
13647 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
13650 elink_emac_init(params, vars);
13652 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
13653 vars->link_status |= LINK_STATUS_PFC_ENABLED;
13655 if ((params->num_phys == 0) &&
13656 !CHIP_REV_IS_SLOW(sc)) {
13657 ELINK_DEBUG_P0(sc, "No phy found for initialization !!\n");
13658 return ELINK_STATUS_ERROR;
13660 set_phy_vars(params, vars);
13662 ELINK_DEBUG_P1(sc, "Num of phys on board: %d\n", params->num_phys);
13663 #ifdef ELINK_INCLUDE_FPGA
13664 if (CHIP_REV_IS_FPGA(sc)) {
13665 return elink_init_fpga(params, vars);
13668 #ifdef ELINK_INCLUDE_EMUL
13669 if (CHIP_REV_IS_EMUL(sc)) {
13670 return elink_init_emul(params, vars);
13673 switch (params->loopback_mode) {
13674 case ELINK_LOOPBACK_BMAC:
13675 elink_init_bmac_loopback(params, vars);
13677 case ELINK_LOOPBACK_EMAC:
13678 elink_init_emac_loopback(params, vars);
13680 case ELINK_LOOPBACK_XMAC:
13681 elink_init_xmac_loopback(params, vars);
13683 case ELINK_LOOPBACK_UMAC:
13684 elink_init_umac_loopback(params, vars);
13686 case ELINK_LOOPBACK_XGXS:
13687 case ELINK_LOOPBACK_EXT_PHY:
13688 elink_init_xgxs_loopback(params, vars);
13691 if (!CHIP_IS_E3(sc)) {
13692 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
13693 elink_xgxs_deassert(params);
13695 elink_serdes_deassert(sc, params->port);
13697 elink_link_initialize(params, vars);
13699 elink_link_int_enable(params);
13702 elink_update_mng(params, vars->link_status);
13704 elink_update_mng_eee(params, vars->eee_status);
13705 return ELINK_STATUS_OK;
13708 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
13709 uint8_t reset_ext_phy)
13711 struct bxe_softc *sc = params->sc;
13712 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
13713 ELINK_DEBUG_P1(sc, "Resetting the link of port %d\n", port);
13714 /* Disable attentions */
13715 vars->link_status = 0;
13716 elink_update_mng(params, vars->link_status);
13717 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
13718 SHMEM_EEE_ACTIVE_BIT);
13719 elink_update_mng_eee(params, vars->eee_status);
13720 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
13721 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13722 ELINK_NIG_MASK_XGXS0_LINK10G |
13723 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13724 ELINK_NIG_MASK_MI_INT));
13726 /* Activate nig drain */
13727 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
13729 /* Disable nig egress interface */
13730 if (!CHIP_IS_E3(sc)) {
13731 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0);
13732 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
13735 #ifdef ELINK_INCLUDE_EMUL
13736 /* Stop BigMac rx */
13737 if (!(params->feature_config_flags &
13738 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
13740 if (!CHIP_IS_E3(sc))
13741 elink_set_bmac_rx(sc, params->chip_id, port, 0);
13742 #ifdef ELINK_INCLUDE_EMUL
13743 /* Stop XMAC/UMAC rx */
13744 if (!(params->feature_config_flags &
13745 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
13747 if (CHIP_IS_E3(sc) &&
13748 !CHIP_REV_IS_FPGA(sc)) {
13749 elink_set_xmac_rxtx(params, 0);
13750 elink_set_umac_rxtx(params, 0);
13753 if (!CHIP_IS_E3(sc))
13754 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
13757 /* The PHY reset is controlled by GPIO 1
13758 * Hold it as vars low
13760 /* Clear link led */
13761 elink_set_mdio_emac_per_phy(sc, params);
13762 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
13764 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
13765 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
13767 if (params->phy[phy_index].link_reset) {
13768 elink_set_aer_mmd(params,
13769 ¶ms->phy[phy_index]);
13770 params->phy[phy_index].link_reset(
13771 ¶ms->phy[phy_index],
13774 if (params->phy[phy_index].flags &
13775 ELINK_FLAGS_REARM_LATCH_SIGNAL)
13776 clear_latch_ind = 1;
13780 if (clear_latch_ind) {
13781 /* Clear latching indication */
13782 elink_rearm_latch_signal(sc, port, 0);
13783 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port*4,
13784 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
13786 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
13787 if (!CHIP_REV_IS_SLOW(sc))
13789 if (params->phy[ELINK_INT_PHY].link_reset)
13790 params->phy[ELINK_INT_PHY].link_reset(
13791 ¶ms->phy[ELINK_INT_PHY], params);
13793 /* Disable nig ingress interface */
13794 if (!CHIP_IS_E3(sc)) {
13796 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
13797 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
13798 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0);
13799 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0);
13801 uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13802 elink_set_xumac_nig(params, 0, 0);
13803 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
13804 MISC_REGISTERS_RESET_REG_2_XMAC)
13805 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
13806 XMAC_CTRL_REG_SOFT_RESET);
13809 vars->phy_flags = 0;
13810 return ELINK_STATUS_OK;
13812 elink_status_t elink_lfa_reset(struct elink_params *params,
13813 struct elink_vars *vars)
13815 struct bxe_softc *sc = params->sc;
13817 vars->phy_flags = 0;
13818 params->link_flags &= ~ELINK_PHY_INITIALIZED;
13819 if (!params->lfa_base)
13820 return elink_link_reset(params, vars, 1);
13822 * Activate NIG drain so that during this time the device won't send
13823 * anything while it is unable to response.
13825 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13828 * Close gracefully the gate from BMAC to NIG such that no half packets
13831 if (!CHIP_IS_E3(sc))
13832 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
13834 if (CHIP_IS_E3(sc)) {
13835 elink_set_xmac_rxtx(params, 0);
13836 elink_set_umac_rxtx(params, 0);
13838 /* Wait 10ms for the pipe to clean up*/
13841 /* Clean the NIG-BRB using the network filters in a way that will
13842 * not cut a packet in the middle.
13844 elink_set_rx_filter(params, 0);
13847 * Re-open the gate between the BMAC and the NIG, after verifying the
13848 * gate to the BRB is closed, otherwise packets may arrive to the
13849 * firmware before driver had initialized it. The target is to achieve
13850 * minimum management protocol down time.
13852 if (!CHIP_IS_E3(sc))
13853 elink_set_bmac_rx(sc, params->chip_id, params->port, 1);
13855 if (CHIP_IS_E3(sc)) {
13856 elink_set_xmac_rxtx(params, 1);
13857 elink_set_umac_rxtx(params, 1);
13859 /* Disable NIG drain */
13860 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13861 return ELINK_STATUS_OK;
13864 /****************************************************************************/
13865 /* Common function */
13866 /****************************************************************************/
13867 static elink_status_t elink_8073_common_init_phy(struct bxe_softc *sc,
13868 uint32_t shmem_base_path[],
13869 uint32_t shmem2_base_path[], uint8_t phy_index,
13872 struct elink_phy phy[PORT_MAX];
13873 struct elink_phy *phy_blk[PORT_MAX];
13876 int8_t port_of_path = 0;
13877 uint32_t swap_val, swap_override;
13878 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13879 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
13880 port ^= (swap_val && swap_override);
13881 elink_ext_phy_hw_reset(sc, port);
13882 /* PART1 - Reset both phys */
13883 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13884 uint32_t shmem_base, shmem2_base;
13885 /* In E2, same phy is using for port0 of the two paths */
13886 if (CHIP_IS_E1x(sc)) {
13887 shmem_base = shmem_base_path[0];
13888 shmem2_base = shmem2_base_path[0];
13889 port_of_path = port;
13891 shmem_base = shmem_base_path[port];
13892 shmem2_base = shmem2_base_path[port];
13896 /* Extract the ext phy address for the port */
13897 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
13898 port_of_path, &phy[port]) !=
13900 ELINK_DEBUG_P0(sc, "populate_phy failed\n");
13901 return ELINK_STATUS_ERROR;
13903 /* Disable attentions */
13904 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
13906 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13907 ELINK_NIG_MASK_XGXS0_LINK10G |
13908 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13909 ELINK_NIG_MASK_MI_INT));
13911 /* Need to take the phy out of low power mode in order
13912 * to write to access its registers
13914 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
13915 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13918 /* Reset the phy */
13919 elink_cl45_write(sc, &phy[port],
13925 /* Add delay of 150ms after reset */
13928 if (phy[PORT_0].addr & 0x1) {
13929 phy_blk[PORT_0] = &(phy[PORT_1]);
13930 phy_blk[PORT_1] = &(phy[PORT_0]);
13932 phy_blk[PORT_0] = &(phy[PORT_0]);
13933 phy_blk[PORT_1] = &(phy[PORT_1]);
13936 /* PART2 - Download firmware to both phys */
13937 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13938 if (CHIP_IS_E1x(sc))
13939 port_of_path = port;
13943 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
13944 phy_blk[port]->addr);
13945 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
13947 return ELINK_STATUS_ERROR;
13949 /* Only set bit 10 = 1 (Tx power down) */
13950 elink_cl45_read(sc, phy_blk[port],
13952 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13954 /* Phase1 of TX_POWER_DOWN reset */
13955 elink_cl45_write(sc, phy_blk[port],
13957 MDIO_PMA_REG_TX_POWER_DOWN,
13961 /* Toggle Transmitter: Power down and then up with 600ms delay
13966 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
13967 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13968 /* Phase2 of POWER_DOWN_RESET */
13969 /* Release bit 10 (Release Tx power down) */
13970 elink_cl45_read(sc, phy_blk[port],
13972 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13974 elink_cl45_write(sc, phy_blk[port],
13976 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13979 /* Read modify write the SPI-ROM version select register */
13980 elink_cl45_read(sc, phy_blk[port],
13982 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13983 elink_cl45_write(sc, phy_blk[port],
13985 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
13987 /* set GPIO2 back to LOW */
13988 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
13989 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
13991 return ELINK_STATUS_OK;
13993 static elink_status_t elink_8726_common_init_phy(struct bxe_softc *sc,
13994 uint32_t shmem_base_path[],
13995 uint32_t shmem2_base_path[], uint8_t phy_index,
14000 struct elink_phy phy;
14001 /* Use port1 because of the static port-swap */
14002 /* Enable the module detection interrupt */
14003 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14004 val |= ((1<<MISC_REGISTERS_GPIO_3)|
14005 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
14006 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
14008 elink_ext_phy_hw_reset(sc, 0);
14010 for (port = 0; port < PORT_MAX; port++) {
14011 uint32_t shmem_base, shmem2_base;
14013 /* In E2, same phy is using for port0 of the two paths */
14014 if (CHIP_IS_E1x(sc)) {
14015 shmem_base = shmem_base_path[0];
14016 shmem2_base = shmem2_base_path[0];
14018 shmem_base = shmem_base_path[port];
14019 shmem2_base = shmem2_base_path[port];
14021 /* Extract the ext phy address for the port */
14022 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14025 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14026 return ELINK_STATUS_ERROR;
14030 elink_cl45_write(sc, &phy,
14031 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
14034 /* Set fault module detected LED on */
14035 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
14036 MISC_REGISTERS_GPIO_HIGH,
14040 return ELINK_STATUS_OK;
14042 static void elink_get_ext_phy_reset_gpio(struct bxe_softc *sc, uint32_t shmem_base,
14043 uint8_t *io_gpio, uint8_t *io_port)
14046 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
14047 offsetof(struct shmem_region,
14048 dev_info.port_hw_config[PORT_0].default_cfg));
14049 switch (phy_gpio_reset) {
14050 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
14054 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
14058 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
14062 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
14066 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
14070 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
14074 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
14078 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
14083 /* Don't override the io_gpio and io_port */
14088 static elink_status_t elink_8727_common_init_phy(struct bxe_softc *sc,
14089 uint32_t shmem_base_path[],
14090 uint32_t shmem2_base_path[], uint8_t phy_index,
14093 int8_t port, reset_gpio;
14094 uint32_t swap_val, swap_override;
14095 struct elink_phy phy[PORT_MAX];
14096 struct elink_phy *phy_blk[PORT_MAX];
14097 int8_t port_of_path;
14098 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14099 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14101 reset_gpio = MISC_REGISTERS_GPIO_1;
14104 /* Retrieve the reset gpio/port which control the reset.
14105 * Default is GPIO1, PORT1
14107 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
14108 (uint8_t *)&reset_gpio, (uint8_t *)&port);
14110 /* Calculate the port based on port swap */
14111 port ^= (swap_val && swap_override);
14113 /* Initiate PHY reset*/
14114 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
14117 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
14122 /* PART1 - Reset both phys */
14123 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14124 uint32_t shmem_base, shmem2_base;
14126 /* In E2, same phy is using for port0 of the two paths */
14127 if (CHIP_IS_E1x(sc)) {
14128 shmem_base = shmem_base_path[0];
14129 shmem2_base = shmem2_base_path[0];
14130 port_of_path = port;
14132 shmem_base = shmem_base_path[port];
14133 shmem2_base = shmem2_base_path[port];
14137 /* Extract the ext phy address for the port */
14138 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14139 port_of_path, &phy[port]) !=
14141 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14142 return ELINK_STATUS_ERROR;
14144 /* disable attentions */
14145 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
14147 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14148 ELINK_NIG_MASK_XGXS0_LINK10G |
14149 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14150 ELINK_NIG_MASK_MI_INT));
14153 /* Reset the phy */
14154 elink_cl45_write(sc, &phy[port],
14155 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
14158 /* Add delay of 150ms after reset */
14160 if (phy[PORT_0].addr & 0x1) {
14161 phy_blk[PORT_0] = &(phy[PORT_1]);
14162 phy_blk[PORT_1] = &(phy[PORT_0]);
14164 phy_blk[PORT_0] = &(phy[PORT_0]);
14165 phy_blk[PORT_1] = &(phy[PORT_1]);
14167 /* PART2 - Download firmware to both phys */
14168 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14169 if (CHIP_IS_E1x(sc))
14170 port_of_path = port;
14173 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14174 phy_blk[port]->addr);
14175 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
14177 return ELINK_STATUS_ERROR;
14178 /* Disable PHY transmitter output */
14179 elink_cl45_write(sc, phy_blk[port],
14181 MDIO_PMA_REG_TX_DISABLE, 1);
14184 return ELINK_STATUS_OK;
14187 static elink_status_t elink_84833_common_init_phy(struct bxe_softc *sc,
14188 uint32_t shmem_base_path[],
14189 uint32_t shmem2_base_path[],
14193 uint8_t reset_gpios;
14194 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
14195 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
14197 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
14198 ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x\n",
14200 return ELINK_STATUS_OK;
14202 static elink_status_t elink_ext_phy_common_init(struct bxe_softc *sc, uint32_t shmem_base_path[],
14203 uint32_t shmem2_base_path[], uint8_t phy_index,
14204 uint32_t ext_phy_type, uint32_t chip_id)
14206 elink_status_t rc = ELINK_STATUS_OK;
14208 switch (ext_phy_type) {
14209 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
14210 rc = elink_8073_common_init_phy(sc, shmem_base_path,
14212 phy_index, chip_id);
14214 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
14215 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
14216 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
14217 rc = elink_8727_common_init_phy(sc, shmem_base_path,
14219 phy_index, chip_id);
14222 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
14223 /* GPIO1 affects both ports, so there's need to pull
14224 * it for single port alone
14226 rc = elink_8726_common_init_phy(sc, shmem_base_path,
14228 phy_index, chip_id);
14230 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
14231 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
14232 /* GPIO3's are linked, and so both need to be toggled
14233 * to obtain required 2us pulse.
14235 rc = elink_84833_common_init_phy(sc, shmem_base_path,
14237 phy_index, chip_id);
14239 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
14240 rc = ELINK_STATUS_ERROR;
14244 "ext_phy 0x%x common init not required\n",
14249 if (rc != ELINK_STATUS_OK)
14250 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
14256 elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[],
14257 uint32_t shmem2_base_path[], uint32_t chip_id,
14258 uint8_t one_port_enabled)
14260 elink_status_t rc = ELINK_STATUS_OK;
14261 uint32_t phy_ver, val;
14262 uint8_t phy_index = 0;
14263 uint32_t ext_phy_type, ext_phy_config;
14264 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
14265 if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
14266 return ELINK_STATUS_OK;
14269 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0);
14270 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1);
14271 ELINK_DEBUG_P0(sc, "Begin common phy init\n");
14272 if (CHIP_IS_E3(sc)) {
14274 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
14275 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
14277 /* Check if common init was already done */
14278 phy_ver = REG_RD(sc, shmem_base_path[0] +
14279 offsetof(struct shmem_region,
14280 port_mb[PORT_0].ext_phy_fw_version));
14282 ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x\n",
14284 return ELINK_STATUS_OK;
14287 /* Read the ext_phy_type for arbitrary port(0) */
14288 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14290 ext_phy_config = elink_get_ext_phy_config(sc,
14291 shmem_base_path[0],
14293 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
14294 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
14296 phy_index, ext_phy_type,
14302 static void elink_check_over_curr(struct elink_params *params,
14303 struct elink_vars *vars)
14305 struct bxe_softc *sc = params->sc;
14307 uint8_t port = params->port;
14310 cfg_pin = (REG_RD(sc, params->shmem_base +
14311 offsetof(struct shmem_region,
14312 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
14313 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
14314 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
14316 /* Ignore check if no external input PIN available */
14317 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
14321 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
14322 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
14323 // " been detected and the power to "
14324 // "that SFP+ module has been removed"
14325 // " to prevent failure of the card."
14326 // " Please remove the SFP+ module and"
14327 // " restart the system to clear this"
14329 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
14330 elink_warpcore_power_module(params, 0);
14333 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
14336 /* Returns 0 if no change occured since last check; 1 otherwise. */
14337 static uint8_t elink_analyze_link_error(struct elink_params *params,
14338 struct elink_vars *vars, uint32_t status,
14339 uint32_t phy_flag, uint32_t link_flag, uint8_t notify)
14341 struct bxe_softc *sc = params->sc;
14342 /* Compare new value with previous value */
14344 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
14346 if ((status ^ old_status) == 0)
14349 /* If values differ */
14350 switch (phy_flag) {
14351 case PHY_HALF_OPEN_CONN_FLAG:
14352 ELINK_DEBUG_P0(sc, "Analyze Remote Fault\n");
14354 case PHY_SFP_TX_FAULT_FLAG:
14355 ELINK_DEBUG_P0(sc, "Analyze TX Fault\n");
14358 ELINK_DEBUG_P0(sc, "Analyze UNKNOWN\n");
14360 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up,
14361 old_status, status);
14363 /* a. Update shmem->link_status accordingly
14364 * b. Update elink_vars->link_up
14367 vars->link_status &= ~LINK_STATUS_LINK_UP;
14368 vars->link_status |= link_flag;
14370 vars->phy_flags |= phy_flag;
14372 /* activate nig drain */
14373 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14374 /* Set LED mode to off since the PHY doesn't know about these
14377 led_mode = ELINK_LED_MODE_OFF;
14379 vars->link_status |= LINK_STATUS_LINK_UP;
14380 vars->link_status &= ~link_flag;
14382 vars->phy_flags &= ~phy_flag;
14383 led_mode = ELINK_LED_MODE_OPER;
14385 /* Clear nig drain */
14386 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14388 elink_sync_link(params, vars);
14389 /* Update the LED according to the link state */
14390 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
14392 /* Update link status in the shared memory */
14393 elink_update_mng(params, vars->link_status);
14395 /* C. Trigger General Attention */
14396 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
14398 elink_cb_notify_link_changed(sc);
14403 /******************************************************************************
14405 * This function checks for half opened connection change indication.
14406 * When such change occurs, it calls the elink_analyze_link_error
14407 * to check if Remote Fault is set or cleared. Reception of remote fault
14408 * status message in the MAC indicates that the peer's MAC has detected
14409 * a fault, for example, due to break in the TX side of fiber.
14411 ******************************************************************************/
14412 elink_status_t elink_check_half_open_conn(struct elink_params *params,
14413 struct elink_vars *vars,
14416 struct bxe_softc *sc = params->sc;
14417 uint32_t lss_status = 0;
14419 /* In case link status is physically up @ 10G do */
14420 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
14421 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
14422 return ELINK_STATUS_OK;
14424 if (CHIP_IS_E3(sc) &&
14425 (REG_RD(sc, MISC_REG_RESET_REG_2) &
14426 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
14427 /* Check E3 XMAC */
14428 /* Note that link speed cannot be queried here, since it may be
14429 * zero while link is down. In case UMAC is active, LSS will
14430 * simply not be set
14432 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
14434 /* Clear stick bits (Requires rising edge) */
14435 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
14436 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
14437 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
14438 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
14439 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
14442 elink_analyze_link_error(params, vars, lss_status,
14443 PHY_HALF_OPEN_CONN_FLAG,
14444 LINK_STATUS_NONE, notify);
14445 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
14446 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
14447 /* Check E1X / E2 BMAC */
14448 uint32_t lss_status_reg;
14449 uint32_t wb_data[2];
14450 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
14451 NIG_REG_INGRESS_BMAC0_MEM;
14452 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
14453 if (CHIP_IS_E2(sc))
14454 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
14456 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
14458 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
14459 lss_status = (wb_data[0] > 0);
14461 elink_analyze_link_error(params, vars, lss_status,
14462 PHY_HALF_OPEN_CONN_FLAG,
14463 LINK_STATUS_NONE, notify);
14465 return ELINK_STATUS_OK;
14467 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
14468 struct elink_params *params,
14469 struct elink_vars *vars)
14471 struct bxe_softc *sc = params->sc;
14472 uint32_t cfg_pin, value = 0;
14473 uint8_t led_change, port = params->port;
14475 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
14476 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
14477 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
14478 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
14479 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
14481 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
14482 ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x\n", cfg_pin);
14486 led_change = elink_analyze_link_error(params, vars, value,
14487 PHY_SFP_TX_FAULT_FLAG,
14488 LINK_STATUS_SFP_TX_FAULT, 1);
14491 /* Change TX_Fault led, set link status for further syncs */
14494 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
14495 led_mode = MISC_REGISTERS_GPIO_HIGH;
14496 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
14498 led_mode = MISC_REGISTERS_GPIO_LOW;
14499 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14502 /* If module is unapproved, led should be on regardless */
14503 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
14504 ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x\n",
14506 elink_set_e3_module_fault_led(params, led_mode);
14510 static void elink_kr2_recovery(struct elink_params *params,
14511 struct elink_vars *vars,
14512 struct elink_phy *phy)
14514 struct bxe_softc *sc = params->sc;
14515 ELINK_DEBUG_P0(sc, "KR2 recovery\n");
14516 elink_warpcore_enable_AN_KR2(phy, params, vars);
14517 elink_warpcore_restart_AN_KR(phy, params);
14520 static void elink_check_kr2_wa(struct elink_params *params,
14521 struct elink_vars *vars,
14522 struct elink_phy *phy)
14524 struct bxe_softc *sc = params->sc;
14525 uint16_t base_page, next_page, not_kr2_device, lane;
14528 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
14529 * Since some switches tend to reinit the AN process and clear the
14530 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
14531 * and recovered many times
14533 if (vars->check_kr2_recovery_cnt > 0) {
14534 vars->check_kr2_recovery_cnt--;
14538 sigdet = elink_warpcore_get_sigdet(phy, params);
14540 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14541 elink_kr2_recovery(params, vars, phy);
14542 ELINK_DEBUG_P0(sc, "No sigdet\n");
14547 lane = elink_get_warpcore_lane(phy, params);
14548 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
14549 MDIO_AER_BLOCK_AER_REG, lane);
14550 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14551 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
14552 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14553 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
14554 elink_set_aer_mmd(params, phy);
14556 /* CL73 has not begun yet */
14557 if (base_page == 0) {
14558 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14559 elink_kr2_recovery(params, vars, phy);
14560 ELINK_DEBUG_P0(sc, "No BP\n");
14565 /* In case NP bit is not set in the BasePage, or it is set,
14566 * but only KX is advertised, declare this link partner as non-KR2
14569 not_kr2_device = (((base_page & 0x8000) == 0) ||
14570 (((base_page & 0x8000) &&
14571 ((next_page & 0xe0) == 0x2))));
14573 /* In case KR2 is already disabled, check if we need to re-enable it */
14574 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14575 if (!not_kr2_device) {
14576 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page,
14578 elink_kr2_recovery(params, vars, phy);
14582 /* KR2 is enabled, but not KR2 device */
14583 if (not_kr2_device) {
14584 /* Disable KR2 on both lanes */
14585 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page, next_page);
14586 elink_disable_kr2(params, vars, phy);
14587 /* Restart AN on leading lane */
14588 elink_warpcore_restart_AN_KR(phy, params);
14593 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
14596 struct bxe_softc *sc = params->sc;
14597 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
14598 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
14599 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
14600 if (elink_check_half_open_conn(params, vars, 1) !=
14602 ELINK_DEBUG_P0(sc, "Fault detection failed\n");
14607 if (CHIP_IS_E3(sc)) {
14608 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
14609 elink_set_aer_mmd(params, phy);
14610 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
14611 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
14612 elink_check_kr2_wa(params, vars, phy);
14613 elink_check_over_curr(params, vars);
14614 if (vars->rx_tx_asic_rst)
14615 elink_warpcore_config_runtime(phy, params, vars);
14617 if ((REG_RD(sc, params->shmem_base +
14618 offsetof(struct shmem_region, dev_info.
14619 port_hw_config[params->port].default_cfg))
14620 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
14621 PORT_HW_CFG_NET_SERDES_IF_SFI) {
14622 if (elink_is_sfp_module_plugged(phy, params)) {
14623 elink_sfp_tx_fault_detection(phy, params, vars);
14624 } else if (vars->link_status &
14625 LINK_STATUS_SFP_TX_FAULT) {
14626 /* Clean trail, interrupt corrects the leds */
14627 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14628 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
14629 /* Update link status in the shared memory */
14630 elink_update_mng(params, vars->link_status);
14636 uint8_t elink_fan_failure_det_req(struct bxe_softc *sc,
14637 uint32_t shmem_base,
14638 uint32_t shmem2_base,
14641 uint8_t phy_index, fan_failure_det_req = 0;
14642 struct elink_phy phy;
14643 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14645 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14647 != ELINK_STATUS_OK) {
14648 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14651 fan_failure_det_req |= (phy.flags &
14652 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
14654 return fan_failure_det_req;
14657 void elink_hw_reset_phy(struct elink_params *params)
14660 struct bxe_softc *sc = params->sc;
14661 elink_update_mng(params, 0);
14662 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
14663 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14664 ELINK_NIG_MASK_XGXS0_LINK10G |
14665 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14666 ELINK_NIG_MASK_MI_INT));
14668 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
14670 if (params->phy[phy_index].hw_reset) {
14671 params->phy[phy_index].hw_reset(
14672 ¶ms->phy[phy_index],
14674 params->phy[phy_index] = phy_null;
14679 void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars,
14680 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
14683 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
14685 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
14686 if (CHIP_IS_E3(sc)) {
14687 if (elink_get_mod_abs_int_cfg(sc, chip_id,
14691 &gpio_port) != ELINK_STATUS_OK)
14694 struct elink_phy phy;
14695 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14697 if (elink_populate_phy(sc, phy_index, shmem_base,
14698 shmem2_base, port, &phy)
14699 != ELINK_STATUS_OK) {
14700 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14703 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
14704 gpio_num = MISC_REGISTERS_GPIO_3;
14711 if (gpio_num == 0xff)
14714 /* Set GPIO3 to trigger SFP+ module insertion/removal */
14715 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
14717 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14718 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14719 gpio_port ^= (swap_val && swap_override);
14721 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
14722 (gpio_num + (gpio_port << 2));
14724 sync_offset = shmem_base +
14725 offsetof(struct shmem_region,
14726 dev_info.port_hw_config[port].aeu_int_mask);
14727 REG_WR(sc, sync_offset, vars->aeu_int_mask);
14729 ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
14730 gpio_num, gpio_port, vars->aeu_int_mask);
14733 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
14735 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
14737 /* Open appropriate AEU for interrupts */
14738 aeu_mask = REG_RD(sc, offset);
14739 aeu_mask |= vars->aeu_int_mask;
14740 REG_WR(sc, offset, aeu_mask);
14742 /* Enable the GPIO to trigger interrupt */
14743 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14744 val |= 1 << (gpio_num + (gpio_port << 2));
14745 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);