2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
38 #include <sys/malloc.h>
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
41 #include <machine/bus.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
44 #include <net/ethernet.h>
46 #include <net/if_media.h>
47 #include <netinet/in.h>
48 #include <netinet/tcp_lro.h>
52 #include "common/t4_msg.h"
53 #include "firmware/t4fw_interface.h"
55 #define KTR_CXGBE KTR_SPARE3
56 MALLOC_DECLARE(M_CXGBE);
57 #define CXGBE_UNIMPLEMENTED(s) \
58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
60 #if defined(__i386__) || defined(__amd64__)
64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
70 #ifndef SYSCTL_ADD_UQUAD
71 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
72 #define sysctl_handle_64 sysctl_handle_quad
73 #define CTLTYPE_U64 CTLTYPE_QUAD
76 #if (__FreeBSD_version >= 900030) || \
77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
82 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
83 static __inline uint64_t
84 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
87 KASSERT(tag == X86_BUS_SPACE_MEM,
88 ("%s: can only handle mem space", __func__));
90 return (*(volatile uint64_t *)(handle + offset));
94 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
95 bus_size_t offset, uint64_t value)
97 KASSERT(tag == X86_BUS_SPACE_MEM,
98 ("%s: can only handle mem space", __func__));
100 *(volatile uint64_t *)(bsh + offset) = value;
103 static __inline uint64_t
104 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
107 return (uint64_t)bus_space_read_4(tag, handle, offset) +
108 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
112 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
113 bus_size_t offset, uint64_t value)
115 bus_space_write_4(tag, bsh, offset, value);
116 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
121 typedef struct adapter adapter_t;
125 * All ingress queues use this entry size. Note that the firmware event
126 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
131 /* Default queue sizes for all kinds of ingress queues */
135 /* All egress queues use this entry size */
138 /* Default queue sizes for all kinds of egress queues */
142 #if MJUMPAGESIZE != MCLBYTES
143 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
145 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
147 CL_METADATA_SIZE = CACHE_LINE_SIZE,
149 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
151 TX_SGL_SEGS_TSO = 38,
152 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
156 /* adapter intr_type */
157 INTR_INTX = (1 << 0),
163 XGMAC_MTU = (1 << 0),
164 XGMAC_PROMISC = (1 << 1),
165 XGMAC_ALLMULTI = (1 << 2),
166 XGMAC_VLANEX = (1 << 3),
167 XGMAC_UCADDR = (1 << 4),
168 XGMAC_MCADDRS = (1 << 5),
174 /* flags understood by begin_synchronized_op */
175 HOLD_LOCK = (1 << 0),
179 /* flags understood by end_synchronized_op */
180 LOCK_HELD = HOLD_LOCK,
185 FULL_INIT_DONE = (1 << 0),
187 /* INTR_DIRECT = (1 << 2), No longer used. */
188 MASTER_PF = (1 << 3),
189 ADAP_SYSCTL_CTX = (1 << 4),
190 /* TOM_INIT_DONE= (1 << 5), No longer used */
191 BUF_PACKING_OK = (1 << 6),
193 CXGBE_BUSY = (1 << 9),
196 HAS_TRACEQ = (1 << 3),
200 VI_INIT_DONE = (1 << 1),
201 VI_SYSCTL_CTX = (1 << 2),
202 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
203 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
204 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ),
206 /* adapter debug_flags */
207 DF_DUMP_MBOX = (1 << 0),
210 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
211 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
212 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
213 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
214 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
218 struct port_info *pi;
221 struct ifmedia media;
226 uint16_t *rss, *nm_rss;
228 int16_t xact_addr_filt;/* index of exact MAC address filter */
229 uint16_t rss_size; /* size of VI's RSS table slice */
230 uint16_t rss_base; /* start of VI's RSS table slice */
232 eventhandler_tag vlan_c;
237 /* These need to be int as they are used in sysctl */
238 int ntxq; /* # of tx queues */
239 int first_txq; /* index of first tx queue */
240 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
241 int nrxq; /* # of rx queues */
242 int first_rxq; /* index of first rx queue */
243 int nofldtxq; /* # of offload tx queues */
244 int first_ofld_txq; /* index of first offload tx queue */
245 int nofldrxq; /* # of offload rx queues */
246 int first_ofld_rxq; /* index of first offload rx queue */
256 struct timeval last_refreshed;
257 struct fw_vi_stats_vf stats;
260 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
262 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
266 /* tx_sched_class flags */
267 TX_SC_OK = (1 << 0), /* Set up in hardware, active. */
270 struct tx_sched_class {
273 struct t4_sched_class_params params;
278 struct adapter *adapter;
285 struct tx_sched_class *tc; /* traffic classes for this channel */
291 uint8_t lport; /* associated offload logical port */
297 uint8_t rx_chan_map; /* rx MPS channel bitmap */
300 struct link_config link_cfg;
302 struct timeval last_refreshed;
303 struct port_stats stats;
304 u_int tx_parse_error;
309 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
311 /* Where the cluster came from, how it has been carved up. */
312 struct cluster_layout {
315 uint16_t region1; /* mbufs laid out within this region */
316 /* region2 is the DMA region */
317 uint16_t region3; /* cluster_metadata within this region */
320 struct cluster_metadata {
322 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
327 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
328 struct cluster_layout cll;
336 struct mbuf *m; /* m_nextpkt linked chain of frames */
337 uint8_t desc_used; /* # of hardware descriptors used by the WR */
341 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
343 struct rss_header rss;
348 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
352 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
353 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
354 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
355 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
362 /* netmap related flags */
369 * Ingress Queue: T4 is producer, driver is consumer.
374 struct adapter *adapter;
375 struct iq_desc *desc; /* KVA of descriptor ring */
376 int8_t intr_pktc_idx; /* packet count threshold index */
377 uint8_t gen; /* generation bit */
378 uint8_t intr_params; /* interrupt holdoff parameters */
379 uint8_t intr_next; /* XXX: holdoff for next interrupt */
380 uint16_t qsize; /* size (# of entries) of the queue */
381 uint16_t sidx; /* index of the entry with the status page */
382 uint16_t cidx; /* consumer index */
383 uint16_t cntxt_id; /* SGE context id for the iq */
384 uint16_t abs_id; /* absolute SGE id for the iq */
386 STAILQ_ENTRY(sge_iq) link;
388 bus_dma_tag_t desc_tag;
389 bus_dmamap_t desc_map;
390 bus_addr_t ba; /* bus address of descriptor ring */
399 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
400 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
401 EQ_ENABLED = (1 << 3), /* open for business */
404 /* Listed in order of preference. Update t4_sysctls too if you change these */
405 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
408 * Egress Queue: driver is producer, T4 is consumer.
410 * Note: A free list is an egress queue (driver produces the buffers and T4
411 * consumes them) but it's special enough to have its own struct (see sge_fl).
414 unsigned int flags; /* MUST be first */
415 unsigned int cntxt_id; /* SGE context id for the eq */
418 struct tx_desc *desc; /* KVA of descriptor ring */
420 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
421 u_int udb_qid; /* relative qid within the doorbell page */
422 uint16_t sidx; /* index of the entry with the status page */
423 uint16_t cidx; /* consumer idx (desc idx) */
424 uint16_t pidx; /* producer idx (desc idx) */
425 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
426 uint16_t dbidx; /* pidx of the most recent doorbell */
427 uint16_t iqid; /* iq that gets egr_update for the eq */
428 uint8_t tx_chan; /* tx channel used by the eq */
429 volatile u_int equiq; /* EQUIQ outstanding */
431 bus_dma_tag_t desc_tag;
432 bus_dmamap_t desc_map;
433 bus_addr_t ba; /* bus address of descriptor ring */
437 struct sw_zone_info {
438 uma_zone_t zone; /* zone that this cluster comes from */
439 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
440 int type; /* EXT_xxx type of the cluster */
446 int8_t zidx; /* backpointer to zone; -ve means unused */
447 int8_t next; /* next hwidx for this zone; -1 means no more */
454 MEMWIN0_APERTURE = 2048,
455 MEMWIN0_BASE = 0x1b800,
457 MEMWIN1_APERTURE = 32768,
458 MEMWIN1_BASE = 0x28000,
460 MEMWIN2_APERTURE_T4 = 65536,
461 MEMWIN2_BASE_T4 = 0x30000,
463 MEMWIN2_APERTURE_T5 = 128 * 1024,
464 MEMWIN2_BASE_T5 = 0x60000,
468 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
469 uint32_t mw_base; /* constant after setup_memwin */
470 uint32_t mw_aperture; /* ditto */
471 uint32_t mw_curpos; /* protected by mw_lock */
475 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
476 FL_DOOMED = (1 << 1), /* about to be destroyed */
477 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
478 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
481 #define FL_RUNNING_LOW(fl) \
482 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
483 #define FL_NOT_RUNNING_LOW(fl) \
484 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
488 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
489 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
490 struct cluster_layout cll_def; /* default refill zone, layout */
491 uint16_t lowat; /* # of buffers <= this means fl needs help */
493 uint16_t buf_boundary;
495 /* The 16b idx all deal with hw descriptors */
496 uint16_t dbidx; /* hw pidx after last doorbell */
497 uint16_t sidx; /* index of status page */
498 volatile uint16_t hw_cidx;
500 /* The 32b idx are all buffer idx, not hardware descriptor idx */
501 uint32_t cidx; /* consumer index */
502 uint32_t pidx; /* producer index */
505 u_int rx_offset; /* offset in fl buf (when buffer packing) */
506 volatile uint32_t *udb;
508 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
509 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
510 uint64_t cl_allocated; /* # of clusters allocated */
511 uint64_t cl_recycled; /* # of clusters recycled */
512 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
514 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
519 uint16_t qsize; /* # of hw descriptors (status page included) */
520 uint16_t cntxt_id; /* SGE context id for the freelist */
521 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
522 bus_dma_tag_t desc_tag;
523 bus_dmamap_t desc_map;
525 bus_addr_t ba; /* bus address of descriptor ring */
526 struct cluster_layout cll_alt; /* alternate refill zone, layout */
531 /* txq: SGE egress queue + what's needed for Ethernet NIC */
533 struct sge_eq eq; /* MUST be first */
535 struct ifnet *ifp; /* the interface this txq belongs to */
536 struct mp_ring *r; /* tx software ring */
537 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
539 __be32 cpl_ctrl0; /* for convenience */
540 int tc_idx; /* traffic class */
542 struct task tx_reclaim_task;
543 /* stats for common events first */
545 uint64_t txcsum; /* # of times hardware assisted with checksum */
546 uint64_t tso_wrs; /* # of TSO work requests */
547 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
548 uint64_t imm_wrs; /* # of work requests with immediate data */
549 uint64_t sgl_wrs; /* # of work requests with direct SGL */
550 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
551 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
552 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
553 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
554 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
556 /* stats for not-that-common events */
557 } __aligned(CACHE_LINE_SIZE);
559 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
561 struct sge_iq iq; /* MUST be first */
562 struct sge_fl fl; /* MUST follow iq */
564 struct ifnet *ifp; /* the interface this rxq belongs to */
565 #if defined(INET) || defined(INET6)
566 struct lro_ctrl lro; /* LRO state */
569 /* stats for common events first */
571 uint64_t rxcsum; /* # of times hardware assisted with checksum */
572 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
574 /* stats for not-that-common events */
576 } __aligned(CACHE_LINE_SIZE);
578 static inline struct sge_rxq *
579 iq_to_rxq(struct sge_iq *iq)
582 return (__containerof(iq, struct sge_rxq, iq));
586 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
587 struct sge_ofld_rxq {
588 struct sge_iq iq; /* MUST be first */
589 struct sge_fl fl; /* MUST follow iq */
590 } __aligned(CACHE_LINE_SIZE);
592 static inline struct sge_ofld_rxq *
593 iq_to_ofld_rxq(struct sge_iq *iq)
596 return (__containerof(iq, struct sge_ofld_rxq, iq));
600 STAILQ_ENTRY(wrqe) link;
603 char wr[] __aligned(16);
607 TAILQ_ENTRY(wrq_cookie) link;
613 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
614 * and offload tx queues are of this type.
617 struct sge_eq eq; /* MUST be first */
619 struct adapter *adapter;
620 struct task wrq_tx_task;
622 /* Tx desc reserved but WR not "committed" yet. */
623 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
625 /* List of WRs ready to go out as soon as descriptors are available. */
626 STAILQ_HEAD(, wrqe) wr_list;
630 /* stats for common events first */
632 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
633 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
634 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
636 /* stats for not-that-common events */
639 * Scratch space for work requests that wrap around after reaching the
640 * status page, and some infomation about the last WR that used it.
644 uint8_t ss[SGE_MAX_WR_LEN];
646 } __aligned(CACHE_LINE_SIZE);
652 struct iq_desc *iq_desc;
654 uint16_t iq_cntxt_id;
660 uint16_t fl_cntxt_id;
667 u_int nid; /* netmap ring # for this queue */
669 /* infrequently used items after this */
671 bus_dma_tag_t iq_desc_tag;
672 bus_dmamap_t iq_desc_map;
676 bus_dma_tag_t fl_desc_tag;
677 bus_dmamap_t fl_desc_map;
679 } __aligned(CACHE_LINE_SIZE);
682 struct tx_desc *desc;
686 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
687 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
688 uint16_t dbidx; /* pidx of the most recent doorbell */
690 volatile uint32_t *udb;
693 __be32 cpl_ctrl0; /* for convenience */
694 u_int nid; /* netmap ring # for this queue */
696 /* infrequently used items after this */
698 bus_dma_tag_t desc_tag;
699 bus_dmamap_t desc_map;
702 } __aligned(CACHE_LINE_SIZE);
705 int nrxq; /* total # of Ethernet rx queues */
706 int ntxq; /* total # of Ethernet tx tx queues */
707 int nofldrxq; /* total # of TOE rx queues */
708 int nofldtxq; /* total # of TOE tx queues */
709 int nnmrxq; /* total # of netmap rx queues */
710 int nnmtxq; /* total # of netmap tx queues */
711 int niq; /* total # of ingress queues */
712 int neq; /* total # of egress queues */
714 struct sge_iq fwq; /* Firmware event queue */
715 struct sge_wrq mgmtq; /* Management queue (control queue) */
716 struct sge_wrq *ctrlq; /* Control queues */
717 struct sge_txq *txq; /* NIC tx queues */
718 struct sge_rxq *rxq; /* NIC rx queues */
719 struct sge_wrq *ofld_txq; /* TOE tx queues */
720 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
721 struct sge_nm_txq *nm_txq; /* netmap tx queues */
722 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
726 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
727 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
729 int8_t safe_hwidx1; /* may not have room for metadata */
730 int8_t safe_hwidx2; /* with room for metadata and maybe more */
731 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
732 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
736 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
738 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
739 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
742 SLIST_ENTRY(adapter) link;
746 /* PCIe register resources */
748 struct resource *regs_res;
750 struct resource *msix_res;
751 bus_space_handle_t bh;
755 struct resource *udbs_res;
756 volatile uint8_t *udbs_base;
760 unsigned int vpd_busy;
761 unsigned int vpd_flag;
763 /* Interrupt information */
767 struct resource *res;
769 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
772 struct sge_nm_rxq *nm_rxq;
773 } __aligned(CACHE_LINE_SIZE) *irq;
775 bus_dma_tag_t dmat; /* Parent DMA tag */
780 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
781 struct port_info *port[MAX_NPORTS];
782 uint8_t chan_map[MAX_NCHAN];
784 void *tom_softc; /* (struct tom_data *) */
785 struct tom_tunables tt;
786 void *iwarp_softc; /* (struct c4iw_dev *) */
788 struct l2t_data *l2t; /* L2 table */
789 struct tid_info tids;
792 int offload_map; /* ports with IFCAP_TOE enabled */
793 int active_ulds; /* ULDs activated on this adapter */
797 char ifp_lockname[16];
799 struct ifnet *ifp; /* tracer ifp */
800 struct ifmedia media;
801 int traceq; /* iq used by all tracers, -1 if none */
802 int tracer_valid; /* bitmap of valid tracers */
803 int tracer_enabled; /* bitmap of enabled tracers */
807 char exprom_version[16];
810 struct adapter_params params;
811 const struct chip_params *chip_params;
812 struct t4_virt_res vres;
824 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
829 /* Starving free lists */
830 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
831 TAILQ_HEAD(, sge_fl) sfl;
832 struct callout sfl_callout;
834 struct mtx reg_lock; /* for indirect register access */
836 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
838 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
839 fw_msg_handler_t fw_msg_handler[7]; /* NUM_FW6_TYPES */
840 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
843 const void *last_op_thr;
849 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
850 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
851 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
852 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
854 #define ASSERT_SYNCHRONIZED_OP(sc) \
855 KASSERT(IS_BUSY(sc) && \
856 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
857 ("%s: operation not synchronized.", __func__))
859 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
860 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
861 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
862 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
864 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
865 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
866 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
867 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
868 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
870 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
871 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
872 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
873 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
875 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
876 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
877 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
878 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
879 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
881 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
882 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
883 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
884 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
885 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
887 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
889 if (sc->debug_flags & DF_DUMP_MBOX) { \
891 "%s mbox %u: %016llx %016llx %016llx %016llx " \
892 "%016llx %016llx %016llx %016llx\n", \
893 device_get_nameunit(sc->dev), mbox, \
894 (unsigned long long)t4_read_reg64(sc, data_reg), \
895 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
896 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
897 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
898 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
899 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
900 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
901 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
905 #define for_each_txq(vi, iter, q) \
906 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
907 iter < vi->ntxq; ++iter, ++q)
908 #define for_each_rxq(vi, iter, q) \
909 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
910 iter < vi->nrxq; ++iter, ++q)
911 #define for_each_ofld_txq(vi, iter, q) \
912 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
913 iter < vi->nofldtxq; ++iter, ++q)
914 #define for_each_ofld_rxq(vi, iter, q) \
915 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
916 iter < vi->nofldrxq; ++iter, ++q)
917 #define for_each_nm_txq(vi, iter, q) \
918 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
919 iter < vi->nnmtxq; ++iter, ++q)
920 #define for_each_nm_rxq(vi, iter, q) \
921 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
922 iter < vi->nnmrxq; ++iter, ++q)
923 #define for_each_vi(_pi, _iter, _vi) \
924 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
927 #define IDXINCR(idx, incr, wrap) do { \
928 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
930 #define IDXDIFF(head, tail, wrap) \
931 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
933 /* One for errors, one for firmware events */
934 #define T4_EXTRA_INTR 2
936 static inline uint32_t
937 t4_read_reg(struct adapter *sc, uint32_t reg)
940 return bus_space_read_4(sc->bt, sc->bh, reg);
944 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
947 bus_space_write_4(sc->bt, sc->bh, reg, val);
950 static inline uint64_t
951 t4_read_reg64(struct adapter *sc, uint32_t reg)
954 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
958 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
961 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
965 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
968 *val = pci_read_config(sc->dev, reg, 1);
972 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
975 pci_write_config(sc->dev, reg, val, 1);
979 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
982 *val = pci_read_config(sc->dev, reg, 2);
986 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
989 pci_write_config(sc->dev, reg, val, 2);
993 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
996 *val = pci_read_config(sc->dev, reg, 4);
1000 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1003 pci_write_config(sc->dev, reg, val, 4);
1006 static inline struct port_info *
1007 adap2pinfo(struct adapter *sc, int idx)
1010 return (sc->port[idx]);
1014 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
1017 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN);
1021 is_10G_port(const struct port_info *pi)
1024 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1028 is_40G_port(const struct port_info *pi)
1031 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1035 port_top_speed(const struct port_info *pi)
1038 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
1040 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
1042 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
1044 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
1051 tx_resume_threshold(struct sge_eq *eq)
1054 /* not quite the same as qsize / 4, but this will do. */
1055 return (eq->sidx / 4);
1059 t4_use_ldst(struct adapter *sc)
1063 return (sc->flags & FW_OK || !sc->use_bd);
1070 int t4_os_find_pci_capability(struct adapter *, int);
1071 int t4_os_pci_save_state(struct adapter *);
1072 int t4_os_pci_restore_state(struct adapter *);
1073 void t4_os_portmod_changed(const struct adapter *, int);
1074 void t4_os_link_changed(struct adapter *, int, int, int);
1075 void t4_iterate(void (*)(struct adapter *, void *), void *);
1076 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
1077 int t4_register_an_handler(struct adapter *, an_handler_t);
1078 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
1079 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1080 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1081 void doom_vi(struct adapter *, struct vi_info *);
1082 void end_synchronized_op(struct adapter *, int);
1083 int update_mac_settings(struct ifnet *, int);
1084 int adapter_full_init(struct adapter *);
1085 int adapter_full_uninit(struct adapter *);
1086 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1087 int vi_full_init(struct vi_info *);
1088 int vi_full_uninit(struct vi_info *);
1089 void vi_sysctls(struct vi_info *);
1090 void vi_tick(void *);
1094 void cxgbe_nm_attach(struct vi_info *);
1095 void cxgbe_nm_detach(struct vi_info *);
1096 void t4_nm_intr(void *);
1100 void t4_sge_modload(void);
1101 void t4_sge_modunload(void);
1102 uint64_t t4_sge_extfree_refs(void);
1103 void t4_init_sge_cpl_handlers(struct adapter *);
1104 void t4_tweak_chip_settings(struct adapter *);
1105 int t4_read_chip_settings(struct adapter *);
1106 int t4_create_dma_tag(struct adapter *);
1107 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1108 struct sysctl_oid_list *);
1109 int t4_destroy_dma_tag(struct adapter *);
1110 int t4_setup_adapter_queues(struct adapter *);
1111 int t4_teardown_adapter_queues(struct adapter *);
1112 int t4_setup_vi_queues(struct vi_info *);
1113 int t4_teardown_vi_queues(struct vi_info *);
1114 void t4_intr_all(void *);
1115 void t4_intr(void *);
1116 void t4_vi_intr(void *);
1117 void t4_intr_err(void *);
1118 void t4_intr_evt(void *);
1119 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1120 void t4_update_fl_bufsize(struct ifnet *);
1121 int parse_pkt(struct mbuf **);
1122 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1123 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1124 int tnl_cong(struct port_info *, int);
1128 void t4_tracer_modload(void);
1129 void t4_tracer_modunload(void);
1130 void t4_tracer_port_detach(struct adapter *);
1131 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1132 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1133 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1134 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1136 static inline struct wrqe *
1137 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1139 int len = offsetof(struct wrqe, wr) + wr_len;
1142 wr = malloc(len, M_CXGBE, M_NOWAIT);
1143 if (__predict_false(wr == NULL))
1145 wr->wr_len = wr_len;
1150 static inline void *
1151 wrtod(struct wrqe *wr)
1153 return (&wr->wr[0]);
1157 free_wrqe(struct wrqe *wr)
1163 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1165 struct sge_wrq *wrq = wr->wrq;
1168 t4_wrq_tx_locked(sc, wrq, wr);