2 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef __CHELSIO_COMMON_H
31 #define __CHELSIO_COMMON_H
35 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \
36 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \
37 F_CPL_SWITCH | F_SGE | F_ULP_TX)
40 MAX_NPORTS = 4, /* max # of ports */
41 SERNUM_LEN = 24, /* Serial # length */
42 EC_LEN = 16, /* E/C length */
43 ID_LEN = 16, /* ID length */
44 PN_LEN = 16, /* Part Number length */
45 MACADDR_LEN = 12, /* MAC Address length */
49 T4_REGMAP_SIZE = (160 * 1024),
50 T5_REGMAP_SIZE = (332 * 1024),
53 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
55 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
57 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
62 PAUSE_AUTONEG = 1 << 2
66 u64 tx_octets; /* total # of octets in good frames */
67 u64 tx_frames; /* all good frames */
68 u64 tx_bcast_frames; /* all broadcast frames */
69 u64 tx_mcast_frames; /* all multicast frames */
70 u64 tx_ucast_frames; /* all unicast frames */
71 u64 tx_error_frames; /* all error frames */
73 u64 tx_frames_64; /* # of Tx frames in a particular range */
75 u64 tx_frames_128_255;
76 u64 tx_frames_256_511;
77 u64 tx_frames_512_1023;
78 u64 tx_frames_1024_1518;
79 u64 tx_frames_1519_max;
81 u64 tx_drop; /* # of dropped Tx frames */
82 u64 tx_pause; /* # of transmitted pause frames */
83 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
84 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
85 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
86 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
87 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
88 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
89 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
90 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
92 u64 rx_octets; /* total # of octets in good frames */
93 u64 rx_frames; /* all good frames */
94 u64 rx_bcast_frames; /* all broadcast frames */
95 u64 rx_mcast_frames; /* all multicast frames */
96 u64 rx_ucast_frames; /* all unicast frames */
97 u64 rx_too_long; /* # of frames exceeding MTU */
98 u64 rx_jabber; /* # of jabber frames */
99 u64 rx_fcs_err; /* # of received frames with bad FCS */
100 u64 rx_len_err; /* # of received frames with length error */
101 u64 rx_symbol_err; /* symbol errors */
102 u64 rx_runt; /* # of short frames */
104 u64 rx_frames_64; /* # of Rx frames in a particular range */
105 u64 rx_frames_65_127;
106 u64 rx_frames_128_255;
107 u64 rx_frames_256_511;
108 u64 rx_frames_512_1023;
109 u64 rx_frames_1024_1518;
110 u64 rx_frames_1519_max;
112 u64 rx_pause; /* # of received pause frames */
113 u64 rx_ppp0; /* # of received PPP prio 0 frames */
114 u64 rx_ppp1; /* # of received PPP prio 1 frames */
115 u64 rx_ppp2; /* # of received PPP prio 2 frames */
116 u64 rx_ppp3; /* # of received PPP prio 3 frames */
117 u64 rx_ppp4; /* # of received PPP prio 4 frames */
118 u64 rx_ppp5; /* # of received PPP prio 5 frames */
119 u64 rx_ppp6; /* # of received PPP prio 6 frames */
120 u64 rx_ppp7; /* # of received PPP prio 7 frames */
122 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
123 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
124 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
125 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
126 u64 rx_trunc0; /* buffer-group 0 truncated packets */
127 u64 rx_trunc1; /* buffer-group 1 truncated packets */
128 u64 rx_trunc2; /* buffer-group 2 truncated packets */
129 u64 rx_trunc3; /* buffer-group 3 truncated packets */
132 struct lb_port_stats {
145 u64 frames_1024_1518;
160 struct tp_tcp_stats {
164 u64 tcp_retrans_segs;
167 struct tp_usm_stats {
173 struct tp_fcoe_stats {
179 struct tp_err_stats {
180 u32 mac_in_errs[MAX_NCHAN];
181 u32 hdr_in_errs[MAX_NCHAN];
182 u32 tcp_in_errs[MAX_NCHAN];
183 u32 tnl_cong_drops[MAX_NCHAN];
184 u32 ofld_chan_drops[MAX_NCHAN];
185 u32 tnl_tx_drops[MAX_NCHAN];
186 u32 ofld_vlan_drops[MAX_NCHAN];
187 u32 tcp6_in_errs[MAX_NCHAN];
192 struct tp_proxy_stats {
193 u32 proxy[MAX_NCHAN];
196 struct tp_cpl_stats {
201 struct tp_rdma_stats {
207 int timer_val[SGE_NTIMERS];
208 int counter_val[SGE_NCOUNTERS];
209 int fl_starve_threshold;
210 int fl_starve_threshold2;
219 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES];
223 unsigned int tre; /* log2 of core clocks per TP tick */
224 unsigned int dack_re; /* DACK timer resolution */
225 unsigned int la_mask; /* what events are recorded by TP LA */
226 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */
228 uint32_t vlan_pri_map;
229 uint32_t ingress_config;
230 uint32_t rx_pkt_encap;
237 int8_t protocol_shift;
238 int8_t ethertype_shift;
239 int8_t macmatch_shift;
240 int8_t matchtype_shift;
247 u8 sn[SERNUM_LEN + 1];
250 u8 na[MACADDR_LEN + 1];
254 unsigned int vpd_cap_addr;
256 unsigned short speed;
257 unsigned short width;
261 * Firmware device log.
263 struct devlog_params {
264 u32 memtype; /* which memory (FW_MEMTYPE_* ) */
265 u32 start; /* start of log in firmware memory */
266 u32 size; /* size of log */
267 u32 addr; /* start address in flat addr space */
270 /* Stores chip specific parameters */
274 u8 cng_ch_bits_log; /* congestion channel map bits width */
283 /* VF-only parameters. */
286 * Global Receive Side Scaling (RSS) parameters in host-native format.
289 unsigned int mode; /* RSS mode */
292 u_int synmapen:1; /* SYN Map Enable */
293 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
294 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
295 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
296 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
297 u_int ofdmapen:1; /* Offload Map Enable */
298 u_int tnlmapen:1; /* Tunnel Map Enable */
299 u_int tnlalllookup:1; /* Tunnel All Lookup */
300 u_int hashtoeplitz:1; /* use Toeplitz hash */
306 * Maximum resources provisioned for a PCI VF.
308 struct vf_resources {
309 unsigned int nvi; /* N virtual interfaces */
310 unsigned int neq; /* N egress Qs */
311 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
312 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
313 unsigned int niq; /* N ingress Qs */
314 unsigned int tc; /* PCI-E traffic class */
315 unsigned int pmask; /* port access rights mask */
316 unsigned int nexactf; /* N exact MPS filters */
317 unsigned int r_caps; /* read capabilities */
318 unsigned int wx_caps; /* write/execute capabilities */
321 struct adapter_params {
322 struct sge_params sge;
323 struct tp_params tp; /* PF-only */
324 struct vpd_params vpd;
325 struct pci_params pci;
326 struct devlog_params devlog; /* PF-only */
327 struct rss_params rss; /* VF-only */
328 struct vf_resources vfres; /* VF-only */
330 unsigned int sf_size; /* serial flash size in bytes */
331 unsigned int sf_nsec; /* # of flash sectors */
333 unsigned int fw_vers; /* firmware version */
334 unsigned int bs_vers; /* bootstrap version */
335 unsigned int tp_vers; /* TP microcode version */
336 unsigned int er_vers; /* expansion ROM version */
337 unsigned int scfg_vers; /* Serial Configuration version */
338 unsigned int vpd_vers; /* VPD version */
340 unsigned short mtus[NMTUS];
341 unsigned short a_wnd[NCCTRL_WIN];
342 unsigned short b_wnd[NCCTRL_WIN];
349 unsigned int cim_la_size;
351 uint8_t nports; /* # of ethernet ports */
353 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
354 unsigned int rev:4; /* chip revision */
355 unsigned int fpga:1; /* this is an FPGA */
356 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
357 resources for TOE operation. */
358 unsigned int bypass:1; /* this is a bypass card */
359 unsigned int ethoffload:1;
361 unsigned int ofldq_wr_cred;
362 unsigned int eo_wr_cred;
365 #define CHELSIO_T4 0x4
366 #define CHELSIO_T5 0x5
367 #define CHELSIO_T6 0x6
370 * State needed to monitor the forward progress of SGE Ingress DMA activities
371 * and possible hangs.
373 struct sge_idma_monitor_state {
374 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
375 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
376 unsigned int idma_state[2]; /* IDMA Hang detect state */
377 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
378 unsigned int idma_warn[2]; /* time to warning in HZ */
381 struct trace_params {
382 u32 data[TRACE_LEN / 4];
383 u32 mask[TRACE_LEN / 4];
384 unsigned short snap_len;
385 unsigned short min_len;
386 unsigned char skip_ofst;
387 unsigned char skip_len;
388 unsigned char invert;
393 unsigned short supported; /* link capabilities */
394 unsigned short advertising; /* advertised capabilities */
395 unsigned short requested_speed; /* speed user has requested */
396 unsigned short speed; /* actual link speed */
397 unsigned char requested_fc; /* flow control user has requested */
398 unsigned char fc; /* actual link flow control */
399 unsigned char autoneg; /* autonegotiating? */
400 unsigned char link_ok; /* link up? */
405 #ifndef PCI_VENDOR_ID_CHELSIO
406 # define PCI_VENDOR_ID_CHELSIO 0x1425
409 #define for_each_port(adapter, iter) \
410 for (iter = 0; iter < (adapter)->params.nports; ++iter)
412 static inline int is_ftid(const struct adapter *sc, u_int tid)
415 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max);
418 static inline int is_etid(const struct adapter *sc, u_int tid)
421 return (tid >= sc->params.etid_min);
424 static inline int is_offload(const struct adapter *adap)
426 return adap->params.offload;
429 static inline int is_ethoffload(const struct adapter *adap)
431 return adap->params.ethoffload;
434 static inline int chip_id(struct adapter *adap)
436 return adap->params.chipid;
439 static inline int chip_rev(struct adapter *adap)
441 return adap->params.rev;
444 static inline int is_t4(struct adapter *adap)
446 return adap->params.chipid == CHELSIO_T4;
449 static inline int is_t5(struct adapter *adap)
451 return adap->params.chipid == CHELSIO_T5;
454 static inline int is_t6(struct adapter *adap)
456 return adap->params.chipid == CHELSIO_T6;
459 static inline int is_fpga(struct adapter *adap)
461 return adap->params.fpga;
464 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
466 return adap->params.vpd.cclk / 1000;
469 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
472 return (us * adap->params.vpd.cclk) / 1000;
475 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
478 /* add Core Clock / 2 to round ticks to nearest uS */
479 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
480 adapter->params.vpd.cclk);
483 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
486 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
489 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
491 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
492 int size, void *rpl, bool sleep_ok, int timeout);
493 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
494 void *rpl, bool sleep_ok);
496 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
497 const void *cmd, int size, void *rpl,
500 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
504 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
507 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
510 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
513 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
516 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
517 unsigned int data_reg, u32 *vals, unsigned int nregs,
518 unsigned int start_idx);
519 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
520 unsigned int data_reg, const u32 *vals,
521 unsigned int nregs, unsigned int start_idx);
523 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);
527 void t4_intr_enable(struct adapter *adapter);
528 void t4_intr_disable(struct adapter *adapter);
529 void t4_intr_clear(struct adapter *adapter);
530 int t4_slow_intr_handler(struct adapter *adapter);
532 int t4_hash_mac_addr(const u8 *addr);
533 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
534 struct link_config *lc);
535 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
536 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
537 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
538 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
539 int t4_seeprom_wp(struct adapter *adapter, int enable);
540 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
541 u32 *data, int byte_oriented);
542 int t4_write_flash(struct adapter *adapter, unsigned int addr,
543 unsigned int n, const u8 *data, int byte_oriented);
544 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
545 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
546 int t5_fw_init_extern_mem(struct adapter *adap);
547 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
548 int t4_load_boot(struct adapter *adap, u8 *boot_data,
549 unsigned int boot_addr, unsigned int size);
550 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
551 int t4_flash_cfg_addr(struct adapter *adapter);
552 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
553 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
554 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
555 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
556 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
557 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
558 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
559 int t4_get_version_info(struct adapter *adapter);
560 int t4_init_hw(struct adapter *adapter, u32 fw_params);
561 const struct chip_params *t4_get_chip_params(int chipid);
562 int t4_prep_adapter(struct adapter *adapter, u8 *buf);
563 int t4_shutdown_adapter(struct adapter *adapter);
564 int t4_init_devlog_params(struct adapter *adapter, int fw_attach);
565 int t4_init_sge_params(struct adapter *adapter);
566 int t4_init_tp_params(struct adapter *adap);
567 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
568 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id);
569 void t4_fatal_err(struct adapter *adapter);
570 void t4_db_full(struct adapter *adapter);
571 void t4_db_dropped(struct adapter *adapter);
572 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
573 int filter_index, int enable);
574 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
575 int filter_index, int *enabled);
576 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
577 int start, int n, const u16 *rspq, unsigned int nrspq);
578 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
580 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
581 unsigned int flags, unsigned int defq, unsigned int skeyidx,
583 int t4_read_rss(struct adapter *adapter, u16 *entries);
584 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
585 unsigned int start_index, unsigned int rw);
586 void t4_read_rss_key(struct adapter *adapter, u32 *key);
587 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
588 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp);
589 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val);
590 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
592 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
594 u32 t4_read_rss_pf_map(struct adapter *adapter);
595 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap);
596 u32 t4_read_rss_pf_mask(struct adapter *adapter);
597 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask);
598 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
599 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
600 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
601 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
602 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
603 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
604 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
606 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
607 const unsigned int *valp);
608 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
610 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
611 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
612 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
613 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
614 int t4_get_flash_params(struct adapter *adapter);
616 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
617 int t4_mc_read(struct adapter *adap, int idx, u32 addr,
618 __be32 *data, u64 *parity);
619 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
620 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
622 void t4_idma_monitor_init(struct adapter *adapter,
623 struct sge_idma_monitor_state *idma);
624 void t4_idma_monitor(struct adapter *adapter,
625 struct sge_idma_monitor_state *idma,
628 unsigned int t4_get_regs_len(struct adapter *adapter);
629 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size);
631 const char *t4_get_port_type_description(enum fw_port_type port_type);
632 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
633 void t4_get_port_stats_offset(struct adapter *adap, int idx,
634 struct port_stats *stats,
635 struct port_stats *offset);
636 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
637 void t4_clr_port_stats(struct adapter *adap, int idx);
639 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
640 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
641 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
642 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
644 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
645 unsigned int mask, unsigned int val);
646 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
647 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
648 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st);
649 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
650 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
651 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
652 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
653 struct tp_tcp_stats *v6);
654 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
655 struct tp_fcoe_stats *st);
656 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
657 const unsigned short *alpha, const unsigned short *beta);
659 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
661 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps);
662 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg);
663 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
664 unsigned int start, unsigned int n);
665 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
666 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map);
667 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
669 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
670 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
671 u64 mask0, u64 mask1, unsigned int crc, bool enable);
673 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
674 enum dev_master master, enum dev_state *state);
675 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
676 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
677 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
678 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
679 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
680 const u8 *fw_data, unsigned int size, int force);
681 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
682 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
683 unsigned int vf, unsigned int nparams, const u32 *params,
685 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
686 unsigned int vf, unsigned int nparams, const u32 *params,
688 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
689 unsigned int pf, unsigned int vf,
690 unsigned int nparams, const u32 *params,
691 const u32 *val, int timeout);
692 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
693 unsigned int vf, unsigned int nparams, const u32 *params,
695 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
696 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
697 unsigned int rxqi, unsigned int rxq, unsigned int tc,
698 unsigned int vi, unsigned int cmask, unsigned int pmask,
699 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
700 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
701 unsigned int port, unsigned int pf, unsigned int vf,
702 unsigned int nmac, u8 *mac, u16 *rss_size,
703 unsigned int portfunc, unsigned int idstype);
704 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
705 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
707 int t4_free_vi(struct adapter *adap, unsigned int mbox,
708 unsigned int pf, unsigned int vf,
710 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
711 int mtu, int promisc, int all_multi, int bcast, int vlanex,
713 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
714 bool free, unsigned int naddr, const u8 **addr, u16 *idx,
715 u64 *hash, bool sleep_ok);
716 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
717 int idx, const u8 *addr, bool persist, bool add_smt);
718 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
719 bool ucast, u64 vec, bool sleep_ok);
720 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
721 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
722 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
723 bool rx_en, bool tx_en);
724 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
725 unsigned int nblinks);
726 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
727 unsigned int mmd, unsigned int reg, unsigned int *valp);
728 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
729 unsigned int mmd, unsigned int reg, unsigned int val);
730 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
731 int port, unsigned int devid,
732 unsigned int offset, unsigned int len,
734 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
735 int port, unsigned int devid,
736 unsigned int offset, unsigned int len,
738 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
739 unsigned int vf, unsigned int iqtype, unsigned int iqid,
740 unsigned int fl0id, unsigned int fl1id);
741 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
742 unsigned int vf, unsigned int iqtype, unsigned int iqid,
743 unsigned int fl0id, unsigned int fl1id);
744 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
745 unsigned int vf, unsigned int eqid);
746 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
747 unsigned int vf, unsigned int eqid);
748 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
749 unsigned int vf, unsigned int eqid);
750 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
751 enum ctxt_type ctype, u32 *data);
752 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
754 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
755 const char *t4_link_down_rc_str(unsigned char link_down_rc);
756 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
757 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
758 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
760 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
761 int rateunit, int ratemode, int channel, int cl,
762 int minrate, int maxrate, int weight, int pktsize,
764 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
765 unsigned int pf, unsigned int vf,
766 unsigned int timeout, unsigned int action);
767 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level);
768 int t4_set_devlog_level(struct adapter *adapter, unsigned int level);
769 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
771 static inline int t4vf_query_params(struct adapter *adapter,
772 unsigned int nparams, const u32 *params,
775 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals);
778 static inline int t4vf_set_params(struct adapter *adapter,
779 unsigned int nparams, const u32 *params,
782 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals);
785 static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd,
788 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl);
791 int t4vf_wait_dev_ready(struct adapter *adapter);
792 int t4vf_fw_reset(struct adapter *adapter);
793 int t4vf_get_sge_params(struct adapter *adapter);
794 int t4vf_get_rss_glb_config(struct adapter *adapter);
795 int t4vf_get_vfres(struct adapter *adapter);
796 int t4vf_prep_adapter(struct adapter *adapter);
798 #endif /* __CHELSIO_COMMON_H */