2 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef __CHELSIO_COMMON_H
31 #define __CHELSIO_COMMON_H
35 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \
36 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \
37 F_CPL_SWITCH | F_SGE | F_ULP_TX)
40 MAX_NPORTS = 4, /* max # of ports */
41 SERNUM_LEN = 24, /* Serial # length */
42 EC_LEN = 16, /* E/C length */
43 ID_LEN = 16, /* ID length */
44 PN_LEN = 16, /* Part Number length */
45 MACADDR_LEN = 12, /* MAC Address length */
49 T4_REGMAP_SIZE = (160 * 1024),
50 T5_REGMAP_SIZE = (332 * 1024),
53 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
56 MEMWIN0_APERTURE = 2048,
57 MEMWIN0_BASE = 0x1b800,
59 MEMWIN1_APERTURE = 32768,
60 MEMWIN1_BASE = 0x28000,
62 MEMWIN2_APERTURE_T4 = 65536,
63 MEMWIN2_BASE_T4 = 0x30000,
65 MEMWIN2_APERTURE_T5 = 128 * 1024,
66 MEMWIN2_BASE_T5 = 0x60000,
69 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
71 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
76 PAUSE_AUTONEG = 1 << 2
85 u64 tx_octets; /* total # of octets in good frames */
86 u64 tx_frames; /* all good frames */
87 u64 tx_bcast_frames; /* all broadcast frames */
88 u64 tx_mcast_frames; /* all multicast frames */
89 u64 tx_ucast_frames; /* all unicast frames */
90 u64 tx_error_frames; /* all error frames */
92 u64 tx_frames_64; /* # of Tx frames in a particular range */
94 u64 tx_frames_128_255;
95 u64 tx_frames_256_511;
96 u64 tx_frames_512_1023;
97 u64 tx_frames_1024_1518;
98 u64 tx_frames_1519_max;
100 u64 tx_drop; /* # of dropped Tx frames */
101 u64 tx_pause; /* # of transmitted pause frames */
102 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
103 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
104 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
105 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
106 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
107 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
108 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
109 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
111 u64 rx_octets; /* total # of octets in good frames */
112 u64 rx_frames; /* all good frames */
113 u64 rx_bcast_frames; /* all broadcast frames */
114 u64 rx_mcast_frames; /* all multicast frames */
115 u64 rx_ucast_frames; /* all unicast frames */
116 u64 rx_too_long; /* # of frames exceeding MTU */
117 u64 rx_jabber; /* # of jabber frames */
118 u64 rx_fcs_err; /* # of received frames with bad FCS */
119 u64 rx_len_err; /* # of received frames with length error */
120 u64 rx_symbol_err; /* symbol errors */
121 u64 rx_runt; /* # of short frames */
123 u64 rx_frames_64; /* # of Rx frames in a particular range */
124 u64 rx_frames_65_127;
125 u64 rx_frames_128_255;
126 u64 rx_frames_256_511;
127 u64 rx_frames_512_1023;
128 u64 rx_frames_1024_1518;
129 u64 rx_frames_1519_max;
131 u64 rx_pause; /* # of received pause frames */
132 u64 rx_ppp0; /* # of received PPP prio 0 frames */
133 u64 rx_ppp1; /* # of received PPP prio 1 frames */
134 u64 rx_ppp2; /* # of received PPP prio 2 frames */
135 u64 rx_ppp3; /* # of received PPP prio 3 frames */
136 u64 rx_ppp4; /* # of received PPP prio 4 frames */
137 u64 rx_ppp5; /* # of received PPP prio 5 frames */
138 u64 rx_ppp6; /* # of received PPP prio 6 frames */
139 u64 rx_ppp7; /* # of received PPP prio 7 frames */
141 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
142 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
143 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
144 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
145 u64 rx_trunc0; /* buffer-group 0 truncated packets */
146 u64 rx_trunc1; /* buffer-group 1 truncated packets */
147 u64 rx_trunc2; /* buffer-group 2 truncated packets */
148 u64 rx_trunc3; /* buffer-group 3 truncated packets */
151 struct lb_port_stats {
164 u64 frames_1024_1518;
179 struct tp_tcp_stats {
183 u64 tcp_retrans_segs;
186 struct tp_usm_stats {
192 struct tp_fcoe_stats {
198 struct tp_err_stats {
199 u32 mac_in_errs[MAX_NCHAN];
200 u32 hdr_in_errs[MAX_NCHAN];
201 u32 tcp_in_errs[MAX_NCHAN];
202 u32 tnl_cong_drops[MAX_NCHAN];
203 u32 ofld_chan_drops[MAX_NCHAN];
204 u32 tnl_tx_drops[MAX_NCHAN];
205 u32 ofld_vlan_drops[MAX_NCHAN];
206 u32 tcp6_in_errs[MAX_NCHAN];
211 struct tp_proxy_stats {
212 u32 proxy[MAX_NCHAN];
215 struct tp_cpl_stats {
220 struct tp_rdma_stats {
226 int timer_val[SGE_NTIMERS];
227 int counter_val[SGE_NCOUNTERS];
228 int fl_starve_threshold;
229 int fl_starve_threshold2;
240 unsigned int tre; /* log2 of core clocks per TP tick */
241 unsigned int dack_re; /* DACK timer resolution */
242 unsigned int la_mask; /* what events are recorded by TP LA */
243 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */
245 uint32_t vlan_pri_map;
246 uint32_t ingress_config;
247 uint32_t rx_pkt_encap;
254 int8_t protocol_shift;
255 int8_t ethertype_shift;
256 int8_t macmatch_shift;
257 int8_t matchtype_shift;
264 u8 sn[SERNUM_LEN + 1];
267 u8 na[MACADDR_LEN + 1];
271 unsigned int vpd_cap_addr;
273 unsigned short speed;
274 unsigned short width;
278 * Firmware device log.
280 struct devlog_params {
281 u32 memtype; /* which memory (FW_MEMTYPE_* ) */
282 u32 start; /* start of log in firmware memory */
283 u32 size; /* size of log */
286 /* Stores chip specific parameters */
290 u8 cng_ch_bits_log; /* congestion channel map bits width */
299 struct adapter_params {
300 struct sge_params sge;
302 struct vpd_params vpd;
303 struct pci_params pci;
304 struct devlog_params devlog;
306 unsigned int sf_size; /* serial flash size in bytes */
307 unsigned int sf_nsec; /* # of flash sectors */
309 unsigned int fw_vers;
310 unsigned int tp_vers;
312 unsigned short mtus[NMTUS];
313 unsigned short a_wnd[NCCTRL_WIN];
314 unsigned short b_wnd[NCCTRL_WIN];
321 unsigned int cim_la_size;
323 uint8_t nports; /* # of ethernet ports */
325 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
326 unsigned int rev:4; /* chip revision */
327 unsigned int fpga:1; /* this is an FPGA */
328 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
329 resources for TOE operation. */
330 unsigned int bypass:1; /* this is a bypass card */
331 unsigned int ethoffload:1;
333 unsigned int ofldq_wr_cred;
334 unsigned int eo_wr_cred;
337 #define CHELSIO_T4 0x4
338 #define CHELSIO_T5 0x5
339 #define CHELSIO_T6 0x6
342 * State needed to monitor the forward progress of SGE Ingress DMA activities
343 * and possible hangs.
345 struct sge_idma_monitor_state {
346 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
347 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
348 unsigned int idma_state[2]; /* IDMA Hang detect state */
349 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
350 unsigned int idma_warn[2]; /* time to warning in HZ */
353 struct trace_params {
354 u32 data[TRACE_LEN / 4];
355 u32 mask[TRACE_LEN / 4];
356 unsigned short snap_len;
357 unsigned short min_len;
358 unsigned char skip_ofst;
359 unsigned char skip_len;
360 unsigned char invert;
365 unsigned short supported; /* link capabilities */
366 unsigned short advertising; /* advertised capabilities */
367 unsigned short requested_speed; /* speed user has requested */
368 unsigned short speed; /* actual link speed */
369 unsigned char requested_fc; /* flow control user has requested */
370 unsigned char fc; /* actual link flow control */
371 unsigned char autoneg; /* autonegotiating? */
372 unsigned char link_ok; /* link up? */
377 #ifndef PCI_VENDOR_ID_CHELSIO
378 # define PCI_VENDOR_ID_CHELSIO 0x1425
381 #define for_each_port(adapter, iter) \
382 for (iter = 0; iter < (adapter)->params.nports; ++iter)
384 static inline int is_ftid(const struct adapter *sc, u_int tid)
387 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max);
390 static inline int is_etid(const struct adapter *sc, u_int tid)
393 return (tid >= sc->params.etid_min);
396 static inline int is_offload(const struct adapter *adap)
398 return adap->params.offload;
401 static inline int is_ethoffload(const struct adapter *adap)
403 return adap->params.ethoffload;
406 static inline int chip_id(struct adapter *adap)
408 return adap->params.chipid;
411 static inline int chip_rev(struct adapter *adap)
413 return adap->params.rev;
416 static inline int is_t4(struct adapter *adap)
418 return adap->params.chipid == CHELSIO_T4;
421 static inline int is_t5(struct adapter *adap)
423 return adap->params.chipid == CHELSIO_T5;
426 static inline int is_t6(struct adapter *adap)
428 return adap->params.chipid == CHELSIO_T6;
431 static inline int is_fpga(struct adapter *adap)
433 return adap->params.fpga;
436 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
438 return adap->params.vpd.cclk / 1000;
441 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
444 return (us * adap->params.vpd.cclk) / 1000;
447 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
450 /* add Core Clock / 2 to round ticks to nearest uS */
451 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
452 adapter->params.vpd.cclk);
455 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
458 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
461 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
463 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
464 int size, void *rpl, bool sleep_ok, int timeout);
465 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
466 void *rpl, bool sleep_ok);
468 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
469 const void *cmd, int size, void *rpl,
472 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
476 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
479 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
482 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
485 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
488 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
489 unsigned int data_reg, u32 *vals, unsigned int nregs,
490 unsigned int start_idx);
491 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
492 unsigned int data_reg, const u32 *vals,
493 unsigned int nregs, unsigned int start_idx);
495 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);
499 void t4_intr_enable(struct adapter *adapter);
500 void t4_intr_disable(struct adapter *adapter);
501 void t4_intr_clear(struct adapter *adapter);
502 int t4_slow_intr_handler(struct adapter *adapter);
504 int t4_hash_mac_addr(const u8 *addr);
505 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
506 struct link_config *lc);
507 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
508 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
509 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
510 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
511 int t4_seeprom_wp(struct adapter *adapter, int enable);
512 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
513 u32 *data, int byte_oriented);
514 int t4_write_flash(struct adapter *adapter, unsigned int addr,
515 unsigned int n, const u8 *data, int byte_oriented);
516 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
517 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
518 int t5_fw_init_extern_mem(struct adapter *adap);
519 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
520 int t4_load_boot(struct adapter *adap, u8 *boot_data,
521 unsigned int boot_addr, unsigned int size);
522 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
523 int t4_flash_cfg_addr(struct adapter *adapter);
524 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
525 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
526 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
527 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
528 int t4_init_hw(struct adapter *adapter, u32 fw_params);
529 int t4_prep_adapter(struct adapter *adapter, u8 *buf);
530 int t4_shutdown_adapter(struct adapter *adapter);
531 int t4_init_devlog_params(struct adapter *adapter, int fw_attach);
532 int t4_init_sge_params(struct adapter *adapter);
533 int t4_init_tp_params(struct adapter *adap);
534 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
535 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id);
536 void t4_fatal_err(struct adapter *adapter);
537 void t4_db_full(struct adapter *adapter);
538 void t4_db_dropped(struct adapter *adapter);
539 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
540 int filter_index, int enable);
541 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
542 int filter_index, int *enabled);
543 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
544 int start, int n, const u16 *rspq, unsigned int nrspq);
545 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
547 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
548 unsigned int flags, unsigned int defq);
549 int t4_read_rss(struct adapter *adapter, u16 *entries);
550 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
551 unsigned int start_index, unsigned int rw);
552 void t4_read_rss_key(struct adapter *adapter, u32 *key);
553 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
554 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp);
555 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val);
556 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
558 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
560 u32 t4_read_rss_pf_map(struct adapter *adapter);
561 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap);
562 u32 t4_read_rss_pf_mask(struct adapter *adapter);
563 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask);
564 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
565 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
566 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
567 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
568 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
569 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
570 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
572 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
573 const unsigned int *valp);
574 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
576 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
577 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
578 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
579 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
580 int t4_get_flash_params(struct adapter *adapter);
582 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
583 int t4_mc_read(struct adapter *adap, int idx, u32 addr,
584 __be32 *data, u64 *parity);
585 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
586 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
588 void t4_idma_monitor_init(struct adapter *adapter,
589 struct sge_idma_monitor_state *idma);
590 void t4_idma_monitor(struct adapter *adapter,
591 struct sge_idma_monitor_state *idma,
594 unsigned int t4_get_regs_len(struct adapter *adapter);
595 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size);
597 const char *t4_get_port_type_description(enum fw_port_type port_type);
598 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
599 void t4_get_port_stats_offset(struct adapter *adap, int idx,
600 struct port_stats *stats,
601 struct port_stats *offset);
602 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
603 void t4_clr_port_stats(struct adapter *adap, int idx);
605 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
606 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
607 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
608 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
610 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
611 unsigned int mask, unsigned int val);
612 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
613 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
614 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st);
615 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
616 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
617 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
618 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
619 struct tp_tcp_stats *v6);
620 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
621 struct tp_fcoe_stats *st);
622 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
623 const unsigned short *alpha, const unsigned short *beta);
625 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
627 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps);
628 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg);
629 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
630 unsigned int start, unsigned int n);
631 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
632 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map);
633 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
635 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
636 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
637 u64 mask0, u64 mask1, unsigned int crc, bool enable);
639 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
640 enum dev_master master, enum dev_state *state);
641 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
642 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
643 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
644 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
645 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
646 const u8 *fw_data, unsigned int size, int force);
647 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
648 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
649 unsigned int vf, unsigned int nparams, const u32 *params,
651 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
652 unsigned int vf, unsigned int nparams, const u32 *params,
654 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
655 unsigned int pf, unsigned int vf,
656 unsigned int nparams, const u32 *params,
657 const u32 *val, int timeout);
658 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
659 unsigned int vf, unsigned int nparams, const u32 *params,
661 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
662 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
663 unsigned int rxqi, unsigned int rxq, unsigned int tc,
664 unsigned int vi, unsigned int cmask, unsigned int pmask,
665 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
666 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
667 unsigned int port, unsigned int pf, unsigned int vf,
668 unsigned int nmac, u8 *mac, u16 *rss_size,
669 unsigned int portfunc, unsigned int idstype);
670 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
671 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
673 int t4_free_vi(struct adapter *adap, unsigned int mbox,
674 unsigned int pf, unsigned int vf,
676 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
677 int mtu, int promisc, int all_multi, int bcast, int vlanex,
679 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
680 bool free, unsigned int naddr, const u8 **addr, u16 *idx,
681 u64 *hash, bool sleep_ok);
682 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
683 int idx, const u8 *addr, bool persist, bool add_smt);
684 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
685 bool ucast, u64 vec, bool sleep_ok);
686 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
687 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
688 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
689 bool rx_en, bool tx_en);
690 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
691 unsigned int nblinks);
692 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
693 unsigned int mmd, unsigned int reg, unsigned int *valp);
694 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
695 unsigned int mmd, unsigned int reg, unsigned int val);
696 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
697 int port, unsigned int devid,
698 unsigned int offset, unsigned int len,
700 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
701 int port, unsigned int devid,
702 unsigned int offset, unsigned int len,
704 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
705 unsigned int vf, unsigned int iqtype, unsigned int iqid,
706 unsigned int fl0id, unsigned int fl1id);
707 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
708 unsigned int vf, unsigned int iqtype, unsigned int iqid,
709 unsigned int fl0id, unsigned int fl1id);
710 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
711 unsigned int vf, unsigned int eqid);
712 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
713 unsigned int vf, unsigned int eqid);
714 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
715 unsigned int vf, unsigned int eqid);
716 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
717 enum ctxt_type ctype, u32 *data);
718 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
720 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
721 const char *t4_link_down_rc_str(unsigned char link_down_rc);
722 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
723 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
724 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
726 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
727 int rateunit, int ratemode, int channel, int cl,
728 int minrate, int maxrate, int weight, int pktsize,
730 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
731 unsigned int pf, unsigned int vf,
732 unsigned int timeout, unsigned int action);
733 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level);
734 int t4_set_devlog_level(struct adapter *adapter, unsigned int level);
735 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
736 #endif /* __CHELSIO_COMMON_H */