sys/dev/cxgbe/common/t4_hw.c

   1 /*-
   2  * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include "opt_inet.h"
  31
  32 #include "common.h"
  33 #include "t4_regs.h"
  34 #include "t4_regs_values.h"
  35 #include "firmware/t4fw_interface.h"
  36
  37 #undef msleep
  38 #define msleep(x) do { \
  39         if (cold) \
  40                 DELAY((x) * 1000); \
  41         else \
  42                 pause("t4hw", (x) * hz / 1000); \
  43 } while (0)
  44
  45 /**
  46  *      t4_wait_op_done_val - wait until an operation is completed
  47  *      @adapter: the adapter performing the operation
  48  *      @reg: the register to check for completion
  49  *      @mask: a single-bit field within @reg that indicates completion
  50  *      @polarity: the value of the field when the operation is completed
  51  *      @attempts: number of check iterations
  52  *      @delay: delay in usecs between iterations
  53  *      @valp: where to store the value of the register at completion time
  54  *
  55  *      Wait until an operation is completed by checking a bit in a register
  56  *      up to @attempts times.  If @valp is not NULL the value of the register
  57  *      at the time it indicated completion is stored there.  Returns 0 if the
  58  *      operation completes and -EAGAIN otherwise.
  59  */
  60 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  61                                int polarity, int attempts, int delay, u32 *valp)
  62 {
  63         while (1) {
  64                 u32 val = t4_read_reg(adapter, reg);
  65
  66                 if (!!(val & mask) == polarity) {
  67                         if (valp)
  68                                 *valp = val;
  69                         return 0;
  70                 }
  71                 if (--attempts == 0)
  72                         return -EAGAIN;
  73                 if (delay)
  74                         udelay(delay);
  75         }
  76 }
  77
  78 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  79                                   int polarity, int attempts, int delay)
  80 {
  81         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  82                                    delay, NULL);
  83 }
  84
  85 /**
  86  *      t4_set_reg_field - set a register field to a value
  87  *      @adapter: the adapter to program
  88  *      @addr: the register address
  89  *      @mask: specifies the portion of the register to modify
  90  *      @val: the new value for the register field
  91  *
  92  *      Sets a register field specified by the supplied mask to the
  93  *      given value.
  94  */
  95 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  96                       u32 val)
  97 {
  98         u32 v = t4_read_reg(adapter, addr) & ~mask;
  99
 100         t4_write_reg(adapter, addr, v | val);
 101         (void) t4_read_reg(adapter, addr);      /* flush */
 102 }
 103
 104 /**
 105  *      t4_read_indirect - read indirectly addressed registers
 106  *      @adap: the adapter
 107  *      @addr_reg: register holding the indirect address
 108  *      @data_reg: register holding the value of the indirect register
 109  *      @vals: where the read register values are stored
 110  *      @nregs: how many indirect registers to read
 111  *      @start_idx: index of first indirect register to read
 112  *
 113  *      Reads registers that are accessed indirectly through an address/data
 114  *      register pair.
 115  */
 116 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 117                              unsigned int data_reg, u32 *vals,
 118                              unsigned int nregs, unsigned int start_idx)
 119 {
 120         while (nregs--) {
 121                 t4_write_reg(adap, addr_reg, start_idx);
 122                 *vals++ = t4_read_reg(adap, data_reg);
 123                 start_idx++;
 124         }
 125 }
 126
 127 /**
 128  *      t4_write_indirect - write indirectly addressed registers
 129  *      @adap: the adapter
 130  *      @addr_reg: register holding the indirect addresses
 131  *      @data_reg: register holding the value for the indirect registers
 132  *      @vals: values to write
 133  *      @nregs: how many indirect registers to write
 134  *      @start_idx: address of first indirect register to write
 135  *
 136  *      Writes a sequential block of registers that are accessed indirectly
 137  *      through an address/data register pair.
 138  */
 139 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 140                        unsigned int data_reg, const u32 *vals,
 141                        unsigned int nregs, unsigned int start_idx)
 142 {
 143         while (nregs--) {
 144                 t4_write_reg(adap, addr_reg, start_idx++);
 145                 t4_write_reg(adap, data_reg, *vals++);
 146         }
 147 }
 148
 149 /*
 150  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 151  * mechanism.  This guarantees that we get the real value even if we're
 152  * operating within a Virtual Machine and the Hypervisor is trapping our
 153  * Configuration Space accesses.
 154  *
 155  * N.B. This routine should only be used as a last resort: the firmware uses
 156  *      the backdoor registers on a regular basis and we can end up
 157  *      conflicting with it's uses!
 158  */
 159 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
 160 {
 161         u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
 162         u32 val;
 163
 164         if (chip_id(adap) <= CHELSIO_T5)
 165                 req |= F_ENABLE;
 166         else
 167                 req |= F_T6_ENABLE;
 168
 169         if (is_t4(adap))
 170                 req |= F_LOCALCFG;
 171
 172         t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
 173         val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
 174
 175         /*
 176          * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 177          * Configuration Space read.  (None of the other fields matter when
 178          * F_ENABLE is 0 so a simple register write is easier than a
 179          * read-modify-write via t4_set_reg_field().)
 180          */
 181         t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
 182
 183         return val;
 184 }
 185
 186 /*
 187  * t4_report_fw_error - report firmware error
 188  * @adap: the adapter
 189  *
 190  * The adapter firmware can indicate error conditions to the host.
 191  * If the firmware has indicated an error, print out the reason for
 192  * the firmware error.
 193  */
 194 static void t4_report_fw_error(struct adapter *adap)
 195 {
 196         static const char *const reason[] = {
 197                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 198                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 199                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 200                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 201                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 202                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 203                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 204                 "Reserved",                     /* reserved */
 205         };
 206         u32 pcie_fw;
 207
 208         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 209         if (pcie_fw & F_PCIE_FW_ERR)
 210                 CH_ERR(adap, "Firmware reports adapter error: %s\n",
 211                         reason[G_PCIE_FW_EVAL(pcie_fw)]);
 212 }
 213
 214 /*
 215  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 216  */
 217 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 218                          u32 mbox_addr)
 219 {
 220         for ( ; nflit; nflit--, mbox_addr += 8)
 221                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 222 }
 223
 224 /*
 225  * Handle a FW assertion reported in a mailbox.
 226  */
 227 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
 228 {
 229         CH_ALERT(adap,
 230                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 231                   asrt->u.assert.filename_0_7,
 232                   be32_to_cpu(asrt->u.assert.line),
 233                   be32_to_cpu(asrt->u.assert.x),
 234                   be32_to_cpu(asrt->u.assert.y));
 235 }
 236
 237 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 238 /**
 239  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 240  *      @adap: the adapter
 241  *      @mbox: index of the mailbox to use
 242  *      @cmd: the command to write
 243  *      @size: command length in bytes
 244  *      @rpl: where to optionally store the reply
 245  *      @sleep_ok: if true we may sleep while awaiting command completion
 246  *      @timeout: time to wait for command to finish before timing out
 247  *              (negative implies @sleep_ok=false)
 248  *
 249  *      Sends the given command to FW through the selected mailbox and waits
 250  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 251  *      store the FW's reply to the command.  The command and its optional
 252  *      reply are of the same length.  Some FW commands like RESET and
 253  *      INITIALIZE can take a considerable amount of time to execute.
 254  *      @sleep_ok determines whether we may sleep while awaiting the response.
 255  *      If sleeping is allowed we use progressive backoff otherwise we spin.
 256  *      Note that passing in a negative @timeout is an alternate mechanism
 257  *      for specifying @sleep_ok=false.  This is useful when a higher level
 258  *      interface allows for specification of @timeout but not @sleep_ok ...
 259  *
 260  *      The return value is 0 on success or a negative errno on failure.  A
 261  *      failure can happen either because we are not able to execute the
 262  *      command or FW executes it but signals an error.  In the latter case
 263  *      the return value is the error code indicated by FW (negated).
 264  */
 265 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 266                             int size, void *rpl, bool sleep_ok, int timeout)
 267 {
 268         /*
 269          * We delay in small increments at first in an effort to maintain
 270          * responsiveness for simple, fast executing commands but then back
 271          * off to larger delays to a maximum retry delay.
 272          */
 273         static const int delay[] = {
 274                 1, 1, 3, 5, 10, 10, 20, 50, 100
 275         };
 276         u32 v;
 277         u64 res;
 278         int i, ms, delay_idx, ret;
 279         const __be64 *p = cmd;
 280         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 281         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 282         u32 ctl;
 283         __be64 cmd_rpl[MBOX_LEN/8];
 284         u32 pcie_fw;
 285
 286         if ((size & 15) || size > MBOX_LEN)
 287                 return -EINVAL;
 288
 289         /*
 290          * If we have a negative timeout, that implies that we can't sleep.
 291          */
 292         if (timeout < 0) {
 293                 sleep_ok = false;
 294                 timeout = -timeout;
 295         }
 296
 297         /*
 298          * Attempt to gain access to the mailbox.
 299          */
 300         for (i = 0; i < 4; i++) {
 301                 ctl = t4_read_reg(adap, ctl_reg);
 302                 v = G_MBOWNER(ctl);
 303                 if (v != X_MBOWNER_NONE)
 304                         break;
 305         }
 306
 307         /*
 308          * If we were unable to gain access, dequeue ourselves from the
 309          * mailbox atomic access list and report the error to our caller.
 310          */
 311         if (v != X_MBOWNER_PL) {
 312                 t4_report_fw_error(adap);
 313                 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
 314                 return ret;
 315         }
 316
 317         /*
 318          * If we gain ownership of the mailbox and there's a "valid" message
 319          * in it, this is likely an asynchronous error message from the
 320          * firmware.  So we'll report that and then proceed on with attempting
 321          * to issue our own command ... which may well fail if the error
 322          * presaged the firmware crashing ...
 323          */
 324         if (ctl & F_MBMSGVALID) {
 325                 CH_ERR(adap, "found VALID command in mbox %u: "
 326                        "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 327                        (unsigned long long)t4_read_reg64(adap, data_reg),
 328                        (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 329                        (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 330                        (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 331                        (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 332                        (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 333                        (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 334                        (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 335         }
 336
 337         /*
 338          * Copy in the new mailbox command and send it on its way ...
 339          */
 340         for (i = 0; i < size; i += 8, p++)
 341                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 342
 343         CH_DUMP_MBOX(adap, mbox, data_reg);
 344
 345         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 346         t4_read_reg(adap, ctl_reg);     /* flush write */
 347
 348         delay_idx = 0;
 349         ms = delay[0];
 350
 351         /*
 352          * Loop waiting for the reply; bail out if we time out or the firmware
 353          * reports an error.
 354          */
 355         for (i = 0;
 356              !((pcie_fw = t4_read_reg(adap, A_PCIE_FW)) & F_PCIE_FW_ERR) &&
 357              i < timeout;
 358              i += ms) {
 359                 if (sleep_ok) {
 360                         ms = delay[delay_idx];  /* last element may repeat */
 361                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 362                                 delay_idx++;
 363                         msleep(ms);
 364                 } else {
 365                         mdelay(ms);
 366                 }
 367
 368                 v = t4_read_reg(adap, ctl_reg);
 369                 if (v == X_CIM_PF_NOACCESS)
 370                         continue;
 371                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 372                         if (!(v & F_MBMSGVALID)) {
 373                                 t4_write_reg(adap, ctl_reg,
 374                                              V_MBOWNER(X_MBOWNER_NONE));
 375                                 continue;
 376                         }
 377
 378                         /*
 379                          * Retrieve the command reply and release the mailbox.
 380                          */
 381                         get_mbox_rpl(adap, cmd_rpl, size/8, data_reg);
 382                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 383
 384                         CH_DUMP_MBOX(adap, mbox, data_reg);
 385
 386                         res = be64_to_cpu(cmd_rpl[0]);
 387                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 388                                 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
 389                                 res = V_FW_CMD_RETVAL(EIO);
 390                         } else if (rpl)
 391                                 memcpy(rpl, cmd_rpl, size);
 392                         return -G_FW_CMD_RETVAL((int)res);
 393                 }
 394         }
 395
 396         /*
 397          * We timed out waiting for a reply to our mailbox command.  Report
 398          * the error and also check to see if the firmware reported any
 399          * errors ...
 400          */
 401         ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 402         CH_ERR(adap, "command %#x in mailbox %d timed out\n",
 403                *(const u8 *)cmd, mbox);
 404
 405         t4_report_fw_error(adap);
 406         t4_fatal_err(adap);
 407         return ret;
 408 }
 409
 410 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 411                     void *rpl, bool sleep_ok)
 412 {
 413                 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
 414                                                sleep_ok, FW_CMD_MAX_TIMEOUT);
 415
 416 }
 417
 418 static int t4_edc_err_read(struct adapter *adap, int idx)
 419 {
 420         u32 edc_ecc_err_addr_reg;
 421         u32 edc_bist_status_rdata_reg;
 422
 423         if (is_t4(adap)) {
 424                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 425                 return 0;
 426         }
 427         if (idx != 0 && idx != 1) {
 428                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 429                 return 0;
 430         }
 431
 432         edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
 433         edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
 434
 435         CH_WARN(adap,
 436                 "edc%d err addr 0x%x: 0x%x.\n",
 437                 idx, edc_ecc_err_addr_reg,
 438                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 439         CH_WARN(adap,
 440                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 441                 edc_bist_status_rdata_reg,
 442                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
 443                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
 444                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
 445                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
 446                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
 447                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
 448                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
 449                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
 450                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
 451
 452         return 0;
 453 }
 454
 455 /**
 456  *      t4_mc_read - read from MC through backdoor accesses
 457  *      @adap: the adapter
 458  *      @idx: which MC to access
 459  *      @addr: address of first byte requested
 460  *      @data: 64 bytes of data containing the requested address
 461  *      @ecc: where to store the corresponding 64-bit ECC word
 462  *
 463  *      Read 64 bytes of data from MC starting at a 64-byte-aligned address
 464  *      that covers the requested address @addr.  If @parity is not %NULL it
 465  *      is assigned the 64-bit ECC word for the read data.
 466  */
 467 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
 468 {
 469         int i;
 470         u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
 471         u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
 472
 473         if (is_t4(adap)) {
 474                 mc_bist_cmd_reg = A_MC_BIST_CMD;
 475                 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
 476                 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
 477                 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
 478                 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
 479         } else {
 480                 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
 481                 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
 482                 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
 483                 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
 484                                                   idx);
 485                 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
 486                                                   idx);
 487         }
 488
 489         if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
 490                 return -EBUSY;
 491         t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
 492         t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
 493         t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
 494         t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
 495                      F_START_BIST | V_BIST_CMD_GAP(1));
 496         i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
 497         if (i)
 498                 return i;
 499
 500 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
 501
 502         for (i = 15; i >= 0; i--)
 503                 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
 504         if (ecc)
 505                 *ecc = t4_read_reg64(adap, MC_DATA(16));
 506 #undef MC_DATA
 507         return 0;
 508 }
 509
 510 /**
 511  *      t4_edc_read - read from EDC through backdoor accesses
 512  *      @adap: the adapter
 513  *      @idx: which EDC to access
 514  *      @addr: address of first byte requested
 515  *      @data: 64 bytes of data containing the requested address
 516  *      @ecc: where to store the corresponding 64-bit ECC word
 517  *
 518  *      Read 64 bytes of data from EDC starting at a 64-byte-aligned address
 519  *      that covers the requested address @addr.  If @parity is not %NULL it
 520  *      is assigned the 64-bit ECC word for the read data.
 521  */
 522 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
 523 {
 524         int i;
 525         u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
 526         u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
 527
 528         if (is_t4(adap)) {
 529                 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
 530                 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
 531                 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
 532                 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
 533                                                     idx);
 534                 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
 535                                                     idx);
 536         } else {
 537 /*
 538  * These macro are missing in t4_regs.h file.
 539  * Added temporarily for testing.
 540  */
 541 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
 542 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
 543                 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
 544                 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
 545                 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
 546                 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
 547                                                     idx);
 548                 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
 549                                                     idx);
 550 #undef EDC_REG_T5
 551 #undef EDC_STRIDE_T5
 552         }
 553
 554         if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
 555                 return -EBUSY;
 556         t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
 557         t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
 558         t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
 559         t4_write_reg(adap, edc_bist_cmd_reg,
 560                      V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
 561         i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
 562         if (i)
 563                 return i;
 564
 565 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
 566
 567         for (i = 15; i >= 0; i--)
 568                 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
 569         if (ecc)
 570                 *ecc = t4_read_reg64(adap, EDC_DATA(16));
 571 #undef EDC_DATA
 572         return 0;
 573 }
 574
 575 /**
 576  *      t4_mem_read - read EDC 0, EDC 1 or MC into buffer
 577  *      @adap: the adapter
 578  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 579  *      @addr: address within indicated memory type
 580  *      @len: amount of memory to read
 581  *      @buf: host memory buffer
 582  *
 583  *      Reads an [almost] arbitrary memory region in the firmware: the
 584  *      firmware memory address, length and host buffer must be aligned on
 585  *      32-bit boudaries.  The memory is returned as a raw byte sequence from
 586  *      the firmware's memory.  If this memory contains data structures which
 587  *      contain multi-byte integers, it's the callers responsibility to
 588  *      perform appropriate byte order conversions.
 589  */
 590 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
 591                 __be32 *buf)
 592 {
 593         u32 pos, start, end, offset;
 594         int ret;
 595
 596         /*
 597          * Argument sanity checks ...
 598          */
 599         if ((addr & 0x3) || (len & 0x3))
 600                 return -EINVAL;
 601
 602         /*
 603          * The underlaying EDC/MC read routines read 64 bytes at a time so we
 604          * need to round down the start and round up the end.  We'll start
 605          * copying out of the first line at (addr - start) a word at a time.
 606          */
 607         start = addr & ~(64-1);
 608         end = (addr + len + 64-1) & ~(64-1);
 609         offset = (addr - start)/sizeof(__be32);
 610
 611         for (pos = start; pos < end; pos += 64, offset = 0) {
 612                 __be32 data[16];
 613
 614                 /*
 615                  * Read the chip's memory block and bail if there's an error.
 616                  */
 617                 if ((mtype == MEM_MC) || (mtype == MEM_MC1))
 618                         ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
 619                 else
 620                         ret = t4_edc_read(adap, mtype, pos, data, NULL);
 621                 if (ret)
 622                         return ret;
 623
 624                 /*
 625                  * Copy the data into the caller's memory buffer.
 626                  */
 627                 while (offset < 16 && len > 0) {
 628                         *buf++ = data[offset++];
 629                         len -= sizeof(__be32);
 630                 }
 631         }
 632
 633         return 0;
 634 }
 635
 636 /*
 637  * Return the specified PCI-E Configuration Space register from our Physical
 638  * Function.  We try first via a Firmware LDST Command (if fw_attach != 0)
 639  * since we prefer to let the firmware own all of these registers, but if that
 640  * fails we go for it directly ourselves.
 641  */
 642 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
 643 {
 644
 645         /*
 646          * If fw_attach != 0, construct and send the Firmware LDST Command to
 647          * retrieve the specified PCI-E Configuration Space register.
 648          */
 649         if (drv_fw_attach != 0) {
 650                 struct fw_ldst_cmd ldst_cmd;
 651                 int ret;
 652
 653                 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 654                 ldst_cmd.op_to_addrspace =
 655                         cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
 656                                     F_FW_CMD_REQUEST |
 657                                     F_FW_CMD_READ |
 658                                     V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
 659                 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 660                 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
 661                 ldst_cmd.u.pcie.ctrl_to_fn =
 662                         (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
 663                 ldst_cmd.u.pcie.r = reg;
 664
 665                 /*
 666                  * If the LDST Command succeeds, return the result, otherwise
 667                  * fall through to reading it directly ourselves ...
 668                  */
 669                 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 670                                  &ldst_cmd);
 671                 if (ret == 0)
 672                         return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 673
 674                 CH_WARN(adap, "Firmware failed to return "
 675                         "Configuration Space register %d, err = %d\n",
 676                         reg, -ret);
 677         }
 678
 679         /*
 680          * Read the desired Configuration Space register via the PCI-E
 681          * Backdoor mechanism.
 682          */
 683         return t4_hw_pci_read_cfg4(adap, reg);
 684 }
 685
 686 /**
 687  *      t4_get_regs_len - return the size of the chips register set
 688  *      @adapter: the adapter
 689  *
 690  *      Returns the size of the chip's BAR0 register space.
 691  */
 692 unsigned int t4_get_regs_len(struct adapter *adapter)
 693 {
 694         unsigned int chip_version = chip_id(adapter);
 695
 696         switch (chip_version) {
 697         case CHELSIO_T4:
 698                 return T4_REGMAP_SIZE;
 699
 700         case CHELSIO_T5:
 701         case CHELSIO_T6:
 702                 return T5_REGMAP_SIZE;
 703         }
 704
 705         CH_ERR(adapter,
 706                 "Unsupported chip version %d\n", chip_version);
 707         return 0;
 708 }
 709
 710 /**
 711  *      t4_get_regs - read chip registers into provided buffer
 712  *      @adap: the adapter
 713  *      @buf: register buffer
 714  *      @buf_size: size (in bytes) of register buffer
 715  *
 716  *      If the provided register buffer isn't large enough for the chip's
 717  *      full register range, the register dump will be truncated to the
 718  *      register buffer's size.
 719  */
 720 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
 721 {
 722         static const unsigned int t4_reg_ranges[] = {
 723                 0x1008, 0x1108,
 724                 0x1180, 0x1184,
 725                 0x1190, 0x1194,
 726                 0x11a0, 0x11a4,
 727                 0x11b0, 0x11b4,
 728                 0x11fc, 0x123c,
 729                 0x1300, 0x173c,
 730                 0x1800, 0x18fc,
 731                 0x3000, 0x30d8,
 732                 0x30e0, 0x30e4,
 733                 0x30ec, 0x5910,
 734                 0x5920, 0x5924,
 735                 0x5960, 0x5960,
 736                 0x5968, 0x5968,
 737                 0x5970, 0x5970,
 738                 0x5978, 0x5978,
 739                 0x5980, 0x5980,
 740                 0x5988, 0x5988,
 741                 0x5990, 0x5990,
 742                 0x5998, 0x5998,
 743                 0x59a0, 0x59d4,
 744                 0x5a00, 0x5ae0,
 745                 0x5ae8, 0x5ae8,
 746                 0x5af0, 0x5af0,
 747                 0x5af8, 0x5af8,
 748                 0x6000, 0x6098,
 749                 0x6100, 0x6150,
 750                 0x6200, 0x6208,
 751                 0x6240, 0x6248,
 752                 0x6280, 0x62b0,
 753                 0x62c0, 0x6338,
 754                 0x6370, 0x638c,
 755                 0x6400, 0x643c,
 756                 0x6500, 0x6524,
 757                 0x6a00, 0x6a04,
 758                 0x6a14, 0x6a38,
 759                 0x6a60, 0x6a70,
 760                 0x6a78, 0x6a78,
 761                 0x6b00, 0x6b0c,
 762                 0x6b1c, 0x6b84,
 763                 0x6bf0, 0x6bf8,
 764                 0x6c00, 0x6c0c,
 765                 0x6c1c, 0x6c84,
 766                 0x6cf0, 0x6cf8,
 767                 0x6d00, 0x6d0c,
 768                 0x6d1c, 0x6d84,
 769                 0x6df0, 0x6df8,
 770                 0x6e00, 0x6e0c,
 771                 0x6e1c, 0x6e84,
 772                 0x6ef0, 0x6ef8,
 773                 0x6f00, 0x6f0c,
 774                 0x6f1c, 0x6f84,
 775                 0x6ff0, 0x6ff8,
 776                 0x7000, 0x700c,
 777                 0x701c, 0x7084,
 778                 0x70f0, 0x70f8,
 779                 0x7100, 0x710c,
 780                 0x711c, 0x7184,
 781                 0x71f0, 0x71f8,
 782                 0x7200, 0x720c,
 783                 0x721c, 0x7284,
 784                 0x72f0, 0x72f8,
 785                 0x7300, 0x730c,
 786                 0x731c, 0x7384,
 787                 0x73f0, 0x73f8,
 788                 0x7400, 0x7450,
 789                 0x7500, 0x7530,
 790                 0x7600, 0x760c,
 791                 0x7614, 0x761c,
 792                 0x7680, 0x76cc,
 793                 0x7700, 0x7798,
 794                 0x77c0, 0x77fc,
 795                 0x7900, 0x79fc,
 796                 0x7b00, 0x7b58,
 797                 0x7b60, 0x7b84,
 798                 0x7b8c, 0x7c38,
 799                 0x7d00, 0x7d38,
 800                 0x7d40, 0x7d80,
 801                 0x7d8c, 0x7ddc,
 802                 0x7de4, 0x7e04,
 803                 0x7e10, 0x7e1c,
 804                 0x7e24, 0x7e38,
 805                 0x7e40, 0x7e44,
 806                 0x7e4c, 0x7e78,
 807                 0x7e80, 0x7ea4,
 808                 0x7eac, 0x7edc,
 809                 0x7ee8, 0x7efc,
 810                 0x8dc0, 0x8e04,
 811                 0x8e10, 0x8e1c,
 812                 0x8e30, 0x8e78,
 813                 0x8ea0, 0x8eb8,
 814                 0x8ec0, 0x8f6c,
 815                 0x8fc0, 0x9008,
 816                 0x9010, 0x9058,
 817                 0x9060, 0x9060,
 818                 0x9068, 0x9074,
 819                 0x90fc, 0x90fc,
 820                 0x9400, 0x9408,
 821                 0x9410, 0x9458,
 822                 0x9600, 0x9600,
 823                 0x9608, 0x9638,
 824                 0x9640, 0x96bc,
 825                 0x9800, 0x9808,
 826                 0x9820, 0x983c,
 827                 0x9850, 0x9864,
 828                 0x9c00, 0x9c6c,
 829                 0x9c80, 0x9cec,
 830                 0x9d00, 0x9d6c,
 831                 0x9d80, 0x9dec,
 832                 0x9e00, 0x9e6c,
 833                 0x9e80, 0x9eec,
 834                 0x9f00, 0x9f6c,
 835                 0x9f80, 0x9fec,
 836                 0xd004, 0xd004,
 837                 0xd010, 0xd03c,
 838                 0xdfc0, 0xdfe0,
 839                 0xe000, 0xea7c,
 840                 0xf000, 0x11190,
 841                 0x19040, 0x1906c,
 842                 0x19078, 0x19080,
 843                 0x1908c, 0x190e4,
 844                 0x190f0, 0x190f8,
 845                 0x19100, 0x19110,
 846                 0x19120, 0x19124,
 847                 0x19150, 0x19194,
 848                 0x1919c, 0x191b0,
 849                 0x191d0, 0x191e8,
 850                 0x19238, 0x1924c,
 851                 0x193f8, 0x1943c,
 852                 0x1944c, 0x19474,
 853                 0x19490, 0x194e0,
 854                 0x194f0, 0x194f8,
 855                 0x19800, 0x19c08,
 856                 0x19c10, 0x19c90,
 857                 0x19ca0, 0x19ce4,
 858                 0x19cf0, 0x19d40,
 859                 0x19d50, 0x19d94,
 860                 0x19da0, 0x19de8,
 861                 0x19df0, 0x19e40,
 862                 0x19e50, 0x19e90,
 863                 0x19ea0, 0x19f4c,
 864                 0x1a000, 0x1a004,
 865                 0x1a010, 0x1a06c,
 866                 0x1a0b0, 0x1a0e4,
 867                 0x1a0ec, 0x1a0f4,
 868                 0x1a100, 0x1a108,
 869                 0x1a114, 0x1a120,
 870                 0x1a128, 0x1a130,
 871                 0x1a138, 0x1a138,
 872                 0x1a190, 0x1a1c4,
 873                 0x1a1fc, 0x1a1fc,
 874                 0x1e040, 0x1e04c,
 875                 0x1e284, 0x1e28c,
 876                 0x1e2c0, 0x1e2c0,
 877                 0x1e2e0, 0x1e2e0,
 878                 0x1e300, 0x1e384,
 879                 0x1e3c0, 0x1e3c8,
 880                 0x1e440, 0x1e44c,
 881                 0x1e684, 0x1e68c,
 882                 0x1e6c0, 0x1e6c0,
 883                 0x1e6e0, 0x1e6e0,
 884                 0x1e700, 0x1e784,
 885                 0x1e7c0, 0x1e7c8,
 886                 0x1e840, 0x1e84c,
 887                 0x1ea84, 0x1ea8c,
 888                 0x1eac0, 0x1eac0,
 889                 0x1eae0, 0x1eae0,
 890                 0x1eb00, 0x1eb84,
 891                 0x1ebc0, 0x1ebc8,
 892                 0x1ec40, 0x1ec4c,
 893                 0x1ee84, 0x1ee8c,
 894                 0x1eec0, 0x1eec0,
 895                 0x1eee0, 0x1eee0,
 896                 0x1ef00, 0x1ef84,
 897                 0x1efc0, 0x1efc8,
 898                 0x1f040, 0x1f04c,
 899                 0x1f284, 0x1f28c,
 900                 0x1f2c0, 0x1f2c0,
 901                 0x1f2e0, 0x1f2e0,
 902                 0x1f300, 0x1f384,
 903                 0x1f3c0, 0x1f3c8,
 904                 0x1f440, 0x1f44c,
 905                 0x1f684, 0x1f68c,
 906                 0x1f6c0, 0x1f6c0,
 907                 0x1f6e0, 0x1f6e0,
 908                 0x1f700, 0x1f784,
 909                 0x1f7c0, 0x1f7c8,
 910                 0x1f840, 0x1f84c,
 911                 0x1fa84, 0x1fa8c,
 912                 0x1fac0, 0x1fac0,
 913                 0x1fae0, 0x1fae0,
 914                 0x1fb00, 0x1fb84,
 915                 0x1fbc0, 0x1fbc8,
 916                 0x1fc40, 0x1fc4c,
 917                 0x1fe84, 0x1fe8c,
 918                 0x1fec0, 0x1fec0,
 919                 0x1fee0, 0x1fee0,
 920                 0x1ff00, 0x1ff84,
 921                 0x1ffc0, 0x1ffc8,
 922                 0x20000, 0x2002c,
 923                 0x20100, 0x2013c,
 924                 0x20190, 0x201a0,
 925                 0x201a8, 0x201b8,
 926                 0x201c4, 0x201c8,
 927                 0x20200, 0x20318,
 928                 0x20400, 0x204b4,
 929                 0x204c0, 0x20528,
 930                 0x20540, 0x20614,
 931                 0x21000, 0x21040,
 932                 0x2104c, 0x21060,
 933                 0x210c0, 0x210ec,
 934                 0x21200, 0x21268,
 935                 0x21270, 0x21284,
 936                 0x212fc, 0x21388,
 937                 0x21400, 0x21404,
 938                 0x21500, 0x21500,
 939                 0x21510, 0x21518,
 940                 0x2152c, 0x21530,
 941                 0x2153c, 0x2153c,
 942                 0x21550, 0x21554,
 943                 0x21600, 0x21600,
 944                 0x21608, 0x2161c,
 945                 0x21624, 0x21628,
 946                 0x21630, 0x21634,
 947                 0x2163c, 0x2163c,
 948                 0x21700, 0x2171c,
 949                 0x21780, 0x2178c,
 950                 0x21800, 0x21818,
 951                 0x21820, 0x21828,
 952                 0x21830, 0x21848,
 953                 0x21850, 0x21854,
 954                 0x21860, 0x21868,
 955                 0x21870, 0x21870,
 956                 0x21878, 0x21898,
 957                 0x218a0, 0x218a8,
 958                 0x218b0, 0x218c8,
 959                 0x218d0, 0x218d4,
 960                 0x218e0, 0x218e8,
 961                 0x218f0, 0x218f0,
 962                 0x218f8, 0x21a18,
 963                 0x21a20, 0x21a28,
 964                 0x21a30, 0x21a48,
 965                 0x21a50, 0x21a54,
 966                 0x21a60, 0x21a68,
 967                 0x21a70, 0x21a70,
 968                 0x21a78, 0x21a98,
 969                 0x21aa0, 0x21aa8,
 970                 0x21ab0, 0x21ac8,
 971                 0x21ad0, 0x21ad4,
 972                 0x21ae0, 0x21ae8,
 973                 0x21af0, 0x21af0,
 974                 0x21af8, 0x21c18,
 975                 0x21c20, 0x21c20,
 976                 0x21c28, 0x21c30,
 977                 0x21c38, 0x21c38,
 978                 0x21c80, 0x21c98,
 979                 0x21ca0, 0x21ca8,
 980                 0x21cb0, 0x21cc8,
 981                 0x21cd0, 0x21cd4,
 982                 0x21ce0, 0x21ce8,
 983                 0x21cf0, 0x21cf0,
 984                 0x21cf8, 0x21d7c,
 985                 0x21e00, 0x21e04,
 986                 0x22000, 0x2202c,
 987                 0x22100, 0x2213c,
 988                 0x22190, 0x221a0,
 989                 0x221a8, 0x221b8,
 990                 0x221c4, 0x221c8,
 991                 0x22200, 0x22318,
 992                 0x22400, 0x224b4,
 993                 0x224c0, 0x22528,
 994                 0x22540, 0x22614,
 995                 0x23000, 0x23040,
 996                 0x2304c, 0x23060,
 997                 0x230c0, 0x230ec,
 998                 0x23200, 0x23268,
 999                 0x23270, 0x23284,
1000                 0x232fc, 0x23388,
1001                 0x23400, 0x23404,
1002                 0x23500, 0x23500,
1003                 0x23510, 0x23518,
1004                 0x2352c, 0x23530,
1005                 0x2353c, 0x2353c,
1006                 0x23550, 0x23554,
1007                 0x23600, 0x23600,
1008                 0x23608, 0x2361c,
1009                 0x23624, 0x23628,
1010                 0x23630, 0x23634,
1011                 0x2363c, 0x2363c,
1012                 0x23700, 0x2371c,
1013                 0x23780, 0x2378c,
1014                 0x23800, 0x23818,
1015                 0x23820, 0x23828,
1016                 0x23830, 0x23848,
1017                 0x23850, 0x23854,
1018                 0x23860, 0x23868,
1019                 0x23870, 0x23870,
1020                 0x23878, 0x23898,
1021                 0x238a0, 0x238a8,
1022                 0x238b0, 0x238c8,
1023                 0x238d0, 0x238d4,
1024                 0x238e0, 0x238e8,
1025                 0x238f0, 0x238f0,
1026                 0x238f8, 0x23a18,
1027                 0x23a20, 0x23a28,
1028                 0x23a30, 0x23a48,
1029                 0x23a50, 0x23a54,
1030                 0x23a60, 0x23a68,
1031                 0x23a70, 0x23a70,
1032                 0x23a78, 0x23a98,
1033                 0x23aa0, 0x23aa8,
1034                 0x23ab0, 0x23ac8,
1035                 0x23ad0, 0x23ad4,
1036                 0x23ae0, 0x23ae8,
1037                 0x23af0, 0x23af0,
1038                 0x23af8, 0x23c18,
1039                 0x23c20, 0x23c20,
1040                 0x23c28, 0x23c30,
1041                 0x23c38, 0x23c38,
1042                 0x23c80, 0x23c98,
1043                 0x23ca0, 0x23ca8,
1044                 0x23cb0, 0x23cc8,
1045                 0x23cd0, 0x23cd4,
1046                 0x23ce0, 0x23ce8,
1047                 0x23cf0, 0x23cf0,
1048                 0x23cf8, 0x23d7c,
1049                 0x23e00, 0x23e04,
1050                 0x24000, 0x2402c,
1051                 0x24100, 0x2413c,
1052                 0x24190, 0x241a0,
1053                 0x241a8, 0x241b8,
1054                 0x241c4, 0x241c8,
1055                 0x24200, 0x24318,
1056                 0x24400, 0x244b4,
1057                 0x244c0, 0x24528,
1058                 0x24540, 0x24614,
1059                 0x25000, 0x25040,
1060                 0x2504c, 0x25060,
1061                 0x250c0, 0x250ec,
1062                 0x25200, 0x25268,
1063                 0x25270, 0x25284,
1064                 0x252fc, 0x25388,
1065                 0x25400, 0x25404,
1066                 0x25500, 0x25500,
1067                 0x25510, 0x25518,
1068                 0x2552c, 0x25530,
1069                 0x2553c, 0x2553c,
1070                 0x25550, 0x25554,
1071                 0x25600, 0x25600,
1072                 0x25608, 0x2561c,
1073                 0x25624, 0x25628,
1074                 0x25630, 0x25634,
1075                 0x2563c, 0x2563c,
1076                 0x25700, 0x2571c,
1077                 0x25780, 0x2578c,
1078                 0x25800, 0x25818,
1079                 0x25820, 0x25828,
1080                 0x25830, 0x25848,
1081                 0x25850, 0x25854,
1082                 0x25860, 0x25868,
1083                 0x25870, 0x25870,
1084                 0x25878, 0x25898,
1085                 0x258a0, 0x258a8,
1086                 0x258b0, 0x258c8,
1087                 0x258d0, 0x258d4,
1088                 0x258e0, 0x258e8,
1089                 0x258f0, 0x258f0,
1090                 0x258f8, 0x25a18,
1091                 0x25a20, 0x25a28,
1092                 0x25a30, 0x25a48,
1093                 0x25a50, 0x25a54,
1094                 0x25a60, 0x25a68,
1095                 0x25a70, 0x25a70,
1096                 0x25a78, 0x25a98,
1097                 0x25aa0, 0x25aa8,
1098                 0x25ab0, 0x25ac8,
1099                 0x25ad0, 0x25ad4,
1100                 0x25ae0, 0x25ae8,
1101                 0x25af0, 0x25af0,
1102                 0x25af8, 0x25c18,
1103                 0x25c20, 0x25c20,
1104                 0x25c28, 0x25c30,
1105                 0x25c38, 0x25c38,
1106                 0x25c80, 0x25c98,
1107                 0x25ca0, 0x25ca8,
1108                 0x25cb0, 0x25cc8,
1109                 0x25cd0, 0x25cd4,
1110                 0x25ce0, 0x25ce8,
1111                 0x25cf0, 0x25cf0,
1112                 0x25cf8, 0x25d7c,
1113                 0x25e00, 0x25e04,
1114                 0x26000, 0x2602c,
1115                 0x26100, 0x2613c,
1116                 0x26190, 0x261a0,
1117                 0x261a8, 0x261b8,
1118                 0x261c4, 0x261c8,
1119                 0x26200, 0x26318,
1120                 0x26400, 0x264b4,
1121                 0x264c0, 0x26528,
1122                 0x26540, 0x26614,
1123                 0x27000, 0x27040,
1124                 0x2704c, 0x27060,
1125                 0x270c0, 0x270ec,
1126                 0x27200, 0x27268,
1127                 0x27270, 0x27284,
1128                 0x272fc, 0x27388,
1129                 0x27400, 0x27404,
1130                 0x27500, 0x27500,
1131                 0x27510, 0x27518,
1132                 0x2752c, 0x27530,
1133                 0x2753c, 0x2753c,
1134                 0x27550, 0x27554,
1135                 0x27600, 0x27600,
1136                 0x27608, 0x2761c,
1137                 0x27624, 0x27628,
1138                 0x27630, 0x27634,
1139                 0x2763c, 0x2763c,
1140                 0x27700, 0x2771c,
1141                 0x27780, 0x2778c,
1142                 0x27800, 0x27818,
1143                 0x27820, 0x27828,
1144                 0x27830, 0x27848,
1145                 0x27850, 0x27854,
1146                 0x27860, 0x27868,
1147                 0x27870, 0x27870,
1148                 0x27878, 0x27898,
1149                 0x278a0, 0x278a8,
1150                 0x278b0, 0x278c8,
1151                 0x278d0, 0x278d4,
1152                 0x278e0, 0x278e8,
1153                 0x278f0, 0x278f0,
1154                 0x278f8, 0x27a18,
1155                 0x27a20, 0x27a28,
1156                 0x27a30, 0x27a48,
1157                 0x27a50, 0x27a54,
1158                 0x27a60, 0x27a68,
1159                 0x27a70, 0x27a70,
1160                 0x27a78, 0x27a98,
1161                 0x27aa0, 0x27aa8,
1162                 0x27ab0, 0x27ac8,
1163                 0x27ad0, 0x27ad4,
1164                 0x27ae0, 0x27ae8,
1165                 0x27af0, 0x27af0,
1166                 0x27af8, 0x27c18,
1167                 0x27c20, 0x27c20,
1168                 0x27c28, 0x27c30,
1169                 0x27c38, 0x27c38,
1170                 0x27c80, 0x27c98,
1171                 0x27ca0, 0x27ca8,
1172                 0x27cb0, 0x27cc8,
1173                 0x27cd0, 0x27cd4,
1174                 0x27ce0, 0x27ce8,
1175                 0x27cf0, 0x27cf0,
1176                 0x27cf8, 0x27d7c,
1177                 0x27e00, 0x27e04,
1178         };
1179
1180         static const unsigned int t5_reg_ranges[] = {
1181                 0x1008, 0x10c0,
1182                 0x10cc, 0x10f8,
1183                 0x1100, 0x1100,
1184                 0x110c, 0x1148,
1185                 0x1180, 0x1184,
1186                 0x1190, 0x1194,
1187                 0x11a0, 0x11a4,
1188                 0x11b0, 0x11b4,
1189                 0x11fc, 0x123c,
1190                 0x1280, 0x173c,
1191                 0x1800, 0x18fc,
1192                 0x3000, 0x3028,
1193                 0x3060, 0x30b0,
1194                 0x30b8, 0x30d8,
1195                 0x30e0, 0x30fc,
1196                 0x3140, 0x357c,
1197                 0x35a8, 0x35cc,
1198                 0x35ec, 0x35ec,
1199                 0x3600, 0x5624,
1200                 0x56cc, 0x56ec,
1201                 0x56f4, 0x5720,
1202                 0x5728, 0x575c,
1203                 0x580c, 0x5814,
1204                 0x5890, 0x589c,
1205                 0x58a4, 0x58ac,
1206                 0x58b8, 0x58bc,
1207                 0x5940, 0x59c8,
1208                 0x59d0, 0x59dc,
1209                 0x59fc, 0x5a18,
1210                 0x5a60, 0x5a70,
1211                 0x5a80, 0x5a9c,
1212                 0x5b94, 0x5bfc,
1213                 0x6000, 0x6020,
1214                 0x6028, 0x6040,
1215                 0x6058, 0x609c,
1216                 0x60a8, 0x614c,
1217                 0x7700, 0x7798,
1218                 0x77c0, 0x78fc,
1219                 0x7b00, 0x7b58,
1220                 0x7b60, 0x7b84,
1221                 0x7b8c, 0x7c54,
1222                 0x7d00, 0x7d38,
1223                 0x7d40, 0x7d80,
1224                 0x7d8c, 0x7ddc,
1225                 0x7de4, 0x7e04,
1226                 0x7e10, 0x7e1c,
1227                 0x7e24, 0x7e38,
1228                 0x7e40, 0x7e44,
1229                 0x7e4c, 0x7e78,
1230                 0x7e80, 0x7edc,
1231                 0x7ee8, 0x7efc,
1232                 0x8dc0, 0x8de0,
1233                 0x8df8, 0x8e04,
1234                 0x8e10, 0x8e84,
1235                 0x8ea0, 0x8f84,
1236                 0x8fc0, 0x9058,
1237                 0x9060, 0x9060,
1238                 0x9068, 0x90f8,
1239                 0x9400, 0x9408,
1240                 0x9410, 0x9470,
1241                 0x9600, 0x9600,
1242                 0x9608, 0x9638,
1243                 0x9640, 0x96f4,
1244                 0x9800, 0x9808,
1245                 0x9820, 0x983c,
1246                 0x9850, 0x9864,
1247                 0x9c00, 0x9c6c,
1248                 0x9c80, 0x9cec,
1249                 0x9d00, 0x9d6c,
1250                 0x9d80, 0x9dec,
1251                 0x9e00, 0x9e6c,
1252                 0x9e80, 0x9eec,
1253                 0x9f00, 0x9f6c,
1254                 0x9f80, 0xa020,
1255                 0xd004, 0xd004,
1256                 0xd010, 0xd03c,
1257                 0xdfc0, 0xdfe0,
1258                 0xe000, 0x1106c,
1259                 0x11074, 0x11088,
1260                 0x1109c, 0x1117c,
1261                 0x11190, 0x11204,
1262                 0x19040, 0x1906c,
1263                 0x19078, 0x19080,
1264                 0x1908c, 0x190e8,
1265                 0x190f0, 0x190f8,
1266                 0x19100, 0x19110,
1267                 0x19120, 0x19124,
1268                 0x19150, 0x19194,
1269                 0x1919c, 0x191b0,
1270                 0x191d0, 0x191e8,
1271                 0x19238, 0x19290,
1272                 0x193f8, 0x19428,
1273                 0x19430, 0x19444,
1274                 0x1944c, 0x1946c,
1275                 0x19474, 0x19474,
1276                 0x19490, 0x194cc,
1277                 0x194f0, 0x194f8,
1278                 0x19c00, 0x19c08,
1279                 0x19c10, 0x19c60,
1280                 0x19c94, 0x19ce4,
1281                 0x19cf0, 0x19d40,
1282                 0x19d50, 0x19d94,
1283                 0x19da0, 0x19de8,
1284                 0x19df0, 0x19e10,
1285                 0x19e50, 0x19e90,
1286                 0x19ea0, 0x19f24,
1287                 0x19f34, 0x19f34,
1288                 0x19f40, 0x19f50,
1289                 0x19f90, 0x19fb4,
1290                 0x19fc4, 0x19fe4,
1291                 0x1a000, 0x1a004,
1292                 0x1a010, 0x1a06c,
1293                 0x1a0b0, 0x1a0e4,
1294                 0x1a0ec, 0x1a0f8,
1295                 0x1a100, 0x1a108,
1296                 0x1a114, 0x1a120,
1297                 0x1a128, 0x1a130,
1298                 0x1a138, 0x1a138,
1299                 0x1a190, 0x1a1c4,
1300                 0x1a1fc, 0x1a1fc,
1301                 0x1e008, 0x1e00c,
1302                 0x1e040, 0x1e044,
1303                 0x1e04c, 0x1e04c,
1304                 0x1e284, 0x1e290,
1305                 0x1e2c0, 0x1e2c0,
1306                 0x1e2e0, 0x1e2e0,
1307                 0x1e300, 0x1e384,
1308                 0x1e3c0, 0x1e3c8,
1309                 0x1e408, 0x1e40c,
1310                 0x1e440, 0x1e444,
1311                 0x1e44c, 0x1e44c,
1312                 0x1e684, 0x1e690,
1313                 0x1e6c0, 0x1e6c0,
1314                 0x1e6e0, 0x1e6e0,
1315                 0x1e700, 0x1e784,
1316                 0x1e7c0, 0x1e7c8,
1317                 0x1e808, 0x1e80c,
1318                 0x1e840, 0x1e844,
1319                 0x1e84c, 0x1e84c,
1320                 0x1ea84, 0x1ea90,
1321                 0x1eac0, 0x1eac0,
1322                 0x1eae0, 0x1eae0,
1323                 0x1eb00, 0x1eb84,
1324                 0x1ebc0, 0x1ebc8,
1325                 0x1ec08, 0x1ec0c,
1326                 0x1ec40, 0x1ec44,
1327                 0x1ec4c, 0x1ec4c,
1328                 0x1ee84, 0x1ee90,
1329                 0x1eec0, 0x1eec0,
1330                 0x1eee0, 0x1eee0,
1331                 0x1ef00, 0x1ef84,
1332                 0x1efc0, 0x1efc8,
1333                 0x1f008, 0x1f00c,
1334                 0x1f040, 0x1f044,
1335                 0x1f04c, 0x1f04c,
1336                 0x1f284, 0x1f290,
1337                 0x1f2c0, 0x1f2c0,
1338                 0x1f2e0, 0x1f2e0,
1339                 0x1f300, 0x1f384,
1340                 0x1f3c0, 0x1f3c8,
1341                 0x1f408, 0x1f40c,
1342                 0x1f440, 0x1f444,
1343                 0x1f44c, 0x1f44c,
1344                 0x1f684, 0x1f690,
1345                 0x1f6c0, 0x1f6c0,
1346                 0x1f6e0, 0x1f6e0,
1347                 0x1f700, 0x1f784,
1348                 0x1f7c0, 0x1f7c8,
1349                 0x1f808, 0x1f80c,
1350                 0x1f840, 0x1f844,
1351                 0x1f84c, 0x1f84c,
1352                 0x1fa84, 0x1fa90,
1353                 0x1fac0, 0x1fac0,
1354                 0x1fae0, 0x1fae0,
1355                 0x1fb00, 0x1fb84,
1356                 0x1fbc0, 0x1fbc8,
1357                 0x1fc08, 0x1fc0c,
1358                 0x1fc40, 0x1fc44,
1359                 0x1fc4c, 0x1fc4c,
1360                 0x1fe84, 0x1fe90,
1361                 0x1fec0, 0x1fec0,
1362                 0x1fee0, 0x1fee0,
1363                 0x1ff00, 0x1ff84,
1364                 0x1ffc0, 0x1ffc8,
1365                 0x30000, 0x30030,
1366                 0x30038, 0x30038,
1367                 0x30040, 0x30040,
1368                 0x30100, 0x30144,
1369                 0x30190, 0x301a0,
1370                 0x301a8, 0x301b8,
1371                 0x301c4, 0x301c8,
1372                 0x301d0, 0x301d0,
1373                 0x30200, 0x30318,
1374                 0x30400, 0x304b4,
1375                 0x304c0, 0x3052c,
1376                 0x30540, 0x3061c,
1377                 0x30800, 0x30828,
1378                 0x30834, 0x30834,
1379                 0x308c0, 0x30908,
1380                 0x30910, 0x309ac,
1381                 0x30a00, 0x30a14,
1382                 0x30a1c, 0x30a2c,
1383                 0x30a44, 0x30a50,
1384                 0x30a74, 0x30a74,
1385                 0x30a7c, 0x30afc,
1386                 0x30b08, 0x30c24,
1387                 0x30d00, 0x30d00,
1388                 0x30d08, 0x30d14,
1389                 0x30d1c, 0x30d20,
1390                 0x30d3c, 0x30d3c,
1391                 0x30d48, 0x30d50,
1392                 0x31200, 0x3120c,
1393                 0x31220, 0x31220,
1394                 0x31240, 0x31240,
1395                 0x31600, 0x3160c,
1396                 0x31a00, 0x31a1c,
1397                 0x31e00, 0x31e20,
1398                 0x31e38, 0x31e3c,
1399                 0x31e80, 0x31e80,
1400                 0x31e88, 0x31ea8,
1401                 0x31eb0, 0x31eb4,
1402                 0x31ec8, 0x31ed4,
1403                 0x31fb8, 0x32004,
1404                 0x32200, 0x32200,
1405                 0x32208, 0x32240,
1406                 0x32248, 0x32280,
1407                 0x32288, 0x322c0,
1408                 0x322c8, 0x322fc,
1409                 0x32600, 0x32630,
1410                 0x32a00, 0x32abc,
1411                 0x32b00, 0x32b10,
1412                 0x32b20, 0x32b30,
1413                 0x32b40, 0x32b50,
1414                 0x32b60, 0x32b70,
1415                 0x33000, 0x33028,
1416                 0x33030, 0x33048,
1417                 0x33060, 0x33068,
1418                 0x33070, 0x3309c,
1419                 0x330f0, 0x33128,
1420                 0x33130, 0x33148,
1421                 0x33160, 0x33168,
1422                 0x33170, 0x3319c,
1423                 0x331f0, 0x33238,
1424                 0x33240, 0x33240,
1425                 0x33248, 0x33250,
1426                 0x3325c, 0x33264,
1427                 0x33270, 0x332b8,
1428                 0x332c0, 0x332e4,
1429                 0x332f8, 0x33338,
1430                 0x33340, 0x33340,
1431                 0x33348, 0x33350,
1432                 0x3335c, 0x33364,
1433                 0x33370, 0x333b8,
1434                 0x333c0, 0x333e4,
1435                 0x333f8, 0x33428,
1436                 0x33430, 0x33448,
1437                 0x33460, 0x33468,
1438                 0x33470, 0x3349c,
1439                 0x334f0, 0x33528,
1440                 0x33530, 0x33548,
1441                 0x33560, 0x33568,
1442                 0x33570, 0x3359c,
1443                 0x335f0, 0x33638,
1444                 0x33640, 0x33640,
1445                 0x33648, 0x33650,
1446                 0x3365c, 0x33664,
1447                 0x33670, 0x336b8,
1448                 0x336c0, 0x336e4,
1449                 0x336f8, 0x33738,
1450                 0x33740, 0x33740,
1451                 0x33748, 0x33750,
1452                 0x3375c, 0x33764,
1453                 0x33770, 0x337b8,
1454                 0x337c0, 0x337e4,
1455                 0x337f8, 0x337fc,
1456                 0x33814, 0x33814,
1457                 0x3382c, 0x3382c,
1458                 0x33880, 0x3388c,
1459                 0x338e8, 0x338ec,
1460                 0x33900, 0x33928,
1461                 0x33930, 0x33948,
1462                 0x33960, 0x33968,
1463                 0x33970, 0x3399c,
1464                 0x339f0, 0x33a38,
1465                 0x33a40, 0x33a40,
1466                 0x33a48, 0x33a50,
1467                 0x33a5c, 0x33a64,
1468                 0x33a70, 0x33ab8,
1469                 0x33ac0, 0x33ae4,
1470                 0x33af8, 0x33b10,
1471                 0x33b28, 0x33b28,
1472                 0x33b3c, 0x33b50,
1473                 0x33bf0, 0x33c10,
1474                 0x33c28, 0x33c28,
1475                 0x33c3c, 0x33c50,
1476                 0x33cf0, 0x33cfc,
1477                 0x34000, 0x34030,
1478                 0x34038, 0x34038,
1479                 0x34040, 0x34040,
1480                 0x34100, 0x34144,
1481                 0x34190, 0x341a0,
1482                 0x341a8, 0x341b8,
1483                 0x341c4, 0x341c8,
1484                 0x341d0, 0x341d0,
1485                 0x34200, 0x34318,
1486                 0x34400, 0x344b4,
1487                 0x344c0, 0x3452c,
1488                 0x34540, 0x3461c,
1489                 0x34800, 0x34828,
1490                 0x34834, 0x34834,
1491                 0x348c0, 0x34908,
1492                 0x34910, 0x349ac,
1493                 0x34a00, 0x34a14,
1494                 0x34a1c, 0x34a2c,
1495                 0x34a44, 0x34a50,
1496                 0x34a74, 0x34a74,
1497                 0x34a7c, 0x34afc,
1498                 0x34b08, 0x34c24,
1499                 0x34d00, 0x34d00,
1500                 0x34d08, 0x34d14,
1501                 0x34d1c, 0x34d20,
1502                 0x34d3c, 0x34d3c,
1503                 0x34d48, 0x34d50,
1504                 0x35200, 0x3520c,
1505                 0x35220, 0x35220,
1506                 0x35240, 0x35240,
1507                 0x35600, 0x3560c,
1508                 0x35a00, 0x35a1c,
1509                 0x35e00, 0x35e20,
1510                 0x35e38, 0x35e3c,
1511                 0x35e80, 0x35e80,
1512                 0x35e88, 0x35ea8,
1513                 0x35eb0, 0x35eb4,
1514                 0x35ec8, 0x35ed4,
1515                 0x35fb8, 0x36004,
1516                 0x36200, 0x36200,
1517                 0x36208, 0x36240,
1518                 0x36248, 0x36280,
1519                 0x36288, 0x362c0,
1520                 0x362c8, 0x362fc,
1521                 0x36600, 0x36630,
1522                 0x36a00, 0x36abc,
1523                 0x36b00, 0x36b10,
1524                 0x36b20, 0x36b30,
1525                 0x36b40, 0x36b50,
1526                 0x36b60, 0x36b70,
1527                 0x37000, 0x37028,
1528                 0x37030, 0x37048,
1529                 0x37060, 0x37068,
1530                 0x37070, 0x3709c,
1531                 0x370f0, 0x37128,
1532                 0x37130, 0x37148,
1533                 0x37160, 0x37168,
1534                 0x37170, 0x3719c,
1535                 0x371f0, 0x37238,
1536                 0x37240, 0x37240,
1537                 0x37248, 0x37250,
1538                 0x3725c, 0x37264,
1539                 0x37270, 0x372b8,
1540                 0x372c0, 0x372e4,
1541                 0x372f8, 0x37338,
1542                 0x37340, 0x37340,
1543                 0x37348, 0x37350,
1544                 0x3735c, 0x37364,
1545                 0x37370, 0x373b8,
1546                 0x373c0, 0x373e4,
1547                 0x373f8, 0x37428,
1548                 0x37430, 0x37448,
1549                 0x37460, 0x37468,
1550                 0x37470, 0x3749c,
1551                 0x374f0, 0x37528,
1552                 0x37530, 0x37548,
1553                 0x37560, 0x37568,
1554                 0x37570, 0x3759c,
1555                 0x375f0, 0x37638,
1556                 0x37640, 0x37640,
1557                 0x37648, 0x37650,
1558                 0x3765c, 0x37664,
1559                 0x37670, 0x376b8,
1560                 0x376c0, 0x376e4,
1561                 0x376f8, 0x37738,
1562                 0x37740, 0x37740,
1563                 0x37748, 0x37750,
1564                 0x3775c, 0x37764,
1565                 0x37770, 0x377b8,
1566                 0x377c0, 0x377e4,
1567                 0x377f8, 0x377fc,
1568                 0x37814, 0x37814,
1569                 0x3782c, 0x3782c,
1570                 0x37880, 0x3788c,
1571                 0x378e8, 0x378ec,
1572                 0x37900, 0x37928,
1573                 0x37930, 0x37948,
1574                 0x37960, 0x37968,
1575                 0x37970, 0x3799c,
1576                 0x379f0, 0x37a38,
1577                 0x37a40, 0x37a40,
1578                 0x37a48, 0x37a50,
1579                 0x37a5c, 0x37a64,
1580                 0x37a70, 0x37ab8,
1581                 0x37ac0, 0x37ae4,
1582                 0x37af8, 0x37b10,
1583                 0x37b28, 0x37b28,
1584                 0x37b3c, 0x37b50,
1585                 0x37bf0, 0x37c10,
1586                 0x37c28, 0x37c28,
1587                 0x37c3c, 0x37c50,
1588                 0x37cf0, 0x37cfc,
1589                 0x38000, 0x38030,
1590                 0x38038, 0x38038,
1591                 0x38040, 0x38040,
1592                 0x38100, 0x38144,
1593                 0x38190, 0x381a0,
1594                 0x381a8, 0x381b8,
1595                 0x381c4, 0x381c8,
1596                 0x381d0, 0x381d0,
1597                 0x38200, 0x38318,
1598                 0x38400, 0x384b4,
1599                 0x384c0, 0x3852c,
1600                 0x38540, 0x3861c,
1601                 0x38800, 0x38828,
1602                 0x38834, 0x38834,
1603                 0x388c0, 0x38908,
1604                 0x38910, 0x389ac,
1605                 0x38a00, 0x38a14,
1606                 0x38a1c, 0x38a2c,
1607                 0x38a44, 0x38a50,
1608                 0x38a74, 0x38a74,
1609                 0x38a7c, 0x38afc,
1610                 0x38b08, 0x38c24,
1611                 0x38d00, 0x38d00,
1612                 0x38d08, 0x38d14,
1613                 0x38d1c, 0x38d20,
1614                 0x38d3c, 0x38d3c,
1615                 0x38d48, 0x38d50,
1616                 0x39200, 0x3920c,
1617                 0x39220, 0x39220,
1618                 0x39240, 0x39240,
1619                 0x39600, 0x3960c,
1620                 0x39a00, 0x39a1c,
1621                 0x39e00, 0x39e20,
1622                 0x39e38, 0x39e3c,
1623                 0x39e80, 0x39e80,
1624                 0x39e88, 0x39ea8,
1625                 0x39eb0, 0x39eb4,
1626                 0x39ec8, 0x39ed4,
1627                 0x39fb8, 0x3a004,
1628                 0x3a200, 0x3a200,
1629                 0x3a208, 0x3a240,
1630                 0x3a248, 0x3a280,
1631                 0x3a288, 0x3a2c0,
1632                 0x3a2c8, 0x3a2fc,
1633                 0x3a600, 0x3a630,
1634                 0x3aa00, 0x3aabc,
1635                 0x3ab00, 0x3ab10,
1636                 0x3ab20, 0x3ab30,
1637                 0x3ab40, 0x3ab50,
1638                 0x3ab60, 0x3ab70,
1639                 0x3b000, 0x3b028,
1640                 0x3b030, 0x3b048,
1641                 0x3b060, 0x3b068,
1642                 0x3b070, 0x3b09c,
1643                 0x3b0f0, 0x3b128,
1644                 0x3b130, 0x3b148,
1645                 0x3b160, 0x3b168,
1646                 0x3b170, 0x3b19c,
1647                 0x3b1f0, 0x3b238,
1648                 0x3b240, 0x3b240,
1649                 0x3b248, 0x3b250,
1650                 0x3b25c, 0x3b264,
1651                 0x3b270, 0x3b2b8,
1652                 0x3b2c0, 0x3b2e4,
1653                 0x3b2f8, 0x3b338,
1654                 0x3b340, 0x3b340,
1655                 0x3b348, 0x3b350,
1656                 0x3b35c, 0x3b364,
1657                 0x3b370, 0x3b3b8,
1658                 0x3b3c0, 0x3b3e4,
1659                 0x3b3f8, 0x3b428,
1660                 0x3b430, 0x3b448,
1661                 0x3b460, 0x3b468,
1662                 0x3b470, 0x3b49c,
1663                 0x3b4f0, 0x3b528,
1664                 0x3b530, 0x3b548,
1665                 0x3b560, 0x3b568,
1666                 0x3b570, 0x3b59c,
1667                 0x3b5f0, 0x3b638,
1668                 0x3b640, 0x3b640,
1669                 0x3b648, 0x3b650,
1670                 0x3b65c, 0x3b664,
1671                 0x3b670, 0x3b6b8,
1672                 0x3b6c0, 0x3b6e4,
1673                 0x3b6f8, 0x3b738,
1674                 0x3b740, 0x3b740,
1675                 0x3b748, 0x3b750,
1676                 0x3b75c, 0x3b764,
1677                 0x3b770, 0x3b7b8,
1678                 0x3b7c0, 0x3b7e4,
1679                 0x3b7f8, 0x3b7fc,
1680                 0x3b814, 0x3b814,
1681                 0x3b82c, 0x3b82c,
1682                 0x3b880, 0x3b88c,
1683                 0x3b8e8, 0x3b8ec,
1684                 0x3b900, 0x3b928,
1685                 0x3b930, 0x3b948,
1686                 0x3b960, 0x3b968,
1687                 0x3b970, 0x3b99c,
1688                 0x3b9f0, 0x3ba38,
1689                 0x3ba40, 0x3ba40,
1690                 0x3ba48, 0x3ba50,
1691                 0x3ba5c, 0x3ba64,
1692                 0x3ba70, 0x3bab8,
1693                 0x3bac0, 0x3bae4,
1694                 0x3baf8, 0x3bb10,
1695                 0x3bb28, 0x3bb28,
1696                 0x3bb3c, 0x3bb50,
1697                 0x3bbf0, 0x3bc10,
1698                 0x3bc28, 0x3bc28,
1699                 0x3bc3c, 0x3bc50,
1700                 0x3bcf0, 0x3bcfc,
1701                 0x3c000, 0x3c030,
1702                 0x3c038, 0x3c038,
1703                 0x3c040, 0x3c040,
1704                 0x3c100, 0x3c144,
1705                 0x3c190, 0x3c1a0,
1706                 0x3c1a8, 0x3c1b8,
1707                 0x3c1c4, 0x3c1c8,
1708                 0x3c1d0, 0x3c1d0,
1709                 0x3c200, 0x3c318,
1710                 0x3c400, 0x3c4b4,
1711                 0x3c4c0, 0x3c52c,
1712                 0x3c540, 0x3c61c,
1713                 0x3c800, 0x3c828,
1714                 0x3c834, 0x3c834,
1715                 0x3c8c0, 0x3c908,
1716                 0x3c910, 0x3c9ac,
1717                 0x3ca00, 0x3ca14,
1718                 0x3ca1c, 0x3ca2c,
1719                 0x3ca44, 0x3ca50,
1720                 0x3ca74, 0x3ca74,
1721                 0x3ca7c, 0x3cafc,
1722                 0x3cb08, 0x3cc24,
1723                 0x3cd00, 0x3cd00,
1724                 0x3cd08, 0x3cd14,
1725                 0x3cd1c, 0x3cd20,
1726                 0x3cd3c, 0x3cd3c,
1727                 0x3cd48, 0x3cd50,
1728                 0x3d200, 0x3d20c,
1729                 0x3d220, 0x3d220,
1730                 0x3d240, 0x3d240,
1731                 0x3d600, 0x3d60c,
1732                 0x3da00, 0x3da1c,
1733                 0x3de00, 0x3de20,
1734                 0x3de38, 0x3de3c,
1735                 0x3de80, 0x3de80,
1736                 0x3de88, 0x3dea8,
1737                 0x3deb0, 0x3deb4,
1738                 0x3dec8, 0x3ded4,
1739                 0x3dfb8, 0x3e004,
1740                 0x3e200, 0x3e200,
1741                 0x3e208, 0x3e240,
1742                 0x3e248, 0x3e280,
1743                 0x3e288, 0x3e2c0,
1744                 0x3e2c8, 0x3e2fc,
1745                 0x3e600, 0x3e630,
1746                 0x3ea00, 0x3eabc,
1747                 0x3eb00, 0x3eb10,
1748                 0x3eb20, 0x3eb30,
1749                 0x3eb40, 0x3eb50,
1750                 0x3eb60, 0x3eb70,
1751                 0x3f000, 0x3f028,
1752                 0x3f030, 0x3f048,
1753                 0x3f060, 0x3f068,
1754                 0x3f070, 0x3f09c,
1755                 0x3f0f0, 0x3f128,
1756                 0x3f130, 0x3f148,
1757                 0x3f160, 0x3f168,
1758                 0x3f170, 0x3f19c,
1759                 0x3f1f0, 0x3f238,
1760                 0x3f240, 0x3f240,
1761                 0x3f248, 0x3f250,
1762                 0x3f25c, 0x3f264,
1763                 0x3f270, 0x3f2b8,
1764                 0x3f2c0, 0x3f2e4,
1765                 0x3f2f8, 0x3f338,
1766                 0x3f340, 0x3f340,
1767                 0x3f348, 0x3f350,
1768                 0x3f35c, 0x3f364,
1769                 0x3f370, 0x3f3b8,
1770                 0x3f3c0, 0x3f3e4,
1771                 0x3f3f8, 0x3f428,
1772                 0x3f430, 0x3f448,
1773                 0x3f460, 0x3f468,
1774                 0x3f470, 0x3f49c,
1775                 0x3f4f0, 0x3f528,
1776                 0x3f530, 0x3f548,
1777                 0x3f560, 0x3f568,
1778                 0x3f570, 0x3f59c,
1779                 0x3f5f0, 0x3f638,
1780                 0x3f640, 0x3f640,
1781                 0x3f648, 0x3f650,
1782                 0x3f65c, 0x3f664,
1783                 0x3f670, 0x3f6b8,
1784                 0x3f6c0, 0x3f6e4,
1785                 0x3f6f8, 0x3f738,
1786                 0x3f740, 0x3f740,
1787                 0x3f748, 0x3f750,
1788                 0x3f75c, 0x3f764,
1789                 0x3f770, 0x3f7b8,
1790                 0x3f7c0, 0x3f7e4,
1791                 0x3f7f8, 0x3f7fc,
1792                 0x3f814, 0x3f814,
1793                 0x3f82c, 0x3f82c,
1794                 0x3f880, 0x3f88c,
1795                 0x3f8e8, 0x3f8ec,
1796                 0x3f900, 0x3f928,
1797                 0x3f930, 0x3f948,
1798                 0x3f960, 0x3f968,
1799                 0x3f970, 0x3f99c,
1800                 0x3f9f0, 0x3fa38,
1801                 0x3fa40, 0x3fa40,
1802                 0x3fa48, 0x3fa50,
1803                 0x3fa5c, 0x3fa64,
1804                 0x3fa70, 0x3fab8,
1805                 0x3fac0, 0x3fae4,
1806                 0x3faf8, 0x3fb10,
1807                 0x3fb28, 0x3fb28,
1808                 0x3fb3c, 0x3fb50,
1809                 0x3fbf0, 0x3fc10,
1810                 0x3fc28, 0x3fc28,
1811                 0x3fc3c, 0x3fc50,
1812                 0x3fcf0, 0x3fcfc,
1813                 0x40000, 0x4000c,
1814                 0x40040, 0x40050,
1815                 0x40060, 0x40068,
1816                 0x4007c, 0x4008c,
1817                 0x40094, 0x400b0,
1818                 0x400c0, 0x40144,
1819                 0x40180, 0x4018c,
1820                 0x40200, 0x40254,
1821                 0x40260, 0x40264,
1822                 0x40270, 0x40288,
1823                 0x40290, 0x40298,
1824                 0x402ac, 0x402c8,
1825                 0x402d0, 0x402e0,
1826                 0x402f0, 0x402f0,
1827                 0x40300, 0x4033c,
1828                 0x403f8, 0x403fc,
1829                 0x41304, 0x413c4,
1830                 0x41400, 0x4140c,
1831                 0x41414, 0x4141c,
1832                 0x41480, 0x414d0,
1833                 0x44000, 0x44054,
1834                 0x4405c, 0x44078,
1835                 0x440c0, 0x44174,
1836                 0x44180, 0x441ac,
1837                 0x441b4, 0x441b8,
1838                 0x441c0, 0x44254,
1839                 0x4425c, 0x44278,
1840                 0x442c0, 0x44374,
1841                 0x44380, 0x443ac,
1842                 0x443b4, 0x443b8,
1843                 0x443c0, 0x44454,
1844                 0x4445c, 0x44478,
1845                 0x444c0, 0x44574,
1846                 0x44580, 0x445ac,
1847                 0x445b4, 0x445b8,
1848                 0x445c0, 0x44654,
1849                 0x4465c, 0x44678,
1850                 0x446c0, 0x44774,
1851                 0x44780, 0x447ac,
1852                 0x447b4, 0x447b8,
1853                 0x447c0, 0x44854,
1854                 0x4485c, 0x44878,
1855                 0x448c0, 0x44974,
1856                 0x44980, 0x449ac,
1857                 0x449b4, 0x449b8,
1858                 0x449c0, 0x449fc,
1859                 0x45000, 0x45004,
1860                 0x45010, 0x45030,
1861                 0x45040, 0x45060,
1862                 0x45068, 0x45068,
1863                 0x45080, 0x45084,
1864                 0x450a0, 0x450b0,
1865                 0x45200, 0x45204,
1866                 0x45210, 0x45230,
1867                 0x45240, 0x45260,
1868                 0x45268, 0x45268,
1869                 0x45280, 0x45284,
1870                 0x452a0, 0x452b0,
1871                 0x460c0, 0x460e4,
1872                 0x47000, 0x4703c,
1873                 0x47044, 0x4708c,
1874                 0x47200, 0x47250,
1875                 0x47400, 0x47408,
1876                 0x47414, 0x47420,
1877                 0x47600, 0x47618,
1878                 0x47800, 0x47814,
1879                 0x48000, 0x4800c,
1880                 0x48040, 0x48050,
1881                 0x48060, 0x48068,
1882                 0x4807c, 0x4808c,
1883                 0x48094, 0x480b0,
1884                 0x480c0, 0x48144,
1885                 0x48180, 0x4818c,
1886                 0x48200, 0x48254,
1887                 0x48260, 0x48264,
1888                 0x48270, 0x48288,
1889                 0x48290, 0x48298,
1890                 0x482ac, 0x482c8,
1891                 0x482d0, 0x482e0,
1892                 0x482f0, 0x482f0,
1893                 0x48300, 0x4833c,
1894                 0x483f8, 0x483fc,
1895                 0x49304, 0x493c4,
1896                 0x49400, 0x4940c,
1897                 0x49414, 0x4941c,
1898                 0x49480, 0x494d0,
1899                 0x4c000, 0x4c054,
1900                 0x4c05c, 0x4c078,
1901                 0x4c0c0, 0x4c174,
1902                 0x4c180, 0x4c1ac,
1903                 0x4c1b4, 0x4c1b8,
1904                 0x4c1c0, 0x4c254,
1905                 0x4c25c, 0x4c278,
1906                 0x4c2c0, 0x4c374,
1907                 0x4c380, 0x4c3ac,
1908                 0x4c3b4, 0x4c3b8,
1909                 0x4c3c0, 0x4c454,
1910                 0x4c45c, 0x4c478,
1911                 0x4c4c0, 0x4c574,
1912                 0x4c580, 0x4c5ac,
1913                 0x4c5b4, 0x4c5b8,
1914                 0x4c5c0, 0x4c654,
1915                 0x4c65c, 0x4c678,
1916                 0x4c6c0, 0x4c774,
1917                 0x4c780, 0x4c7ac,
1918                 0x4c7b4, 0x4c7b8,
1919                 0x4c7c0, 0x4c854,
1920                 0x4c85c, 0x4c878,
1921                 0x4c8c0, 0x4c974,
1922                 0x4c980, 0x4c9ac,
1923                 0x4c9b4, 0x4c9b8,
1924                 0x4c9c0, 0x4c9fc,
1925                 0x4d000, 0x4d004,
1926                 0x4d010, 0x4d030,
1927                 0x4d040, 0x4d060,
1928                 0x4d068, 0x4d068,
1929                 0x4d080, 0x4d084,
1930                 0x4d0a0, 0x4d0b0,
1931                 0x4d200, 0x4d204,
1932                 0x4d210, 0x4d230,
1933                 0x4d240, 0x4d260,
1934                 0x4d268, 0x4d268,
1935                 0x4d280, 0x4d284,
1936                 0x4d2a0, 0x4d2b0,
1937                 0x4e0c0, 0x4e0e4,
1938                 0x4f000, 0x4f03c,
1939                 0x4f044, 0x4f08c,
1940                 0x4f200, 0x4f250,
1941                 0x4f400, 0x4f408,
1942                 0x4f414, 0x4f420,
1943                 0x4f600, 0x4f618,
1944                 0x4f800, 0x4f814,
1945                 0x50000, 0x50084,
1946                 0x50090, 0x500cc,
1947                 0x50400, 0x50400,
1948                 0x50800, 0x50884,
1949                 0x50890, 0x508cc,
1950                 0x50c00, 0x50c00,
1951                 0x51000, 0x5101c,
1952                 0x51300, 0x51308,
1953         };
1954
1955         static const unsigned int t6_reg_ranges[] = {
1956                 0x1008, 0x101c,
1957                 0x1024, 0x10a8,
1958                 0x10b4, 0x10f8,
1959                 0x1100, 0x1114,
1960                 0x111c, 0x112c,
1961                 0x1138, 0x113c,
1962                 0x1144, 0x114c,
1963                 0x1180, 0x1184,
1964                 0x1190, 0x1194,
1965                 0x11a0, 0x11a4,
1966                 0x11b0, 0x11b4,
1967                 0x11fc, 0x1274,
1968                 0x1280, 0x133c,
1969                 0x1800, 0x18fc,
1970                 0x3000, 0x302c,
1971                 0x3060, 0x30b0,
1972                 0x30b8, 0x30d8,
1973                 0x30e0, 0x30fc,
1974                 0x3140, 0x357c,
1975                 0x35a8, 0x35cc,
1976                 0x35ec, 0x35ec,
1977                 0x3600, 0x5624,
1978                 0x56cc, 0x56ec,
1979                 0x56f4, 0x5720,
1980                 0x5728, 0x575c,
1981                 0x580c, 0x5814,
1982                 0x5890, 0x589c,
1983                 0x58a4, 0x58ac,
1984                 0x58b8, 0x58bc,
1985                 0x5940, 0x595c,
1986                 0x5980, 0x598c,
1987                 0x59b0, 0x59c8,
1988                 0x59d0, 0x59dc,
1989                 0x59fc, 0x5a18,
1990                 0x5a60, 0x5a6c,
1991                 0x5a80, 0x5a8c,
1992                 0x5a94, 0x5a9c,
1993                 0x5b94, 0x5bfc,
1994                 0x5c10, 0x5e48,
1995                 0x5e50, 0x5e94,
1996                 0x5ea0, 0x5eb0,
1997                 0x5ec0, 0x5ec0,
1998                 0x5ec8, 0x5ed0,
1999                 0x5ee0, 0x5ee0,
2000                 0x5ef0, 0x5ef0,
2001                 0x5f00, 0x5f00,
2002                 0x6000, 0x6020,
2003                 0x6028, 0x6040,
2004                 0x6058, 0x609c,
2005                 0x60a8, 0x619c,
2006                 0x7700, 0x7798,
2007                 0x77c0, 0x7880,
2008                 0x78cc, 0x78fc,
2009                 0x7b00, 0x7b58,
2010                 0x7b60, 0x7b84,
2011                 0x7b8c, 0x7c54,
2012                 0x7d00, 0x7d38,
2013                 0x7d40, 0x7d84,
2014                 0x7d8c, 0x7ddc,
2015                 0x7de4, 0x7e04,
2016                 0x7e10, 0x7e1c,
2017                 0x7e24, 0x7e38,
2018                 0x7e40, 0x7e44,
2019                 0x7e4c, 0x7e78,
2020                 0x7e80, 0x7edc,
2021                 0x7ee8, 0x7efc,
2022                 0x8dc0, 0x8de4,
2023                 0x8df8, 0x8e04,
2024                 0x8e10, 0x8e84,
2025                 0x8ea0, 0x8f88,
2026                 0x8fb8, 0x9058,
2027                 0x9060, 0x9060,
2028                 0x9068, 0x90f8,
2029                 0x9100, 0x9124,
2030                 0x9400, 0x9470,
2031                 0x9600, 0x9600,
2032                 0x9608, 0x9638,
2033                 0x9640, 0x9704,
2034                 0x9710, 0x971c,
2035                 0x9800, 0x9808,
2036                 0x9820, 0x983c,
2037                 0x9850, 0x9864,
2038                 0x9c00, 0x9c6c,
2039                 0x9c80, 0x9cec,
2040                 0x9d00, 0x9d6c,
2041                 0x9d80, 0x9dec,
2042                 0x9e00, 0x9e6c,
2043                 0x9e80, 0x9eec,
2044                 0x9f00, 0x9f6c,
2045                 0x9f80, 0xa020,
2046                 0xd004, 0xd03c,
2047                 0xd100, 0xd118,
2048                 0xd200, 0xd214,
2049                 0xd220, 0xd234,
2050                 0xd240, 0xd254,
2051                 0xd260, 0xd274,
2052                 0xd280, 0xd294,
2053                 0xd2a0, 0xd2b4,
2054                 0xd2c0, 0xd2d4,
2055                 0xd2e0, 0xd2f4,
2056                 0xd300, 0xd31c,
2057                 0xdfc0, 0xdfe0,
2058                 0xe000, 0xf008,
2059                 0xf010, 0xf018,
2060                 0xf020, 0xf028,
2061                 0x11000, 0x11014,
2062                 0x11048, 0x1106c,
2063                 0x11074, 0x11088,
2064                 0x11098, 0x11120,
2065                 0x1112c, 0x1117c,
2066                 0x11190, 0x112e0,
2067                 0x11300, 0x1130c,
2068                 0x12000, 0x1206c,
2069                 0x19040, 0x1906c,
2070                 0x19078, 0x19080,
2071                 0x1908c, 0x190e8,
2072                 0x190f0, 0x190f8,
2073                 0x19100, 0x19110,
2074                 0x19120, 0x19124,
2075                 0x19150, 0x19194,
2076                 0x1919c, 0x191b0,
2077                 0x191d0, 0x191e8,
2078                 0x19238, 0x19290,
2079                 0x192a4, 0x192b0,
2080                 0x192bc, 0x192bc,
2081                 0x19348, 0x1934c,
2082                 0x193f8, 0x19418,
2083                 0x19420, 0x19428,
2084                 0x19430, 0x19444,
2085                 0x1944c, 0x1946c,
2086                 0x19474, 0x19474,
2087                 0x19490, 0x194cc,
2088                 0x194f0, 0x194f8,
2089                 0x19c00, 0x19c48,
2090                 0x19c50, 0x19c80,
2091                 0x19c94, 0x19c98,
2092                 0x19ca0, 0x19cbc,
2093                 0x19ce4, 0x19ce4,
2094                 0x19cf0, 0x19cf8,
2095                 0x19d00, 0x19d28,
2096                 0x19d50, 0x19d78,
2097                 0x19d94, 0x19d98,
2098                 0x19da0, 0x19dc8,
2099                 0x19df0, 0x19e10,
2100                 0x19e50, 0x19e6c,
2101                 0x19ea0, 0x19ebc,
2102                 0x19ec4, 0x19ef4,
2103                 0x19f04, 0x19f2c,
2104                 0x19f34, 0x19f34,
2105                 0x19f40, 0x19f50,
2106                 0x19f90, 0x19fac,
2107                 0x19fc4, 0x19fc8,
2108                 0x19fd0, 0x19fe4,
2109                 0x1a000, 0x1a004,
2110                 0x1a010, 0x1a06c,
2111                 0x1a0b0, 0x1a0e4,
2112                 0x1a0ec, 0x1a0f8,
2113                 0x1a100, 0x1a108,
2114                 0x1a114, 0x1a120,
2115                 0x1a128, 0x1a130,
2116                 0x1a138, 0x1a138,
2117                 0x1a190, 0x1a1c4,
2118                 0x1a1fc, 0x1a1fc,
2119                 0x1e008, 0x1e00c,
2120                 0x1e040, 0x1e044,
2121                 0x1e04c, 0x1e04c,
2122                 0x1e284, 0x1e290,
2123                 0x1e2c0, 0x1e2c0,
2124                 0x1e2e0, 0x1e2e0,
2125                 0x1e300, 0x1e384,
2126                 0x1e3c0, 0x1e3c8,
2127                 0x1e408, 0x1e40c,
2128                 0x1e440, 0x1e444,
2129                 0x1e44c, 0x1e44c,
2130                 0x1e684, 0x1e690,
2131                 0x1e6c0, 0x1e6c0,
2132                 0x1e6e0, 0x1e6e0,
2133                 0x1e700, 0x1e784,
2134                 0x1e7c0, 0x1e7c8,
2135                 0x1e808, 0x1e80c,
2136                 0x1e840, 0x1e844,
2137                 0x1e84c, 0x1e84c,
2138                 0x1ea84, 0x1ea90,
2139                 0x1eac0, 0x1eac0,
2140                 0x1eae0, 0x1eae0,
2141                 0x1eb00, 0x1eb84,
2142                 0x1ebc0, 0x1ebc8,
2143                 0x1ec08, 0x1ec0c,
2144                 0x1ec40, 0x1ec44,
2145                 0x1ec4c, 0x1ec4c,
2146                 0x1ee84, 0x1ee90,
2147                 0x1eec0, 0x1eec0,
2148                 0x1eee0, 0x1eee0,
2149                 0x1ef00, 0x1ef84,
2150                 0x1efc0, 0x1efc8,
2151                 0x1f008, 0x1f00c,
2152                 0x1f040, 0x1f044,
2153                 0x1f04c, 0x1f04c,
2154                 0x1f284, 0x1f290,
2155                 0x1f2c0, 0x1f2c0,
2156                 0x1f2e0, 0x1f2e0,
2157                 0x1f300, 0x1f384,
2158                 0x1f3c0, 0x1f3c8,
2159                 0x1f408, 0x1f40c,
2160                 0x1f440, 0x1f444,
2161                 0x1f44c, 0x1f44c,
2162                 0x1f684, 0x1f690,
2163                 0x1f6c0, 0x1f6c0,
2164                 0x1f6e0, 0x1f6e0,
2165                 0x1f700, 0x1f784,
2166                 0x1f7c0, 0x1f7c8,
2167                 0x1f808, 0x1f80c,
2168                 0x1f840, 0x1f844,
2169                 0x1f84c, 0x1f84c,
2170                 0x1fa84, 0x1fa90,
2171                 0x1fac0, 0x1fac0,
2172                 0x1fae0, 0x1fae0,
2173                 0x1fb00, 0x1fb84,
2174                 0x1fbc0, 0x1fbc8,
2175                 0x1fc08, 0x1fc0c,
2176                 0x1fc40, 0x1fc44,
2177                 0x1fc4c, 0x1fc4c,
2178                 0x1fe84, 0x1fe90,
2179                 0x1fec0, 0x1fec0,
2180                 0x1fee0, 0x1fee0,
2181                 0x1ff00, 0x1ff84,
2182                 0x1ffc0, 0x1ffc8,
2183                 0x30000, 0x30030,
2184                 0x30038, 0x30038,
2185                 0x30040, 0x30040,
2186                 0x30048, 0x30048,
2187                 0x30050, 0x30050,
2188                 0x3005c, 0x30060,
2189                 0x30068, 0x30068,
2190                 0x30070, 0x30070,
2191                 0x30100, 0x30168,
2192                 0x30190, 0x301a0,
2193                 0x301a8, 0x301b8,
2194                 0x301c4, 0x301c8,
2195                 0x301d0, 0x301d0,
2196                 0x30200, 0x30320,
2197                 0x30400, 0x304b4,
2198                 0x304c0, 0x3052c,
2199                 0x30540, 0x3061c,
2200                 0x30800, 0x308a0,
2201                 0x308c0, 0x30908,
2202                 0x30910, 0x309b8,
2203                 0x30a00, 0x30a04,
2204                 0x30a0c, 0x30a14,
2205                 0x30a1c, 0x30a2c,
2206                 0x30a44, 0x30a50,
2207                 0x30a74, 0x30a74,
2208                 0x30a7c, 0x30afc,
2209                 0x30b08, 0x30c24,
2210                 0x30d00, 0x30d14,
2211                 0x30d1c, 0x30d3c,
2212                 0x30d44, 0x30d4c,
2213                 0x30d54, 0x30d74,
2214                 0x30d7c, 0x30d7c,
2215                 0x30de0, 0x30de0,
2216                 0x30e00, 0x30ed4,
2217                 0x30f00, 0x30fa4,
2218                 0x30fc0, 0x30fc4,
2219                 0x31000, 0x31004,
2220                 0x31080, 0x310fc,
2221                 0x31208, 0x31220,
2222                 0x3123c, 0x31254,
2223                 0x31300, 0x31300,
2224                 0x31308, 0x3131c,
2225                 0x31338, 0x3133c,
2226                 0x31380, 0x31380,
2227                 0x31388, 0x313a8,
2228                 0x313b4, 0x313b4,
2229                 0x31400, 0x31420,
2230                 0x31438, 0x3143c,
2231                 0x31480, 0x31480,
2232                 0x314a8, 0x314a8,
2233                 0x314b0, 0x314b4,
2234                 0x314c8, 0x314d4,
2235                 0x31a40, 0x31a4c,
2236                 0x31af0, 0x31b20,
2237                 0x31b38, 0x31b3c,
2238                 0x31b80, 0x31b80,
2239                 0x31ba8, 0x31ba8,
2240                 0x31bb0, 0x31bb4,
2241                 0x31bc8, 0x31bd4,
2242                 0x32140, 0x3218c,
2243                 0x321f0, 0x321f4,
2244                 0x32200, 0x32200,
2245                 0x32218, 0x32218,
2246                 0x32400, 0x32400,
2247                 0x32408, 0x3241c,
2248                 0x32618, 0x32620,
2249                 0x32664, 0x32664,
2250                 0x326a8, 0x326a8,
2251                 0x326ec, 0x326ec,
2252                 0x32a00, 0x32abc,
2253                 0x32b00, 0x32b38,
2254                 0x32b40, 0x32b58,
2255                 0x32b60, 0x32b78,
2256                 0x32c00, 0x32c00,
2257                 0x32c08, 0x32c3c,
2258                 0x32e00, 0x32e2c,
2259                 0x32f00, 0x32f2c,
2260                 0x33000, 0x3302c,
2261                 0x33034, 0x33050,
2262                 0x33058, 0x33058,
2263                 0x33060, 0x3308c,
2264                 0x3309c, 0x330ac,
2265                 0x330c0, 0x330c0,
2266                 0x330c8, 0x330d0,
2267                 0x330d8, 0x330e0,
2268                 0x330ec, 0x3312c,
2269                 0x33134, 0x33150,
2270                 0x33158, 0x33158,
2271                 0x33160, 0x3318c,
2272                 0x3319c, 0x331ac,
2273                 0x331c0, 0x331c0,
2274                 0x331c8, 0x331d0,
2275                 0x331d8, 0x331e0,
2276                 0x331ec, 0x33290,
2277                 0x33298, 0x332c4,
2278                 0x332e4, 0x33390,
2279                 0x33398, 0x333c4,
2280                 0x333e4, 0x3342c,
2281                 0x33434, 0x33450,
2282                 0x33458, 0x33458,
2283                 0x33460, 0x3348c,
2284                 0x3349c, 0x334ac,
2285                 0x334c0, 0x334c0,
2286                 0x334c8, 0x334d0,
2287                 0x334d8, 0x334e0,
2288                 0x334ec, 0x3352c,
2289                 0x33534, 0x33550,
2290                 0x33558, 0x33558,
2291                 0x33560, 0x3358c,
2292                 0x3359c, 0x335ac,
2293                 0x335c0, 0x335c0,
2294                 0x335c8, 0x335d0,
2295                 0x335d8, 0x335e0,
2296                 0x335ec, 0x33690,
2297                 0x33698, 0x336c4,
2298                 0x336e4, 0x33790,
2299                 0x33798, 0x337c4,
2300                 0x337e4, 0x337fc,
2301                 0x33814, 0x33814,
2302                 0x33854, 0x33868,
2303                 0x33880, 0x3388c,
2304                 0x338c0, 0x338d0,
2305                 0x338e8, 0x338ec,
2306                 0x33900, 0x3392c,
2307                 0x33934, 0x33950,
2308                 0x33958, 0x33958,
2309                 0x33960, 0x3398c,
2310                 0x3399c, 0x339ac,
2311                 0x339c0, 0x339c0,
2312                 0x339c8, 0x339d0,
2313                 0x339d8, 0x339e0,
2314                 0x339ec, 0x33a90,
2315                 0x33a98, 0x33ac4,
2316                 0x33ae4, 0x33b10,
2317                 0x33b24, 0x33b28,
2318                 0x33b38, 0x33b50,
2319                 0x33bf0, 0x33c10,
2320                 0x33c24, 0x33c28,
2321                 0x33c38, 0x33c50,
2322                 0x33cf0, 0x33cfc,
2323                 0x34000, 0x34030,
2324                 0x34038, 0x34038,
2325                 0x34040, 0x34040,
2326                 0x34048, 0x34048,
2327                 0x34050, 0x34050,
2328                 0x3405c, 0x34060,
2329                 0x34068, 0x34068,
2330                 0x34070, 0x34070,
2331                 0x34100, 0x34168,
2332                 0x34190, 0x341a0,
2333                 0x341a8, 0x341b8,
2334                 0x341c4, 0x341c8,
2335                 0x341d0, 0x341d0,
2336                 0x34200, 0x34320,
2337                 0x34400, 0x344b4,
2338                 0x344c0, 0x3452c,
2339                 0x34540, 0x3461c,
2340                 0x34800, 0x348a0,
2341                 0x348c0, 0x34908,
2342                 0x34910, 0x349b8,
2343                 0x34a00, 0x34a04,
2344                 0x34a0c, 0x34a14,
2345                 0x34a1c, 0x34a2c,
2346                 0x34a44, 0x34a50,
2347                 0x34a74, 0x34a74,
2348                 0x34a7c, 0x34afc,
2349                 0x34b08, 0x34c24,
2350                 0x34d00, 0x34d14,
2351                 0x34d1c, 0x34d3c,
2352                 0x34d44, 0x34d4c,
2353                 0x34d54, 0x34d74,
2354                 0x34d7c, 0x34d7c,
2355                 0x34de0, 0x34de0,
2356                 0x34e00, 0x34ed4,
2357                 0x34f00, 0x34fa4,
2358                 0x34fc0, 0x34fc4,
2359                 0x35000, 0x35004,
2360                 0x35080, 0x350fc,
2361                 0x35208, 0x35220,
2362                 0x3523c, 0x35254,
2363                 0x35300, 0x35300,
2364                 0x35308, 0x3531c,
2365                 0x35338, 0x3533c,
2366                 0x35380, 0x35380,
2367                 0x35388, 0x353a8,
2368                 0x353b4, 0x353b4,
2369                 0x35400, 0x35420,
2370                 0x35438, 0x3543c,
2371                 0x35480, 0x35480,
2372                 0x354a8, 0x354a8,
2373                 0x354b0, 0x354b4,
2374                 0x354c8, 0x354d4,
2375                 0x35a40, 0x35a4c,
2376                 0x35af0, 0x35b20,
2377                 0x35b38, 0x35b3c,
2378                 0x35b80, 0x35b80,
2379                 0x35ba8, 0x35ba8,
2380                 0x35bb0, 0x35bb4,
2381                 0x35bc8, 0x35bd4,
2382                 0x36140, 0x3618c,
2383                 0x361f0, 0x361f4,
2384                 0x36200, 0x36200,
2385                 0x36218, 0x36218,
2386                 0x36400, 0x36400,
2387                 0x36408, 0x3641c,
2388                 0x36618, 0x36620,
2389                 0x36664, 0x36664,
2390                 0x366a8, 0x366a8,
2391                 0x366ec, 0x366ec,
2392                 0x36a00, 0x36abc,
2393                 0x36b00, 0x36b38,
2394                 0x36b40, 0x36b58,
2395                 0x36b60, 0x36b78,
2396                 0x36c00, 0x36c00,
2397                 0x36c08, 0x36c3c,
2398                 0x36e00, 0x36e2c,
2399                 0x36f00, 0x36f2c,
2400                 0x37000, 0x3702c,
2401                 0x37034, 0x37050,
2402                 0x37058, 0x37058,
2403                 0x37060, 0x3708c,
2404                 0x3709c, 0x370ac,
2405                 0x370c0, 0x370c0,
2406                 0x370c8, 0x370d0,
2407                 0x370d8, 0x370e0,
2408                 0x370ec, 0x3712c,
2409                 0x37134, 0x37150,
2410                 0x37158, 0x37158,
2411                 0x37160, 0x3718c,
2412                 0x3719c, 0x371ac,
2413                 0x371c0, 0x371c0,
2414                 0x371c8, 0x371d0,
2415                 0x371d8, 0x371e0,
2416                 0x371ec, 0x37290,
2417                 0x37298, 0x372c4,
2418                 0x372e4, 0x37390,
2419                 0x37398, 0x373c4,
2420                 0x373e4, 0x3742c,
2421                 0x37434, 0x37450,
2422                 0x37458, 0x37458,
2423                 0x37460, 0x3748c,
2424                 0x3749c, 0x374ac,
2425                 0x374c0, 0x374c0,
2426                 0x374c8, 0x374d0,
2427                 0x374d8, 0x374e0,
2428                 0x374ec, 0x3752c,
2429                 0x37534, 0x37550,
2430                 0x37558, 0x37558,
2431                 0x37560, 0x3758c,
2432                 0x3759c, 0x375ac,
2433                 0x375c0, 0x375c0,
2434                 0x375c8, 0x375d0,
2435                 0x375d8, 0x375e0,
2436                 0x375ec, 0x37690,
2437                 0x37698, 0x376c4,
2438                 0x376e4, 0x37790,
2439                 0x37798, 0x377c4,
2440                 0x377e4, 0x377fc,
2441                 0x37814, 0x37814,
2442                 0x37854, 0x37868,
2443                 0x37880, 0x3788c,
2444                 0x378c0, 0x378d0,
2445                 0x378e8, 0x378ec,
2446                 0x37900, 0x3792c,
2447                 0x37934, 0x37950,
2448                 0x37958, 0x37958,
2449                 0x37960, 0x3798c,
2450                 0x3799c, 0x379ac,
2451                 0x379c0, 0x379c0,
2452                 0x379c8, 0x379d0,
2453                 0x379d8, 0x379e0,
2454                 0x379ec, 0x37a90,
2455                 0x37a98, 0x37ac4,
2456                 0x37ae4, 0x37b10,
2457                 0x37b24, 0x37b28,
2458                 0x37b38, 0x37b50,
2459                 0x37bf0, 0x37c10,
2460                 0x37c24, 0x37c28,
2461                 0x37c38, 0x37c50,
2462                 0x37cf0, 0x37cfc,
2463                 0x40040, 0x40040,
2464                 0x40080, 0x40084,
2465                 0x40100, 0x40100,
2466                 0x40140, 0x401bc,
2467                 0x40200, 0x40214,
2468                 0x40228, 0x40228,
2469                 0x40240, 0x40258,
2470                 0x40280, 0x40280,
2471                 0x40304, 0x40304,
2472                 0x40330, 0x4033c,
2473                 0x41304, 0x413c8,
2474                 0x413d0, 0x413dc,
2475                 0x413f0, 0x413f0,
2476                 0x41400, 0x4140c,
2477                 0x41414, 0x4141c,
2478                 0x41480, 0x414d0,
2479                 0x44000, 0x4407c,
2480                 0x440c0, 0x441ac,
2481                 0x441b4, 0x4427c,
2482                 0x442c0, 0x443ac,
2483                 0x443b4, 0x4447c,
2484                 0x444c0, 0x445ac,
2485                 0x445b4, 0x4467c,
2486                 0x446c0, 0x447ac,
2487                 0x447b4, 0x4487c,
2488                 0x448c0, 0x449ac,
2489                 0x449b4, 0x44a7c,
2490                 0x44ac0, 0x44bac,
2491                 0x44bb4, 0x44c7c,
2492                 0x44cc0, 0x44dac,
2493                 0x44db4, 0x44e7c,
2494                 0x44ec0, 0x44fac,
2495                 0x44fb4, 0x4507c,
2496                 0x450c0, 0x451ac,
2497                 0x451b4, 0x451fc,
2498                 0x45800, 0x45804,
2499                 0x45810, 0x45830,
2500                 0x45840, 0x45860,
2501                 0x45868, 0x45868,
2502                 0x45880, 0x45884,
2503                 0x458a0, 0x458b0,
2504                 0x45a00, 0x45a04,
2505                 0x45a10, 0x45a30,
2506                 0x45a40, 0x45a60,
2507                 0x45a68, 0x45a68,
2508                 0x45a80, 0x45a84,
2509                 0x45aa0, 0x45ab0,
2510                 0x460c0, 0x460e4,
2511                 0x47000, 0x4703c,
2512                 0x47044, 0x4708c,
2513                 0x47200, 0x47250,
2514                 0x47400, 0x47408,
2515                 0x47414, 0x47420,
2516                 0x47600, 0x47618,
2517                 0x47800, 0x47814,
2518                 0x47820, 0x4782c,
2519                 0x50000, 0x50084,
2520                 0x50090, 0x500cc,
2521                 0x50300, 0x50384,
2522                 0x50400, 0x50400,
2523                 0x50800, 0x50884,
2524                 0x50890, 0x508cc,
2525                 0x50b00, 0x50b84,
2526                 0x50c00, 0x50c00,
2527                 0x51000, 0x51020,
2528                 0x51028, 0x510b0,
2529                 0x51300, 0x51324,
2530         };
2531
2532         u32 *buf_end = (u32 *)(buf + buf_size);
2533         const unsigned int *reg_ranges;
2534         int reg_ranges_size, range;
2535         unsigned int chip_version = chip_id(adap);
2536
2537         /*
2538          * Select the right set of register ranges to dump depending on the
2539          * adapter chip type.
2540          */
2541         switch (chip_version) {
2542         case CHELSIO_T4:
2543                 reg_ranges = t4_reg_ranges;
2544                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2545                 break;
2546
2547         case CHELSIO_T5:
2548                 reg_ranges = t5_reg_ranges;
2549                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2550                 break;
2551
2552         case CHELSIO_T6:
2553                 reg_ranges = t6_reg_ranges;
2554                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2555                 break;
2556
2557         default:
2558                 CH_ERR(adap,
2559                         "Unsupported chip version %d\n", chip_version);
2560                 return;
2561         }
2562
2563         /*
2564          * Clear the register buffer and insert the appropriate register
2565          * values selected by the above register ranges.
2566          */
2567         memset(buf, 0, buf_size);
2568         for (range = 0; range < reg_ranges_size; range += 2) {
2569                 unsigned int reg = reg_ranges[range];
2570                 unsigned int last_reg = reg_ranges[range + 1];
2571                 u32 *bufp = (u32 *)(buf + reg);
2572
2573                 /*
2574                  * Iterate across the register range filling in the register
2575                  * buffer but don't write past the end of the register buffer.
2576                  */
2577                 while (reg <= last_reg && bufp < buf_end) {
2578                         *bufp++ = t4_read_reg(adap, reg);
2579                         reg += sizeof(u32);
2580                 }
2581         }
2582 }
2583
2584 /*
2585  * Partial EEPROM Vital Product Data structure.  Includes only the ID and
2586  * VPD-R sections.
2587  */
2588 struct t4_vpd_hdr {
2589         u8  id_tag;
2590         u8  id_len[2];
2591         u8  id_data[ID_LEN];
2592         u8  vpdr_tag;
2593         u8  vpdr_len[2];
2594 };
2595
2596 /*
2597  * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2598  */
2599 #define EEPROM_DELAY            10              /* 10us per poll spin */
2600 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
2601
2602 #define EEPROM_STAT_ADDR        0x7bfc
2603 #define VPD_BASE                0x400
2604 #define VPD_BASE_OLD            0
2605 #define VPD_LEN                 1024
2606 #define VPD_INFO_FLD_HDR_SIZE   3
2607 #define CHELSIO_VPD_UNIQUE_ID   0x82
2608
2609 /*
2610  * Small utility function to wait till any outstanding VPD Access is complete.
2611  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2612  * VPD Access in flight.  This allows us to handle the problem of having a
2613  * previous VPD Access time out and prevent an attempt to inject a new VPD
2614  * Request before any in-flight VPD reguest has completed.
2615  */
2616 static int t4_seeprom_wait(struct adapter *adapter)
2617 {
2618         unsigned int base = adapter->params.pci.vpd_cap_addr;
2619         int max_poll;
2620
2621         /*
2622          * If no VPD Access is in flight, we can just return success right
2623          * away.
2624          */
2625         if (!adapter->vpd_busy)
2626                 return 0;
2627
2628         /*
2629          * Poll the VPD Capability Address/Flag register waiting for it
2630          * to indicate that the operation is complete.
2631          */
2632         max_poll = EEPROM_MAX_POLL;
2633         do {
2634                 u16 val;
2635
2636                 udelay(EEPROM_DELAY);
2637                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2638
2639                 /*
2640                  * If the operation is complete, mark the VPD as no longer
2641                  * busy and return success.
2642                  */
2643                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2644                         adapter->vpd_busy = 0;
2645                         return 0;
2646                 }
2647         } while (--max_poll);
2648
2649         /*
2650          * Failure!  Note that we leave the VPD Busy status set in order to
2651          * avoid pushing a new VPD Access request into the VPD Capability till
2652          * the current operation eventually succeeds.  It's a bug to issue a
2653          * new request when an existing request is in flight and will result
2654          * in corrupt hardware state.
2655          */
2656         return -ETIMEDOUT;
2657 }
2658
2659 /**
2660  *      t4_seeprom_read - read a serial EEPROM location
2661  *      @adapter: adapter to read
2662  *      @addr: EEPROM virtual address
2663  *      @data: where to store the read data
2664  *
2665  *      Read a 32-bit word from a location in serial EEPROM using the card's PCI
2666  *      VPD capability.  Note that this function must be called with a virtual
2667  *      address.
2668  */
2669 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2670 {
2671         unsigned int base = adapter->params.pci.vpd_cap_addr;
2672         int ret;
2673
2674         /*
2675          * VPD Accesses must alway be 4-byte aligned!
2676          */
2677         if (addr >= EEPROMVSIZE || (addr & 3))
2678                 return -EINVAL;
2679
2680         /*
2681          * Wait for any previous operation which may still be in flight to
2682          * complete.
2683          */
2684         ret = t4_seeprom_wait(adapter);
2685         if (ret) {
2686                 CH_ERR(adapter, "VPD still busy from previous operation\n");
2687                 return ret;
2688         }
2689
2690         /*
2691          * Issue our new VPD Read request, mark the VPD as being busy and wait
2692          * for our request to complete.  If it doesn't complete, note the
2693          * error and return it to our caller.  Note that we do not reset the
2694          * VPD Busy status!
2695          */
2696         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2697         adapter->vpd_busy = 1;
2698         adapter->vpd_flag = PCI_VPD_ADDR_F;
2699         ret = t4_seeprom_wait(adapter);
2700         if (ret) {
2701                 CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2702                 return ret;
2703         }
2704
2705         /*
2706          * Grab the returned data, swizzle it into our endianess and
2707          * return success.
2708          */
2709         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2710         *data = le32_to_cpu(*data);
2711         return 0;
2712 }
2713
2714 /**
2715  *      t4_seeprom_write - write a serial EEPROM location
2716  *      @adapter: adapter to write
2717  *      @addr: virtual EEPROM address
2718  *      @data: value to write
2719  *
2720  *      Write a 32-bit word to a location in serial EEPROM using the card's PCI
2721  *      VPD capability.  Note that this function must be called with a virtual
2722  *      address.
2723  */
2724 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2725 {
2726         unsigned int base = adapter->params.pci.vpd_cap_addr;
2727         int ret;
2728         u32 stats_reg;
2729         int max_poll;
2730
2731         /*
2732          * VPD Accesses must alway be 4-byte aligned!
2733          */
2734         if (addr >= EEPROMVSIZE || (addr & 3))
2735                 return -EINVAL;
2736
2737         /*
2738          * Wait for any previous operation which may still be in flight to
2739          * complete.
2740          */
2741         ret = t4_seeprom_wait(adapter);
2742         if (ret) {
2743                 CH_ERR(adapter, "VPD still busy from previous operation\n");
2744                 return ret;
2745         }
2746
2747         /*
2748          * Issue our new VPD Read request, mark the VPD as being busy and wait
2749          * for our request to complete.  If it doesn't complete, note the
2750          * error and return it to our caller.  Note that we do not reset the
2751          * VPD Busy status!
2752          */
2753         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2754                                  cpu_to_le32(data));
2755         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2756                                  (u16)addr | PCI_VPD_ADDR_F);
2757         adapter->vpd_busy = 1;
2758         adapter->vpd_flag = 0;
2759         ret = t4_seeprom_wait(adapter);
2760         if (ret) {
2761                 CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2762                 return ret;
2763         }
2764
2765         /*
2766          * Reset PCI_VPD_DATA register after a transaction and wait for our
2767          * request to complete. If it doesn't complete, return error.
2768          */
2769         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2770         max_poll = EEPROM_MAX_POLL;
2771         do {
2772                 udelay(EEPROM_DELAY);
2773                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2774         } while ((stats_reg & 0x1) && --max_poll);
2775         if (!max_poll)
2776                 return -ETIMEDOUT;
2777
2778         /* Return success! */
2779         return 0;
2780 }
2781
2782 /**
2783  *      t4_eeprom_ptov - translate a physical EEPROM address to virtual
2784  *      @phys_addr: the physical EEPROM address
2785  *      @fn: the PCI function number
2786  *      @sz: size of function-specific area
2787  *
2788  *      Translate a physical EEPROM address to virtual.  The first 1K is
2789  *      accessed through virtual addresses starting at 31K, the rest is
2790  *      accessed through virtual addresses starting at 0.
2791  *
2792  *      The mapping is as follows:
2793  *      [0..1K) -> [31K..32K)
2794  *      [1K..1K+A) -> [ES-A..ES)
2795  *      [1K+A..ES) -> [0..ES-A-1K)
2796  *
2797  *      where A = @fn * @sz, and ES = EEPROM size.
2798  */
2799 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2800 {
2801         fn *= sz;
2802         if (phys_addr < 1024)
2803                 return phys_addr + (31 << 10);
2804         if (phys_addr < 1024 + fn)
2805                 return EEPROMSIZE - fn + phys_addr - 1024;
2806         if (phys_addr < EEPROMSIZE)
2807                 return phys_addr - 1024 - fn;
2808         return -EINVAL;
2809 }
2810
2811 /**
2812  *      t4_seeprom_wp - enable/disable EEPROM write protection
2813  *      @adapter: the adapter
2814  *      @enable: whether to enable or disable write protection
2815  *
2816  *      Enables or disables write protection on the serial EEPROM.
2817  */
2818 int t4_seeprom_wp(struct adapter *adapter, int enable)
2819 {
2820         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2821 }
2822
2823 /**
2824  *      get_vpd_keyword_val - Locates an information field keyword in the VPD
2825  *      @v: Pointer to buffered vpd data structure
2826  *      @kw: The keyword to search for
2827  *
2828  *      Returns the value of the information field keyword or
2829  *      -ENOENT otherwise.
2830  */
2831 static int get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw)
2832 {
2833         int i;
2834         unsigned int offset , len;
2835         const u8 *buf = (const u8 *)v;
2836         const u8 *vpdr_len = &v->vpdr_len[0];
2837         offset = sizeof(struct t4_vpd_hdr);
2838         len =  (u16)vpdr_len[0] + ((u16)vpdr_len[1] << 8);
2839
2840         if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) {
2841                 return -ENOENT;
2842         }
2843
2844         for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2845                 if(memcmp(buf + i , kw , 2) == 0){
2846                         i += VPD_INFO_FLD_HDR_SIZE;
2847                         return i;
2848                 }
2849
2850                 i += VPD_INFO_FLD_HDR_SIZE + buf[i+2];
2851         }
2852
2853         return -ENOENT;
2854 }
2855
2856
2857 /**
2858  *      get_vpd_params - read VPD parameters from VPD EEPROM
2859  *      @adapter: adapter to read
2860  *      @p: where to store the parameters
2861  *      @vpd: caller provided temporary space to read the VPD into
2862  *
2863  *      Reads card parameters stored in VPD EEPROM.
2864  */
2865 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
2866     u8 *vpd)
2867 {
2868         int i, ret, addr;
2869         int ec, sn, pn, na;
2870         u8 csum;
2871         const struct t4_vpd_hdr *v;
2872
2873         /*
2874          * Card information normally starts at VPD_BASE but early cards had
2875          * it at 0.
2876          */
2877         ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd));
2878         if (ret)
2879                 return (ret);
2880
2881         /*
2882          * The VPD shall have a unique identifier specified by the PCI SIG.
2883          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2884          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2885          * is expected to automatically put this entry at the
2886          * beginning of the VPD.
2887          */
2888         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2889
2890         for (i = 0; i < VPD_LEN; i += 4) {
2891                 ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i));
2892                 if (ret)
2893                         return ret;
2894         }
2895         v = (const struct t4_vpd_hdr *)vpd;
2896
2897 #define FIND_VPD_KW(var,name) do { \
2898         var = get_vpd_keyword_val(v , name); \
2899         if (var < 0) { \
2900                 CH_ERR(adapter, "missing VPD keyword " name "\n"); \
2901                 return -EINVAL; \
2902         } \
2903 } while (0)
2904
2905         FIND_VPD_KW(i, "RV");
2906         for (csum = 0; i >= 0; i--)
2907                 csum += vpd[i];
2908
2909         if (csum) {
2910                 CH_ERR(adapter,
2911                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2912                 return -EINVAL;
2913         }
2914
2915         FIND_VPD_KW(ec, "EC");
2916         FIND_VPD_KW(sn, "SN");
2917         FIND_VPD_KW(pn, "PN");
2918         FIND_VPD_KW(na, "NA");
2919 #undef FIND_VPD_KW
2920
2921         memcpy(p->id, v->id_data, ID_LEN);
2922         strstrip(p->id);
2923         memcpy(p->ec, vpd + ec, EC_LEN);
2924         strstrip(p->ec);
2925         i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
2926         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2927         strstrip(p->sn);
2928         i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
2929         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2930         strstrip((char *)p->pn);
2931         i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
2932         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2933         strstrip((char *)p->na);
2934
2935         return 0;
2936 }
2937
2938 /* serial flash and firmware constants and flash config file constants */
2939 enum {
2940         SF_ATTEMPTS = 10,       /* max retries for SF operations */
2941
2942         /* flash command opcodes */
2943         SF_PROG_PAGE    = 2,    /* program page */
2944         SF_WR_DISABLE   = 4,    /* disable writes */
2945         SF_RD_STATUS    = 5,    /* read status register */
2946         SF_WR_ENABLE    = 6,    /* enable writes */
2947         SF_RD_DATA_FAST = 0xb,  /* read flash */
2948         SF_RD_ID        = 0x9f, /* read ID */
2949         SF_ERASE_SECTOR = 0xd8, /* erase sector */
2950 };
2951
2952 /**
2953  *      sf1_read - read data from the serial flash
2954  *      @adapter: the adapter
2955  *      @byte_cnt: number of bytes to read
2956  *      @cont: whether another operation will be chained
2957  *      @lock: whether to lock SF for PL access only
2958  *      @valp: where to store the read data
2959  *
2960  *      Reads up to 4 bytes of data from the serial flash.  The location of
2961  *      the read needs to be specified prior to calling this by issuing the
2962  *      appropriate commands to the serial flash.
2963  */
2964 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2965                     int lock, u32 *valp)
2966 {
2967         int ret;
2968
2969         if (!byte_cnt || byte_cnt > 4)
2970                 return -EINVAL;
2971         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2972                 return -EBUSY;
2973         t4_write_reg(adapter, A_SF_OP,
2974                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2975         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2976         if (!ret)
2977                 *valp = t4_read_reg(adapter, A_SF_DATA);
2978         return ret;
2979 }
2980
2981 /**
2982  *      sf1_write - write data to the serial flash
2983  *      @adapter: the adapter
2984  *      @byte_cnt: number of bytes to write
2985  *      @cont: whether another operation will be chained
2986  *      @lock: whether to lock SF for PL access only
2987  *      @val: value to write
2988  *
2989  *      Writes up to 4 bytes of data to the serial flash.  The location of
2990  *      the write needs to be specified prior to calling this by issuing the
2991  *      appropriate commands to the serial flash.
2992  */
2993 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2994                      int lock, u32 val)
2995 {
2996         if (!byte_cnt || byte_cnt > 4)
2997                 return -EINVAL;
2998         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2999                 return -EBUSY;
3000         t4_write_reg(adapter, A_SF_DATA, val);
3001         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3002                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3003         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3004 }
3005
3006 /**
3007  *      flash_wait_op - wait for a flash operation to complete
3008  *      @adapter: the adapter
3009  *      @attempts: max number of polls of the status register
3010  *      @delay: delay between polls in ms
3011  *
3012  *      Wait for a flash operation to complete by polling the status register.
3013  */
3014 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3015 {
3016         int ret;
3017         u32 status;
3018
3019         while (1) {
3020                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3021                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3022                         return ret;
3023                 if (!(status & 1))
3024                         return 0;
3025                 if (--attempts == 0)
3026                         return -EAGAIN;
3027                 if (delay)
3028                         msleep(delay);
3029         }
3030 }
3031
3032 /**
3033  *      t4_read_flash - read words from serial flash
3034  *      @adapter: the adapter
3035  *      @addr: the start address for the read
3036  *      @nwords: how many 32-bit words to read
3037  *      @data: where to store the read data
3038  *      @byte_oriented: whether to store data as bytes or as words
3039  *
3040  *      Read the specified number of 32-bit words from the serial flash.
3041  *      If @byte_oriented is set the read data is stored as a byte array
3042  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
3043  *      natural endianness.
3044  */
3045 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3046                   unsigned int nwords, u32 *data, int byte_oriented)
3047 {
3048         int ret;
3049
3050         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3051                 return -EINVAL;
3052
3053         addr = swab32(addr) | SF_RD_DATA_FAST;
3054
3055         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3056             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3057                 return ret;
3058
3059         for ( ; nwords; nwords--, data++) {
3060                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3061                 if (nwords == 1)
3062                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3063                 if (ret)
3064                         return ret;
3065                 if (byte_oriented)
3066                         *data = (__force __u32)(cpu_to_be32(*data));
3067         }
3068         return 0;
3069 }
3070
3071 /**
3072  *      t4_write_flash - write up to a page of data to the serial flash
3073  *      @adapter: the adapter
3074  *      @addr: the start address to write
3075  *      @n: length of data to write in bytes
3076  *      @data: the data to write
3077  *      @byte_oriented: whether to store data as bytes or as words
3078  *
3079  *      Writes up to a page of data (256 bytes) to the serial flash starting
3080  *      at the given address.  All the data must be written to the same page.
3081  *      If @byte_oriented is set the write data is stored as byte stream
3082  *      (i.e. matches what on disk), otherwise in big-endian.
3083  */
3084 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3085                           unsigned int n, const u8 *data, int byte_oriented)
3086 {
3087         int ret;
3088         u32 buf[SF_PAGE_SIZE / 4];
3089         unsigned int i, c, left, val, offset = addr & 0xff;
3090
3091         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3092                 return -EINVAL;
3093
3094         val = swab32(addr) | SF_PROG_PAGE;
3095
3096         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3097             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3098                 goto unlock;
3099
3100         for (left = n; left; left -= c) {
3101                 c = min(left, 4U);
3102                 for (val = 0, i = 0; i < c; ++i)
3103                         val = (val << 8) + *data++;
3104
3105                 if (!byte_oriented)
3106                         val = cpu_to_be32(val);
3107
3108                 ret = sf1_write(adapter, c, c != left, 1, val);
3109                 if (ret)
3110                         goto unlock;
3111         }
3112         ret = flash_wait_op(adapter, 8, 1);
3113         if (ret)
3114                 goto unlock;
3115
3116         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3117
3118         /* Read the page to verify the write succeeded */
3119         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3120                             byte_oriented);
3121         if (ret)
3122                 return ret;
3123
3124         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3125                 CH_ERR(adapter,
3126                         "failed to correctly write the flash page at %#x\n",
3127                         addr);
3128                 return -EIO;
3129         }
3130         return 0;
3131
3132 unlock:
3133         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3134         return ret;
3135 }
3136
3137 /**
3138  *      t4_get_fw_version - read the firmware version
3139  *      @adapter: the adapter
3140  *      @vers: where to place the version
3141  *
3142  *      Reads the FW version from flash.
3143  */
3144 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3145 {
3146         return t4_read_flash(adapter, FLASH_FW_START +
3147                              offsetof(struct fw_hdr, fw_ver), 1,
3148                              vers, 0);
3149 }
3150
3151 /**
3152  *      t4_get_tp_version - read the TP microcode version
3153  *      @adapter: the adapter
3154  *      @vers: where to place the version
3155  *
3156  *      Reads the TP microcode version from flash.
3157  */
3158 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3159 {
3160         return t4_read_flash(adapter, FLASH_FW_START +
3161                              offsetof(struct fw_hdr, tp_microcode_ver),
3162                              1, vers, 0);
3163 }
3164
3165 /**
3166  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3167  *      @adapter: the adapter
3168  *      @vers: where to place the version
3169  *
3170  *      Reads the Expansion ROM header from FLASH and returns the version
3171  *      number (if present) through the @vers return value pointer.  We return
3172  *      this in the Firmware Version Format since it's convenient.  Return
3173  *      0 on success, -ENOENT if no Expansion ROM is present.
3174  */
3175 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3176 {
3177         struct exprom_header {
3178                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3179                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3180         } *hdr;
3181         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3182                                            sizeof(u32))];
3183         int ret;
3184
3185         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3186                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3187                             0);
3188         if (ret)
3189                 return ret;
3190
3191         hdr = (struct exprom_header *)exprom_header_buf;
3192         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3193                 return -ENOENT;
3194
3195         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3196                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3197                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3198                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3199         return 0;
3200 }
3201
3202 /**
3203  *      t4_flash_erase_sectors - erase a range of flash sectors
3204  *      @adapter: the adapter
3205  *      @start: the first sector to erase
3206  *      @end: the last sector to erase
3207  *
3208  *      Erases the sectors in the given inclusive range.
3209  */
3210 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3211 {
3212         int ret = 0;
3213
3214         if (end >= adapter->params.sf_nsec)
3215                 return -EINVAL;
3216
3217         while (start <= end) {
3218                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3219                     (ret = sf1_write(adapter, 4, 0, 1,
3220                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3221                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3222                         CH_ERR(adapter,
3223                                 "erase of flash sector %d failed, error %d\n",
3224                                 start, ret);
3225                         break;
3226                 }
3227                 start++;
3228         }
3229         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3230         return ret;
3231 }
3232
3233 /**
3234  *      t4_flash_cfg_addr - return the address of the flash configuration file
3235  *      @adapter: the adapter
3236  *
3237  *      Return the address within the flash where the Firmware Configuration
3238  *      File is stored, or an error if the device FLASH is too small to contain
3239  *      a Firmware Configuration File.
3240  */
3241 int t4_flash_cfg_addr(struct adapter *adapter)
3242 {
3243         /*
3244          * If the device FLASH isn't large enough to hold a Firmware
3245          * Configuration File, return an error.
3246          */
3247         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3248                 return -ENOSPC;
3249
3250         return FLASH_CFG_START;
3251 }
3252
3253 /*
3254  * Return TRUE if the specified firmware matches the adapter.  I.e. T4
3255  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3256  * and emit an error message for mismatched firmware to save our caller the
3257  * effort ...
3258  */
3259 static int t4_fw_matches_chip(struct adapter *adap,
3260                               const struct fw_hdr *hdr)
3261 {
3262         /*
3263          * The expression below will return FALSE for any unsupported adapter
3264          * which will keep us "honest" in the future ...
3265          */
3266         if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3267             (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3268             (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3269                 return 1;
3270
3271         CH_ERR(adap,
3272                 "FW image (%d) is not suitable for this adapter (%d)\n",
3273                 hdr->chip, chip_id(adap));
3274         return 0;
3275 }
3276
3277 /**
3278  *      t4_load_fw - download firmware
3279  *      @adap: the adapter
3280  *      @fw_data: the firmware image to write
3281  *      @size: image size
3282  *
3283  *      Write the supplied firmware image to the card's serial flash.
3284  */
3285 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3286 {
3287         u32 csum;
3288         int ret, addr;
3289         unsigned int i;
3290         u8 first_page[SF_PAGE_SIZE];
3291         const u32 *p = (const u32 *)fw_data;
3292         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3293         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3294         unsigned int fw_start_sec;
3295         unsigned int fw_start;
3296         unsigned int fw_size;
3297
3298         if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3299                 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3300                 fw_start = FLASH_FWBOOTSTRAP_START;
3301                 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3302         } else {
3303                 fw_start_sec = FLASH_FW_START_SEC;
3304                 fw_start = FLASH_FW_START;
3305                 fw_size = FLASH_FW_MAX_SIZE;
3306         }
3307
3308         if (!size) {
3309                 CH_ERR(adap, "FW image has no data\n");
3310                 return -EINVAL;
3311         }
3312         if (size & 511) {
3313                 CH_ERR(adap,
3314                         "FW image size not multiple of 512 bytes\n");
3315                 return -EINVAL;
3316         }
3317         if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3318                 CH_ERR(adap,
3319                         "FW image size differs from size in FW header\n");
3320                 return -EINVAL;
3321         }
3322         if (size > fw_size) {
3323                 CH_ERR(adap, "FW image too large, max is %u bytes\n",
3324                         fw_size);
3325                 return -EFBIG;
3326         }
3327         if (!t4_fw_matches_chip(adap, hdr))
3328                 return -EINVAL;
3329
3330         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3331                 csum += be32_to_cpu(p[i]);
3332
3333         if (csum != 0xffffffff) {
3334                 CH_ERR(adap,
3335                         "corrupted firmware image, checksum %#x\n", csum);
3336                 return -EINVAL;
3337         }
3338
3339         i = DIV_ROUND_UP(size, sf_sec_size);    /* # of sectors spanned */
3340         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3341         if (ret)
3342                 goto out;
3343
3344         /*
3345          * We write the correct version at the end so the driver can see a bad
3346          * version if the FW write fails.  Start by writing a copy of the
3347          * first page with a bad version.
3348          */
3349         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3350         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3351         ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3352         if (ret)
3353                 goto out;
3354
3355         addr = fw_start;
3356         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3357                 addr += SF_PAGE_SIZE;
3358                 fw_data += SF_PAGE_SIZE;
3359                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3360                 if (ret)
3361                         goto out;
3362         }
3363
3364         ret = t4_write_flash(adap,
3365                              fw_start + offsetof(struct fw_hdr, fw_ver),
3366                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3367 out:
3368         if (ret)
3369                 CH_ERR(adap, "firmware download failed, error %d\n",
3370                         ret);
3371         return ret;
3372 }
3373
3374 /**
3375  *      t4_fwcache - firmware cache operation
3376  *      @adap: the adapter
3377  *      @op  : the operation (flush or flush and invalidate)
3378  */
3379 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3380 {
3381         struct fw_params_cmd c;
3382
3383         memset(&c, 0, sizeof(c));
3384         c.op_to_vfn =
3385             cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3386                             F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3387                                 V_FW_PARAMS_CMD_PFN(adap->pf) |
3388                                 V_FW_PARAMS_CMD_VFN(0));
3389         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3390         c.param[0].mnem =
3391             cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3392                             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3393         c.param[0].val = (__force __be32)op;
3394
3395         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3396 }
3397
3398 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3399                         unsigned int *pif_req_wrptr,
3400                         unsigned int *pif_rsp_wrptr)
3401 {
3402         int i, j;
3403         u32 cfg, val, req, rsp;
3404
3405         cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3406         if (cfg & F_LADBGEN)
3407                 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3408
3409         val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3410         req = G_POLADBGWRPTR(val);
3411         rsp = G_PILADBGWRPTR(val);
3412         if (pif_req_wrptr)
3413                 *pif_req_wrptr = req;
3414         if (pif_rsp_wrptr)
3415                 *pif_rsp_wrptr = rsp;
3416
3417         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3418                 for (j = 0; j < 6; j++) {
3419                         t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3420                                      V_PILADBGRDPTR(rsp));
3421                         *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3422                         *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3423                         req++;
3424                         rsp++;
3425                 }
3426                 req = (req + 2) & M_POLADBGRDPTR;
3427                 rsp = (rsp + 2) & M_PILADBGRDPTR;
3428         }
3429         t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3430 }
3431
3432 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3433 {
3434         u32 cfg;
3435         int i, j, idx;
3436
3437         cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3438         if (cfg & F_LADBGEN)
3439                 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3440
3441         for (i = 0; i < CIM_MALA_SIZE; i++) {
3442                 for (j = 0; j < 5; j++) {
3443                         idx = 8 * i + j;
3444                         t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3445                                      V_PILADBGRDPTR(idx));
3446                         *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3447                         *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3448                 }
3449         }
3450         t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3451 }
3452
3453 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3454 {
3455         unsigned int i, j;
3456
3457         for (i = 0; i < 8; i++) {
3458                 u32 *p = la_buf + i;
3459
3460                 t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3461                 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3462                 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3463                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3464                         *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3465         }
3466 }
3467
3468 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3469                      FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3470                      FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
3471
3472 /**
3473  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3474  *      @phy: the PHY to setup
3475  *      @mac: the MAC to setup
3476  *      @lc: the requested link configuration
3477  *
3478  *      Set up a port's MAC and PHY according to a desired link configuration.
3479  *      - If the PHY can auto-negotiate first decide what to advertise, then
3480  *        enable/disable auto-negotiation as desired, and reset.
3481  *      - If the PHY does not auto-negotiate just reset it.
3482  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3483  *        otherwise do it later based on the outcome of auto-negotiation.
3484  */
3485 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3486                   struct link_config *lc)
3487 {
3488         struct fw_port_cmd c;
3489         unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
3490
3491         lc->link_ok = 0;
3492         if (lc->requested_fc & PAUSE_RX)
3493                 fc |= FW_PORT_CAP_FC_RX;
3494         if (lc->requested_fc & PAUSE_TX)
3495                 fc |= FW_PORT_CAP_FC_TX;
3496
3497         memset(&c, 0, sizeof(c));
3498         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3499                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3500                                      V_FW_PORT_CMD_PORTID(port));
3501         c.action_to_len16 =
3502                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3503                             FW_LEN16(c));
3504
3505         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3506                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3507                                              fc);
3508                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3509         } else if (lc->autoneg == AUTONEG_DISABLE) {
3510                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3511                 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3512         } else
3513                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3514
3515         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3516 }
3517
3518 /**
3519  *      t4_restart_aneg - restart autonegotiation
3520  *      @adap: the adapter
3521  *      @mbox: mbox to use for the FW command
3522  *      @port: the port id
3523  *
3524  *      Restarts autonegotiation for the selected port.
3525  */
3526 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3527 {
3528         struct fw_port_cmd c;
3529
3530         memset(&c, 0, sizeof(c));
3531         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3532                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3533                                      V_FW_PORT_CMD_PORTID(port));
3534         c.action_to_len16 =
3535                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3536                             FW_LEN16(c));
3537         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3538         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3539 }
3540
3541 typedef void (*int_handler_t)(struct adapter *adap);
3542
3543 struct intr_info {
3544         unsigned int mask;      /* bits to check in interrupt status */
3545         const char *msg;        /* message to print or NULL */
3546         short stat_idx;         /* stat counter to increment or -1 */
3547         unsigned short fatal;   /* whether the condition reported is fatal */
3548         int_handler_t int_handler;      /* platform-specific int handler */
3549 };
3550
3551 /**
3552  *      t4_handle_intr_status - table driven interrupt handler
3553  *      @adapter: the adapter that generated the interrupt
3554  *      @reg: the interrupt status register to process
3555  *      @acts: table of interrupt actions
3556  *
3557  *      A table driven interrupt handler that applies a set of masks to an
3558  *      interrupt status word and performs the corresponding actions if the
3559  *      interrupts described by the mask have occurred.  The actions include
3560  *      optionally emitting a warning or alert message.  The table is terminated
3561  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
3562  *      conditions.
3563  */
3564 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3565                                  const struct intr_info *acts)
3566 {
3567         int fatal = 0;
3568         unsigned int mask = 0;
3569         unsigned int status = t4_read_reg(adapter, reg);
3570
3571         for ( ; acts->mask; ++acts) {
3572                 if (!(status & acts->mask))
3573                         continue;
3574                 if (acts->fatal) {
3575                         fatal++;
3576                         CH_ALERT(adapter, "%s (0x%x)\n", acts->msg,
3577                                   status & acts->mask);
3578                 } else if (acts->msg)
3579                         CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg,
3580                                  status & acts->mask);
3581                 if (acts->int_handler)
3582                         acts->int_handler(adapter);
3583                 mask |= acts->mask;
3584         }
3585         status &= mask;
3586         if (status)     /* clear processed interrupts */
3587                 t4_write_reg(adapter, reg, status);
3588         return fatal;
3589 }
3590
3591 /*
3592  * Interrupt handler for the PCIE module.
3593  */
3594 static void pcie_intr_handler(struct adapter *adapter)
3595 {
3596         static const struct intr_info sysbus_intr_info[] = {
3597                 { F_RNPP, "RXNP array parity error", -1, 1 },
3598                 { F_RPCP, "RXPC array parity error", -1, 1 },
3599                 { F_RCIP, "RXCIF array parity error", -1, 1 },
3600                 { F_RCCP, "Rx completions control array parity error", -1, 1 },
3601                 { F_RFTP, "RXFT array parity error", -1, 1 },
3602                 { 0 }
3603         };
3604         static const struct intr_info pcie_port_intr_info[] = {
3605                 { F_TPCP, "TXPC array parity error", -1, 1 },
3606                 { F_TNPP, "TXNP array parity error", -1, 1 },
3607                 { F_TFTP, "TXFT array parity error", -1, 1 },
3608                 { F_TCAP, "TXCA array parity error", -1, 1 },
3609                 { F_TCIP, "TXCIF array parity error", -1, 1 },
3610                 { F_RCAP, "RXCA array parity error", -1, 1 },
3611                 { F_OTDD, "outbound request TLP discarded", -1, 1 },
3612                 { F_RDPE, "Rx data parity error", -1, 1 },
3613                 { F_TDUE, "Tx uncorrectable data error", -1, 1 },
3614                 { 0 }
3615         };
3616         static const struct intr_info pcie_intr_info[] = {
3617                 { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
3618                 { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
3619                 { F_MSIDATAPERR, "MSI data parity error", -1, 1 },
3620                 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3621                 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3622                 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3623                 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3624                 { F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
3625                 { F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
3626                 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3627                 { F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
3628                 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3629                 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3630                 { F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
3631                 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3632                 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3633                 { F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
3634                 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3635                 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3636                 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3637                 { F_FIDPERR, "PCI FID parity error", -1, 1 },
3638                 { F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
3639                 { F_MATAGPERR, "PCI MA tag parity error", -1, 1 },
3640                 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3641                 { F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
3642                 { F_RXWRPERR, "PCI Rx write parity error", -1, 1 },
3643                 { F_RPLPERR, "PCI replay buffer parity error", -1, 1 },
3644                 { F_PCIESINT, "PCI core secondary fault", -1, 1 },
3645                 { F_PCIEPINT, "PCI core primary fault", -1, 1 },
3646                 { F_UNXSPLCPLERR, "PCI unexpected split completion error", -1,
3647                   0 },
3648                 { 0 }
3649         };
3650
3651         static const struct intr_info t5_pcie_intr_info[] = {
3652                 { F_MSTGRPPERR, "Master Response Read Queue parity error",
3653                   -1, 1 },
3654                 { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
3655                 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
3656                 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3657                 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3658                 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3659                 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3660                 { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
3661                   -1, 1 },
3662                 { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
3663                   -1, 1 },
3664                 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3665                 { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
3666                 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3667                 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3668                 { F_DREQWRPERR, "PCI DMA channel write request parity error",
3669                   -1, 1 },
3670                 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3671                 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3672                 { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
3673                 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3674                 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3675                 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3676                 { F_FIDPERR, "PCI FID parity error", -1, 1 },
3677                 { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 },
3678                 { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
3679                 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3680                 { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
3681                   -1, 1 },
3682                 { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
3683                   -1, 1 },
3684                 { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
3685                 { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
3686                 { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3687                 { F_READRSPERR, "Outbound read error", -1,
3688                   0 },
3689                 { 0 }
3690         };
3691
3692         int fat;
3693
3694         if (is_t4(adapter))
3695                 fat = t4_handle_intr_status(adapter,
3696                                 A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
3697                                 sysbus_intr_info) +
3698                         t4_handle_intr_status(adapter,
3699                                         A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
3700                                         pcie_port_intr_info) +
3701                         t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3702                                               pcie_intr_info);
3703         else
3704                 fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3705                                             t5_pcie_intr_info);
3706         if (fat)
3707                 t4_fatal_err(adapter);
3708 }
3709
3710 /*
3711  * TP interrupt handler.
3712  */
3713 static void tp_intr_handler(struct adapter *adapter)
3714 {
3715         static const struct intr_info tp_intr_info[] = {
3716                 { 0x3fffffff, "TP parity error", -1, 1 },
3717                 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
3718                 { 0 }
3719         };
3720
3721         if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info))
3722                 t4_fatal_err(adapter);
3723 }
3724
3725 /*
3726  * SGE interrupt handler.
3727  */
3728 static void sge_intr_handler(struct adapter *adapter)
3729 {
3730         u64 v;
3731         u32 err;
3732
3733         static const struct intr_info sge_intr_info[] = {
3734                 { F_ERR_CPL_EXCEED_IQE_SIZE,
3735                   "SGE received CPL exceeding IQE size", -1, 1 },
3736                 { F_ERR_INVALID_CIDX_INC,
3737                   "SGE GTS CIDX increment too large", -1, 0 },
3738                 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
3739                 { F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
3740                 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
3741                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
3742                 { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
3743                   0 },
3744                 { F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
3745                   0 },
3746                 { F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
3747                   0 },
3748                 { F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
3749                   0 },
3750                 { F_ERR_ING_CTXT_PRIO,
3751                   "SGE too many priority ingress contexts", -1, 0 },
3752                 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
3753                 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
3754                 { 0 }
3755         };
3756
3757         static const struct intr_info t4t5_sge_intr_info[] = {
3758                 { F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
3759                 { F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
3760                 { F_ERR_EGR_CTXT_PRIO,
3761                   "SGE too many priority egress contexts", -1, 0 },
3762                 { 0 }
3763         };
3764
3765         /*
3766         * For now, treat below interrupts as fatal so that we disable SGE and
3767         * get better debug */
3768         static const struct intr_info t6_sge_intr_info[] = {
3769                 { F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1,
3770                   "SGE PCIe error for a DBP thread", -1, 1 },
3771                 { F_FATAL_WRE_LEN,
3772                   "SGE Actual WRE packet is less than advertized length",
3773                   -1, 1 },
3774                 { 0 }
3775         };
3776
3777         v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) |
3778                 ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32);
3779         if (v) {
3780                 CH_ALERT(adapter, "SGE parity error (%#llx)\n",
3781                                 (unsigned long long)v);
3782                 t4_write_reg(adapter, A_SGE_INT_CAUSE1, v);
3783                 t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32);
3784         }
3785
3786         v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info);
3787         if (chip_id(adapter) <= CHELSIO_T5)
3788                 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
3789                                            t4t5_sge_intr_info);
3790         else
3791                 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
3792                                            t6_sge_intr_info);
3793
3794         err = t4_read_reg(adapter, A_SGE_ERROR_STATS);
3795         if (err & F_ERROR_QID_VALID) {
3796                 CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err));
3797                 if (err & F_UNCAPTURED_ERROR)
3798                         CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n");
3799                 t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID |
3800                              F_UNCAPTURED_ERROR);
3801         }
3802
3803         if (v != 0)
3804                 t4_fatal_err(adapter);
3805 }
3806
3807 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\
3808                       F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR)
3809 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\
3810                       F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR)
3811
3812 /*
3813  * CIM interrupt handler.
3814  */
3815 static void cim_intr_handler(struct adapter *adapter)
3816 {
3817         static const struct intr_info cim_intr_info[] = {
3818                 { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
3819                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3820                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3821                 { F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
3822                 { F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
3823                 { F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
3824                 { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
3825                 { 0 }
3826         };
3827         static const struct intr_info cim_upintr_info[] = {
3828                 { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 },
3829                 { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 },
3830                 { F_ILLWRINT, "CIM illegal write", -1, 1 },
3831                 { F_ILLRDINT, "CIM illegal read", -1, 1 },
3832                 { F_ILLRDBEINT, "CIM illegal read BE", -1, 1 },
3833                 { F_ILLWRBEINT, "CIM illegal write BE", -1, 1 },
3834                 { F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
3835                 { F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
3836                 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
3837                 { F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
3838                 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
3839                 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
3840                 { F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
3841                 { F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
3842                 { F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
3843                 { F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
3844                 { F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
3845                 { F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
3846                 { F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
3847                 { F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
3848                 { F_SGLRDPLINT , "CIM single read from PL space", -1, 1 },
3849                 { F_SGLWRPLINT , "CIM single write to PL space", -1, 1 },
3850                 { F_BLKRDPLINT , "CIM block read from PL space", -1, 1 },
3851                 { F_BLKWRPLINT , "CIM block write to PL space", -1, 1 },
3852                 { F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
3853                 { F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
3854                 { F_TIMEOUTINT , "CIM PIF timeout", -1, 1 },
3855                 { F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
3856                 { 0 }
3857         };
3858         int fat;
3859
3860         if (t4_read_reg(adapter, A_PCIE_FW) & F_PCIE_FW_ERR)
3861                 t4_report_fw_error(adapter);
3862
3863         fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE,
3864                                     cim_intr_info) +
3865               t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE,
3866                                     cim_upintr_info);
3867         if (fat)
3868                 t4_fatal_err(adapter);
3869 }
3870
3871 /*
3872  * ULP RX interrupt handler.
3873  */
3874 static void ulprx_intr_handler(struct adapter *adapter)
3875 {
3876         static const struct intr_info ulprx_intr_info[] = {
3877                 { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 },
3878                 { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 },
3879                 { 0x7fffff, "ULPRX parity error", -1, 1 },
3880                 { 0 }
3881         };
3882
3883         if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info))
3884                 t4_fatal_err(adapter);
3885 }
3886
3887 /*
3888  * ULP TX interrupt handler.
3889  */
3890 static void ulptx_intr_handler(struct adapter *adapter)
3891 {
3892         static const struct intr_info ulptx_intr_info[] = {
3893                 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
3894                   0 },
3895                 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
3896                   0 },
3897                 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
3898                   0 },
3899                 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
3900                   0 },
3901                 { 0xfffffff, "ULPTX parity error", -1, 1 },
3902                 { 0 }
3903         };
3904
3905         if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info))
3906                 t4_fatal_err(adapter);
3907 }
3908
3909 /*
3910  * PM TX interrupt handler.
3911  */
3912 static void pmtx_intr_handler(struct adapter *adapter)
3913 {
3914         static const struct intr_info pmtx_intr_info[] = {
3915                 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
3916                 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
3917                 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
3918                 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
3919                 { 0xffffff0, "PMTX framing error", -1, 1 },
3920                 { F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
3921                 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1,
3922                   1 },
3923                 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
3924                 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
3925                 { 0 }
3926         };
3927
3928         if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info))
3929                 t4_fatal_err(adapter);
3930 }
3931
3932 /*
3933  * PM RX interrupt handler.
3934  */
3935 static void pmrx_intr_handler(struct adapter *adapter)
3936 {
3937         static const struct intr_info pmrx_intr_info[] = {
3938                 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
3939                 { 0x3ffff0, "PMRX framing error", -1, 1 },
3940                 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
3941                 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1,
3942                   1 },
3943                 { F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
3944                 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
3945                 { 0 }
3946         };
3947
3948         if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info))
3949                 t4_fatal_err(adapter);
3950 }
3951
3952 /*
3953  * CPL switch interrupt handler.
3954  */
3955 static void cplsw_intr_handler(struct adapter *adapter)
3956 {
3957         static const struct intr_info cplsw_intr_info[] = {
3958                 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
3959                 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
3960                 { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
3961                 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
3962                 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
3963                 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
3964                 { 0 }
3965         };
3966
3967         if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info))
3968                 t4_fatal_err(adapter);
3969 }
3970
3971 /*
3972  * LE interrupt handler.
3973  */
3974 static void le_intr_handler(struct adapter *adap)
3975 {
3976         unsigned int chip_ver = chip_id(adap);
3977         static const struct intr_info le_intr_info[] = {
3978                 { F_LIPMISS, "LE LIP miss", -1, 0 },
3979                 { F_LIP0, "LE 0 LIP error", -1, 0 },
3980                 { F_PARITYERR, "LE parity error", -1, 1 },
3981                 { F_UNKNOWNCMD, "LE unknown command", -1, 1 },
3982                 { F_REQQPARERR, "LE request queue parity error", -1, 1 },
3983                 { 0 }
3984         };
3985
3986         static const struct intr_info t6_le_intr_info[] = {
3987                 { F_T6_LIPMISS, "LE LIP miss", -1, 0 },
3988                 { F_T6_LIP0, "LE 0 LIP error", -1, 0 },
3989                 { F_TCAMINTPERR, "LE parity error", -1, 1 },
3990                 { F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 },
3991                 { F_SSRAMINTPERR, "LE request queue parity error", -1, 1 },
3992                 { 0 }
3993         };
3994
3995         if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE,
3996                                   (chip_ver <= CHELSIO_T5) ?
3997                                   le_intr_info : t6_le_intr_info))
3998                 t4_fatal_err(adap);
3999 }
4000
4001 /*
4002  * MPS interrupt handler.
4003  */
4004 static void mps_intr_handler(struct adapter *adapter)
4005 {
4006         static const struct intr_info mps_rx_intr_info[] = {
4007                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4008                 { 0 }
4009         };
4010         static const struct intr_info mps_tx_intr_info[] = {
4011                 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 },
4012                 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4013                 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error",
4014                   -1, 1 },
4015                 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error",
4016                   -1, 1 },
4017                 { F_BUBBLE, "MPS Tx underflow", -1, 1 },
4018                 { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
4019                 { F_FRMERR, "MPS Tx framing error", -1, 1 },
4020                 { 0 }
4021         };
4022         static const struct intr_info mps_trc_intr_info[] = {
4023                 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 },
4024                 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1,
4025                   1 },
4026                 { F_MISCPERR, "MPS TRC misc parity error", -1, 1 },
4027                 { 0 }
4028         };
4029         static const struct intr_info mps_stat_sram_intr_info[] = {
4030                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4031                 { 0 }
4032         };
4033         static const struct intr_info mps_stat_tx_intr_info[] = {
4034                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4035                 { 0 }
4036         };
4037         static const struct intr_info mps_stat_rx_intr_info[] = {
4038                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4039                 { 0 }
4040         };
4041         static const struct intr_info mps_cls_intr_info[] = {
4042                 { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
4043                 { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
4044                 { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
4045                 { 0 }
4046         };
4047
4048         int fat;
4049
4050         fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE,
4051                                     mps_rx_intr_info) +
4052               t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE,
4053                                     mps_tx_intr_info) +
4054               t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE,
4055                                     mps_trc_intr_info) +
4056               t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4057                                     mps_stat_sram_intr_info) +
4058               t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4059                                     mps_stat_tx_intr_info) +
4060               t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4061                                     mps_stat_rx_intr_info) +
4062               t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE,
4063                                     mps_cls_intr_info);
4064
4065         t4_write_reg(adapter, A_MPS_INT_CAUSE, 0);
4066         t4_read_reg(adapter, A_MPS_INT_CAUSE);  /* flush */
4067         if (fat)
4068                 t4_fatal_err(adapter);
4069 }
4070
4071 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \
4072                       F_ECC_UE_INT_CAUSE)
4073
4074 /*
4075  * EDC/MC interrupt handler.
4076  */
4077 static void mem_intr_handler(struct adapter *adapter, int idx)
4078 {
4079         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4080
4081         unsigned int addr, cnt_addr, v;
4082
4083         if (idx <= MEM_EDC1) {
4084                 addr = EDC_REG(A_EDC_INT_CAUSE, idx);
4085                 cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx);
4086         } else if (idx == MEM_MC) {
4087                 if (is_t4(adapter)) {
4088                         addr = A_MC_INT_CAUSE;
4089                         cnt_addr = A_MC_ECC_STATUS;
4090                 } else {
4091                         addr = A_MC_P_INT_CAUSE;
4092                         cnt_addr = A_MC_P_ECC_STATUS;
4093                 }
4094         } else {
4095                 addr = MC_REG(A_MC_P_INT_CAUSE, 1);
4096                 cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1);
4097         }
4098
4099         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4100         if (v & F_PERR_INT_CAUSE)
4101                 CH_ALERT(adapter, "%s FIFO parity error\n",
4102                           name[idx]);
4103         if (v & F_ECC_CE_INT_CAUSE) {
4104                 u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr));
4105
4106                 t4_edc_err_read(adapter, idx);
4107
4108                 t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT));
4109                 CH_WARN_RATELIMIT(adapter,
4110                                   "%u %s correctable ECC data error%s\n",
4111                                   cnt, name[idx], cnt > 1 ? "s" : "");
4112         }
4113         if (v & F_ECC_UE_INT_CAUSE)
4114                 CH_ALERT(adapter,
4115                          "%s uncorrectable ECC data error\n", name[idx]);
4116
4117         t4_write_reg(adapter, addr, v);
4118         if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE))
4119                 t4_fatal_err(adapter);
4120 }
4121
4122 /*
4123  * MA interrupt handler.
4124  */
4125 static void ma_intr_handler(struct adapter *adapter)
4126 {
4127         u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE);
4128
4129         if (status & F_MEM_PERR_INT_CAUSE) {
4130                 CH_ALERT(adapter,
4131                           "MA parity error, parity status %#x\n",
4132                           t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1));
4133                 if (is_t5(adapter))
4134                         CH_ALERT(adapter,
4135                                   "MA parity error, parity status %#x\n",
4136                                   t4_read_reg(adapter,
4137                                               A_MA_PARITY_ERROR_STATUS2));
4138         }
4139         if (status & F_MEM_WRAP_INT_CAUSE) {
4140                 v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS);
4141                 CH_ALERT(adapter, "MA address wrap-around error by "
4142                           "client %u to address %#x\n",
4143                           G_MEM_WRAP_CLIENT_NUM(v),
4144                           G_MEM_WRAP_ADDRESS(v) << 4);
4145         }
4146         t4_write_reg(adapter, A_MA_INT_CAUSE, status);
4147         t4_fatal_err(adapter);
4148 }
4149
4150 /*
4151  * SMB interrupt handler.
4152  */
4153 static void smb_intr_handler(struct adapter *adap)
4154 {
4155         static const struct intr_info smb_intr_info[] = {
4156                 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
4157                 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
4158                 { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
4159                 { 0 }
4160         };
4161
4162         if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info))
4163                 t4_fatal_err(adap);
4164 }
4165
4166 /*
4167  * NC-SI interrupt handler.
4168  */
4169 static void ncsi_intr_handler(struct adapter *adap)
4170 {
4171         static const struct intr_info ncsi_intr_info[] = {
4172                 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
4173                 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
4174                 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
4175                 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
4176                 { 0 }
4177         };
4178
4179         if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info))
4180                 t4_fatal_err(adap);
4181 }
4182
4183 /*
4184  * XGMAC interrupt handler.
4185  */
4186 static void xgmac_intr_handler(struct adapter *adap, int port)
4187 {
4188         u32 v, int_cause_reg;
4189
4190         if (is_t4(adap))
4191                 int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
4192         else
4193                 int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
4194
4195         v = t4_read_reg(adap, int_cause_reg);
4196
4197         v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR);
4198         if (!v)
4199                 return;
4200
4201         if (v & F_TXFIFO_PRTY_ERR)
4202                 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n",
4203                           port);
4204         if (v & F_RXFIFO_PRTY_ERR)
4205                 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n",
4206                           port);
4207         t4_write_reg(adap, int_cause_reg, v);
4208         t4_fatal_err(adap);
4209 }
4210
4211 /*
4212  * PL interrupt handler.
4213  */
4214 static void pl_intr_handler(struct adapter *adap)
4215 {
4216         static const struct intr_info pl_intr_info[] = {
4217                 { F_FATALPERR, "Fatal parity error", -1, 1 },
4218                 { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 },
4219                 { 0 }
4220         };
4221
4222         static const struct intr_info t5_pl_intr_info[] = {
4223                 { F_FATALPERR, "Fatal parity error", -1, 1 },
4224                 { 0 }
4225         };
4226
4227         if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE,
4228                                   is_t4(adap) ?
4229                                   pl_intr_info : t5_pl_intr_info))
4230                 t4_fatal_err(adap);
4231 }
4232
4233 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
4234
4235 /**
4236  *      t4_slow_intr_handler - control path interrupt handler
4237  *      @adapter: the adapter
4238  *
4239  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4240  *      The designation 'slow' is because it involves register reads, while
4241  *      data interrupts typically don't involve any MMIOs.
4242  */
4243 int t4_slow_intr_handler(struct adapter *adapter)
4244 {
4245         u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
4246
4247         if (!(cause & GLBL_INTR_MASK))
4248                 return 0;
4249         if (cause & F_CIM)
4250                 cim_intr_handler(adapter);
4251         if (cause & F_MPS)
4252                 mps_intr_handler(adapter);
4253         if (cause & F_NCSI)
4254                 ncsi_intr_handler(adapter);
4255         if (cause & F_PL)
4256                 pl_intr_handler(adapter);
4257         if (cause & F_SMB)
4258                 smb_intr_handler(adapter);
4259         if (cause & F_MAC0)
4260                 xgmac_intr_handler(adapter, 0);
4261         if (cause & F_MAC1)
4262                 xgmac_intr_handler(adapter, 1);
4263         if (cause & F_MAC2)
4264                 xgmac_intr_handler(adapter, 2);
4265         if (cause & F_MAC3)
4266                 xgmac_intr_handler(adapter, 3);
4267         if (cause & F_PCIE)
4268                 pcie_intr_handler(adapter);
4269         if (cause & F_MC0)
4270                 mem_intr_handler(adapter, MEM_MC);
4271         if (is_t5(adapter) && (cause & F_MC1))
4272                 mem_intr_handler(adapter, MEM_MC1);
4273         if (cause & F_EDC0)
4274                 mem_intr_handler(adapter, MEM_EDC0);
4275         if (cause & F_EDC1)
4276                 mem_intr_handler(adapter, MEM_EDC1);
4277         if (cause & F_LE)
4278                 le_intr_handler(adapter);
4279         if (cause & F_TP)
4280                 tp_intr_handler(adapter);
4281         if (cause & F_MA)
4282                 ma_intr_handler(adapter);
4283         if (cause & F_PM_TX)
4284                 pmtx_intr_handler(adapter);
4285         if (cause & F_PM_RX)
4286                 pmrx_intr_handler(adapter);
4287         if (cause & F_ULP_RX)
4288                 ulprx_intr_handler(adapter);
4289         if (cause & F_CPL_SWITCH)
4290                 cplsw_intr_handler(adapter);
4291         if (cause & F_SGE)
4292                 sge_intr_handler(adapter);
4293         if (cause & F_ULP_TX)
4294                 ulptx_intr_handler(adapter);
4295
4296         /* Clear the interrupts just processed for which we are the master. */
4297         t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK);
4298         (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */
4299         return 1;
4300 }
4301
4302 /**
4303  *      t4_intr_enable - enable interrupts
4304  *      @adapter: the adapter whose interrupts should be enabled
4305  *
4306  *      Enable PF-specific interrupts for the calling function and the top-level
4307  *      interrupt concentrator for global interrupts.  Interrupts are already
4308  *      enabled at each module, here we just enable the roots of the interrupt
4309  *      hierarchies.
4310  *
4311  *      Note: this function should be called only when the driver manages
4312  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4313  *      function at a time should be doing this.
4314  */
4315 void t4_intr_enable(struct adapter *adapter)
4316 {
4317         u32 val = 0;
4318         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4319         u32 pf = (chip_id(adapter) <= CHELSIO_T5
4320                   ? G_SOURCEPF(whoami)
4321                   : G_T6_SOURCEPF(whoami));
4322
4323         if (chip_id(adapter) <= CHELSIO_T5)
4324                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
4325         else
4326                 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
4327         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
4328                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
4329                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
4330                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
4331                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4332                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
4333                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
4334         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
4335         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
4336 }
4337
4338 /**
4339  *      t4_intr_disable - disable interrupts
4340  *      @adapter: the adapter whose interrupts should be disabled
4341  *
4342  *      Disable interrupts.  We only disable the top-level interrupt
4343  *      concentrators.  The caller must be a PCI function managing global
4344  *      interrupts.
4345  */
4346 void t4_intr_disable(struct adapter *adapter)
4347 {
4348         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4349         u32 pf = (chip_id(adapter) <= CHELSIO_T5
4350                   ? G_SOURCEPF(whoami)
4351                   : G_T6_SOURCEPF(whoami));
4352
4353         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
4354         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
4355 }
4356
4357 /**
4358  *      t4_intr_clear - clear all interrupts
4359  *      @adapter: the adapter whose interrupts should be cleared
4360  *
4361  *      Clears all interrupts.  The caller must be a PCI function managing
4362  *      global interrupts.
4363  */
4364 void t4_intr_clear(struct adapter *adapter)
4365 {
4366         static const unsigned int cause_reg[] = {
4367                 A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3,
4368                 A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE,
4369                 A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE,
4370                 A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1),
4371                 A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE,
4372                 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4373                 A_TP_INT_CAUSE,
4374                 A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE,
4375                 A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE,
4376                 A_MPS_RX_PERR_INT_CAUSE,
4377                 A_CPL_INTR_CAUSE,
4378                 MYPF_REG(A_PL_PF_INT_CAUSE),
4379                 A_PL_PL_INT_CAUSE,
4380                 A_LE_DB_INT_CAUSE,
4381         };
4382
4383         unsigned int i;
4384
4385         for (i = 0; i < ARRAY_SIZE(cause_reg); ++i)
4386                 t4_write_reg(adapter, cause_reg[i], 0xffffffff);
4387
4388         t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE :
4389                                 A_MC_P_INT_CAUSE, 0xffffffff);
4390
4391         if (is_t4(adapter)) {
4392                 t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4393                                 0xffffffff);
4394                 t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4395                                 0xffffffff);
4396         } else
4397                 t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
4398
4399         t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK);
4400         (void) t4_read_reg(adapter, A_PL_INT_CAUSE);          /* flush */
4401 }
4402
4403 /**
4404  *      hash_mac_addr - return the hash value of a MAC address
4405  *      @addr: the 48-bit Ethernet MAC address
4406  *
4407  *      Hashes a MAC address according to the hash function used by HW inexact
4408  *      (hash) address matching.
4409  */
4410 static int hash_mac_addr(const u8 *addr)
4411 {
4412         u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
4413         u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
4414         a ^= b;
4415         a ^= (a >> 12);
4416         a ^= (a >> 6);
4417         return a & 0x3f;
4418 }
4419
4420 /**
4421  *      t4_config_rss_range - configure a portion of the RSS mapping table
4422  *      @adapter: the adapter
4423  *      @mbox: mbox to use for the FW command
4424  *      @viid: virtual interface whose RSS subtable is to be written
4425  *      @start: start entry in the table to write
4426  *      @n: how many table entries to write
4427  *      @rspq: values for the "response queue" (Ingress Queue) lookup table
4428  *      @nrspq: number of values in @rspq
4429  *
4430  *      Programs the selected part of the VI's RSS mapping table with the
4431  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4432  *      until the full table range is populated.
4433  *
4434  *      The caller must ensure the values in @rspq are in the range allowed for
4435  *      @viid.
4436  */
4437 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4438                         int start, int n, const u16 *rspq, unsigned int nrspq)
4439 {
4440         int ret;
4441         const u16 *rsp = rspq;
4442         const u16 *rsp_end = rspq + nrspq;
4443         struct fw_rss_ind_tbl_cmd cmd;
4444
4445         memset(&cmd, 0, sizeof(cmd));
4446         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
4447                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4448                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
4449         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4450
4451         /*
4452          * Each firmware RSS command can accommodate up to 32 RSS Ingress
4453          * Queue Identifiers.  These Ingress Queue IDs are packed three to
4454          * a 32-bit word as 10-bit values with the upper remaining 2 bits
4455          * reserved.
4456          */
4457         while (n > 0) {
4458                 int nq = min(n, 32);
4459                 int nq_packed = 0;
4460                 __be32 *qp = &cmd.iq0_to_iq2;
4461
4462                 /*
4463                  * Set up the firmware RSS command header to send the next
4464                  * "nq" Ingress Queue IDs to the firmware.
4465                  */
4466                 cmd.niqid = cpu_to_be16(nq);
4467                 cmd.startidx = cpu_to_be16(start);
4468
4469                 /*
4470                  * "nq" more done for the start of the next loop.
4471                  */
4472                 start += nq;
4473                 n -= nq;
4474
4475                 /*
4476                  * While there are still Ingress Queue IDs to stuff into the
4477                  * current firmware RSS command, retrieve them from the
4478                  * Ingress Queue ID array and insert them into the command.
4479                  */
4480                 while (nq > 0) {
4481                         /*
4482                          * Grab up to the next 3 Ingress Queue IDs (wrapping
4483                          * around the Ingress Queue ID array if necessary) and
4484                          * insert them into the firmware RSS command at the
4485                          * current 3-tuple position within the commad.
4486                          */
4487                         u16 qbuf[3];
4488                         u16 *qbp = qbuf;
4489                         int nqbuf = min(3, nq);
4490
4491                         nq -= nqbuf;
4492                         qbuf[0] = qbuf[1] = qbuf[2] = 0;
4493                         while (nqbuf && nq_packed < 32) {
4494                                 nqbuf--;
4495                                 nq_packed++;
4496                                 *qbp++ = *rsp++;
4497                                 if (rsp >= rsp_end)
4498                                         rsp = rspq;
4499                         }
4500                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
4501                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
4502                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
4503                 }
4504
4505                 /*
4506                  * Send this portion of the RRS table update to the firmware;
4507                  * bail out on any errors.
4508                  */
4509                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4510                 if (ret)
4511                         return ret;
4512         }
4513         return 0;
4514 }
4515
4516 /**
4517  *      t4_config_glbl_rss - configure the global RSS mode
4518  *      @adapter: the adapter
4519  *      @mbox: mbox to use for the FW command
4520  *      @mode: global RSS mode
4521  *      @flags: mode-specific flags
4522  *
4523  *      Sets the global RSS mode.
4524  */
4525 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4526                        unsigned int flags)
4527 {
4528         struct fw_rss_glb_config_cmd c;
4529
4530         memset(&c, 0, sizeof(c));
4531         c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
4532                                     F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4533         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4534         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4535                 c.u.manual.mode_pkd =
4536                         cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4537         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4538                 c.u.basicvirtual.mode_pkd =
4539                         cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4540                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4541         } else
4542                 return -EINVAL;
4543         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4544 }
4545
4546 /**
4547  *      t4_config_vi_rss - configure per VI RSS settings
4548  *      @adapter: the adapter
4549  *      @mbox: mbox to use for the FW command
4550  *      @viid: the VI id
4551  *      @flags: RSS flags
4552  *      @defq: id of the default RSS queue for the VI.
4553  *
4554  *      Configures VI-specific RSS properties.
4555  */
4556 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4557                      unsigned int flags, unsigned int defq)
4558 {
4559         struct fw_rss_vi_config_cmd c;
4560
4561         memset(&c, 0, sizeof(c));
4562         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4563                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4564                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
4565         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4566         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4567                                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
4568         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4569 }
4570
4571 /* Read an RSS table row */
4572 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4573 {
4574         t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
4575         return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
4576                                    5, 0, val);
4577 }
4578
4579 /**
4580  *      t4_read_rss - read the contents of the RSS mapping table
4581  *      @adapter: the adapter
4582  *      @map: holds the contents of the RSS mapping table
4583  *
4584  *      Reads the contents of the RSS hash->queue mapping table.
4585  */
4586 int t4_read_rss(struct adapter *adapter, u16 *map)
4587 {
4588         u32 val;
4589         int i, ret;
4590
4591         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4592                 ret = rd_rss_row(adapter, i, &val);
4593                 if (ret)
4594                         return ret;
4595                 *map++ = G_LKPTBLQUEUE0(val);
4596                 *map++ = G_LKPTBLQUEUE1(val);
4597         }
4598         return 0;
4599 }
4600
4601 /**
4602  *      t4_fw_tp_pio_rw - Access TP PIO through LDST
4603  *      @adap: the adapter
4604  *      @vals: where the indirect register values are stored/written
4605  *      @nregs: how many indirect registers to read/write
4606  *      @start_idx: index of first indirect register to read/write
4607  *      @rw: Read (1) or Write (0)
4608  *
4609  *      Access TP PIO registers through LDST
4610  */
4611 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4612                      unsigned int start_index, unsigned int rw)
4613 {
4614         int ret, i;
4615         int cmd = FW_LDST_ADDRSPC_TP_PIO;
4616         struct fw_ldst_cmd c;
4617
4618         for (i = 0 ; i < nregs; i++) {
4619                 memset(&c, 0, sizeof(c));
4620                 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
4621                                                 F_FW_CMD_REQUEST |
4622                                                 (rw ? F_FW_CMD_READ :
4623                                                      F_FW_CMD_WRITE) |
4624                                                 V_FW_LDST_CMD_ADDRSPACE(cmd));
4625                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4626
4627                 c.u.addrval.addr = cpu_to_be32(start_index + i);
4628                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
4629                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4630                 if (ret == 0) {
4631                         if (rw)
4632                                 vals[i] = be32_to_cpu(c.u.addrval.val);
4633                 }
4634         }
4635 }
4636
4637 /**
4638  *      t4_read_rss_key - read the global RSS key
4639  *      @adap: the adapter
4640  *      @key: 10-entry array holding the 320-bit RSS key
4641  *
4642  *      Reads the global 320-bit RSS key.
4643  */
4644 void t4_read_rss_key(struct adapter *adap, u32 *key)
4645 {
4646         if (t4_use_ldst(adap))
4647                 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
4648         else
4649                 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
4650                                  A_TP_RSS_SECRET_KEY0);
4651 }
4652
4653 /**
4654  *      t4_write_rss_key - program one of the RSS keys
4655  *      @adap: the adapter
4656  *      @key: 10-entry array holding the 320-bit RSS key
4657  *      @idx: which RSS key to write
4658  *
4659  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
4660  *      0..15 the corresponding entry in the RSS key table is written,
4661  *      otherwise the global RSS key is written.
4662  */
4663 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
4664 {
4665         u8 rss_key_addr_cnt = 16;
4666         u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
4667
4668         /*
4669          * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4670          * allows access to key addresses 16-63 by using KeyWrAddrX
4671          * as index[5:4](upper 2) into key table
4672          */
4673         if ((chip_id(adap) > CHELSIO_T5) &&
4674             (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
4675                 rss_key_addr_cnt = 32;
4676
4677         if (t4_use_ldst(adap))
4678                 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
4679         else
4680                 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
4681                                   A_TP_RSS_SECRET_KEY0);
4682
4683         if (idx >= 0 && idx < rss_key_addr_cnt) {
4684                 if (rss_key_addr_cnt > 16)
4685                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
4686                                      V_KEYWRADDRX(idx >> 4) |
4687                                      V_T6_VFWRADDR(idx) | F_KEYWREN);
4688                 else
4689                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
4690                                      V_KEYWRADDR(idx) | F_KEYWREN);
4691         }
4692 }
4693
4694 /**
4695  *      t4_read_rss_pf_config - read PF RSS Configuration Table
4696  *      @adapter: the adapter
4697  *      @index: the entry in the PF RSS table to read
4698  *      @valp: where to store the returned value
4699  *
4700  *      Reads the PF RSS Configuration Table at the specified index and returns
4701  *      the value found there.
4702  */
4703 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4704                            u32 *valp)
4705 {
4706         if (t4_use_ldst(adapter))
4707                 t4_fw_tp_pio_rw(adapter, valp, 1,
4708                                 A_TP_RSS_PF0_CONFIG + index, 1);
4709         else
4710                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4711                                  valp, 1, A_TP_RSS_PF0_CONFIG + index);
4712 }
4713
4714 /**
4715  *      t4_write_rss_pf_config - write PF RSS Configuration Table
4716  *      @adapter: the adapter
4717  *      @index: the entry in the VF RSS table to read
4718  *      @val: the value to store
4719  *
4720  *      Writes the PF RSS Configuration Table at the specified index with the
4721  *      specified value.
4722  */
4723 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
4724                             u32 val)
4725 {
4726         if (t4_use_ldst(adapter))
4727                 t4_fw_tp_pio_rw(adapter, &val, 1,
4728                                 A_TP_RSS_PF0_CONFIG + index, 0);
4729         else
4730                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4731                                   &val, 1, A_TP_RSS_PF0_CONFIG + index);
4732 }
4733
4734 /**
4735  *      t4_read_rss_vf_config - read VF RSS Configuration Table
4736  *      @adapter: the adapter
4737  *      @index: the entry in the VF RSS table to read
4738  *      @vfl: where to store the returned VFL
4739  *      @vfh: where to store the returned VFH
4740  *
4741  *      Reads the VF RSS Configuration Table at the specified index and returns
4742  *      the (VFL, VFH) values found there.
4743  */
4744 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4745                            u32 *vfl, u32 *vfh)
4746 {
4747         u32 vrt, mask, data;
4748
4749         if (chip_id(adapter) <= CHELSIO_T5) {
4750                 mask = V_VFWRADDR(M_VFWRADDR);
4751                 data = V_VFWRADDR(index);
4752         } else {
4753                  mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
4754                  data = V_T6_VFWRADDR(index);
4755         }
4756         /*
4757          * Request that the index'th VF Table values be read into VFL/VFH.
4758          */
4759         vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
4760         vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
4761         vrt |= data | F_VFRDEN;
4762         t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
4763
4764         /*
4765          * Grab the VFL/VFH values ...
4766          */
4767         if (t4_use_ldst(adapter)) {
4768                 t4_fw_tp_pio_rw(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, 1);
4769                 t4_fw_tp_pio_rw(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, 1);
4770         } else {
4771                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4772                                  vfl, 1, A_TP_RSS_VFL_CONFIG);
4773                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4774                                  vfh, 1, A_TP_RSS_VFH_CONFIG);
4775         }
4776 }
4777
4778 /**
4779  *      t4_write_rss_vf_config - write VF RSS Configuration Table
4780  *
4781  *      @adapter: the adapter
4782  *      @index: the entry in the VF RSS table to write
4783  *      @vfl: the VFL to store
4784  *      @vfh: the VFH to store
4785  *
4786  *      Writes the VF RSS Configuration Table at the specified index with the
4787  *      specified (VFL, VFH) values.
4788  */
4789 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
4790                             u32 vfl, u32 vfh)
4791 {
4792         u32 vrt, mask, data;
4793
4794         if (chip_id(adapter) <= CHELSIO_T5) {
4795                 mask = V_VFWRADDR(M_VFWRADDR);
4796                 data = V_VFWRADDR(index);
4797         } else {
4798                 mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
4799                 data = V_T6_VFWRADDR(index);
4800         }
4801
4802         /*
4803          * Load up VFL/VFH with the values to be written ...
4804          */
4805         if (t4_use_ldst(adapter)) {
4806                 t4_fw_tp_pio_rw(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, 0);
4807                 t4_fw_tp_pio_rw(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, 0);
4808         } else {
4809                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4810                                   &vfl, 1, A_TP_RSS_VFL_CONFIG);
4811                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4812                                   &vfh, 1, A_TP_RSS_VFH_CONFIG);
4813         }
4814
4815         /*
4816          * Write the VFL/VFH into the VF Table at index'th location.
4817          */
4818         vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
4819         vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
4820         vrt |= data | F_VFRDEN;
4821         t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
4822 }
4823
4824 /**
4825  *      t4_read_rss_pf_map - read PF RSS Map
4826  *      @adapter: the adapter
4827  *
4828  *      Reads the PF RSS Map register and returns its value.
4829  */
4830 u32 t4_read_rss_pf_map(struct adapter *adapter)
4831 {
4832         u32 pfmap;
4833
4834         if (t4_use_ldst(adapter))
4835                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 1);
4836         else
4837                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4838                                  &pfmap, 1, A_TP_RSS_PF_MAP);
4839         return pfmap;
4840 }
4841
4842 /**
4843  *      t4_write_rss_pf_map - write PF RSS Map
4844  *      @adapter: the adapter
4845  *      @pfmap: PF RSS Map value
4846  *
4847  *      Writes the specified value to the PF RSS Map register.
4848  */
4849 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap)
4850 {
4851         if (t4_use_ldst(adapter))
4852                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 0);
4853         else
4854                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4855                                   &pfmap, 1, A_TP_RSS_PF_MAP);
4856 }
4857
4858 /**
4859  *      t4_read_rss_pf_mask - read PF RSS Mask
4860  *      @adapter: the adapter
4861  *
4862  *      Reads the PF RSS Mask register and returns its value.
4863  */
4864 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4865 {
4866         u32 pfmask;
4867
4868         if (t4_use_ldst(adapter))
4869                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 1);
4870         else
4871                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4872                                  &pfmask, 1, A_TP_RSS_PF_MSK);
4873         return pfmask;
4874 }
4875
4876 /**
4877  *      t4_write_rss_pf_mask - write PF RSS Mask
4878  *      @adapter: the adapter
4879  *      @pfmask: PF RSS Mask value
4880  *
4881  *      Writes the specified value to the PF RSS Mask register.
4882  */
4883 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask)
4884 {
4885         if (t4_use_ldst(adapter))
4886                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 0);
4887         else
4888                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4889                                   &pfmask, 1, A_TP_RSS_PF_MSK);
4890 }
4891
4892 /**
4893  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
4894  *      @adap: the adapter
4895  *      @v4: holds the TCP/IP counter values
4896  *      @v6: holds the TCP/IPv6 counter values
4897  *
4898  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4899  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4900  */
4901 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4902                          struct tp_tcp_stats *v6)
4903 {
4904         u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
4905
4906 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
4907 #define STAT(x)     val[STAT_IDX(x)]
4908 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4909
4910         if (v4) {
4911                 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
4912                                  ARRAY_SIZE(val), A_TP_MIB_TCP_OUT_RST);
4913                 v4->tcp_out_rsts = STAT(OUT_RST);
4914                 v4->tcp_in_segs  = STAT64(IN_SEG);
4915                 v4->tcp_out_segs = STAT64(OUT_SEG);
4916                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4917         }
4918         if (v6) {
4919                 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
4920                                  ARRAY_SIZE(val), A_TP_MIB_TCP_V6OUT_RST);
4921                 v6->tcp_out_rsts = STAT(OUT_RST);
4922                 v6->tcp_in_segs  = STAT64(IN_SEG);
4923                 v6->tcp_out_segs = STAT64(OUT_SEG);
4924                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4925         }
4926 #undef STAT64
4927 #undef STAT
4928 #undef STAT_IDX
4929 }
4930
4931 /**
4932  *      t4_tp_get_err_stats - read TP's error MIB counters
4933  *      @adap: the adapter
4934  *      @st: holds the counter values
4935  *
4936  *      Returns the values of TP's error counters.
4937  */
4938 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4939 {
4940         int nchan = adap->chip_params->nchan;
4941
4942         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4943                         st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0);
4944         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4945                         st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0);
4946         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4947                         st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0);
4948         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4949                         st->tnl_cong_drops, nchan, A_TP_MIB_TNL_CNG_DROP_0);
4950         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4951                         st->ofld_chan_drops, nchan, A_TP_MIB_OFD_CHN_DROP_0);
4952         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4953                         st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0);
4954         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4955                         st->ofld_vlan_drops, nchan, A_TP_MIB_OFD_VLN_DROP_0);
4956         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4957                         st->tcp6_in_errs, nchan, A_TP_MIB_TCP_V6IN_ERR_0);
4958
4959         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
4960                          &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP);
4961 }
4962
4963 /**
4964  *      t4_tp_get_proxy_stats - read TP's proxy MIB counters
4965  *      @adap: the adapter
4966  *      @st: holds the counter values
4967  *
4968  *      Returns the values of TP's proxy counters.
4969  */
4970 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st)
4971 {
4972         int nchan = adap->chip_params->nchan;
4973
4974         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->proxy,
4975                          nchan, A_TP_MIB_TNL_LPBK_0);
4976 }
4977
4978 /**
4979  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
4980  *      @adap: the adapter
4981  *      @st: holds the counter values
4982  *
4983  *      Returns the values of TP's CPL counters.
4984  */
4985 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4986 {
4987         int nchan = adap->chip_params->nchan;
4988
4989         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req,
4990                          nchan, A_TP_MIB_CPL_IN_REQ_0);
4991         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->rsp,
4992                          nchan, A_TP_MIB_CPL_OUT_RSP_0);
4993 }
4994
4995 /**
4996  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4997  *      @adap: the adapter
4998  *      @st: holds the counter values
4999  *
5000  *      Returns the values of TP's RDMA counters.
5001  */
5002 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5003 {
5004         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->rqe_dfr_pkt,
5005                          2, A_TP_MIB_RQE_DFR_PKT);
5006 }
5007
5008 /**
5009  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5010  *      @adap: the adapter
5011  *      @idx: the port index
5012  *      @st: holds the counter values
5013  *
5014  *      Returns the values of TP's FCoE counters for the selected port.
5015  */
5016 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5017                        struct tp_fcoe_stats *st)
5018 {
5019         u32 val[2];
5020
5021         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_ddp,
5022                          1, A_TP_MIB_FCOE_DDP_0 + idx);
5023         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_drop,
5024                          1, A_TP_MIB_FCOE_DROP_0 + idx);
5025         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5026                          2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx);
5027         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5028 }
5029
5030 /**
5031  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5032  *      @adap: the adapter
5033  *      @st: holds the counter values
5034  *
5035  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5036  */
5037 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5038 {
5039         u32 val[4];
5040
5041         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 4,
5042                          A_TP_MIB_USM_PKTS);
5043         st->frames = val[0];
5044         st->drops = val[1];
5045         st->octets = ((u64)val[2] << 32) | val[3];
5046 }
5047
5048 /**
5049  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5050  *      @adap: the adapter
5051  *      @mtus: where to store the MTU values
5052  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5053  *
5054  *      Reads the HW path MTU table.
5055  */
5056 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5057 {
5058         u32 v;
5059         int i;
5060
5061         for (i = 0; i < NMTUS; ++i) {
5062                 t4_write_reg(adap, A_TP_MTU_TABLE,
5063                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
5064                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
5065                 mtus[i] = G_MTUVALUE(v);
5066                 if (mtu_log)
5067                         mtu_log[i] = G_MTUWIDTH(v);
5068         }
5069 }
5070
5071 /**
5072  *      t4_read_cong_tbl - reads the congestion control table
5073  *      @adap: the adapter
5074  *      @incr: where to store the alpha values
5075  *
5076  *      Reads the additive increments programmed into the HW congestion
5077  *      control table.
5078  */
5079 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5080 {
5081         unsigned int mtu, w;
5082
5083         for (mtu = 0; mtu < NMTUS; ++mtu)
5084                 for (w = 0; w < NCCTRL_WIN; ++w) {
5085                         t4_write_reg(adap, A_TP_CCTRL_TABLE,
5086                                      V_ROWINDEX(0xffff) | (mtu << 5) | w);
5087                         incr[mtu][w] = (u16)t4_read_reg(adap,
5088                                                 A_TP_CCTRL_TABLE) & 0x1fff;
5089                 }
5090 }
5091
5092 /**
5093  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5094  *      @adap: the adapter
5095  *      @addr: the indirect TP register address
5096  *      @mask: specifies the field within the register to modify
5097  *      @val: new value for the field
5098  *
5099  *      Sets a field of an indirect TP register to the given value.
5100  */
5101 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5102                             unsigned int mask, unsigned int val)
5103 {
5104         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
5105         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
5106         t4_write_reg(adap, A_TP_PIO_DATA, val);
5107 }
5108
5109 /**
5110  *      init_cong_ctrl - initialize congestion control parameters
5111  *      @a: the alpha values for congestion control
5112  *      @b: the beta values for congestion control
5113  *
5114  *      Initialize the congestion control parameters.
5115  */
5116 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5117 {
5118         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5119         a[9] = 2;
5120         a[10] = 3;
5121         a[11] = 4;
5122         a[12] = 5;
5123         a[13] = 6;
5124         a[14] = 7;
5125         a[15] = 8;
5126         a[16] = 9;
5127         a[17] = 10;
5128         a[18] = 14;
5129         a[19] = 17;
5130         a[20] = 21;
5131         a[21] = 25;
5132         a[22] = 30;
5133         a[23] = 35;
5134         a[24] = 45;
5135         a[25] = 60;
5136         a[26] = 80;
5137         a[27] = 100;
5138         a[28] = 200;
5139         a[29] = 300;
5140         a[30] = 400;
5141         a[31] = 500;
5142
5143         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5144         b[9] = b[10] = 1;
5145         b[11] = b[12] = 2;
5146         b[13] = b[14] = b[15] = b[16] = 3;
5147         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5148         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5149         b[28] = b[29] = 6;
5150         b[30] = b[31] = 7;
5151 }
5152
5153 /* The minimum additive increment value for the congestion control table */
5154 #define CC_MIN_INCR 2U
5155
5156 /**
5157  *      t4_load_mtus - write the MTU and congestion control HW tables
5158  *      @adap: the adapter
5159  *      @mtus: the values for the MTU table
5160  *      @alpha: the values for the congestion control alpha parameter
5161  *      @beta: the values for the congestion control beta parameter
5162  *
5163  *      Write the HW MTU table with the supplied MTUs and the high-speed
5164  *      congestion control table with the supplied alpha, beta, and MTUs.
5165  *      We write the two tables together because the additive increments
5166  *      depend on the MTUs.
5167  */
5168 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5169                   const unsigned short *alpha, const unsigned short *beta)
5170 {
5171         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5172                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5173                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5174                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5175         };
5176
5177         unsigned int i, w;
5178
5179         for (i = 0; i < NMTUS; ++i) {
5180                 unsigned int mtu = mtus[i];
5181                 unsigned int log2 = fls(mtu);
5182
5183                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5184                         log2--;
5185                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
5186                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
5187
5188                 for (w = 0; w < NCCTRL_WIN; ++w) {
5189                         unsigned int inc;
5190
5191                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5192                                   CC_MIN_INCR);
5193
5194                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
5195                                      (w << 16) | (beta[w] << 13) | inc);
5196                 }
5197         }
5198 }
5199
5200 /**
5201  *      t4_set_pace_tbl - set the pace table
5202  *      @adap: the adapter
5203  *      @pace_vals: the pace values in microseconds
5204  *      @start: index of the first entry in the HW pace table to set
5205  *      @n: how many entries to set
5206  *
5207  *      Sets (a subset of the) HW pace table.
5208  */
5209 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
5210                      unsigned int start, unsigned int n)
5211 {
5212         unsigned int vals[NTX_SCHED], i;
5213         unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
5214
5215         if (n > NTX_SCHED)
5216             return -ERANGE;
5217
5218         /* convert values from us to dack ticks, rounding to closest value */
5219         for (i = 0; i < n; i++, pace_vals++) {
5220                 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
5221                 if (vals[i] > 0x7ff)
5222                         return -ERANGE;
5223                 if (*pace_vals && vals[i] == 0)
5224                         return -ERANGE;
5225         }
5226         for (i = 0; i < n; i++, start++)
5227                 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
5228         return 0;
5229 }
5230
5231 /**
5232  *      t4_set_sched_bps - set the bit rate for a HW traffic scheduler
5233  *      @adap: the adapter
5234  *      @kbps: target rate in Kbps
5235  *      @sched: the scheduler index
5236  *
5237  *      Configure a Tx HW scheduler for the target rate.
5238  */
5239 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
5240 {
5241         unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
5242         unsigned int clk = adap->params.vpd.cclk * 1000;
5243         unsigned int selected_cpt = 0, selected_bpt = 0;
5244
5245         if (kbps > 0) {
5246                 kbps *= 125;     /* -> bytes */
5247                 for (cpt = 1; cpt <= 255; cpt++) {
5248                         tps = clk / cpt;
5249                         bpt = (kbps + tps / 2) / tps;
5250                         if (bpt > 0 && bpt <= 255) {
5251                                 v = bpt * tps;
5252                                 delta = v >= kbps ? v - kbps : kbps - v;
5253                                 if (delta < mindelta) {
5254                                         mindelta = delta;
5255                                         selected_cpt = cpt;
5256                                         selected_bpt = bpt;
5257                                 }
5258                         } else if (selected_cpt)
5259                                 break;
5260                 }
5261                 if (!selected_cpt)
5262                         return -EINVAL;
5263         }
5264         t4_write_reg(adap, A_TP_TM_PIO_ADDR,
5265                      A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
5266         v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5267         if (sched & 1)
5268                 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
5269         else
5270                 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
5271         t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5272         return 0;
5273 }
5274
5275 /**
5276  *      t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
5277  *      @adap: the adapter
5278  *      @sched: the scheduler index
5279  *      @ipg: the interpacket delay in tenths of nanoseconds
5280  *
5281  *      Set the interpacket delay for a HW packet rate scheduler.
5282  */
5283 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
5284 {
5285         unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
5286
5287         /* convert ipg to nearest number of core clocks */
5288         ipg *= core_ticks_per_usec(adap);
5289         ipg = (ipg + 5000) / 10000;
5290         if (ipg > M_TXTIMERSEPQ0)
5291                 return -EINVAL;
5292
5293         t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
5294         v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5295         if (sched & 1)
5296                 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
5297         else
5298                 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
5299         t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5300         t4_read_reg(adap, A_TP_TM_PIO_DATA);
5301         return 0;
5302 }
5303
5304 /*
5305  * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5306  * clocks.  The formula is
5307  *
5308  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5309  *
5310  * which is equivalent to
5311  *
5312  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5313  */
5314 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5315 {
5316         u64 v = bytes256 * adap->params.vpd.cclk;
5317
5318         return v * 62 + v / 2;
5319 }
5320
5321 /**
5322  *      t4_get_chan_txrate - get the current per channel Tx rates
5323  *      @adap: the adapter
5324  *      @nic_rate: rates for NIC traffic
5325  *      @ofld_rate: rates for offloaded traffic
5326  *
5327  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5328  *      for each channel.
5329  */
5330 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5331 {
5332         u32 v;
5333
5334         v = t4_read_reg(adap, A_TP_TX_TRATE);
5335         nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
5336         nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
5337         if (adap->chip_params->nchan > 2) {
5338                 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
5339                 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
5340         }
5341
5342         v = t4_read_reg(adap, A_TP_TX_ORATE);
5343         ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
5344         ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
5345         if (adap->chip_params->nchan > 2) {
5346                 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
5347                 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
5348         }
5349 }
5350
5351 /**
5352  *      t4_set_trace_filter - configure one of the tracing filters
5353  *      @adap: the adapter
5354  *      @tp: the desired trace filter parameters
5355  *      @idx: which filter to configure
5356  *      @enable: whether to enable or disable the filter
5357  *
5358  *      Configures one of the tracing filters available in HW.  If @tp is %NULL
5359  *      it indicates that the filter is already written in the register and it
5360  *      just needs to be enabled or disabled.
5361  */
5362 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5363     int idx, int enable)
5364 {
5365         int i, ofst = idx * 4;
5366         u32 data_reg, mask_reg, cfg;
5367         u32 multitrc = F_TRCMULTIFILTER;
5368         u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
5369
5370         if (idx < 0 || idx >= NTRACE)
5371                 return -EINVAL;
5372
5373         if (tp == NULL || !enable) {
5374                 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
5375                     enable ? en : 0);
5376                 return 0;
5377         }
5378
5379         /*
5380          * TODO - After T4 data book is updated, specify the exact
5381          * section below.
5382          *
5383          * See T4 data book - MPS section for a complete description
5384          * of the below if..else handling of A_MPS_TRC_CFG register
5385          * value.
5386          */
5387         cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
5388         if (cfg & F_TRCMULTIFILTER) {
5389                 /*
5390                  * If multiple tracers are enabled, then maximum
5391                  * capture size is 2.5KB (FIFO size of a single channel)
5392                  * minus 2 flits for CPL_TRACE_PKT header.
5393                  */
5394                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5395                         return -EINVAL;
5396         } else {
5397                 /*
5398                  * If multiple tracers are disabled, to avoid deadlocks
5399                  * maximum packet capture size of 9600 bytes is recommended.
5400                  * Also in this mode, only trace0 can be enabled and running.
5401                  */
5402                 multitrc = 0;
5403                 if (tp->snap_len > 9600 || idx)
5404                         return -EINVAL;
5405         }
5406
5407         if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
5408             tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
5409             tp->min_len > M_TFMINPKTSIZE)
5410                 return -EINVAL;
5411
5412         /* stop the tracer we'll be changing */
5413         t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
5414
5415         idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
5416         data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
5417         mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
5418
5419         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5420                 t4_write_reg(adap, data_reg, tp->data[i]);
5421                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5422         }
5423         t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
5424                      V_TFCAPTUREMAX(tp->snap_len) |
5425                      V_TFMINPKTSIZE(tp->min_len));
5426         t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
5427                      V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
5428                      (is_t4(adap) ?
5429                      V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
5430                      V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
5431
5432         return 0;
5433 }
5434
5435 /**
5436  *      t4_get_trace_filter - query one of the tracing filters
5437  *      @adap: the adapter
5438  *      @tp: the current trace filter parameters
5439  *      @idx: which trace filter to query
5440  *      @enabled: non-zero if the filter is enabled
5441  *
5442  *      Returns the current settings of one of the HW tracing filters.
5443  */
5444 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5445                          int *enabled)
5446 {
5447         u32 ctla, ctlb;
5448         int i, ofst = idx * 4;
5449         u32 data_reg, mask_reg;
5450
5451         ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
5452         ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
5453
5454         if (is_t4(adap)) {
5455                 *enabled = !!(ctla & F_TFEN);
5456                 tp->port =  G_TFPORT(ctla);
5457                 tp->invert = !!(ctla & F_TFINVERTMATCH);
5458         } else {
5459                 *enabled = !!(ctla & F_T5_TFEN);
5460                 tp->port = G_T5_TFPORT(ctla);
5461                 tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
5462         }
5463         tp->snap_len = G_TFCAPTUREMAX(ctlb);
5464         tp->min_len = G_TFMINPKTSIZE(ctlb);
5465         tp->skip_ofst = G_TFOFFSET(ctla);
5466         tp->skip_len = G_TFLENGTH(ctla);
5467
5468         ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
5469         data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
5470         mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
5471
5472         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5473                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5474                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5475         }
5476 }
5477
5478 /**
5479  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5480  *      @adap: the adapter
5481  *      @cnt: where to store the count statistics
5482  *      @cycles: where to store the cycle statistics
5483  *
5484  *      Returns performance statistics from PMTX.
5485  */
5486 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5487 {
5488         int i;
5489         u32 data[2];
5490
5491         for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5492                 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
5493                 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
5494                 if (is_t4(adap))
5495                         cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
5496                 else {
5497                         t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
5498                                          A_PM_TX_DBG_DATA, data, 2,
5499                                          A_PM_TX_DBG_STAT_MSB);
5500                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5501                 }
5502         }
5503 }
5504
5505 /**
5506  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5507  *      @adap: the adapter
5508  *      @cnt: where to store the count statistics
5509  *      @cycles: where to store the cycle statistics
5510  *
5511  *      Returns performance statistics from PMRX.
5512  */
5513 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5514 {
5515         int i;
5516         u32 data[2];
5517
5518         for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5519                 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
5520                 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
5521                 if (is_t4(adap)) {
5522                         cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
5523                 } else {
5524                         t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
5525                                          A_PM_RX_DBG_DATA, data, 2,
5526                                          A_PM_RX_DBG_STAT_MSB);
5527                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5528                 }
5529         }
5530 }
5531
5532 /**
5533  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5534  *      @adap: the adapter
5535  *      @idx: the port index
5536  *
5537  *      Returns a bitmap indicating which MPS buffer groups are associated
5538  *      with the given port.  Bit i is set if buffer group i is used by the
5539  *      port.
5540  */
5541 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5542 {
5543         u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
5544
5545         if (n == 0)
5546                 return idx == 0 ? 0xf : 0;
5547         if (n == 1 && chip_id(adap) <= CHELSIO_T5)
5548                 return idx < 2 ? (3 << (2 * idx)) : 0;
5549         return 1 << idx;
5550 }
5551
5552 /**
5553  *      t4_get_port_type_description - return Port Type string description
5554  *      @port_type: firmware Port Type enumeration
5555  */
5556 const char *t4_get_port_type_description(enum fw_port_type port_type)
5557 {
5558         static const char *const port_type_description[] = {
5559                 "Fiber_XFI",
5560                 "Fiber_XAUI",
5561                 "BT_SGMII",
5562                 "BT_XFI",
5563                 "BT_XAUI",
5564                 "KX4",
5565                 "CX4",
5566                 "KX",
5567                 "KR",
5568                 "SFP",
5569                 "BP_AP",
5570                 "BP4_AP",
5571                 "QSFP_10G",
5572                 "QSA",
5573                 "QSFP",
5574                 "BP40_BA",
5575         };
5576
5577         if (port_type < ARRAY_SIZE(port_type_description))
5578                 return port_type_description[port_type];
5579         return "UNKNOWN";
5580 }
5581
5582 /**
5583  *      t4_get_port_stats_offset - collect port stats relative to a previous
5584  *                                 snapshot
5585  *      @adap: The adapter
5586  *      @idx: The port
5587  *      @stats: Current stats to fill
5588  *      @offset: Previous stats snapshot
5589  */
5590 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5591                 struct port_stats *stats,
5592                 struct port_stats *offset)
5593 {
5594         u64 *s, *o;
5595         int i;
5596
5597         t4_get_port_stats(adap, idx, stats);
5598         for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
5599                         i < (sizeof(struct port_stats)/sizeof(u64)) ;
5600                         i++, s++, o++)
5601                 *s -= *o;
5602 }
5603
5604 /**
5605  *      t4_get_port_stats - collect port statistics
5606  *      @adap: the adapter
5607  *      @idx: the port index
5608  *      @p: the stats structure to fill
5609  *
5610  *      Collect statistics related to the given port from HW.
5611  */
5612 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5613 {
5614         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5615
5616 #define GET_STAT(name) \
5617         t4_read_reg64(adap, \
5618         (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
5619         T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
5620 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5621
5622         p->tx_pause             = GET_STAT(TX_PORT_PAUSE);
5623         p->tx_octets            = GET_STAT(TX_PORT_BYTES);
5624         p->tx_frames            = GET_STAT(TX_PORT_FRAMES);
5625         p->tx_bcast_frames      = GET_STAT(TX_PORT_BCAST);
5626         p->tx_mcast_frames      = GET_STAT(TX_PORT_MCAST);
5627         p->tx_ucast_frames      = GET_STAT(TX_PORT_UCAST);
5628         p->tx_error_frames      = GET_STAT(TX_PORT_ERROR);
5629         p->tx_frames_64         = GET_STAT(TX_PORT_64B);
5630         p->tx_frames_65_127     = GET_STAT(TX_PORT_65B_127B);
5631         p->tx_frames_128_255    = GET_STAT(TX_PORT_128B_255B);
5632         p->tx_frames_256_511    = GET_STAT(TX_PORT_256B_511B);
5633         p->tx_frames_512_1023   = GET_STAT(TX_PORT_512B_1023B);
5634         p->tx_frames_1024_1518  = GET_STAT(TX_PORT_1024B_1518B);
5635         p->tx_frames_1519_max   = GET_STAT(TX_PORT_1519B_MAX);
5636         p->tx_drop              = GET_STAT(TX_PORT_DROP);
5637         p->tx_ppp0              = GET_STAT(TX_PORT_PPP0);
5638         p->tx_ppp1              = GET_STAT(TX_PORT_PPP1);
5639         p->tx_ppp2              = GET_STAT(TX_PORT_PPP2);
5640         p->tx_ppp3              = GET_STAT(TX_PORT_PPP3);
5641         p->tx_ppp4              = GET_STAT(TX_PORT_PPP4);
5642         p->tx_ppp5              = GET_STAT(TX_PORT_PPP5);
5643         p->tx_ppp6              = GET_STAT(TX_PORT_PPP6);
5644         p->tx_ppp7              = GET_STAT(TX_PORT_PPP7);
5645
5646         p->rx_pause             = GET_STAT(RX_PORT_PAUSE);
5647         p->rx_octets            = GET_STAT(RX_PORT_BYTES);
5648         p->rx_frames            = GET_STAT(RX_PORT_FRAMES);
5649         p->rx_bcast_frames      = GET_STAT(RX_PORT_BCAST);
5650         p->rx_mcast_frames      = GET_STAT(RX_PORT_MCAST);
5651         p->rx_ucast_frames      = GET_STAT(RX_PORT_UCAST);
5652         p->rx_too_long          = GET_STAT(RX_PORT_MTU_ERROR);
5653         p->rx_jabber            = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5654         p->rx_fcs_err           = GET_STAT(RX_PORT_CRC_ERROR);
5655         p->rx_len_err           = GET_STAT(RX_PORT_LEN_ERROR);
5656         p->rx_symbol_err        = GET_STAT(RX_PORT_SYM_ERROR);
5657         p->rx_runt              = GET_STAT(RX_PORT_LESS_64B);
5658         p->rx_frames_64         = GET_STAT(RX_PORT_64B);
5659         p->rx_frames_65_127     = GET_STAT(RX_PORT_65B_127B);
5660         p->rx_frames_128_255    = GET_STAT(RX_PORT_128B_255B);
5661         p->rx_frames_256_511    = GET_STAT(RX_PORT_256B_511B);
5662         p->rx_frames_512_1023   = GET_STAT(RX_PORT_512B_1023B);
5663         p->rx_frames_1024_1518  = GET_STAT(RX_PORT_1024B_1518B);
5664         p->rx_frames_1519_max   = GET_STAT(RX_PORT_1519B_MAX);
5665         p->rx_ppp0              = GET_STAT(RX_PORT_PPP0);
5666         p->rx_ppp1              = GET_STAT(RX_PORT_PPP1);
5667         p->rx_ppp2              = GET_STAT(RX_PORT_PPP2);
5668         p->rx_ppp3              = GET_STAT(RX_PORT_PPP3);
5669         p->rx_ppp4              = GET_STAT(RX_PORT_PPP4);
5670         p->rx_ppp5              = GET_STAT(RX_PORT_PPP5);
5671         p->rx_ppp6              = GET_STAT(RX_PORT_PPP6);
5672         p->rx_ppp7              = GET_STAT(RX_PORT_PPP7);
5673
5674         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5675         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5676         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5677         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5678         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5679         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5680         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5681         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5682
5683 #undef GET_STAT
5684 #undef GET_STAT_COM
5685 }
5686
5687 /**
5688  *      t4_get_lb_stats - collect loopback port statistics
5689  *      @adap: the adapter
5690  *      @idx: the loopback port index
5691  *      @p: the stats structure to fill
5692  *
5693  *      Return HW statistics for the given loopback port.
5694  */
5695 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5696 {
5697         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5698
5699 #define GET_STAT(name) \
5700         t4_read_reg64(adap, \
5701         (is_t4(adap) ? \
5702         PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
5703         T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
5704 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5705
5706         p->octets       = GET_STAT(BYTES);
5707         p->frames       = GET_STAT(FRAMES);
5708         p->bcast_frames = GET_STAT(BCAST);
5709         p->mcast_frames = GET_STAT(MCAST);
5710         p->ucast_frames = GET_STAT(UCAST);
5711         p->error_frames = GET_STAT(ERROR);
5712
5713         p->frames_64            = GET_STAT(64B);
5714         p->frames_65_127        = GET_STAT(65B_127B);
5715         p->frames_128_255       = GET_STAT(128B_255B);
5716         p->frames_256_511       = GET_STAT(256B_511B);
5717         p->frames_512_1023      = GET_STAT(512B_1023B);
5718         p->frames_1024_1518     = GET_STAT(1024B_1518B);
5719         p->frames_1519_max      = GET_STAT(1519B_MAX);
5720         p->drop                 = GET_STAT(DROP_FRAMES);
5721
5722         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5723         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5724         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5725         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5726         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5727         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5728         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5729         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5730
5731 #undef GET_STAT
5732 #undef GET_STAT_COM
5733 }
5734
5735 /**
5736  *      t4_wol_magic_enable - enable/disable magic packet WoL
5737  *      @adap: the adapter
5738  *      @port: the physical port index
5739  *      @addr: MAC address expected in magic packets, %NULL to disable
5740  *
5741  *      Enables/disables magic packet wake-on-LAN for the selected port.
5742  */
5743 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
5744                          const u8 *addr)
5745 {
5746         u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
5747
5748         if (is_t4(adap)) {
5749                 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
5750                 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
5751                 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
5752         } else {
5753                 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
5754                 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
5755                 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
5756         }
5757
5758         if (addr) {
5759                 t4_write_reg(adap, mag_id_reg_l,
5760                              (addr[2] << 24) | (addr[3] << 16) |
5761                              (addr[4] << 8) | addr[5]);
5762                 t4_write_reg(adap, mag_id_reg_h,
5763                              (addr[0] << 8) | addr[1]);
5764         }
5765         t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
5766                          V_MAGICEN(addr != NULL));
5767 }
5768
5769 /**
5770  *      t4_wol_pat_enable - enable/disable pattern-based WoL
5771  *      @adap: the adapter
5772  *      @port: the physical port index
5773  *      @map: bitmap of which HW pattern filters to set
5774  *      @mask0: byte mask for bytes 0-63 of a packet
5775  *      @mask1: byte mask for bytes 64-127 of a packet
5776  *      @crc: Ethernet CRC for selected bytes
5777  *      @enable: enable/disable switch
5778  *
5779  *      Sets the pattern filters indicated in @map to mask out the bytes
5780  *      specified in @mask0/@mask1 in received packets and compare the CRC of
5781  *      the resulting packet against @crc.  If @enable is %true pattern-based
5782  *      WoL is enabled, otherwise disabled.
5783  */
5784 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
5785                       u64 mask0, u64 mask1, unsigned int crc, bool enable)
5786 {
5787         int i;
5788         u32 port_cfg_reg;
5789
5790         if (is_t4(adap))
5791                 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
5792         else
5793                 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
5794
5795         if (!enable) {
5796                 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
5797                 return 0;
5798         }
5799         if (map > 0xff)
5800                 return -EINVAL;
5801
5802 #define EPIO_REG(name) \
5803         (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
5804         T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
5805
5806         t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
5807         t4_write_reg(adap, EPIO_REG(DATA2), mask1);
5808         t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
5809
5810         for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
5811                 if (!(map & 1))
5812                         continue;
5813
5814                 /* write byte masks */
5815                 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
5816                 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
5817                 t4_read_reg(adap, EPIO_REG(OP));                /* flush */
5818                 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
5819                         return -ETIMEDOUT;
5820
5821                 /* write CRC */
5822                 t4_write_reg(adap, EPIO_REG(DATA0), crc);
5823                 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
5824                 t4_read_reg(adap, EPIO_REG(OP));                /* flush */
5825                 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
5826                         return -ETIMEDOUT;
5827         }
5828 #undef EPIO_REG
5829
5830         t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
5831         return 0;
5832 }
5833
5834 /*     t4_mk_filtdelwr - create a delete filter WR
5835  *     @ftid: the filter ID
5836  *     @wr: the filter work request to populate
5837  *     @qid: ingress queue to receive the delete notification
5838  *
5839  *     Creates a filter work request to delete the supplied filter.  If @qid is
5840  *     negative the delete notification is suppressed.
5841  */
5842 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5843 {
5844         memset(wr, 0, sizeof(*wr));
5845         wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
5846         wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
5847         wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
5848                                     V_FW_FILTER_WR_NOREPLY(qid < 0));
5849         wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
5850         if (qid >= 0)
5851                 wr->rx_chan_rx_rpl_iq =
5852                                 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
5853 }
5854
5855 #define INIT_CMD(var, cmd, rd_wr) do { \
5856         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
5857                                         F_FW_CMD_REQUEST | \
5858                                         F_FW_CMD_##rd_wr); \
5859         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5860 } while (0)
5861
5862 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5863                           u32 addr, u32 val)
5864 {
5865         u32 ldst_addrspace;
5866         struct fw_ldst_cmd c;
5867
5868         memset(&c, 0, sizeof(c));
5869         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
5870         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5871                                         F_FW_CMD_REQUEST |
5872                                         F_FW_CMD_WRITE |
5873                                         ldst_addrspace);
5874         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5875         c.u.addrval.addr = cpu_to_be32(addr);
5876         c.u.addrval.val = cpu_to_be32(val);
5877
5878         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5879 }
5880
5881 /**
5882  *      t4_mdio_rd - read a PHY register through MDIO
5883  *      @adap: the adapter
5884  *      @mbox: mailbox to use for the FW command
5885  *      @phy_addr: the PHY address
5886  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5887  *      @reg: the register to read
5888  *      @valp: where to store the value
5889  *
5890  *      Issues a FW command through the given mailbox to read a PHY register.
5891  */
5892 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5893                unsigned int mmd, unsigned int reg, unsigned int *valp)
5894 {
5895         int ret;
5896         u32 ldst_addrspace;
5897         struct fw_ldst_cmd c;
5898
5899         memset(&c, 0, sizeof(c));
5900         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
5901         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5902                                         F_FW_CMD_REQUEST | F_FW_CMD_READ |
5903                                         ldst_addrspace);
5904         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5905         c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
5906                                          V_FW_LDST_CMD_MMD(mmd));
5907         c.u.mdio.raddr = cpu_to_be16(reg);
5908
5909         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5910         if (ret == 0)
5911                 *valp = be16_to_cpu(c.u.mdio.rval);
5912         return ret;
5913 }
5914
5915 /**
5916  *      t4_mdio_wr - write a PHY register through MDIO
5917  *      @adap: the adapter
5918  *      @mbox: mailbox to use for the FW command
5919  *      @phy_addr: the PHY address
5920  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5921  *      @reg: the register to write
5922  *      @valp: value to write
5923  *
5924  *      Issues a FW command through the given mailbox to write a PHY register.
5925  */
5926 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5927                unsigned int mmd, unsigned int reg, unsigned int val)
5928 {
5929         u32 ldst_addrspace;
5930         struct fw_ldst_cmd c;
5931
5932         memset(&c, 0, sizeof(c));
5933         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
5934         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5935                                         F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5936                                         ldst_addrspace);
5937         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5938         c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
5939                                          V_FW_LDST_CMD_MMD(mmd));
5940         c.u.mdio.raddr = cpu_to_be16(reg);
5941         c.u.mdio.rval = cpu_to_be16(val);
5942
5943         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5944 }
5945
5946 /**
5947  *
5948  *      t4_sge_decode_idma_state - decode the idma state
5949  *      @adap: the adapter
5950  *      @state: the state idma is stuck in
5951  */
5952 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5953 {
5954         static const char * const t4_decode[] = {
5955                 "IDMA_IDLE",
5956                 "IDMA_PUSH_MORE_CPL_FIFO",
5957                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5958                 "Not used",
5959                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5960                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5961                 "IDMA_PHYSADDR_SEND_PAYLOAD",
5962                 "IDMA_SEND_FIFO_TO_IMSG",
5963                 "IDMA_FL_REQ_DATA_FL_PREP",
5964                 "IDMA_FL_REQ_DATA_FL",
5965                 "IDMA_FL_DROP",
5966                 "IDMA_FL_H_REQ_HEADER_FL",
5967                 "IDMA_FL_H_SEND_PCIEHDR",
5968                 "IDMA_FL_H_PUSH_CPL_FIFO",
5969                 "IDMA_FL_H_SEND_CPL",
5970                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5971                 "IDMA_FL_H_SEND_IP_HDR",
5972                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5973                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5974                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5975                 "IDMA_FL_D_SEND_PCIEHDR",
5976                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5977                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5978                 "IDMA_FL_SEND_PCIEHDR",
5979                 "IDMA_FL_PUSH_CPL_FIFO",
5980                 "IDMA_FL_SEND_CPL",
5981                 "IDMA_FL_SEND_PAYLOAD_FIRST",
5982                 "IDMA_FL_SEND_PAYLOAD",
5983                 "IDMA_FL_REQ_NEXT_DATA_FL",
5984                 "IDMA_FL_SEND_NEXT_PCIEHDR",
5985                 "IDMA_FL_SEND_PADDING",
5986                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5987                 "IDMA_FL_SEND_FIFO_TO_IMSG",
5988                 "IDMA_FL_REQ_DATAFL_DONE",
5989                 "IDMA_FL_REQ_HEADERFL_DONE",
5990         };
5991         static const char * const t5_decode[] = {
5992                 "IDMA_IDLE",
5993                 "IDMA_ALMOST_IDLE",
5994                 "IDMA_PUSH_MORE_CPL_FIFO",
5995                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5996                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5997                 "IDMA_PHYSADDR_SEND_PCIEHDR",
5998                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5999                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6000                 "IDMA_SEND_FIFO_TO_IMSG",
6001                 "IDMA_FL_REQ_DATA_FL",
6002                 "IDMA_FL_DROP",
6003                 "IDMA_FL_DROP_SEND_INC",
6004                 "IDMA_FL_H_REQ_HEADER_FL",
6005                 "IDMA_FL_H_SEND_PCIEHDR",
6006                 "IDMA_FL_H_PUSH_CPL_FIFO",
6007                 "IDMA_FL_H_SEND_CPL",
6008                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6009                 "IDMA_FL_H_SEND_IP_HDR",
6010                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6011                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6012                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6013                 "IDMA_FL_D_SEND_PCIEHDR",
6014                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6015                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6016                 "IDMA_FL_SEND_PCIEHDR",
6017                 "IDMA_FL_PUSH_CPL_FIFO",
6018                 "IDMA_FL_SEND_CPL",
6019                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6020                 "IDMA_FL_SEND_PAYLOAD",
6021                 "IDMA_FL_REQ_NEXT_DATA_FL",
6022                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6023                 "IDMA_FL_SEND_PADDING",
6024                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6025         };
6026         static const char * const t6_decode[] = {
6027                 "IDMA_IDLE",
6028                 "IDMA_PUSH_MORE_CPL_FIFO",
6029                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6030                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6031                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6032                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6033                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6034                 "IDMA_FL_REQ_DATA_FL",
6035                 "IDMA_FL_DROP",
6036                 "IDMA_FL_DROP_SEND_INC",
6037                 "IDMA_FL_H_REQ_HEADER_FL",
6038                 "IDMA_FL_H_SEND_PCIEHDR",
6039                 "IDMA_FL_H_PUSH_CPL_FIFO",
6040                 "IDMA_FL_H_SEND_CPL",
6041                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6042                 "IDMA_FL_H_SEND_IP_HDR",
6043                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6044                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6045                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6046                 "IDMA_FL_D_SEND_PCIEHDR",
6047                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6048                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6049                 "IDMA_FL_SEND_PCIEHDR",
6050                 "IDMA_FL_PUSH_CPL_FIFO",
6051                 "IDMA_FL_SEND_CPL",
6052                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6053                 "IDMA_FL_SEND_PAYLOAD",
6054                 "IDMA_FL_REQ_NEXT_DATA_FL",
6055                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6056                 "IDMA_FL_SEND_PADDING",
6057                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6058         };
6059         static const u32 sge_regs[] = {
6060                 A_SGE_DEBUG_DATA_LOW_INDEX_2,
6061                 A_SGE_DEBUG_DATA_LOW_INDEX_3,
6062                 A_SGE_DEBUG_DATA_HIGH_INDEX_10,
6063         };
6064         const char * const *sge_idma_decode;
6065         int sge_idma_decode_nstates;
6066         int i;
6067         unsigned int chip_version = chip_id(adapter);
6068
6069         /* Select the right set of decode strings to dump depending on the
6070          * adapter chip type.
6071          */
6072         switch (chip_version) {
6073         case CHELSIO_T4:
6074                 sge_idma_decode = (const char * const *)t4_decode;
6075                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6076                 break;
6077
6078         case CHELSIO_T5:
6079                 sge_idma_decode = (const char * const *)t5_decode;
6080                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6081                 break;
6082
6083         case CHELSIO_T6:
6084                 sge_idma_decode = (const char * const *)t6_decode;
6085                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6086                 break;
6087
6088         default:
6089                 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version);
6090                 return;
6091         }
6092
6093         if (state < sge_idma_decode_nstates)
6094                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6095         else
6096                 CH_WARN(adapter, "idma state %d unknown\n", state);
6097
6098         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6099                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6100                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6101 }
6102
6103 /**
6104  *      t4_sge_ctxt_flush - flush the SGE context cache
6105  *      @adap: the adapter
6106  *      @mbox: mailbox to use for the FW command
6107  *
6108  *      Issues a FW command through the given mailbox to flush the
6109  *      SGE context cache.
6110  */
6111 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6112 {
6113         int ret;
6114         u32 ldst_addrspace;
6115         struct fw_ldst_cmd c;
6116
6117         memset(&c, 0, sizeof(c));
6118         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
6119         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6120                                         F_FW_CMD_REQUEST | F_FW_CMD_READ |
6121                                         ldst_addrspace);
6122         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6123         c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
6124
6125         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6126         return ret;
6127 }
6128
6129 /**
6130  *      t4_fw_hello - establish communication with FW
6131  *      @adap: the adapter
6132  *      @mbox: mailbox to use for the FW command
6133  *      @evt_mbox: mailbox to receive async FW events
6134  *      @master: specifies the caller's willingness to be the device master
6135  *      @state: returns the current device state (if non-NULL)
6136  *
6137  *      Issues a command to establish communication with FW.  Returns either
6138  *      an error (negative integer) or the mailbox of the Master PF.
6139  */
6140 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6141                 enum dev_master master, enum dev_state *state)
6142 {
6143         int ret;
6144         struct fw_hello_cmd c;
6145         u32 v;
6146         unsigned int master_mbox;
6147         int retries = FW_CMD_HELLO_RETRIES;
6148
6149 retry:
6150         memset(&c, 0, sizeof(c));
6151         INIT_CMD(c, HELLO, WRITE);
6152         c.err_to_clearinit = cpu_to_be32(
6153                 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
6154                 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
6155                 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
6156                                         mbox : M_FW_HELLO_CMD_MBMASTER) |
6157                 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
6158                 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
6159                 F_FW_HELLO_CMD_CLEARINIT);
6160
6161         /*
6162          * Issue the HELLO command to the firmware.  If it's not successful
6163          * but indicates that we got a "busy" or "timeout" condition, retry
6164          * the HELLO until we exhaust our retry limit.  If we do exceed our
6165          * retry limit, check to see if the firmware left us any error
6166          * information and report that if so ...
6167          */
6168         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6169         if (ret != FW_SUCCESS) {
6170                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6171                         goto retry;
6172                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
6173                         t4_report_fw_error(adap);
6174                 return ret;
6175         }
6176
6177         v = be32_to_cpu(c.err_to_clearinit);
6178         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
6179         if (state) {
6180                 if (v & F_FW_HELLO_CMD_ERR)
6181                         *state = DEV_STATE_ERR;
6182                 else if (v & F_FW_HELLO_CMD_INIT)
6183                         *state = DEV_STATE_INIT;
6184                 else
6185                         *state = DEV_STATE_UNINIT;
6186         }
6187
6188         /*
6189          * If we're not the Master PF then we need to wait around for the
6190          * Master PF Driver to finish setting up the adapter.
6191          *
6192          * Note that we also do this wait if we're a non-Master-capable PF and
6193          * there is no current Master PF; a Master PF may show up momentarily
6194          * and we wouldn't want to fail pointlessly.  (This can happen when an
6195          * OS loads lots of different drivers rapidly at the same time).  In
6196          * this case, the Master PF returned by the firmware will be
6197          * M_PCIE_FW_MASTER so the test below will work ...
6198          */
6199         if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
6200             master_mbox != mbox) {
6201                 int waiting = FW_CMD_HELLO_TIMEOUT;
6202
6203                 /*
6204                  * Wait for the firmware to either indicate an error or
6205                  * initialized state.  If we see either of these we bail out
6206                  * and report the issue to the caller.  If we exhaust the
6207                  * "hello timeout" and we haven't exhausted our retries, try
6208                  * again.  Otherwise bail with a timeout error.
6209                  */
6210                 for (;;) {
6211                         u32 pcie_fw;
6212
6213                         msleep(50);
6214                         waiting -= 50;
6215
6216                         /*
6217                          * If neither Error nor Initialialized are indicated
6218                          * by the firmware keep waiting till we exhaust our
6219                          * timeout ... and then retry if we haven't exhausted
6220                          * our retries ...
6221                          */
6222                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
6223                         if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
6224                                 if (waiting <= 0) {
6225                                         if (retries-- > 0)
6226                                                 goto retry;
6227
6228                                         return -ETIMEDOUT;
6229                                 }
6230                                 continue;
6231                         }
6232
6233                         /*
6234                          * We either have an Error or Initialized condition
6235                          * report errors preferentially.
6236                          */
6237                         if (state) {
6238                                 if (pcie_fw & F_PCIE_FW_ERR)
6239                                         *state = DEV_STATE_ERR;
6240                                 else if (pcie_fw & F_PCIE_FW_INIT)
6241                                         *state = DEV_STATE_INIT;
6242                         }
6243
6244                         /*
6245                          * If we arrived before a Master PF was selected and
6246                          * there's not a valid Master PF, grab its identity
6247                          * for our caller.
6248                          */
6249                         if (master_mbox == M_PCIE_FW_MASTER &&
6250                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
6251                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
6252                         break;
6253                 }
6254         }
6255
6256         return master_mbox;
6257 }
6258
6259 /**
6260  *      t4_fw_bye - end communication with FW
6261  *      @adap: the adapter
6262  *      @mbox: mailbox to use for the FW command
6263  *
6264  *      Issues a command to terminate communication with FW.
6265  */
6266 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6267 {
6268         struct fw_bye_cmd c;
6269
6270         memset(&c, 0, sizeof(c));
6271         INIT_CMD(c, BYE, WRITE);
6272         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6273 }
6274
6275 /**
6276  *      t4_fw_reset - issue a reset to FW
6277  *      @adap: the adapter
6278  *      @mbox: mailbox to use for the FW command
6279  *      @reset: specifies the type of reset to perform
6280  *
6281  *      Issues a reset command of the specified type to FW.
6282  */
6283 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6284 {
6285         struct fw_reset_cmd c;
6286
6287         memset(&c, 0, sizeof(c));
6288         INIT_CMD(c, RESET, WRITE);
6289         c.val = cpu_to_be32(reset);
6290         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6291 }
6292
6293 /**
6294  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6295  *      @adap: the adapter
6296  *      @mbox: mailbox to use for the FW RESET command (if desired)
6297  *      @force: force uP into RESET even if FW RESET command fails
6298  *
6299  *      Issues a RESET command to firmware (if desired) with a HALT indication
6300  *      and then puts the microprocessor into RESET state.  The RESET command
6301  *      will only be issued if a legitimate mailbox is provided (mbox <=
6302  *      M_PCIE_FW_MASTER).
6303  *
6304  *      This is generally used in order for the host to safely manipulate the
6305  *      adapter without fear of conflicting with whatever the firmware might
6306  *      be doing.  The only way out of this state is to RESTART the firmware
6307  *      ...
6308  */
6309 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6310 {
6311         int ret = 0;
6312
6313         /*
6314          * If a legitimate mailbox is provided, issue a RESET command
6315          * with a HALT indication.
6316          */
6317         if (mbox <= M_PCIE_FW_MASTER) {
6318                 struct fw_reset_cmd c;
6319
6320                 memset(&c, 0, sizeof(c));
6321                 INIT_CMD(c, RESET, WRITE);
6322                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
6323                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
6324                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6325         }
6326
6327         /*
6328          * Normally we won't complete the operation if the firmware RESET
6329          * command fails but if our caller insists we'll go ahead and put the
6330          * uP into RESET.  This can be useful if the firmware is hung or even
6331          * missing ...  We'll have to take the risk of putting the uP into
6332          * RESET without the cooperation of firmware in that case.
6333          *
6334          * We also force the firmware's HALT flag to be on in case we bypassed
6335          * the firmware RESET command above or we're dealing with old firmware
6336          * which doesn't have the HALT capability.  This will serve as a flag
6337          * for the incoming firmware to know that it's coming out of a HALT
6338          * rather than a RESET ... if it's new enough to understand that ...
6339          */
6340         if (ret == 0 || force) {
6341                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
6342                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
6343                                  F_PCIE_FW_HALT);
6344         }
6345
6346         /*
6347          * And we always return the result of the firmware RESET command
6348          * even when we force the uP into RESET ...
6349          */
6350         return ret;
6351 }
6352
6353 /**
6354  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6355  *      @adap: the adapter
6356  *      @reset: if we want to do a RESET to restart things
6357  *
6358  *      Restart firmware previously halted by t4_fw_halt().  On successful
6359  *      return the previous PF Master remains as the new PF Master and there
6360  *      is no need to issue a new HELLO command, etc.
6361  *
6362  *      We do this in two ways:
6363  *
6364  *       1. If we're dealing with newer firmware we'll simply want to take
6365  *          the chip's microprocessor out of RESET.  This will cause the
6366  *          firmware to start up from its start vector.  And then we'll loop
6367  *          until the firmware indicates it's started again (PCIE_FW.HALT
6368  *          reset to 0) or we timeout.
6369  *
6370  *       2. If we're dealing with older firmware then we'll need to RESET
6371  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6372  *          flag and automatically RESET itself on startup.
6373  */
6374 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6375 {
6376         if (reset) {
6377                 /*
6378                  * Since we're directing the RESET instead of the firmware
6379                  * doing it automatically, we need to clear the PCIE_FW.HALT
6380                  * bit.
6381                  */
6382                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
6383
6384                 /*
6385                  * If we've been given a valid mailbox, first try to get the
6386                  * firmware to do the RESET.  If that works, great and we can
6387                  * return success.  Otherwise, if we haven't been given a
6388                  * valid mailbox or the RESET command failed, fall back to
6389                  * hitting the chip with a hammer.
6390                  */
6391                 if (mbox <= M_PCIE_FW_MASTER) {
6392                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6393                         msleep(100);
6394                         if (t4_fw_reset(adap, mbox,
6395                                         F_PIORST | F_PIORSTMODE) == 0)
6396                                 return 0;
6397                 }
6398
6399                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
6400                 msleep(2000);
6401         } else {
6402                 int ms;
6403
6404                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6405                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6406                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
6407                                 return FW_SUCCESS;
6408                         msleep(100);
6409                         ms += 100;
6410                 }
6411                 return -ETIMEDOUT;
6412         }
6413         return 0;
6414 }
6415
6416 /**
6417  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6418  *      @adap: the adapter
6419  *      @mbox: mailbox to use for the FW RESET command (if desired)
6420  *      @fw_data: the firmware image to write
6421  *      @size: image size
6422  *      @force: force upgrade even if firmware doesn't cooperate
6423  *
6424  *      Perform all of the steps necessary for upgrading an adapter's
6425  *      firmware image.  Normally this requires the cooperation of the
6426  *      existing firmware in order to halt all existing activities
6427  *      but if an invalid mailbox token is passed in we skip that step
6428  *      (though we'll still put the adapter microprocessor into RESET in
6429  *      that case).
6430  *
6431  *      On successful return the new firmware will have been loaded and
6432  *      the adapter will have been fully RESET losing all previous setup
6433  *      state.  On unsuccessful return the adapter may be completely hosed ...
6434  *      positive errno indicates that the adapter is ~probably~ intact, a
6435  *      negative errno indicates that things are looking bad ...
6436  */
6437 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6438                   const u8 *fw_data, unsigned int size, int force)
6439 {
6440         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6441         unsigned int bootstrap =
6442             be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
6443         int reset, ret;
6444
6445         if (!t4_fw_matches_chip(adap, fw_hdr))
6446                 return -EINVAL;
6447
6448         if (!bootstrap) {
6449                 ret = t4_fw_halt(adap, mbox, force);
6450                 if (ret < 0 && !force)
6451                         return ret;
6452         }
6453
6454         ret = t4_load_fw(adap, fw_data, size);
6455         if (ret < 0 || bootstrap)
6456                 return ret;
6457
6458         /*
6459          * Older versions of the firmware don't understand the new
6460          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6461          * restart.  So for newly loaded older firmware we'll have to do the
6462          * RESET for it so it starts up on a clean slate.  We can tell if
6463          * the newly loaded firmware will handle this right by checking
6464          * its header flags to see if it advertises the capability.
6465          */
6466         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6467         return t4_fw_restart(adap, mbox, reset);
6468 }
6469
6470 /**
6471  *      t4_fw_initialize - ask FW to initialize the device
6472  *      @adap: the adapter
6473  *      @mbox: mailbox to use for the FW command
6474  *
6475  *      Issues a command to FW to partially initialize the device.  This
6476  *      performs initialization that generally doesn't depend on user input.
6477  */
6478 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6479 {
6480         struct fw_initialize_cmd c;
6481
6482         memset(&c, 0, sizeof(c));
6483         INIT_CMD(c, INITIALIZE, WRITE);
6484         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6485 }
6486
6487 /**
6488  *      t4_query_params_rw - query FW or device parameters
6489  *      @adap: the adapter
6490  *      @mbox: mailbox to use for the FW command
6491  *      @pf: the PF
6492  *      @vf: the VF
6493  *      @nparams: the number of parameters
6494  *      @params: the parameter names
6495  *      @val: the parameter values
6496  *      @rw: Write and read flag
6497  *
6498  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
6499  *      queried at once.
6500  */
6501 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6502                        unsigned int vf, unsigned int nparams, const u32 *params,
6503                        u32 *val, int rw)
6504 {
6505         int i, ret;
6506         struct fw_params_cmd c;
6507         __be32 *p = &c.param[0].mnem;
6508
6509         if (nparams > 7)
6510                 return -EINVAL;
6511
6512         memset(&c, 0, sizeof(c));
6513         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6514                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
6515                                   V_FW_PARAMS_CMD_PFN(pf) |
6516                                   V_FW_PARAMS_CMD_VFN(vf));
6517         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6518
6519         for (i = 0; i < nparams; i++) {
6520                 *p++ = cpu_to_be32(*params++);
6521                 if (rw)
6522                         *p = cpu_to_be32(*(val + i));
6523                 p++;
6524         }
6525
6526         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6527         if (ret == 0)
6528                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6529                         *val++ = be32_to_cpu(*p);
6530         return ret;
6531 }
6532
6533 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6534                     unsigned int vf, unsigned int nparams, const u32 *params,
6535                     u32 *val)
6536 {
6537         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6538 }
6539
6540 /**
6541  *      t4_set_params_timeout - sets FW or device parameters
6542  *      @adap: the adapter
6543  *      @mbox: mailbox to use for the FW command
6544  *      @pf: the PF
6545  *      @vf: the VF
6546  *      @nparams: the number of parameters
6547  *      @params: the parameter names
6548  *      @val: the parameter values
6549  *      @timeout: the timeout time
6550  *
6551  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6552  *      specified at once.
6553  */
6554 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6555                           unsigned int pf, unsigned int vf,
6556                           unsigned int nparams, const u32 *params,
6557                           const u32 *val, int timeout)
6558 {
6559         struct fw_params_cmd c;
6560         __be32 *p = &c.param[0].mnem;
6561
6562         if (nparams > 7)
6563                 return -EINVAL;
6564
6565         memset(&c, 0, sizeof(c));
6566         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6567                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6568                                   V_FW_PARAMS_CMD_PFN(pf) |
6569                                   V_FW_PARAMS_CMD_VFN(vf));
6570         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6571
6572         while (nparams--) {
6573                 *p++ = cpu_to_be32(*params++);
6574                 *p++ = cpu_to_be32(*val++);
6575         }
6576
6577         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6578 }
6579
6580 /**
6581  *      t4_set_params - sets FW or device parameters
6582  *      @adap: the adapter
6583  *      @mbox: mailbox to use for the FW command
6584  *      @pf: the PF
6585  *      @vf: the VF
6586  *      @nparams: the number of parameters
6587  *      @params: the parameter names
6588  *      @val: the parameter values
6589  *
6590  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6591  *      specified at once.
6592  */
6593 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6594                   unsigned int vf, unsigned int nparams, const u32 *params,
6595                   const u32 *val)
6596 {
6597         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6598                                      FW_CMD_MAX_TIMEOUT);
6599 }
6600
6601 /**
6602  *      t4_cfg_pfvf - configure PF/VF resource limits
6603  *      @adap: the adapter
6604  *      @mbox: mailbox to use for the FW command
6605  *      @pf: the PF being configured
6606  *      @vf: the VF being configured
6607  *      @txq: the max number of egress queues
6608  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
6609  *      @rxqi: the max number of interrupt-capable ingress queues
6610  *      @rxq: the max number of interruptless ingress queues
6611  *      @tc: the PCI traffic class
6612  *      @vi: the max number of virtual interfaces
6613  *      @cmask: the channel access rights mask for the PF/VF
6614  *      @pmask: the port access rights mask for the PF/VF
6615  *      @nexact: the maximum number of exact MPS filters
6616  *      @rcaps: read capabilities
6617  *      @wxcaps: write/execute capabilities
6618  *
6619  *      Configures resource limits and capabilities for a physical or virtual
6620  *      function.
6621  */
6622 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6623                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6624                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6625                 unsigned int vi, unsigned int cmask, unsigned int pmask,
6626                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6627 {
6628         struct fw_pfvf_cmd c;
6629
6630         memset(&c, 0, sizeof(c));
6631         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
6632                                   F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
6633                                   V_FW_PFVF_CMD_VFN(vf));
6634         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6635         c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
6636                                      V_FW_PFVF_CMD_NIQ(rxq));
6637         c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
6638                                     V_FW_PFVF_CMD_PMASK(pmask) |
6639                                     V_FW_PFVF_CMD_NEQ(txq));
6640         c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
6641                                       V_FW_PFVF_CMD_NVI(vi) |
6642                                       V_FW_PFVF_CMD_NEXACTF(nexact));
6643         c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
6644                                      V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
6645                                      V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
6646         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6647 }
6648
6649 /**
6650  *      t4_alloc_vi_func - allocate a virtual interface
6651  *      @adap: the adapter
6652  *      @mbox: mailbox to use for the FW command
6653  *      @port: physical port associated with the VI
6654  *      @pf: the PF owning the VI
6655  *      @vf: the VF owning the VI
6656  *      @nmac: number of MAC addresses needed (1 to 5)
6657  *      @mac: the MAC addresses of the VI
6658  *      @rss_size: size of RSS table slice associated with this VI
6659  *      @portfunc: which Port Application Function MAC Address is desired
6660  *      @idstype: Intrusion Detection Type
6661  *
6662  *      Allocates a virtual interface for the given physical port.  If @mac is
6663  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
6664  *      If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
6665  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
6666  *      stored consecutively so the space needed is @nmac * 6 bytes.
6667  *      Returns a negative error number or the non-negative VI id.
6668  */
6669 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
6670                      unsigned int port, unsigned int pf, unsigned int vf,
6671                      unsigned int nmac, u8 *mac, u16 *rss_size,
6672                      unsigned int portfunc, unsigned int idstype)
6673 {
6674         int ret;
6675         struct fw_vi_cmd c;
6676
6677         memset(&c, 0, sizeof(c));
6678         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
6679                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
6680                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
6681         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
6682         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
6683                                      V_FW_VI_CMD_FUNC(portfunc));
6684         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
6685         c.nmac = nmac - 1;
6686         if(!rss_size)
6687                 c.norss_rsssize = F_FW_VI_CMD_NORSS;
6688
6689         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6690         if (ret)
6691                 return ret;
6692
6693         if (mac) {
6694                 memcpy(mac, c.mac, sizeof(c.mac));
6695                 switch (nmac) {
6696                 case 5:
6697                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6698                 case 4:
6699                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6700                 case 3:
6701                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6702                 case 2:
6703                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
6704                 }
6705         }
6706         if (rss_size)
6707                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
6708         return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
6709 }
6710
6711 /**
6712  *      t4_alloc_vi - allocate an [Ethernet Function] virtual interface
6713  *      @adap: the adapter
6714  *      @mbox: mailbox to use for the FW command
6715  *      @port: physical port associated with the VI
6716  *      @pf: the PF owning the VI
6717  *      @vf: the VF owning the VI
6718  *      @nmac: number of MAC addresses needed (1 to 5)
6719  *      @mac: the MAC addresses of the VI
6720  *      @rss_size: size of RSS table slice associated with this VI
6721  *
6722  *      backwards compatible and convieniance routine to allocate a Virtual
6723  *      Interface with a Ethernet Port Application Function and Intrustion
6724  *      Detection System disabled.
6725  */
6726 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6727                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6728                 u16 *rss_size)
6729 {
6730         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
6731                                 FW_VI_FUNC_ETH, 0);
6732 }
6733
6734 /**
6735  *      t4_free_vi - free a virtual interface
6736  *      @adap: the adapter
6737  *      @mbox: mailbox to use for the FW command
6738  *      @pf: the PF owning the VI
6739  *      @vf: the VF owning the VI
6740  *      @viid: virtual interface identifiler
6741  *
6742  *      Free a previously allocated virtual interface.
6743  */
6744 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6745                unsigned int vf, unsigned int viid)
6746 {
6747         struct fw_vi_cmd c;
6748
6749         memset(&c, 0, sizeof(c));
6750         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
6751                                   F_FW_CMD_REQUEST |
6752                                   F_FW_CMD_EXEC |
6753                                   V_FW_VI_CMD_PFN(pf) |
6754                                   V_FW_VI_CMD_VFN(vf));
6755         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
6756         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
6757
6758         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6759 }
6760
6761 /**
6762  *      t4_set_rxmode - set Rx properties of a virtual interface
6763  *      @adap: the adapter
6764  *      @mbox: mailbox to use for the FW command
6765  *      @viid: the VI id
6766  *      @mtu: the new MTU or -1
6767  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6768  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6769  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6770  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6771  *      @sleep_ok: if true we may sleep while awaiting command completion
6772  *
6773  *      Sets Rx properties of a virtual interface.
6774  */
6775 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6776                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
6777                   bool sleep_ok)
6778 {
6779         struct fw_vi_rxmode_cmd c;
6780
6781         /* convert to FW values */
6782         if (mtu < 0)
6783                 mtu = M_FW_VI_RXMODE_CMD_MTU;
6784         if (promisc < 0)
6785                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
6786         if (all_multi < 0)
6787                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
6788         if (bcast < 0)
6789                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
6790         if (vlanex < 0)
6791                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
6792
6793         memset(&c, 0, sizeof(c));
6794         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
6795                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6796                                    V_FW_VI_RXMODE_CMD_VIID(viid));
6797         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6798         c.mtu_to_vlanexen =
6799                 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
6800                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
6801                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
6802                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
6803                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
6804         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6805 }
6806
6807 /**
6808  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6809  *      @adap: the adapter
6810  *      @mbox: mailbox to use for the FW command
6811  *      @viid: the VI id
6812  *      @free: if true any existing filters for this VI id are first removed
6813  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
6814  *      @addr: the MAC address(es)
6815  *      @idx: where to store the index of each allocated filter
6816  *      @hash: pointer to hash address filter bitmap
6817  *      @sleep_ok: call is allowed to sleep
6818  *
6819  *      Allocates an exact-match filter for each of the supplied addresses and
6820  *      sets it to the corresponding address.  If @idx is not %NULL it should
6821  *      have at least @naddr entries, each of which will be set to the index of
6822  *      the filter allocated for the corresponding MAC address.  If a filter
6823  *      could not be allocated for an address its index is set to 0xffff.
6824  *      If @hash is not %NULL addresses that fail to allocate an exact filter
6825  *      are hashed and update the hash filter bitmap pointed at by @hash.
6826  *
6827  *      Returns a negative error number or the number of filters allocated.
6828  */
6829 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6830                       unsigned int viid, bool free, unsigned int naddr,
6831                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6832 {
6833         int offset, ret = 0;
6834         struct fw_vi_mac_cmd c;
6835         unsigned int nfilters = 0;
6836         unsigned int max_naddr = adap->chip_params->mps_tcam_size;
6837         unsigned int rem = naddr;
6838
6839         if (naddr > max_naddr)
6840                 return -EINVAL;
6841
6842         for (offset = 0; offset < naddr ; /**/) {
6843                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6844                                          ? rem
6845                                          : ARRAY_SIZE(c.u.exact));
6846                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6847                                                      u.exact[fw_naddr]), 16);
6848                 struct fw_vi_mac_exact *p;
6849                 int i;
6850
6851                 memset(&c, 0, sizeof(c));
6852                 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
6853                                            F_FW_CMD_REQUEST |
6854                                            F_FW_CMD_WRITE |
6855                                            V_FW_CMD_EXEC(free) |
6856                                            V_FW_VI_MAC_CMD_VIID(viid));
6857                 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
6858                                                   V_FW_CMD_LEN16(len16));
6859
6860                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6861                         p->valid_to_idx =
6862                                 cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
6863                                             V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
6864                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6865                 }
6866
6867                 /*
6868                  * It's okay if we run out of space in our MAC address arena.
6869                  * Some of the addresses we submit may get stored so we need
6870                  * to run through the reply to see what the results were ...
6871                  */
6872                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6873                 if (ret && ret != -FW_ENOMEM)
6874                         break;
6875
6876                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6877                         u16 index = G_FW_VI_MAC_CMD_IDX(
6878                                                 be16_to_cpu(p->valid_to_idx));
6879
6880                         if (idx)
6881                                 idx[offset+i] = (index >=  max_naddr
6882                                                  ? 0xffff
6883                                                  : index);
6884                         if (index < max_naddr)
6885                                 nfilters++;
6886                         else if (hash)
6887                                 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
6888                 }
6889
6890                 free = false;
6891                 offset += fw_naddr;
6892                 rem -= fw_naddr;
6893         }
6894
6895         if (ret == 0 || ret == -FW_ENOMEM)
6896                 ret = nfilters;
6897         return ret;
6898 }
6899
6900 /**
6901  *      t4_change_mac - modifies the exact-match filter for a MAC address
6902  *      @adap: the adapter
6903  *      @mbox: mailbox to use for the FW command
6904  *      @viid: the VI id
6905  *      @idx: index of existing filter for old value of MAC address, or -1
6906  *      @addr: the new MAC address value
6907  *      @persist: whether a new MAC allocation should be persistent
6908  *      @add_smt: if true also add the address to the HW SMT
6909  *
6910  *      Modifies an exact-match filter and sets it to the new MAC address if
6911  *      @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
6912  *      latter case the address is added persistently if @persist is %true.
6913  *
6914  *      Note that in general it is not possible to modify the value of a given
6915  *      filter so the generic way to modify an address filter is to free the one
6916  *      being used by the old address value and allocate a new filter for the
6917  *      new address value.
6918  *
6919  *      Returns a negative error number or the index of the filter with the new
6920  *      MAC value.  Note that this index may differ from @idx.
6921  */
6922 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6923                   int idx, const u8 *addr, bool persist, bool add_smt)
6924 {
6925         int ret, mode;
6926         struct fw_vi_mac_cmd c;
6927         struct fw_vi_mac_exact *p = c.u.exact;
6928         unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
6929
6930         if (idx < 0)            /* new allocation */
6931                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6932         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6933
6934         memset(&c, 0, sizeof(c));
6935         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
6936                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6937                                    V_FW_VI_MAC_CMD_VIID(viid));
6938         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
6939         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
6940                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
6941                                       V_FW_VI_MAC_CMD_IDX(idx));
6942         memcpy(p->macaddr, addr, sizeof(p->macaddr));
6943
6944         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6945         if (ret == 0) {
6946                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
6947                 if (ret >= max_mac_addr)
6948                         ret = -ENOMEM;
6949         }
6950         return ret;
6951 }
6952
6953 /**
6954  *      t4_set_addr_hash - program the MAC inexact-match hash filter
6955  *      @adap: the adapter
6956  *      @mbox: mailbox to use for the FW command
6957  *      @viid: the VI id
6958  *      @ucast: whether the hash filter should also match unicast addresses
6959  *      @vec: the value to be written to the hash filter
6960  *      @sleep_ok: call is allowed to sleep
6961  *
6962  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
6963  */
6964 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6965                      bool ucast, u64 vec, bool sleep_ok)
6966 {
6967         struct fw_vi_mac_cmd c;
6968         u32 val;
6969
6970         memset(&c, 0, sizeof(c));
6971         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
6972                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6973                                    V_FW_VI_ENABLE_CMD_VIID(viid));
6974         val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
6975               V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
6976         c.freemacs_to_len16 = cpu_to_be32(val);
6977         c.u.hash.hashvec = cpu_to_be64(vec);
6978         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6979 }
6980
6981 /**
6982  *      t4_enable_vi_params - enable/disable a virtual interface
6983  *      @adap: the adapter
6984  *      @mbox: mailbox to use for the FW command
6985  *      @viid: the VI id
6986  *      @rx_en: 1=enable Rx, 0=disable Rx
6987  *      @tx_en: 1=enable Tx, 0=disable Tx
6988  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
6989  *
6990  *      Enables/disables a virtual interface.  Note that setting DCB Enable
6991  *      only makes sense when enabling a Virtual Interface ...
6992  */
6993 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6994                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6995 {
6996         struct fw_vi_enable_cmd c;
6997
6998         memset(&c, 0, sizeof(c));
6999         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7000                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7001                                    V_FW_VI_ENABLE_CMD_VIID(viid));
7002         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
7003                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
7004                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
7005                                      FW_LEN16(c));
7006         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7007 }
7008
7009 /**
7010  *      t4_enable_vi - enable/disable a virtual interface
7011  *      @adap: the adapter
7012  *      @mbox: mailbox to use for the FW command
7013  *      @viid: the VI id
7014  *      @rx_en: 1=enable Rx, 0=disable Rx
7015  *      @tx_en: 1=enable Tx, 0=disable Tx
7016  *
7017  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7018  *      only makes sense when enabling a Virtual Interface ...
7019  */
7020 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7021                  bool rx_en, bool tx_en)
7022 {
7023         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7024 }
7025
7026 /**
7027  *      t4_identify_port - identify a VI's port by blinking its LED
7028  *      @adap: the adapter
7029  *      @mbox: mailbox to use for the FW command
7030  *      @viid: the VI id
7031  *      @nblinks: how many times to blink LED at 2.5 Hz
7032  *
7033  *      Identifies a VI's port by blinking its LED.
7034  */
7035 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7036                      unsigned int nblinks)
7037 {
7038         struct fw_vi_enable_cmd c;
7039
7040         memset(&c, 0, sizeof(c));
7041         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7042                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7043                                    V_FW_VI_ENABLE_CMD_VIID(viid));
7044         c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
7045         c.blinkdur = cpu_to_be16(nblinks);
7046         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7047 }
7048
7049 /**
7050  *      t4_iq_stop - stop an ingress queue and its FLs
7051  *      @adap: the adapter
7052  *      @mbox: mailbox to use for the FW command
7053  *      @pf: the PF owning the queues
7054  *      @vf: the VF owning the queues
7055  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7056  *      @iqid: ingress queue id
7057  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7058  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7059  *
7060  *      Stops an ingress queue and its associated FLs, if any.  This causes
7061  *      any current or future data/messages destined for these queues to be
7062  *      tossed.
7063  */
7064 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7065                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7066                unsigned int fl0id, unsigned int fl1id)
7067 {
7068         struct fw_iq_cmd c;
7069
7070         memset(&c, 0, sizeof(c));
7071         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7072                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7073                                   V_FW_IQ_CMD_VFN(vf));
7074         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
7075         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7076         c.iqid = cpu_to_be16(iqid);
7077         c.fl0id = cpu_to_be16(fl0id);
7078         c.fl1id = cpu_to_be16(fl1id);
7079         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7080 }
7081
7082 /**
7083  *      t4_iq_free - free an ingress queue and its FLs
7084  *      @adap: the adapter
7085  *      @mbox: mailbox to use for the FW command
7086  *      @pf: the PF owning the queues
7087  *      @vf: the VF owning the queues
7088  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7089  *      @iqid: ingress queue id
7090  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7091  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7092  *
7093  *      Frees an ingress queue and its associated FLs, if any.
7094  */
7095 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7096                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7097                unsigned int fl0id, unsigned int fl1id)
7098 {
7099         struct fw_iq_cmd c;
7100
7101         memset(&c, 0, sizeof(c));
7102         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7103                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7104                                   V_FW_IQ_CMD_VFN(vf));
7105         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
7106         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7107         c.iqid = cpu_to_be16(iqid);
7108         c.fl0id = cpu_to_be16(fl0id);
7109         c.fl1id = cpu_to_be16(fl1id);
7110         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7111 }
7112
7113 /**
7114  *      t4_eth_eq_free - free an Ethernet egress queue
7115  *      @adap: the adapter
7116  *      @mbox: mailbox to use for the FW command
7117  *      @pf: the PF owning the queue
7118  *      @vf: the VF owning the queue
7119  *      @eqid: egress queue id
7120  *
7121  *      Frees an Ethernet egress queue.
7122  */
7123 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7124                    unsigned int vf, unsigned int eqid)
7125 {
7126         struct fw_eq_eth_cmd c;
7127
7128         memset(&c, 0, sizeof(c));
7129         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
7130                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7131                                   V_FW_EQ_ETH_CMD_PFN(pf) |
7132                                   V_FW_EQ_ETH_CMD_VFN(vf));
7133         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
7134         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
7135         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7136 }
7137
7138 /**
7139  *      t4_ctrl_eq_free - free a control egress queue
7140  *      @adap: the adapter
7141  *      @mbox: mailbox to use for the FW command
7142  *      @pf: the PF owning the queue
7143  *      @vf: the VF owning the queue
7144  *      @eqid: egress queue id
7145  *
7146  *      Frees a control egress queue.
7147  */
7148 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7149                     unsigned int vf, unsigned int eqid)
7150 {
7151         struct fw_eq_ctrl_cmd c;
7152
7153         memset(&c, 0, sizeof(c));
7154         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
7155                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7156                                   V_FW_EQ_CTRL_CMD_PFN(pf) |
7157                                   V_FW_EQ_CTRL_CMD_VFN(vf));
7158         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
7159         c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
7160         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7161 }
7162
7163 /**
7164  *      t4_ofld_eq_free - free an offload egress queue
7165  *      @adap: the adapter
7166  *      @mbox: mailbox to use for the FW command
7167  *      @pf: the PF owning the queue
7168  *      @vf: the VF owning the queue
7169  *      @eqid: egress queue id
7170  *
7171  *      Frees a control egress queue.
7172  */
7173 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7174                     unsigned int vf, unsigned int eqid)
7175 {
7176         struct fw_eq_ofld_cmd c;
7177
7178         memset(&c, 0, sizeof(c));
7179         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
7180                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7181                                   V_FW_EQ_OFLD_CMD_PFN(pf) |
7182                                   V_FW_EQ_OFLD_CMD_VFN(vf));
7183         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
7184         c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
7185         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7186 }
7187
7188 /**
7189  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7190  *      @link_down_rc: Link Down Reason Code
7191  *
7192  *      Returns a string representation of the Link Down Reason Code.
7193  */
7194 const char *t4_link_down_rc_str(unsigned char link_down_rc)
7195 {
7196         static const char *reason[] = {
7197                 "Link Down",
7198                 "Remote Fault",
7199                 "Auto-negotiation Failure",
7200                 "Reserved3",
7201                 "Insufficient Airflow",
7202                 "Unable To Determine Reason",
7203                 "No RX Signal Detected",
7204                 "Reserved7",
7205         };
7206
7207         if (link_down_rc >= ARRAY_SIZE(reason))
7208                 return "Bad Reason Code";
7209
7210         return reason[link_down_rc];
7211 }
7212
7213 /**
7214  *      t4_handle_fw_rpl - process a FW reply message
7215  *      @adap: the adapter
7216  *      @rpl: start of the FW message
7217  *
7218  *      Processes a FW message, such as link state change messages.
7219  */
7220 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7221 {
7222         u8 opcode = *(const u8 *)rpl;
7223         const struct fw_port_cmd *p = (const void *)rpl;
7224         unsigned int action =
7225                         G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
7226
7227         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7228                 /* link/module state change message */
7229                 int speed = 0, fc = 0, i;
7230                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
7231                 struct port_info *pi = NULL;
7232                 struct link_config *lc;
7233                 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7234                 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
7235                 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
7236
7237                 if (stat & F_FW_PORT_CMD_RXPAUSE)
7238                         fc |= PAUSE_RX;
7239                 if (stat & F_FW_PORT_CMD_TXPAUSE)
7240                         fc |= PAUSE_TX;
7241                 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
7242                         speed = 100;
7243                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
7244                         speed = 1000;
7245                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
7246                         speed = 10000;
7247                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
7248                         speed = 40000;
7249
7250                 for_each_port(adap, i) {
7251                         pi = adap2pinfo(adap, i);
7252                         if (pi->tx_chan == chan)
7253                                 break;
7254                 }
7255                 lc = &pi->link_cfg;
7256
7257                 if (mod != pi->mod_type) {
7258                         pi->mod_type = mod;
7259                         t4_os_portmod_changed(adap, i);
7260                 }
7261                 if (link_ok != lc->link_ok || speed != lc->speed ||
7262                     fc != lc->fc) {                    /* something changed */
7263                         int reason;
7264
7265                         if (!link_ok && lc->link_ok)
7266                                 reason = G_FW_PORT_CMD_LINKDNRC(stat);
7267                         else
7268                                 reason = -1;
7269
7270                         lc->link_ok = link_ok;
7271                         lc->speed = speed;
7272                         lc->fc = fc;
7273                         lc->supported = be16_to_cpu(p->u.info.pcap);
7274                         t4_os_link_changed(adap, i, link_ok, reason);
7275                 }
7276         } else {
7277                 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
7278                 return -EINVAL;
7279         }
7280         return 0;
7281 }
7282
7283 /**
7284  *      get_pci_mode - determine a card's PCI mode
7285  *      @adapter: the adapter
7286  *      @p: where to store the PCI settings
7287  *
7288  *      Determines a card's PCI mode and associated parameters, such as speed
7289  *      and width.
7290  */
7291 static void get_pci_mode(struct adapter *adapter,
7292                                    struct pci_params *p)
7293 {
7294         u16 val;
7295         u32 pcie_cap;
7296
7297         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7298         if (pcie_cap) {
7299                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
7300                 p->speed = val & PCI_EXP_LNKSTA_CLS;
7301                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7302         }
7303 }
7304
7305 /**
7306  *      init_link_config - initialize a link's SW state
7307  *      @lc: structure holding the link state
7308  *      @caps: link capabilities
7309  *
7310  *      Initializes the SW state maintained for each link, including the link's
7311  *      capabilities and default speed/flow-control/autonegotiation settings.
7312  */
7313 static void init_link_config(struct link_config *lc, unsigned int caps)
7314 {
7315         lc->supported = caps;
7316         lc->requested_speed = 0;
7317         lc->speed = 0;
7318         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7319         if (lc->supported & FW_PORT_CAP_ANEG) {
7320                 lc->advertising = lc->supported & ADVERT_MASK;
7321                 lc->autoneg = AUTONEG_ENABLE;
7322                 lc->requested_fc |= PAUSE_AUTONEG;
7323         } else {
7324                 lc->advertising = 0;
7325                 lc->autoneg = AUTONEG_DISABLE;
7326         }
7327 }
7328
7329 struct flash_desc {
7330         u32 vendor_and_model_id;
7331         u32 size_mb;
7332 };
7333
7334 int t4_get_flash_params(struct adapter *adapter)
7335 {
7336         /*
7337          * Table for non-Numonix supported flash parts.  Numonix parts are left
7338          * to the preexisting well-tested code.  All flash parts have 64KB
7339          * sectors.
7340          */
7341         static struct flash_desc supported_flash[] = {
7342                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
7343         };
7344
7345         int ret;
7346         u32 info = 0;
7347
7348         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
7349         if (!ret)
7350                 ret = sf1_read(adapter, 3, 0, 1, &info);
7351         t4_write_reg(adapter, A_SF_OP, 0);      /* unlock SF */
7352         if (ret < 0)
7353                 return ret;
7354
7355         for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7356                 if (supported_flash[ret].vendor_and_model_id == info) {
7357                         adapter->params.sf_size = supported_flash[ret].size_mb;
7358                         adapter->params.sf_nsec =
7359                                 adapter->params.sf_size / SF_SEC_SIZE;
7360                         return 0;
7361                 }
7362
7363         if ((info & 0xff) != 0x20)              /* not a Numonix flash */
7364                 return -EINVAL;
7365         info >>= 16;                            /* log2 of size */
7366         if (info >= 0x14 && info < 0x18)
7367                 adapter->params.sf_nsec = 1 << (info - 16);
7368         else if (info == 0x18)
7369                 adapter->params.sf_nsec = 64;
7370         else
7371                 return -EINVAL;
7372         adapter->params.sf_size = 1 << info;
7373
7374         /*
7375          * We should ~probably~ reject adapters with FLASHes which are too
7376          * small but we have some legacy FPGAs with small FLASHes that we'd
7377          * still like to use.  So instead we emit a scary message ...
7378          */
7379         if (adapter->params.sf_size < FLASH_MIN_SIZE)
7380                 CH_WARN(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
7381                         adapter->params.sf_size, FLASH_MIN_SIZE);
7382
7383         return 0;
7384 }
7385
7386 static void set_pcie_completion_timeout(struct adapter *adapter,
7387                                                   u8 range)
7388 {
7389         u16 val;
7390         u32 pcie_cap;
7391
7392         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7393         if (pcie_cap) {
7394                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
7395                 val &= 0xfff0;
7396                 val |= range ;
7397                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
7398         }
7399 }
7400
7401 static const struct chip_params *get_chip_params(int chipid)
7402 {
7403         static const struct chip_params chip_params[] = {
7404                 {
7405                         /* T4 */
7406                         .nchan = NCHAN,
7407                         .pm_stats_cnt = PM_NSTATS,
7408                         .cng_ch_bits_log = 2,
7409                         .nsched_cls = 15,
7410                         .cim_num_obq = CIM_NUM_OBQ,
7411                         .mps_rplc_size = 128,
7412                         .vfcount = 128,
7413                         .sge_fl_db = F_DBPRIO,
7414                         .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
7415                 },
7416                 {
7417                         /* T5 */
7418                         .nchan = NCHAN,
7419                         .pm_stats_cnt = PM_NSTATS,
7420                         .cng_ch_bits_log = 2,
7421                         .nsched_cls = 16,
7422                         .cim_num_obq = CIM_NUM_OBQ_T5,
7423                         .mps_rplc_size = 128,
7424                         .vfcount = 128,
7425                         .sge_fl_db = F_DBPRIO | F_DBTYPE,
7426                         .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7427                 },
7428                 {
7429                         /* T6 */
7430                         .nchan = T6_NCHAN,
7431                         .pm_stats_cnt = T6_PM_NSTATS,
7432                         .cng_ch_bits_log = 3,
7433                         .nsched_cls = 16,
7434                         .cim_num_obq = CIM_NUM_OBQ_T5,
7435                         .mps_rplc_size = 256,
7436                         .vfcount = 256,
7437                         .sge_fl_db = 0,
7438                         .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7439                 },
7440         };
7441
7442         chipid -= CHELSIO_T4;
7443         if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
7444                 return NULL;
7445
7446         return &chip_params[chipid];
7447 }
7448
7449 /**
7450  *      t4_prep_adapter - prepare SW and HW for operation
7451  *      @adapter: the adapter
7452  *      @buf: temporary space of at least VPD_LEN size provided by the caller.
7453  *
7454  *      Initialize adapter SW state for the various HW modules, set initial
7455  *      values for some adapter tunables, take PHYs out of reset, and
7456  *      initialize the MDIO interface.
7457  */
7458 int t4_prep_adapter(struct adapter *adapter, u8 *buf)
7459 {
7460         int ret;
7461         uint16_t device_id;
7462         uint32_t pl_rev;
7463
7464         get_pci_mode(adapter, &adapter->params.pci);
7465
7466         pl_rev = t4_read_reg(adapter, A_PL_REV);
7467         adapter->params.chipid = G_CHIPID(pl_rev);
7468         adapter->params.rev = G_REV(pl_rev);
7469         if (adapter->params.chipid == 0) {
7470                 /* T4 did not have chipid in PL_REV (T5 onwards do) */
7471                 adapter->params.chipid = CHELSIO_T4;
7472
7473                 /* T4A1 chip is not supported */
7474                 if (adapter->params.rev == 1) {
7475                         CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
7476                         return -EINVAL;
7477                 }
7478         }
7479
7480         adapter->chip_params = get_chip_params(chip_id(adapter));
7481         if (adapter->chip_params == NULL)
7482                 return -EINVAL;
7483
7484         adapter->params.pci.vpd_cap_addr =
7485             t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
7486
7487         ret = t4_get_flash_params(adapter);
7488         if (ret < 0)
7489                 return ret;
7490
7491         ret = get_vpd_params(adapter, &adapter->params.vpd, buf);
7492         if (ret < 0)
7493                 return ret;
7494
7495         /* Cards with real ASICs have the chipid in the PCIe device id */
7496         t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
7497         if (device_id >> 12 == chip_id(adapter))
7498                 adapter->params.cim_la_size = CIMLA_SIZE;
7499         else {
7500                 /* FPGA */
7501                 adapter->params.fpga = 1;
7502                 adapter->params.cim_la_size = 2 * CIMLA_SIZE;
7503         }
7504
7505         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7506
7507         /*
7508          * Default port and clock for debugging in case we can't reach FW.
7509          */
7510         adapter->params.nports = 1;
7511         adapter->params.portvec = 1;
7512         adapter->params.vpd.cclk = 50000;
7513
7514         /* Set pci completion timeout value to 4 seconds. */
7515         set_pcie_completion_timeout(adapter, 0xd);
7516         return 0;
7517 }
7518
7519 /**
7520  *      t4_shutdown_adapter - shut down adapter, host & wire
7521  *      @adapter: the adapter
7522  *
7523  *      Perform an emergency shutdown of the adapter and stop it from
7524  *      continuing any further communication on the ports or DMA to the
7525  *      host.  This is typically used when the adapter and/or firmware
7526  *      have crashed and we want to prevent any further accidental
7527  *      communication with the rest of the world.  This will also force
7528  *      the port Link Status to go down -- if register writes work --
7529  *      which should help our peers figure out that we're down.
7530  */
7531 int t4_shutdown_adapter(struct adapter *adapter)
7532 {
7533         int port;
7534
7535         t4_intr_disable(adapter);
7536         t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
7537         for_each_port(adapter, port) {
7538                 u32 a_port_cfg = PORT_REG(port,
7539                                           is_t4(adapter)
7540                                           ? A_XGMAC_PORT_CFG
7541                                           : A_MAC_PORT_CFG);
7542
7543                 t4_write_reg(adapter, a_port_cfg,
7544                              t4_read_reg(adapter, a_port_cfg)
7545                              & ~V_SIGNAL_DET(1));
7546         }
7547         t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
7548
7549         return 0;
7550 }
7551
7552 /**
7553  *      t4_init_devlog_params - initialize adapter->params.devlog
7554  *      @adap: the adapter
7555  *      @fw_attach: whether we can talk to the firmware
7556  *
7557  *      Initialize various fields of the adapter's Firmware Device Log
7558  *      Parameters structure.
7559  */
7560 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
7561 {
7562         struct devlog_params *dparams = &adap->params.devlog;
7563         u32 pf_dparams;
7564         unsigned int devlog_meminfo;
7565         struct fw_devlog_cmd devlog_cmd;
7566         int ret;
7567
7568         /* If we're dealing with newer firmware, the Device Log Paramerters
7569          * are stored in a designated register which allows us to access the
7570          * Device Log even if we can't talk to the firmware.
7571          */
7572         pf_dparams =
7573                 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
7574         if (pf_dparams) {
7575                 unsigned int nentries, nentries128;
7576
7577                 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
7578                 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
7579
7580                 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
7581                 nentries = (nentries128 + 1) * 128;
7582                 dparams->size = nentries * sizeof(struct fw_devlog_e);
7583
7584                 return 0;
7585         }
7586
7587         /*
7588          * For any failing returns ...
7589          */
7590         memset(dparams, 0, sizeof *dparams);
7591
7592         /*
7593          * If we can't talk to the firmware, there's really nothing we can do
7594          * at this point.
7595          */
7596         if (!fw_attach)
7597                 return -ENXIO;
7598
7599         /* Otherwise, ask the firmware for it's Device Log Parameters.
7600          */
7601         memset(&devlog_cmd, 0, sizeof devlog_cmd);
7602         devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
7603                                              F_FW_CMD_REQUEST | F_FW_CMD_READ);
7604         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7605         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7606                          &devlog_cmd);
7607         if (ret)
7608                 return ret;
7609
7610         devlog_meminfo =
7611                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7612         dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
7613         dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
7614         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7615
7616         return 0;
7617 }
7618
7619 /**
7620  *      t4_init_sge_params - initialize adap->params.sge
7621  *      @adapter: the adapter
7622  *
7623  *      Initialize various fields of the adapter's SGE Parameters structure.
7624  */
7625 int t4_init_sge_params(struct adapter *adapter)
7626 {
7627         u32 r;
7628         struct sge_params *sp = &adapter->params.sge;
7629
7630         r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
7631         sp->counter_val[0] = G_THRESHOLD_0(r);
7632         sp->counter_val[1] = G_THRESHOLD_1(r);
7633         sp->counter_val[2] = G_THRESHOLD_2(r);
7634         sp->counter_val[3] = G_THRESHOLD_3(r);
7635
7636         r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
7637         sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r));
7638         sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r));
7639         r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
7640         sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r));
7641         sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r));
7642         r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
7643         sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r));
7644         sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r));
7645
7646         r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
7647         sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
7648         if (is_t4(adapter))
7649                 sp->fl_starve_threshold2 = sp->fl_starve_threshold;
7650         else
7651                 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
7652
7653         /* egress queues: log2 of # of doorbells per BAR2 page */
7654         r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
7655         r >>= S_QUEUESPERPAGEPF0 +
7656             (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
7657         sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
7658
7659         /* ingress queues: log2 of # of doorbells per BAR2 page */
7660         r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
7661         r >>= S_QUEUESPERPAGEPF0 +
7662             (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
7663         sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
7664
7665         r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
7666         r >>= S_HOSTPAGESIZEPF0 +
7667             (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
7668         sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
7669
7670         r = t4_read_reg(adapter, A_SGE_CONTROL);
7671         sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
7672         sp->fl_pktshift = G_PKTSHIFT(r);
7673         sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 5);
7674         if (is_t4(adapter))
7675                 sp->pack_boundary = sp->pad_boundary;
7676         else {
7677                 r = t4_read_reg(adapter, A_SGE_CONTROL2);
7678                 if (G_INGPACKBOUNDARY(r) == 0)
7679                         sp->pack_boundary = 16;
7680                 else
7681                         sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
7682         }
7683
7684         return 0;
7685 }
7686
7687 /*
7688  * Read and cache the adapter's compressed filter mode and ingress config.
7689  */
7690 static void read_filter_mode_and_ingress_config(struct adapter *adap)
7691 {
7692         struct tp_params *tpp = &adap->params.tp;
7693
7694         if (t4_use_ldst(adap)) {
7695                 t4_fw_tp_pio_rw(adap, &tpp->vlan_pri_map, 1,
7696                                 A_TP_VLAN_PRI_MAP, 1);
7697                 t4_fw_tp_pio_rw(adap, &tpp->ingress_config, 1,
7698                                 A_TP_INGRESS_CONFIG, 1);
7699         } else {
7700                 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7701                                  &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
7702                 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7703                                  &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG);
7704         }
7705
7706         /*
7707          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7708          * shift positions of several elements of the Compressed Filter Tuple
7709          * for this adapter which we need frequently ...
7710          */
7711         tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
7712         tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
7713         tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
7714         tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
7715         tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
7716         tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
7717         tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
7718         tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
7719         tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
7720         tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
7721
7722         /*
7723          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7724          * represents the presense of an Outer VLAN instead of a VNIC ID.
7725          */
7726         if ((tpp->ingress_config & F_VNIC) == 0)
7727                 tpp->vnic_shift = -1;
7728 }
7729
7730 /**
7731  *      t4_init_tp_params - initialize adap->params.tp
7732  *      @adap: the adapter
7733  *
7734  *      Initialize various fields of the adapter's TP Parameters structure.
7735  */
7736 int t4_init_tp_params(struct adapter *adap)
7737 {
7738         int chan;
7739         u32 v;
7740         struct tp_params *tpp = &adap->params.tp;
7741
7742         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
7743         tpp->tre = G_TIMERRESOLUTION(v);
7744         tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
7745
7746         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7747         for (chan = 0; chan < MAX_NCHAN; chan++)
7748                 tpp->tx_modq[chan] = chan;
7749
7750         read_filter_mode_and_ingress_config(adap);
7751
7752         /*
7753          * For T6, cache the adapter's compressed error vector
7754          * and passing outer header info for encapsulated packets.
7755          */
7756         if (chip_id(adap) > CHELSIO_T5) {
7757                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
7758                 tpp->rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
7759         }
7760
7761         return 0;
7762 }
7763
7764 /**
7765  *      t4_filter_field_shift - calculate filter field shift
7766  *      @adap: the adapter
7767  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7768  *
7769  *      Return the shift position of a filter field within the Compressed
7770  *      Filter Tuple.  The filter field is specified via its selection bit
7771  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
7772  */
7773 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7774 {
7775         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7776         unsigned int sel;
7777         int field_shift;
7778
7779         if ((filter_mode & filter_sel) == 0)
7780                 return -1;
7781
7782         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7783                 switch (filter_mode & sel) {
7784                 case F_FCOE:
7785                         field_shift += W_FT_FCOE;
7786                         break;
7787                 case F_PORT:
7788                         field_shift += W_FT_PORT;
7789                         break;
7790                 case F_VNIC_ID:
7791                         field_shift += W_FT_VNIC_ID;
7792                         break;
7793                 case F_VLAN:
7794                         field_shift += W_FT_VLAN;
7795                         break;
7796                 case F_TOS:
7797                         field_shift += W_FT_TOS;
7798                         break;
7799                 case F_PROTOCOL:
7800                         field_shift += W_FT_PROTOCOL;
7801                         break;
7802                 case F_ETHERTYPE:
7803                         field_shift += W_FT_ETHERTYPE;
7804                         break;
7805                 case F_MACMATCH:
7806                         field_shift += W_FT_MACMATCH;
7807                         break;
7808                 case F_MPSHITTYPE:
7809                         field_shift += W_FT_MPSHITTYPE;
7810                         break;
7811                 case F_FRAGMENTATION:
7812                         field_shift += W_FT_FRAGMENTATION;
7813                         break;
7814                 }
7815         }
7816         return field_shift;
7817 }
7818
7819 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
7820 {
7821         u8 addr[6];
7822         int ret, i, j;
7823         struct fw_port_cmd c;
7824         u16 rss_size;
7825         struct port_info *p = adap2pinfo(adap, port_id);
7826         u32 param, val;
7827
7828         memset(&c, 0, sizeof(c));
7829
7830         for (i = 0, j = -1; i <= p->port_id; i++) {
7831                 do {
7832                         j++;
7833                 } while ((adap->params.portvec & (1 << j)) == 0);
7834         }
7835
7836         c.op_to_portid = htonl(V_FW_CMD_OP(FW_PORT_CMD) |
7837                                F_FW_CMD_REQUEST | F_FW_CMD_READ |
7838                                V_FW_PORT_CMD_PORTID(j));
7839         c.action_to_len16 = htonl(
7840                 V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
7841                 FW_LEN16(c));
7842         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7843         if (ret)
7844                 return ret;
7845
7846         ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
7847         if (ret < 0)
7848                 return ret;
7849
7850         p->vi[0].viid = ret;
7851         p->tx_chan = j;
7852         p->rx_chan_map = t4_get_mps_bg_map(adap, j);
7853         p->lport = j;
7854         p->vi[0].rss_size = rss_size;
7855         t4_os_set_hw_addr(adap, p->port_id, addr);
7856
7857         ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7858         p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
7859                 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
7860         p->port_type = G_FW_PORT_CMD_PTYPE(ret);
7861         p->mod_type = G_FW_PORT_CMD_MODTYPE(ret);
7862
7863         init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
7864
7865         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
7866             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
7867             V_FW_PARAMS_PARAM_YZ(p->vi[0].viid);
7868         ret = t4_query_params(adap, mbox, pf, vf, 1, &param, &val);
7869         if (ret)
7870                 p->vi[0].rss_base = 0xffff;
7871         else {
7872                 /* MPASS((val >> 16) == rss_size); */
7873                 p->vi[0].rss_base = val & 0xffff;
7874         }
7875
7876         return 0;
7877 }
7878
7879 /**
7880  *      t4_read_cimq_cfg - read CIM queue configuration
7881  *      @adap: the adapter
7882  *      @base: holds the queue base addresses in bytes
7883  *      @size: holds the queue sizes in bytes
7884  *      @thres: holds the queue full thresholds in bytes
7885  *
7886  *      Returns the current configuration of the CIM queues, starting with
7887  *      the IBQs, then the OBQs.
7888  */
7889 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7890 {
7891         unsigned int i, v;
7892         int cim_num_obq = adap->chip_params->cim_num_obq;
7893
7894         for (i = 0; i < CIM_NUM_IBQ; i++) {
7895                 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
7896                              V_QUENUMSELECT(i));
7897                 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
7898                 /* value is in 256-byte units */
7899                 *base++ = G_CIMQBASE(v) * 256;
7900                 *size++ = G_CIMQSIZE(v) * 256;
7901                 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
7902         }
7903         for (i = 0; i < cim_num_obq; i++) {
7904                 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
7905                              V_QUENUMSELECT(i));
7906                 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
7907                 /* value is in 256-byte units */
7908                 *base++ = G_CIMQBASE(v) * 256;
7909                 *size++ = G_CIMQSIZE(v) * 256;
7910         }
7911 }
7912
7913 /**
7914  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
7915  *      @adap: the adapter
7916  *      @qid: the queue index
7917  *      @data: where to store the queue contents
7918  *      @n: capacity of @data in 32-bit words
7919  *
7920  *      Reads the contents of the selected CIM queue starting at address 0 up
7921  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
7922  *      error and the number of 32-bit words actually read on success.
7923  */
7924 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7925 {
7926         int i, err, attempts;
7927         unsigned int addr;
7928         const unsigned int nwords = CIM_IBQ_SIZE * 4;
7929
7930         if (qid > 5 || (n & 3))
7931                 return -EINVAL;
7932
7933         addr = qid * nwords;
7934         if (n > nwords)
7935                 n = nwords;
7936
7937         /* It might take 3-10ms before the IBQ debug read access is allowed.
7938          * Wait for 1 Sec with a delay of 1 usec.
7939          */
7940         attempts = 1000000;
7941
7942         for (i = 0; i < n; i++, addr++) {
7943                 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
7944                              F_IBQDBGEN);
7945                 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
7946                                       attempts, 1);
7947                 if (err)
7948                         return err;
7949                 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
7950         }
7951         t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
7952         return i;
7953 }
7954
7955 /**
7956  *      t4_read_cim_obq - read the contents of a CIM outbound queue
7957  *      @adap: the adapter
7958  *      @qid: the queue index
7959  *      @data: where to store the queue contents
7960  *      @n: capacity of @data in 32-bit words
7961  *
7962  *      Reads the contents of the selected CIM queue starting at address 0 up
7963  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
7964  *      error and the number of 32-bit words actually read on success.
7965  */
7966 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7967 {
7968         int i, err;
7969         unsigned int addr, v, nwords;
7970         int cim_num_obq = adap->chip_params->cim_num_obq;
7971
7972         if ((qid > (cim_num_obq - 1)) || (n & 3))
7973                 return -EINVAL;
7974
7975         t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
7976                      V_QUENUMSELECT(qid));
7977         v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
7978
7979         addr = G_CIMQBASE(v) * 64;    /* muliple of 256 -> muliple of 4 */
7980         nwords = G_CIMQSIZE(v) * 64;  /* same */
7981         if (n > nwords)
7982                 n = nwords;
7983
7984         for (i = 0; i < n; i++, addr++) {
7985                 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
7986                              F_OBQDBGEN);
7987                 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
7988                                       2, 1);
7989                 if (err)
7990                         return err;
7991                 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
7992         }
7993         t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
7994         return i;
7995 }
7996
7997 enum {
7998         CIM_QCTL_BASE     = 0,
7999         CIM_CTL_BASE      = 0x2000,
8000         CIM_PBT_ADDR_BASE = 0x2800,
8001         CIM_PBT_LRF_BASE  = 0x3000,
8002         CIM_PBT_DATA_BASE = 0x3800
8003 };
8004
8005 /**
8006  *      t4_cim_read - read a block from CIM internal address space
8007  *      @adap: the adapter
8008  *      @addr: the start address within the CIM address space
8009  *      @n: number of words to read
8010  *      @valp: where to store the result
8011  *
8012  *      Reads a block of 4-byte words from the CIM intenal address space.
8013  */
8014 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8015                 unsigned int *valp)
8016 {
8017         int ret = 0;
8018
8019         if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8020                 return -EBUSY;
8021
8022         for ( ; !ret && n--; addr += 4) {
8023                 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
8024                 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8025                                       0, 5, 2);
8026                 if (!ret)
8027                         *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
8028         }
8029         return ret;
8030 }
8031
8032 /**
8033  *      t4_cim_write - write a block into CIM internal address space
8034  *      @adap: the adapter
8035  *      @addr: the start address within the CIM address space
8036  *      @n: number of words to write
8037  *      @valp: set of values to write
8038  *
8039  *      Writes a block of 4-byte words into the CIM intenal address space.
8040  */
8041 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8042                  const unsigned int *valp)
8043 {
8044         int ret = 0;
8045
8046         if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8047                 return -EBUSY;
8048
8049         for ( ; !ret && n--; addr += 4) {
8050                 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
8051                 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
8052                 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8053                                       0, 5, 2);
8054         }
8055         return ret;
8056 }
8057
8058 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8059                          unsigned int val)
8060 {
8061         return t4_cim_write(adap, addr, 1, &val);
8062 }
8063
8064 /**
8065  *      t4_cim_ctl_read - read a block from CIM control region
8066  *      @adap: the adapter
8067  *      @addr: the start address within the CIM control region
8068  *      @n: number of words to read
8069  *      @valp: where to store the result
8070  *
8071  *      Reads a block of 4-byte words from the CIM control region.
8072  */
8073 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
8074                     unsigned int *valp)
8075 {
8076         return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
8077 }
8078
8079 /**
8080  *      t4_cim_read_la - read CIM LA capture buffer
8081  *      @adap: the adapter
8082  *      @la_buf: where to store the LA data
8083  *      @wrptr: the HW write pointer within the capture buffer
8084  *
8085  *      Reads the contents of the CIM LA buffer with the most recent entry at
8086  *      the end of the returned data and with the entry at @wrptr first.
8087  *      We try to leave the LA in the running state we find it in.
8088  */
8089 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8090 {
8091         int i, ret;
8092         unsigned int cfg, val, idx;
8093
8094         ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
8095         if (ret)
8096                 return ret;
8097
8098         if (cfg & F_UPDBGLAEN) {        /* LA is running, freeze it */
8099                 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
8100                 if (ret)
8101                         return ret;
8102         }
8103
8104         ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8105         if (ret)
8106                 goto restart;
8107
8108         idx = G_UPDBGLAWRPTR(val);
8109         if (wrptr)
8110                 *wrptr = idx;
8111
8112         for (i = 0; i < adap->params.cim_la_size; i++) {
8113                 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8114                                     V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
8115                 if (ret)
8116                         break;
8117                 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8118                 if (ret)
8119                         break;
8120                 if (val & F_UPDBGLARDEN) {
8121                         ret = -ETIMEDOUT;
8122                         break;
8123                 }
8124                 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
8125                 if (ret)
8126                         break;
8127
8128                 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
8129                 idx = (idx + 1) & M_UPDBGLARDPTR;
8130                 /*
8131                  * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
8132                  * identify the 32-bit portion of the full 312-bit data
8133                  */
8134                 if (is_t6(adap))
8135                         while ((idx & 0xf) > 9)
8136                                 idx = (idx + 1) % M_UPDBGLARDPTR;
8137         }
8138 restart:
8139         if (cfg & F_UPDBGLAEN) {
8140                 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8141                                       cfg & ~F_UPDBGLARDEN);
8142                 if (!ret)
8143                         ret = r;
8144         }
8145         return ret;
8146 }
8147
8148 /**
8149  *      t4_tp_read_la - read TP LA capture buffer
8150  *      @adap: the adapter
8151  *      @la_buf: where to store the LA data
8152  *      @wrptr: the HW write pointer within the capture buffer
8153  *
8154  *      Reads the contents of the TP LA buffer with the most recent entry at
8155  *      the end of the returned data and with the entry at @wrptr first.
8156  *      We leave the LA in the running state we find it in.
8157  */
8158 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8159 {
8160         bool last_incomplete;
8161         unsigned int i, cfg, val, idx;
8162
8163         cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
8164         if (cfg & F_DBGLAENABLE)                        /* freeze LA */
8165                 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8166                              adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
8167
8168         val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
8169         idx = G_DBGLAWPTR(val);
8170         last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
8171         if (last_incomplete)
8172                 idx = (idx + 1) & M_DBGLARPTR;
8173         if (wrptr)
8174                 *wrptr = idx;
8175
8176         val &= 0xffff;
8177         val &= ~V_DBGLARPTR(M_DBGLARPTR);
8178         val |= adap->params.tp.la_mask;
8179
8180         for (i = 0; i < TPLA_SIZE; i++) {
8181                 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
8182                 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
8183                 idx = (idx + 1) & M_DBGLARPTR;
8184         }
8185
8186         /* Wipe out last entry if it isn't valid */
8187         if (last_incomplete)
8188                 la_buf[TPLA_SIZE - 1] = ~0ULL;
8189
8190         if (cfg & F_DBGLAENABLE)                /* restore running state */
8191                 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8192                              cfg | adap->params.tp.la_mask);
8193 }
8194
8195 /*
8196  * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8197  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
8198  * state for more than the Warning Threshold then we'll issue a warning about
8199  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
8200  * appears to be hung every Warning Repeat second till the situation clears.
8201  * If the situation clears, we'll note that as well.
8202  */
8203 #define SGE_IDMA_WARN_THRESH 1
8204 #define SGE_IDMA_WARN_REPEAT 300
8205
8206 /**
8207  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8208  *      @adapter: the adapter
8209  *      @idma: the adapter IDMA Monitor state
8210  *
8211  *      Initialize the state of an SGE Ingress DMA Monitor.
8212  */
8213 void t4_idma_monitor_init(struct adapter *adapter,
8214                           struct sge_idma_monitor_state *idma)
8215 {
8216         /* Initialize the state variables for detecting an SGE Ingress DMA
8217          * hang.  The SGE has internal counters which count up on each clock
8218          * tick whenever the SGE finds its Ingress DMA State Engines in the
8219          * same state they were on the previous clock tick.  The clock used is
8220          * the Core Clock so we have a limit on the maximum "time" they can
8221          * record; typically a very small number of seconds.  For instance,
8222          * with a 600MHz Core Clock, we can only count up to a bit more than
8223          * 7s.  So we'll synthesize a larger counter in order to not run the
8224          * risk of having the "timers" overflow and give us the flexibility to
8225          * maintain a Hung SGE State Machine of our own which operates across
8226          * a longer time frame.
8227          */
8228         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8229         idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
8230 }
8231
8232 /**
8233  *      t4_idma_monitor - monitor SGE Ingress DMA state
8234  *      @adapter: the adapter
8235  *      @idma: the adapter IDMA Monitor state
8236  *      @hz: number of ticks/second
8237  *      @ticks: number of ticks since the last IDMA Monitor call
8238  */
8239 void t4_idma_monitor(struct adapter *adapter,
8240                      struct sge_idma_monitor_state *idma,
8241                      int hz, int ticks)
8242 {
8243         int i, idma_same_state_cnt[2];
8244
8245          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
8246           * are counters inside the SGE which count up on each clock when the
8247           * SGE finds its Ingress DMA State Engines in the same states they
8248           * were in the previous clock.  The counters will peg out at
8249           * 0xffffffff without wrapping around so once they pass the 1s
8250           * threshold they'll stay above that till the IDMA state changes.
8251           */
8252         t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
8253         idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
8254         idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8255
8256         for (i = 0; i < 2; i++) {
8257                 u32 debug0, debug11;
8258
8259                 /* If the Ingress DMA Same State Counter ("timer") is less
8260                  * than 1s, then we can reset our synthesized Stall Timer and
8261                  * continue.  If we have previously emitted warnings about a
8262                  * potential stalled Ingress Queue, issue a note indicating
8263                  * that the Ingress Queue has resumed forward progress.
8264                  */
8265                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8266                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
8267                                 CH_WARN(adapter, "SGE idma%d, queue %u, "
8268                                         "resumed after %d seconds\n",
8269                                         i, idma->idma_qid[i],
8270                                         idma->idma_stalled[i]/hz);
8271                         idma->idma_stalled[i] = 0;
8272                         continue;
8273                 }
8274
8275                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8276                  * domain.  The first time we get here it'll be because we
8277                  * passed the 1s Threshold; each additional time it'll be
8278                  * because the RX Timer Callback is being fired on its regular
8279                  * schedule.
8280                  *
8281                  * If the stall is below our Potential Hung Ingress Queue
8282                  * Warning Threshold, continue.
8283                  */
8284                 if (idma->idma_stalled[i] == 0) {
8285                         idma->idma_stalled[i] = hz;
8286                         idma->idma_warn[i] = 0;
8287                 } else {
8288                         idma->idma_stalled[i] += ticks;
8289                         idma->idma_warn[i] -= ticks;
8290                 }
8291
8292                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
8293                         continue;
8294
8295                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8296                  */
8297                 if (idma->idma_warn[i] > 0)
8298                         continue;
8299                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
8300
8301                 /* Read and save the SGE IDMA State and Queue ID information.
8302                  * We do this every time in case it changes across time ...
8303                  * can't be too careful ...
8304                  */
8305                 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
8306                 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8307                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8308
8309                 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
8310                 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8311                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8312
8313                 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
8314                         " state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8315                         i, idma->idma_qid[i], idma->idma_state[i],
8316                         idma->idma_stalled[i]/hz,
8317                         debug0, debug11);
8318                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8319         }
8320 }
8321
8322 /**
8323  *      t4_read_pace_tbl - read the pace table
8324  *      @adap: the adapter
8325  *      @pace_vals: holds the returned values
8326  *
8327  *      Returns the values of TP's pace table in microseconds.
8328  */
8329 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
8330 {
8331         unsigned int i, v;
8332
8333         for (i = 0; i < NTX_SCHED; i++) {
8334                 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
8335                 v = t4_read_reg(adap, A_TP_PACE_TABLE);
8336                 pace_vals[i] = dack_ticks_to_usec(adap, v);
8337         }
8338 }
8339
8340 /**
8341  *      t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
8342  *      @adap: the adapter
8343  *      @sched: the scheduler index
8344  *      @kbps: the byte rate in Kbps
8345  *      @ipg: the interpacket delay in tenths of nanoseconds
8346  *
8347  *      Return the current configuration of a HW Tx scheduler.
8348  */
8349 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
8350                      unsigned int *ipg)
8351 {
8352         unsigned int v, addr, bpt, cpt;
8353
8354         if (kbps) {
8355                 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
8356                 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8357                 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8358                 if (sched & 1)
8359                         v >>= 16;
8360                 bpt = (v >> 8) & 0xff;
8361                 cpt = v & 0xff;
8362                 if (!cpt)
8363                         *kbps = 0;      /* scheduler disabled */
8364                 else {
8365                         v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
8366                         *kbps = (v * bpt) / 125;
8367                 }
8368         }
8369         if (ipg) {
8370                 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
8371                 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8372                 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8373                 if (sched & 1)
8374                         v >>= 16;
8375                 v &= 0xffff;
8376                 *ipg = (10000 * v) / core_ticks_per_usec(adap);
8377         }
8378 }
8379
8380 /**
8381  *      t4_load_cfg - download config file
8382  *      @adap: the adapter
8383  *      @cfg_data: the cfg text file to write
8384  *      @size: text file size
8385  *
8386  *      Write the supplied config text file to the card's serial flash.
8387  */
8388 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
8389 {
8390         int ret, i, n, cfg_addr;
8391         unsigned int addr;
8392         unsigned int flash_cfg_start_sec;
8393         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8394
8395         cfg_addr = t4_flash_cfg_addr(adap);
8396         if (cfg_addr < 0)
8397                 return cfg_addr;
8398
8399         addr = cfg_addr;
8400         flash_cfg_start_sec = addr / SF_SEC_SIZE;
8401
8402         if (size > FLASH_CFG_MAX_SIZE) {
8403                 CH_ERR(adap, "cfg file too large, max is %u bytes\n",
8404                        FLASH_CFG_MAX_SIZE);
8405                 return -EFBIG;
8406         }
8407
8408         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
8409                          sf_sec_size);
8410         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
8411                                      flash_cfg_start_sec + i - 1);
8412         /*
8413          * If size == 0 then we're simply erasing the FLASH sectors associated
8414          * with the on-adapter Firmware Configuration File.
8415          */
8416         if (ret || size == 0)
8417                 goto out;
8418
8419         /* this will write to the flash up to SF_PAGE_SIZE at a time */
8420         for (i = 0; i< size; i+= SF_PAGE_SIZE) {
8421                 if ( (size - i) <  SF_PAGE_SIZE)
8422                         n = size - i;
8423                 else
8424                         n = SF_PAGE_SIZE;
8425                 ret = t4_write_flash(adap, addr, n, cfg_data, 1);
8426                 if (ret)
8427                         goto out;
8428
8429                 addr += SF_PAGE_SIZE;
8430                 cfg_data += SF_PAGE_SIZE;
8431         }
8432
8433 out:
8434         if (ret)
8435                 CH_ERR(adap, "config file %s failed %d\n",
8436                        (size == 0 ? "clear" : "download"), ret);
8437         return ret;
8438 }
8439
8440 /**
8441  *      t5_fw_init_extern_mem - initialize the external memory
8442  *      @adap: the adapter
8443  *
8444  *      Initializes the external memory on T5.
8445  */
8446 int t5_fw_init_extern_mem(struct adapter *adap)
8447 {
8448         u32 params[1], val[1];
8449         int ret;
8450
8451         if (!is_t5(adap))
8452                 return 0;
8453
8454         val[0] = 0xff; /* Initialize all MCs */
8455         params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8456                         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
8457         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
8458                         FW_CMD_MAX_TIMEOUT);
8459
8460         return ret;
8461 }
8462
8463 /* BIOS boot headers */
8464 typedef struct pci_expansion_rom_header {
8465         u8      signature[2]; /* ROM Signature. Should be 0xaa55 */
8466         u8      reserved[22]; /* Reserved per processor Architecture data */
8467         u8      pcir_offset[2]; /* Offset to PCI Data Structure */
8468 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
8469
8470 /* Legacy PCI Expansion ROM Header */
8471 typedef struct legacy_pci_expansion_rom_header {
8472         u8      signature[2]; /* ROM Signature. Should be 0xaa55 */
8473         u8      size512; /* Current Image Size in units of 512 bytes */
8474         u8      initentry_point[4];
8475         u8      cksum; /* Checksum computed on the entire Image */
8476         u8      reserved[16]; /* Reserved */
8477         u8      pcir_offset[2]; /* Offset to PCI Data Struture */
8478 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
8479
8480 /* EFI PCI Expansion ROM Header */
8481 typedef struct efi_pci_expansion_rom_header {
8482         u8      signature[2]; // ROM signature. The value 0xaa55
8483         u8      initialization_size[2]; /* Units 512. Includes this header */
8484         u8      efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
8485         u8      efi_subsystem[2]; /* Subsystem value for EFI image header */
8486         u8      efi_machine_type[2]; /* Machine type from EFI image header */
8487         u8      compression_type[2]; /* Compression type. */
8488                 /*
8489                  * Compression type definition
8490                  * 0x0: uncompressed
8491                  * 0x1: Compressed
8492                  * 0x2-0xFFFF: Reserved
8493                  */
8494         u8      reserved[8]; /* Reserved */
8495         u8      efi_image_header_offset[2]; /* Offset to EFI Image */
8496         u8      pcir_offset[2]; /* Offset to PCI Data Structure */
8497 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
8498
8499 /* PCI Data Structure Format */
8500 typedef struct pcir_data_structure { /* PCI Data Structure */
8501         u8      signature[4]; /* Signature. The string "PCIR" */
8502         u8      vendor_id[2]; /* Vendor Identification */
8503         u8      device_id[2]; /* Device Identification */
8504         u8      vital_product[2]; /* Pointer to Vital Product Data */
8505         u8      length[2]; /* PCIR Data Structure Length */
8506         u8      revision; /* PCIR Data Structure Revision */
8507         u8      class_code[3]; /* Class Code */
8508         u8      image_length[2]; /* Image Length. Multiple of 512B */
8509         u8      code_revision[2]; /* Revision Level of Code/Data */
8510         u8      code_type; /* Code Type. */
8511                 /*
8512                  * PCI Expansion ROM Code Types
8513                  * 0x00: Intel IA-32, PC-AT compatible. Legacy
8514                  * 0x01: Open Firmware standard for PCI. FCODE
8515                  * 0x02: Hewlett-Packard PA RISC. HP reserved
8516                  * 0x03: EFI Image. EFI
8517                  * 0x04-0xFF: Reserved.
8518                  */
8519         u8      indicator; /* Indicator. Identifies the last image in the ROM */
8520         u8      reserved[2]; /* Reserved */
8521 } pcir_data_t; /* PCI__DATA_STRUCTURE */
8522
8523 /* BOOT constants */
8524 enum {
8525         BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
8526         BOOT_SIGNATURE = 0xaa55,   /* signature of BIOS boot ROM */
8527         BOOT_SIZE_INC = 512,       /* image size measured in 512B chunks */
8528         BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
8529         BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment  */
8530         VENDOR_ID = 0x1425, /* Vendor ID */
8531         PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
8532 };
8533
8534 /*
8535  *      modify_device_id - Modifies the device ID of the Boot BIOS image
8536  *      @adatper: the device ID to write.
8537  *      @boot_data: the boot image to modify.
8538  *
8539  *      Write the supplied device ID to the boot BIOS image.
8540  */
8541 static void modify_device_id(int device_id, u8 *boot_data)
8542 {
8543         legacy_pci_exp_rom_header_t *header;
8544         pcir_data_t *pcir_header;
8545         u32 cur_header = 0;
8546
8547         /*
8548          * Loop through all chained images and change the device ID's
8549          */
8550         while (1) {
8551                 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
8552                 pcir_header = (pcir_data_t *) &boot_data[cur_header +
8553                               le16_to_cpu(*(u16*)header->pcir_offset)];
8554
8555                 /*
8556                  * Only modify the Device ID if code type is Legacy or HP.
8557                  * 0x00: Okay to modify
8558                  * 0x01: FCODE. Do not be modify
8559                  * 0x03: Okay to modify
8560                  * 0x04-0xFF: Do not modify
8561                  */
8562                 if (pcir_header->code_type == 0x00) {
8563                         u8 csum = 0;
8564                         int i;
8565
8566                         /*
8567                          * Modify Device ID to match current adatper
8568                          */
8569                         *(u16*) pcir_header->device_id = device_id;
8570
8571                         /*
8572                          * Set checksum temporarily to 0.
8573                          * We will recalculate it later.
8574                          */
8575                         header->cksum = 0x0;
8576
8577                         /*
8578                          * Calculate and update checksum
8579                          */
8580                         for (i = 0; i < (header->size512 * 512); i++)
8581                                 csum += (u8)boot_data[cur_header + i];
8582
8583                         /*
8584                          * Invert summed value to create the checksum
8585                          * Writing new checksum value directly to the boot data
8586                          */
8587                         boot_data[cur_header + 7] = -csum;
8588
8589                 } else if (pcir_header->code_type == 0x03) {
8590
8591                         /*
8592                          * Modify Device ID to match current adatper
8593                          */
8594                         *(u16*) pcir_header->device_id = device_id;
8595
8596                 }
8597
8598
8599                 /*
8600                  * Check indicator element to identify if this is the last
8601                  * image in the ROM.
8602                  */
8603                 if (pcir_header->indicator & 0x80)
8604                         break;
8605
8606                 /*
8607                  * Move header pointer up to the next image in the ROM.
8608                  */
8609                 cur_header += header->size512 * 512;
8610         }
8611 }
8612
8613 /*
8614  *      t4_load_boot - download boot flash
8615  *      @adapter: the adapter
8616  *      @boot_data: the boot image to write
8617  *      @boot_addr: offset in flash to write boot_data
8618  *      @size: image size
8619  *
8620  *      Write the supplied boot image to the card's serial flash.
8621  *      The boot image has the following sections: a 28-byte header and the
8622  *      boot image.
8623  */
8624 int t4_load_boot(struct adapter *adap, u8 *boot_data,
8625                  unsigned int boot_addr, unsigned int size)
8626 {
8627         pci_exp_rom_header_t *header;
8628         int pcir_offset ;
8629         pcir_data_t *pcir_header;
8630         int ret, addr;
8631         uint16_t device_id;
8632         unsigned int i;
8633         unsigned int boot_sector = (boot_addr * 1024 );
8634         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8635
8636         /*
8637          * Make sure the boot image does not encroach on the firmware region
8638          */
8639         if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
8640                 CH_ERR(adap, "boot image encroaching on firmware region\n");
8641                 return -EFBIG;
8642         }
8643
8644         /*
8645          * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
8646          * and Boot configuration data sections. These 3 boot sections span
8647          * sectors 0 to 7 in flash and live right before the FW image location.
8648          */
8649         i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
8650                         sf_sec_size);
8651         ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
8652                                      (boot_sector >> 16) + i - 1);
8653
8654         /*
8655          * If size == 0 then we're simply erasing the FLASH sectors associated
8656          * with the on-adapter option ROM file
8657          */
8658         if (ret || (size == 0))
8659                 goto out;
8660
8661         /* Get boot header */
8662         header = (pci_exp_rom_header_t *)boot_data;
8663         pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
8664         /* PCIR Data Structure */
8665         pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
8666
8667         /*
8668          * Perform some primitive sanity testing to avoid accidentally
8669          * writing garbage over the boot sectors.  We ought to check for
8670          * more but it's not worth it for now ...
8671          */
8672         if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
8673                 CH_ERR(adap, "boot image too small/large\n");
8674                 return -EFBIG;
8675         }
8676
8677 #ifndef CHELSIO_T4_DIAGS
8678         /*
8679          * Check BOOT ROM header signature
8680          */
8681         if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
8682                 CH_ERR(adap, "Boot image missing signature\n");
8683                 return -EINVAL;
8684         }
8685
8686         /*
8687          * Check PCI header signature
8688          */
8689         if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
8690                 CH_ERR(adap, "PCI header missing signature\n");
8691                 return -EINVAL;
8692         }
8693
8694         /*
8695          * Check Vendor ID matches Chelsio ID
8696          */
8697         if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
8698                 CH_ERR(adap, "Vendor ID missing signature\n");
8699                 return -EINVAL;
8700         }
8701 #endif
8702
8703         /*
8704          * Retrieve adapter's device ID
8705          */
8706         t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
8707         /* Want to deal with PF 0 so I strip off PF 4 indicator */
8708         device_id = device_id & 0xf0ff;
8709
8710         /*
8711          * Check PCIE Device ID
8712          */
8713         if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
8714                 /*
8715                  * Change the device ID in the Boot BIOS image to match
8716                  * the Device ID of the current adapter.
8717                  */
8718                 modify_device_id(device_id, boot_data);
8719         }
8720
8721         /*
8722          * Skip over the first SF_PAGE_SIZE worth of data and write it after
8723          * we finish copying the rest of the boot image. This will ensure
8724          * that the BIOS boot header will only be written if the boot image
8725          * was written in full.
8726          */
8727         addr = boot_sector;
8728         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
8729                 addr += SF_PAGE_SIZE;
8730                 boot_data += SF_PAGE_SIZE;
8731                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
8732                 if (ret)
8733                         goto out;
8734         }
8735
8736         ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
8737                              (const u8 *)header, 0);
8738
8739 out:
8740         if (ret)
8741                 CH_ERR(adap, "boot image download failed, error %d\n", ret);
8742         return ret;
8743 }
8744
8745 /*
8746  *      t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
8747  *      @adapter: the adapter
8748  *
8749  *      Return the address within the flash where the OptionROM Configuration
8750  *      is stored, or an error if the device FLASH is too small to contain
8751  *      a OptionROM Configuration.
8752  */
8753 static int t4_flash_bootcfg_addr(struct adapter *adapter)
8754 {
8755         /*
8756          * If the device FLASH isn't large enough to hold a Firmware
8757          * Configuration File, return an error.
8758          */
8759         if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
8760                 return -ENOSPC;
8761
8762         return FLASH_BOOTCFG_START;
8763 }
8764
8765 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
8766 {
8767         int ret, i, n, cfg_addr;
8768         unsigned int addr;
8769         unsigned int flash_cfg_start_sec;
8770         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8771
8772         cfg_addr = t4_flash_bootcfg_addr(adap);
8773         if (cfg_addr < 0)
8774                 return cfg_addr;
8775
8776         addr = cfg_addr;
8777         flash_cfg_start_sec = addr / SF_SEC_SIZE;
8778
8779         if (size > FLASH_BOOTCFG_MAX_SIZE) {
8780                 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
8781                         FLASH_BOOTCFG_MAX_SIZE);
8782                 return -EFBIG;
8783         }
8784
8785         i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
8786                          sf_sec_size);
8787         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
8788                                         flash_cfg_start_sec + i - 1);
8789
8790         /*
8791          * If size == 0 then we're simply erasing the FLASH sectors associated
8792          * with the on-adapter OptionROM Configuration File.
8793          */
8794         if (ret || size == 0)
8795                 goto out;
8796
8797         /* this will write to the flash up to SF_PAGE_SIZE at a time */
8798         for (i = 0; i< size; i+= SF_PAGE_SIZE) {
8799                 if ( (size - i) <  SF_PAGE_SIZE)
8800                         n = size - i;
8801                 else
8802                         n = SF_PAGE_SIZE;
8803                 ret = t4_write_flash(adap, addr, n, cfg_data, 0);
8804                 if (ret)
8805                         goto out;
8806
8807                 addr += SF_PAGE_SIZE;
8808                 cfg_data += SF_PAGE_SIZE;
8809         }
8810
8811 out:
8812         if (ret)
8813                 CH_ERR(adap, "boot config data %s failed %d\n",
8814                                 (size == 0 ? "clear" : "download"), ret);
8815         return ret;
8816 }
8817
8818 /**
8819  *      t4_set_filter_mode - configure the optional components of filter tuples
8820  *      @adap: the adapter
8821  *      @mode_map: a bitmap selcting which optional filter components to enable
8822  *
8823  *      Sets the filter mode by selecting the optional components to enable
8824  *      in filter tuples.  Returns 0 on success and a negative error if the
8825  *      requested mode needs more bits than are available for optional
8826  *      components.
8827  */
8828 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map)
8829 {
8830         static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
8831
8832         int i, nbits = 0;
8833
8834         for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
8835                 if (mode_map & (1 << i))
8836                         nbits += width[i];
8837         if (nbits > FILTER_OPT_LEN)
8838                 return -EINVAL;
8839         if (t4_use_ldst(adap))
8840                 t4_fw_tp_pio_rw(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, 0);
8841         else
8842                 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, &mode_map,
8843                                   1, A_TP_VLAN_PRI_MAP);
8844         read_filter_mode_and_ingress_config(adap);
8845
8846         return 0;
8847 }
8848
8849 /**
8850  *      t4_clr_port_stats - clear port statistics
8851  *      @adap: the adapter
8852  *      @idx: the port index
8853  *
8854  *      Clear HW statistics for the given port.
8855  */
8856 void t4_clr_port_stats(struct adapter *adap, int idx)
8857 {
8858         unsigned int i;
8859         u32 bgmap = t4_get_mps_bg_map(adap, idx);
8860         u32 port_base_addr;
8861
8862         if (is_t4(adap))
8863                 port_base_addr = PORT_BASE(idx);
8864         else
8865                 port_base_addr = T5_PORT_BASE(idx);
8866
8867         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
8868                         i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
8869                 t4_write_reg(adap, port_base_addr + i, 0);
8870         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
8871                         i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
8872                 t4_write_reg(adap, port_base_addr + i, 0);
8873         for (i = 0; i < 4; i++)
8874                 if (bgmap & (1 << i)) {
8875                         t4_write_reg(adap,
8876                         A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
8877                         t4_write_reg(adap,
8878                         A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
8879                 }
8880 }
8881
8882 /**
8883  *      t4_i2c_rd - read I2C data from adapter
8884  *      @adap: the adapter
8885  *      @port: Port number if per-port device; <0 if not
8886  *      @devid: per-port device ID or absolute device ID
8887  *      @offset: byte offset into device I2C space
8888  *      @len: byte length of I2C space data
8889  *      @buf: buffer in which to return I2C data
8890  *
8891  *      Reads the I2C data from the indicated device and location.
8892  */
8893 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
8894               int port, unsigned int devid,
8895               unsigned int offset, unsigned int len,
8896               u8 *buf)
8897 {
8898         u32 ldst_addrspace;
8899         struct fw_ldst_cmd ldst;
8900         int ret;
8901
8902         if (port >= 4 ||
8903             devid >= 256 ||
8904             offset >= 256 ||
8905             len > sizeof ldst.u.i2c.data)
8906                 return -EINVAL;
8907
8908         memset(&ldst, 0, sizeof ldst);
8909         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
8910         ldst.op_to_addrspace =
8911                 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
8912                             F_FW_CMD_REQUEST |
8913                             F_FW_CMD_READ |
8914                             ldst_addrspace);
8915         ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
8916         ldst.u.i2c.pid = (port < 0 ? 0xff : port);
8917         ldst.u.i2c.did = devid;
8918         ldst.u.i2c.boffset = offset;
8919         ldst.u.i2c.blen = len;
8920         ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
8921         if (!ret)
8922                 memcpy(buf, ldst.u.i2c.data, len);
8923         return ret;
8924 }
8925
8926 /**
8927  *      t4_i2c_wr - write I2C data to adapter
8928  *      @adap: the adapter
8929  *      @port: Port number if per-port device; <0 if not
8930  *      @devid: per-port device ID or absolute device ID
8931  *      @offset: byte offset into device I2C space
8932  *      @len: byte length of I2C space data
8933  *      @buf: buffer containing new I2C data
8934  *
8935  *      Write the I2C data to the indicated device and location.
8936  */
8937 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
8938               int port, unsigned int devid,
8939               unsigned int offset, unsigned int len,
8940               u8 *buf)
8941 {
8942         u32 ldst_addrspace;
8943         struct fw_ldst_cmd ldst;
8944
8945         if (port >= 4 ||
8946             devid >= 256 ||
8947             offset >= 256 ||
8948             len > sizeof ldst.u.i2c.data)
8949                 return -EINVAL;
8950
8951         memset(&ldst, 0, sizeof ldst);
8952         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
8953         ldst.op_to_addrspace =
8954                 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
8955                             F_FW_CMD_REQUEST |
8956                             F_FW_CMD_WRITE |
8957                             ldst_addrspace);
8958         ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
8959         ldst.u.i2c.pid = (port < 0 ? 0xff : port);
8960         ldst.u.i2c.did = devid;
8961         ldst.u.i2c.boffset = offset;
8962         ldst.u.i2c.blen = len;
8963         memcpy(ldst.u.i2c.data, buf, len);
8964         return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
8965 }
8966
8967 /**
8968  *      t4_sge_ctxt_rd - read an SGE context through FW
8969  *      @adap: the adapter
8970  *      @mbox: mailbox to use for the FW command
8971  *      @cid: the context id
8972  *      @ctype: the context type
8973  *      @data: where to store the context data
8974  *
8975  *      Issues a FW command through the given mailbox to read an SGE context.
8976  */
8977 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
8978                    enum ctxt_type ctype, u32 *data)
8979 {
8980         int ret;
8981         struct fw_ldst_cmd c;
8982
8983         if (ctype == CTXT_EGRESS)
8984                 ret = FW_LDST_ADDRSPC_SGE_EGRC;
8985         else if (ctype == CTXT_INGRESS)
8986                 ret = FW_LDST_ADDRSPC_SGE_INGC;
8987         else if (ctype == CTXT_FLM)
8988                 ret = FW_LDST_ADDRSPC_SGE_FLMC;
8989         else
8990                 ret = FW_LDST_ADDRSPC_SGE_CONMC;
8991
8992         memset(&c, 0, sizeof(c));
8993         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
8994                                         F_FW_CMD_REQUEST | F_FW_CMD_READ |
8995                                         V_FW_LDST_CMD_ADDRSPACE(ret));
8996         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
8997         c.u.idctxt.physid = cpu_to_be32(cid);
8998
8999         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9000         if (ret == 0) {
9001                 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9002                 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9003                 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9004                 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9005                 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9006                 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9007         }
9008         return ret;
9009 }
9010
9011 /**
9012  *      t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9013  *      @adap: the adapter
9014  *      @cid: the context id
9015  *      @ctype: the context type
9016  *      @data: where to store the context data
9017  *
9018  *      Reads an SGE context directly, bypassing FW.  This is only for
9019  *      debugging when FW is unavailable.
9020  */
9021 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
9022                       u32 *data)
9023 {
9024         int i, ret;
9025
9026         t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
9027         ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
9028         if (!ret)
9029                 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
9030                         *data++ = t4_read_reg(adap, i);
9031         return ret;
9032 }
9033
9034 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
9035                     int sleep_ok)
9036 {
9037         struct fw_sched_cmd cmd;
9038
9039         memset(&cmd, 0, sizeof(cmd));
9040         cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9041                                       F_FW_CMD_REQUEST |
9042                                       F_FW_CMD_WRITE);
9043         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9044
9045         cmd.u.config.sc = FW_SCHED_SC_CONFIG;
9046         cmd.u.config.type = type;
9047         cmd.u.config.minmaxen = minmaxen;
9048
9049         return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9050                                NULL, sleep_ok);
9051 }
9052
9053 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9054                     int rateunit, int ratemode, int channel, int cl,
9055                     int minrate, int maxrate, int weight, int pktsize,
9056                     int sleep_ok)
9057 {
9058         struct fw_sched_cmd cmd;
9059
9060         memset(&cmd, 0, sizeof(cmd));
9061         cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9062                                       F_FW_CMD_REQUEST |
9063                                       F_FW_CMD_WRITE);
9064         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9065
9066         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9067         cmd.u.params.type = type;
9068         cmd.u.params.level = level;
9069         cmd.u.params.mode = mode;
9070         cmd.u.params.ch = channel;
9071         cmd.u.params.cl = cl;
9072         cmd.u.params.unit = rateunit;
9073         cmd.u.params.rate = ratemode;
9074         cmd.u.params.min = cpu_to_be32(minrate);
9075         cmd.u.params.max = cpu_to_be32(maxrate);
9076         cmd.u.params.weight = cpu_to_be16(weight);
9077         cmd.u.params.pktsize = cpu_to_be16(pktsize);
9078
9079         return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9080                                NULL, sleep_ok);
9081 }
9082
9083 /*
9084  *      t4_config_watchdog - configure (enable/disable) a watchdog timer
9085  *      @adapter: the adapter
9086  *      @mbox: mailbox to use for the FW command
9087  *      @pf: the PF owning the queue
9088  *      @vf: the VF owning the queue
9089  *      @timeout: watchdog timeout in ms
9090  *      @action: watchdog timer / action
9091  *
9092  *      There are separate watchdog timers for each possible watchdog
9093  *      action.  Configure one of the watchdog timers by setting a non-zero
9094  *      timeout.  Disable a watchdog timer by using a timeout of zero.
9095  */
9096 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
9097                        unsigned int pf, unsigned int vf,
9098                        unsigned int timeout, unsigned int action)
9099 {
9100         struct fw_watchdog_cmd wdog;
9101         unsigned int ticks;
9102
9103         /*
9104          * The watchdog command expects a timeout in units of 10ms so we need
9105          * to convert it here (via rounding) and force a minimum of one 10ms
9106          * "tick" if the timeout is non-zero but the convertion results in 0
9107          * ticks.
9108          */
9109         ticks = (timeout + 5)/10;
9110         if (timeout && !ticks)
9111                 ticks = 1;
9112
9113         memset(&wdog, 0, sizeof wdog);
9114         wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
9115                                      F_FW_CMD_REQUEST |
9116                                      F_FW_CMD_WRITE |
9117                                      V_FW_PARAMS_CMD_PFN(pf) |
9118                                      V_FW_PARAMS_CMD_VFN(vf));
9119         wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
9120         wdog.timeout = cpu_to_be32(ticks);
9121         wdog.action = cpu_to_be32(action);
9122
9123         return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
9124 }
9125
9126 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
9127 {
9128         struct fw_devlog_cmd devlog_cmd;
9129         int ret;
9130
9131         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9132         devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9133                                              F_FW_CMD_REQUEST | F_FW_CMD_READ);
9134         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9135         ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9136                          sizeof(devlog_cmd), &devlog_cmd);
9137         if (ret)
9138                 return ret;
9139
9140         *level = devlog_cmd.level;
9141         return 0;
9142 }
9143
9144 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
9145 {
9146         struct fw_devlog_cmd devlog_cmd;
9147
9148         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9149         devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9150                                              F_FW_CMD_REQUEST |
9151                                              F_FW_CMD_WRITE);
9152         devlog_cmd.level = level;
9153         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9154         return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9155                           sizeof(devlog_cmd), &devlog_cmd);
9156 }