sys/dev/cxgbe/common/t4_hw.c

   1 /*-
   2  * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include "opt_inet.h"
  31
  32 #include "common.h"
  33 #include "t4_regs.h"
  34 #include "t4_regs_values.h"
  35 #include "firmware/t4fw_interface.h"
  36
  37 #undef msleep
  38 #define msleep(x) do { \
  39         if (cold) \
  40                 DELAY((x) * 1000); \
  41         else \
  42                 pause("t4hw", (x) * hz / 1000); \
  43 } while (0)
  44
  45 /**
  46  *      t4_wait_op_done_val - wait until an operation is completed
  47  *      @adapter: the adapter performing the operation
  48  *      @reg: the register to check for completion
  49  *      @mask: a single-bit field within @reg that indicates completion
  50  *      @polarity: the value of the field when the operation is completed
  51  *      @attempts: number of check iterations
  52  *      @delay: delay in usecs between iterations
  53  *      @valp: where to store the value of the register at completion time
  54  *
  55  *      Wait until an operation is completed by checking a bit in a register
  56  *      up to @attempts times.  If @valp is not NULL the value of the register
  57  *      at the time it indicated completion is stored there.  Returns 0 if the
  58  *      operation completes and -EAGAIN otherwise.
  59  */
  60 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  61                                int polarity, int attempts, int delay, u32 *valp)
  62 {
  63         while (1) {
  64                 u32 val = t4_read_reg(adapter, reg);
  65
  66                 if (!!(val & mask) == polarity) {
  67                         if (valp)
  68                                 *valp = val;
  69                         return 0;
  70                 }
  71                 if (--attempts == 0)
  72                         return -EAGAIN;
  73                 if (delay)
  74                         udelay(delay);
  75         }
  76 }
  77
  78 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  79                                   int polarity, int attempts, int delay)
  80 {
  81         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  82                                    delay, NULL);
  83 }
  84
  85 /**
  86  *      t4_set_reg_field - set a register field to a value
  87  *      @adapter: the adapter to program
  88  *      @addr: the register address
  89  *      @mask: specifies the portion of the register to modify
  90  *      @val: the new value for the register field
  91  *
  92  *      Sets a register field specified by the supplied mask to the
  93  *      given value.
  94  */
  95 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  96                       u32 val)
  97 {
  98         u32 v = t4_read_reg(adapter, addr) & ~mask;
  99
 100         t4_write_reg(adapter, addr, v | val);
 101         (void) t4_read_reg(adapter, addr);      /* flush */
 102 }
 103
 104 /**
 105  *      t4_read_indirect - read indirectly addressed registers
 106  *      @adap: the adapter
 107  *      @addr_reg: register holding the indirect address
 108  *      @data_reg: register holding the value of the indirect register
 109  *      @vals: where the read register values are stored
 110  *      @nregs: how many indirect registers to read
 111  *      @start_idx: index of first indirect register to read
 112  *
 113  *      Reads registers that are accessed indirectly through an address/data
 114  *      register pair.
 115  */
 116 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 117                              unsigned int data_reg, u32 *vals,
 118                              unsigned int nregs, unsigned int start_idx)
 119 {
 120         while (nregs--) {
 121                 t4_write_reg(adap, addr_reg, start_idx);
 122                 *vals++ = t4_read_reg(adap, data_reg);
 123                 start_idx++;
 124         }
 125 }
 126
 127 /**
 128  *      t4_write_indirect - write indirectly addressed registers
 129  *      @adap: the adapter
 130  *      @addr_reg: register holding the indirect addresses
 131  *      @data_reg: register holding the value for the indirect registers
 132  *      @vals: values to write
 133  *      @nregs: how many indirect registers to write
 134  *      @start_idx: address of first indirect register to write
 135  *
 136  *      Writes a sequential block of registers that are accessed indirectly
 137  *      through an address/data register pair.
 138  */
 139 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 140                        unsigned int data_reg, const u32 *vals,
 141                        unsigned int nregs, unsigned int start_idx)
 142 {
 143         while (nregs--) {
 144                 t4_write_reg(adap, addr_reg, start_idx++);
 145                 t4_write_reg(adap, data_reg, *vals++);
 146         }
 147 }
 148
 149 /*
 150  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 151  * mechanism.  This guarantees that we get the real value even if we're
 152  * operating within a Virtual Machine and the Hypervisor is trapping our
 153  * Configuration Space accesses.
 154  *
 155  * N.B. This routine should only be used as a last resort: the firmware uses
 156  *      the backdoor registers on a regular basis and we can end up
 157  *      conflicting with it's uses!
 158  */
 159 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
 160 {
 161         u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
 162         u32 val;
 163
 164         if (chip_id(adap) <= CHELSIO_T5)
 165                 req |= F_ENABLE;
 166         else
 167                 req |= F_T6_ENABLE;
 168
 169         if (is_t4(adap))
 170                 req |= F_LOCALCFG;
 171
 172         t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
 173         val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
 174
 175         /*
 176          * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 177          * Configuration Space read.  (None of the other fields matter when
 178          * F_ENABLE is 0 so a simple register write is easier than a
 179          * read-modify-write via t4_set_reg_field().)
 180          */
 181         t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
 182
 183         return val;
 184 }
 185
 186 /*
 187  * t4_report_fw_error - report firmware error
 188  * @adap: the adapter
 189  *
 190  * The adapter firmware can indicate error conditions to the host.
 191  * If the firmware has indicated an error, print out the reason for
 192  * the firmware error.
 193  */
 194 static void t4_report_fw_error(struct adapter *adap)
 195 {
 196         static const char *const reason[] = {
 197                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 198                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 199                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 200                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 201                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 202                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 203                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 204                 "Reserved",                     /* reserved */
 205         };
 206         u32 pcie_fw;
 207
 208         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 209         if (pcie_fw & F_PCIE_FW_ERR)
 210                 CH_ERR(adap, "Firmware reports adapter error: %s\n",
 211                         reason[G_PCIE_FW_EVAL(pcie_fw)]);
 212 }
 213
 214 /*
 215  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 216  */
 217 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 218                          u32 mbox_addr)
 219 {
 220         for ( ; nflit; nflit--, mbox_addr += 8)
 221                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 222 }
 223
 224 /*
 225  * Handle a FW assertion reported in a mailbox.
 226  */
 227 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
 228 {
 229         CH_ALERT(adap,
 230                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 231                   asrt->u.assert.filename_0_7,
 232                   be32_to_cpu(asrt->u.assert.line),
 233                   be32_to_cpu(asrt->u.assert.x),
 234                   be32_to_cpu(asrt->u.assert.y));
 235 }
 236
 237 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 238 /**
 239  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 240  *      @adap: the adapter
 241  *      @mbox: index of the mailbox to use
 242  *      @cmd: the command to write
 243  *      @size: command length in bytes
 244  *      @rpl: where to optionally store the reply
 245  *      @sleep_ok: if true we may sleep while awaiting command completion
 246  *      @timeout: time to wait for command to finish before timing out
 247  *              (negative implies @sleep_ok=false)
 248  *
 249  *      Sends the given command to FW through the selected mailbox and waits
 250  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 251  *      store the FW's reply to the command.  The command and its optional
 252  *      reply are of the same length.  Some FW commands like RESET and
 253  *      INITIALIZE can take a considerable amount of time to execute.
 254  *      @sleep_ok determines whether we may sleep while awaiting the response.
 255  *      If sleeping is allowed we use progressive backoff otherwise we spin.
 256  *      Note that passing in a negative @timeout is an alternate mechanism
 257  *      for specifying @sleep_ok=false.  This is useful when a higher level
 258  *      interface allows for specification of @timeout but not @sleep_ok ...
 259  *
 260  *      The return value is 0 on success or a negative errno on failure.  A
 261  *      failure can happen either because we are not able to execute the
 262  *      command or FW executes it but signals an error.  In the latter case
 263  *      the return value is the error code indicated by FW (negated).
 264  */
 265 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 266                             int size, void *rpl, bool sleep_ok, int timeout)
 267 {
 268         /*
 269          * We delay in small increments at first in an effort to maintain
 270          * responsiveness for simple, fast executing commands but then back
 271          * off to larger delays to a maximum retry delay.
 272          */
 273         static const int delay[] = {
 274                 1, 1, 3, 5, 10, 10, 20, 50, 100
 275         };
 276         u32 v;
 277         u64 res;
 278         int i, ms, delay_idx, ret;
 279         const __be64 *p = cmd;
 280         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 281         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 282         u32 ctl;
 283         __be64 cmd_rpl[MBOX_LEN/8];
 284         u32 pcie_fw;
 285
 286         if ((size & 15) || size > MBOX_LEN)
 287                 return -EINVAL;
 288
 289         if (adap->flags & IS_VF) {
 290                 if (is_t6(adap))
 291                         data_reg = FW_T6VF_MBDATA_BASE_ADDR;
 292                 else
 293                         data_reg = FW_T4VF_MBDATA_BASE_ADDR;
 294                 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
 295         }
 296
 297         /*
 298          * If we have a negative timeout, that implies that we can't sleep.
 299          */
 300         if (timeout < 0) {
 301                 sleep_ok = false;
 302                 timeout = -timeout;
 303         }
 304
 305         /*
 306          * Attempt to gain access to the mailbox.
 307          */
 308         for (i = 0; i < 4; i++) {
 309                 ctl = t4_read_reg(adap, ctl_reg);
 310                 v = G_MBOWNER(ctl);
 311                 if (v != X_MBOWNER_NONE)
 312                         break;
 313         }
 314
 315         /*
 316          * If we were unable to gain access, dequeue ourselves from the
 317          * mailbox atomic access list and report the error to our caller.
 318          */
 319         if (v != X_MBOWNER_PL) {
 320                 t4_report_fw_error(adap);
 321                 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
 322                 return ret;
 323         }
 324
 325         /*
 326          * If we gain ownership of the mailbox and there's a "valid" message
 327          * in it, this is likely an asynchronous error message from the
 328          * firmware.  So we'll report that and then proceed on with attempting
 329          * to issue our own command ... which may well fail if the error
 330          * presaged the firmware crashing ...
 331          */
 332         if (ctl & F_MBMSGVALID) {
 333                 CH_ERR(adap, "found VALID command in mbox %u: "
 334                        "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 335                        (unsigned long long)t4_read_reg64(adap, data_reg),
 336                        (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 337                        (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 338                        (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 339                        (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 340                        (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 341                        (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 342                        (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 343         }
 344
 345         /*
 346          * Copy in the new mailbox command and send it on its way ...
 347          */
 348         for (i = 0; i < size; i += 8, p++)
 349                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 350
 351         if (adap->flags & IS_VF) {
 352                 /*
 353                  * For the VFs, the Mailbox Data "registers" are
 354                  * actually backed by T4's "MA" interface rather than
 355                  * PL Registers (as is the case for the PFs).  Because
 356                  * these are in different coherency domains, the write
 357                  * to the VF's PL-register-backed Mailbox Control can
 358                  * race in front of the writes to the MA-backed VF
 359                  * Mailbox Data "registers".  So we need to do a
 360                  * read-back on at least one byte of the VF Mailbox
 361                  * Data registers before doing the write to the VF
 362                  * Mailbox Control register.
 363                  */
 364                 t4_read_reg(adap, data_reg);
 365         }
 366
 367         CH_DUMP_MBOX(adap, mbox, data_reg);
 368
 369         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 370         t4_read_reg(adap, ctl_reg);     /* flush write */
 371
 372         delay_idx = 0;
 373         ms = delay[0];
 374
 375         /*
 376          * Loop waiting for the reply; bail out if we time out or the firmware
 377          * reports an error.
 378          */
 379         pcie_fw = 0;
 380         for (i = 0; i < timeout; i += ms) {
 381                 if (!(adap->flags & IS_VF)) {
 382                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 383                         if (pcie_fw & F_PCIE_FW_ERR)
 384                                 break;
 385                 }
 386                 if (sleep_ok) {
 387                         ms = delay[delay_idx];  /* last element may repeat */
 388                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 389                                 delay_idx++;
 390                         msleep(ms);
 391                 } else {
 392                         mdelay(ms);
 393                 }
 394
 395                 v = t4_read_reg(adap, ctl_reg);
 396                 if (v == X_CIM_PF_NOACCESS)
 397                         continue;
 398                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 399                         if (!(v & F_MBMSGVALID)) {
 400                                 t4_write_reg(adap, ctl_reg,
 401                                              V_MBOWNER(X_MBOWNER_NONE));
 402                                 continue;
 403                         }
 404
 405                         /*
 406                          * Retrieve the command reply and release the mailbox.
 407                          */
 408                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
 409                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 410
 411                         CH_DUMP_MBOX(adap, mbox, data_reg);
 412
 413                         res = be64_to_cpu(cmd_rpl[0]);
 414                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 415                                 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
 416                                 res = V_FW_CMD_RETVAL(EIO);
 417                         } else if (rpl)
 418                                 memcpy(rpl, cmd_rpl, size);
 419                         return -G_FW_CMD_RETVAL((int)res);
 420                 }
 421         }
 422
 423         /*
 424          * We timed out waiting for a reply to our mailbox command.  Report
 425          * the error and also check to see if the firmware reported any
 426          * errors ...
 427          */
 428         ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 429         CH_ERR(adap, "command %#x in mailbox %d timed out\n",
 430                *(const u8 *)cmd, mbox);
 431
 432         /* If DUMP_MBOX is set the mbox has already been dumped */
 433         if ((adap->debug_flags & DF_DUMP_MBOX) == 0) {
 434                 p = cmd;
 435                 CH_ERR(adap, "mbox: %016llx %016llx %016llx %016llx "
 436                     "%016llx %016llx %016llx %016llx\n",
 437                     (unsigned long long)be64_to_cpu(p[0]),
 438                     (unsigned long long)be64_to_cpu(p[1]),
 439                     (unsigned long long)be64_to_cpu(p[2]),
 440                     (unsigned long long)be64_to_cpu(p[3]),
 441                     (unsigned long long)be64_to_cpu(p[4]),
 442                     (unsigned long long)be64_to_cpu(p[5]),
 443                     (unsigned long long)be64_to_cpu(p[6]),
 444                     (unsigned long long)be64_to_cpu(p[7]));
 445         }
 446
 447         t4_report_fw_error(adap);
 448         t4_fatal_err(adap);
 449         return ret;
 450 }
 451
 452 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 453                     void *rpl, bool sleep_ok)
 454 {
 455                 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
 456                                                sleep_ok, FW_CMD_MAX_TIMEOUT);
 457
 458 }
 459
 460 static int t4_edc_err_read(struct adapter *adap, int idx)
 461 {
 462         u32 edc_ecc_err_addr_reg;
 463         u32 edc_bist_status_rdata_reg;
 464
 465         if (is_t4(adap)) {
 466                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 467                 return 0;
 468         }
 469         if (idx != 0 && idx != 1) {
 470                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 471                 return 0;
 472         }
 473
 474         edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
 475         edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
 476
 477         CH_WARN(adap,
 478                 "edc%d err addr 0x%x: 0x%x.\n",
 479                 idx, edc_ecc_err_addr_reg,
 480                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 481         CH_WARN(adap,
 482                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 483                 edc_bist_status_rdata_reg,
 484                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
 485                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
 486                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
 487                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
 488                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
 489                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
 490                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
 491                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
 492                 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
 493
 494         return 0;
 495 }
 496
 497 /**
 498  *      t4_mc_read - read from MC through backdoor accesses
 499  *      @adap: the adapter
 500  *      @idx: which MC to access
 501  *      @addr: address of first byte requested
 502  *      @data: 64 bytes of data containing the requested address
 503  *      @ecc: where to store the corresponding 64-bit ECC word
 504  *
 505  *      Read 64 bytes of data from MC starting at a 64-byte-aligned address
 506  *      that covers the requested address @addr.  If @parity is not %NULL it
 507  *      is assigned the 64-bit ECC word for the read data.
 508  */
 509 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
 510 {
 511         int i;
 512         u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
 513         u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
 514
 515         if (is_t4(adap)) {
 516                 mc_bist_cmd_reg = A_MC_BIST_CMD;
 517                 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
 518                 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
 519                 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
 520                 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
 521         } else {
 522                 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
 523                 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
 524                 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
 525                 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
 526                                                   idx);
 527                 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
 528                                                   idx);
 529         }
 530
 531         if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
 532                 return -EBUSY;
 533         t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
 534         t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
 535         t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
 536         t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
 537                      F_START_BIST | V_BIST_CMD_GAP(1));
 538         i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
 539         if (i)
 540                 return i;
 541
 542 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
 543
 544         for (i = 15; i >= 0; i--)
 545                 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
 546         if (ecc)
 547                 *ecc = t4_read_reg64(adap, MC_DATA(16));
 548 #undef MC_DATA
 549         return 0;
 550 }
 551
 552 /**
 553  *      t4_edc_read - read from EDC through backdoor accesses
 554  *      @adap: the adapter
 555  *      @idx: which EDC to access
 556  *      @addr: address of first byte requested
 557  *      @data: 64 bytes of data containing the requested address
 558  *      @ecc: where to store the corresponding 64-bit ECC word
 559  *
 560  *      Read 64 bytes of data from EDC starting at a 64-byte-aligned address
 561  *      that covers the requested address @addr.  If @parity is not %NULL it
 562  *      is assigned the 64-bit ECC word for the read data.
 563  */
 564 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
 565 {
 566         int i;
 567         u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
 568         u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
 569
 570         if (is_t4(adap)) {
 571                 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
 572                 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
 573                 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
 574                 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
 575                                                     idx);
 576                 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
 577                                                     idx);
 578         } else {
 579 /*
 580  * These macro are missing in t4_regs.h file.
 581  * Added temporarily for testing.
 582  */
 583 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
 584 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
 585                 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
 586                 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
 587                 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
 588                 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
 589                                                     idx);
 590                 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
 591                                                     idx);
 592 #undef EDC_REG_T5
 593 #undef EDC_STRIDE_T5
 594         }
 595
 596         if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
 597                 return -EBUSY;
 598         t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
 599         t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
 600         t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
 601         t4_write_reg(adap, edc_bist_cmd_reg,
 602                      V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
 603         i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
 604         if (i)
 605                 return i;
 606
 607 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
 608
 609         for (i = 15; i >= 0; i--)
 610                 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
 611         if (ecc)
 612                 *ecc = t4_read_reg64(adap, EDC_DATA(16));
 613 #undef EDC_DATA
 614         return 0;
 615 }
 616
 617 /**
 618  *      t4_mem_read - read EDC 0, EDC 1 or MC into buffer
 619  *      @adap: the adapter
 620  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 621  *      @addr: address within indicated memory type
 622  *      @len: amount of memory to read
 623  *      @buf: host memory buffer
 624  *
 625  *      Reads an [almost] arbitrary memory region in the firmware: the
 626  *      firmware memory address, length and host buffer must be aligned on
 627  *      32-bit boudaries.  The memory is returned as a raw byte sequence from
 628  *      the firmware's memory.  If this memory contains data structures which
 629  *      contain multi-byte integers, it's the callers responsibility to
 630  *      perform appropriate byte order conversions.
 631  */
 632 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
 633                 __be32 *buf)
 634 {
 635         u32 pos, start, end, offset;
 636         int ret;
 637
 638         /*
 639          * Argument sanity checks ...
 640          */
 641         if ((addr & 0x3) || (len & 0x3))
 642                 return -EINVAL;
 643
 644         /*
 645          * The underlaying EDC/MC read routines read 64 bytes at a time so we
 646          * need to round down the start and round up the end.  We'll start
 647          * copying out of the first line at (addr - start) a word at a time.
 648          */
 649         start = addr & ~(64-1);
 650         end = (addr + len + 64-1) & ~(64-1);
 651         offset = (addr - start)/sizeof(__be32);
 652
 653         for (pos = start; pos < end; pos += 64, offset = 0) {
 654                 __be32 data[16];
 655
 656                 /*
 657                  * Read the chip's memory block and bail if there's an error.
 658                  */
 659                 if ((mtype == MEM_MC) || (mtype == MEM_MC1))
 660                         ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
 661                 else
 662                         ret = t4_edc_read(adap, mtype, pos, data, NULL);
 663                 if (ret)
 664                         return ret;
 665
 666                 /*
 667                  * Copy the data into the caller's memory buffer.
 668                  */
 669                 while (offset < 16 && len > 0) {
 670                         *buf++ = data[offset++];
 671                         len -= sizeof(__be32);
 672                 }
 673         }
 674
 675         return 0;
 676 }
 677
 678 /*
 679  * Return the specified PCI-E Configuration Space register from our Physical
 680  * Function.  We try first via a Firmware LDST Command (if fw_attach != 0)
 681  * since we prefer to let the firmware own all of these registers, but if that
 682  * fails we go for it directly ourselves.
 683  */
 684 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
 685 {
 686
 687         /*
 688          * If fw_attach != 0, construct and send the Firmware LDST Command to
 689          * retrieve the specified PCI-E Configuration Space register.
 690          */
 691         if (drv_fw_attach != 0) {
 692                 struct fw_ldst_cmd ldst_cmd;
 693                 int ret;
 694
 695                 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 696                 ldst_cmd.op_to_addrspace =
 697                         cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
 698                                     F_FW_CMD_REQUEST |
 699                                     F_FW_CMD_READ |
 700                                     V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
 701                 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 702                 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
 703                 ldst_cmd.u.pcie.ctrl_to_fn =
 704                         (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
 705                 ldst_cmd.u.pcie.r = reg;
 706
 707                 /*
 708                  * If the LDST Command succeeds, return the result, otherwise
 709                  * fall through to reading it directly ourselves ...
 710                  */
 711                 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 712                                  &ldst_cmd);
 713                 if (ret == 0)
 714                         return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 715
 716                 CH_WARN(adap, "Firmware failed to return "
 717                         "Configuration Space register %d, err = %d\n",
 718                         reg, -ret);
 719         }
 720
 721         /*
 722          * Read the desired Configuration Space register via the PCI-E
 723          * Backdoor mechanism.
 724          */
 725         return t4_hw_pci_read_cfg4(adap, reg);
 726 }
 727
 728 /**
 729  *      t4_get_regs_len - return the size of the chips register set
 730  *      @adapter: the adapter
 731  *
 732  *      Returns the size of the chip's BAR0 register space.
 733  */
 734 unsigned int t4_get_regs_len(struct adapter *adapter)
 735 {
 736         unsigned int chip_version = chip_id(adapter);
 737
 738         switch (chip_version) {
 739         case CHELSIO_T4:
 740                 if (adapter->flags & IS_VF)
 741                         return FW_T4VF_REGMAP_SIZE;
 742                 return T4_REGMAP_SIZE;
 743
 744         case CHELSIO_T5:
 745         case CHELSIO_T6:
 746                 if (adapter->flags & IS_VF)
 747                         return FW_T4VF_REGMAP_SIZE;
 748                 return T5_REGMAP_SIZE;
 749         }
 750
 751         CH_ERR(adapter,
 752                 "Unsupported chip version %d\n", chip_version);
 753         return 0;
 754 }
 755
 756 /**
 757  *      t4_get_regs - read chip registers into provided buffer
 758  *      @adap: the adapter
 759  *      @buf: register buffer
 760  *      @buf_size: size (in bytes) of register buffer
 761  *
 762  *      If the provided register buffer isn't large enough for the chip's
 763  *      full register range, the register dump will be truncated to the
 764  *      register buffer's size.
 765  */
 766 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
 767 {
 768         static const unsigned int t4_reg_ranges[] = {
 769                 0x1008, 0x1108,
 770                 0x1180, 0x1184,
 771                 0x1190, 0x1194,
 772                 0x11a0, 0x11a4,
 773                 0x11b0, 0x11b4,
 774                 0x11fc, 0x123c,
 775                 0x1300, 0x173c,
 776                 0x1800, 0x18fc,
 777                 0x3000, 0x30d8,
 778                 0x30e0, 0x30e4,
 779                 0x30ec, 0x5910,
 780                 0x5920, 0x5924,
 781                 0x5960, 0x5960,
 782                 0x5968, 0x5968,
 783                 0x5970, 0x5970,
 784                 0x5978, 0x5978,
 785                 0x5980, 0x5980,
 786                 0x5988, 0x5988,
 787                 0x5990, 0x5990,
 788                 0x5998, 0x5998,
 789                 0x59a0, 0x59d4,
 790                 0x5a00, 0x5ae0,
 791                 0x5ae8, 0x5ae8,
 792                 0x5af0, 0x5af0,
 793                 0x5af8, 0x5af8,
 794                 0x6000, 0x6098,
 795                 0x6100, 0x6150,
 796                 0x6200, 0x6208,
 797                 0x6240, 0x6248,
 798                 0x6280, 0x62b0,
 799                 0x62c0, 0x6338,
 800                 0x6370, 0x638c,
 801                 0x6400, 0x643c,
 802                 0x6500, 0x6524,
 803                 0x6a00, 0x6a04,
 804                 0x6a14, 0x6a38,
 805                 0x6a60, 0x6a70,
 806                 0x6a78, 0x6a78,
 807                 0x6b00, 0x6b0c,
 808                 0x6b1c, 0x6b84,
 809                 0x6bf0, 0x6bf8,
 810                 0x6c00, 0x6c0c,
 811                 0x6c1c, 0x6c84,
 812                 0x6cf0, 0x6cf8,
 813                 0x6d00, 0x6d0c,
 814                 0x6d1c, 0x6d84,
 815                 0x6df0, 0x6df8,
 816                 0x6e00, 0x6e0c,
 817                 0x6e1c, 0x6e84,
 818                 0x6ef0, 0x6ef8,
 819                 0x6f00, 0x6f0c,
 820                 0x6f1c, 0x6f84,
 821                 0x6ff0, 0x6ff8,
 822                 0x7000, 0x700c,
 823                 0x701c, 0x7084,
 824                 0x70f0, 0x70f8,
 825                 0x7100, 0x710c,
 826                 0x711c, 0x7184,
 827                 0x71f0, 0x71f8,
 828                 0x7200, 0x720c,
 829                 0x721c, 0x7284,
 830                 0x72f0, 0x72f8,
 831                 0x7300, 0x730c,
 832                 0x731c, 0x7384,
 833                 0x73f0, 0x73f8,
 834                 0x7400, 0x7450,
 835                 0x7500, 0x7530,
 836                 0x7600, 0x760c,
 837                 0x7614, 0x761c,
 838                 0x7680, 0x76cc,
 839                 0x7700, 0x7798,
 840                 0x77c0, 0x77fc,
 841                 0x7900, 0x79fc,
 842                 0x7b00, 0x7b58,
 843                 0x7b60, 0x7b84,
 844                 0x7b8c, 0x7c38,
 845                 0x7d00, 0x7d38,
 846                 0x7d40, 0x7d80,
 847                 0x7d8c, 0x7ddc,
 848                 0x7de4, 0x7e04,
 849                 0x7e10, 0x7e1c,
 850                 0x7e24, 0x7e38,
 851                 0x7e40, 0x7e44,
 852                 0x7e4c, 0x7e78,
 853                 0x7e80, 0x7ea4,
 854                 0x7eac, 0x7edc,
 855                 0x7ee8, 0x7efc,
 856                 0x8dc0, 0x8e04,
 857                 0x8e10, 0x8e1c,
 858                 0x8e30, 0x8e78,
 859                 0x8ea0, 0x8eb8,
 860                 0x8ec0, 0x8f6c,
 861                 0x8fc0, 0x9008,
 862                 0x9010, 0x9058,
 863                 0x9060, 0x9060,
 864                 0x9068, 0x9074,
 865                 0x90fc, 0x90fc,
 866                 0x9400, 0x9408,
 867                 0x9410, 0x9458,
 868                 0x9600, 0x9600,
 869                 0x9608, 0x9638,
 870                 0x9640, 0x96bc,
 871                 0x9800, 0x9808,
 872                 0x9820, 0x983c,
 873                 0x9850, 0x9864,
 874                 0x9c00, 0x9c6c,
 875                 0x9c80, 0x9cec,
 876                 0x9d00, 0x9d6c,
 877                 0x9d80, 0x9dec,
 878                 0x9e00, 0x9e6c,
 879                 0x9e80, 0x9eec,
 880                 0x9f00, 0x9f6c,
 881                 0x9f80, 0x9fec,
 882                 0xd004, 0xd004,
 883                 0xd010, 0xd03c,
 884                 0xdfc0, 0xdfe0,
 885                 0xe000, 0xea7c,
 886                 0xf000, 0x11190,
 887                 0x19040, 0x1906c,
 888                 0x19078, 0x19080,
 889                 0x1908c, 0x190e4,
 890                 0x190f0, 0x190f8,
 891                 0x19100, 0x19110,
 892                 0x19120, 0x19124,
 893                 0x19150, 0x19194,
 894                 0x1919c, 0x191b0,
 895                 0x191d0, 0x191e8,
 896                 0x19238, 0x1924c,
 897                 0x193f8, 0x1943c,
 898                 0x1944c, 0x19474,
 899                 0x19490, 0x194e0,
 900                 0x194f0, 0x194f8,
 901                 0x19800, 0x19c08,
 902                 0x19c10, 0x19c90,
 903                 0x19ca0, 0x19ce4,
 904                 0x19cf0, 0x19d40,
 905                 0x19d50, 0x19d94,
 906                 0x19da0, 0x19de8,
 907                 0x19df0, 0x19e40,
 908                 0x19e50, 0x19e90,
 909                 0x19ea0, 0x19f4c,
 910                 0x1a000, 0x1a004,
 911                 0x1a010, 0x1a06c,
 912                 0x1a0b0, 0x1a0e4,
 913                 0x1a0ec, 0x1a0f4,
 914                 0x1a100, 0x1a108,
 915                 0x1a114, 0x1a120,
 916                 0x1a128, 0x1a130,
 917                 0x1a138, 0x1a138,
 918                 0x1a190, 0x1a1c4,
 919                 0x1a1fc, 0x1a1fc,
 920                 0x1e040, 0x1e04c,
 921                 0x1e284, 0x1e28c,
 922                 0x1e2c0, 0x1e2c0,
 923                 0x1e2e0, 0x1e2e0,
 924                 0x1e300, 0x1e384,
 925                 0x1e3c0, 0x1e3c8,
 926                 0x1e440, 0x1e44c,
 927                 0x1e684, 0x1e68c,
 928                 0x1e6c0, 0x1e6c0,
 929                 0x1e6e0, 0x1e6e0,
 930                 0x1e700, 0x1e784,
 931                 0x1e7c0, 0x1e7c8,
 932                 0x1e840, 0x1e84c,
 933                 0x1ea84, 0x1ea8c,
 934                 0x1eac0, 0x1eac0,
 935                 0x1eae0, 0x1eae0,
 936                 0x1eb00, 0x1eb84,
 937                 0x1ebc0, 0x1ebc8,
 938                 0x1ec40, 0x1ec4c,
 939                 0x1ee84, 0x1ee8c,
 940                 0x1eec0, 0x1eec0,
 941                 0x1eee0, 0x1eee0,
 942                 0x1ef00, 0x1ef84,
 943                 0x1efc0, 0x1efc8,
 944                 0x1f040, 0x1f04c,
 945                 0x1f284, 0x1f28c,
 946                 0x1f2c0, 0x1f2c0,
 947                 0x1f2e0, 0x1f2e0,
 948                 0x1f300, 0x1f384,
 949                 0x1f3c0, 0x1f3c8,
 950                 0x1f440, 0x1f44c,
 951                 0x1f684, 0x1f68c,
 952                 0x1f6c0, 0x1f6c0,
 953                 0x1f6e0, 0x1f6e0,
 954                 0x1f700, 0x1f784,
 955                 0x1f7c0, 0x1f7c8,
 956                 0x1f840, 0x1f84c,
 957                 0x1fa84, 0x1fa8c,
 958                 0x1fac0, 0x1fac0,
 959                 0x1fae0, 0x1fae0,
 960                 0x1fb00, 0x1fb84,
 961                 0x1fbc0, 0x1fbc8,
 962                 0x1fc40, 0x1fc4c,
 963                 0x1fe84, 0x1fe8c,
 964                 0x1fec0, 0x1fec0,
 965                 0x1fee0, 0x1fee0,
 966                 0x1ff00, 0x1ff84,
 967                 0x1ffc0, 0x1ffc8,
 968                 0x20000, 0x2002c,
 969                 0x20100, 0x2013c,
 970                 0x20190, 0x201a0,
 971                 0x201a8, 0x201b8,
 972                 0x201c4, 0x201c8,
 973                 0x20200, 0x20318,
 974                 0x20400, 0x204b4,
 975                 0x204c0, 0x20528,
 976                 0x20540, 0x20614,
 977                 0x21000, 0x21040,
 978                 0x2104c, 0x21060,
 979                 0x210c0, 0x210ec,
 980                 0x21200, 0x21268,
 981                 0x21270, 0x21284,
 982                 0x212fc, 0x21388,
 983                 0x21400, 0x21404,
 984                 0x21500, 0x21500,
 985                 0x21510, 0x21518,
 986                 0x2152c, 0x21530,
 987                 0x2153c, 0x2153c,
 988                 0x21550, 0x21554,
 989                 0x21600, 0x21600,
 990                 0x21608, 0x2161c,
 991                 0x21624, 0x21628,
 992                 0x21630, 0x21634,
 993                 0x2163c, 0x2163c,
 994                 0x21700, 0x2171c,
 995                 0x21780, 0x2178c,
 996                 0x21800, 0x21818,
 997                 0x21820, 0x21828,
 998                 0x21830, 0x21848,
 999                 0x21850, 0x21854,
1000                 0x21860, 0x21868,
1001                 0x21870, 0x21870,
1002                 0x21878, 0x21898,
1003                 0x218a0, 0x218a8,
1004                 0x218b0, 0x218c8,
1005                 0x218d0, 0x218d4,
1006                 0x218e0, 0x218e8,
1007                 0x218f0, 0x218f0,
1008                 0x218f8, 0x21a18,
1009                 0x21a20, 0x21a28,
1010                 0x21a30, 0x21a48,
1011                 0x21a50, 0x21a54,
1012                 0x21a60, 0x21a68,
1013                 0x21a70, 0x21a70,
1014                 0x21a78, 0x21a98,
1015                 0x21aa0, 0x21aa8,
1016                 0x21ab0, 0x21ac8,
1017                 0x21ad0, 0x21ad4,
1018                 0x21ae0, 0x21ae8,
1019                 0x21af0, 0x21af0,
1020                 0x21af8, 0x21c18,
1021                 0x21c20, 0x21c20,
1022                 0x21c28, 0x21c30,
1023                 0x21c38, 0x21c38,
1024                 0x21c80, 0x21c98,
1025                 0x21ca0, 0x21ca8,
1026                 0x21cb0, 0x21cc8,
1027                 0x21cd0, 0x21cd4,
1028                 0x21ce0, 0x21ce8,
1029                 0x21cf0, 0x21cf0,
1030                 0x21cf8, 0x21d7c,
1031                 0x21e00, 0x21e04,
1032                 0x22000, 0x2202c,
1033                 0x22100, 0x2213c,
1034                 0x22190, 0x221a0,
1035                 0x221a8, 0x221b8,
1036                 0x221c4, 0x221c8,
1037                 0x22200, 0x22318,
1038                 0x22400, 0x224b4,
1039                 0x224c0, 0x22528,
1040                 0x22540, 0x22614,
1041                 0x23000, 0x23040,
1042                 0x2304c, 0x23060,
1043                 0x230c0, 0x230ec,
1044                 0x23200, 0x23268,
1045                 0x23270, 0x23284,
1046                 0x232fc, 0x23388,
1047                 0x23400, 0x23404,
1048                 0x23500, 0x23500,
1049                 0x23510, 0x23518,
1050                 0x2352c, 0x23530,
1051                 0x2353c, 0x2353c,
1052                 0x23550, 0x23554,
1053                 0x23600, 0x23600,
1054                 0x23608, 0x2361c,
1055                 0x23624, 0x23628,
1056                 0x23630, 0x23634,
1057                 0x2363c, 0x2363c,
1058                 0x23700, 0x2371c,
1059                 0x23780, 0x2378c,
1060                 0x23800, 0x23818,
1061                 0x23820, 0x23828,
1062                 0x23830, 0x23848,
1063                 0x23850, 0x23854,
1064                 0x23860, 0x23868,
1065                 0x23870, 0x23870,
1066                 0x23878, 0x23898,
1067                 0x238a0, 0x238a8,
1068                 0x238b0, 0x238c8,
1069                 0x238d0, 0x238d4,
1070                 0x238e0, 0x238e8,
1071                 0x238f0, 0x238f0,
1072                 0x238f8, 0x23a18,
1073                 0x23a20, 0x23a28,
1074                 0x23a30, 0x23a48,
1075                 0x23a50, 0x23a54,
1076                 0x23a60, 0x23a68,
1077                 0x23a70, 0x23a70,
1078                 0x23a78, 0x23a98,
1079                 0x23aa0, 0x23aa8,
1080                 0x23ab0, 0x23ac8,
1081                 0x23ad0, 0x23ad4,
1082                 0x23ae0, 0x23ae8,
1083                 0x23af0, 0x23af0,
1084                 0x23af8, 0x23c18,
1085                 0x23c20, 0x23c20,
1086                 0x23c28, 0x23c30,
1087                 0x23c38, 0x23c38,
1088                 0x23c80, 0x23c98,
1089                 0x23ca0, 0x23ca8,
1090                 0x23cb0, 0x23cc8,
1091                 0x23cd0, 0x23cd4,
1092                 0x23ce0, 0x23ce8,
1093                 0x23cf0, 0x23cf0,
1094                 0x23cf8, 0x23d7c,
1095                 0x23e00, 0x23e04,
1096                 0x24000, 0x2402c,
1097                 0x24100, 0x2413c,
1098                 0x24190, 0x241a0,
1099                 0x241a8, 0x241b8,
1100                 0x241c4, 0x241c8,
1101                 0x24200, 0x24318,
1102                 0x24400, 0x244b4,
1103                 0x244c0, 0x24528,
1104                 0x24540, 0x24614,
1105                 0x25000, 0x25040,
1106                 0x2504c, 0x25060,
1107                 0x250c0, 0x250ec,
1108                 0x25200, 0x25268,
1109                 0x25270, 0x25284,
1110                 0x252fc, 0x25388,
1111                 0x25400, 0x25404,
1112                 0x25500, 0x25500,
1113                 0x25510, 0x25518,
1114                 0x2552c, 0x25530,
1115                 0x2553c, 0x2553c,
1116                 0x25550, 0x25554,
1117                 0x25600, 0x25600,
1118                 0x25608, 0x2561c,
1119                 0x25624, 0x25628,
1120                 0x25630, 0x25634,
1121                 0x2563c, 0x2563c,
1122                 0x25700, 0x2571c,
1123                 0x25780, 0x2578c,
1124                 0x25800, 0x25818,
1125                 0x25820, 0x25828,
1126                 0x25830, 0x25848,
1127                 0x25850, 0x25854,
1128                 0x25860, 0x25868,
1129                 0x25870, 0x25870,
1130                 0x25878, 0x25898,
1131                 0x258a0, 0x258a8,
1132                 0x258b0, 0x258c8,
1133                 0x258d0, 0x258d4,
1134                 0x258e0, 0x258e8,
1135                 0x258f0, 0x258f0,
1136                 0x258f8, 0x25a18,
1137                 0x25a20, 0x25a28,
1138                 0x25a30, 0x25a48,
1139                 0x25a50, 0x25a54,
1140                 0x25a60, 0x25a68,
1141                 0x25a70, 0x25a70,
1142                 0x25a78, 0x25a98,
1143                 0x25aa0, 0x25aa8,
1144                 0x25ab0, 0x25ac8,
1145                 0x25ad0, 0x25ad4,
1146                 0x25ae0, 0x25ae8,
1147                 0x25af0, 0x25af0,
1148                 0x25af8, 0x25c18,
1149                 0x25c20, 0x25c20,
1150                 0x25c28, 0x25c30,
1151                 0x25c38, 0x25c38,
1152                 0x25c80, 0x25c98,
1153                 0x25ca0, 0x25ca8,
1154                 0x25cb0, 0x25cc8,
1155                 0x25cd0, 0x25cd4,
1156                 0x25ce0, 0x25ce8,
1157                 0x25cf0, 0x25cf0,
1158                 0x25cf8, 0x25d7c,
1159                 0x25e00, 0x25e04,
1160                 0x26000, 0x2602c,
1161                 0x26100, 0x2613c,
1162                 0x26190, 0x261a0,
1163                 0x261a8, 0x261b8,
1164                 0x261c4, 0x261c8,
1165                 0x26200, 0x26318,
1166                 0x26400, 0x264b4,
1167                 0x264c0, 0x26528,
1168                 0x26540, 0x26614,
1169                 0x27000, 0x27040,
1170                 0x2704c, 0x27060,
1171                 0x270c0, 0x270ec,
1172                 0x27200, 0x27268,
1173                 0x27270, 0x27284,
1174                 0x272fc, 0x27388,
1175                 0x27400, 0x27404,
1176                 0x27500, 0x27500,
1177                 0x27510, 0x27518,
1178                 0x2752c, 0x27530,
1179                 0x2753c, 0x2753c,
1180                 0x27550, 0x27554,
1181                 0x27600, 0x27600,
1182                 0x27608, 0x2761c,
1183                 0x27624, 0x27628,
1184                 0x27630, 0x27634,
1185                 0x2763c, 0x2763c,
1186                 0x27700, 0x2771c,
1187                 0x27780, 0x2778c,
1188                 0x27800, 0x27818,
1189                 0x27820, 0x27828,
1190                 0x27830, 0x27848,
1191                 0x27850, 0x27854,
1192                 0x27860, 0x27868,
1193                 0x27870, 0x27870,
1194                 0x27878, 0x27898,
1195                 0x278a0, 0x278a8,
1196                 0x278b0, 0x278c8,
1197                 0x278d0, 0x278d4,
1198                 0x278e0, 0x278e8,
1199                 0x278f0, 0x278f0,
1200                 0x278f8, 0x27a18,
1201                 0x27a20, 0x27a28,
1202                 0x27a30, 0x27a48,
1203                 0x27a50, 0x27a54,
1204                 0x27a60, 0x27a68,
1205                 0x27a70, 0x27a70,
1206                 0x27a78, 0x27a98,
1207                 0x27aa0, 0x27aa8,
1208                 0x27ab0, 0x27ac8,
1209                 0x27ad0, 0x27ad4,
1210                 0x27ae0, 0x27ae8,
1211                 0x27af0, 0x27af0,
1212                 0x27af8, 0x27c18,
1213                 0x27c20, 0x27c20,
1214                 0x27c28, 0x27c30,
1215                 0x27c38, 0x27c38,
1216                 0x27c80, 0x27c98,
1217                 0x27ca0, 0x27ca8,
1218                 0x27cb0, 0x27cc8,
1219                 0x27cd0, 0x27cd4,
1220                 0x27ce0, 0x27ce8,
1221                 0x27cf0, 0x27cf0,
1222                 0x27cf8, 0x27d7c,
1223                 0x27e00, 0x27e04,
1224         };
1225
1226         static const unsigned int t4vf_reg_ranges[] = {
1227                 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1228                 VF_MPS_REG(A_MPS_VF_CTL),
1229                 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1230                 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1231                 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1232                 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1233                 FW_T4VF_MBDATA_BASE_ADDR,
1234                 FW_T4VF_MBDATA_BASE_ADDR +
1235                 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1236         };
1237
1238         static const unsigned int t5_reg_ranges[] = {
1239                 0x1008, 0x10c0,
1240                 0x10cc, 0x10f8,
1241                 0x1100, 0x1100,
1242                 0x110c, 0x1148,
1243                 0x1180, 0x1184,
1244                 0x1190, 0x1194,
1245                 0x11a0, 0x11a4,
1246                 0x11b0, 0x11b4,
1247                 0x11fc, 0x123c,
1248                 0x1280, 0x173c,
1249                 0x1800, 0x18fc,
1250                 0x3000, 0x3028,
1251                 0x3060, 0x30b0,
1252                 0x30b8, 0x30d8,
1253                 0x30e0, 0x30fc,
1254                 0x3140, 0x357c,
1255                 0x35a8, 0x35cc,
1256                 0x35ec, 0x35ec,
1257                 0x3600, 0x5624,
1258                 0x56cc, 0x56ec,
1259                 0x56f4, 0x5720,
1260                 0x5728, 0x575c,
1261                 0x580c, 0x5814,
1262                 0x5890, 0x589c,
1263                 0x58a4, 0x58ac,
1264                 0x58b8, 0x58bc,
1265                 0x5940, 0x59c8,
1266                 0x59d0, 0x59dc,
1267                 0x59fc, 0x5a18,
1268                 0x5a60, 0x5a70,
1269                 0x5a80, 0x5a9c,
1270                 0x5b94, 0x5bfc,
1271                 0x6000, 0x6020,
1272                 0x6028, 0x6040,
1273                 0x6058, 0x609c,
1274                 0x60a8, 0x614c,
1275                 0x7700, 0x7798,
1276                 0x77c0, 0x78fc,
1277                 0x7b00, 0x7b58,
1278                 0x7b60, 0x7b84,
1279                 0x7b8c, 0x7c54,
1280                 0x7d00, 0x7d38,
1281                 0x7d40, 0x7d80,
1282                 0x7d8c, 0x7ddc,
1283                 0x7de4, 0x7e04,
1284                 0x7e10, 0x7e1c,
1285                 0x7e24, 0x7e38,
1286                 0x7e40, 0x7e44,
1287                 0x7e4c, 0x7e78,
1288                 0x7e80, 0x7edc,
1289                 0x7ee8, 0x7efc,
1290                 0x8dc0, 0x8de0,
1291                 0x8df8, 0x8e04,
1292                 0x8e10, 0x8e84,
1293                 0x8ea0, 0x8f84,
1294                 0x8fc0, 0x9058,
1295                 0x9060, 0x9060,
1296                 0x9068, 0x90f8,
1297                 0x9400, 0x9408,
1298                 0x9410, 0x9470,
1299                 0x9600, 0x9600,
1300                 0x9608, 0x9638,
1301                 0x9640, 0x96f4,
1302                 0x9800, 0x9808,
1303                 0x9820, 0x983c,
1304                 0x9850, 0x9864,
1305                 0x9c00, 0x9c6c,
1306                 0x9c80, 0x9cec,
1307                 0x9d00, 0x9d6c,
1308                 0x9d80, 0x9dec,
1309                 0x9e00, 0x9e6c,
1310                 0x9e80, 0x9eec,
1311                 0x9f00, 0x9f6c,
1312                 0x9f80, 0xa020,
1313                 0xd004, 0xd004,
1314                 0xd010, 0xd03c,
1315                 0xdfc0, 0xdfe0,
1316                 0xe000, 0x1106c,
1317                 0x11074, 0x11088,
1318                 0x1109c, 0x1117c,
1319                 0x11190, 0x11204,
1320                 0x19040, 0x1906c,
1321                 0x19078, 0x19080,
1322                 0x1908c, 0x190e8,
1323                 0x190f0, 0x190f8,
1324                 0x19100, 0x19110,
1325                 0x19120, 0x19124,
1326                 0x19150, 0x19194,
1327                 0x1919c, 0x191b0,
1328                 0x191d0, 0x191e8,
1329                 0x19238, 0x19290,
1330                 0x193f8, 0x19428,
1331                 0x19430, 0x19444,
1332                 0x1944c, 0x1946c,
1333                 0x19474, 0x19474,
1334                 0x19490, 0x194cc,
1335                 0x194f0, 0x194f8,
1336                 0x19c00, 0x19c08,
1337                 0x19c10, 0x19c60,
1338                 0x19c94, 0x19ce4,
1339                 0x19cf0, 0x19d40,
1340                 0x19d50, 0x19d94,
1341                 0x19da0, 0x19de8,
1342                 0x19df0, 0x19e10,
1343                 0x19e50, 0x19e90,
1344                 0x19ea0, 0x19f24,
1345                 0x19f34, 0x19f34,
1346                 0x19f40, 0x19f50,
1347                 0x19f90, 0x19fb4,
1348                 0x19fc4, 0x19fe4,
1349                 0x1a000, 0x1a004,
1350                 0x1a010, 0x1a06c,
1351                 0x1a0b0, 0x1a0e4,
1352                 0x1a0ec, 0x1a0f8,
1353                 0x1a100, 0x1a108,
1354                 0x1a114, 0x1a120,
1355                 0x1a128, 0x1a130,
1356                 0x1a138, 0x1a138,
1357                 0x1a190, 0x1a1c4,
1358                 0x1a1fc, 0x1a1fc,
1359                 0x1e008, 0x1e00c,
1360                 0x1e040, 0x1e044,
1361                 0x1e04c, 0x1e04c,
1362                 0x1e284, 0x1e290,
1363                 0x1e2c0, 0x1e2c0,
1364                 0x1e2e0, 0x1e2e0,
1365                 0x1e300, 0x1e384,
1366                 0x1e3c0, 0x1e3c8,
1367                 0x1e408, 0x1e40c,
1368                 0x1e440, 0x1e444,
1369                 0x1e44c, 0x1e44c,
1370                 0x1e684, 0x1e690,
1371                 0x1e6c0, 0x1e6c0,
1372                 0x1e6e0, 0x1e6e0,
1373                 0x1e700, 0x1e784,
1374                 0x1e7c0, 0x1e7c8,
1375                 0x1e808, 0x1e80c,
1376                 0x1e840, 0x1e844,
1377                 0x1e84c, 0x1e84c,
1378                 0x1ea84, 0x1ea90,
1379                 0x1eac0, 0x1eac0,
1380                 0x1eae0, 0x1eae0,
1381                 0x1eb00, 0x1eb84,
1382                 0x1ebc0, 0x1ebc8,
1383                 0x1ec08, 0x1ec0c,
1384                 0x1ec40, 0x1ec44,
1385                 0x1ec4c, 0x1ec4c,
1386                 0x1ee84, 0x1ee90,
1387                 0x1eec0, 0x1eec0,
1388                 0x1eee0, 0x1eee0,
1389                 0x1ef00, 0x1ef84,
1390                 0x1efc0, 0x1efc8,
1391                 0x1f008, 0x1f00c,
1392                 0x1f040, 0x1f044,
1393                 0x1f04c, 0x1f04c,
1394                 0x1f284, 0x1f290,
1395                 0x1f2c0, 0x1f2c0,
1396                 0x1f2e0, 0x1f2e0,
1397                 0x1f300, 0x1f384,
1398                 0x1f3c0, 0x1f3c8,
1399                 0x1f408, 0x1f40c,
1400                 0x1f440, 0x1f444,
1401                 0x1f44c, 0x1f44c,
1402                 0x1f684, 0x1f690,
1403                 0x1f6c0, 0x1f6c0,
1404                 0x1f6e0, 0x1f6e0,
1405                 0x1f700, 0x1f784,
1406                 0x1f7c0, 0x1f7c8,
1407                 0x1f808, 0x1f80c,
1408                 0x1f840, 0x1f844,
1409                 0x1f84c, 0x1f84c,
1410                 0x1fa84, 0x1fa90,
1411                 0x1fac0, 0x1fac0,
1412                 0x1fae0, 0x1fae0,
1413                 0x1fb00, 0x1fb84,
1414                 0x1fbc0, 0x1fbc8,
1415                 0x1fc08, 0x1fc0c,
1416                 0x1fc40, 0x1fc44,
1417                 0x1fc4c, 0x1fc4c,
1418                 0x1fe84, 0x1fe90,
1419                 0x1fec0, 0x1fec0,
1420                 0x1fee0, 0x1fee0,
1421                 0x1ff00, 0x1ff84,
1422                 0x1ffc0, 0x1ffc8,
1423                 0x30000, 0x30030,
1424                 0x30038, 0x30038,
1425                 0x30040, 0x30040,
1426                 0x30100, 0x30144,
1427                 0x30190, 0x301a0,
1428                 0x301a8, 0x301b8,
1429                 0x301c4, 0x301c8,
1430                 0x301d0, 0x301d0,
1431                 0x30200, 0x30318,
1432                 0x30400, 0x304b4,
1433                 0x304c0, 0x3052c,
1434                 0x30540, 0x3061c,
1435                 0x30800, 0x30828,
1436                 0x30834, 0x30834,
1437                 0x308c0, 0x30908,
1438                 0x30910, 0x309ac,
1439                 0x30a00, 0x30a14,
1440                 0x30a1c, 0x30a2c,
1441                 0x30a44, 0x30a50,
1442                 0x30a74, 0x30a74,
1443                 0x30a7c, 0x30afc,
1444                 0x30b08, 0x30c24,
1445                 0x30d00, 0x30d00,
1446                 0x30d08, 0x30d14,
1447                 0x30d1c, 0x30d20,
1448                 0x30d3c, 0x30d3c,
1449                 0x30d48, 0x30d50,
1450                 0x31200, 0x3120c,
1451                 0x31220, 0x31220,
1452                 0x31240, 0x31240,
1453                 0x31600, 0x3160c,
1454                 0x31a00, 0x31a1c,
1455                 0x31e00, 0x31e20,
1456                 0x31e38, 0x31e3c,
1457                 0x31e80, 0x31e80,
1458                 0x31e88, 0x31ea8,
1459                 0x31eb0, 0x31eb4,
1460                 0x31ec8, 0x31ed4,
1461                 0x31fb8, 0x32004,
1462                 0x32200, 0x32200,
1463                 0x32208, 0x32240,
1464                 0x32248, 0x32280,
1465                 0x32288, 0x322c0,
1466                 0x322c8, 0x322fc,
1467                 0x32600, 0x32630,
1468                 0x32a00, 0x32abc,
1469                 0x32b00, 0x32b10,
1470                 0x32b20, 0x32b30,
1471                 0x32b40, 0x32b50,
1472                 0x32b60, 0x32b70,
1473                 0x33000, 0x33028,
1474                 0x33030, 0x33048,
1475                 0x33060, 0x33068,
1476                 0x33070, 0x3309c,
1477                 0x330f0, 0x33128,
1478                 0x33130, 0x33148,
1479                 0x33160, 0x33168,
1480                 0x33170, 0x3319c,
1481                 0x331f0, 0x33238,
1482                 0x33240, 0x33240,
1483                 0x33248, 0x33250,
1484                 0x3325c, 0x33264,
1485                 0x33270, 0x332b8,
1486                 0x332c0, 0x332e4,
1487                 0x332f8, 0x33338,
1488                 0x33340, 0x33340,
1489                 0x33348, 0x33350,
1490                 0x3335c, 0x33364,
1491                 0x33370, 0x333b8,
1492                 0x333c0, 0x333e4,
1493                 0x333f8, 0x33428,
1494                 0x33430, 0x33448,
1495                 0x33460, 0x33468,
1496                 0x33470, 0x3349c,
1497                 0x334f0, 0x33528,
1498                 0x33530, 0x33548,
1499                 0x33560, 0x33568,
1500                 0x33570, 0x3359c,
1501                 0x335f0, 0x33638,
1502                 0x33640, 0x33640,
1503                 0x33648, 0x33650,
1504                 0x3365c, 0x33664,
1505                 0x33670, 0x336b8,
1506                 0x336c0, 0x336e4,
1507                 0x336f8, 0x33738,
1508                 0x33740, 0x33740,
1509                 0x33748, 0x33750,
1510                 0x3375c, 0x33764,
1511                 0x33770, 0x337b8,
1512                 0x337c0, 0x337e4,
1513                 0x337f8, 0x337fc,
1514                 0x33814, 0x33814,
1515                 0x3382c, 0x3382c,
1516                 0x33880, 0x3388c,
1517                 0x338e8, 0x338ec,
1518                 0x33900, 0x33928,
1519                 0x33930, 0x33948,
1520                 0x33960, 0x33968,
1521                 0x33970, 0x3399c,
1522                 0x339f0, 0x33a38,
1523                 0x33a40, 0x33a40,
1524                 0x33a48, 0x33a50,
1525                 0x33a5c, 0x33a64,
1526                 0x33a70, 0x33ab8,
1527                 0x33ac0, 0x33ae4,
1528                 0x33af8, 0x33b10,
1529                 0x33b28, 0x33b28,
1530                 0x33b3c, 0x33b50,
1531                 0x33bf0, 0x33c10,
1532                 0x33c28, 0x33c28,
1533                 0x33c3c, 0x33c50,
1534                 0x33cf0, 0x33cfc,
1535                 0x34000, 0x34030,
1536                 0x34038, 0x34038,
1537                 0x34040, 0x34040,
1538                 0x34100, 0x34144,
1539                 0x34190, 0x341a0,
1540                 0x341a8, 0x341b8,
1541                 0x341c4, 0x341c8,
1542                 0x341d0, 0x341d0,
1543                 0x34200, 0x34318,
1544                 0x34400, 0x344b4,
1545                 0x344c0, 0x3452c,
1546                 0x34540, 0x3461c,
1547                 0x34800, 0x34828,
1548                 0x34834, 0x34834,
1549                 0x348c0, 0x34908,
1550                 0x34910, 0x349ac,
1551                 0x34a00, 0x34a14,
1552                 0x34a1c, 0x34a2c,
1553                 0x34a44, 0x34a50,
1554                 0x34a74, 0x34a74,
1555                 0x34a7c, 0x34afc,
1556                 0x34b08, 0x34c24,
1557                 0x34d00, 0x34d00,
1558                 0x34d08, 0x34d14,
1559                 0x34d1c, 0x34d20,
1560                 0x34d3c, 0x34d3c,
1561                 0x34d48, 0x34d50,
1562                 0x35200, 0x3520c,
1563                 0x35220, 0x35220,
1564                 0x35240, 0x35240,
1565                 0x35600, 0x3560c,
1566                 0x35a00, 0x35a1c,
1567                 0x35e00, 0x35e20,
1568                 0x35e38, 0x35e3c,
1569                 0x35e80, 0x35e80,
1570                 0x35e88, 0x35ea8,
1571                 0x35eb0, 0x35eb4,
1572                 0x35ec8, 0x35ed4,
1573                 0x35fb8, 0x36004,
1574                 0x36200, 0x36200,
1575                 0x36208, 0x36240,
1576                 0x36248, 0x36280,
1577                 0x36288, 0x362c0,
1578                 0x362c8, 0x362fc,
1579                 0x36600, 0x36630,
1580                 0x36a00, 0x36abc,
1581                 0x36b00, 0x36b10,
1582                 0x36b20, 0x36b30,
1583                 0x36b40, 0x36b50,
1584                 0x36b60, 0x36b70,
1585                 0x37000, 0x37028,
1586                 0x37030, 0x37048,
1587                 0x37060, 0x37068,
1588                 0x37070, 0x3709c,
1589                 0x370f0, 0x37128,
1590                 0x37130, 0x37148,
1591                 0x37160, 0x37168,
1592                 0x37170, 0x3719c,
1593                 0x371f0, 0x37238,
1594                 0x37240, 0x37240,
1595                 0x37248, 0x37250,
1596                 0x3725c, 0x37264,
1597                 0x37270, 0x372b8,
1598                 0x372c0, 0x372e4,
1599                 0x372f8, 0x37338,
1600                 0x37340, 0x37340,
1601                 0x37348, 0x37350,
1602                 0x3735c, 0x37364,
1603                 0x37370, 0x373b8,
1604                 0x373c0, 0x373e4,
1605                 0x373f8, 0x37428,
1606                 0x37430, 0x37448,
1607                 0x37460, 0x37468,
1608                 0x37470, 0x3749c,
1609                 0x374f0, 0x37528,
1610                 0x37530, 0x37548,
1611                 0x37560, 0x37568,
1612                 0x37570, 0x3759c,
1613                 0x375f0, 0x37638,
1614                 0x37640, 0x37640,
1615                 0x37648, 0x37650,
1616                 0x3765c, 0x37664,
1617                 0x37670, 0x376b8,
1618                 0x376c0, 0x376e4,
1619                 0x376f8, 0x37738,
1620                 0x37740, 0x37740,
1621                 0x37748, 0x37750,
1622                 0x3775c, 0x37764,
1623                 0x37770, 0x377b8,
1624                 0x377c0, 0x377e4,
1625                 0x377f8, 0x377fc,
1626                 0x37814, 0x37814,
1627                 0x3782c, 0x3782c,
1628                 0x37880, 0x3788c,
1629                 0x378e8, 0x378ec,
1630                 0x37900, 0x37928,
1631                 0x37930, 0x37948,
1632                 0x37960, 0x37968,
1633                 0x37970, 0x3799c,
1634                 0x379f0, 0x37a38,
1635                 0x37a40, 0x37a40,
1636                 0x37a48, 0x37a50,
1637                 0x37a5c, 0x37a64,
1638                 0x37a70, 0x37ab8,
1639                 0x37ac0, 0x37ae4,
1640                 0x37af8, 0x37b10,
1641                 0x37b28, 0x37b28,
1642                 0x37b3c, 0x37b50,
1643                 0x37bf0, 0x37c10,
1644                 0x37c28, 0x37c28,
1645                 0x37c3c, 0x37c50,
1646                 0x37cf0, 0x37cfc,
1647                 0x38000, 0x38030,
1648                 0x38038, 0x38038,
1649                 0x38040, 0x38040,
1650                 0x38100, 0x38144,
1651                 0x38190, 0x381a0,
1652                 0x381a8, 0x381b8,
1653                 0x381c4, 0x381c8,
1654                 0x381d0, 0x381d0,
1655                 0x38200, 0x38318,
1656                 0x38400, 0x384b4,
1657                 0x384c0, 0x3852c,
1658                 0x38540, 0x3861c,
1659                 0x38800, 0x38828,
1660                 0x38834, 0x38834,
1661                 0x388c0, 0x38908,
1662                 0x38910, 0x389ac,
1663                 0x38a00, 0x38a14,
1664                 0x38a1c, 0x38a2c,
1665                 0x38a44, 0x38a50,
1666                 0x38a74, 0x38a74,
1667                 0x38a7c, 0x38afc,
1668                 0x38b08, 0x38c24,
1669                 0x38d00, 0x38d00,
1670                 0x38d08, 0x38d14,
1671                 0x38d1c, 0x38d20,
1672                 0x38d3c, 0x38d3c,
1673                 0x38d48, 0x38d50,
1674                 0x39200, 0x3920c,
1675                 0x39220, 0x39220,
1676                 0x39240, 0x39240,
1677                 0x39600, 0x3960c,
1678                 0x39a00, 0x39a1c,
1679                 0x39e00, 0x39e20,
1680                 0x39e38, 0x39e3c,
1681                 0x39e80, 0x39e80,
1682                 0x39e88, 0x39ea8,
1683                 0x39eb0, 0x39eb4,
1684                 0x39ec8, 0x39ed4,
1685                 0x39fb8, 0x3a004,
1686                 0x3a200, 0x3a200,
1687                 0x3a208, 0x3a240,
1688                 0x3a248, 0x3a280,
1689                 0x3a288, 0x3a2c0,
1690                 0x3a2c8, 0x3a2fc,
1691                 0x3a600, 0x3a630,
1692                 0x3aa00, 0x3aabc,
1693                 0x3ab00, 0x3ab10,
1694                 0x3ab20, 0x3ab30,
1695                 0x3ab40, 0x3ab50,
1696                 0x3ab60, 0x3ab70,
1697                 0x3b000, 0x3b028,
1698                 0x3b030, 0x3b048,
1699                 0x3b060, 0x3b068,
1700                 0x3b070, 0x3b09c,
1701                 0x3b0f0, 0x3b128,
1702                 0x3b130, 0x3b148,
1703                 0x3b160, 0x3b168,
1704                 0x3b170, 0x3b19c,
1705                 0x3b1f0, 0x3b238,
1706                 0x3b240, 0x3b240,
1707                 0x3b248, 0x3b250,
1708                 0x3b25c, 0x3b264,
1709                 0x3b270, 0x3b2b8,
1710                 0x3b2c0, 0x3b2e4,
1711                 0x3b2f8, 0x3b338,
1712                 0x3b340, 0x3b340,
1713                 0x3b348, 0x3b350,
1714                 0x3b35c, 0x3b364,
1715                 0x3b370, 0x3b3b8,
1716                 0x3b3c0, 0x3b3e4,
1717                 0x3b3f8, 0x3b428,
1718                 0x3b430, 0x3b448,
1719                 0x3b460, 0x3b468,
1720                 0x3b470, 0x3b49c,
1721                 0x3b4f0, 0x3b528,
1722                 0x3b530, 0x3b548,
1723                 0x3b560, 0x3b568,
1724                 0x3b570, 0x3b59c,
1725                 0x3b5f0, 0x3b638,
1726                 0x3b640, 0x3b640,
1727                 0x3b648, 0x3b650,
1728                 0x3b65c, 0x3b664,
1729                 0x3b670, 0x3b6b8,
1730                 0x3b6c0, 0x3b6e4,
1731                 0x3b6f8, 0x3b738,
1732                 0x3b740, 0x3b740,
1733                 0x3b748, 0x3b750,
1734                 0x3b75c, 0x3b764,
1735                 0x3b770, 0x3b7b8,
1736                 0x3b7c0, 0x3b7e4,
1737                 0x3b7f8, 0x3b7fc,
1738                 0x3b814, 0x3b814,
1739                 0x3b82c, 0x3b82c,
1740                 0x3b880, 0x3b88c,
1741                 0x3b8e8, 0x3b8ec,
1742                 0x3b900, 0x3b928,
1743                 0x3b930, 0x3b948,
1744                 0x3b960, 0x3b968,
1745                 0x3b970, 0x3b99c,
1746                 0x3b9f0, 0x3ba38,
1747                 0x3ba40, 0x3ba40,
1748                 0x3ba48, 0x3ba50,
1749                 0x3ba5c, 0x3ba64,
1750                 0x3ba70, 0x3bab8,
1751                 0x3bac0, 0x3bae4,
1752                 0x3baf8, 0x3bb10,
1753                 0x3bb28, 0x3bb28,
1754                 0x3bb3c, 0x3bb50,
1755                 0x3bbf0, 0x3bc10,
1756                 0x3bc28, 0x3bc28,
1757                 0x3bc3c, 0x3bc50,
1758                 0x3bcf0, 0x3bcfc,
1759                 0x3c000, 0x3c030,
1760                 0x3c038, 0x3c038,
1761                 0x3c040, 0x3c040,
1762                 0x3c100, 0x3c144,
1763                 0x3c190, 0x3c1a0,
1764                 0x3c1a8, 0x3c1b8,
1765                 0x3c1c4, 0x3c1c8,
1766                 0x3c1d0, 0x3c1d0,
1767                 0x3c200, 0x3c318,
1768                 0x3c400, 0x3c4b4,
1769                 0x3c4c0, 0x3c52c,
1770                 0x3c540, 0x3c61c,
1771                 0x3c800, 0x3c828,
1772                 0x3c834, 0x3c834,
1773                 0x3c8c0, 0x3c908,
1774                 0x3c910, 0x3c9ac,
1775                 0x3ca00, 0x3ca14,
1776                 0x3ca1c, 0x3ca2c,
1777                 0x3ca44, 0x3ca50,
1778                 0x3ca74, 0x3ca74,
1779                 0x3ca7c, 0x3cafc,
1780                 0x3cb08, 0x3cc24,
1781                 0x3cd00, 0x3cd00,
1782                 0x3cd08, 0x3cd14,
1783                 0x3cd1c, 0x3cd20,
1784                 0x3cd3c, 0x3cd3c,
1785                 0x3cd48, 0x3cd50,
1786                 0x3d200, 0x3d20c,
1787                 0x3d220, 0x3d220,
1788                 0x3d240, 0x3d240,
1789                 0x3d600, 0x3d60c,
1790                 0x3da00, 0x3da1c,
1791                 0x3de00, 0x3de20,
1792                 0x3de38, 0x3de3c,
1793                 0x3de80, 0x3de80,
1794                 0x3de88, 0x3dea8,
1795                 0x3deb0, 0x3deb4,
1796                 0x3dec8, 0x3ded4,
1797                 0x3dfb8, 0x3e004,
1798                 0x3e200, 0x3e200,
1799                 0x3e208, 0x3e240,
1800                 0x3e248, 0x3e280,
1801                 0x3e288, 0x3e2c0,
1802                 0x3e2c8, 0x3e2fc,
1803                 0x3e600, 0x3e630,
1804                 0x3ea00, 0x3eabc,
1805                 0x3eb00, 0x3eb10,
1806                 0x3eb20, 0x3eb30,
1807                 0x3eb40, 0x3eb50,
1808                 0x3eb60, 0x3eb70,
1809                 0x3f000, 0x3f028,
1810                 0x3f030, 0x3f048,
1811                 0x3f060, 0x3f068,
1812                 0x3f070, 0x3f09c,
1813                 0x3f0f0, 0x3f128,
1814                 0x3f130, 0x3f148,
1815                 0x3f160, 0x3f168,
1816                 0x3f170, 0x3f19c,
1817                 0x3f1f0, 0x3f238,
1818                 0x3f240, 0x3f240,
1819                 0x3f248, 0x3f250,
1820                 0x3f25c, 0x3f264,
1821                 0x3f270, 0x3f2b8,
1822                 0x3f2c0, 0x3f2e4,
1823                 0x3f2f8, 0x3f338,
1824                 0x3f340, 0x3f340,
1825                 0x3f348, 0x3f350,
1826                 0x3f35c, 0x3f364,
1827                 0x3f370, 0x3f3b8,
1828                 0x3f3c0, 0x3f3e4,
1829                 0x3f3f8, 0x3f428,
1830                 0x3f430, 0x3f448,
1831                 0x3f460, 0x3f468,
1832                 0x3f470, 0x3f49c,
1833                 0x3f4f0, 0x3f528,
1834                 0x3f530, 0x3f548,
1835                 0x3f560, 0x3f568,
1836                 0x3f570, 0x3f59c,
1837                 0x3f5f0, 0x3f638,
1838                 0x3f640, 0x3f640,
1839                 0x3f648, 0x3f650,
1840                 0x3f65c, 0x3f664,
1841                 0x3f670, 0x3f6b8,
1842                 0x3f6c0, 0x3f6e4,
1843                 0x3f6f8, 0x3f738,
1844                 0x3f740, 0x3f740,
1845                 0x3f748, 0x3f750,
1846                 0x3f75c, 0x3f764,
1847                 0x3f770, 0x3f7b8,
1848                 0x3f7c0, 0x3f7e4,
1849                 0x3f7f8, 0x3f7fc,
1850                 0x3f814, 0x3f814,
1851                 0x3f82c, 0x3f82c,
1852                 0x3f880, 0x3f88c,
1853                 0x3f8e8, 0x3f8ec,
1854                 0x3f900, 0x3f928,
1855                 0x3f930, 0x3f948,
1856                 0x3f960, 0x3f968,
1857                 0x3f970, 0x3f99c,
1858                 0x3f9f0, 0x3fa38,
1859                 0x3fa40, 0x3fa40,
1860                 0x3fa48, 0x3fa50,
1861                 0x3fa5c, 0x3fa64,
1862                 0x3fa70, 0x3fab8,
1863                 0x3fac0, 0x3fae4,
1864                 0x3faf8, 0x3fb10,
1865                 0x3fb28, 0x3fb28,
1866                 0x3fb3c, 0x3fb50,
1867                 0x3fbf0, 0x3fc10,
1868                 0x3fc28, 0x3fc28,
1869                 0x3fc3c, 0x3fc50,
1870                 0x3fcf0, 0x3fcfc,
1871                 0x40000, 0x4000c,
1872                 0x40040, 0x40050,
1873                 0x40060, 0x40068,
1874                 0x4007c, 0x4008c,
1875                 0x40094, 0x400b0,
1876                 0x400c0, 0x40144,
1877                 0x40180, 0x4018c,
1878                 0x40200, 0x40254,
1879                 0x40260, 0x40264,
1880                 0x40270, 0x40288,
1881                 0x40290, 0x40298,
1882                 0x402ac, 0x402c8,
1883                 0x402d0, 0x402e0,
1884                 0x402f0, 0x402f0,
1885                 0x40300, 0x4033c,
1886                 0x403f8, 0x403fc,
1887                 0x41304, 0x413c4,
1888                 0x41400, 0x4140c,
1889                 0x41414, 0x4141c,
1890                 0x41480, 0x414d0,
1891                 0x44000, 0x44054,
1892                 0x4405c, 0x44078,
1893                 0x440c0, 0x44174,
1894                 0x44180, 0x441ac,
1895                 0x441b4, 0x441b8,
1896                 0x441c0, 0x44254,
1897                 0x4425c, 0x44278,
1898                 0x442c0, 0x44374,
1899                 0x44380, 0x443ac,
1900                 0x443b4, 0x443b8,
1901                 0x443c0, 0x44454,
1902                 0x4445c, 0x44478,
1903                 0x444c0, 0x44574,
1904                 0x44580, 0x445ac,
1905                 0x445b4, 0x445b8,
1906                 0x445c0, 0x44654,
1907                 0x4465c, 0x44678,
1908                 0x446c0, 0x44774,
1909                 0x44780, 0x447ac,
1910                 0x447b4, 0x447b8,
1911                 0x447c0, 0x44854,
1912                 0x4485c, 0x44878,
1913                 0x448c0, 0x44974,
1914                 0x44980, 0x449ac,
1915                 0x449b4, 0x449b8,
1916                 0x449c0, 0x449fc,
1917                 0x45000, 0x45004,
1918                 0x45010, 0x45030,
1919                 0x45040, 0x45060,
1920                 0x45068, 0x45068,
1921                 0x45080, 0x45084,
1922                 0x450a0, 0x450b0,
1923                 0x45200, 0x45204,
1924                 0x45210, 0x45230,
1925                 0x45240, 0x45260,
1926                 0x45268, 0x45268,
1927                 0x45280, 0x45284,
1928                 0x452a0, 0x452b0,
1929                 0x460c0, 0x460e4,
1930                 0x47000, 0x4703c,
1931                 0x47044, 0x4708c,
1932                 0x47200, 0x47250,
1933                 0x47400, 0x47408,
1934                 0x47414, 0x47420,
1935                 0x47600, 0x47618,
1936                 0x47800, 0x47814,
1937                 0x48000, 0x4800c,
1938                 0x48040, 0x48050,
1939                 0x48060, 0x48068,
1940                 0x4807c, 0x4808c,
1941                 0x48094, 0x480b0,
1942                 0x480c0, 0x48144,
1943                 0x48180, 0x4818c,
1944                 0x48200, 0x48254,
1945                 0x48260, 0x48264,
1946                 0x48270, 0x48288,
1947                 0x48290, 0x48298,
1948                 0x482ac, 0x482c8,
1949                 0x482d0, 0x482e0,
1950                 0x482f0, 0x482f0,
1951                 0x48300, 0x4833c,
1952                 0x483f8, 0x483fc,
1953                 0x49304, 0x493c4,
1954                 0x49400, 0x4940c,
1955                 0x49414, 0x4941c,
1956                 0x49480, 0x494d0,
1957                 0x4c000, 0x4c054,
1958                 0x4c05c, 0x4c078,
1959                 0x4c0c0, 0x4c174,
1960                 0x4c180, 0x4c1ac,
1961                 0x4c1b4, 0x4c1b8,
1962                 0x4c1c0, 0x4c254,
1963                 0x4c25c, 0x4c278,
1964                 0x4c2c0, 0x4c374,
1965                 0x4c380, 0x4c3ac,
1966                 0x4c3b4, 0x4c3b8,
1967                 0x4c3c0, 0x4c454,
1968                 0x4c45c, 0x4c478,
1969                 0x4c4c0, 0x4c574,
1970                 0x4c580, 0x4c5ac,
1971                 0x4c5b4, 0x4c5b8,
1972                 0x4c5c0, 0x4c654,
1973                 0x4c65c, 0x4c678,
1974                 0x4c6c0, 0x4c774,
1975                 0x4c780, 0x4c7ac,
1976                 0x4c7b4, 0x4c7b8,
1977                 0x4c7c0, 0x4c854,
1978                 0x4c85c, 0x4c878,
1979                 0x4c8c0, 0x4c974,
1980                 0x4c980, 0x4c9ac,
1981                 0x4c9b4, 0x4c9b8,
1982                 0x4c9c0, 0x4c9fc,
1983                 0x4d000, 0x4d004,
1984                 0x4d010, 0x4d030,
1985                 0x4d040, 0x4d060,
1986                 0x4d068, 0x4d068,
1987                 0x4d080, 0x4d084,
1988                 0x4d0a0, 0x4d0b0,
1989                 0x4d200, 0x4d204,
1990                 0x4d210, 0x4d230,
1991                 0x4d240, 0x4d260,
1992                 0x4d268, 0x4d268,
1993                 0x4d280, 0x4d284,
1994                 0x4d2a0, 0x4d2b0,
1995                 0x4e0c0, 0x4e0e4,
1996                 0x4f000, 0x4f03c,
1997                 0x4f044, 0x4f08c,
1998                 0x4f200, 0x4f250,
1999                 0x4f400, 0x4f408,
2000                 0x4f414, 0x4f420,
2001                 0x4f600, 0x4f618,
2002                 0x4f800, 0x4f814,
2003                 0x50000, 0x50084,
2004                 0x50090, 0x500cc,
2005                 0x50400, 0x50400,
2006                 0x50800, 0x50884,
2007                 0x50890, 0x508cc,
2008                 0x50c00, 0x50c00,
2009                 0x51000, 0x5101c,
2010                 0x51300, 0x51308,
2011         };
2012
2013         static const unsigned int t5vf_reg_ranges[] = {
2014                 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2015                 VF_MPS_REG(A_MPS_VF_CTL),
2016                 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2017                 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2018                 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2019                 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2020                 FW_T4VF_MBDATA_BASE_ADDR,
2021                 FW_T4VF_MBDATA_BASE_ADDR +
2022                 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2023         };
2024
2025         static const unsigned int t6_reg_ranges[] = {
2026                 0x1008, 0x101c,
2027                 0x1024, 0x10a8,
2028                 0x10b4, 0x10f8,
2029                 0x1100, 0x1114,
2030                 0x111c, 0x112c,
2031                 0x1138, 0x113c,
2032                 0x1144, 0x114c,
2033                 0x1180, 0x1184,
2034                 0x1190, 0x1194,
2035                 0x11a0, 0x11a4,
2036                 0x11b0, 0x11b4,
2037                 0x11fc, 0x1274,
2038                 0x1280, 0x133c,
2039                 0x1800, 0x18fc,
2040                 0x3000, 0x302c,
2041                 0x3060, 0x30b0,
2042                 0x30b8, 0x30d8,
2043                 0x30e0, 0x30fc,
2044                 0x3140, 0x357c,
2045                 0x35a8, 0x35cc,
2046                 0x35ec, 0x35ec,
2047                 0x3600, 0x5624,
2048                 0x56cc, 0x56ec,
2049                 0x56f4, 0x5720,
2050                 0x5728, 0x575c,
2051                 0x580c, 0x5814,
2052                 0x5890, 0x589c,
2053                 0x58a4, 0x58ac,
2054                 0x58b8, 0x58bc,
2055                 0x5940, 0x595c,
2056                 0x5980, 0x598c,
2057                 0x59b0, 0x59c8,
2058                 0x59d0, 0x59dc,
2059                 0x59fc, 0x5a18,
2060                 0x5a60, 0x5a6c,
2061                 0x5a80, 0x5a8c,
2062                 0x5a94, 0x5a9c,
2063                 0x5b94, 0x5bfc,
2064                 0x5c10, 0x5e48,
2065                 0x5e50, 0x5e94,
2066                 0x5ea0, 0x5eb0,
2067                 0x5ec0, 0x5ec0,
2068                 0x5ec8, 0x5ed0,
2069                 0x5ee0, 0x5ee0,
2070                 0x5ef0, 0x5ef0,
2071                 0x5f00, 0x5f00,
2072                 0x6000, 0x6020,
2073                 0x6028, 0x6040,
2074                 0x6058, 0x609c,
2075                 0x60a8, 0x619c,
2076                 0x7700, 0x7798,
2077                 0x77c0, 0x7880,
2078                 0x78cc, 0x78fc,
2079                 0x7b00, 0x7b58,
2080                 0x7b60, 0x7b84,
2081                 0x7b8c, 0x7c54,
2082                 0x7d00, 0x7d38,
2083                 0x7d40, 0x7d84,
2084                 0x7d8c, 0x7ddc,
2085                 0x7de4, 0x7e04,
2086                 0x7e10, 0x7e1c,
2087                 0x7e24, 0x7e38,
2088                 0x7e40, 0x7e44,
2089                 0x7e4c, 0x7e78,
2090                 0x7e80, 0x7edc,
2091                 0x7ee8, 0x7efc,
2092                 0x8dc0, 0x8de4,
2093                 0x8df8, 0x8e04,
2094                 0x8e10, 0x8e84,
2095                 0x8ea0, 0x8f88,
2096                 0x8fb8, 0x9058,
2097                 0x9060, 0x9060,
2098                 0x9068, 0x90f8,
2099                 0x9100, 0x9124,
2100                 0x9400, 0x9470,
2101                 0x9600, 0x9600,
2102                 0x9608, 0x9638,
2103                 0x9640, 0x9704,
2104                 0x9710, 0x971c,
2105                 0x9800, 0x9808,
2106                 0x9820, 0x983c,
2107                 0x9850, 0x9864,
2108                 0x9c00, 0x9c6c,
2109                 0x9c80, 0x9cec,
2110                 0x9d00, 0x9d6c,
2111                 0x9d80, 0x9dec,
2112                 0x9e00, 0x9e6c,
2113                 0x9e80, 0x9eec,
2114                 0x9f00, 0x9f6c,
2115                 0x9f80, 0xa020,
2116                 0xd004, 0xd03c,
2117                 0xd100, 0xd118,
2118                 0xd200, 0xd214,
2119                 0xd220, 0xd234,
2120                 0xd240, 0xd254,
2121                 0xd260, 0xd274,
2122                 0xd280, 0xd294,
2123                 0xd2a0, 0xd2b4,
2124                 0xd2c0, 0xd2d4,
2125                 0xd2e0, 0xd2f4,
2126                 0xd300, 0xd31c,
2127                 0xdfc0, 0xdfe0,
2128                 0xe000, 0xf008,
2129                 0xf010, 0xf018,
2130                 0xf020, 0xf028,
2131                 0x11000, 0x11014,
2132                 0x11048, 0x1106c,
2133                 0x11074, 0x11088,
2134                 0x11098, 0x11120,
2135                 0x1112c, 0x1117c,
2136                 0x11190, 0x112e0,
2137                 0x11300, 0x1130c,
2138                 0x12000, 0x1206c,
2139                 0x19040, 0x1906c,
2140                 0x19078, 0x19080,
2141                 0x1908c, 0x190e8,
2142                 0x190f0, 0x190f8,
2143                 0x19100, 0x19110,
2144                 0x19120, 0x19124,
2145                 0x19150, 0x19194,
2146                 0x1919c, 0x191b0,
2147                 0x191d0, 0x191e8,
2148                 0x19238, 0x19290,
2149                 0x192a4, 0x192b0,
2150                 0x192bc, 0x192bc,
2151                 0x19348, 0x1934c,
2152                 0x193f8, 0x19418,
2153                 0x19420, 0x19428,
2154                 0x19430, 0x19444,
2155                 0x1944c, 0x1946c,
2156                 0x19474, 0x19474,
2157                 0x19490, 0x194cc,
2158                 0x194f0, 0x194f8,
2159                 0x19c00, 0x19c48,
2160                 0x19c50, 0x19c80,
2161                 0x19c94, 0x19c98,
2162                 0x19ca0, 0x19cbc,
2163                 0x19ce4, 0x19ce4,
2164                 0x19cf0, 0x19cf8,
2165                 0x19d00, 0x19d28,
2166                 0x19d50, 0x19d78,
2167                 0x19d94, 0x19d98,
2168                 0x19da0, 0x19dc8,
2169                 0x19df0, 0x19e10,
2170                 0x19e50, 0x19e6c,
2171                 0x19ea0, 0x19ebc,
2172                 0x19ec4, 0x19ef4,
2173                 0x19f04, 0x19f2c,
2174                 0x19f34, 0x19f34,
2175                 0x19f40, 0x19f50,
2176                 0x19f90, 0x19fac,
2177                 0x19fc4, 0x19fc8,
2178                 0x19fd0, 0x19fe4,
2179                 0x1a000, 0x1a004,
2180                 0x1a010, 0x1a06c,
2181                 0x1a0b0, 0x1a0e4,
2182                 0x1a0ec, 0x1a0f8,
2183                 0x1a100, 0x1a108,
2184                 0x1a114, 0x1a120,
2185                 0x1a128, 0x1a130,
2186                 0x1a138, 0x1a138,
2187                 0x1a190, 0x1a1c4,
2188                 0x1a1fc, 0x1a1fc,
2189                 0x1e008, 0x1e00c,
2190                 0x1e040, 0x1e044,
2191                 0x1e04c, 0x1e04c,
2192                 0x1e284, 0x1e290,
2193                 0x1e2c0, 0x1e2c0,
2194                 0x1e2e0, 0x1e2e0,
2195                 0x1e300, 0x1e384,
2196                 0x1e3c0, 0x1e3c8,
2197                 0x1e408, 0x1e40c,
2198                 0x1e440, 0x1e444,
2199                 0x1e44c, 0x1e44c,
2200                 0x1e684, 0x1e690,
2201                 0x1e6c0, 0x1e6c0,
2202                 0x1e6e0, 0x1e6e0,
2203                 0x1e700, 0x1e784,
2204                 0x1e7c0, 0x1e7c8,
2205                 0x1e808, 0x1e80c,
2206                 0x1e840, 0x1e844,
2207                 0x1e84c, 0x1e84c,
2208                 0x1ea84, 0x1ea90,
2209                 0x1eac0, 0x1eac0,
2210                 0x1eae0, 0x1eae0,
2211                 0x1eb00, 0x1eb84,
2212                 0x1ebc0, 0x1ebc8,
2213                 0x1ec08, 0x1ec0c,
2214                 0x1ec40, 0x1ec44,
2215                 0x1ec4c, 0x1ec4c,
2216                 0x1ee84, 0x1ee90,
2217                 0x1eec0, 0x1eec0,
2218                 0x1eee0, 0x1eee0,
2219                 0x1ef00, 0x1ef84,
2220                 0x1efc0, 0x1efc8,
2221                 0x1f008, 0x1f00c,
2222                 0x1f040, 0x1f044,
2223                 0x1f04c, 0x1f04c,
2224                 0x1f284, 0x1f290,
2225                 0x1f2c0, 0x1f2c0,
2226                 0x1f2e0, 0x1f2e0,
2227                 0x1f300, 0x1f384,
2228                 0x1f3c0, 0x1f3c8,
2229                 0x1f408, 0x1f40c,
2230                 0x1f440, 0x1f444,
2231                 0x1f44c, 0x1f44c,
2232                 0x1f684, 0x1f690,
2233                 0x1f6c0, 0x1f6c0,
2234                 0x1f6e0, 0x1f6e0,
2235                 0x1f700, 0x1f784,
2236                 0x1f7c0, 0x1f7c8,
2237                 0x1f808, 0x1f80c,
2238                 0x1f840, 0x1f844,
2239                 0x1f84c, 0x1f84c,
2240                 0x1fa84, 0x1fa90,
2241                 0x1fac0, 0x1fac0,
2242                 0x1fae0, 0x1fae0,
2243                 0x1fb00, 0x1fb84,
2244                 0x1fbc0, 0x1fbc8,
2245                 0x1fc08, 0x1fc0c,
2246                 0x1fc40, 0x1fc44,
2247                 0x1fc4c, 0x1fc4c,
2248                 0x1fe84, 0x1fe90,
2249                 0x1fec0, 0x1fec0,
2250                 0x1fee0, 0x1fee0,
2251                 0x1ff00, 0x1ff84,
2252                 0x1ffc0, 0x1ffc8,
2253                 0x30000, 0x30030,
2254                 0x30038, 0x30038,
2255                 0x30040, 0x30040,
2256                 0x30048, 0x30048,
2257                 0x30050, 0x30050,
2258                 0x3005c, 0x30060,
2259                 0x30068, 0x30068,
2260                 0x30070, 0x30070,
2261                 0x30100, 0x30168,
2262                 0x30190, 0x301a0,
2263                 0x301a8, 0x301b8,
2264                 0x301c4, 0x301c8,
2265                 0x301d0, 0x301d0,
2266                 0x30200, 0x30320,
2267                 0x30400, 0x304b4,
2268                 0x304c0, 0x3052c,
2269                 0x30540, 0x3061c,
2270                 0x30800, 0x308a0,
2271                 0x308c0, 0x30908,
2272                 0x30910, 0x309b8,
2273                 0x30a00, 0x30a04,
2274                 0x30a0c, 0x30a14,
2275                 0x30a1c, 0x30a2c,
2276                 0x30a44, 0x30a50,
2277                 0x30a74, 0x30a74,
2278                 0x30a7c, 0x30afc,
2279                 0x30b08, 0x30c24,
2280                 0x30d00, 0x30d14,
2281                 0x30d1c, 0x30d3c,
2282                 0x30d44, 0x30d4c,
2283                 0x30d54, 0x30d74,
2284                 0x30d7c, 0x30d7c,
2285                 0x30de0, 0x30de0,
2286                 0x30e00, 0x30ed4,
2287                 0x30f00, 0x30fa4,
2288                 0x30fc0, 0x30fc4,
2289                 0x31000, 0x31004,
2290                 0x31080, 0x310fc,
2291                 0x31208, 0x31220,
2292                 0x3123c, 0x31254,
2293                 0x31300, 0x31300,
2294                 0x31308, 0x3131c,
2295                 0x31338, 0x3133c,
2296                 0x31380, 0x31380,
2297                 0x31388, 0x313a8,
2298                 0x313b4, 0x313b4,
2299                 0x31400, 0x31420,
2300                 0x31438, 0x3143c,
2301                 0x31480, 0x31480,
2302                 0x314a8, 0x314a8,
2303                 0x314b0, 0x314b4,
2304                 0x314c8, 0x314d4,
2305                 0x31a40, 0x31a4c,
2306                 0x31af0, 0x31b20,
2307                 0x31b38, 0x31b3c,
2308                 0x31b80, 0x31b80,
2309                 0x31ba8, 0x31ba8,
2310                 0x31bb0, 0x31bb4,
2311                 0x31bc8, 0x31bd4,
2312                 0x32140, 0x3218c,
2313                 0x321f0, 0x321f4,
2314                 0x32200, 0x32200,
2315                 0x32218, 0x32218,
2316                 0x32400, 0x32400,
2317                 0x32408, 0x3241c,
2318                 0x32618, 0x32620,
2319                 0x32664, 0x32664,
2320                 0x326a8, 0x326a8,
2321                 0x326ec, 0x326ec,
2322                 0x32a00, 0x32abc,
2323                 0x32b00, 0x32b38,
2324                 0x32b40, 0x32b58,
2325                 0x32b60, 0x32b78,
2326                 0x32c00, 0x32c00,
2327                 0x32c08, 0x32c3c,
2328                 0x32e00, 0x32e2c,
2329                 0x32f00, 0x32f2c,
2330                 0x33000, 0x3302c,
2331                 0x33034, 0x33050,
2332                 0x33058, 0x33058,
2333                 0x33060, 0x3308c,
2334                 0x3309c, 0x330ac,
2335                 0x330c0, 0x330c0,
2336                 0x330c8, 0x330d0,
2337                 0x330d8, 0x330e0,
2338                 0x330ec, 0x3312c,
2339                 0x33134, 0x33150,
2340                 0x33158, 0x33158,
2341                 0x33160, 0x3318c,
2342                 0x3319c, 0x331ac,
2343                 0x331c0, 0x331c0,
2344                 0x331c8, 0x331d0,
2345                 0x331d8, 0x331e0,
2346                 0x331ec, 0x33290,
2347                 0x33298, 0x332c4,
2348                 0x332e4, 0x33390,
2349                 0x33398, 0x333c4,
2350                 0x333e4, 0x3342c,
2351                 0x33434, 0x33450,
2352                 0x33458, 0x33458,
2353                 0x33460, 0x3348c,
2354                 0x3349c, 0x334ac,
2355                 0x334c0, 0x334c0,
2356                 0x334c8, 0x334d0,
2357                 0x334d8, 0x334e0,
2358                 0x334ec, 0x3352c,
2359                 0x33534, 0x33550,
2360                 0x33558, 0x33558,
2361                 0x33560, 0x3358c,
2362                 0x3359c, 0x335ac,
2363                 0x335c0, 0x335c0,
2364                 0x335c8, 0x335d0,
2365                 0x335d8, 0x335e0,
2366                 0x335ec, 0x33690,
2367                 0x33698, 0x336c4,
2368                 0x336e4, 0x33790,
2369                 0x33798, 0x337c4,
2370                 0x337e4, 0x337fc,
2371                 0x33814, 0x33814,
2372                 0x33854, 0x33868,
2373                 0x33880, 0x3388c,
2374                 0x338c0, 0x338d0,
2375                 0x338e8, 0x338ec,
2376                 0x33900, 0x3392c,
2377                 0x33934, 0x33950,
2378                 0x33958, 0x33958,
2379                 0x33960, 0x3398c,
2380                 0x3399c, 0x339ac,
2381                 0x339c0, 0x339c0,
2382                 0x339c8, 0x339d0,
2383                 0x339d8, 0x339e0,
2384                 0x339ec, 0x33a90,
2385                 0x33a98, 0x33ac4,
2386                 0x33ae4, 0x33b10,
2387                 0x33b24, 0x33b28,
2388                 0x33b38, 0x33b50,
2389                 0x33bf0, 0x33c10,
2390                 0x33c24, 0x33c28,
2391                 0x33c38, 0x33c50,
2392                 0x33cf0, 0x33cfc,
2393                 0x34000, 0x34030,
2394                 0x34038, 0x34038,
2395                 0x34040, 0x34040,
2396                 0x34048, 0x34048,
2397                 0x34050, 0x34050,
2398                 0x3405c, 0x34060,
2399                 0x34068, 0x34068,
2400                 0x34070, 0x34070,
2401                 0x34100, 0x34168,
2402                 0x34190, 0x341a0,
2403                 0x341a8, 0x341b8,
2404                 0x341c4, 0x341c8,
2405                 0x341d0, 0x341d0,
2406                 0x34200, 0x34320,
2407                 0x34400, 0x344b4,
2408                 0x344c0, 0x3452c,
2409                 0x34540, 0x3461c,
2410                 0x34800, 0x348a0,
2411                 0x348c0, 0x34908,
2412                 0x34910, 0x349b8,
2413                 0x34a00, 0x34a04,
2414                 0x34a0c, 0x34a14,
2415                 0x34a1c, 0x34a2c,
2416                 0x34a44, 0x34a50,
2417                 0x34a74, 0x34a74,
2418                 0x34a7c, 0x34afc,
2419                 0x34b08, 0x34c24,
2420                 0x34d00, 0x34d14,
2421                 0x34d1c, 0x34d3c,
2422                 0x34d44, 0x34d4c,
2423                 0x34d54, 0x34d74,
2424                 0x34d7c, 0x34d7c,
2425                 0x34de0, 0x34de0,
2426                 0x34e00, 0x34ed4,
2427                 0x34f00, 0x34fa4,
2428                 0x34fc0, 0x34fc4,
2429                 0x35000, 0x35004,
2430                 0x35080, 0x350fc,
2431                 0x35208, 0x35220,
2432                 0x3523c, 0x35254,
2433                 0x35300, 0x35300,
2434                 0x35308, 0x3531c,
2435                 0x35338, 0x3533c,
2436                 0x35380, 0x35380,
2437                 0x35388, 0x353a8,
2438                 0x353b4, 0x353b4,
2439                 0x35400, 0x35420,
2440                 0x35438, 0x3543c,
2441                 0x35480, 0x35480,
2442                 0x354a8, 0x354a8,
2443                 0x354b0, 0x354b4,
2444                 0x354c8, 0x354d4,
2445                 0x35a40, 0x35a4c,
2446                 0x35af0, 0x35b20,
2447                 0x35b38, 0x35b3c,
2448                 0x35b80, 0x35b80,
2449                 0x35ba8, 0x35ba8,
2450                 0x35bb0, 0x35bb4,
2451                 0x35bc8, 0x35bd4,
2452                 0x36140, 0x3618c,
2453                 0x361f0, 0x361f4,
2454                 0x36200, 0x36200,
2455                 0x36218, 0x36218,
2456                 0x36400, 0x36400,
2457                 0x36408, 0x3641c,
2458                 0x36618, 0x36620,
2459                 0x36664, 0x36664,
2460                 0x366a8, 0x366a8,
2461                 0x366ec, 0x366ec,
2462                 0x36a00, 0x36abc,
2463                 0x36b00, 0x36b38,
2464                 0x36b40, 0x36b58,
2465                 0x36b60, 0x36b78,
2466                 0x36c00, 0x36c00,
2467                 0x36c08, 0x36c3c,
2468                 0x36e00, 0x36e2c,
2469                 0x36f00, 0x36f2c,
2470                 0x37000, 0x3702c,
2471                 0x37034, 0x37050,
2472                 0x37058, 0x37058,
2473                 0x37060, 0x3708c,
2474                 0x3709c, 0x370ac,
2475                 0x370c0, 0x370c0,
2476                 0x370c8, 0x370d0,
2477                 0x370d8, 0x370e0,
2478                 0x370ec, 0x3712c,
2479                 0x37134, 0x37150,
2480                 0x37158, 0x37158,
2481                 0x37160, 0x3718c,
2482                 0x3719c, 0x371ac,
2483                 0x371c0, 0x371c0,
2484                 0x371c8, 0x371d0,
2485                 0x371d8, 0x371e0,
2486                 0x371ec, 0x37290,
2487                 0x37298, 0x372c4,
2488                 0x372e4, 0x37390,
2489                 0x37398, 0x373c4,
2490                 0x373e4, 0x3742c,
2491                 0x37434, 0x37450,
2492                 0x37458, 0x37458,
2493                 0x37460, 0x3748c,
2494                 0x3749c, 0x374ac,
2495                 0x374c0, 0x374c0,
2496                 0x374c8, 0x374d0,
2497                 0x374d8, 0x374e0,
2498                 0x374ec, 0x3752c,
2499                 0x37534, 0x37550,
2500                 0x37558, 0x37558,
2501                 0x37560, 0x3758c,
2502                 0x3759c, 0x375ac,
2503                 0x375c0, 0x375c0,
2504                 0x375c8, 0x375d0,
2505                 0x375d8, 0x375e0,
2506                 0x375ec, 0x37690,
2507                 0x37698, 0x376c4,
2508                 0x376e4, 0x37790,
2509                 0x37798, 0x377c4,
2510                 0x377e4, 0x377fc,
2511                 0x37814, 0x37814,
2512                 0x37854, 0x37868,
2513                 0x37880, 0x3788c,
2514                 0x378c0, 0x378d0,
2515                 0x378e8, 0x378ec,
2516                 0x37900, 0x3792c,
2517                 0x37934, 0x37950,
2518                 0x37958, 0x37958,
2519                 0x37960, 0x3798c,
2520                 0x3799c, 0x379ac,
2521                 0x379c0, 0x379c0,
2522                 0x379c8, 0x379d0,
2523                 0x379d8, 0x379e0,
2524                 0x379ec, 0x37a90,
2525                 0x37a98, 0x37ac4,
2526                 0x37ae4, 0x37b10,
2527                 0x37b24, 0x37b28,
2528                 0x37b38, 0x37b50,
2529                 0x37bf0, 0x37c10,
2530                 0x37c24, 0x37c28,
2531                 0x37c38, 0x37c50,
2532                 0x37cf0, 0x37cfc,
2533                 0x40040, 0x40040,
2534                 0x40080, 0x40084,
2535                 0x40100, 0x40100,
2536                 0x40140, 0x401bc,
2537                 0x40200, 0x40214,
2538                 0x40228, 0x40228,
2539                 0x40240, 0x40258,
2540                 0x40280, 0x40280,
2541                 0x40304, 0x40304,
2542                 0x40330, 0x4033c,
2543                 0x41304, 0x413c8,
2544                 0x413d0, 0x413dc,
2545                 0x413f0, 0x413f0,
2546                 0x41400, 0x4140c,
2547                 0x41414, 0x4141c,
2548                 0x41480, 0x414d0,
2549                 0x44000, 0x4407c,
2550                 0x440c0, 0x441ac,
2551                 0x441b4, 0x4427c,
2552                 0x442c0, 0x443ac,
2553                 0x443b4, 0x4447c,
2554                 0x444c0, 0x445ac,
2555                 0x445b4, 0x4467c,
2556                 0x446c0, 0x447ac,
2557                 0x447b4, 0x4487c,
2558                 0x448c0, 0x449ac,
2559                 0x449b4, 0x44a7c,
2560                 0x44ac0, 0x44bac,
2561                 0x44bb4, 0x44c7c,
2562                 0x44cc0, 0x44dac,
2563                 0x44db4, 0x44e7c,
2564                 0x44ec0, 0x44fac,
2565                 0x44fb4, 0x4507c,
2566                 0x450c0, 0x451ac,
2567                 0x451b4, 0x451fc,
2568                 0x45800, 0x45804,
2569                 0x45810, 0x45830,
2570                 0x45840, 0x45860,
2571                 0x45868, 0x45868,
2572                 0x45880, 0x45884,
2573                 0x458a0, 0x458b0,
2574                 0x45a00, 0x45a04,
2575                 0x45a10, 0x45a30,
2576                 0x45a40, 0x45a60,
2577                 0x45a68, 0x45a68,
2578                 0x45a80, 0x45a84,
2579                 0x45aa0, 0x45ab0,
2580                 0x460c0, 0x460e4,
2581                 0x47000, 0x4703c,
2582                 0x47044, 0x4708c,
2583                 0x47200, 0x47250,
2584                 0x47400, 0x47408,
2585                 0x47414, 0x47420,
2586                 0x47600, 0x47618,
2587                 0x47800, 0x47814,
2588                 0x47820, 0x4782c,
2589                 0x50000, 0x50084,
2590                 0x50090, 0x500cc,
2591                 0x50300, 0x50384,
2592                 0x50400, 0x50400,
2593                 0x50800, 0x50884,
2594                 0x50890, 0x508cc,
2595                 0x50b00, 0x50b84,
2596                 0x50c00, 0x50c00,
2597                 0x51000, 0x51020,
2598                 0x51028, 0x510b0,
2599                 0x51300, 0x51324,
2600         };
2601
2602         static const unsigned int t6vf_reg_ranges[] = {
2603                 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2604                 VF_MPS_REG(A_MPS_VF_CTL),
2605                 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2606                 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2607                 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2608                 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2609                 FW_T6VF_MBDATA_BASE_ADDR,
2610                 FW_T6VF_MBDATA_BASE_ADDR +
2611                 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2612         };
2613
2614         u32 *buf_end = (u32 *)(buf + buf_size);
2615         const unsigned int *reg_ranges;
2616         int reg_ranges_size, range;
2617         unsigned int chip_version = chip_id(adap);
2618
2619         /*
2620          * Select the right set of register ranges to dump depending on the
2621          * adapter chip type.
2622          */
2623         switch (chip_version) {
2624         case CHELSIO_T4:
2625                 if (adap->flags & IS_VF) {
2626                         reg_ranges = t4vf_reg_ranges;
2627                         reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2628                 } else {
2629                         reg_ranges = t4_reg_ranges;
2630                         reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2631                 }
2632                 break;
2633
2634         case CHELSIO_T5:
2635                 if (adap->flags & IS_VF) {
2636                         reg_ranges = t5vf_reg_ranges;
2637                         reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2638                 } else {
2639                         reg_ranges = t5_reg_ranges;
2640                         reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2641                 }
2642                 break;
2643
2644         case CHELSIO_T6:
2645                 if (adap->flags & IS_VF) {
2646                         reg_ranges = t6vf_reg_ranges;
2647                         reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2648                 } else {
2649                         reg_ranges = t6_reg_ranges;
2650                         reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2651                 }
2652                 break;
2653
2654         default:
2655                 CH_ERR(adap,
2656                         "Unsupported chip version %d\n", chip_version);
2657                 return;
2658         }
2659
2660         /*
2661          * Clear the register buffer and insert the appropriate register
2662          * values selected by the above register ranges.
2663          */
2664         memset(buf, 0, buf_size);
2665         for (range = 0; range < reg_ranges_size; range += 2) {
2666                 unsigned int reg = reg_ranges[range];
2667                 unsigned int last_reg = reg_ranges[range + 1];
2668                 u32 *bufp = (u32 *)(buf + reg);
2669
2670                 /*
2671                  * Iterate across the register range filling in the register
2672                  * buffer but don't write past the end of the register buffer.
2673                  */
2674                 while (reg <= last_reg && bufp < buf_end) {
2675                         *bufp++ = t4_read_reg(adap, reg);
2676                         reg += sizeof(u32);
2677                 }
2678         }
2679 }
2680
2681 /*
2682  * Partial EEPROM Vital Product Data structure.  Includes only the ID and
2683  * VPD-R sections.
2684  */
2685 struct t4_vpd_hdr {
2686         u8  id_tag;
2687         u8  id_len[2];
2688         u8  id_data[ID_LEN];
2689         u8  vpdr_tag;
2690         u8  vpdr_len[2];
2691 };
2692
2693 /*
2694  * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2695  */
2696 #define EEPROM_DELAY            10              /* 10us per poll spin */
2697 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
2698
2699 #define EEPROM_STAT_ADDR        0x7bfc
2700 #define VPD_BASE                0x400
2701 #define VPD_BASE_OLD            0
2702 #define VPD_LEN                 1024
2703 #define VPD_INFO_FLD_HDR_SIZE   3
2704 #define CHELSIO_VPD_UNIQUE_ID   0x82
2705
2706 /*
2707  * Small utility function to wait till any outstanding VPD Access is complete.
2708  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2709  * VPD Access in flight.  This allows us to handle the problem of having a
2710  * previous VPD Access time out and prevent an attempt to inject a new VPD
2711  * Request before any in-flight VPD reguest has completed.
2712  */
2713 static int t4_seeprom_wait(struct adapter *adapter)
2714 {
2715         unsigned int base = adapter->params.pci.vpd_cap_addr;
2716         int max_poll;
2717
2718         /*
2719          * If no VPD Access is in flight, we can just return success right
2720          * away.
2721          */
2722         if (!adapter->vpd_busy)
2723                 return 0;
2724
2725         /*
2726          * Poll the VPD Capability Address/Flag register waiting for it
2727          * to indicate that the operation is complete.
2728          */
2729         max_poll = EEPROM_MAX_POLL;
2730         do {
2731                 u16 val;
2732
2733                 udelay(EEPROM_DELAY);
2734                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2735
2736                 /*
2737                  * If the operation is complete, mark the VPD as no longer
2738                  * busy and return success.
2739                  */
2740                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2741                         adapter->vpd_busy = 0;
2742                         return 0;
2743                 }
2744         } while (--max_poll);
2745
2746         /*
2747          * Failure!  Note that we leave the VPD Busy status set in order to
2748          * avoid pushing a new VPD Access request into the VPD Capability till
2749          * the current operation eventually succeeds.  It's a bug to issue a
2750          * new request when an existing request is in flight and will result
2751          * in corrupt hardware state.
2752          */
2753         return -ETIMEDOUT;
2754 }
2755
2756 /**
2757  *      t4_seeprom_read - read a serial EEPROM location
2758  *      @adapter: adapter to read
2759  *      @addr: EEPROM virtual address
2760  *      @data: where to store the read data
2761  *
2762  *      Read a 32-bit word from a location in serial EEPROM using the card's PCI
2763  *      VPD capability.  Note that this function must be called with a virtual
2764  *      address.
2765  */
2766 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2767 {
2768         unsigned int base = adapter->params.pci.vpd_cap_addr;
2769         int ret;
2770
2771         /*
2772          * VPD Accesses must alway be 4-byte aligned!
2773          */
2774         if (addr >= EEPROMVSIZE || (addr & 3))
2775                 return -EINVAL;
2776
2777         /*
2778          * Wait for any previous operation which may still be in flight to
2779          * complete.
2780          */
2781         ret = t4_seeprom_wait(adapter);
2782         if (ret) {
2783                 CH_ERR(adapter, "VPD still busy from previous operation\n");
2784                 return ret;
2785         }
2786
2787         /*
2788          * Issue our new VPD Read request, mark the VPD as being busy and wait
2789          * for our request to complete.  If it doesn't complete, note the
2790          * error and return it to our caller.  Note that we do not reset the
2791          * VPD Busy status!
2792          */
2793         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2794         adapter->vpd_busy = 1;
2795         adapter->vpd_flag = PCI_VPD_ADDR_F;
2796         ret = t4_seeprom_wait(adapter);
2797         if (ret) {
2798                 CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2799                 return ret;
2800         }
2801
2802         /*
2803          * Grab the returned data, swizzle it into our endianess and
2804          * return success.
2805          */
2806         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2807         *data = le32_to_cpu(*data);
2808         return 0;
2809 }
2810
2811 /**
2812  *      t4_seeprom_write - write a serial EEPROM location
2813  *      @adapter: adapter to write
2814  *      @addr: virtual EEPROM address
2815  *      @data: value to write
2816  *
2817  *      Write a 32-bit word to a location in serial EEPROM using the card's PCI
2818  *      VPD capability.  Note that this function must be called with a virtual
2819  *      address.
2820  */
2821 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2822 {
2823         unsigned int base = adapter->params.pci.vpd_cap_addr;
2824         int ret;
2825         u32 stats_reg;
2826         int max_poll;
2827
2828         /*
2829          * VPD Accesses must alway be 4-byte aligned!
2830          */
2831         if (addr >= EEPROMVSIZE || (addr & 3))
2832                 return -EINVAL;
2833
2834         /*
2835          * Wait for any previous operation which may still be in flight to
2836          * complete.
2837          */
2838         ret = t4_seeprom_wait(adapter);
2839         if (ret) {
2840                 CH_ERR(adapter, "VPD still busy from previous operation\n");
2841                 return ret;
2842         }
2843
2844         /*
2845          * Issue our new VPD Read request, mark the VPD as being busy and wait
2846          * for our request to complete.  If it doesn't complete, note the
2847          * error and return it to our caller.  Note that we do not reset the
2848          * VPD Busy status!
2849          */
2850         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2851                                  cpu_to_le32(data));
2852         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2853                                  (u16)addr | PCI_VPD_ADDR_F);
2854         adapter->vpd_busy = 1;
2855         adapter->vpd_flag = 0;
2856         ret = t4_seeprom_wait(adapter);
2857         if (ret) {
2858                 CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2859                 return ret;
2860         }
2861
2862         /*
2863          * Reset PCI_VPD_DATA register after a transaction and wait for our
2864          * request to complete. If it doesn't complete, return error.
2865          */
2866         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2867         max_poll = EEPROM_MAX_POLL;
2868         do {
2869                 udelay(EEPROM_DELAY);
2870                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2871         } while ((stats_reg & 0x1) && --max_poll);
2872         if (!max_poll)
2873                 return -ETIMEDOUT;
2874
2875         /* Return success! */
2876         return 0;
2877 }
2878
2879 /**
2880  *      t4_eeprom_ptov - translate a physical EEPROM address to virtual
2881  *      @phys_addr: the physical EEPROM address
2882  *      @fn: the PCI function number
2883  *      @sz: size of function-specific area
2884  *
2885  *      Translate a physical EEPROM address to virtual.  The first 1K is
2886  *      accessed through virtual addresses starting at 31K, the rest is
2887  *      accessed through virtual addresses starting at 0.
2888  *
2889  *      The mapping is as follows:
2890  *      [0..1K) -> [31K..32K)
2891  *      [1K..1K+A) -> [ES-A..ES)
2892  *      [1K+A..ES) -> [0..ES-A-1K)
2893  *
2894  *      where A = @fn * @sz, and ES = EEPROM size.
2895  */
2896 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2897 {
2898         fn *= sz;
2899         if (phys_addr < 1024)
2900                 return phys_addr + (31 << 10);
2901         if (phys_addr < 1024 + fn)
2902                 return EEPROMSIZE - fn + phys_addr - 1024;
2903         if (phys_addr < EEPROMSIZE)
2904                 return phys_addr - 1024 - fn;
2905         return -EINVAL;
2906 }
2907
2908 /**
2909  *      t4_seeprom_wp - enable/disable EEPROM write protection
2910  *      @adapter: the adapter
2911  *      @enable: whether to enable or disable write protection
2912  *
2913  *      Enables or disables write protection on the serial EEPROM.
2914  */
2915 int t4_seeprom_wp(struct adapter *adapter, int enable)
2916 {
2917         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2918 }
2919
2920 /**
2921  *      get_vpd_keyword_val - Locates an information field keyword in the VPD
2922  *      @v: Pointer to buffered vpd data structure
2923  *      @kw: The keyword to search for
2924  *
2925  *      Returns the value of the information field keyword or
2926  *      -ENOENT otherwise.
2927  */
2928 static int get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw)
2929 {
2930         int i;
2931         unsigned int offset , len;
2932         const u8 *buf = (const u8 *)v;
2933         const u8 *vpdr_len = &v->vpdr_len[0];
2934         offset = sizeof(struct t4_vpd_hdr);
2935         len =  (u16)vpdr_len[0] + ((u16)vpdr_len[1] << 8);
2936
2937         if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) {
2938                 return -ENOENT;
2939         }
2940
2941         for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2942                 if(memcmp(buf + i , kw , 2) == 0){
2943                         i += VPD_INFO_FLD_HDR_SIZE;
2944                         return i;
2945                 }
2946
2947                 i += VPD_INFO_FLD_HDR_SIZE + buf[i+2];
2948         }
2949
2950         return -ENOENT;
2951 }
2952
2953
2954 /**
2955  *      get_vpd_params - read VPD parameters from VPD EEPROM
2956  *      @adapter: adapter to read
2957  *      @p: where to store the parameters
2958  *      @vpd: caller provided temporary space to read the VPD into
2959  *
2960  *      Reads card parameters stored in VPD EEPROM.
2961  */
2962 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
2963     u8 *vpd)
2964 {
2965         int i, ret, addr;
2966         int ec, sn, pn, na;
2967         u8 csum;
2968         const struct t4_vpd_hdr *v;
2969
2970         /*
2971          * Card information normally starts at VPD_BASE but early cards had
2972          * it at 0.
2973          */
2974         ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd));
2975         if (ret)
2976                 return (ret);
2977
2978         /*
2979          * The VPD shall have a unique identifier specified by the PCI SIG.
2980          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2981          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2982          * is expected to automatically put this entry at the
2983          * beginning of the VPD.
2984          */
2985         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2986
2987         for (i = 0; i < VPD_LEN; i += 4) {
2988                 ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i));
2989                 if (ret)
2990                         return ret;
2991         }
2992         v = (const struct t4_vpd_hdr *)vpd;
2993
2994 #define FIND_VPD_KW(var,name) do { \
2995         var = get_vpd_keyword_val(v , name); \
2996         if (var < 0) { \
2997                 CH_ERR(adapter, "missing VPD keyword " name "\n"); \
2998                 return -EINVAL; \
2999         } \
3000 } while (0)
3001
3002         FIND_VPD_KW(i, "RV");
3003         for (csum = 0; i >= 0; i--)
3004                 csum += vpd[i];
3005
3006         if (csum) {
3007                 CH_ERR(adapter,
3008                         "corrupted VPD EEPROM, actual csum %u\n", csum);
3009                 return -EINVAL;
3010         }
3011
3012         FIND_VPD_KW(ec, "EC");
3013         FIND_VPD_KW(sn, "SN");
3014         FIND_VPD_KW(pn, "PN");
3015         FIND_VPD_KW(na, "NA");
3016 #undef FIND_VPD_KW
3017
3018         memcpy(p->id, v->id_data, ID_LEN);
3019         strstrip(p->id);
3020         memcpy(p->ec, vpd + ec, EC_LEN);
3021         strstrip(p->ec);
3022         i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3023         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3024         strstrip(p->sn);
3025         i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3026         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3027         strstrip((char *)p->pn);
3028         i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3029         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3030         strstrip((char *)p->na);
3031
3032         return 0;
3033 }
3034
3035 /* serial flash and firmware constants and flash config file constants */
3036 enum {
3037         SF_ATTEMPTS = 10,       /* max retries for SF operations */
3038
3039         /* flash command opcodes */
3040         SF_PROG_PAGE    = 2,    /* program page */
3041         SF_WR_DISABLE   = 4,    /* disable writes */
3042         SF_RD_STATUS    = 5,    /* read status register */
3043         SF_WR_ENABLE    = 6,    /* enable writes */
3044         SF_RD_DATA_FAST = 0xb,  /* read flash */
3045         SF_RD_ID        = 0x9f, /* read ID */
3046         SF_ERASE_SECTOR = 0xd8, /* erase sector */
3047 };
3048
3049 /**
3050  *      sf1_read - read data from the serial flash
3051  *      @adapter: the adapter
3052  *      @byte_cnt: number of bytes to read
3053  *      @cont: whether another operation will be chained
3054  *      @lock: whether to lock SF for PL access only
3055  *      @valp: where to store the read data
3056  *
3057  *      Reads up to 4 bytes of data from the serial flash.  The location of
3058  *      the read needs to be specified prior to calling this by issuing the
3059  *      appropriate commands to the serial flash.
3060  */
3061 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3062                     int lock, u32 *valp)
3063 {
3064         int ret;
3065
3066         if (!byte_cnt || byte_cnt > 4)
3067                 return -EINVAL;
3068         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3069                 return -EBUSY;
3070         t4_write_reg(adapter, A_SF_OP,
3071                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3072         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3073         if (!ret)
3074                 *valp = t4_read_reg(adapter, A_SF_DATA);
3075         return ret;
3076 }
3077
3078 /**
3079  *      sf1_write - write data to the serial flash
3080  *      @adapter: the adapter
3081  *      @byte_cnt: number of bytes to write
3082  *      @cont: whether another operation will be chained
3083  *      @lock: whether to lock SF for PL access only
3084  *      @val: value to write
3085  *
3086  *      Writes up to 4 bytes of data to the serial flash.  The location of
3087  *      the write needs to be specified prior to calling this by issuing the
3088  *      appropriate commands to the serial flash.
3089  */
3090 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3091                      int lock, u32 val)
3092 {
3093         if (!byte_cnt || byte_cnt > 4)
3094                 return -EINVAL;
3095         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3096                 return -EBUSY;
3097         t4_write_reg(adapter, A_SF_DATA, val);
3098         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3099                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3100         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3101 }
3102
3103 /**
3104  *      flash_wait_op - wait for a flash operation to complete
3105  *      @adapter: the adapter
3106  *      @attempts: max number of polls of the status register
3107  *      @delay: delay between polls in ms
3108  *
3109  *      Wait for a flash operation to complete by polling the status register.
3110  */
3111 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3112 {
3113         int ret;
3114         u32 status;
3115
3116         while (1) {
3117                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3118                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3119                         return ret;
3120                 if (!(status & 1))
3121                         return 0;
3122                 if (--attempts == 0)
3123                         return -EAGAIN;
3124                 if (delay)
3125                         msleep(delay);
3126         }
3127 }
3128
3129 /**
3130  *      t4_read_flash - read words from serial flash
3131  *      @adapter: the adapter
3132  *      @addr: the start address for the read
3133  *      @nwords: how many 32-bit words to read
3134  *      @data: where to store the read data
3135  *      @byte_oriented: whether to store data as bytes or as words
3136  *
3137  *      Read the specified number of 32-bit words from the serial flash.
3138  *      If @byte_oriented is set the read data is stored as a byte array
3139  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
3140  *      natural endianness.
3141  */
3142 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3143                   unsigned int nwords, u32 *data, int byte_oriented)
3144 {
3145         int ret;
3146
3147         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3148                 return -EINVAL;
3149
3150         addr = swab32(addr) | SF_RD_DATA_FAST;
3151
3152         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3153             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3154                 return ret;
3155
3156         for ( ; nwords; nwords--, data++) {
3157                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3158                 if (nwords == 1)
3159                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3160                 if (ret)
3161                         return ret;
3162                 if (byte_oriented)
3163                         *data = (__force __u32)(cpu_to_be32(*data));
3164         }
3165         return 0;
3166 }
3167
3168 /**
3169  *      t4_write_flash - write up to a page of data to the serial flash
3170  *      @adapter: the adapter
3171  *      @addr: the start address to write
3172  *      @n: length of data to write in bytes
3173  *      @data: the data to write
3174  *      @byte_oriented: whether to store data as bytes or as words
3175  *
3176  *      Writes up to a page of data (256 bytes) to the serial flash starting
3177  *      at the given address.  All the data must be written to the same page.
3178  *      If @byte_oriented is set the write data is stored as byte stream
3179  *      (i.e. matches what on disk), otherwise in big-endian.
3180  */
3181 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3182                           unsigned int n, const u8 *data, int byte_oriented)
3183 {
3184         int ret;
3185         u32 buf[SF_PAGE_SIZE / 4];
3186         unsigned int i, c, left, val, offset = addr & 0xff;
3187
3188         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3189                 return -EINVAL;
3190
3191         val = swab32(addr) | SF_PROG_PAGE;
3192
3193         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3194             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3195                 goto unlock;
3196
3197         for (left = n; left; left -= c) {
3198                 c = min(left, 4U);
3199                 for (val = 0, i = 0; i < c; ++i)
3200                         val = (val << 8) + *data++;
3201
3202                 if (!byte_oriented)
3203                         val = cpu_to_be32(val);
3204
3205                 ret = sf1_write(adapter, c, c != left, 1, val);
3206                 if (ret)
3207                         goto unlock;
3208         }
3209         ret = flash_wait_op(adapter, 8, 1);
3210         if (ret)
3211                 goto unlock;
3212
3213         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3214
3215         /* Read the page to verify the write succeeded */
3216         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3217                             byte_oriented);
3218         if (ret)
3219                 return ret;
3220
3221         if (memcmp(data - n, (u8 *)buf + offset, n)) {
3222                 CH_ERR(adapter,
3223                         "failed to correctly write the flash page at %#x\n",
3224                         addr);
3225                 return -EIO;
3226         }
3227         return 0;
3228
3229 unlock:
3230         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3231         return ret;
3232 }
3233
3234 /**
3235  *      t4_get_fw_version - read the firmware version
3236  *      @adapter: the adapter
3237  *      @vers: where to place the version
3238  *
3239  *      Reads the FW version from flash.
3240  */
3241 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3242 {
3243         return t4_read_flash(adapter, FLASH_FW_START +
3244                              offsetof(struct fw_hdr, fw_ver), 1,
3245                              vers, 0);
3246 }
3247
3248 /**
3249  *      t4_get_bs_version - read the firmware bootstrap version
3250  *      @adapter: the adapter
3251  *      @vers: where to place the version
3252  *
3253  *      Reads the FW Bootstrap version from flash.
3254  */
3255 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3256 {
3257         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3258                              offsetof(struct fw_hdr, fw_ver), 1,
3259                              vers, 0);
3260 }
3261
3262 /**
3263  *      t4_get_tp_version - read the TP microcode version
3264  *      @adapter: the adapter
3265  *      @vers: where to place the version
3266  *
3267  *      Reads the TP microcode version from flash.
3268  */
3269 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3270 {
3271         return t4_read_flash(adapter, FLASH_FW_START +
3272                              offsetof(struct fw_hdr, tp_microcode_ver),
3273                              1, vers, 0);
3274 }
3275
3276 /**
3277  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3278  *      @adapter: the adapter
3279  *      @vers: where to place the version
3280  *
3281  *      Reads the Expansion ROM header from FLASH and returns the version
3282  *      number (if present) through the @vers return value pointer.  We return
3283  *      this in the Firmware Version Format since it's convenient.  Return
3284  *      0 on success, -ENOENT if no Expansion ROM is present.
3285  */
3286 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3287 {
3288         struct exprom_header {
3289                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3290                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3291         } *hdr;
3292         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3293                                            sizeof(u32))];
3294         int ret;
3295
3296         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3297                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3298                             0);
3299         if (ret)
3300                 return ret;
3301
3302         hdr = (struct exprom_header *)exprom_header_buf;
3303         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3304                 return -ENOENT;
3305
3306         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3307                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3308                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3309                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3310         return 0;
3311 }
3312
3313 /**
3314  *      t4_get_scfg_version - return the Serial Configuration version
3315  *      @adapter: the adapter
3316  *      @vers: where to place the version
3317  *
3318  *      Reads the Serial Configuration Version via the Firmware interface
3319  *      (thus this can only be called once we're ready to issue Firmware
3320  *      commands).  The format of the Serial Configuration version is
3321  *      adapter specific.  Returns 0 on success, an error on failure.
3322  *
3323  *      Note that early versions of the Firmware didn't include the ability
3324  *      to retrieve the Serial Configuration version, so we zero-out the
3325  *      return-value parameter in that case to avoid leaving it with
3326  *      garbage in it.
3327  *
3328  *      Also note that the Firmware will return its cached copy of the Serial
3329  *      Initialization Revision ID, not the actual Revision ID as written in
3330  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3331  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3332  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3333  *      been issued if the Host Driver will be performing a full adapter
3334  *      initialization.
3335  */
3336 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3337 {
3338         u32 scfgrev_param;
3339         int ret;
3340
3341         scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3342                          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3343         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3344                               1, &scfgrev_param, vers);
3345         if (ret)
3346                 *vers = 0;
3347         return ret;
3348 }
3349
3350 /**
3351  *      t4_get_vpd_version - return the VPD version
3352  *      @adapter: the adapter
3353  *      @vers: where to place the version
3354  *
3355  *      Reads the VPD via the Firmware interface (thus this can only be called
3356  *      once we're ready to issue Firmware commands).  The format of the
3357  *      VPD version is adapter specific.  Returns 0 on success, an error on
3358  *      failure.
3359  *
3360  *      Note that early versions of the Firmware didn't include the ability
3361  *      to retrieve the VPD version, so we zero-out the return-value parameter
3362  *      in that case to avoid leaving it with garbage in it.
3363  *
3364  *      Also note that the Firmware will return its cached copy of the VPD
3365  *      Revision ID, not the actual Revision ID as written in the Serial
3366  *      EEPROM.  This is only an issue if a new VPD has been written and the
3367  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3368  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3369  *      if the Host Driver will be performing a full adapter initialization.
3370  */
3371 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3372 {
3373         u32 vpdrev_param;
3374         int ret;
3375
3376         vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3377                         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3378         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3379                               1, &vpdrev_param, vers);
3380         if (ret)
3381                 *vers = 0;
3382         return ret;
3383 }
3384
3385 /**
3386  *      t4_get_version_info - extract various chip/firmware version information
3387  *      @adapter: the adapter
3388  *
3389  *      Reads various chip/firmware version numbers and stores them into the
3390  *      adapter Adapter Parameters structure.  If any of the efforts fails
3391  *      the first failure will be returned, but all of the version numbers
3392  *      will be read.
3393  */
3394 int t4_get_version_info(struct adapter *adapter)
3395 {
3396         int ret = 0;
3397
3398         #define FIRST_RET(__getvinfo) \
3399         do { \
3400                 int __ret = __getvinfo; \
3401                 if (__ret && !ret) \
3402                         ret = __ret; \
3403         } while (0)
3404
3405         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3406         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3407         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3408         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3409         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3410         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3411
3412         #undef FIRST_RET
3413
3414         return ret;
3415 }
3416
3417 /**
3418  *      t4_flash_erase_sectors - erase a range of flash sectors
3419  *      @adapter: the adapter
3420  *      @start: the first sector to erase
3421  *      @end: the last sector to erase
3422  *
3423  *      Erases the sectors in the given inclusive range.
3424  */
3425 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3426 {
3427         int ret = 0;
3428
3429         if (end >= adapter->params.sf_nsec)
3430                 return -EINVAL;
3431
3432         while (start <= end) {
3433                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3434                     (ret = sf1_write(adapter, 4, 0, 1,
3435                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3436                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3437                         CH_ERR(adapter,
3438                                 "erase of flash sector %d failed, error %d\n",
3439                                 start, ret);
3440                         break;
3441                 }
3442                 start++;
3443         }
3444         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3445         return ret;
3446 }
3447
3448 /**
3449  *      t4_flash_cfg_addr - return the address of the flash configuration file
3450  *      @adapter: the adapter
3451  *
3452  *      Return the address within the flash where the Firmware Configuration
3453  *      File is stored, or an error if the device FLASH is too small to contain
3454  *      a Firmware Configuration File.
3455  */
3456 int t4_flash_cfg_addr(struct adapter *adapter)
3457 {
3458         /*
3459          * If the device FLASH isn't large enough to hold a Firmware
3460          * Configuration File, return an error.
3461          */
3462         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3463                 return -ENOSPC;
3464
3465         return FLASH_CFG_START;
3466 }
3467
3468 /*
3469  * Return TRUE if the specified firmware matches the adapter.  I.e. T4
3470  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3471  * and emit an error message for mismatched firmware to save our caller the
3472  * effort ...
3473  */
3474 static int t4_fw_matches_chip(struct adapter *adap,
3475                               const struct fw_hdr *hdr)
3476 {
3477         /*
3478          * The expression below will return FALSE for any unsupported adapter
3479          * which will keep us "honest" in the future ...
3480          */
3481         if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3482             (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3483             (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3484                 return 1;
3485
3486         CH_ERR(adap,
3487                 "FW image (%d) is not suitable for this adapter (%d)\n",
3488                 hdr->chip, chip_id(adap));
3489         return 0;
3490 }
3491
3492 /**
3493  *      t4_load_fw - download firmware
3494  *      @adap: the adapter
3495  *      @fw_data: the firmware image to write
3496  *      @size: image size
3497  *
3498  *      Write the supplied firmware image to the card's serial flash.
3499  */
3500 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3501 {
3502         u32 csum;
3503         int ret, addr;
3504         unsigned int i;
3505         u8 first_page[SF_PAGE_SIZE];
3506         const u32 *p = (const u32 *)fw_data;
3507         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3508         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3509         unsigned int fw_start_sec;
3510         unsigned int fw_start;
3511         unsigned int fw_size;
3512
3513         if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3514                 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3515                 fw_start = FLASH_FWBOOTSTRAP_START;
3516                 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3517         } else {
3518                 fw_start_sec = FLASH_FW_START_SEC;
3519                 fw_start = FLASH_FW_START;
3520                 fw_size = FLASH_FW_MAX_SIZE;
3521         }
3522
3523         if (!size) {
3524                 CH_ERR(adap, "FW image has no data\n");
3525                 return -EINVAL;
3526         }
3527         if (size & 511) {
3528                 CH_ERR(adap,
3529                         "FW image size not multiple of 512 bytes\n");
3530                 return -EINVAL;
3531         }
3532         if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3533                 CH_ERR(adap,
3534                         "FW image size differs from size in FW header\n");
3535                 return -EINVAL;
3536         }
3537         if (size > fw_size) {
3538                 CH_ERR(adap, "FW image too large, max is %u bytes\n",
3539                         fw_size);
3540                 return -EFBIG;
3541         }
3542         if (!t4_fw_matches_chip(adap, hdr))
3543                 return -EINVAL;
3544
3545         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3546                 csum += be32_to_cpu(p[i]);
3547
3548         if (csum != 0xffffffff) {
3549                 CH_ERR(adap,
3550                         "corrupted firmware image, checksum %#x\n", csum);
3551                 return -EINVAL;
3552         }
3553
3554         i = DIV_ROUND_UP(size, sf_sec_size);    /* # of sectors spanned */
3555         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3556         if (ret)
3557                 goto out;
3558
3559         /*
3560          * We write the correct version at the end so the driver can see a bad
3561          * version if the FW write fails.  Start by writing a copy of the
3562          * first page with a bad version.
3563          */
3564         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3565         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3566         ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3567         if (ret)
3568                 goto out;
3569
3570         addr = fw_start;
3571         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3572                 addr += SF_PAGE_SIZE;
3573                 fw_data += SF_PAGE_SIZE;
3574                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3575                 if (ret)
3576                         goto out;
3577         }
3578
3579         ret = t4_write_flash(adap,
3580                              fw_start + offsetof(struct fw_hdr, fw_ver),
3581                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3582 out:
3583         if (ret)
3584                 CH_ERR(adap, "firmware download failed, error %d\n",
3585                         ret);
3586         return ret;
3587 }
3588
3589 /**
3590  *      t4_fwcache - firmware cache operation
3591  *      @adap: the adapter
3592  *      @op  : the operation (flush or flush and invalidate)
3593  */
3594 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3595 {
3596         struct fw_params_cmd c;
3597
3598         memset(&c, 0, sizeof(c));
3599         c.op_to_vfn =
3600             cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3601                             F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3602                                 V_FW_PARAMS_CMD_PFN(adap->pf) |
3603                                 V_FW_PARAMS_CMD_VFN(0));
3604         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3605         c.param[0].mnem =
3606             cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3607                             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3608         c.param[0].val = (__force __be32)op;
3609
3610         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3611 }
3612
3613 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3614                         unsigned int *pif_req_wrptr,
3615                         unsigned int *pif_rsp_wrptr)
3616 {
3617         int i, j;
3618         u32 cfg, val, req, rsp;
3619
3620         cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3621         if (cfg & F_LADBGEN)
3622                 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3623
3624         val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3625         req = G_POLADBGWRPTR(val);
3626         rsp = G_PILADBGWRPTR(val);
3627         if (pif_req_wrptr)
3628                 *pif_req_wrptr = req;
3629         if (pif_rsp_wrptr)
3630                 *pif_rsp_wrptr = rsp;
3631
3632         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3633                 for (j = 0; j < 6; j++) {
3634                         t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3635                                      V_PILADBGRDPTR(rsp));
3636                         *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3637                         *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3638                         req++;
3639                         rsp++;
3640                 }
3641                 req = (req + 2) & M_POLADBGRDPTR;
3642                 rsp = (rsp + 2) & M_PILADBGRDPTR;
3643         }
3644         t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3645 }
3646
3647 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3648 {
3649         u32 cfg;
3650         int i, j, idx;
3651
3652         cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3653         if (cfg & F_LADBGEN)
3654                 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3655
3656         for (i = 0; i < CIM_MALA_SIZE; i++) {
3657                 for (j = 0; j < 5; j++) {
3658                         idx = 8 * i + j;
3659                         t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3660                                      V_PILADBGRDPTR(idx));
3661                         *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3662                         *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3663                 }
3664         }
3665         t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3666 }
3667
3668 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3669 {
3670         unsigned int i, j;
3671
3672         for (i = 0; i < 8; i++) {
3673                 u32 *p = la_buf + i;
3674
3675                 t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3676                 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3677                 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3678                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3679                         *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3680         }
3681 }
3682
3683 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
3684                      FW_PORT_CAP_ANEG)
3685
3686 /**
3687  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3688  *      @phy: the PHY to setup
3689  *      @mac: the MAC to setup
3690  *      @lc: the requested link configuration
3691  *
3692  *      Set up a port's MAC and PHY according to a desired link configuration.
3693  *      - If the PHY can auto-negotiate first decide what to advertise, then
3694  *        enable/disable auto-negotiation as desired, and reset.
3695  *      - If the PHY does not auto-negotiate just reset it.
3696  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3697  *        otherwise do it later based on the outcome of auto-negotiation.
3698  */
3699 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3700                   struct link_config *lc)
3701 {
3702         struct fw_port_cmd c;
3703         unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
3704         unsigned int fc, fec;
3705
3706         fc = 0;
3707         if (lc->requested_fc & PAUSE_RX)
3708                 fc |= FW_PORT_CAP_FC_RX;
3709         if (lc->requested_fc & PAUSE_TX)
3710                 fc |= FW_PORT_CAP_FC_TX;
3711
3712         fec = 0;
3713         if (lc->requested_fec & FEC_RS)
3714                 fec |= FW_PORT_CAP_FEC_RS;
3715         if (lc->requested_fec & FEC_BASER_RS)
3716                 fec |= FW_PORT_CAP_FEC_BASER_RS;
3717         if (lc->requested_fec & FEC_RESERVED)
3718                 fec |= FW_PORT_CAP_FEC_RESERVED;
3719
3720         memset(&c, 0, sizeof(c));
3721         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3722                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3723                                      V_FW_PORT_CMD_PORTID(port));
3724         c.action_to_len16 =
3725                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3726                             FW_LEN16(c));
3727
3728         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3729                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3730                                              fc | fec);
3731                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
3732                 lc->fec = lc->requested_fec;
3733         } else if (lc->autoneg == AUTONEG_DISABLE) {
3734                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed |
3735                                              fc | fec | mdi);
3736                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
3737                 lc->fec = lc->requested_fec;
3738         } else
3739                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
3740
3741         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3742 }
3743
3744 /**
3745  *      t4_restart_aneg - restart autonegotiation
3746  *      @adap: the adapter
3747  *      @mbox: mbox to use for the FW command
3748  *      @port: the port id
3749  *
3750  *      Restarts autonegotiation for the selected port.
3751  */
3752 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3753 {
3754         struct fw_port_cmd c;
3755
3756         memset(&c, 0, sizeof(c));
3757         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3758                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3759                                      V_FW_PORT_CMD_PORTID(port));
3760         c.action_to_len16 =
3761                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3762                             FW_LEN16(c));
3763         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3764         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3765 }
3766
3767 typedef void (*int_handler_t)(struct adapter *adap);
3768
3769 struct intr_info {
3770         unsigned int mask;      /* bits to check in interrupt status */
3771         const char *msg;        /* message to print or NULL */
3772         short stat_idx;         /* stat counter to increment or -1 */
3773         unsigned short fatal;   /* whether the condition reported is fatal */
3774         int_handler_t int_handler;      /* platform-specific int handler */
3775 };
3776
3777 /**
3778  *      t4_handle_intr_status - table driven interrupt handler
3779  *      @adapter: the adapter that generated the interrupt
3780  *      @reg: the interrupt status register to process
3781  *      @acts: table of interrupt actions
3782  *
3783  *      A table driven interrupt handler that applies a set of masks to an
3784  *      interrupt status word and performs the corresponding actions if the
3785  *      interrupts described by the mask have occurred.  The actions include
3786  *      optionally emitting a warning or alert message.  The table is terminated
3787  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
3788  *      conditions.
3789  */
3790 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3791                                  const struct intr_info *acts)
3792 {
3793         int fatal = 0;
3794         unsigned int mask = 0;
3795         unsigned int status = t4_read_reg(adapter, reg);
3796
3797         for ( ; acts->mask; ++acts) {
3798                 if (!(status & acts->mask))
3799                         continue;
3800                 if (acts->fatal) {
3801                         fatal++;
3802                         CH_ALERT(adapter, "%s (0x%x)\n", acts->msg,
3803                                   status & acts->mask);
3804                 } else if (acts->msg)
3805                         CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg,
3806                                  status & acts->mask);
3807                 if (acts->int_handler)
3808                         acts->int_handler(adapter);
3809                 mask |= acts->mask;
3810         }
3811         status &= mask;
3812         if (status)     /* clear processed interrupts */
3813                 t4_write_reg(adapter, reg, status);
3814         return fatal;
3815 }
3816
3817 /*
3818  * Interrupt handler for the PCIE module.
3819  */
3820 static void pcie_intr_handler(struct adapter *adapter)
3821 {
3822         static const struct intr_info sysbus_intr_info[] = {
3823                 { F_RNPP, "RXNP array parity error", -1, 1 },
3824                 { F_RPCP, "RXPC array parity error", -1, 1 },
3825                 { F_RCIP, "RXCIF array parity error", -1, 1 },
3826                 { F_RCCP, "Rx completions control array parity error", -1, 1 },
3827                 { F_RFTP, "RXFT array parity error", -1, 1 },
3828                 { 0 }
3829         };
3830         static const struct intr_info pcie_port_intr_info[] = {
3831                 { F_TPCP, "TXPC array parity error", -1, 1 },
3832                 { F_TNPP, "TXNP array parity error", -1, 1 },
3833                 { F_TFTP, "TXFT array parity error", -1, 1 },
3834                 { F_TCAP, "TXCA array parity error", -1, 1 },
3835                 { F_TCIP, "TXCIF array parity error", -1, 1 },
3836                 { F_RCAP, "RXCA array parity error", -1, 1 },
3837                 { F_OTDD, "outbound request TLP discarded", -1, 1 },
3838                 { F_RDPE, "Rx data parity error", -1, 1 },
3839                 { F_TDUE, "Tx uncorrectable data error", -1, 1 },
3840                 { 0 }
3841         };
3842         static const struct intr_info pcie_intr_info[] = {
3843                 { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
3844                 { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
3845                 { F_MSIDATAPERR, "MSI data parity error", -1, 1 },
3846                 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3847                 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3848                 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3849                 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3850                 { F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
3851                 { F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
3852                 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3853                 { F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
3854                 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3855                 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3856                 { F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
3857                 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3858                 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3859                 { F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
3860                 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3861                 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3862                 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3863                 { F_FIDPERR, "PCI FID parity error", -1, 1 },
3864                 { F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
3865                 { F_MATAGPERR, "PCI MA tag parity error", -1, 1 },
3866                 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3867                 { F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
3868                 { F_RXWRPERR, "PCI Rx write parity error", -1, 1 },
3869                 { F_RPLPERR, "PCI replay buffer parity error", -1, 1 },
3870                 { F_PCIESINT, "PCI core secondary fault", -1, 1 },
3871                 { F_PCIEPINT, "PCI core primary fault", -1, 1 },
3872                 { F_UNXSPLCPLERR, "PCI unexpected split completion error", -1,
3873                   0 },
3874                 { 0 }
3875         };
3876
3877         static const struct intr_info t5_pcie_intr_info[] = {
3878                 { F_MSTGRPPERR, "Master Response Read Queue parity error",
3879                   -1, 1 },
3880                 { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
3881                 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
3882                 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3883                 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3884                 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3885                 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3886                 { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
3887                   -1, 1 },
3888                 { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
3889                   -1, 1 },
3890                 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3891                 { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
3892                 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3893                 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3894                 { F_DREQWRPERR, "PCI DMA channel write request parity error",
3895                   -1, 1 },
3896                 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3897                 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3898                 { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
3899                 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3900                 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3901                 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3902                 { F_FIDPERR, "PCI FID parity error", -1, 1 },
3903                 { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 },
3904                 { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
3905                 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3906                 { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
3907                   -1, 1 },
3908                 { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
3909                   -1, 1 },
3910                 { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
3911                 { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
3912                 { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3913                 { F_READRSPERR, "Outbound read error", -1,
3914                   0 },
3915                 { 0 }
3916         };
3917
3918         int fat;
3919
3920         if (is_t4(adapter))
3921                 fat = t4_handle_intr_status(adapter,
3922                                 A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
3923                                 sysbus_intr_info) +
3924                         t4_handle_intr_status(adapter,
3925                                         A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
3926                                         pcie_port_intr_info) +
3927                         t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3928                                               pcie_intr_info);
3929         else
3930                 fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3931                                             t5_pcie_intr_info);
3932         if (fat)
3933                 t4_fatal_err(adapter);
3934 }
3935
3936 /*
3937  * TP interrupt handler.
3938  */
3939 static void tp_intr_handler(struct adapter *adapter)
3940 {
3941         static const struct intr_info tp_intr_info[] = {
3942                 { 0x3fffffff, "TP parity error", -1, 1 },
3943                 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
3944                 { 0 }
3945         };
3946
3947         if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info))
3948                 t4_fatal_err(adapter);
3949 }
3950
3951 /*
3952  * SGE interrupt handler.
3953  */
3954 static void sge_intr_handler(struct adapter *adapter)
3955 {
3956         u64 v;
3957         u32 err;
3958
3959         static const struct intr_info sge_intr_info[] = {
3960                 { F_ERR_CPL_EXCEED_IQE_SIZE,
3961                   "SGE received CPL exceeding IQE size", -1, 1 },
3962                 { F_ERR_INVALID_CIDX_INC,
3963                   "SGE GTS CIDX increment too large", -1, 0 },
3964                 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
3965                 { F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
3966                 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
3967                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
3968                 { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
3969                   0 },
3970                 { F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
3971                   0 },
3972                 { F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
3973                   0 },
3974                 { F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
3975                   0 },
3976                 { F_ERR_ING_CTXT_PRIO,
3977                   "SGE too many priority ingress contexts", -1, 0 },
3978                 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
3979                 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
3980                 { 0 }
3981         };
3982
3983         static const struct intr_info t4t5_sge_intr_info[] = {
3984                 { F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
3985                 { F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
3986                 { F_ERR_EGR_CTXT_PRIO,
3987                   "SGE too many priority egress contexts", -1, 0 },
3988                 { 0 }
3989         };
3990
3991         /*
3992         * For now, treat below interrupts as fatal so that we disable SGE and
3993         * get better debug */
3994         static const struct intr_info t6_sge_intr_info[] = {
3995                 { F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1,
3996                   "SGE PCIe error for a DBP thread", -1, 1 },
3997                 { F_FATAL_WRE_LEN,
3998                   "SGE Actual WRE packet is less than advertized length",
3999                   -1, 1 },
4000                 { 0 }
4001         };
4002
4003         v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) |
4004                 ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32);
4005         if (v) {
4006                 CH_ALERT(adapter, "SGE parity error (%#llx)\n",
4007                                 (unsigned long long)v);
4008                 t4_write_reg(adapter, A_SGE_INT_CAUSE1, v);
4009                 t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32);
4010         }
4011
4012         v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info);
4013         if (chip_id(adapter) <= CHELSIO_T5)
4014                 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
4015                                            t4t5_sge_intr_info);
4016         else
4017                 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
4018                                            t6_sge_intr_info);
4019
4020         err = t4_read_reg(adapter, A_SGE_ERROR_STATS);
4021         if (err & F_ERROR_QID_VALID) {
4022                 CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err));
4023                 if (err & F_UNCAPTURED_ERROR)
4024                         CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n");
4025                 t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID |
4026                              F_UNCAPTURED_ERROR);
4027         }
4028
4029         if (v != 0)
4030                 t4_fatal_err(adapter);
4031 }
4032
4033 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\
4034                       F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR)
4035 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\
4036                       F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR)
4037
4038 /*
4039  * CIM interrupt handler.
4040  */
4041 static void cim_intr_handler(struct adapter *adapter)
4042 {
4043         static const struct intr_info cim_intr_info[] = {
4044                 { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
4045                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4046                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4047                 { F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
4048                 { F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
4049                 { F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
4050                 { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
4051                 { 0 }
4052         };
4053         static const struct intr_info cim_upintr_info[] = {
4054                 { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 },
4055                 { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 },
4056                 { F_ILLWRINT, "CIM illegal write", -1, 1 },
4057                 { F_ILLRDINT, "CIM illegal read", -1, 1 },
4058                 { F_ILLRDBEINT, "CIM illegal read BE", -1, 1 },
4059                 { F_ILLWRBEINT, "CIM illegal write BE", -1, 1 },
4060                 { F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
4061                 { F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
4062                 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
4063                 { F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
4064                 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
4065                 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
4066                 { F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
4067                 { F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
4068                 { F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
4069                 { F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
4070                 { F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
4071                 { F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
4072                 { F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
4073                 { F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
4074                 { F_SGLRDPLINT , "CIM single read from PL space", -1, 1 },
4075                 { F_SGLWRPLINT , "CIM single write to PL space", -1, 1 },
4076                 { F_BLKRDPLINT , "CIM block read from PL space", -1, 1 },
4077                 { F_BLKWRPLINT , "CIM block write to PL space", -1, 1 },
4078                 { F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
4079                 { F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
4080                 { F_TIMEOUTINT , "CIM PIF timeout", -1, 1 },
4081                 { F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
4082                 { 0 }
4083         };
4084         int fat;
4085
4086         if (t4_read_reg(adapter, A_PCIE_FW) & F_PCIE_FW_ERR)
4087                 t4_report_fw_error(adapter);
4088
4089         fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE,
4090                                     cim_intr_info) +
4091               t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE,
4092                                     cim_upintr_info);
4093         if (fat)
4094                 t4_fatal_err(adapter);
4095 }
4096
4097 /*
4098  * ULP RX interrupt handler.
4099  */
4100 static void ulprx_intr_handler(struct adapter *adapter)
4101 {
4102         static const struct intr_info ulprx_intr_info[] = {
4103                 { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 },
4104                 { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 },
4105                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4106                 { 0 }
4107         };
4108
4109         if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info))
4110                 t4_fatal_err(adapter);
4111 }
4112
4113 /*
4114  * ULP TX interrupt handler.
4115  */
4116 static void ulptx_intr_handler(struct adapter *adapter)
4117 {
4118         static const struct intr_info ulptx_intr_info[] = {
4119                 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
4120                   0 },
4121                 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
4122                   0 },
4123                 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
4124                   0 },
4125                 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
4126                   0 },
4127                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4128                 { 0 }
4129         };
4130
4131         if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info))
4132                 t4_fatal_err(adapter);
4133 }
4134
4135 /*
4136  * PM TX interrupt handler.
4137  */
4138 static void pmtx_intr_handler(struct adapter *adapter)
4139 {
4140         static const struct intr_info pmtx_intr_info[] = {
4141                 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
4142                 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
4143                 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
4144                 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
4145                 { 0xffffff0, "PMTX framing error", -1, 1 },
4146                 { F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
4147                 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1,
4148                   1 },
4149                 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
4150                 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
4151                 { 0 }
4152         };
4153
4154         if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info))
4155                 t4_fatal_err(adapter);
4156 }
4157
4158 /*
4159  * PM RX interrupt handler.
4160  */
4161 static void pmrx_intr_handler(struct adapter *adapter)
4162 {
4163         static const struct intr_info pmrx_intr_info[] = {
4164                 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
4165                 { 0x3ffff0, "PMRX framing error", -1, 1 },
4166                 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
4167                 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1,
4168                   1 },
4169                 { F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
4170                 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
4171                 { 0 }
4172         };
4173
4174         if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info))
4175                 t4_fatal_err(adapter);
4176 }
4177
4178 /*
4179  * CPL switch interrupt handler.
4180  */
4181 static void cplsw_intr_handler(struct adapter *adapter)
4182 {
4183         static const struct intr_info cplsw_intr_info[] = {
4184                 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
4185                 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
4186                 { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
4187                 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
4188                 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
4189                 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
4190                 { 0 }
4191         };
4192
4193         if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info))
4194                 t4_fatal_err(adapter);
4195 }
4196
4197 /*
4198  * LE interrupt handler.
4199  */
4200 static void le_intr_handler(struct adapter *adap)
4201 {
4202         unsigned int chip_ver = chip_id(adap);
4203         static const struct intr_info le_intr_info[] = {
4204                 { F_LIPMISS, "LE LIP miss", -1, 0 },
4205                 { F_LIP0, "LE 0 LIP error", -1, 0 },
4206                 { F_PARITYERR, "LE parity error", -1, 1 },
4207                 { F_UNKNOWNCMD, "LE unknown command", -1, 1 },
4208                 { F_REQQPARERR, "LE request queue parity error", -1, 1 },
4209                 { 0 }
4210         };
4211
4212         static const struct intr_info t6_le_intr_info[] = {
4213                 { F_T6_LIPMISS, "LE LIP miss", -1, 0 },
4214                 { F_T6_LIP0, "LE 0 LIP error", -1, 0 },
4215                 { F_TCAMINTPERR, "LE parity error", -1, 1 },
4216                 { F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 },
4217                 { F_SSRAMINTPERR, "LE request queue parity error", -1, 1 },
4218                 { 0 }
4219         };
4220
4221         if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE,
4222                                   (chip_ver <= CHELSIO_T5) ?
4223                                   le_intr_info : t6_le_intr_info))
4224                 t4_fatal_err(adap);
4225 }
4226
4227 /*
4228  * MPS interrupt handler.
4229  */
4230 static void mps_intr_handler(struct adapter *adapter)
4231 {
4232         static const struct intr_info mps_rx_intr_info[] = {
4233                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4234                 { 0 }
4235         };
4236         static const struct intr_info mps_tx_intr_info[] = {
4237                 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 },
4238                 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4239                 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error",
4240                   -1, 1 },
4241                 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error",
4242                   -1, 1 },
4243                 { F_BUBBLE, "MPS Tx underflow", -1, 1 },
4244                 { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
4245                 { F_FRMERR, "MPS Tx framing error", -1, 1 },
4246                 { 0 }
4247         };
4248         static const struct intr_info mps_trc_intr_info[] = {
4249                 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 },
4250                 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1,
4251                   1 },
4252                 { F_MISCPERR, "MPS TRC misc parity error", -1, 1 },
4253                 { 0 }
4254         };
4255         static const struct intr_info mps_stat_sram_intr_info[] = {
4256                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4257                 { 0 }
4258         };
4259         static const struct intr_info mps_stat_tx_intr_info[] = {
4260                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4261                 { 0 }
4262         };
4263         static const struct intr_info mps_stat_rx_intr_info[] = {
4264                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4265                 { 0 }
4266         };
4267         static const struct intr_info mps_cls_intr_info[] = {
4268                 { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
4269                 { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
4270                 { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
4271                 { 0 }
4272         };
4273
4274         int fat;
4275
4276         fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE,
4277                                     mps_rx_intr_info) +
4278               t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE,
4279                                     mps_tx_intr_info) +
4280               t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE,
4281                                     mps_trc_intr_info) +
4282               t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4283                                     mps_stat_sram_intr_info) +
4284               t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4285                                     mps_stat_tx_intr_info) +
4286               t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4287                                     mps_stat_rx_intr_info) +
4288               t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE,
4289                                     mps_cls_intr_info);
4290
4291         t4_write_reg(adapter, A_MPS_INT_CAUSE, 0);
4292         t4_read_reg(adapter, A_MPS_INT_CAUSE);  /* flush */
4293         if (fat)
4294                 t4_fatal_err(adapter);
4295 }
4296
4297 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \
4298                       F_ECC_UE_INT_CAUSE)
4299
4300 /*
4301  * EDC/MC interrupt handler.
4302  */
4303 static void mem_intr_handler(struct adapter *adapter, int idx)
4304 {
4305         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4306
4307         unsigned int addr, cnt_addr, v;
4308
4309         if (idx <= MEM_EDC1) {
4310                 addr = EDC_REG(A_EDC_INT_CAUSE, idx);
4311                 cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx);
4312         } else if (idx == MEM_MC) {
4313                 if (is_t4(adapter)) {
4314                         addr = A_MC_INT_CAUSE;
4315                         cnt_addr = A_MC_ECC_STATUS;
4316                 } else {
4317                         addr = A_MC_P_INT_CAUSE;
4318                         cnt_addr = A_MC_P_ECC_STATUS;
4319                 }
4320         } else {
4321                 addr = MC_REG(A_MC_P_INT_CAUSE, 1);
4322                 cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1);
4323         }
4324
4325         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4326         if (v & F_PERR_INT_CAUSE)
4327                 CH_ALERT(adapter, "%s FIFO parity error\n",
4328                           name[idx]);
4329         if (v & F_ECC_CE_INT_CAUSE) {
4330                 u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr));
4331
4332                 t4_edc_err_read(adapter, idx);
4333
4334                 t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT));
4335                 CH_WARN_RATELIMIT(adapter,
4336                                   "%u %s correctable ECC data error%s\n",
4337                                   cnt, name[idx], cnt > 1 ? "s" : "");
4338         }
4339         if (v & F_ECC_UE_INT_CAUSE)
4340                 CH_ALERT(adapter,
4341                          "%s uncorrectable ECC data error\n", name[idx]);
4342
4343         t4_write_reg(adapter, addr, v);
4344         if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE))
4345                 t4_fatal_err(adapter);
4346 }
4347
4348 /*
4349  * MA interrupt handler.
4350  */
4351 static void ma_intr_handler(struct adapter *adapter)
4352 {
4353         u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE);
4354
4355         if (status & F_MEM_PERR_INT_CAUSE) {
4356                 CH_ALERT(adapter,
4357                           "MA parity error, parity status %#x\n",
4358                           t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1));
4359                 if (is_t5(adapter))
4360                         CH_ALERT(adapter,
4361                                   "MA parity error, parity status %#x\n",
4362                                   t4_read_reg(adapter,
4363                                               A_MA_PARITY_ERROR_STATUS2));
4364         }
4365         if (status & F_MEM_WRAP_INT_CAUSE) {
4366                 v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS);
4367                 CH_ALERT(adapter, "MA address wrap-around error by "
4368                           "client %u to address %#x\n",
4369                           G_MEM_WRAP_CLIENT_NUM(v),
4370                           G_MEM_WRAP_ADDRESS(v) << 4);
4371         }
4372         t4_write_reg(adapter, A_MA_INT_CAUSE, status);
4373         t4_fatal_err(adapter);
4374 }
4375
4376 /*
4377  * SMB interrupt handler.
4378  */
4379 static void smb_intr_handler(struct adapter *adap)
4380 {
4381         static const struct intr_info smb_intr_info[] = {
4382                 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
4383                 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
4384                 { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
4385                 { 0 }
4386         };
4387
4388         if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info))
4389                 t4_fatal_err(adap);
4390 }
4391
4392 /*
4393  * NC-SI interrupt handler.
4394  */
4395 static void ncsi_intr_handler(struct adapter *adap)
4396 {
4397         static const struct intr_info ncsi_intr_info[] = {
4398                 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
4399                 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
4400                 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
4401                 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
4402                 { 0 }
4403         };
4404
4405         if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info))
4406                 t4_fatal_err(adap);
4407 }
4408
4409 /*
4410  * XGMAC interrupt handler.
4411  */
4412 static void xgmac_intr_handler(struct adapter *adap, int port)
4413 {
4414         u32 v, int_cause_reg;
4415
4416         if (is_t4(adap))
4417                 int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
4418         else
4419                 int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
4420
4421         v = t4_read_reg(adap, int_cause_reg);
4422
4423         v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR);
4424         if (!v)
4425                 return;
4426
4427         if (v & F_TXFIFO_PRTY_ERR)
4428                 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n",
4429                           port);
4430         if (v & F_RXFIFO_PRTY_ERR)
4431                 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n",
4432                           port);
4433         t4_write_reg(adap, int_cause_reg, v);
4434         t4_fatal_err(adap);
4435 }
4436
4437 /*
4438  * PL interrupt handler.
4439  */
4440 static void pl_intr_handler(struct adapter *adap)
4441 {
4442         static const struct intr_info pl_intr_info[] = {
4443                 { F_FATALPERR, "Fatal parity error", -1, 1 },
4444                 { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 },
4445                 { 0 }
4446         };
4447
4448         static const struct intr_info t5_pl_intr_info[] = {
4449                 { F_FATALPERR, "Fatal parity error", -1, 1 },
4450                 { 0 }
4451         };
4452
4453         if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE,
4454                                   is_t4(adap) ?
4455                                   pl_intr_info : t5_pl_intr_info))
4456                 t4_fatal_err(adap);
4457 }
4458
4459 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
4460
4461 /**
4462  *      t4_slow_intr_handler - control path interrupt handler
4463  *      @adapter: the adapter
4464  *
4465  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4466  *      The designation 'slow' is because it involves register reads, while
4467  *      data interrupts typically don't involve any MMIOs.
4468  */
4469 int t4_slow_intr_handler(struct adapter *adapter)
4470 {
4471         u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
4472
4473         if (!(cause & GLBL_INTR_MASK))
4474                 return 0;
4475         if (cause & F_CIM)
4476                 cim_intr_handler(adapter);
4477         if (cause & F_MPS)
4478                 mps_intr_handler(adapter);
4479         if (cause & F_NCSI)
4480                 ncsi_intr_handler(adapter);
4481         if (cause & F_PL)
4482                 pl_intr_handler(adapter);
4483         if (cause & F_SMB)
4484                 smb_intr_handler(adapter);
4485         if (cause & F_MAC0)
4486                 xgmac_intr_handler(adapter, 0);
4487         if (cause & F_MAC1)
4488                 xgmac_intr_handler(adapter, 1);
4489         if (cause & F_MAC2)
4490                 xgmac_intr_handler(adapter, 2);
4491         if (cause & F_MAC3)
4492                 xgmac_intr_handler(adapter, 3);
4493         if (cause & F_PCIE)
4494                 pcie_intr_handler(adapter);
4495         if (cause & F_MC0)
4496                 mem_intr_handler(adapter, MEM_MC);
4497         if (is_t5(adapter) && (cause & F_MC1))
4498                 mem_intr_handler(adapter, MEM_MC1);
4499         if (cause & F_EDC0)
4500                 mem_intr_handler(adapter, MEM_EDC0);
4501         if (cause & F_EDC1)
4502                 mem_intr_handler(adapter, MEM_EDC1);
4503         if (cause & F_LE)
4504                 le_intr_handler(adapter);
4505         if (cause & F_TP)
4506                 tp_intr_handler(adapter);
4507         if (cause & F_MA)
4508                 ma_intr_handler(adapter);
4509         if (cause & F_PM_TX)
4510                 pmtx_intr_handler(adapter);
4511         if (cause & F_PM_RX)
4512                 pmrx_intr_handler(adapter);
4513         if (cause & F_ULP_RX)
4514                 ulprx_intr_handler(adapter);
4515         if (cause & F_CPL_SWITCH)
4516                 cplsw_intr_handler(adapter);
4517         if (cause & F_SGE)
4518                 sge_intr_handler(adapter);
4519         if (cause & F_ULP_TX)
4520                 ulptx_intr_handler(adapter);
4521
4522         /* Clear the interrupts just processed for which we are the master. */
4523         t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK);
4524         (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */
4525         return 1;
4526 }
4527
4528 /**
4529  *      t4_intr_enable - enable interrupts
4530  *      @adapter: the adapter whose interrupts should be enabled
4531  *
4532  *      Enable PF-specific interrupts for the calling function and the top-level
4533  *      interrupt concentrator for global interrupts.  Interrupts are already
4534  *      enabled at each module, here we just enable the roots of the interrupt
4535  *      hierarchies.
4536  *
4537  *      Note: this function should be called only when the driver manages
4538  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4539  *      function at a time should be doing this.
4540  */
4541 void t4_intr_enable(struct adapter *adapter)
4542 {
4543         u32 val = 0;
4544         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4545         u32 pf = (chip_id(adapter) <= CHELSIO_T5
4546                   ? G_SOURCEPF(whoami)
4547                   : G_T6_SOURCEPF(whoami));
4548
4549         if (chip_id(adapter) <= CHELSIO_T5)
4550                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
4551         else
4552                 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
4553         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
4554                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
4555                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
4556                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
4557                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4558                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
4559                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
4560         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
4561         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
4562 }
4563
4564 /**
4565  *      t4_intr_disable - disable interrupts
4566  *      @adapter: the adapter whose interrupts should be disabled
4567  *
4568  *      Disable interrupts.  We only disable the top-level interrupt
4569  *      concentrators.  The caller must be a PCI function managing global
4570  *      interrupts.
4571  */
4572 void t4_intr_disable(struct adapter *adapter)
4573 {
4574         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4575         u32 pf = (chip_id(adapter) <= CHELSIO_T5
4576                   ? G_SOURCEPF(whoami)
4577                   : G_T6_SOURCEPF(whoami));
4578
4579         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
4580         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
4581 }
4582
4583 /**
4584  *      t4_intr_clear - clear all interrupts
4585  *      @adapter: the adapter whose interrupts should be cleared
4586  *
4587  *      Clears all interrupts.  The caller must be a PCI function managing
4588  *      global interrupts.
4589  */
4590 void t4_intr_clear(struct adapter *adapter)
4591 {
4592         static const unsigned int cause_reg[] = {
4593                 A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3,
4594                 A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE,
4595                 A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE,
4596                 A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1),
4597                 A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE,
4598                 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4599                 A_TP_INT_CAUSE,
4600                 A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE,
4601                 A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE,
4602                 A_MPS_RX_PERR_INT_CAUSE,
4603                 A_CPL_INTR_CAUSE,
4604                 MYPF_REG(A_PL_PF_INT_CAUSE),
4605                 A_PL_PL_INT_CAUSE,
4606                 A_LE_DB_INT_CAUSE,
4607         };
4608
4609         unsigned int i;
4610
4611         for (i = 0; i < ARRAY_SIZE(cause_reg); ++i)
4612                 t4_write_reg(adapter, cause_reg[i], 0xffffffff);
4613
4614         t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE :
4615                                 A_MC_P_INT_CAUSE, 0xffffffff);
4616
4617         if (is_t4(adapter)) {
4618                 t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4619                                 0xffffffff);
4620                 t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4621                                 0xffffffff);
4622         } else
4623                 t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
4624
4625         t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK);
4626         (void) t4_read_reg(adapter, A_PL_INT_CAUSE);          /* flush */
4627 }
4628
4629 /**
4630  *      hash_mac_addr - return the hash value of a MAC address
4631  *      @addr: the 48-bit Ethernet MAC address
4632  *
4633  *      Hashes a MAC address according to the hash function used by HW inexact
4634  *      (hash) address matching.
4635  */
4636 static int hash_mac_addr(const u8 *addr)
4637 {
4638         u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
4639         u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
4640         a ^= b;
4641         a ^= (a >> 12);
4642         a ^= (a >> 6);
4643         return a & 0x3f;
4644 }
4645
4646 /**
4647  *      t4_config_rss_range - configure a portion of the RSS mapping table
4648  *      @adapter: the adapter
4649  *      @mbox: mbox to use for the FW command
4650  *      @viid: virtual interface whose RSS subtable is to be written
4651  *      @start: start entry in the table to write
4652  *      @n: how many table entries to write
4653  *      @rspq: values for the "response queue" (Ingress Queue) lookup table
4654  *      @nrspq: number of values in @rspq
4655  *
4656  *      Programs the selected part of the VI's RSS mapping table with the
4657  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4658  *      until the full table range is populated.
4659  *
4660  *      The caller must ensure the values in @rspq are in the range allowed for
4661  *      @viid.
4662  */
4663 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4664                         int start, int n, const u16 *rspq, unsigned int nrspq)
4665 {
4666         int ret;
4667         const u16 *rsp = rspq;
4668         const u16 *rsp_end = rspq + nrspq;
4669         struct fw_rss_ind_tbl_cmd cmd;
4670
4671         memset(&cmd, 0, sizeof(cmd));
4672         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
4673                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4674                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
4675         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4676
4677         /*
4678          * Each firmware RSS command can accommodate up to 32 RSS Ingress
4679          * Queue Identifiers.  These Ingress Queue IDs are packed three to
4680          * a 32-bit word as 10-bit values with the upper remaining 2 bits
4681          * reserved.
4682          */
4683         while (n > 0) {
4684                 int nq = min(n, 32);
4685                 int nq_packed = 0;
4686                 __be32 *qp = &cmd.iq0_to_iq2;
4687
4688                 /*
4689                  * Set up the firmware RSS command header to send the next
4690                  * "nq" Ingress Queue IDs to the firmware.
4691                  */
4692                 cmd.niqid = cpu_to_be16(nq);
4693                 cmd.startidx = cpu_to_be16(start);
4694
4695                 /*
4696                  * "nq" more done for the start of the next loop.
4697                  */
4698                 start += nq;
4699                 n -= nq;
4700
4701                 /*
4702                  * While there are still Ingress Queue IDs to stuff into the
4703                  * current firmware RSS command, retrieve them from the
4704                  * Ingress Queue ID array and insert them into the command.
4705                  */
4706                 while (nq > 0) {
4707                         /*
4708                          * Grab up to the next 3 Ingress Queue IDs (wrapping
4709                          * around the Ingress Queue ID array if necessary) and
4710                          * insert them into the firmware RSS command at the
4711                          * current 3-tuple position within the commad.
4712                          */
4713                         u16 qbuf[3];
4714                         u16 *qbp = qbuf;
4715                         int nqbuf = min(3, nq);
4716
4717                         nq -= nqbuf;
4718                         qbuf[0] = qbuf[1] = qbuf[2] = 0;
4719                         while (nqbuf && nq_packed < 32) {
4720                                 nqbuf--;
4721                                 nq_packed++;
4722                                 *qbp++ = *rsp++;
4723                                 if (rsp >= rsp_end)
4724                                         rsp = rspq;
4725                         }
4726                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
4727                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
4728                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
4729                 }
4730
4731                 /*
4732                  * Send this portion of the RRS table update to the firmware;
4733                  * bail out on any errors.
4734                  */
4735                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4736                 if (ret)
4737                         return ret;
4738         }
4739         return 0;
4740 }
4741
4742 /**
4743  *      t4_config_glbl_rss - configure the global RSS mode
4744  *      @adapter: the adapter
4745  *      @mbox: mbox to use for the FW command
4746  *      @mode: global RSS mode
4747  *      @flags: mode-specific flags
4748  *
4749  *      Sets the global RSS mode.
4750  */
4751 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4752                        unsigned int flags)
4753 {
4754         struct fw_rss_glb_config_cmd c;
4755
4756         memset(&c, 0, sizeof(c));
4757         c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
4758                                     F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4759         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4760         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4761                 c.u.manual.mode_pkd =
4762                         cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4763         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4764                 c.u.basicvirtual.mode_keymode =
4765                         cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4766                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4767         } else
4768                 return -EINVAL;
4769         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4770 }
4771
4772 /**
4773  *      t4_config_vi_rss - configure per VI RSS settings
4774  *      @adapter: the adapter
4775  *      @mbox: mbox to use for the FW command
4776  *      @viid: the VI id
4777  *      @flags: RSS flags
4778  *      @defq: id of the default RSS queue for the VI.
4779  *      @skeyidx: RSS secret key table index for non-global mode
4780  *      @skey: RSS vf_scramble key for VI.
4781  *
4782  *      Configures VI-specific RSS properties.
4783  */
4784 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4785                      unsigned int flags, unsigned int defq, unsigned int skeyidx,
4786                      unsigned int skey)
4787 {
4788         struct fw_rss_vi_config_cmd c;
4789
4790         memset(&c, 0, sizeof(c));
4791         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4792                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4793                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
4794         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4795         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4796                                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
4797         c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
4798                                         V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
4799         c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
4800
4801         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4802 }
4803
4804 /* Read an RSS table row */
4805 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4806 {
4807         t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
4808         return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
4809                                    5, 0, val);
4810 }
4811
4812 /**
4813  *      t4_read_rss - read the contents of the RSS mapping table
4814  *      @adapter: the adapter
4815  *      @map: holds the contents of the RSS mapping table
4816  *
4817  *      Reads the contents of the RSS hash->queue mapping table.
4818  */
4819 int t4_read_rss(struct adapter *adapter, u16 *map)
4820 {
4821         u32 val;
4822         int i, ret;
4823
4824         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4825                 ret = rd_rss_row(adapter, i, &val);
4826                 if (ret)
4827                         return ret;
4828                 *map++ = G_LKPTBLQUEUE0(val);
4829                 *map++ = G_LKPTBLQUEUE1(val);
4830         }
4831         return 0;
4832 }
4833
4834 /**
4835  *      t4_fw_tp_pio_rw - Access TP PIO through LDST
4836  *      @adap: the adapter
4837  *      @vals: where the indirect register values are stored/written
4838  *      @nregs: how many indirect registers to read/write
4839  *      @start_idx: index of first indirect register to read/write
4840  *      @rw: Read (1) or Write (0)
4841  *
4842  *      Access TP PIO registers through LDST
4843  */
4844 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4845                      unsigned int start_index, unsigned int rw)
4846 {
4847         int ret, i;
4848         int cmd = FW_LDST_ADDRSPC_TP_PIO;
4849         struct fw_ldst_cmd c;
4850
4851         for (i = 0 ; i < nregs; i++) {
4852                 memset(&c, 0, sizeof(c));
4853                 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
4854                                                 F_FW_CMD_REQUEST |
4855                                                 (rw ? F_FW_CMD_READ :
4856                                                      F_FW_CMD_WRITE) |
4857                                                 V_FW_LDST_CMD_ADDRSPACE(cmd));
4858                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4859
4860                 c.u.addrval.addr = cpu_to_be32(start_index + i);
4861                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
4862                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4863                 if (ret == 0) {
4864                         if (rw)
4865                                 vals[i] = be32_to_cpu(c.u.addrval.val);
4866                 }
4867         }
4868 }
4869
4870 /**
4871  *      t4_read_rss_key - read the global RSS key
4872  *      @adap: the adapter
4873  *      @key: 10-entry array holding the 320-bit RSS key
4874  *
4875  *      Reads the global 320-bit RSS key.
4876  */
4877 void t4_read_rss_key(struct adapter *adap, u32 *key)
4878 {
4879         if (t4_use_ldst(adap))
4880                 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
4881         else
4882                 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
4883                                  A_TP_RSS_SECRET_KEY0);
4884 }
4885
4886 /**
4887  *      t4_write_rss_key - program one of the RSS keys
4888  *      @adap: the adapter
4889  *      @key: 10-entry array holding the 320-bit RSS key
4890  *      @idx: which RSS key to write
4891  *
4892  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
4893  *      0..15 the corresponding entry in the RSS key table is written,
4894  *      otherwise the global RSS key is written.
4895  */
4896 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
4897 {
4898         u8 rss_key_addr_cnt = 16;
4899         u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
4900
4901         /*
4902          * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4903          * allows access to key addresses 16-63 by using KeyWrAddrX
4904          * as index[5:4](upper 2) into key table
4905          */
4906         if ((chip_id(adap) > CHELSIO_T5) &&
4907             (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
4908                 rss_key_addr_cnt = 32;
4909
4910         if (t4_use_ldst(adap))
4911                 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
4912         else
4913                 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
4914                                   A_TP_RSS_SECRET_KEY0);
4915
4916         if (idx >= 0 && idx < rss_key_addr_cnt) {
4917                 if (rss_key_addr_cnt > 16)
4918                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
4919                                      vrt | V_KEYWRADDRX(idx >> 4) |
4920                                      V_T6_VFWRADDR(idx) | F_KEYWREN);
4921                 else
4922                         t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
4923                                      vrt| V_KEYWRADDR(idx) | F_KEYWREN);
4924         }
4925 }
4926
4927 /**
4928  *      t4_read_rss_pf_config - read PF RSS Configuration Table
4929  *      @adapter: the adapter
4930  *      @index: the entry in the PF RSS table to read
4931  *      @valp: where to store the returned value
4932  *
4933  *      Reads the PF RSS Configuration Table at the specified index and returns
4934  *      the value found there.
4935  */
4936 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4937                            u32 *valp)
4938 {
4939         if (t4_use_ldst(adapter))
4940                 t4_fw_tp_pio_rw(adapter, valp, 1,
4941                                 A_TP_RSS_PF0_CONFIG + index, 1);
4942         else
4943                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4944                                  valp, 1, A_TP_RSS_PF0_CONFIG + index);
4945 }
4946
4947 /**
4948  *      t4_write_rss_pf_config - write PF RSS Configuration Table
4949  *      @adapter: the adapter
4950  *      @index: the entry in the VF RSS table to read
4951  *      @val: the value to store
4952  *
4953  *      Writes the PF RSS Configuration Table at the specified index with the
4954  *      specified value.
4955  */
4956 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
4957                             u32 val)
4958 {
4959         if (t4_use_ldst(adapter))
4960                 t4_fw_tp_pio_rw(adapter, &val, 1,
4961                                 A_TP_RSS_PF0_CONFIG + index, 0);
4962         else
4963                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4964                                   &val, 1, A_TP_RSS_PF0_CONFIG + index);
4965 }
4966
4967 /**
4968  *      t4_read_rss_vf_config - read VF RSS Configuration Table
4969  *      @adapter: the adapter
4970  *      @index: the entry in the VF RSS table to read
4971  *      @vfl: where to store the returned VFL
4972  *      @vfh: where to store the returned VFH
4973  *
4974  *      Reads the VF RSS Configuration Table at the specified index and returns
4975  *      the (VFL, VFH) values found there.
4976  */
4977 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4978                            u32 *vfl, u32 *vfh)
4979 {
4980         u32 vrt, mask, data;
4981
4982         if (chip_id(adapter) <= CHELSIO_T5) {
4983                 mask = V_VFWRADDR(M_VFWRADDR);
4984                 data = V_VFWRADDR(index);
4985         } else {
4986                  mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
4987                  data = V_T6_VFWRADDR(index);
4988         }
4989         /*
4990          * Request that the index'th VF Table values be read into VFL/VFH.
4991          */
4992         vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
4993         vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
4994         vrt |= data | F_VFRDEN;
4995         t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
4996
4997         /*
4998          * Grab the VFL/VFH values ...
4999          */
5000         if (t4_use_ldst(adapter)) {
5001                 t4_fw_tp_pio_rw(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, 1);
5002                 t4_fw_tp_pio_rw(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, 1);
5003         } else {
5004                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5005                                  vfl, 1, A_TP_RSS_VFL_CONFIG);
5006                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5007                                  vfh, 1, A_TP_RSS_VFH_CONFIG);
5008         }
5009 }
5010
5011 /**
5012  *      t4_write_rss_vf_config - write VF RSS Configuration Table
5013  *
5014  *      @adapter: the adapter
5015  *      @index: the entry in the VF RSS table to write
5016  *      @vfl: the VFL to store
5017  *      @vfh: the VFH to store
5018  *
5019  *      Writes the VF RSS Configuration Table at the specified index with the
5020  *      specified (VFL, VFH) values.
5021  */
5022 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
5023                             u32 vfl, u32 vfh)
5024 {
5025         u32 vrt, mask, data;
5026
5027         if (chip_id(adapter) <= CHELSIO_T5) {
5028                 mask = V_VFWRADDR(M_VFWRADDR);
5029                 data = V_VFWRADDR(index);
5030         } else {
5031                 mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
5032                 data = V_T6_VFWRADDR(index);
5033         }
5034
5035         /*
5036          * Load up VFL/VFH with the values to be written ...
5037          */
5038         if (t4_use_ldst(adapter)) {
5039                 t4_fw_tp_pio_rw(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, 0);
5040                 t4_fw_tp_pio_rw(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, 0);
5041         } else {
5042                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5043                                   &vfl, 1, A_TP_RSS_VFL_CONFIG);
5044                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5045                                   &vfh, 1, A_TP_RSS_VFH_CONFIG);
5046         }
5047
5048         /*
5049          * Write the VFL/VFH into the VF Table at index'th location.
5050          */
5051         vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5052         vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5053         vrt |= data | F_VFRDEN;
5054         t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5055 }
5056
5057 /**
5058  *      t4_read_rss_pf_map - read PF RSS Map
5059  *      @adapter: the adapter
5060  *
5061  *      Reads the PF RSS Map register and returns its value.
5062  */
5063 u32 t4_read_rss_pf_map(struct adapter *adapter)
5064 {
5065         u32 pfmap;
5066
5067         if (t4_use_ldst(adapter))
5068                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 1);
5069         else
5070                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5071                                  &pfmap, 1, A_TP_RSS_PF_MAP);
5072         return pfmap;
5073 }
5074
5075 /**
5076  *      t4_write_rss_pf_map - write PF RSS Map
5077  *      @adapter: the adapter
5078  *      @pfmap: PF RSS Map value
5079  *
5080  *      Writes the specified value to the PF RSS Map register.
5081  */
5082 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap)
5083 {
5084         if (t4_use_ldst(adapter))
5085                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 0);
5086         else
5087                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5088                                   &pfmap, 1, A_TP_RSS_PF_MAP);
5089 }
5090
5091 /**
5092  *      t4_read_rss_pf_mask - read PF RSS Mask
5093  *      @adapter: the adapter
5094  *
5095  *      Reads the PF RSS Mask register and returns its value.
5096  */
5097 u32 t4_read_rss_pf_mask(struct adapter *adapter)
5098 {
5099         u32 pfmask;
5100
5101         if (t4_use_ldst(adapter))
5102                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 1);
5103         else
5104                 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5105                                  &pfmask, 1, A_TP_RSS_PF_MSK);
5106         return pfmask;
5107 }
5108
5109 /**
5110  *      t4_write_rss_pf_mask - write PF RSS Mask
5111  *      @adapter: the adapter
5112  *      @pfmask: PF RSS Mask value
5113  *
5114  *      Writes the specified value to the PF RSS Mask register.
5115  */
5116 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask)
5117 {
5118         if (t4_use_ldst(adapter))
5119                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 0);
5120         else
5121                 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5122                                   &pfmask, 1, A_TP_RSS_PF_MSK);
5123 }
5124
5125 /**
5126  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5127  *      @adap: the adapter
5128  *      @v4: holds the TCP/IP counter values
5129  *      @v6: holds the TCP/IPv6 counter values
5130  *
5131  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5132  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5133  */
5134 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5135                          struct tp_tcp_stats *v6)
5136 {
5137         u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
5138
5139 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
5140 #define STAT(x)     val[STAT_IDX(x)]
5141 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5142
5143         if (v4) {
5144                 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5145                                  ARRAY_SIZE(val), A_TP_MIB_TCP_OUT_RST);
5146                 v4->tcp_out_rsts = STAT(OUT_RST);
5147                 v4->tcp_in_segs  = STAT64(IN_SEG);
5148                 v4->tcp_out_segs = STAT64(OUT_SEG);
5149                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5150         }
5151         if (v6) {
5152                 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5153                                  ARRAY_SIZE(val), A_TP_MIB_TCP_V6OUT_RST);
5154                 v6->tcp_out_rsts = STAT(OUT_RST);
5155                 v6->tcp_in_segs  = STAT64(IN_SEG);
5156                 v6->tcp_out_segs = STAT64(OUT_SEG);
5157                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5158         }
5159 #undef STAT64
5160 #undef STAT
5161 #undef STAT_IDX
5162 }
5163
5164 /**
5165  *      t4_tp_get_err_stats - read TP's error MIB counters
5166  *      @adap: the adapter
5167  *      @st: holds the counter values
5168  *
5169  *      Returns the values of TP's error counters.
5170  */
5171 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
5172 {
5173         int nchan = adap->chip_params->nchan;
5174
5175         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5176                         st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0);
5177         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5178                         st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0);
5179         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5180                         st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0);
5181         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5182                         st->tnl_cong_drops, nchan, A_TP_MIB_TNL_CNG_DROP_0);
5183         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5184                         st->ofld_chan_drops, nchan, A_TP_MIB_OFD_CHN_DROP_0);
5185         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5186                         st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0);
5187         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5188                         st->ofld_vlan_drops, nchan, A_TP_MIB_OFD_VLN_DROP_0);
5189         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5190                         st->tcp6_in_errs, nchan, A_TP_MIB_TCP_V6IN_ERR_0);
5191
5192         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5193                          &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP);
5194 }
5195
5196 /**
5197  *      t4_tp_get_proxy_stats - read TP's proxy MIB counters
5198  *      @adap: the adapter
5199  *      @st: holds the counter values
5200  *
5201  *      Returns the values of TP's proxy counters.
5202  */
5203 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st)
5204 {
5205         int nchan = adap->chip_params->nchan;
5206
5207         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->proxy,
5208                          nchan, A_TP_MIB_TNL_LPBK_0);
5209 }
5210
5211 /**
5212  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5213  *      @adap: the adapter
5214  *      @st: holds the counter values
5215  *
5216  *      Returns the values of TP's CPL counters.
5217  */
5218 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
5219 {
5220         int nchan = adap->chip_params->nchan;
5221
5222         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req,
5223                          nchan, A_TP_MIB_CPL_IN_REQ_0);
5224         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->rsp,
5225                          nchan, A_TP_MIB_CPL_OUT_RSP_0);
5226 }
5227
5228 /**
5229  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5230  *      @adap: the adapter
5231  *      @st: holds the counter values
5232  *
5233  *      Returns the values of TP's RDMA counters.
5234  */
5235 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5236 {
5237         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->rqe_dfr_pkt,
5238                          2, A_TP_MIB_RQE_DFR_PKT);
5239 }
5240
5241 /**
5242  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5243  *      @adap: the adapter
5244  *      @idx: the port index
5245  *      @st: holds the counter values
5246  *
5247  *      Returns the values of TP's FCoE counters for the selected port.
5248  */
5249 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5250                        struct tp_fcoe_stats *st)
5251 {
5252         u32 val[2];
5253
5254         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_ddp,
5255                          1, A_TP_MIB_FCOE_DDP_0 + idx);
5256         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_drop,
5257                          1, A_TP_MIB_FCOE_DROP_0 + idx);
5258         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5259                          2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx);
5260         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5261 }
5262
5263 /**
5264  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5265  *      @adap: the adapter
5266  *      @st: holds the counter values
5267  *
5268  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5269  */
5270 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5271 {
5272         u32 val[4];
5273
5274         t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 4,
5275                          A_TP_MIB_USM_PKTS);
5276         st->frames = val[0];
5277         st->drops = val[1];
5278         st->octets = ((u64)val[2] << 32) | val[3];
5279 }
5280
5281 /**
5282  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5283  *      @adap: the adapter
5284  *      @mtus: where to store the MTU values
5285  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5286  *
5287  *      Reads the HW path MTU table.
5288  */
5289 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5290 {
5291         u32 v;
5292         int i;
5293
5294         for (i = 0; i < NMTUS; ++i) {
5295                 t4_write_reg(adap, A_TP_MTU_TABLE,
5296                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
5297                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
5298                 mtus[i] = G_MTUVALUE(v);
5299                 if (mtu_log)
5300                         mtu_log[i] = G_MTUWIDTH(v);
5301         }
5302 }
5303
5304 /**
5305  *      t4_read_cong_tbl - reads the congestion control table
5306  *      @adap: the adapter
5307  *      @incr: where to store the alpha values
5308  *
5309  *      Reads the additive increments programmed into the HW congestion
5310  *      control table.
5311  */
5312 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5313 {
5314         unsigned int mtu, w;
5315
5316         for (mtu = 0; mtu < NMTUS; ++mtu)
5317                 for (w = 0; w < NCCTRL_WIN; ++w) {
5318                         t4_write_reg(adap, A_TP_CCTRL_TABLE,
5319                                      V_ROWINDEX(0xffff) | (mtu << 5) | w);
5320                         incr[mtu][w] = (u16)t4_read_reg(adap,
5321                                                 A_TP_CCTRL_TABLE) & 0x1fff;
5322                 }
5323 }
5324
5325 /**
5326  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5327  *      @adap: the adapter
5328  *      @addr: the indirect TP register address
5329  *      @mask: specifies the field within the register to modify
5330  *      @val: new value for the field
5331  *
5332  *      Sets a field of an indirect TP register to the given value.
5333  */
5334 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5335                             unsigned int mask, unsigned int val)
5336 {
5337         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
5338         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
5339         t4_write_reg(adap, A_TP_PIO_DATA, val);
5340 }
5341
5342 /**
5343  *      init_cong_ctrl - initialize congestion control parameters
5344  *      @a: the alpha values for congestion control
5345  *      @b: the beta values for congestion control
5346  *
5347  *      Initialize the congestion control parameters.
5348  */
5349 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5350 {
5351         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5352         a[9] = 2;
5353         a[10] = 3;
5354         a[11] = 4;
5355         a[12] = 5;
5356         a[13] = 6;
5357         a[14] = 7;
5358         a[15] = 8;
5359         a[16] = 9;
5360         a[17] = 10;
5361         a[18] = 14;
5362         a[19] = 17;
5363         a[20] = 21;
5364         a[21] = 25;
5365         a[22] = 30;
5366         a[23] = 35;
5367         a[24] = 45;
5368         a[25] = 60;
5369         a[26] = 80;
5370         a[27] = 100;
5371         a[28] = 200;
5372         a[29] = 300;
5373         a[30] = 400;
5374         a[31] = 500;
5375
5376         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5377         b[9] = b[10] = 1;
5378         b[11] = b[12] = 2;
5379         b[13] = b[14] = b[15] = b[16] = 3;
5380         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5381         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5382         b[28] = b[29] = 6;
5383         b[30] = b[31] = 7;
5384 }
5385
5386 /* The minimum additive increment value for the congestion control table */
5387 #define CC_MIN_INCR 2U
5388
5389 /**
5390  *      t4_load_mtus - write the MTU and congestion control HW tables
5391  *      @adap: the adapter
5392  *      @mtus: the values for the MTU table
5393  *      @alpha: the values for the congestion control alpha parameter
5394  *      @beta: the values for the congestion control beta parameter
5395  *
5396  *      Write the HW MTU table with the supplied MTUs and the high-speed
5397  *      congestion control table with the supplied alpha, beta, and MTUs.
5398  *      We write the two tables together because the additive increments
5399  *      depend on the MTUs.
5400  */
5401 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5402                   const unsigned short *alpha, const unsigned short *beta)
5403 {
5404         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5405                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5406                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5407                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5408         };
5409
5410         unsigned int i, w;
5411
5412         for (i = 0; i < NMTUS; ++i) {
5413                 unsigned int mtu = mtus[i];
5414                 unsigned int log2 = fls(mtu);
5415
5416                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5417                         log2--;
5418                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
5419                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
5420
5421                 for (w = 0; w < NCCTRL_WIN; ++w) {
5422                         unsigned int inc;
5423
5424                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5425                                   CC_MIN_INCR);
5426
5427                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
5428                                      (w << 16) | (beta[w] << 13) | inc);
5429                 }
5430         }
5431 }
5432
5433 /**
5434  *      t4_set_pace_tbl - set the pace table
5435  *      @adap: the adapter
5436  *      @pace_vals: the pace values in microseconds
5437  *      @start: index of the first entry in the HW pace table to set
5438  *      @n: how many entries to set
5439  *
5440  *      Sets (a subset of the) HW pace table.
5441  */
5442 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
5443                      unsigned int start, unsigned int n)
5444 {
5445         unsigned int vals[NTX_SCHED], i;
5446         unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
5447
5448         if (n > NTX_SCHED)
5449             return -ERANGE;
5450
5451         /* convert values from us to dack ticks, rounding to closest value */
5452         for (i = 0; i < n; i++, pace_vals++) {
5453                 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
5454                 if (vals[i] > 0x7ff)
5455                         return -ERANGE;
5456                 if (*pace_vals && vals[i] == 0)
5457                         return -ERANGE;
5458         }
5459         for (i = 0; i < n; i++, start++)
5460                 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
5461         return 0;
5462 }
5463
5464 /**
5465  *      t4_set_sched_bps - set the bit rate for a HW traffic scheduler
5466  *      @adap: the adapter
5467  *      @kbps: target rate in Kbps
5468  *      @sched: the scheduler index
5469  *
5470  *      Configure a Tx HW scheduler for the target rate.
5471  */
5472 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
5473 {
5474         unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
5475         unsigned int clk = adap->params.vpd.cclk * 1000;
5476         unsigned int selected_cpt = 0, selected_bpt = 0;
5477
5478         if (kbps > 0) {
5479                 kbps *= 125;     /* -> bytes */
5480                 for (cpt = 1; cpt <= 255; cpt++) {
5481                         tps = clk / cpt;
5482                         bpt = (kbps + tps / 2) / tps;
5483                         if (bpt > 0 && bpt <= 255) {
5484                                 v = bpt * tps;
5485                                 delta = v >= kbps ? v - kbps : kbps - v;
5486                                 if (delta < mindelta) {
5487                                         mindelta = delta;
5488                                         selected_cpt = cpt;
5489                                         selected_bpt = bpt;
5490                                 }
5491                         } else if (selected_cpt)
5492                                 break;
5493                 }
5494                 if (!selected_cpt)
5495                         return -EINVAL;
5496         }
5497         t4_write_reg(adap, A_TP_TM_PIO_ADDR,
5498                      A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
5499         v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5500         if (sched & 1)
5501                 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
5502         else
5503                 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
5504         t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5505         return 0;
5506 }
5507
5508 /**
5509  *      t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
5510  *      @adap: the adapter
5511  *      @sched: the scheduler index
5512  *      @ipg: the interpacket delay in tenths of nanoseconds
5513  *
5514  *      Set the interpacket delay for a HW packet rate scheduler.
5515  */
5516 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
5517 {
5518         unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
5519
5520         /* convert ipg to nearest number of core clocks */
5521         ipg *= core_ticks_per_usec(adap);
5522         ipg = (ipg + 5000) / 10000;
5523         if (ipg > M_TXTIMERSEPQ0)
5524                 return -EINVAL;
5525
5526         t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
5527         v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5528         if (sched & 1)
5529                 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
5530         else
5531                 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
5532         t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5533         t4_read_reg(adap, A_TP_TM_PIO_DATA);
5534         return 0;
5535 }
5536
5537 /*
5538  * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5539  * clocks.  The formula is
5540  *
5541  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5542  *
5543  * which is equivalent to
5544  *
5545  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5546  */
5547 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5548 {
5549         u64 v = bytes256 * adap->params.vpd.cclk;
5550
5551         return v * 62 + v / 2;
5552 }
5553
5554 /**
5555  *      t4_get_chan_txrate - get the current per channel Tx rates
5556  *      @adap: the adapter
5557  *      @nic_rate: rates for NIC traffic
5558  *      @ofld_rate: rates for offloaded traffic
5559  *
5560  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5561  *      for each channel.
5562  */
5563 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5564 {
5565         u32 v;
5566
5567         v = t4_read_reg(adap, A_TP_TX_TRATE);
5568         nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
5569         nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
5570         if (adap->chip_params->nchan > 2) {
5571                 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
5572                 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
5573         }
5574
5575         v = t4_read_reg(adap, A_TP_TX_ORATE);
5576         ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
5577         ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
5578         if (adap->chip_params->nchan > 2) {
5579                 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
5580                 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
5581         }
5582 }
5583
5584 /**
5585  *      t4_set_trace_filter - configure one of the tracing filters
5586  *      @adap: the adapter
5587  *      @tp: the desired trace filter parameters
5588  *      @idx: which filter to configure
5589  *      @enable: whether to enable or disable the filter
5590  *
5591  *      Configures one of the tracing filters available in HW.  If @tp is %NULL
5592  *      it indicates that the filter is already written in the register and it
5593  *      just needs to be enabled or disabled.
5594  */
5595 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5596     int idx, int enable)
5597 {
5598         int i, ofst = idx * 4;
5599         u32 data_reg, mask_reg, cfg;
5600         u32 multitrc = F_TRCMULTIFILTER;
5601         u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
5602
5603         if (idx < 0 || idx >= NTRACE)
5604                 return -EINVAL;
5605
5606         if (tp == NULL || !enable) {
5607                 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
5608                     enable ? en : 0);
5609                 return 0;
5610         }
5611
5612         /*
5613          * TODO - After T4 data book is updated, specify the exact
5614          * section below.
5615          *
5616          * See T4 data book - MPS section for a complete description
5617          * of the below if..else handling of A_MPS_TRC_CFG register
5618          * value.
5619          */
5620         cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
5621         if (cfg & F_TRCMULTIFILTER) {
5622                 /*
5623                  * If multiple tracers are enabled, then maximum
5624                  * capture size is 2.5KB (FIFO size of a single channel)
5625                  * minus 2 flits for CPL_TRACE_PKT header.
5626                  */
5627                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5628                         return -EINVAL;
5629         } else {
5630                 /*
5631                  * If multiple tracers are disabled, to avoid deadlocks
5632                  * maximum packet capture size of 9600 bytes is recommended.
5633                  * Also in this mode, only trace0 can be enabled and running.
5634                  */
5635                 multitrc = 0;
5636                 if (tp->snap_len > 9600 || idx)
5637                         return -EINVAL;
5638         }
5639
5640         if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
5641             tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
5642             tp->min_len > M_TFMINPKTSIZE)
5643                 return -EINVAL;
5644
5645         /* stop the tracer we'll be changing */
5646         t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
5647
5648         idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
5649         data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
5650         mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
5651
5652         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5653                 t4_write_reg(adap, data_reg, tp->data[i]);
5654                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5655         }
5656         t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
5657                      V_TFCAPTUREMAX(tp->snap_len) |
5658                      V_TFMINPKTSIZE(tp->min_len));
5659         t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
5660                      V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
5661                      (is_t4(adap) ?
5662                      V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
5663                      V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
5664
5665         return 0;
5666 }
5667
5668 /**
5669  *      t4_get_trace_filter - query one of the tracing filters
5670  *      @adap: the adapter
5671  *      @tp: the current trace filter parameters
5672  *      @idx: which trace filter to query
5673  *      @enabled: non-zero if the filter is enabled
5674  *
5675  *      Returns the current settings of one of the HW tracing filters.
5676  */
5677 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5678                          int *enabled)
5679 {
5680         u32 ctla, ctlb;
5681         int i, ofst = idx * 4;
5682         u32 data_reg, mask_reg;
5683
5684         ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
5685         ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
5686
5687         if (is_t4(adap)) {
5688                 *enabled = !!(ctla & F_TFEN);
5689                 tp->port =  G_TFPORT(ctla);
5690                 tp->invert = !!(ctla & F_TFINVERTMATCH);
5691         } else {
5692                 *enabled = !!(ctla & F_T5_TFEN);
5693                 tp->port = G_T5_TFPORT(ctla);
5694                 tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
5695         }
5696         tp->snap_len = G_TFCAPTUREMAX(ctlb);
5697         tp->min_len = G_TFMINPKTSIZE(ctlb);
5698         tp->skip_ofst = G_TFOFFSET(ctla);
5699         tp->skip_len = G_TFLENGTH(ctla);
5700
5701         ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
5702         data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
5703         mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
5704
5705         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5706                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5707                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5708         }
5709 }
5710
5711 /**
5712  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5713  *      @adap: the adapter
5714  *      @cnt: where to store the count statistics
5715  *      @cycles: where to store the cycle statistics
5716  *
5717  *      Returns performance statistics from PMTX.
5718  */
5719 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5720 {
5721         int i;
5722         u32 data[2];
5723
5724         for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5725                 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
5726                 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
5727                 if (is_t4(adap))
5728                         cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
5729                 else {
5730                         t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
5731                                          A_PM_TX_DBG_DATA, data, 2,
5732                                          A_PM_TX_DBG_STAT_MSB);
5733                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5734                 }
5735         }
5736 }
5737
5738 /**
5739  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5740  *      @adap: the adapter
5741  *      @cnt: where to store the count statistics
5742  *      @cycles: where to store the cycle statistics
5743  *
5744  *      Returns performance statistics from PMRX.
5745  */
5746 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5747 {
5748         int i;
5749         u32 data[2];
5750
5751         for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5752                 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
5753                 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
5754                 if (is_t4(adap)) {
5755                         cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
5756                 } else {
5757                         t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
5758                                          A_PM_RX_DBG_DATA, data, 2,
5759                                          A_PM_RX_DBG_STAT_MSB);
5760                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5761                 }
5762         }
5763 }
5764
5765 /**
5766  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5767  *      @adap: the adapter
5768  *      @idx: the port index
5769  *
5770  *      Returns a bitmap indicating which MPS buffer groups are associated
5771  *      with the given port.  Bit i is set if buffer group i is used by the
5772  *      port.
5773  */
5774 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5775 {
5776         u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
5777
5778         if (n == 0)
5779                 return idx == 0 ? 0xf : 0;
5780         if (n == 1 && chip_id(adap) <= CHELSIO_T5)
5781                 return idx < 2 ? (3 << (2 * idx)) : 0;
5782         return 1 << idx;
5783 }
5784
5785 /**
5786  *      t4_get_port_type_description - return Port Type string description
5787  *      @port_type: firmware Port Type enumeration
5788  */
5789 const char *t4_get_port_type_description(enum fw_port_type port_type)
5790 {
5791         static const char *const port_type_description[] = {
5792                 "Fiber_XFI",
5793                 "Fiber_XAUI",
5794                 "BT_SGMII",
5795                 "BT_XFI",
5796                 "BT_XAUI",
5797                 "KX4",
5798                 "CX4",
5799                 "KX",
5800                 "KR",
5801                 "SFP",
5802                 "BP_AP",
5803                 "BP4_AP",
5804                 "QSFP_10G",
5805                 "QSA",
5806                 "QSFP",
5807                 "BP40_BA",
5808                 "KR4_100G",
5809                 "CR4_QSFP",
5810                 "CR_QSFP",
5811                 "CR2_QSFP",
5812                 "SFP28",
5813                 "KR_SFP28",
5814         };
5815
5816         if (port_type < ARRAY_SIZE(port_type_description))
5817                 return port_type_description[port_type];
5818         return "UNKNOWN";
5819 }
5820
5821 /**
5822  *      t4_get_port_stats_offset - collect port stats relative to a previous
5823  *                                 snapshot
5824  *      @adap: The adapter
5825  *      @idx: The port
5826  *      @stats: Current stats to fill
5827  *      @offset: Previous stats snapshot
5828  */
5829 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5830                 struct port_stats *stats,
5831                 struct port_stats *offset)
5832 {
5833         u64 *s, *o;
5834         int i;
5835
5836         t4_get_port_stats(adap, idx, stats);
5837         for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
5838                         i < (sizeof(struct port_stats)/sizeof(u64)) ;
5839                         i++, s++, o++)
5840                 *s -= *o;
5841 }
5842
5843 /**
5844  *      t4_get_port_stats - collect port statistics
5845  *      @adap: the adapter
5846  *      @idx: the port index
5847  *      @p: the stats structure to fill
5848  *
5849  *      Collect statistics related to the given port from HW.
5850  */
5851 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5852 {
5853         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5854         u32 stat_ctl;
5855
5856 #define GET_STAT(name) \
5857         t4_read_reg64(adap, \
5858         (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
5859         T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
5860 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5861
5862         stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
5863
5864         p->tx_pause             = GET_STAT(TX_PORT_PAUSE);
5865         p->tx_octets            = GET_STAT(TX_PORT_BYTES);
5866         p->tx_frames            = GET_STAT(TX_PORT_FRAMES);
5867         p->tx_bcast_frames      = GET_STAT(TX_PORT_BCAST);
5868         p->tx_mcast_frames      = GET_STAT(TX_PORT_MCAST);
5869         p->tx_ucast_frames      = GET_STAT(TX_PORT_UCAST);
5870         p->tx_error_frames      = GET_STAT(TX_PORT_ERROR);
5871         p->tx_frames_64         = GET_STAT(TX_PORT_64B);
5872         p->tx_frames_65_127     = GET_STAT(TX_PORT_65B_127B);
5873         p->tx_frames_128_255    = GET_STAT(TX_PORT_128B_255B);
5874         p->tx_frames_256_511    = GET_STAT(TX_PORT_256B_511B);
5875         p->tx_frames_512_1023   = GET_STAT(TX_PORT_512B_1023B);
5876         p->tx_frames_1024_1518  = GET_STAT(TX_PORT_1024B_1518B);
5877         p->tx_frames_1519_max   = GET_STAT(TX_PORT_1519B_MAX);
5878         p->tx_drop              = GET_STAT(TX_PORT_DROP);
5879         p->tx_ppp0              = GET_STAT(TX_PORT_PPP0);
5880         p->tx_ppp1              = GET_STAT(TX_PORT_PPP1);
5881         p->tx_ppp2              = GET_STAT(TX_PORT_PPP2);
5882         p->tx_ppp3              = GET_STAT(TX_PORT_PPP3);
5883         p->tx_ppp4              = GET_STAT(TX_PORT_PPP4);
5884         p->tx_ppp5              = GET_STAT(TX_PORT_PPP5);
5885         p->tx_ppp6              = GET_STAT(TX_PORT_PPP6);
5886         p->tx_ppp7              = GET_STAT(TX_PORT_PPP7);
5887
5888         if (chip_id(adap) >= CHELSIO_T5) {
5889                 if (stat_ctl & F_COUNTPAUSESTATTX) {
5890                         p->tx_frames -= p->tx_pause;
5891                         p->tx_octets -= p->tx_pause * 64;
5892                 }
5893                 if (stat_ctl & F_COUNTPAUSEMCTX)
5894                         p->tx_mcast_frames -= p->tx_pause;
5895         }
5896
5897         p->rx_pause             = GET_STAT(RX_PORT_PAUSE);
5898         p->rx_octets            = GET_STAT(RX_PORT_BYTES);
5899         p->rx_frames            = GET_STAT(RX_PORT_FRAMES);
5900         p->rx_bcast_frames      = GET_STAT(RX_PORT_BCAST);
5901         p->rx_mcast_frames      = GET_STAT(RX_PORT_MCAST);
5902         p->rx_ucast_frames      = GET_STAT(RX_PORT_UCAST);
5903         p->rx_too_long          = GET_STAT(RX_PORT_MTU_ERROR);
5904         p->rx_jabber            = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5905         p->rx_fcs_err           = GET_STAT(RX_PORT_CRC_ERROR);
5906         p->rx_len_err           = GET_STAT(RX_PORT_LEN_ERROR);
5907         p->rx_symbol_err        = GET_STAT(RX_PORT_SYM_ERROR);
5908         p->rx_runt              = GET_STAT(RX_PORT_LESS_64B);
5909         p->rx_frames_64         = GET_STAT(RX_PORT_64B);
5910         p->rx_frames_65_127     = GET_STAT(RX_PORT_65B_127B);
5911         p->rx_frames_128_255    = GET_STAT(RX_PORT_128B_255B);
5912         p->rx_frames_256_511    = GET_STAT(RX_PORT_256B_511B);
5913         p->rx_frames_512_1023   = GET_STAT(RX_PORT_512B_1023B);
5914         p->rx_frames_1024_1518  = GET_STAT(RX_PORT_1024B_1518B);
5915         p->rx_frames_1519_max   = GET_STAT(RX_PORT_1519B_MAX);
5916         p->rx_ppp0              = GET_STAT(RX_PORT_PPP0);
5917         p->rx_ppp1              = GET_STAT(RX_PORT_PPP1);
5918         p->rx_ppp2              = GET_STAT(RX_PORT_PPP2);
5919         p->rx_ppp3              = GET_STAT(RX_PORT_PPP3);
5920         p->rx_ppp4              = GET_STAT(RX_PORT_PPP4);
5921         p->rx_ppp5              = GET_STAT(RX_PORT_PPP5);
5922         p->rx_ppp6              = GET_STAT(RX_PORT_PPP6);
5923         p->rx_ppp7              = GET_STAT(RX_PORT_PPP7);
5924
5925         if (chip_id(adap) >= CHELSIO_T5) {
5926                 if (stat_ctl & F_COUNTPAUSESTATRX) {
5927                         p->rx_frames -= p->rx_pause;
5928                         p->rx_octets -= p->rx_pause * 64;
5929                 }
5930                 if (stat_ctl & F_COUNTPAUSEMCRX)
5931                         p->rx_mcast_frames -= p->rx_pause;
5932         }
5933
5934         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5935         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5936         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5937         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5938         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5939         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5940         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5941         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5942
5943 #undef GET_STAT
5944 #undef GET_STAT_COM
5945 }
5946
5947 /**
5948  *      t4_get_lb_stats - collect loopback port statistics
5949  *      @adap: the adapter
5950  *      @idx: the loopback port index
5951  *      @p: the stats structure to fill
5952  *
5953  *      Return HW statistics for the given loopback port.
5954  */
5955 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5956 {
5957         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5958
5959 #define GET_STAT(name) \
5960         t4_read_reg64(adap, \
5961         (is_t4(adap) ? \
5962         PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
5963         T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
5964 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5965
5966         p->octets       = GET_STAT(BYTES);
5967         p->frames       = GET_STAT(FRAMES);
5968         p->bcast_frames = GET_STAT(BCAST);
5969         p->mcast_frames = GET_STAT(MCAST);
5970         p->ucast_frames = GET_STAT(UCAST);
5971         p->error_frames = GET_STAT(ERROR);
5972
5973         p->frames_64            = GET_STAT(64B);
5974         p->frames_65_127        = GET_STAT(65B_127B);
5975         p->frames_128_255       = GET_STAT(128B_255B);
5976         p->frames_256_511       = GET_STAT(256B_511B);
5977         p->frames_512_1023      = GET_STAT(512B_1023B);
5978         p->frames_1024_1518     = GET_STAT(1024B_1518B);
5979         p->frames_1519_max      = GET_STAT(1519B_MAX);
5980         p->drop                 = GET_STAT(DROP_FRAMES);
5981
5982         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5983         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5984         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5985         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5986         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5987         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5988         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5989         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5990
5991 #undef GET_STAT
5992 #undef GET_STAT_COM
5993 }
5994
5995 /**
5996  *      t4_wol_magic_enable - enable/disable magic packet WoL
5997  *      @adap: the adapter
5998  *      @port: the physical port index
5999  *      @addr: MAC address expected in magic packets, %NULL to disable
6000  *
6001  *      Enables/disables magic packet wake-on-LAN for the selected port.
6002  */
6003 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
6004                          const u8 *addr)
6005 {
6006         u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
6007
6008         if (is_t4(adap)) {
6009                 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
6010                 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
6011                 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
6012         } else {
6013                 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
6014                 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
6015                 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
6016         }
6017
6018         if (addr) {
6019                 t4_write_reg(adap, mag_id_reg_l,
6020                              (addr[2] << 24) | (addr[3] << 16) |
6021                              (addr[4] << 8) | addr[5]);
6022                 t4_write_reg(adap, mag_id_reg_h,
6023                              (addr[0] << 8) | addr[1]);
6024         }
6025         t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
6026                          V_MAGICEN(addr != NULL));
6027 }
6028
6029 /**
6030  *      t4_wol_pat_enable - enable/disable pattern-based WoL
6031  *      @adap: the adapter
6032  *      @port: the physical port index
6033  *      @map: bitmap of which HW pattern filters to set
6034  *      @mask0: byte mask for bytes 0-63 of a packet
6035  *      @mask1: byte mask for bytes 64-127 of a packet
6036  *      @crc: Ethernet CRC for selected bytes
6037  *      @enable: enable/disable switch
6038  *
6039  *      Sets the pattern filters indicated in @map to mask out the bytes
6040  *      specified in @mask0/@mask1 in received packets and compare the CRC of
6041  *      the resulting packet against @crc.  If @enable is %true pattern-based
6042  *      WoL is enabled, otherwise disabled.
6043  */
6044 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
6045                       u64 mask0, u64 mask1, unsigned int crc, bool enable)
6046 {
6047         int i;
6048         u32 port_cfg_reg;
6049
6050         if (is_t4(adap))
6051                 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
6052         else
6053                 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
6054
6055         if (!enable) {
6056                 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
6057                 return 0;
6058         }
6059         if (map > 0xff)
6060                 return -EINVAL;
6061
6062 #define EPIO_REG(name) \
6063         (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
6064         T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
6065
6066         t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
6067         t4_write_reg(adap, EPIO_REG(DATA2), mask1);
6068         t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
6069
6070         for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
6071                 if (!(map & 1))
6072                         continue;
6073
6074                 /* write byte masks */
6075                 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
6076                 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
6077                 t4_read_reg(adap, EPIO_REG(OP));                /* flush */
6078                 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
6079                         return -ETIMEDOUT;
6080
6081                 /* write CRC */
6082                 t4_write_reg(adap, EPIO_REG(DATA0), crc);
6083                 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
6084                 t4_read_reg(adap, EPIO_REG(OP));                /* flush */
6085                 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
6086                         return -ETIMEDOUT;
6087         }
6088 #undef EPIO_REG
6089
6090         t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
6091         return 0;
6092 }
6093
6094 /*     t4_mk_filtdelwr - create a delete filter WR
6095  *     @ftid: the filter ID
6096  *     @wr: the filter work request to populate
6097  *     @qid: ingress queue to receive the delete notification
6098  *
6099  *     Creates a filter work request to delete the supplied filter.  If @qid is
6100  *     negative the delete notification is suppressed.
6101  */
6102 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6103 {
6104         memset(wr, 0, sizeof(*wr));
6105         wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
6106         wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
6107         wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
6108                                     V_FW_FILTER_WR_NOREPLY(qid < 0));
6109         wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
6110         if (qid >= 0)
6111                 wr->rx_chan_rx_rpl_iq =
6112                                 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
6113 }
6114
6115 #define INIT_CMD(var, cmd, rd_wr) do { \
6116         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
6117                                         F_FW_CMD_REQUEST | \
6118                                         F_FW_CMD_##rd_wr); \
6119         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6120 } while (0)
6121
6122 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6123                           u32 addr, u32 val)
6124 {
6125         u32 ldst_addrspace;
6126         struct fw_ldst_cmd c;
6127
6128         memset(&c, 0, sizeof(c));
6129         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
6130         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6131                                         F_FW_CMD_REQUEST |
6132                                         F_FW_CMD_WRITE |
6133                                         ldst_addrspace);
6134         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6135         c.u.addrval.addr = cpu_to_be32(addr);
6136         c.u.addrval.val = cpu_to_be32(val);
6137
6138         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6139 }
6140
6141 /**
6142  *      t4_mdio_rd - read a PHY register through MDIO
6143  *      @adap: the adapter
6144  *      @mbox: mailbox to use for the FW command
6145  *      @phy_addr: the PHY address
6146  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6147  *      @reg: the register to read
6148  *      @valp: where to store the value
6149  *
6150  *      Issues a FW command through the given mailbox to read a PHY register.
6151  */
6152 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6153                unsigned int mmd, unsigned int reg, unsigned int *valp)
6154 {
6155         int ret;
6156         u32 ldst_addrspace;
6157         struct fw_ldst_cmd c;
6158
6159         memset(&c, 0, sizeof(c));
6160         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
6161         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6162                                         F_FW_CMD_REQUEST | F_FW_CMD_READ |
6163                                         ldst_addrspace);
6164         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6165         c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
6166                                          V_FW_LDST_CMD_MMD(mmd));
6167         c.u.mdio.raddr = cpu_to_be16(reg);
6168
6169         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6170         if (ret == 0)
6171                 *valp = be16_to_cpu(c.u.mdio.rval);
6172         return ret;
6173 }
6174
6175 /**
6176  *      t4_mdio_wr - write a PHY register through MDIO
6177  *      @adap: the adapter
6178  *      @mbox: mailbox to use for the FW command
6179  *      @phy_addr: the PHY address
6180  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6181  *      @reg: the register to write
6182  *      @valp: value to write
6183  *
6184  *      Issues a FW command through the given mailbox to write a PHY register.
6185  */
6186 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6187                unsigned int mmd, unsigned int reg, unsigned int val)
6188 {
6189         u32 ldst_addrspace;
6190         struct fw_ldst_cmd c;
6191
6192         memset(&c, 0, sizeof(c));
6193         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
6194         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6195                                         F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6196                                         ldst_addrspace);
6197         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6198         c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
6199                                          V_FW_LDST_CMD_MMD(mmd));
6200         c.u.mdio.raddr = cpu_to_be16(reg);
6201         c.u.mdio.rval = cpu_to_be16(val);
6202
6203         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6204 }
6205
6206 /**
6207  *
6208  *      t4_sge_decode_idma_state - decode the idma state
6209  *      @adap: the adapter
6210  *      @state: the state idma is stuck in
6211  */
6212 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6213 {
6214         static const char * const t4_decode[] = {
6215                 "IDMA_IDLE",
6216                 "IDMA_PUSH_MORE_CPL_FIFO",
6217                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6218                 "Not used",
6219                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6220                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6221                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6222                 "IDMA_SEND_FIFO_TO_IMSG",
6223                 "IDMA_FL_REQ_DATA_FL_PREP",
6224                 "IDMA_FL_REQ_DATA_FL",
6225                 "IDMA_FL_DROP",
6226                 "IDMA_FL_H_REQ_HEADER_FL",
6227                 "IDMA_FL_H_SEND_PCIEHDR",
6228                 "IDMA_FL_H_PUSH_CPL_FIFO",
6229                 "IDMA_FL_H_SEND_CPL",
6230                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6231                 "IDMA_FL_H_SEND_IP_HDR",
6232                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6233                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6234                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6235                 "IDMA_FL_D_SEND_PCIEHDR",
6236                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6237                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6238                 "IDMA_FL_SEND_PCIEHDR",
6239                 "IDMA_FL_PUSH_CPL_FIFO",
6240                 "IDMA_FL_SEND_CPL",
6241                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6242                 "IDMA_FL_SEND_PAYLOAD",
6243                 "IDMA_FL_REQ_NEXT_DATA_FL",
6244                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6245                 "IDMA_FL_SEND_PADDING",
6246                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6247                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6248                 "IDMA_FL_REQ_DATAFL_DONE",
6249                 "IDMA_FL_REQ_HEADERFL_DONE",
6250         };
6251         static const char * const t5_decode[] = {
6252                 "IDMA_IDLE",
6253                 "IDMA_ALMOST_IDLE",
6254                 "IDMA_PUSH_MORE_CPL_FIFO",
6255                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6256                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6257                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6258                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6259                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6260                 "IDMA_SEND_FIFO_TO_IMSG",
6261                 "IDMA_FL_REQ_DATA_FL",
6262                 "IDMA_FL_DROP",
6263                 "IDMA_FL_DROP_SEND_INC",
6264                 "IDMA_FL_H_REQ_HEADER_FL",
6265                 "IDMA_FL_H_SEND_PCIEHDR",
6266                 "IDMA_FL_H_PUSH_CPL_FIFO",
6267                 "IDMA_FL_H_SEND_CPL",
6268                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6269                 "IDMA_FL_H_SEND_IP_HDR",
6270                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6271                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6272                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6273                 "IDMA_FL_D_SEND_PCIEHDR",
6274                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6275                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6276                 "IDMA_FL_SEND_PCIEHDR",
6277                 "IDMA_FL_PUSH_CPL_FIFO",
6278                 "IDMA_FL_SEND_CPL",
6279                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6280                 "IDMA_FL_SEND_PAYLOAD",
6281                 "IDMA_FL_REQ_NEXT_DATA_FL",
6282                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6283                 "IDMA_FL_SEND_PADDING",
6284                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6285         };
6286         static const char * const t6_decode[] = {
6287                 "IDMA_IDLE",
6288                 "IDMA_PUSH_MORE_CPL_FIFO",
6289                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6290                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6291                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6292                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6293                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6294                 "IDMA_FL_REQ_DATA_FL",
6295                 "IDMA_FL_DROP",
6296                 "IDMA_FL_DROP_SEND_INC",
6297                 "IDMA_FL_H_REQ_HEADER_FL",
6298                 "IDMA_FL_H_SEND_PCIEHDR",
6299                 "IDMA_FL_H_PUSH_CPL_FIFO",
6300                 "IDMA_FL_H_SEND_CPL",
6301                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6302                 "IDMA_FL_H_SEND_IP_HDR",
6303                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6304                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6305                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6306                 "IDMA_FL_D_SEND_PCIEHDR",
6307                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6308                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6309                 "IDMA_FL_SEND_PCIEHDR",
6310                 "IDMA_FL_PUSH_CPL_FIFO",
6311                 "IDMA_FL_SEND_CPL",
6312                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6313                 "IDMA_FL_SEND_PAYLOAD",
6314                 "IDMA_FL_REQ_NEXT_DATA_FL",
6315                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6316                 "IDMA_FL_SEND_PADDING",
6317                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6318         };
6319         static const u32 sge_regs[] = {
6320                 A_SGE_DEBUG_DATA_LOW_INDEX_2,
6321                 A_SGE_DEBUG_DATA_LOW_INDEX_3,
6322                 A_SGE_DEBUG_DATA_HIGH_INDEX_10,
6323         };
6324         const char * const *sge_idma_decode;
6325         int sge_idma_decode_nstates;
6326         int i;
6327         unsigned int chip_version = chip_id(adapter);
6328
6329         /* Select the right set of decode strings to dump depending on the
6330          * adapter chip type.
6331          */
6332         switch (chip_version) {
6333         case CHELSIO_T4:
6334                 sge_idma_decode = (const char * const *)t4_decode;
6335                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6336                 break;
6337
6338         case CHELSIO_T5:
6339                 sge_idma_decode = (const char * const *)t5_decode;
6340                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6341                 break;
6342
6343         case CHELSIO_T6:
6344                 sge_idma_decode = (const char * const *)t6_decode;
6345                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6346                 break;
6347
6348         default:
6349                 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version);
6350                 return;
6351         }
6352
6353         if (state < sge_idma_decode_nstates)
6354                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6355         else
6356                 CH_WARN(adapter, "idma state %d unknown\n", state);
6357
6358         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6359                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6360                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6361 }
6362
6363 /**
6364  *      t4_sge_ctxt_flush - flush the SGE context cache
6365  *      @adap: the adapter
6366  *      @mbox: mailbox to use for the FW command
6367  *
6368  *      Issues a FW command through the given mailbox to flush the
6369  *      SGE context cache.
6370  */
6371 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6372 {
6373         int ret;
6374         u32 ldst_addrspace;
6375         struct fw_ldst_cmd c;
6376
6377         memset(&c, 0, sizeof(c));
6378         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
6379         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6380                                         F_FW_CMD_REQUEST | F_FW_CMD_READ |
6381                                         ldst_addrspace);
6382         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6383         c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
6384
6385         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6386         return ret;
6387 }
6388
6389 /**
6390  *      t4_fw_hello - establish communication with FW
6391  *      @adap: the adapter
6392  *      @mbox: mailbox to use for the FW command
6393  *      @evt_mbox: mailbox to receive async FW events
6394  *      @master: specifies the caller's willingness to be the device master
6395  *      @state: returns the current device state (if non-NULL)
6396  *
6397  *      Issues a command to establish communication with FW.  Returns either
6398  *      an error (negative integer) or the mailbox of the Master PF.
6399  */
6400 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6401                 enum dev_master master, enum dev_state *state)
6402 {
6403         int ret;
6404         struct fw_hello_cmd c;
6405         u32 v;
6406         unsigned int master_mbox;
6407         int retries = FW_CMD_HELLO_RETRIES;
6408
6409 retry:
6410         memset(&c, 0, sizeof(c));
6411         INIT_CMD(c, HELLO, WRITE);
6412         c.err_to_clearinit = cpu_to_be32(
6413                 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
6414                 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
6415                 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
6416                                         mbox : M_FW_HELLO_CMD_MBMASTER) |
6417                 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
6418                 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
6419                 F_FW_HELLO_CMD_CLEARINIT);
6420
6421         /*
6422          * Issue the HELLO command to the firmware.  If it's not successful
6423          * but indicates that we got a "busy" or "timeout" condition, retry
6424          * the HELLO until we exhaust our retry limit.  If we do exceed our
6425          * retry limit, check to see if the firmware left us any error
6426          * information and report that if so ...
6427          */
6428         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6429         if (ret != FW_SUCCESS) {
6430                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6431                         goto retry;
6432                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
6433                         t4_report_fw_error(adap);
6434                 return ret;
6435         }
6436
6437         v = be32_to_cpu(c.err_to_clearinit);
6438         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
6439         if (state) {
6440                 if (v & F_FW_HELLO_CMD_ERR)
6441                         *state = DEV_STATE_ERR;
6442                 else if (v & F_FW_HELLO_CMD_INIT)
6443                         *state = DEV_STATE_INIT;
6444                 else
6445                         *state = DEV_STATE_UNINIT;
6446         }
6447
6448         /*
6449          * If we're not the Master PF then we need to wait around for the
6450          * Master PF Driver to finish setting up the adapter.
6451          *
6452          * Note that we also do this wait if we're a non-Master-capable PF and
6453          * there is no current Master PF; a Master PF may show up momentarily
6454          * and we wouldn't want to fail pointlessly.  (This can happen when an
6455          * OS loads lots of different drivers rapidly at the same time).  In
6456          * this case, the Master PF returned by the firmware will be
6457          * M_PCIE_FW_MASTER so the test below will work ...
6458          */
6459         if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
6460             master_mbox != mbox) {
6461                 int waiting = FW_CMD_HELLO_TIMEOUT;
6462
6463                 /*
6464                  * Wait for the firmware to either indicate an error or
6465                  * initialized state.  If we see either of these we bail out
6466                  * and report the issue to the caller.  If we exhaust the
6467                  * "hello timeout" and we haven't exhausted our retries, try
6468                  * again.  Otherwise bail with a timeout error.
6469                  */
6470                 for (;;) {
6471                         u32 pcie_fw;
6472
6473                         msleep(50);
6474                         waiting -= 50;
6475
6476                         /*
6477                          * If neither Error nor Initialialized are indicated
6478                          * by the firmware keep waiting till we exhaust our
6479                          * timeout ... and then retry if we haven't exhausted
6480                          * our retries ...
6481                          */
6482                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
6483                         if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
6484                                 if (waiting <= 0) {
6485                                         if (retries-- > 0)
6486                                                 goto retry;
6487
6488                                         return -ETIMEDOUT;
6489                                 }
6490                                 continue;
6491                         }
6492
6493                         /*
6494                          * We either have an Error or Initialized condition
6495                          * report errors preferentially.
6496                          */
6497                         if (state) {
6498                                 if (pcie_fw & F_PCIE_FW_ERR)
6499                                         *state = DEV_STATE_ERR;
6500                                 else if (pcie_fw & F_PCIE_FW_INIT)
6501                                         *state = DEV_STATE_INIT;
6502                         }
6503
6504                         /*
6505                          * If we arrived before a Master PF was selected and
6506                          * there's not a valid Master PF, grab its identity
6507                          * for our caller.
6508                          */
6509                         if (master_mbox == M_PCIE_FW_MASTER &&
6510                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
6511                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
6512                         break;
6513                 }
6514         }
6515
6516         return master_mbox;
6517 }
6518
6519 /**
6520  *      t4_fw_bye - end communication with FW
6521  *      @adap: the adapter
6522  *      @mbox: mailbox to use for the FW command
6523  *
6524  *      Issues a command to terminate communication with FW.
6525  */
6526 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6527 {
6528         struct fw_bye_cmd c;
6529
6530         memset(&c, 0, sizeof(c));
6531         INIT_CMD(c, BYE, WRITE);
6532         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6533 }
6534
6535 /**
6536  *      t4_fw_reset - issue a reset to FW
6537  *      @adap: the adapter
6538  *      @mbox: mailbox to use for the FW command
6539  *      @reset: specifies the type of reset to perform
6540  *
6541  *      Issues a reset command of the specified type to FW.
6542  */
6543 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6544 {
6545         struct fw_reset_cmd c;
6546
6547         memset(&c, 0, sizeof(c));
6548         INIT_CMD(c, RESET, WRITE);
6549         c.val = cpu_to_be32(reset);
6550         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6551 }
6552
6553 /**
6554  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6555  *      @adap: the adapter
6556  *      @mbox: mailbox to use for the FW RESET command (if desired)
6557  *      @force: force uP into RESET even if FW RESET command fails
6558  *
6559  *      Issues a RESET command to firmware (if desired) with a HALT indication
6560  *      and then puts the microprocessor into RESET state.  The RESET command
6561  *      will only be issued if a legitimate mailbox is provided (mbox <=
6562  *      M_PCIE_FW_MASTER).
6563  *
6564  *      This is generally used in order for the host to safely manipulate the
6565  *      adapter without fear of conflicting with whatever the firmware might
6566  *      be doing.  The only way out of this state is to RESTART the firmware
6567  *      ...
6568  */
6569 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6570 {
6571         int ret = 0;
6572
6573         /*
6574          * If a legitimate mailbox is provided, issue a RESET command
6575          * with a HALT indication.
6576          */
6577         if (mbox <= M_PCIE_FW_MASTER) {
6578                 struct fw_reset_cmd c;
6579
6580                 memset(&c, 0, sizeof(c));
6581                 INIT_CMD(c, RESET, WRITE);
6582                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
6583                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
6584                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6585         }
6586
6587         /*
6588          * Normally we won't complete the operation if the firmware RESET
6589          * command fails but if our caller insists we'll go ahead and put the
6590          * uP into RESET.  This can be useful if the firmware is hung or even
6591          * missing ...  We'll have to take the risk of putting the uP into
6592          * RESET without the cooperation of firmware in that case.
6593          *
6594          * We also force the firmware's HALT flag to be on in case we bypassed
6595          * the firmware RESET command above or we're dealing with old firmware
6596          * which doesn't have the HALT capability.  This will serve as a flag
6597          * for the incoming firmware to know that it's coming out of a HALT
6598          * rather than a RESET ... if it's new enough to understand that ...
6599          */
6600         if (ret == 0 || force) {
6601                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
6602                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
6603                                  F_PCIE_FW_HALT);
6604         }
6605
6606         /*
6607          * And we always return the result of the firmware RESET command
6608          * even when we force the uP into RESET ...
6609          */
6610         return ret;
6611 }
6612
6613 /**
6614  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6615  *      @adap: the adapter
6616  *      @reset: if we want to do a RESET to restart things
6617  *
6618  *      Restart firmware previously halted by t4_fw_halt().  On successful
6619  *      return the previous PF Master remains as the new PF Master and there
6620  *      is no need to issue a new HELLO command, etc.
6621  *
6622  *      We do this in two ways:
6623  *
6624  *       1. If we're dealing with newer firmware we'll simply want to take
6625  *          the chip's microprocessor out of RESET.  This will cause the
6626  *          firmware to start up from its start vector.  And then we'll loop
6627  *          until the firmware indicates it's started again (PCIE_FW.HALT
6628  *          reset to 0) or we timeout.
6629  *
6630  *       2. If we're dealing with older firmware then we'll need to RESET
6631  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6632  *          flag and automatically RESET itself on startup.
6633  */
6634 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6635 {
6636         if (reset) {
6637                 /*
6638                  * Since we're directing the RESET instead of the firmware
6639                  * doing it automatically, we need to clear the PCIE_FW.HALT
6640                  * bit.
6641                  */
6642                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
6643
6644                 /*
6645                  * If we've been given a valid mailbox, first try to get the
6646                  * firmware to do the RESET.  If that works, great and we can
6647                  * return success.  Otherwise, if we haven't been given a
6648                  * valid mailbox or the RESET command failed, fall back to
6649                  * hitting the chip with a hammer.
6650                  */
6651                 if (mbox <= M_PCIE_FW_MASTER) {
6652                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6653                         msleep(100);
6654                         if (t4_fw_reset(adap, mbox,
6655                                         F_PIORST | F_PIORSTMODE) == 0)
6656                                 return 0;
6657                 }
6658
6659                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
6660                 msleep(2000);
6661         } else {
6662                 int ms;
6663
6664                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6665                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6666                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
6667                                 return FW_SUCCESS;
6668                         msleep(100);
6669                         ms += 100;
6670                 }
6671                 return -ETIMEDOUT;
6672         }
6673         return 0;
6674 }
6675
6676 /**
6677  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6678  *      @adap: the adapter
6679  *      @mbox: mailbox to use for the FW RESET command (if desired)
6680  *      @fw_data: the firmware image to write
6681  *      @size: image size
6682  *      @force: force upgrade even if firmware doesn't cooperate
6683  *
6684  *      Perform all of the steps necessary for upgrading an adapter's
6685  *      firmware image.  Normally this requires the cooperation of the
6686  *      existing firmware in order to halt all existing activities
6687  *      but if an invalid mailbox token is passed in we skip that step
6688  *      (though we'll still put the adapter microprocessor into RESET in
6689  *      that case).
6690  *
6691  *      On successful return the new firmware will have been loaded and
6692  *      the adapter will have been fully RESET losing all previous setup
6693  *      state.  On unsuccessful return the adapter may be completely hosed ...
6694  *      positive errno indicates that the adapter is ~probably~ intact, a
6695  *      negative errno indicates that things are looking bad ...
6696  */
6697 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6698                   const u8 *fw_data, unsigned int size, int force)
6699 {
6700         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6701         unsigned int bootstrap =
6702             be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
6703         int reset, ret;
6704
6705         if (!t4_fw_matches_chip(adap, fw_hdr))
6706                 return -EINVAL;
6707
6708         if (!bootstrap) {
6709                 ret = t4_fw_halt(adap, mbox, force);
6710                 if (ret < 0 && !force)
6711                         return ret;
6712         }
6713
6714         ret = t4_load_fw(adap, fw_data, size);
6715         if (ret < 0 || bootstrap)
6716                 return ret;
6717
6718         /*
6719          * Older versions of the firmware don't understand the new
6720          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6721          * restart.  So for newly loaded older firmware we'll have to do the
6722          * RESET for it so it starts up on a clean slate.  We can tell if
6723          * the newly loaded firmware will handle this right by checking
6724          * its header flags to see if it advertises the capability.
6725          */
6726         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6727         return t4_fw_restart(adap, mbox, reset);
6728 }
6729
6730 /**
6731  *      t4_fw_initialize - ask FW to initialize the device
6732  *      @adap: the adapter
6733  *      @mbox: mailbox to use for the FW command
6734  *
6735  *      Issues a command to FW to partially initialize the device.  This
6736  *      performs initialization that generally doesn't depend on user input.
6737  */
6738 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6739 {
6740         struct fw_initialize_cmd c;
6741
6742         memset(&c, 0, sizeof(c));
6743         INIT_CMD(c, INITIALIZE, WRITE);
6744         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6745 }
6746
6747 /**
6748  *      t4_query_params_rw - query FW or device parameters
6749  *      @adap: the adapter
6750  *      @mbox: mailbox to use for the FW command
6751  *      @pf: the PF
6752  *      @vf: the VF
6753  *      @nparams: the number of parameters
6754  *      @params: the parameter names
6755  *      @val: the parameter values
6756  *      @rw: Write and read flag
6757  *
6758  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
6759  *      queried at once.
6760  */
6761 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6762                        unsigned int vf, unsigned int nparams, const u32 *params,
6763                        u32 *val, int rw)
6764 {
6765         int i, ret;
6766         struct fw_params_cmd c;
6767         __be32 *p = &c.param[0].mnem;
6768
6769         if (nparams > 7)
6770                 return -EINVAL;
6771
6772         memset(&c, 0, sizeof(c));
6773         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6774                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
6775                                   V_FW_PARAMS_CMD_PFN(pf) |
6776                                   V_FW_PARAMS_CMD_VFN(vf));
6777         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6778
6779         for (i = 0; i < nparams; i++) {
6780                 *p++ = cpu_to_be32(*params++);
6781                 if (rw)
6782                         *p = cpu_to_be32(*(val + i));
6783                 p++;
6784         }
6785
6786         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6787         if (ret == 0)
6788                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6789                         *val++ = be32_to_cpu(*p);
6790         return ret;
6791 }
6792
6793 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6794                     unsigned int vf, unsigned int nparams, const u32 *params,
6795                     u32 *val)
6796 {
6797         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6798 }
6799
6800 /**
6801  *      t4_set_params_timeout - sets FW or device parameters
6802  *      @adap: the adapter
6803  *      @mbox: mailbox to use for the FW command
6804  *      @pf: the PF
6805  *      @vf: the VF
6806  *      @nparams: the number of parameters
6807  *      @params: the parameter names
6808  *      @val: the parameter values
6809  *      @timeout: the timeout time
6810  *
6811  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6812  *      specified at once.
6813  */
6814 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6815                           unsigned int pf, unsigned int vf,
6816                           unsigned int nparams, const u32 *params,
6817                           const u32 *val, int timeout)
6818 {
6819         struct fw_params_cmd c;
6820         __be32 *p = &c.param[0].mnem;
6821
6822         if (nparams > 7)
6823                 return -EINVAL;
6824
6825         memset(&c, 0, sizeof(c));
6826         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6827                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6828                                   V_FW_PARAMS_CMD_PFN(pf) |
6829                                   V_FW_PARAMS_CMD_VFN(vf));
6830         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6831
6832         while (nparams--) {
6833                 *p++ = cpu_to_be32(*params++);
6834                 *p++ = cpu_to_be32(*val++);
6835         }
6836
6837         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6838 }
6839
6840 /**
6841  *      t4_set_params - sets FW or device parameters
6842  *      @adap: the adapter
6843  *      @mbox: mailbox to use for the FW command
6844  *      @pf: the PF
6845  *      @vf: the VF
6846  *      @nparams: the number of parameters
6847  *      @params: the parameter names
6848  *      @val: the parameter values
6849  *
6850  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6851  *      specified at once.
6852  */
6853 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6854                   unsigned int vf, unsigned int nparams, const u32 *params,
6855                   const u32 *val)
6856 {
6857         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6858                                      FW_CMD_MAX_TIMEOUT);
6859 }
6860
6861 /**
6862  *      t4_cfg_pfvf - configure PF/VF resource limits
6863  *      @adap: the adapter
6864  *      @mbox: mailbox to use for the FW command
6865  *      @pf: the PF being configured
6866  *      @vf: the VF being configured
6867  *      @txq: the max number of egress queues
6868  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
6869  *      @rxqi: the max number of interrupt-capable ingress queues
6870  *      @rxq: the max number of interruptless ingress queues
6871  *      @tc: the PCI traffic class
6872  *      @vi: the max number of virtual interfaces
6873  *      @cmask: the channel access rights mask for the PF/VF
6874  *      @pmask: the port access rights mask for the PF/VF
6875  *      @nexact: the maximum number of exact MPS filters
6876  *      @rcaps: read capabilities
6877  *      @wxcaps: write/execute capabilities
6878  *
6879  *      Configures resource limits and capabilities for a physical or virtual
6880  *      function.
6881  */
6882 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6883                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6884                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6885                 unsigned int vi, unsigned int cmask, unsigned int pmask,
6886                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6887 {
6888         struct fw_pfvf_cmd c;
6889
6890         memset(&c, 0, sizeof(c));
6891         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
6892                                   F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
6893                                   V_FW_PFVF_CMD_VFN(vf));
6894         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6895         c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
6896                                      V_FW_PFVF_CMD_NIQ(rxq));
6897         c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
6898                                     V_FW_PFVF_CMD_PMASK(pmask) |
6899                                     V_FW_PFVF_CMD_NEQ(txq));
6900         c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
6901                                       V_FW_PFVF_CMD_NVI(vi) |
6902                                       V_FW_PFVF_CMD_NEXACTF(nexact));
6903         c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
6904                                      V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
6905                                      V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
6906         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6907 }
6908
6909 /**
6910  *      t4_alloc_vi_func - allocate a virtual interface
6911  *      @adap: the adapter
6912  *      @mbox: mailbox to use for the FW command
6913  *      @port: physical port associated with the VI
6914  *      @pf: the PF owning the VI
6915  *      @vf: the VF owning the VI
6916  *      @nmac: number of MAC addresses needed (1 to 5)
6917  *      @mac: the MAC addresses of the VI
6918  *      @rss_size: size of RSS table slice associated with this VI
6919  *      @portfunc: which Port Application Function MAC Address is desired
6920  *      @idstype: Intrusion Detection Type
6921  *
6922  *      Allocates a virtual interface for the given physical port.  If @mac is
6923  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
6924  *      If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
6925  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
6926  *      stored consecutively so the space needed is @nmac * 6 bytes.
6927  *      Returns a negative error number or the non-negative VI id.
6928  */
6929 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
6930                      unsigned int port, unsigned int pf, unsigned int vf,
6931                      unsigned int nmac, u8 *mac, u16 *rss_size,
6932                      unsigned int portfunc, unsigned int idstype)
6933 {
6934         int ret;
6935         struct fw_vi_cmd c;
6936
6937         memset(&c, 0, sizeof(c));
6938         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
6939                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
6940                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
6941         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
6942         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
6943                                      V_FW_VI_CMD_FUNC(portfunc));
6944         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
6945         c.nmac = nmac - 1;
6946         if(!rss_size)
6947                 c.norss_rsssize = F_FW_VI_CMD_NORSS;
6948
6949         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6950         if (ret)
6951                 return ret;
6952
6953         if (mac) {
6954                 memcpy(mac, c.mac, sizeof(c.mac));
6955                 switch (nmac) {
6956                 case 5:
6957                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6958                 case 4:
6959                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6960                 case 3:
6961                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6962                 case 2:
6963                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
6964                 }
6965         }
6966         if (rss_size)
6967                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
6968         return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
6969 }
6970
6971 /**
6972  *      t4_alloc_vi - allocate an [Ethernet Function] virtual interface
6973  *      @adap: the adapter
6974  *      @mbox: mailbox to use for the FW command
6975  *      @port: physical port associated with the VI
6976  *      @pf: the PF owning the VI
6977  *      @vf: the VF owning the VI
6978  *      @nmac: number of MAC addresses needed (1 to 5)
6979  *      @mac: the MAC addresses of the VI
6980  *      @rss_size: size of RSS table slice associated with this VI
6981  *
6982  *      backwards compatible and convieniance routine to allocate a Virtual
6983  *      Interface with a Ethernet Port Application Function and Intrustion
6984  *      Detection System disabled.
6985  */
6986 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6987                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6988                 u16 *rss_size)
6989 {
6990         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
6991                                 FW_VI_FUNC_ETH, 0);
6992 }
6993
6994 /**
6995  *      t4_free_vi - free a virtual interface
6996  *      @adap: the adapter
6997  *      @mbox: mailbox to use for the FW command
6998  *      @pf: the PF owning the VI
6999  *      @vf: the VF owning the VI
7000  *      @viid: virtual interface identifiler
7001  *
7002  *      Free a previously allocated virtual interface.
7003  */
7004 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7005                unsigned int vf, unsigned int viid)
7006 {
7007         struct fw_vi_cmd c;
7008
7009         memset(&c, 0, sizeof(c));
7010         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
7011                                   F_FW_CMD_REQUEST |
7012                                   F_FW_CMD_EXEC |
7013                                   V_FW_VI_CMD_PFN(pf) |
7014                                   V_FW_VI_CMD_VFN(vf));
7015         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
7016         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
7017
7018         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7019 }
7020
7021 /**
7022  *      t4_set_rxmode - set Rx properties of a virtual interface
7023  *      @adap: the adapter
7024  *      @mbox: mailbox to use for the FW command
7025  *      @viid: the VI id
7026  *      @mtu: the new MTU or -1
7027  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7028  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7029  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7030  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7031  *      @sleep_ok: if true we may sleep while awaiting command completion
7032  *
7033  *      Sets Rx properties of a virtual interface.
7034  */
7035 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7036                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7037                   bool sleep_ok)
7038 {
7039         struct fw_vi_rxmode_cmd c;
7040
7041         /* convert to FW values */
7042         if (mtu < 0)
7043                 mtu = M_FW_VI_RXMODE_CMD_MTU;
7044         if (promisc < 0)
7045                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
7046         if (all_multi < 0)
7047                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
7048         if (bcast < 0)
7049                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
7050         if (vlanex < 0)
7051                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
7052
7053         memset(&c, 0, sizeof(c));
7054         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
7055                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7056                                    V_FW_VI_RXMODE_CMD_VIID(viid));
7057         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7058         c.mtu_to_vlanexen =
7059                 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
7060                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
7061                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
7062                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
7063                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
7064         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7065 }
7066
7067 /**
7068  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7069  *      @adap: the adapter
7070  *      @mbox: mailbox to use for the FW command
7071  *      @viid: the VI id
7072  *      @free: if true any existing filters for this VI id are first removed
7073  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7074  *      @addr: the MAC address(es)
7075  *      @idx: where to store the index of each allocated filter
7076  *      @hash: pointer to hash address filter bitmap
7077  *      @sleep_ok: call is allowed to sleep
7078  *
7079  *      Allocates an exact-match filter for each of the supplied addresses and
7080  *      sets it to the corresponding address.  If @idx is not %NULL it should
7081  *      have at least @naddr entries, each of which will be set to the index of
7082  *      the filter allocated for the corresponding MAC address.  If a filter
7083  *      could not be allocated for an address its index is set to 0xffff.
7084  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7085  *      are hashed and update the hash filter bitmap pointed at by @hash.
7086  *
7087  *      Returns a negative error number or the number of filters allocated.
7088  */
7089 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7090                       unsigned int viid, bool free, unsigned int naddr,
7091                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7092 {
7093         int offset, ret = 0;
7094         struct fw_vi_mac_cmd c;
7095         unsigned int nfilters = 0;
7096         unsigned int max_naddr = adap->chip_params->mps_tcam_size;
7097         unsigned int rem = naddr;
7098
7099         if (naddr > max_naddr)
7100                 return -EINVAL;
7101
7102         for (offset = 0; offset < naddr ; /**/) {
7103                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7104                                          ? rem
7105                                          : ARRAY_SIZE(c.u.exact));
7106                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7107                                                      u.exact[fw_naddr]), 16);
7108                 struct fw_vi_mac_exact *p;
7109                 int i;
7110
7111                 memset(&c, 0, sizeof(c));
7112                 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7113                                            F_FW_CMD_REQUEST |
7114                                            F_FW_CMD_WRITE |
7115                                            V_FW_CMD_EXEC(free) |
7116                                            V_FW_VI_MAC_CMD_VIID(viid));
7117                 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
7118                                                   V_FW_CMD_LEN16(len16));
7119
7120                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7121                         p->valid_to_idx =
7122                                 cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
7123                                             V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
7124                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7125                 }
7126
7127                 /*
7128                  * It's okay if we run out of space in our MAC address arena.
7129                  * Some of the addresses we submit may get stored so we need
7130                  * to run through the reply to see what the results were ...
7131                  */
7132                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7133                 if (ret && ret != -FW_ENOMEM)
7134                         break;
7135
7136                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7137                         u16 index = G_FW_VI_MAC_CMD_IDX(
7138                                                 be16_to_cpu(p->valid_to_idx));
7139
7140                         if (idx)
7141                                 idx[offset+i] = (index >=  max_naddr
7142                                                  ? 0xffff
7143                                                  : index);
7144                         if (index < max_naddr)
7145                                 nfilters++;
7146                         else if (hash)
7147                                 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
7148                 }
7149
7150                 free = false;
7151                 offset += fw_naddr;
7152                 rem -= fw_naddr;
7153         }
7154
7155         if (ret == 0 || ret == -FW_ENOMEM)
7156                 ret = nfilters;
7157         return ret;
7158 }
7159
7160 /**
7161  *      t4_change_mac - modifies the exact-match filter for a MAC address
7162  *      @adap: the adapter
7163  *      @mbox: mailbox to use for the FW command
7164  *      @viid: the VI id
7165  *      @idx: index of existing filter for old value of MAC address, or -1
7166  *      @addr: the new MAC address value
7167  *      @persist: whether a new MAC allocation should be persistent
7168  *      @add_smt: if true also add the address to the HW SMT
7169  *
7170  *      Modifies an exact-match filter and sets it to the new MAC address if
7171  *      @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
7172  *      latter case the address is added persistently if @persist is %true.
7173  *
7174  *      Note that in general it is not possible to modify the value of a given
7175  *      filter so the generic way to modify an address filter is to free the one
7176  *      being used by the old address value and allocate a new filter for the
7177  *      new address value.
7178  *
7179  *      Returns a negative error number or the index of the filter with the new
7180  *      MAC value.  Note that this index may differ from @idx.
7181  */
7182 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7183                   int idx, const u8 *addr, bool persist, bool add_smt)
7184 {
7185         int ret, mode;
7186         struct fw_vi_mac_cmd c;
7187         struct fw_vi_mac_exact *p = c.u.exact;
7188         unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
7189
7190         if (idx < 0)            /* new allocation */
7191                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7192         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7193
7194         memset(&c, 0, sizeof(c));
7195         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7196                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7197                                    V_FW_VI_MAC_CMD_VIID(viid));
7198         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
7199         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
7200                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
7201                                       V_FW_VI_MAC_CMD_IDX(idx));
7202         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7203
7204         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7205         if (ret == 0) {
7206                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
7207                 if (ret >= max_mac_addr)
7208                         ret = -ENOMEM;
7209         }
7210         return ret;
7211 }
7212
7213 /**
7214  *      t4_set_addr_hash - program the MAC inexact-match hash filter
7215  *      @adap: the adapter
7216  *      @mbox: mailbox to use for the FW command
7217  *      @viid: the VI id
7218  *      @ucast: whether the hash filter should also match unicast addresses
7219  *      @vec: the value to be written to the hash filter
7220  *      @sleep_ok: call is allowed to sleep
7221  *
7222  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
7223  */
7224 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7225                      bool ucast, u64 vec, bool sleep_ok)
7226 {
7227         struct fw_vi_mac_cmd c;
7228         u32 val;
7229
7230         memset(&c, 0, sizeof(c));
7231         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7232                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7233                                    V_FW_VI_ENABLE_CMD_VIID(viid));
7234         val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
7235               V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
7236         c.freemacs_to_len16 = cpu_to_be32(val);
7237         c.u.hash.hashvec = cpu_to_be64(vec);
7238         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7239 }
7240
7241 /**
7242  *      t4_enable_vi_params - enable/disable a virtual interface
7243  *      @adap: the adapter
7244  *      @mbox: mailbox to use for the FW command
7245  *      @viid: the VI id
7246  *      @rx_en: 1=enable Rx, 0=disable Rx
7247  *      @tx_en: 1=enable Tx, 0=disable Tx
7248  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7249  *
7250  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7251  *      only makes sense when enabling a Virtual Interface ...
7252  */
7253 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7254                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7255 {
7256         struct fw_vi_enable_cmd c;
7257
7258         memset(&c, 0, sizeof(c));
7259         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7260                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7261                                    V_FW_VI_ENABLE_CMD_VIID(viid));
7262         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
7263                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
7264                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
7265                                      FW_LEN16(c));
7266         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7267 }
7268
7269 /**
7270  *      t4_enable_vi - enable/disable a virtual interface
7271  *      @adap: the adapter
7272  *      @mbox: mailbox to use for the FW command
7273  *      @viid: the VI id
7274  *      @rx_en: 1=enable Rx, 0=disable Rx
7275  *      @tx_en: 1=enable Tx, 0=disable Tx
7276  *
7277  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7278  *      only makes sense when enabling a Virtual Interface ...
7279  */
7280 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7281                  bool rx_en, bool tx_en)
7282 {
7283         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7284 }
7285
7286 /**
7287  *      t4_identify_port - identify a VI's port by blinking its LED
7288  *      @adap: the adapter
7289  *      @mbox: mailbox to use for the FW command
7290  *      @viid: the VI id
7291  *      @nblinks: how many times to blink LED at 2.5 Hz
7292  *
7293  *      Identifies a VI's port by blinking its LED.
7294  */
7295 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7296                      unsigned int nblinks)
7297 {
7298         struct fw_vi_enable_cmd c;
7299
7300         memset(&c, 0, sizeof(c));
7301         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7302                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7303                                    V_FW_VI_ENABLE_CMD_VIID(viid));
7304         c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
7305         c.blinkdur = cpu_to_be16(nblinks);
7306         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7307 }
7308
7309 /**
7310  *      t4_iq_stop - stop an ingress queue and its FLs
7311  *      @adap: the adapter
7312  *      @mbox: mailbox to use for the FW command
7313  *      @pf: the PF owning the queues
7314  *      @vf: the VF owning the queues
7315  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7316  *      @iqid: ingress queue id
7317  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7318  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7319  *
7320  *      Stops an ingress queue and its associated FLs, if any.  This causes
7321  *      any current or future data/messages destined for these queues to be
7322  *      tossed.
7323  */
7324 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7325                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7326                unsigned int fl0id, unsigned int fl1id)
7327 {
7328         struct fw_iq_cmd c;
7329
7330         memset(&c, 0, sizeof(c));
7331         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7332                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7333                                   V_FW_IQ_CMD_VFN(vf));
7334         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
7335         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7336         c.iqid = cpu_to_be16(iqid);
7337         c.fl0id = cpu_to_be16(fl0id);
7338         c.fl1id = cpu_to_be16(fl1id);
7339         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7340 }
7341
7342 /**
7343  *      t4_iq_free - free an ingress queue and its FLs
7344  *      @adap: the adapter
7345  *      @mbox: mailbox to use for the FW command
7346  *      @pf: the PF owning the queues
7347  *      @vf: the VF owning the queues
7348  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7349  *      @iqid: ingress queue id
7350  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7351  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7352  *
7353  *      Frees an ingress queue and its associated FLs, if any.
7354  */
7355 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7356                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7357                unsigned int fl0id, unsigned int fl1id)
7358 {
7359         struct fw_iq_cmd c;
7360
7361         memset(&c, 0, sizeof(c));
7362         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7363                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7364                                   V_FW_IQ_CMD_VFN(vf));
7365         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
7366         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7367         c.iqid = cpu_to_be16(iqid);
7368         c.fl0id = cpu_to_be16(fl0id);
7369         c.fl1id = cpu_to_be16(fl1id);
7370         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7371 }
7372
7373 /**
7374  *      t4_eth_eq_free - free an Ethernet egress queue
7375  *      @adap: the adapter
7376  *      @mbox: mailbox to use for the FW command
7377  *      @pf: the PF owning the queue
7378  *      @vf: the VF owning the queue
7379  *      @eqid: egress queue id
7380  *
7381  *      Frees an Ethernet egress queue.
7382  */
7383 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7384                    unsigned int vf, unsigned int eqid)
7385 {
7386         struct fw_eq_eth_cmd c;
7387
7388         memset(&c, 0, sizeof(c));
7389         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
7390                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7391                                   V_FW_EQ_ETH_CMD_PFN(pf) |
7392                                   V_FW_EQ_ETH_CMD_VFN(vf));
7393         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
7394         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
7395         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7396 }
7397
7398 /**
7399  *      t4_ctrl_eq_free - free a control egress queue
7400  *      @adap: the adapter
7401  *      @mbox: mailbox to use for the FW command
7402  *      @pf: the PF owning the queue
7403  *      @vf: the VF owning the queue
7404  *      @eqid: egress queue id
7405  *
7406  *      Frees a control egress queue.
7407  */
7408 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7409                     unsigned int vf, unsigned int eqid)
7410 {
7411         struct fw_eq_ctrl_cmd c;
7412
7413         memset(&c, 0, sizeof(c));
7414         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
7415                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7416                                   V_FW_EQ_CTRL_CMD_PFN(pf) |
7417                                   V_FW_EQ_CTRL_CMD_VFN(vf));
7418         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
7419         c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
7420         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7421 }
7422
7423 /**
7424  *      t4_ofld_eq_free - free an offload egress queue
7425  *      @adap: the adapter
7426  *      @mbox: mailbox to use for the FW command
7427  *      @pf: the PF owning the queue
7428  *      @vf: the VF owning the queue
7429  *      @eqid: egress queue id
7430  *
7431  *      Frees a control egress queue.
7432  */
7433 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7434                     unsigned int vf, unsigned int eqid)
7435 {
7436         struct fw_eq_ofld_cmd c;
7437
7438         memset(&c, 0, sizeof(c));
7439         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
7440                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7441                                   V_FW_EQ_OFLD_CMD_PFN(pf) |
7442                                   V_FW_EQ_OFLD_CMD_VFN(vf));
7443         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
7444         c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
7445         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7446 }
7447
7448 /**
7449  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7450  *      @link_down_rc: Link Down Reason Code
7451  *
7452  *      Returns a string representation of the Link Down Reason Code.
7453  */
7454 const char *t4_link_down_rc_str(unsigned char link_down_rc)
7455 {
7456         static const char *reason[] = {
7457                 "Link Down",
7458                 "Remote Fault",
7459                 "Auto-negotiation Failure",
7460                 "Reserved3",
7461                 "Insufficient Airflow",
7462                 "Unable To Determine Reason",
7463                 "No RX Signal Detected",
7464                 "Reserved7",
7465         };
7466
7467         if (link_down_rc >= ARRAY_SIZE(reason))
7468                 return "Bad Reason Code";
7469
7470         return reason[link_down_rc];
7471 }
7472
7473 /**
7474  *      t4_handle_fw_rpl - process a FW reply message
7475  *      @adap: the adapter
7476  *      @rpl: start of the FW message
7477  *
7478  *      Processes a FW message, such as link state change messages.
7479  */
7480 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7481 {
7482         u8 opcode = *(const u8 *)rpl;
7483         const struct fw_port_cmd *p = (const void *)rpl;
7484         unsigned int action =
7485                         G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
7486
7487         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7488                 /* link/module state change message */
7489                 int speed = 0, fc = 0, i;
7490                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
7491                 struct port_info *pi = NULL;
7492                 struct link_config *lc;
7493                 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7494                 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
7495                 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
7496
7497                 if (stat & F_FW_PORT_CMD_RXPAUSE)
7498                         fc |= PAUSE_RX;
7499                 if (stat & F_FW_PORT_CMD_TXPAUSE)
7500                         fc |= PAUSE_TX;
7501                 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
7502                         speed = 100;
7503                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
7504                         speed = 1000;
7505                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
7506                         speed = 10000;
7507                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
7508                         speed = 25000;
7509                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
7510                         speed = 40000;
7511                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
7512                         speed = 100000;
7513
7514                 for_each_port(adap, i) {
7515                         pi = adap2pinfo(adap, i);
7516                         if (pi->tx_chan == chan)
7517                                 break;
7518                 }
7519                 lc = &pi->link_cfg;
7520
7521                 if (mod != pi->mod_type) {
7522                         pi->mod_type = mod;
7523                         t4_os_portmod_changed(adap, i);
7524                 }
7525                 if (link_ok != lc->link_ok || speed != lc->speed ||
7526                     fc != lc->fc) {                    /* something changed */
7527                         if (!link_ok && lc->link_ok)
7528                                 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
7529                         lc->link_ok = link_ok;
7530                         lc->speed = speed;
7531                         lc->fc = fc;
7532                         lc->supported = be16_to_cpu(p->u.info.pcap);
7533                         lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7534                         t4_os_link_changed(adap, i, link_ok);
7535                 }
7536         } else {
7537                 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
7538                 return -EINVAL;
7539         }
7540         return 0;
7541 }
7542
7543 /**
7544  *      get_pci_mode - determine a card's PCI mode
7545  *      @adapter: the adapter
7546  *      @p: where to store the PCI settings
7547  *
7548  *      Determines a card's PCI mode and associated parameters, such as speed
7549  *      and width.
7550  */
7551 static void get_pci_mode(struct adapter *adapter,
7552                                    struct pci_params *p)
7553 {
7554         u16 val;
7555         u32 pcie_cap;
7556
7557         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7558         if (pcie_cap) {
7559                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
7560                 p->speed = val & PCI_EXP_LNKSTA_CLS;
7561                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7562         }
7563 }
7564
7565 /**
7566  *      init_link_config - initialize a link's SW state
7567  *      @lc: structure holding the link state
7568  *      @pcaps: supported link capabilities
7569  *      @acaps: advertised link capabilities
7570  *
7571  *      Initializes the SW state maintained for each link, including the link's
7572  *      capabilities and default speed/flow-control/autonegotiation settings.
7573  */
7574 static void init_link_config(struct link_config *lc, unsigned int pcaps,
7575                              unsigned int acaps)
7576 {
7577         unsigned int fec;
7578
7579         lc->supported = pcaps;
7580         lc->lp_advertising = 0;
7581         lc->requested_speed = 0;
7582         lc->speed = 0;
7583         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7584         lc->link_ok = 0;
7585         lc->link_down_rc = 255;
7586
7587         fec = 0;
7588         if (acaps & FW_PORT_CAP_FEC_RS)
7589                 fec |= FEC_RS;
7590         if (acaps & FW_PORT_CAP_FEC_BASER_RS)
7591                 fec |= FEC_BASER_RS;
7592         if (acaps & FW_PORT_CAP_FEC_RESERVED)
7593                 fec |= FEC_RESERVED;
7594         lc->requested_fec = lc->fec = fec;
7595
7596         if (lc->supported & FW_PORT_CAP_ANEG) {
7597                 lc->advertising = lc->supported & ADVERT_MASK;
7598                 lc->autoneg = AUTONEG_ENABLE;
7599                 lc->requested_fc |= PAUSE_AUTONEG;
7600         } else {
7601                 lc->advertising = 0;
7602                 lc->autoneg = AUTONEG_DISABLE;
7603         }
7604 }
7605
7606 struct flash_desc {
7607         u32 vendor_and_model_id;
7608         u32 size_mb;
7609 };
7610
7611 int t4_get_flash_params(struct adapter *adapter)
7612 {
7613         /*
7614          * Table for non-Numonix supported flash parts.  Numonix parts are left
7615          * to the preexisting well-tested code.  All flash parts have 64KB
7616          * sectors.
7617          */
7618         static struct flash_desc supported_flash[] = {
7619                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
7620         };
7621
7622         int ret;
7623         u32 info = 0;
7624
7625         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
7626         if (!ret)
7627                 ret = sf1_read(adapter, 3, 0, 1, &info);
7628         t4_write_reg(adapter, A_SF_OP, 0);      /* unlock SF */
7629         if (ret < 0)
7630                 return ret;
7631
7632         for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7633                 if (supported_flash[ret].vendor_and_model_id == info) {
7634                         adapter->params.sf_size = supported_flash[ret].size_mb;
7635                         adapter->params.sf_nsec =
7636                                 adapter->params.sf_size / SF_SEC_SIZE;
7637                         return 0;
7638                 }
7639
7640         if ((info & 0xff) != 0x20)              /* not a Numonix flash */
7641                 return -EINVAL;
7642         info >>= 16;                            /* log2 of size */
7643         if (info >= 0x14 && info < 0x18)
7644                 adapter->params.sf_nsec = 1 << (info - 16);
7645         else if (info == 0x18)
7646                 adapter->params.sf_nsec = 64;
7647         else
7648                 return -EINVAL;
7649         adapter->params.sf_size = 1 << info;
7650
7651         /*
7652          * We should ~probably~ reject adapters with FLASHes which are too
7653          * small but we have some legacy FPGAs with small FLASHes that we'd
7654          * still like to use.  So instead we emit a scary message ...
7655          */
7656         if (adapter->params.sf_size < FLASH_MIN_SIZE)
7657                 CH_WARN(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
7658                         adapter->params.sf_size, FLASH_MIN_SIZE);
7659
7660         return 0;
7661 }
7662
7663 static void set_pcie_completion_timeout(struct adapter *adapter,
7664                                                   u8 range)
7665 {
7666         u16 val;
7667         u32 pcie_cap;
7668
7669         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7670         if (pcie_cap) {
7671                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
7672                 val &= 0xfff0;
7673                 val |= range ;
7674                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
7675         }
7676 }
7677
7678 const struct chip_params *t4_get_chip_params(int chipid)
7679 {
7680         static const struct chip_params chip_params[] = {
7681                 {
7682                         /* T4 */
7683                         .nchan = NCHAN,
7684                         .pm_stats_cnt = PM_NSTATS,
7685                         .cng_ch_bits_log = 2,
7686                         .nsched_cls = 15,
7687                         .cim_num_obq = CIM_NUM_OBQ,
7688                         .mps_rplc_size = 128,
7689                         .vfcount = 128,
7690                         .sge_fl_db = F_DBPRIO,
7691                         .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
7692                 },
7693                 {
7694                         /* T5 */
7695                         .nchan = NCHAN,
7696                         .pm_stats_cnt = PM_NSTATS,
7697                         .cng_ch_bits_log = 2,
7698                         .nsched_cls = 16,
7699                         .cim_num_obq = CIM_NUM_OBQ_T5,
7700                         .mps_rplc_size = 128,
7701                         .vfcount = 128,
7702                         .sge_fl_db = F_DBPRIO | F_DBTYPE,
7703                         .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7704                 },
7705                 {
7706                         /* T6 */
7707                         .nchan = T6_NCHAN,
7708                         .pm_stats_cnt = T6_PM_NSTATS,
7709                         .cng_ch_bits_log = 3,
7710                         .nsched_cls = 16,
7711                         .cim_num_obq = CIM_NUM_OBQ_T5,
7712                         .mps_rplc_size = 256,
7713                         .vfcount = 256,
7714                         .sge_fl_db = 0,
7715                         .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7716                 },
7717         };
7718
7719         chipid -= CHELSIO_T4;
7720         if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
7721                 return NULL;
7722
7723         return &chip_params[chipid];
7724 }
7725
7726 /**
7727  *      t4_prep_adapter - prepare SW and HW for operation
7728  *      @adapter: the adapter
7729  *      @buf: temporary space of at least VPD_LEN size provided by the caller.
7730  *
7731  *      Initialize adapter SW state for the various HW modules, set initial
7732  *      values for some adapter tunables, take PHYs out of reset, and
7733  *      initialize the MDIO interface.
7734  */
7735 int t4_prep_adapter(struct adapter *adapter, u8 *buf)
7736 {
7737         int ret;
7738         uint16_t device_id;
7739         uint32_t pl_rev;
7740
7741         get_pci_mode(adapter, &adapter->params.pci);
7742
7743         pl_rev = t4_read_reg(adapter, A_PL_REV);
7744         adapter->params.chipid = G_CHIPID(pl_rev);
7745         adapter->params.rev = G_REV(pl_rev);
7746         if (adapter->params.chipid == 0) {
7747                 /* T4 did not have chipid in PL_REV (T5 onwards do) */
7748                 adapter->params.chipid = CHELSIO_T4;
7749
7750                 /* T4A1 chip is not supported */
7751                 if (adapter->params.rev == 1) {
7752                         CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
7753                         return -EINVAL;
7754                 }
7755         }
7756
7757         adapter->chip_params = t4_get_chip_params(chip_id(adapter));
7758         if (adapter->chip_params == NULL)
7759                 return -EINVAL;
7760
7761         adapter->params.pci.vpd_cap_addr =
7762             t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
7763
7764         ret = t4_get_flash_params(adapter);
7765         if (ret < 0)
7766                 return ret;
7767
7768         ret = get_vpd_params(adapter, &adapter->params.vpd, buf);
7769         if (ret < 0)
7770                 return ret;
7771
7772         /* Cards with real ASICs have the chipid in the PCIe device id */
7773         t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
7774         if (device_id >> 12 == chip_id(adapter))
7775                 adapter->params.cim_la_size = CIMLA_SIZE;
7776         else {
7777                 /* FPGA */
7778                 adapter->params.fpga = 1;
7779                 adapter->params.cim_la_size = 2 * CIMLA_SIZE;
7780         }
7781
7782         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7783
7784         /*
7785          * Default port and clock for debugging in case we can't reach FW.
7786          */
7787         adapter->params.nports = 1;
7788         adapter->params.portvec = 1;
7789         adapter->params.vpd.cclk = 50000;
7790
7791         /* Set pci completion timeout value to 4 seconds. */
7792         set_pcie_completion_timeout(adapter, 0xd);
7793         return 0;
7794 }
7795
7796 /**
7797  *      t4_shutdown_adapter - shut down adapter, host & wire
7798  *      @adapter: the adapter
7799  *
7800  *      Perform an emergency shutdown of the adapter and stop it from
7801  *      continuing any further communication on the ports or DMA to the
7802  *      host.  This is typically used when the adapter and/or firmware
7803  *      have crashed and we want to prevent any further accidental
7804  *      communication with the rest of the world.  This will also force
7805  *      the port Link Status to go down -- if register writes work --
7806  *      which should help our peers figure out that we're down.
7807  */
7808 int t4_shutdown_adapter(struct adapter *adapter)
7809 {
7810         int port;
7811
7812         t4_intr_disable(adapter);
7813         t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
7814         for_each_port(adapter, port) {
7815                 u32 a_port_cfg = PORT_REG(port,
7816                                           is_t4(adapter)
7817                                           ? A_XGMAC_PORT_CFG
7818                                           : A_MAC_PORT_CFG);
7819
7820                 t4_write_reg(adapter, a_port_cfg,
7821                              t4_read_reg(adapter, a_port_cfg)
7822                              & ~V_SIGNAL_DET(1));
7823         }
7824         t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
7825
7826         return 0;
7827 }
7828
7829 /**
7830  *      t4_init_devlog_params - initialize adapter->params.devlog
7831  *      @adap: the adapter
7832  *      @fw_attach: whether we can talk to the firmware
7833  *
7834  *      Initialize various fields of the adapter's Firmware Device Log
7835  *      Parameters structure.
7836  */
7837 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
7838 {
7839         struct devlog_params *dparams = &adap->params.devlog;
7840         u32 pf_dparams;
7841         unsigned int devlog_meminfo;
7842         struct fw_devlog_cmd devlog_cmd;
7843         int ret;
7844
7845         /* If we're dealing with newer firmware, the Device Log Paramerters
7846          * are stored in a designated register which allows us to access the
7847          * Device Log even if we can't talk to the firmware.
7848          */
7849         pf_dparams =
7850                 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
7851         if (pf_dparams) {
7852                 unsigned int nentries, nentries128;
7853
7854                 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
7855                 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
7856
7857                 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
7858                 nentries = (nentries128 + 1) * 128;
7859                 dparams->size = nentries * sizeof(struct fw_devlog_e);
7860
7861                 return 0;
7862         }
7863
7864         /*
7865          * For any failing returns ...
7866          */
7867         memset(dparams, 0, sizeof *dparams);
7868
7869         /*
7870          * If we can't talk to the firmware, there's really nothing we can do
7871          * at this point.
7872          */
7873         if (!fw_attach)
7874                 return -ENXIO;
7875
7876         /* Otherwise, ask the firmware for it's Device Log Parameters.
7877          */
7878         memset(&devlog_cmd, 0, sizeof devlog_cmd);
7879         devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
7880                                              F_FW_CMD_REQUEST | F_FW_CMD_READ);
7881         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7882         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7883                          &devlog_cmd);
7884         if (ret)
7885                 return ret;
7886
7887         devlog_meminfo =
7888                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7889         dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
7890         dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
7891         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7892
7893         return 0;
7894 }
7895
7896 /**
7897  *      t4_init_sge_params - initialize adap->params.sge
7898  *      @adapter: the adapter
7899  *
7900  *      Initialize various fields of the adapter's SGE Parameters structure.
7901  */
7902 int t4_init_sge_params(struct adapter *adapter)
7903 {
7904         u32 r;
7905         struct sge_params *sp = &adapter->params.sge;
7906         unsigned i;
7907
7908         r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
7909         sp->counter_val[0] = G_THRESHOLD_0(r);
7910         sp->counter_val[1] = G_THRESHOLD_1(r);
7911         sp->counter_val[2] = G_THRESHOLD_2(r);
7912         sp->counter_val[3] = G_THRESHOLD_3(r);
7913
7914         r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
7915         sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r));
7916         sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r));
7917         r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
7918         sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r));
7919         sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r));
7920         r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
7921         sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r));
7922         sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r));
7923
7924         r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
7925         sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
7926         if (is_t4(adapter))
7927                 sp->fl_starve_threshold2 = sp->fl_starve_threshold;
7928         else if (is_t5(adapter))
7929                 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
7930         else
7931                 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
7932
7933         /* egress queues: log2 of # of doorbells per BAR2 page */
7934         r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
7935         r >>= S_QUEUESPERPAGEPF0 +
7936             (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
7937         sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
7938
7939         /* ingress queues: log2 of # of doorbells per BAR2 page */
7940         r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
7941         r >>= S_QUEUESPERPAGEPF0 +
7942             (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
7943         sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
7944
7945         r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
7946         r >>= S_HOSTPAGESIZEPF0 +
7947             (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
7948         sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
7949
7950         r = t4_read_reg(adapter, A_SGE_CONTROL);
7951         sp->sge_control = r;
7952         sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
7953         sp->fl_pktshift = G_PKTSHIFT(r);
7954         if (chip_id(adapter) <= CHELSIO_T5) {
7955                 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
7956                     X_INGPADBOUNDARY_SHIFT);
7957         } else {
7958                 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
7959                     X_T6_INGPADBOUNDARY_SHIFT);
7960         }
7961         if (is_t4(adapter))
7962                 sp->pack_boundary = sp->pad_boundary;
7963         else {
7964                 r = t4_read_reg(adapter, A_SGE_CONTROL2);
7965                 if (G_INGPACKBOUNDARY(r) == 0)
7966                         sp->pack_boundary = 16;
7967                 else
7968                         sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
7969         }
7970         for (i = 0; i < SGE_FLBUF_SIZES; i++)
7971                 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
7972                     A_SGE_FL_BUFFER_SIZE0 + (4 * i));
7973
7974         return 0;
7975 }
7976
7977 /*
7978  * Read and cache the adapter's compressed filter mode and ingress config.
7979  */
7980 static void read_filter_mode_and_ingress_config(struct adapter *adap)
7981 {
7982         struct tp_params *tpp = &adap->params.tp;
7983
7984         if (t4_use_ldst(adap)) {
7985                 t4_fw_tp_pio_rw(adap, &tpp->vlan_pri_map, 1,
7986                                 A_TP_VLAN_PRI_MAP, 1);
7987                 t4_fw_tp_pio_rw(adap, &tpp->ingress_config, 1,
7988                                 A_TP_INGRESS_CONFIG, 1);
7989         } else {
7990                 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7991                                  &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
7992                 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7993                                  &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG);
7994         }
7995
7996         /*
7997          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7998          * shift positions of several elements of the Compressed Filter Tuple
7999          * for this adapter which we need frequently ...
8000          */
8001         tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
8002         tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
8003         tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
8004         tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
8005         tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
8006         tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
8007         tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
8008         tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
8009         tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
8010         tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
8011
8012         /*
8013          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8014          * represents the presense of an Outer VLAN instead of a VNIC ID.
8015          */
8016         if ((tpp->ingress_config & F_VNIC) == 0)
8017                 tpp->vnic_shift = -1;
8018 }
8019
8020 /**
8021  *      t4_init_tp_params - initialize adap->params.tp
8022  *      @adap: the adapter
8023  *
8024  *      Initialize various fields of the adapter's TP Parameters structure.
8025  */
8026 int t4_init_tp_params(struct adapter *adap)
8027 {
8028         int chan;
8029         u32 v;
8030         struct tp_params *tpp = &adap->params.tp;
8031
8032         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
8033         tpp->tre = G_TIMERRESOLUTION(v);
8034         tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
8035
8036         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8037         for (chan = 0; chan < MAX_NCHAN; chan++)
8038                 tpp->tx_modq[chan] = chan;
8039
8040         read_filter_mode_and_ingress_config(adap);
8041
8042         /*
8043          * Cache a mask of the bits that represent the error vector portion of
8044          * rx_pkt.err_vec.  T6+ can use a compressed error vector to make room
8045          * for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
8046          */
8047         tpp->err_vec_mask = htobe16(0xffff);
8048         if (chip_id(adap) > CHELSIO_T5) {
8049                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
8050                 if (v & F_CRXPKTENC) {
8051                         tpp->err_vec_mask =
8052                             htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
8053                 }
8054         }
8055
8056         return 0;
8057 }
8058
8059 /**
8060  *      t4_filter_field_shift - calculate filter field shift
8061  *      @adap: the adapter
8062  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8063  *
8064  *      Return the shift position of a filter field within the Compressed
8065  *      Filter Tuple.  The filter field is specified via its selection bit
8066  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8067  */
8068 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8069 {
8070         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8071         unsigned int sel;
8072         int field_shift;
8073
8074         if ((filter_mode & filter_sel) == 0)
8075                 return -1;
8076
8077         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8078                 switch (filter_mode & sel) {
8079                 case F_FCOE:
8080                         field_shift += W_FT_FCOE;
8081                         break;
8082                 case F_PORT:
8083                         field_shift += W_FT_PORT;
8084                         break;
8085                 case F_VNIC_ID:
8086                         field_shift += W_FT_VNIC_ID;
8087                         break;
8088                 case F_VLAN:
8089                         field_shift += W_FT_VLAN;
8090                         break;
8091                 case F_TOS:
8092                         field_shift += W_FT_TOS;
8093                         break;
8094                 case F_PROTOCOL:
8095                         field_shift += W_FT_PROTOCOL;
8096                         break;
8097                 case F_ETHERTYPE:
8098                         field_shift += W_FT_ETHERTYPE;
8099                         break;
8100                 case F_MACMATCH:
8101                         field_shift += W_FT_MACMATCH;
8102                         break;
8103                 case F_MPSHITTYPE:
8104                         field_shift += W_FT_MPSHITTYPE;
8105                         break;
8106                 case F_FRAGMENTATION:
8107                         field_shift += W_FT_FRAGMENTATION;
8108                         break;
8109                 }
8110         }
8111         return field_shift;
8112 }
8113
8114 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
8115 {
8116         u8 addr[6];
8117         int ret, i, j;
8118         struct fw_port_cmd c;
8119         u16 rss_size;
8120         struct port_info *p = adap2pinfo(adap, port_id);
8121         u32 param, val;
8122
8123         memset(&c, 0, sizeof(c));
8124
8125         for (i = 0, j = -1; i <= p->port_id; i++) {
8126                 do {
8127                         j++;
8128                 } while ((adap->params.portvec & (1 << j)) == 0);
8129         }
8130
8131         if (!(adap->flags & IS_VF) ||
8132             adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
8133                 c.op_to_portid = htonl(V_FW_CMD_OP(FW_PORT_CMD) |
8134                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
8135                                        V_FW_PORT_CMD_PORTID(j));
8136                 c.action_to_len16 = htonl(
8137                         V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
8138                         FW_LEN16(c));
8139                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8140                 if (ret)
8141                         return ret;
8142
8143                 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
8144                 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
8145                         G_FW_PORT_CMD_MDIOADDR(ret) : -1;
8146                 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
8147                 p->mod_type = G_FW_PORT_CMD_MODTYPE(ret);
8148
8149                 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
8150                                  be16_to_cpu(c.u.info.acap));
8151         }
8152
8153         ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
8154         if (ret < 0)
8155                 return ret;
8156
8157         p->vi[0].viid = ret;
8158         if (chip_id(adap) <= CHELSIO_T5)
8159                 p->vi[0].smt_idx = (ret & 0x7f) << 1;
8160         else
8161                 p->vi[0].smt_idx = (ret & 0x7f);
8162         p->tx_chan = j;
8163         p->rx_chan_map = t4_get_mps_bg_map(adap, j);
8164         p->lport = j;
8165         p->vi[0].rss_size = rss_size;
8166         t4_os_set_hw_addr(adap, p->port_id, addr);
8167
8168         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8169             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
8170             V_FW_PARAMS_PARAM_YZ(p->vi[0].viid);
8171         ret = t4_query_params(adap, mbox, pf, vf, 1, &param, &val);
8172         if (ret)
8173                 p->vi[0].rss_base = 0xffff;
8174         else {
8175                 /* MPASS((val >> 16) == rss_size); */
8176                 p->vi[0].rss_base = val & 0xffff;
8177         }
8178
8179         return 0;
8180 }
8181
8182 /**
8183  *      t4_read_cimq_cfg - read CIM queue configuration
8184  *      @adap: the adapter
8185  *      @base: holds the queue base addresses in bytes
8186  *      @size: holds the queue sizes in bytes
8187  *      @thres: holds the queue full thresholds in bytes
8188  *
8189  *      Returns the current configuration of the CIM queues, starting with
8190  *      the IBQs, then the OBQs.
8191  */
8192 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8193 {
8194         unsigned int i, v;
8195         int cim_num_obq = adap->chip_params->cim_num_obq;
8196
8197         for (i = 0; i < CIM_NUM_IBQ; i++) {
8198                 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
8199                              V_QUENUMSELECT(i));
8200                 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8201                 /* value is in 256-byte units */
8202                 *base++ = G_CIMQBASE(v) * 256;
8203                 *size++ = G_CIMQSIZE(v) * 256;
8204                 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
8205         }
8206         for (i = 0; i < cim_num_obq; i++) {
8207                 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
8208                              V_QUENUMSELECT(i));
8209                 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8210                 /* value is in 256-byte units */
8211                 *base++ = G_CIMQBASE(v) * 256;
8212                 *size++ = G_CIMQSIZE(v) * 256;
8213         }
8214 }
8215
8216 /**
8217  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
8218  *      @adap: the adapter
8219  *      @qid: the queue index
8220  *      @data: where to store the queue contents
8221  *      @n: capacity of @data in 32-bit words
8222  *
8223  *      Reads the contents of the selected CIM queue starting at address 0 up
8224  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8225  *      error and the number of 32-bit words actually read on success.
8226  */
8227 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8228 {
8229         int i, err, attempts;
8230         unsigned int addr;
8231         const unsigned int nwords = CIM_IBQ_SIZE * 4;
8232
8233         if (qid > 5 || (n & 3))
8234                 return -EINVAL;
8235
8236         addr = qid * nwords;
8237         if (n > nwords)
8238                 n = nwords;
8239
8240         /* It might take 3-10ms before the IBQ debug read access is allowed.
8241          * Wait for 1 Sec with a delay of 1 usec.
8242          */
8243         attempts = 1000000;
8244
8245         for (i = 0; i < n; i++, addr++) {
8246                 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
8247                              F_IBQDBGEN);
8248                 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
8249                                       attempts, 1);
8250                 if (err)
8251                         return err;
8252                 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
8253         }
8254         t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
8255         return i;
8256 }
8257
8258 /**
8259  *      t4_read_cim_obq - read the contents of a CIM outbound queue
8260  *      @adap: the adapter
8261  *      @qid: the queue index
8262  *      @data: where to store the queue contents
8263  *      @n: capacity of @data in 32-bit words
8264  *
8265  *      Reads the contents of the selected CIM queue starting at address 0 up
8266  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8267  *      error and the number of 32-bit words actually read on success.
8268  */
8269 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8270 {
8271         int i, err;
8272         unsigned int addr, v, nwords;
8273         int cim_num_obq = adap->chip_params->cim_num_obq;
8274
8275         if ((qid > (cim_num_obq - 1)) || (n & 3))
8276                 return -EINVAL;
8277
8278         t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
8279                      V_QUENUMSELECT(qid));
8280         v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8281
8282         addr = G_CIMQBASE(v) * 64;    /* muliple of 256 -> muliple of 4 */
8283         nwords = G_CIMQSIZE(v) * 64;  /* same */
8284         if (n > nwords)
8285                 n = nwords;
8286
8287         for (i = 0; i < n; i++, addr++) {
8288                 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
8289                              F_OBQDBGEN);
8290                 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
8291                                       2, 1);
8292                 if (err)
8293                         return err;
8294                 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
8295         }
8296         t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
8297         return i;
8298 }
8299
8300 enum {
8301         CIM_QCTL_BASE     = 0,
8302         CIM_CTL_BASE      = 0x2000,
8303         CIM_PBT_ADDR_BASE = 0x2800,
8304         CIM_PBT_LRF_BASE  = 0x3000,
8305         CIM_PBT_DATA_BASE = 0x3800
8306 };
8307
8308 /**
8309  *      t4_cim_read - read a block from CIM internal address space
8310  *      @adap: the adapter
8311  *      @addr: the start address within the CIM address space
8312  *      @n: number of words to read
8313  *      @valp: where to store the result
8314  *
8315  *      Reads a block of 4-byte words from the CIM intenal address space.
8316  */
8317 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8318                 unsigned int *valp)
8319 {
8320         int ret = 0;
8321
8322         if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8323                 return -EBUSY;
8324
8325         for ( ; !ret && n--; addr += 4) {
8326                 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
8327                 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8328                                       0, 5, 2);
8329                 if (!ret)
8330                         *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
8331         }
8332         return ret;
8333 }
8334
8335 /**
8336  *      t4_cim_write - write a block into CIM internal address space
8337  *      @adap: the adapter
8338  *      @addr: the start address within the CIM address space
8339  *      @n: number of words to write
8340  *      @valp: set of values to write
8341  *
8342  *      Writes a block of 4-byte words into the CIM intenal address space.
8343  */
8344 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8345                  const unsigned int *valp)
8346 {
8347         int ret = 0;
8348
8349         if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8350                 return -EBUSY;
8351
8352         for ( ; !ret && n--; addr += 4) {
8353                 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
8354                 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
8355                 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8356                                       0, 5, 2);
8357         }
8358         return ret;
8359 }
8360
8361 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8362                          unsigned int val)
8363 {
8364         return t4_cim_write(adap, addr, 1, &val);
8365 }
8366
8367 /**
8368  *      t4_cim_ctl_read - read a block from CIM control region
8369  *      @adap: the adapter
8370  *      @addr: the start address within the CIM control region
8371  *      @n: number of words to read
8372  *      @valp: where to store the result
8373  *
8374  *      Reads a block of 4-byte words from the CIM control region.
8375  */
8376 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
8377                     unsigned int *valp)
8378 {
8379         return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
8380 }
8381
8382 /**
8383  *      t4_cim_read_la - read CIM LA capture buffer
8384  *      @adap: the adapter
8385  *      @la_buf: where to store the LA data
8386  *      @wrptr: the HW write pointer within the capture buffer
8387  *
8388  *      Reads the contents of the CIM LA buffer with the most recent entry at
8389  *      the end of the returned data and with the entry at @wrptr first.
8390  *      We try to leave the LA in the running state we find it in.
8391  */
8392 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8393 {
8394         int i, ret;
8395         unsigned int cfg, val, idx;
8396
8397         ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
8398         if (ret)
8399                 return ret;
8400
8401         if (cfg & F_UPDBGLAEN) {        /* LA is running, freeze it */
8402                 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
8403                 if (ret)
8404                         return ret;
8405         }
8406
8407         ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8408         if (ret)
8409                 goto restart;
8410
8411         idx = G_UPDBGLAWRPTR(val);
8412         if (wrptr)
8413                 *wrptr = idx;
8414
8415         for (i = 0; i < adap->params.cim_la_size; i++) {
8416                 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8417                                     V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
8418                 if (ret)
8419                         break;
8420                 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8421                 if (ret)
8422                         break;
8423                 if (val & F_UPDBGLARDEN) {
8424                         ret = -ETIMEDOUT;
8425                         break;
8426                 }
8427                 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
8428                 if (ret)
8429                         break;
8430
8431                 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
8432                 idx = (idx + 1) & M_UPDBGLARDPTR;
8433                 /*
8434                  * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
8435                  * identify the 32-bit portion of the full 312-bit data
8436                  */
8437                 if (is_t6(adap))
8438                         while ((idx & 0xf) > 9)
8439                                 idx = (idx + 1) % M_UPDBGLARDPTR;
8440         }
8441 restart:
8442         if (cfg & F_UPDBGLAEN) {
8443                 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8444                                       cfg & ~F_UPDBGLARDEN);
8445                 if (!ret)
8446                         ret = r;
8447         }
8448         return ret;
8449 }
8450
8451 /**
8452  *      t4_tp_read_la - read TP LA capture buffer
8453  *      @adap: the adapter
8454  *      @la_buf: where to store the LA data
8455  *      @wrptr: the HW write pointer within the capture buffer
8456  *
8457  *      Reads the contents of the TP LA buffer with the most recent entry at
8458  *      the end of the returned data and with the entry at @wrptr first.
8459  *      We leave the LA in the running state we find it in.
8460  */
8461 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8462 {
8463         bool last_incomplete;
8464         unsigned int i, cfg, val, idx;
8465
8466         cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
8467         if (cfg & F_DBGLAENABLE)                        /* freeze LA */
8468                 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8469                              adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
8470
8471         val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
8472         idx = G_DBGLAWPTR(val);
8473         last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
8474         if (last_incomplete)
8475                 idx = (idx + 1) & M_DBGLARPTR;
8476         if (wrptr)
8477                 *wrptr = idx;
8478
8479         val &= 0xffff;
8480         val &= ~V_DBGLARPTR(M_DBGLARPTR);
8481         val |= adap->params.tp.la_mask;
8482
8483         for (i = 0; i < TPLA_SIZE; i++) {
8484                 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
8485                 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
8486                 idx = (idx + 1) & M_DBGLARPTR;
8487         }
8488
8489         /* Wipe out last entry if it isn't valid */
8490         if (last_incomplete)
8491                 la_buf[TPLA_SIZE - 1] = ~0ULL;
8492
8493         if (cfg & F_DBGLAENABLE)                /* restore running state */
8494                 t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8495                              cfg | adap->params.tp.la_mask);
8496 }
8497
8498 /*
8499  * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8500  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
8501  * state for more than the Warning Threshold then we'll issue a warning about
8502  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
8503  * appears to be hung every Warning Repeat second till the situation clears.
8504  * If the situation clears, we'll note that as well.
8505  */
8506 #define SGE_IDMA_WARN_THRESH 1
8507 #define SGE_IDMA_WARN_REPEAT 300
8508
8509 /**
8510  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8511  *      @adapter: the adapter
8512  *      @idma: the adapter IDMA Monitor state
8513  *
8514  *      Initialize the state of an SGE Ingress DMA Monitor.
8515  */
8516 void t4_idma_monitor_init(struct adapter *adapter,
8517                           struct sge_idma_monitor_state *idma)
8518 {
8519         /* Initialize the state variables for detecting an SGE Ingress DMA
8520          * hang.  The SGE has internal counters which count up on each clock
8521          * tick whenever the SGE finds its Ingress DMA State Engines in the
8522          * same state they were on the previous clock tick.  The clock used is
8523          * the Core Clock so we have a limit on the maximum "time" they can
8524          * record; typically a very small number of seconds.  For instance,
8525          * with a 600MHz Core Clock, we can only count up to a bit more than
8526          * 7s.  So we'll synthesize a larger counter in order to not run the
8527          * risk of having the "timers" overflow and give us the flexibility to
8528          * maintain a Hung SGE State Machine of our own which operates across
8529          * a longer time frame.
8530          */
8531         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8532         idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
8533 }
8534
8535 /**
8536  *      t4_idma_monitor - monitor SGE Ingress DMA state
8537  *      @adapter: the adapter
8538  *      @idma: the adapter IDMA Monitor state
8539  *      @hz: number of ticks/second
8540  *      @ticks: number of ticks since the last IDMA Monitor call
8541  */
8542 void t4_idma_monitor(struct adapter *adapter,
8543                      struct sge_idma_monitor_state *idma,
8544                      int hz, int ticks)
8545 {
8546         int i, idma_same_state_cnt[2];
8547
8548          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
8549           * are counters inside the SGE which count up on each clock when the
8550           * SGE finds its Ingress DMA State Engines in the same states they
8551           * were in the previous clock.  The counters will peg out at
8552           * 0xffffffff without wrapping around so once they pass the 1s
8553           * threshold they'll stay above that till the IDMA state changes.
8554           */
8555         t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
8556         idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
8557         idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8558
8559         for (i = 0; i < 2; i++) {
8560                 u32 debug0, debug11;
8561
8562                 /* If the Ingress DMA Same State Counter ("timer") is less
8563                  * than 1s, then we can reset our synthesized Stall Timer and
8564                  * continue.  If we have previously emitted warnings about a
8565                  * potential stalled Ingress Queue, issue a note indicating
8566                  * that the Ingress Queue has resumed forward progress.
8567                  */
8568                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8569                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
8570                                 CH_WARN(adapter, "SGE idma%d, queue %u, "
8571                                         "resumed after %d seconds\n",
8572                                         i, idma->idma_qid[i],
8573                                         idma->idma_stalled[i]/hz);
8574                         idma->idma_stalled[i] = 0;
8575                         continue;
8576                 }
8577
8578                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8579                  * domain.  The first time we get here it'll be because we
8580                  * passed the 1s Threshold; each additional time it'll be
8581                  * because the RX Timer Callback is being fired on its regular
8582                  * schedule.
8583                  *
8584                  * If the stall is below our Potential Hung Ingress Queue
8585                  * Warning Threshold, continue.
8586                  */
8587                 if (idma->idma_stalled[i] == 0) {
8588                         idma->idma_stalled[i] = hz;
8589                         idma->idma_warn[i] = 0;
8590                 } else {
8591                         idma->idma_stalled[i] += ticks;
8592                         idma->idma_warn[i] -= ticks;
8593                 }
8594
8595                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
8596                         continue;
8597
8598                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8599                  */
8600                 if (idma->idma_warn[i] > 0)
8601                         continue;
8602                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
8603
8604                 /* Read and save the SGE IDMA State and Queue ID information.
8605                  * We do this every time in case it changes across time ...
8606                  * can't be too careful ...
8607                  */
8608                 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
8609                 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8610                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8611
8612                 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
8613                 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8614                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8615
8616                 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
8617                         " state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8618                         i, idma->idma_qid[i], idma->idma_state[i],
8619                         idma->idma_stalled[i]/hz,
8620                         debug0, debug11);
8621                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8622         }
8623 }
8624
8625 /**
8626  *      t4_read_pace_tbl - read the pace table
8627  *      @adap: the adapter
8628  *      @pace_vals: holds the returned values
8629  *
8630  *      Returns the values of TP's pace table in microseconds.
8631  */
8632 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
8633 {
8634         unsigned int i, v;
8635
8636         for (i = 0; i < NTX_SCHED; i++) {
8637                 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
8638                 v = t4_read_reg(adap, A_TP_PACE_TABLE);
8639                 pace_vals[i] = dack_ticks_to_usec(adap, v);
8640         }
8641 }
8642
8643 /**
8644  *      t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
8645  *      @adap: the adapter
8646  *      @sched: the scheduler index
8647  *      @kbps: the byte rate in Kbps
8648  *      @ipg: the interpacket delay in tenths of nanoseconds
8649  *
8650  *      Return the current configuration of a HW Tx scheduler.
8651  */
8652 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
8653                      unsigned int *ipg)
8654 {
8655         unsigned int v, addr, bpt, cpt;
8656
8657         if (kbps) {
8658                 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
8659                 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8660                 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8661                 if (sched & 1)
8662                         v >>= 16;
8663                 bpt = (v >> 8) & 0xff;
8664                 cpt = v & 0xff;
8665                 if (!cpt)
8666                         *kbps = 0;      /* scheduler disabled */
8667                 else {
8668                         v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
8669                         *kbps = (v * bpt) / 125;
8670                 }
8671         }
8672         if (ipg) {
8673                 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
8674                 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8675                 v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8676                 if (sched & 1)
8677                         v >>= 16;
8678                 v &= 0xffff;
8679                 *ipg = (10000 * v) / core_ticks_per_usec(adap);
8680         }
8681 }
8682
8683 /**
8684  *      t4_load_cfg - download config file
8685  *      @adap: the adapter
8686  *      @cfg_data: the cfg text file to write
8687  *      @size: text file size
8688  *
8689  *      Write the supplied config text file to the card's serial flash.
8690  */
8691 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
8692 {
8693         int ret, i, n, cfg_addr;
8694         unsigned int addr;
8695         unsigned int flash_cfg_start_sec;
8696         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8697
8698         cfg_addr = t4_flash_cfg_addr(adap);
8699         if (cfg_addr < 0)
8700                 return cfg_addr;
8701
8702         addr = cfg_addr;
8703         flash_cfg_start_sec = addr / SF_SEC_SIZE;
8704
8705         if (size > FLASH_CFG_MAX_SIZE) {
8706                 CH_ERR(adap, "cfg file too large, max is %u bytes\n",
8707                        FLASH_CFG_MAX_SIZE);
8708                 return -EFBIG;
8709         }
8710
8711         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
8712                          sf_sec_size);
8713         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
8714                                      flash_cfg_start_sec + i - 1);
8715         /*
8716          * If size == 0 then we're simply erasing the FLASH sectors associated
8717          * with the on-adapter Firmware Configuration File.
8718          */
8719         if (ret || size == 0)
8720                 goto out;
8721
8722         /* this will write to the flash up to SF_PAGE_SIZE at a time */
8723         for (i = 0; i< size; i+= SF_PAGE_SIZE) {
8724                 if ( (size - i) <  SF_PAGE_SIZE)
8725                         n = size - i;
8726                 else
8727                         n = SF_PAGE_SIZE;
8728                 ret = t4_write_flash(adap, addr, n, cfg_data, 1);
8729                 if (ret)
8730                         goto out;
8731
8732                 addr += SF_PAGE_SIZE;
8733                 cfg_data += SF_PAGE_SIZE;
8734         }
8735
8736 out:
8737         if (ret)
8738                 CH_ERR(adap, "config file %s failed %d\n",
8739                        (size == 0 ? "clear" : "download"), ret);
8740         return ret;
8741 }
8742
8743 /**
8744  *      t5_fw_init_extern_mem - initialize the external memory
8745  *      @adap: the adapter
8746  *
8747  *      Initializes the external memory on T5.
8748  */
8749 int t5_fw_init_extern_mem(struct adapter *adap)
8750 {
8751         u32 params[1], val[1];
8752         int ret;
8753
8754         if (!is_t5(adap))
8755                 return 0;
8756
8757         val[0] = 0xff; /* Initialize all MCs */
8758         params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8759                         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
8760         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
8761                         FW_CMD_MAX_TIMEOUT);
8762
8763         return ret;
8764 }
8765
8766 /* BIOS boot headers */
8767 typedef struct pci_expansion_rom_header {
8768         u8      signature[2]; /* ROM Signature. Should be 0xaa55 */
8769         u8      reserved[22]; /* Reserved per processor Architecture data */
8770         u8      pcir_offset[2]; /* Offset to PCI Data Structure */
8771 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
8772
8773 /* Legacy PCI Expansion ROM Header */
8774 typedef struct legacy_pci_expansion_rom_header {
8775         u8      signature[2]; /* ROM Signature. Should be 0xaa55 */
8776         u8      size512; /* Current Image Size in units of 512 bytes */
8777         u8      initentry_point[4];
8778         u8      cksum; /* Checksum computed on the entire Image */
8779         u8      reserved[16]; /* Reserved */
8780         u8      pcir_offset[2]; /* Offset to PCI Data Struture */
8781 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
8782
8783 /* EFI PCI Expansion ROM Header */
8784 typedef struct efi_pci_expansion_rom_header {
8785         u8      signature[2]; // ROM signature. The value 0xaa55
8786         u8      initialization_size[2]; /* Units 512. Includes this header */
8787         u8      efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
8788         u8      efi_subsystem[2]; /* Subsystem value for EFI image header */
8789         u8      efi_machine_type[2]; /* Machine type from EFI image header */
8790         u8      compression_type[2]; /* Compression type. */
8791                 /*
8792                  * Compression type definition
8793                  * 0x0: uncompressed
8794                  * 0x1: Compressed
8795                  * 0x2-0xFFFF: Reserved
8796                  */
8797         u8      reserved[8]; /* Reserved */
8798         u8      efi_image_header_offset[2]; /* Offset to EFI Image */
8799         u8      pcir_offset[2]; /* Offset to PCI Data Structure */
8800 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
8801
8802 /* PCI Data Structure Format */
8803 typedef struct pcir_data_structure { /* PCI Data Structure */
8804         u8      signature[4]; /* Signature. The string "PCIR" */
8805         u8      vendor_id[2]; /* Vendor Identification */
8806         u8      device_id[2]; /* Device Identification */
8807         u8      vital_product[2]; /* Pointer to Vital Product Data */
8808         u8      length[2]; /* PCIR Data Structure Length */
8809         u8      revision; /* PCIR Data Structure Revision */
8810         u8      class_code[3]; /* Class Code */
8811         u8      image_length[2]; /* Image Length. Multiple of 512B */
8812         u8      code_revision[2]; /* Revision Level of Code/Data */
8813         u8      code_type; /* Code Type. */
8814                 /*
8815                  * PCI Expansion ROM Code Types
8816                  * 0x00: Intel IA-32, PC-AT compatible. Legacy
8817                  * 0x01: Open Firmware standard for PCI. FCODE
8818                  * 0x02: Hewlett-Packard PA RISC. HP reserved
8819                  * 0x03: EFI Image. EFI
8820                  * 0x04-0xFF: Reserved.
8821                  */
8822         u8      indicator; /* Indicator. Identifies the last image in the ROM */
8823         u8      reserved[2]; /* Reserved */
8824 } pcir_data_t; /* PCI__DATA_STRUCTURE */
8825
8826 /* BOOT constants */
8827 enum {
8828         BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
8829         BOOT_SIGNATURE = 0xaa55,   /* signature of BIOS boot ROM */
8830         BOOT_SIZE_INC = 512,       /* image size measured in 512B chunks */
8831         BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
8832         BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment  */
8833         VENDOR_ID = 0x1425, /* Vendor ID */
8834         PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
8835 };
8836
8837 /*
8838  *      modify_device_id - Modifies the device ID of the Boot BIOS image
8839  *      @adatper: the device ID to write.
8840  *      @boot_data: the boot image to modify.
8841  *
8842  *      Write the supplied device ID to the boot BIOS image.
8843  */
8844 static void modify_device_id(int device_id, u8 *boot_data)
8845 {
8846         legacy_pci_exp_rom_header_t *header;
8847         pcir_data_t *pcir_header;
8848         u32 cur_header = 0;
8849
8850         /*
8851          * Loop through all chained images and change the device ID's
8852          */
8853         while (1) {
8854                 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
8855                 pcir_header = (pcir_data_t *) &boot_data[cur_header +
8856                               le16_to_cpu(*(u16*)header->pcir_offset)];
8857
8858                 /*
8859                  * Only modify the Device ID if code type is Legacy or HP.
8860                  * 0x00: Okay to modify
8861                  * 0x01: FCODE. Do not be modify
8862                  * 0x03: Okay to modify
8863                  * 0x04-0xFF: Do not modify
8864                  */
8865                 if (pcir_header->code_type == 0x00) {
8866                         u8 csum = 0;
8867                         int i;
8868
8869                         /*
8870                          * Modify Device ID to match current adatper
8871                          */
8872                         *(u16*) pcir_header->device_id = device_id;
8873
8874                         /*
8875                          * Set checksum temporarily to 0.
8876                          * We will recalculate it later.
8877                          */
8878                         header->cksum = 0x0;
8879
8880                         /*
8881                          * Calculate and update checksum
8882                          */
8883                         for (i = 0; i < (header->size512 * 512); i++)
8884                                 csum += (u8)boot_data[cur_header + i];
8885
8886                         /*
8887                          * Invert summed value to create the checksum
8888                          * Writing new checksum value directly to the boot data
8889                          */
8890                         boot_data[cur_header + 7] = -csum;
8891
8892                 } else if (pcir_header->code_type == 0x03) {
8893
8894                         /*
8895                          * Modify Device ID to match current adatper
8896                          */
8897                         *(u16*) pcir_header->device_id = device_id;
8898
8899                 }
8900
8901
8902                 /*
8903                  * Check indicator element to identify if this is the last
8904                  * image in the ROM.
8905                  */
8906                 if (pcir_header->indicator & 0x80)
8907                         break;
8908
8909                 /*
8910                  * Move header pointer up to the next image in the ROM.
8911                  */
8912                 cur_header += header->size512 * 512;
8913         }
8914 }
8915
8916 /*
8917  *      t4_load_boot - download boot flash
8918  *      @adapter: the adapter
8919  *      @boot_data: the boot image to write
8920  *      @boot_addr: offset in flash to write boot_data
8921  *      @size: image size
8922  *
8923  *      Write the supplied boot image to the card's serial flash.
8924  *      The boot image has the following sections: a 28-byte header and the
8925  *      boot image.
8926  */
8927 int t4_load_boot(struct adapter *adap, u8 *boot_data,
8928                  unsigned int boot_addr, unsigned int size)
8929 {
8930         pci_exp_rom_header_t *header;
8931         int pcir_offset ;
8932         pcir_data_t *pcir_header;
8933         int ret, addr;
8934         uint16_t device_id;
8935         unsigned int i;
8936         unsigned int boot_sector = (boot_addr * 1024 );
8937         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8938
8939         /*
8940          * Make sure the boot image does not encroach on the firmware region
8941          */
8942         if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
8943                 CH_ERR(adap, "boot image encroaching on firmware region\n");
8944                 return -EFBIG;
8945         }
8946
8947         /*
8948          * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
8949          * and Boot configuration data sections. These 3 boot sections span
8950          * sectors 0 to 7 in flash and live right before the FW image location.
8951          */
8952         i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
8953                         sf_sec_size);
8954         ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
8955                                      (boot_sector >> 16) + i - 1);
8956
8957         /*
8958          * If size == 0 then we're simply erasing the FLASH sectors associated
8959          * with the on-adapter option ROM file
8960          */
8961         if (ret || (size == 0))
8962                 goto out;
8963
8964         /* Get boot header */
8965         header = (pci_exp_rom_header_t *)boot_data;
8966         pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
8967         /* PCIR Data Structure */
8968         pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
8969
8970         /*
8971          * Perform some primitive sanity testing to avoid accidentally
8972          * writing garbage over the boot sectors.  We ought to check for
8973          * more but it's not worth it for now ...
8974          */
8975         if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
8976                 CH_ERR(adap, "boot image too small/large\n");
8977                 return -EFBIG;
8978         }
8979
8980 #ifndef CHELSIO_T4_DIAGS
8981         /*
8982          * Check BOOT ROM header signature
8983          */
8984         if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
8985                 CH_ERR(adap, "Boot image missing signature\n");
8986                 return -EINVAL;
8987         }
8988
8989         /*
8990          * Check PCI header signature
8991          */
8992         if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
8993                 CH_ERR(adap, "PCI header missing signature\n");
8994                 return -EINVAL;
8995         }
8996
8997         /*
8998          * Check Vendor ID matches Chelsio ID
8999          */
9000         if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
9001                 CH_ERR(adap, "Vendor ID missing signature\n");
9002                 return -EINVAL;
9003         }
9004 #endif
9005
9006         /*
9007          * Retrieve adapter's device ID
9008          */
9009         t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
9010         /* Want to deal with PF 0 so I strip off PF 4 indicator */
9011         device_id = device_id & 0xf0ff;
9012
9013         /*
9014          * Check PCIE Device ID
9015          */
9016         if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
9017                 /*
9018                  * Change the device ID in the Boot BIOS image to match
9019                  * the Device ID of the current adapter.
9020                  */
9021                 modify_device_id(device_id, boot_data);
9022         }
9023
9024         /*
9025          * Skip over the first SF_PAGE_SIZE worth of data and write it after
9026          * we finish copying the rest of the boot image. This will ensure
9027          * that the BIOS boot header will only be written if the boot image
9028          * was written in full.
9029          */
9030         addr = boot_sector;
9031         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
9032                 addr += SF_PAGE_SIZE;
9033                 boot_data += SF_PAGE_SIZE;
9034                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
9035                 if (ret)
9036                         goto out;
9037         }
9038
9039         ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
9040                              (const u8 *)header, 0);
9041
9042 out:
9043         if (ret)
9044                 CH_ERR(adap, "boot image download failed, error %d\n", ret);
9045         return ret;
9046 }
9047
9048 /*
9049  *      t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
9050  *      @adapter: the adapter
9051  *
9052  *      Return the address within the flash where the OptionROM Configuration
9053  *      is stored, or an error if the device FLASH is too small to contain
9054  *      a OptionROM Configuration.
9055  */
9056 static int t4_flash_bootcfg_addr(struct adapter *adapter)
9057 {
9058         /*
9059          * If the device FLASH isn't large enough to hold a Firmware
9060          * Configuration File, return an error.
9061          */
9062         if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
9063                 return -ENOSPC;
9064
9065         return FLASH_BOOTCFG_START;
9066 }
9067
9068 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
9069 {
9070         int ret, i, n, cfg_addr;
9071         unsigned int addr;
9072         unsigned int flash_cfg_start_sec;
9073         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9074
9075         cfg_addr = t4_flash_bootcfg_addr(adap);
9076         if (cfg_addr < 0)
9077                 return cfg_addr;
9078
9079         addr = cfg_addr;
9080         flash_cfg_start_sec = addr / SF_SEC_SIZE;
9081
9082         if (size > FLASH_BOOTCFG_MAX_SIZE) {
9083                 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
9084                         FLASH_BOOTCFG_MAX_SIZE);
9085                 return -EFBIG;
9086         }
9087
9088         i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
9089                          sf_sec_size);
9090         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9091                                         flash_cfg_start_sec + i - 1);
9092
9093         /*
9094          * If size == 0 then we're simply erasing the FLASH sectors associated
9095          * with the on-adapter OptionROM Configuration File.
9096          */
9097         if (ret || size == 0)
9098                 goto out;
9099
9100         /* this will write to the flash up to SF_PAGE_SIZE at a time */
9101         for (i = 0; i< size; i+= SF_PAGE_SIZE) {
9102                 if ( (size - i) <  SF_PAGE_SIZE)
9103                         n = size - i;
9104                 else
9105                         n = SF_PAGE_SIZE;
9106                 ret = t4_write_flash(adap, addr, n, cfg_data, 0);
9107                 if (ret)
9108                         goto out;
9109
9110                 addr += SF_PAGE_SIZE;
9111                 cfg_data += SF_PAGE_SIZE;
9112         }
9113
9114 out:
9115         if (ret)
9116                 CH_ERR(adap, "boot config data %s failed %d\n",
9117                                 (size == 0 ? "clear" : "download"), ret);
9118         return ret;
9119 }
9120
9121 /**
9122  *      t4_set_filter_mode - configure the optional components of filter tuples
9123  *      @adap: the adapter
9124  *      @mode_map: a bitmap selcting which optional filter components to enable
9125  *
9126  *      Sets the filter mode by selecting the optional components to enable
9127  *      in filter tuples.  Returns 0 on success and a negative error if the
9128  *      requested mode needs more bits than are available for optional
9129  *      components.
9130  */
9131 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map)
9132 {
9133         static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
9134
9135         int i, nbits = 0;
9136
9137         for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
9138                 if (mode_map & (1 << i))
9139                         nbits += width[i];
9140         if (nbits > FILTER_OPT_LEN)
9141                 return -EINVAL;
9142         if (t4_use_ldst(adap))
9143                 t4_fw_tp_pio_rw(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, 0);
9144         else
9145                 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, &mode_map,
9146                                   1, A_TP_VLAN_PRI_MAP);
9147         read_filter_mode_and_ingress_config(adap);
9148
9149         return 0;
9150 }
9151
9152 /**
9153  *      t4_clr_port_stats - clear port statistics
9154  *      @adap: the adapter
9155  *      @idx: the port index
9156  *
9157  *      Clear HW statistics for the given port.
9158  */
9159 void t4_clr_port_stats(struct adapter *adap, int idx)
9160 {
9161         unsigned int i;
9162         u32 bgmap = t4_get_mps_bg_map(adap, idx);
9163         u32 port_base_addr;
9164
9165         if (is_t4(adap))
9166                 port_base_addr = PORT_BASE(idx);
9167         else
9168                 port_base_addr = T5_PORT_BASE(idx);
9169
9170         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
9171                         i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
9172                 t4_write_reg(adap, port_base_addr + i, 0);
9173         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
9174                         i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
9175                 t4_write_reg(adap, port_base_addr + i, 0);
9176         for (i = 0; i < 4; i++)
9177                 if (bgmap & (1 << i)) {
9178                         t4_write_reg(adap,
9179                         A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
9180                         t4_write_reg(adap,
9181                         A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
9182                 }
9183 }
9184
9185 /**
9186  *      t4_i2c_rd - read I2C data from adapter
9187  *      @adap: the adapter
9188  *      @port: Port number if per-port device; <0 if not
9189  *      @devid: per-port device ID or absolute device ID
9190  *      @offset: byte offset into device I2C space
9191  *      @len: byte length of I2C space data
9192  *      @buf: buffer in which to return I2C data
9193  *
9194  *      Reads the I2C data from the indicated device and location.
9195  */
9196 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
9197               int port, unsigned int devid,
9198               unsigned int offset, unsigned int len,
9199               u8 *buf)
9200 {
9201         u32 ldst_addrspace;
9202         struct fw_ldst_cmd ldst;
9203         int ret;
9204
9205         if (port >= 4 ||
9206             devid >= 256 ||
9207             offset >= 256 ||
9208             len > sizeof ldst.u.i2c.data)
9209                 return -EINVAL;
9210
9211         memset(&ldst, 0, sizeof ldst);
9212         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
9213         ldst.op_to_addrspace =
9214                 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9215                             F_FW_CMD_REQUEST |
9216                             F_FW_CMD_READ |
9217                             ldst_addrspace);
9218         ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
9219         ldst.u.i2c.pid = (port < 0 ? 0xff : port);
9220         ldst.u.i2c.did = devid;
9221         ldst.u.i2c.boffset = offset;
9222         ldst.u.i2c.blen = len;
9223         ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
9224         if (!ret)
9225                 memcpy(buf, ldst.u.i2c.data, len);
9226         return ret;
9227 }
9228
9229 /**
9230  *      t4_i2c_wr - write I2C data to adapter
9231  *      @adap: the adapter
9232  *      @port: Port number if per-port device; <0 if not
9233  *      @devid: per-port device ID or absolute device ID
9234  *      @offset: byte offset into device I2C space
9235  *      @len: byte length of I2C space data
9236  *      @buf: buffer containing new I2C data
9237  *
9238  *      Write the I2C data to the indicated device and location.
9239  */
9240 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
9241               int port, unsigned int devid,
9242               unsigned int offset, unsigned int len,
9243               u8 *buf)
9244 {
9245         u32 ldst_addrspace;
9246         struct fw_ldst_cmd ldst;
9247
9248         if (port >= 4 ||
9249             devid >= 256 ||
9250             offset >= 256 ||
9251             len > sizeof ldst.u.i2c.data)
9252                 return -EINVAL;
9253
9254         memset(&ldst, 0, sizeof ldst);
9255         ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
9256         ldst.op_to_addrspace =
9257                 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9258                             F_FW_CMD_REQUEST |
9259                             F_FW_CMD_WRITE |
9260                             ldst_addrspace);
9261         ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
9262         ldst.u.i2c.pid = (port < 0 ? 0xff : port);
9263         ldst.u.i2c.did = devid;
9264         ldst.u.i2c.boffset = offset;
9265         ldst.u.i2c.blen = len;
9266         memcpy(ldst.u.i2c.data, buf, len);
9267         return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
9268 }
9269
9270 /**
9271  *      t4_sge_ctxt_rd - read an SGE context through FW
9272  *      @adap: the adapter
9273  *      @mbox: mailbox to use for the FW command
9274  *      @cid: the context id
9275  *      @ctype: the context type
9276  *      @data: where to store the context data
9277  *
9278  *      Issues a FW command through the given mailbox to read an SGE context.
9279  */
9280 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9281                    enum ctxt_type ctype, u32 *data)
9282 {
9283         int ret;
9284         struct fw_ldst_cmd c;
9285
9286         if (ctype == CTXT_EGRESS)
9287                 ret = FW_LDST_ADDRSPC_SGE_EGRC;
9288         else if (ctype == CTXT_INGRESS)
9289                 ret = FW_LDST_ADDRSPC_SGE_INGC;
9290         else if (ctype == CTXT_FLM)
9291                 ret = FW_LDST_ADDRSPC_SGE_FLMC;
9292         else
9293                 ret = FW_LDST_ADDRSPC_SGE_CONMC;
9294
9295         memset(&c, 0, sizeof(c));
9296         c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9297                                         F_FW_CMD_REQUEST | F_FW_CMD_READ |
9298                                         V_FW_LDST_CMD_ADDRSPACE(ret));
9299         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9300         c.u.idctxt.physid = cpu_to_be32(cid);
9301
9302         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9303         if (ret == 0) {
9304                 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9305                 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9306                 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9307                 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9308                 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9309                 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9310         }
9311         return ret;
9312 }
9313
9314 /**
9315  *      t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9316  *      @adap: the adapter
9317  *      @cid: the context id
9318  *      @ctype: the context type
9319  *      @data: where to store the context data
9320  *
9321  *      Reads an SGE context directly, bypassing FW.  This is only for
9322  *      debugging when FW is unavailable.
9323  */
9324 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
9325                       u32 *data)
9326 {
9327         int i, ret;
9328
9329         t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
9330         ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
9331         if (!ret)
9332                 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
9333                         *data++ = t4_read_reg(adap, i);
9334         return ret;
9335 }
9336
9337 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
9338                     int sleep_ok)
9339 {
9340         struct fw_sched_cmd cmd;
9341
9342         memset(&cmd, 0, sizeof(cmd));
9343         cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9344                                       F_FW_CMD_REQUEST |
9345                                       F_FW_CMD_WRITE);
9346         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9347
9348         cmd.u.config.sc = FW_SCHED_SC_CONFIG;
9349         cmd.u.config.type = type;
9350         cmd.u.config.minmaxen = minmaxen;
9351
9352         return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9353                                NULL, sleep_ok);
9354 }
9355
9356 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9357                     int rateunit, int ratemode, int channel, int cl,
9358                     int minrate, int maxrate, int weight, int pktsize,
9359                     int sleep_ok)
9360 {
9361         struct fw_sched_cmd cmd;
9362
9363         memset(&cmd, 0, sizeof(cmd));
9364         cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9365                                       F_FW_CMD_REQUEST |
9366                                       F_FW_CMD_WRITE);
9367         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9368
9369         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9370         cmd.u.params.type = type;
9371         cmd.u.params.level = level;
9372         cmd.u.params.mode = mode;
9373         cmd.u.params.ch = channel;
9374         cmd.u.params.cl = cl;
9375         cmd.u.params.unit = rateunit;
9376         cmd.u.params.rate = ratemode;
9377         cmd.u.params.min = cpu_to_be32(minrate);
9378         cmd.u.params.max = cpu_to_be32(maxrate);
9379         cmd.u.params.weight = cpu_to_be16(weight);
9380         cmd.u.params.pktsize = cpu_to_be16(pktsize);
9381
9382         return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9383                                NULL, sleep_ok);
9384 }
9385
9386 /*
9387  *      t4_config_watchdog - configure (enable/disable) a watchdog timer
9388  *      @adapter: the adapter
9389  *      @mbox: mailbox to use for the FW command
9390  *      @pf: the PF owning the queue
9391  *      @vf: the VF owning the queue
9392  *      @timeout: watchdog timeout in ms
9393  *      @action: watchdog timer / action
9394  *
9395  *      There are separate watchdog timers for each possible watchdog
9396  *      action.  Configure one of the watchdog timers by setting a non-zero
9397  *      timeout.  Disable a watchdog timer by using a timeout of zero.
9398  */
9399 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
9400                        unsigned int pf, unsigned int vf,
9401                        unsigned int timeout, unsigned int action)
9402 {
9403         struct fw_watchdog_cmd wdog;
9404         unsigned int ticks;
9405
9406         /*
9407          * The watchdog command expects a timeout in units of 10ms so we need
9408          * to convert it here (via rounding) and force a minimum of one 10ms
9409          * "tick" if the timeout is non-zero but the convertion results in 0
9410          * ticks.
9411          */
9412         ticks = (timeout + 5)/10;
9413         if (timeout && !ticks)
9414                 ticks = 1;
9415
9416         memset(&wdog, 0, sizeof wdog);
9417         wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
9418                                      F_FW_CMD_REQUEST |
9419                                      F_FW_CMD_WRITE |
9420                                      V_FW_PARAMS_CMD_PFN(pf) |
9421                                      V_FW_PARAMS_CMD_VFN(vf));
9422         wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
9423         wdog.timeout = cpu_to_be32(ticks);
9424         wdog.action = cpu_to_be32(action);
9425
9426         return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
9427 }
9428
9429 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
9430 {
9431         struct fw_devlog_cmd devlog_cmd;
9432         int ret;
9433
9434         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9435         devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9436                                              F_FW_CMD_REQUEST | F_FW_CMD_READ);
9437         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9438         ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9439                          sizeof(devlog_cmd), &devlog_cmd);
9440         if (ret)
9441                 return ret;
9442
9443         *level = devlog_cmd.level;
9444         return 0;
9445 }
9446
9447 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
9448 {
9449         struct fw_devlog_cmd devlog_cmd;
9450
9451         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9452         devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9453                                              F_FW_CMD_REQUEST |
9454                                              F_FW_CMD_WRITE);
9455         devlog_cmd.level = level;
9456         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9457         return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9458                           sizeof(devlog_cmd), &devlog_cmd);
9459 }