2 * Copyright (c) 2011, 2016 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 CPL_PASS_OPEN_REQ = 0x1,
35 CPL_PASS_ACCEPT_RPL = 0x2,
36 CPL_ACT_OPEN_REQ = 0x3,
38 CPL_SET_TCB_FIELD = 0x5,
40 CPL_CLOSE_CON_REQ = 0x8,
41 CPL_CLOSE_LISTSRV_REQ = 0x9,
45 CPL_RX_DATA_ACK = 0xD,
47 CPL_RTE_DELETE_REQ = 0xF,
48 CPL_RTE_WRITE_REQ = 0x10,
49 CPL_RTE_READ_REQ = 0x11,
50 CPL_L2T_WRITE_REQ = 0x12,
51 CPL_L2T_READ_REQ = 0x13,
52 CPL_SMT_WRITE_REQ = 0x14,
53 CPL_SMT_READ_REQ = 0x15,
54 CPL_TAG_WRITE_REQ = 0x16,
56 CPL_TID_RELEASE = 0x1A,
57 CPL_TAG_READ_REQ = 0x1B,
58 CPL_SRQ_TABLE_REQ = 0x1C,
59 CPL_TX_PKT_FSO = 0x1E,
60 CPL_TX_DATA_ISO = 0x1F,
62 CPL_CLOSE_LISTSRV_RPL = 0x20,
64 CPL_GET_TCB_RPL = 0x22,
65 CPL_L2T_WRITE_RPL = 0x23,
66 CPL_PASS_OPEN_RPL = 0x24,
67 CPL_ACT_OPEN_RPL = 0x25,
68 CPL_PEER_CLOSE = 0x26,
69 CPL_RTE_DELETE_RPL = 0x27,
70 CPL_RTE_WRITE_RPL = 0x28,
71 CPL_RX_URG_PKT = 0x29,
72 CPL_TAG_WRITE_RPL = 0x2A,
73 CPL_ABORT_REQ_RSS = 0x2B,
74 CPL_RX_URG_NOTIFY = 0x2C,
75 CPL_ABORT_RPL_RSS = 0x2D,
76 CPL_SMT_WRITE_RPL = 0x2E,
77 CPL_TX_DATA_ACK = 0x2F,
79 CPL_RX_PHYS_ADDR = 0x30,
80 CPL_PCMD_READ_RPL = 0x31,
81 CPL_CLOSE_CON_RPL = 0x32,
83 CPL_L2T_READ_RPL = 0x34,
85 CPL_RDMA_CQE_READ_RSP = 0x36,
86 CPL_RDMA_CQE_ERR = 0x37,
87 CPL_RTE_READ_RPL = 0x38,
89 CPL_SET_TCB_RPL = 0x3A,
91 CPL_TAG_READ_RPL = 0x3C,
92 CPL_HIT_NOTIFY = 0x3D,
93 CPL_PKT_NOTIFY = 0x3E,
94 CPL_RX_DDP_COMPLETE = 0x3F,
96 CPL_ACT_ESTABLISH = 0x40,
97 CPL_PASS_ESTABLISH = 0x41,
98 CPL_RX_DATA_DDP = 0x42,
99 CPL_SMT_READ_RPL = 0x43,
100 CPL_PASS_ACCEPT_REQ = 0x44,
101 CPL_RX_ISCSI_CMP = 0x45,
102 CPL_RX_FCOE_DDP = 0x46,
104 CPL_T5_TRACE_PKT = 0x48,
105 CPL_RX_ISCSI_DDP = 0x49,
106 CPL_RX_FCOE_DIF = 0x4A,
107 CPL_RX_DATA_DIF = 0x4B,
108 CPL_ERR_NOTIFY = 0x4D,
110 CPL_RDMA_READ_REQ = 0x60,
111 CPL_RX_ISCSI_DIF = 0x60,
113 CPL_SET_LE_REQ = 0x80,
114 CPL_PASS_OPEN_REQ6 = 0x81,
115 CPL_ACT_OPEN_REQ6 = 0x83,
117 CPL_RDMA_TERMINATE = 0xA2,
118 CPL_RDMA_WRITE = 0xA4,
119 CPL_SGE_EGR_UPDATE = 0xA5,
120 CPL_SET_LE_RPL = 0xA6,
123 CPL_T5_RDMA_READ_REQ = 0xA9,
124 CPL_RDMA_ATOMIC_REQ = 0xAA,
125 CPL_RDMA_ATOMIC_RPL = 0xAB,
126 CPL_RDMA_IMM_DATA = 0xAC,
127 CPL_RDMA_IMM_DATA_SE = 0xAD,
128 CPL_RX_MPS_PKT = 0xAF,
130 CPL_TRACE_PKT = 0xB0,
131 CPL_RX2TX_DATA = 0xB1,
132 CPL_ISCSI_DATA = 0xB2,
133 CPL_FCOE_DATA = 0xB3,
138 CPL_SRQ_TABLE_RPL = 0xCC,
142 CPL_TX_TNL_LSO = 0xEC,
143 CPL_TX_PKT_LSO = 0xED,
144 CPL_TX_PKT_XT = 0xEE,
146 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
151 CPL_ERR_TCAM_PARITY = 1,
152 CPL_ERR_TCAM_MISS = 2,
153 CPL_ERR_TCAM_FULL = 3,
154 CPL_ERR_BAD_LENGTH = 15,
155 CPL_ERR_BAD_ROUTE = 18,
156 CPL_ERR_CONN_RESET = 20,
157 CPL_ERR_CONN_EXIST_SYNRECV = 21,
158 CPL_ERR_CONN_EXIST = 22,
159 CPL_ERR_ARP_MISS = 23,
160 CPL_ERR_BAD_SYN = 24,
161 CPL_ERR_CONN_TIMEDOUT = 30,
162 CPL_ERR_XMIT_TIMEDOUT = 31,
163 CPL_ERR_PERSIST_TIMEDOUT = 32,
164 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
165 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
166 CPL_ERR_RTX_NEG_ADVICE = 35,
167 CPL_ERR_PERSIST_NEG_ADVICE = 36,
168 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
169 CPL_ERR_WAIT_ARP_RPL = 41,
170 CPL_ERR_ABORT_FAILED = 42,
171 CPL_ERR_IWARP_FLM = 50,
172 CPL_CONTAINS_READ_RPL = 60,
173 CPL_CONTAINS_WRITE_RPL = 61,
177 * Some of the error codes above implicitly indicate that there is no TID
178 * allocated with the result of an ACT_OPEN. We use this predicate to make
181 static inline int act_open_has_tid(int status)
183 return (status != CPL_ERR_TCAM_PARITY &&
184 status != CPL_ERR_TCAM_MISS &&
185 status != CPL_ERR_TCAM_FULL &&
186 status != CPL_ERR_CONN_EXIST_SYNRECV &&
187 status != CPL_ERR_CONN_EXIST);
191 CPL_CONN_POLICY_AUTO = 0,
192 CPL_CONN_POLICY_ASK = 1,
193 CPL_CONN_POLICY_FILTER = 2,
194 CPL_CONN_POLICY_DENY = 3
206 ULP_CRC_HEADER = 1 << 0,
207 ULP_CRC_DATA = 1 << 1
211 CPL_PASS_OPEN_ACCEPT,
212 CPL_PASS_OPEN_REJECT,
213 CPL_PASS_OPEN_ACCEPT_TNL
217 CPL_ABORT_SEND_RST = 0,
221 enum { /* TX_PKT_XT checksum types */
235 enum { /* packet type in CPL_RX_PKT */
236 PKTYPE_XACT_UCAST = 0,
237 PKTYPE_HASH_UCAST = 1,
238 PKTYPE_XACT_MCAST = 2,
239 PKTYPE_HASH_MCAST = 3,
245 enum { /* DMAC type in CPL_RX_PKT */
251 enum { /* TCP congestion control algorithms */
258 enum { /* RSS hash type */
259 RSS_HASH_NONE = 0, /* no hash computed */
260 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */
261 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */
262 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */
265 enum { /* LE commands */
270 enum { /* LE request size */
284 #define S_CPL_OPCODE 24
285 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
286 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF)
287 #define G_TID(x) ((x) & 0xFFFFFF)
289 /* tid is assumed to be 24-bits */
290 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
292 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
294 /* extract the TID from a CPL command */
295 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
296 #define GET_OPCODE(cmd) ((cmd)->ot.opcode)
298 /* partitioning of TID fields that also carry a queue id */
300 #define M_TID_TID 0x3fff
301 #define V_TID_TID(x) ((x) << S_TID_TID)
302 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
305 #define M_TID_QID 0x3ff
306 #define V_TID_QID(x) ((x) << S_TID_QID)
307 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID)
317 #if defined(__LITTLE_ENDIAN_BITFIELD)
334 #if defined(__LITTLE_ENDIAN_BITFIELD)
353 #define S_HASHTYPE 20
354 #define M_HASHTYPE 0x3
355 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
358 #define M_QNUM 0xFFFF
359 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
361 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
362 # define RSS_HDR struct rss_header rss_hdr;
368 struct work_request_hdr {
376 #define M_WR_LEN16 0xFF
377 #define V_WR_LEN16(x) ((x) << S_WR_LEN16)
378 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16)
383 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
384 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
386 # define WR_HDR struct work_request_hdr wr
387 # define WR_HDR_SIZE sizeof(struct work_request_hdr)
390 # define WR_HDR_SIZE 0
393 /* option 0 fields */
394 #define S_ACCEPT_MODE 0
395 #define M_ACCEPT_MODE 0x3
396 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE)
397 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE)
400 #define M_TX_CHAN 0x3
401 #define V_TX_CHAN(x) ((x) << S_TX_CHAN)
402 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN)
405 #define V_NO_CONG(x) ((x) << S_NO_CONG)
406 #define F_NO_CONG V_NO_CONG(1U)
409 #define V_DELACK(x) ((x) << S_DELACK)
410 #define F_DELACK V_DELACK(1U)
412 #define S_INJECT_TIMER 6
413 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
414 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
416 #define S_NON_OFFLOAD 7
417 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
418 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
421 #define M_ULP_MODE 0xF
422 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
423 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
425 #define S_RCV_BUFSIZ 12
426 #define M_RCV_BUFSIZ 0x3FFU
427 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
428 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
432 #define V_DSCP(x) ((x) << S_DSCP)
433 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP)
435 #define S_SMAC_SEL 28
436 #define M_SMAC_SEL 0xFF
437 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
438 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL)
441 #define M_L2T_IDX 0xFFF
442 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX)
443 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
445 #define S_TCAM_BYPASS 48
446 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
447 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
450 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE)
451 #define F_NAGLE V_NAGLE(1ULL)
453 #define S_WND_SCALE 50
454 #define M_WND_SCALE 0xF
455 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE)
456 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
458 #define S_KEEP_ALIVE 54
459 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE)
460 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL)
464 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT)
465 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT)
467 #define S_MAX_RT_OVERRIDE 59
468 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE)
469 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL)
472 #define M_MSS_IDX 0xF
473 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
474 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
476 /* option 1 fields */
477 #define S_SYN_RSS_ENABLE 0
478 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE)
479 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U)
481 #define S_SYN_RSS_USE_HASH 1
482 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH)
483 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U)
485 #define S_SYN_RSS_QUEUE 2
486 #define M_SYN_RSS_QUEUE 0x3FF
487 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE)
488 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE)
490 #define S_LISTEN_INTF 12
491 #define M_LISTEN_INTF 0xFF
492 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF)
493 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF)
495 #define S_LISTEN_FILTER 20
496 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER)
497 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U)
499 #define S_SYN_DEFENSE 21
500 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
501 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
503 #define S_CONN_POLICY 22
504 #define M_CONN_POLICY 0x3
505 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
506 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
508 #define S_T5_FILT_INFO 24
509 #define M_T5_FILT_INFO 0xffffffffffULL
510 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO)
511 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO)
513 #define S_FILT_INFO 28
514 #define M_FILT_INFO 0xfffffffffULL
515 #define V_FILT_INFO(x) ((x) << S_FILT_INFO)
516 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO)
518 /* option 2 fields */
519 #define S_RSS_QUEUE 0
520 #define M_RSS_QUEUE 0x3FF
521 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
522 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
524 #define S_RSS_QUEUE_VALID 10
525 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
526 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
528 #define S_RX_COALESCE_VALID 11
529 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
530 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
532 #define S_RX_COALESCE 12
533 #define M_RX_COALESCE 0x3
534 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
535 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
537 #define S_CONG_CNTRL 14
538 #define M_CONG_CNTRL 0x3
539 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
540 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL)
544 #define V_PACE(x) ((x) << S_PACE)
545 #define G_PACE(x) (((x) >> S_PACE) & M_PACE)
547 #define S_CONG_CNTRL_VALID 18
548 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID)
549 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U)
552 #define V_T5_ISS(x) ((x) << S_T5_ISS)
553 #define F_T5_ISS V_T5_ISS(1U)
555 #define S_PACE_VALID 19
556 #define V_PACE_VALID(x) ((x) << S_PACE_VALID)
557 #define F_PACE_VALID V_PACE_VALID(1U)
559 #define S_RX_FC_DISABLE 20
560 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
561 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
563 #define S_RX_FC_DDP 21
564 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP)
565 #define F_RX_FC_DDP V_RX_FC_DDP(1U)
567 #define S_RX_FC_VALID 22
568 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
569 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
571 #define S_TX_QUEUE 23
572 #define M_TX_QUEUE 0x7
573 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE)
574 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE)
576 #define S_RX_CHANNEL 26
577 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
578 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
580 #define S_CCTRL_ECN 27
581 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
582 #define F_CCTRL_ECN V_CCTRL_ECN(1U)
584 #define S_WND_SCALE_EN 28
585 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN)
586 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U)
588 #define S_TSTAMPS_EN 29
589 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
590 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U)
593 #define V_SACK_EN(x) ((x) << S_SACK_EN)
594 #define F_SACK_EN V_SACK_EN(1U)
596 #define S_T5_OPT_2_VALID 31
597 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
598 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
600 struct cpl_pass_open_req {
611 struct cpl_pass_open_req6 {
624 struct cpl_pass_open_rpl {
631 struct cpl_pass_establish {
642 /* cpl_pass_establish.tos_stid fields */
643 #define S_PASS_OPEN_TID 0
644 #define M_PASS_OPEN_TID 0xFFFFFF
645 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
646 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
648 #define S_PASS_OPEN_TOS 24
649 #define M_PASS_OPEN_TOS 0xFF
650 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
651 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
653 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
654 #define S_TCPOPT_WSCALE_OK 5
655 #define M_TCPOPT_WSCALE_OK 0x1
656 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK)
657 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK)
659 #define S_TCPOPT_SACK 6
660 #define M_TCPOPT_SACK 0x1
661 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK)
662 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK)
664 #define S_TCPOPT_TSTAMP 7
665 #define M_TCPOPT_TSTAMP 0x1
666 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP)
667 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP)
669 #define S_TCPOPT_SND_WSCALE 8
670 #define M_TCPOPT_SND_WSCALE 0xF
671 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE)
672 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE)
674 #define S_TCPOPT_MSS 12
675 #define M_TCPOPT_MSS 0xF
676 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS)
677 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS)
679 struct cpl_pass_accept_req {
688 struct tcp_options tcpopt;
691 /* cpl_pass_accept_req.hdr_len fields */
692 #define S_SYN_RX_CHAN 0
693 #define M_SYN_RX_CHAN 0xF
694 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
695 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN)
697 #define S_TCP_HDR_LEN 10
698 #define M_TCP_HDR_LEN 0x3F
699 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
700 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
702 #define S_T6_TCP_HDR_LEN 8
703 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN)
704 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN)
706 #define S_IP_HDR_LEN 16
707 #define M_IP_HDR_LEN 0x3FF
708 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
709 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
711 #define S_T6_IP_HDR_LEN 14
712 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN)
713 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN)
715 #define S_ETH_HDR_LEN 26
716 #define M_ETH_HDR_LEN 0x3F
717 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
718 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
720 #define S_T6_ETH_HDR_LEN 24
721 #define M_T6_ETH_HDR_LEN 0xFF
722 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN)
723 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN)
725 /* cpl_pass_accept_req.l2info fields */
726 #define S_SYN_MAC_IDX 0
727 #define M_SYN_MAC_IDX 0x1FF
728 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
729 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX)
731 #define S_SYN_XACT_MATCH 9
732 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
733 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U)
735 #define S_SYN_INTF 12
736 #define M_SYN_INTF 0xF
737 #define V_SYN_INTF(x) ((x) << S_SYN_INTF)
738 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
740 struct cpl_pass_accept_rpl {
747 struct cpl_t5_pass_accept_rpl {
754 __be32 rsvd; /* T5 */
755 __be32 opt3; /* T6 */
759 struct cpl_act_open_req {
771 #define S_FILTER_TUPLE 24
772 #define M_FILTER_TUPLE 0xFFFFFFFFFF
773 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
774 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
775 struct cpl_t5_act_open_req {
788 struct cpl_t6_act_open_req {
803 /* cpl_{t5,t6}_act_open_req.params field */
804 #define S_AOPEN_FCOEMASK 0
805 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK)
806 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U)
808 struct cpl_act_open_req6 {
822 struct cpl_t5_act_open_req6 {
837 struct cpl_t6_act_open_req6 {
854 struct cpl_act_open_rpl {
860 /* cpl_act_open_rpl.atid_status fields */
861 #define S_AOPEN_STATUS 0
862 #define M_AOPEN_STATUS 0xFF
863 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS)
864 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
866 #define S_AOPEN_ATID 8
867 #define M_AOPEN_ATID 0xFFFFFF
868 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID)
869 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
871 struct cpl_act_establish {
889 /* cpl_get_tcb.reply_ctrl fields */
891 #define M_QUEUENO 0x3FF
892 #define V_QUEUENO(x) ((x) << S_QUEUENO)
893 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO)
895 #define S_REPLY_CHAN 14
896 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
897 #define F_REPLY_CHAN V_REPLY_CHAN(1U)
899 #define S_NO_REPLY 15
900 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
901 #define F_NO_REPLY V_NO_REPLY(1U)
903 struct cpl_get_tcb_rpl {
918 struct cpl_set_tcb_field {
927 struct cpl_set_tcb_field_core {
935 /* cpl_set_tcb_field.word_cookie fields */
938 #define V_WORD(x) ((x) << S_WORD)
939 #define G_WORD(x) (((x) >> S_WORD) & M_WORD)
943 #define V_COOKIE(x) ((x) << S_COOKIE)
944 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
946 struct cpl_set_tcb_rpl {
955 struct cpl_close_con_req {
961 struct cpl_close_con_rpl {
970 struct cpl_close_listsvr_req {
977 /* additional cpl_close_listsvr_req.reply_ctrl field */
978 #define S_LISTSVR_IPV6 14
979 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6)
980 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U)
982 struct cpl_close_listsvr_rpl {
989 struct cpl_abort_req_rss {
996 /* cpl_abort_req status command code in case of T6,
997 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1)
998 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ
999 * bit[2] specifies whether to disable the mmgr (1) or not (0)
1001 struct cpl_abort_req {
1003 union opcode_tid ot;
1010 struct cpl_abort_rpl_rss {
1012 union opcode_tid ot;
1017 struct cpl_abort_rpl {
1019 union opcode_tid ot;
1026 struct cpl_peer_close {
1028 union opcode_tid ot;
1032 struct cpl_tid_release {
1034 union opcode_tid ot;
1047 /* tx_data_wr.flags fields */
1048 #define S_TX_ACK_PAGES 21
1049 #define M_TX_ACK_PAGES 0x7
1050 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
1051 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
1053 /* tx_data_wr.param fields */
1055 #define M_TX_PORT 0x7
1056 #define V_TX_PORT(x) ((x) << S_TX_PORT)
1057 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
1060 #define M_TX_MSS 0xF
1061 #define V_TX_MSS(x) ((x) << S_TX_MSS)
1062 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
1065 #define M_TX_QOS 0xFF
1066 #define V_TX_QOS(x) ((x) << S_TX_QOS)
1067 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
1069 #define S_TX_SNDBUF 16
1070 #define M_TX_SNDBUF 0xFFFF
1071 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
1072 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
1074 struct cpl_tx_data {
1075 union opcode_tid ot;
1081 /* cpl_tx_data.flags fields */
1082 #define S_TX_PROXY 5
1083 #define V_TX_PROXY(x) ((x) << S_TX_PROXY)
1084 #define F_TX_PROXY V_TX_PROXY(1U)
1086 #define S_TX_ULP_SUBMODE 6
1087 #define M_TX_ULP_SUBMODE 0xF
1088 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
1089 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
1091 #define S_TX_ULP_MODE 10
1092 #define M_TX_ULP_MODE 0x7
1093 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
1094 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
1096 #define S_TX_FORCE 13
1097 #define V_TX_FORCE(x) ((x) << S_TX_FORCE)
1098 #define F_TX_FORCE V_TX_FORCE(1U)
1100 #define S_TX_SHOVE 14
1101 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
1102 #define F_TX_SHOVE V_TX_SHOVE(1U)
1104 #define S_TX_MORE 15
1105 #define V_TX_MORE(x) ((x) << S_TX_MORE)
1106 #define F_TX_MORE V_TX_MORE(1U)
1109 #define V_TX_URG(x) ((x) << S_TX_URG)
1110 #define F_TX_URG V_TX_URG(1U)
1112 #define S_TX_FLUSH 17
1113 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH)
1114 #define F_TX_FLUSH V_TX_FLUSH(1U)
1116 #define S_TX_SAVE 18
1117 #define V_TX_SAVE(x) ((x) << S_TX_SAVE)
1118 #define F_TX_SAVE V_TX_SAVE(1U)
1121 #define V_TX_TNL(x) ((x) << S_TX_TNL)
1122 #define F_TX_TNL V_TX_TNL(1U)
1124 #define S_T6_TX_FORCE 20
1125 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE)
1126 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U)
1128 /* additional tx_data_wr.flags fields */
1129 #define S_TX_CPU_IDX 0
1130 #define M_TX_CPU_IDX 0x3F
1131 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
1132 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
1134 #define S_TX_CLOSE 17
1135 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
1136 #define F_TX_CLOSE V_TX_CLOSE(1U)
1138 #define S_TX_INIT 18
1139 #define V_TX_INIT(x) ((x) << S_TX_INIT)
1140 #define F_TX_INIT V_TX_INIT(1U)
1142 #define S_TX_IMM_ACK 19
1143 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
1144 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
1146 #define S_TX_IMM_DMA 20
1147 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
1148 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
1150 struct cpl_tx_data_ack {
1152 union opcode_tid ot;
1156 struct cpl_wr_ack { /* XXX */
1158 union opcode_tid ot;
1165 struct cpl_tx_pkt_core {
1174 struct cpl_tx_pkt_core c;
1177 #define cpl_tx_pkt_xt cpl_tx_pkt
1179 /* cpl_tx_pkt_core.ctrl0 fields */
1180 #define S_TXPKT_VF 0
1181 #define M_TXPKT_VF 0xFF
1182 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF)
1183 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF)
1185 #define S_TXPKT_PF 8
1186 #define M_TXPKT_PF 0x7
1187 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
1188 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
1190 #define S_TXPKT_VF_VLD 11
1191 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
1192 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U)
1194 #define S_TXPKT_OVLAN_IDX 12
1195 #define M_TXPKT_OVLAN_IDX 0xF
1196 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
1197 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
1199 #define S_TXPKT_T5_OVLAN_IDX 12
1200 #define M_TXPKT_T5_OVLAN_IDX 0x7
1201 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX)
1202 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \
1203 M_TXPKT_T5_OVLAN_IDX)
1205 #define S_TXPKT_INTF 16
1206 #define M_TXPKT_INTF 0xF
1207 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1208 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1210 #define S_TXPKT_SPECIAL_STAT 20
1211 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
1212 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
1214 #define S_TXPKT_T5_FCS_DIS 21
1215 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS)
1216 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U)
1218 #define S_TXPKT_INS_OVLAN 21
1219 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
1220 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
1222 #define S_TXPKT_T5_INS_OVLAN 15
1223 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN)
1224 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U)
1226 #define S_TXPKT_STAT_DIS 22
1227 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
1228 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
1230 #define S_TXPKT_LOOPBACK 23
1231 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1232 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1234 #define S_TXPKT_TSTAMP 23
1235 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP)
1236 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U)
1238 #define S_TXPKT_OPCODE 24
1239 #define M_TXPKT_OPCODE 0xFF
1240 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1241 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1243 /* cpl_tx_pkt_core.ctrl1 fields */
1244 #define S_TXPKT_SA_IDX 0
1245 #define M_TXPKT_SA_IDX 0xFFF
1246 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX)
1247 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX)
1249 #define S_TXPKT_CSUM_END 12
1250 #define M_TXPKT_CSUM_END 0xFF
1251 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END)
1252 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END)
1254 #define S_TXPKT_CSUM_START 20
1255 #define M_TXPKT_CSUM_START 0x3FF
1256 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START)
1257 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START)
1259 #define S_TXPKT_IPHDR_LEN 20
1260 #define M_TXPKT_IPHDR_LEN 0x3FFF
1261 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
1262 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
1264 #define M_T6_TXPKT_IPHDR_LEN 0xFFF
1265 #define G_T6_TXPKT_IPHDR_LEN(x) \
1266 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN)
1268 #define S_TXPKT_CSUM_LOC 30
1269 #define M_TXPKT_CSUM_LOC 0x3FF
1270 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC)
1271 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC)
1273 #define S_TXPKT_ETHHDR_LEN 34
1274 #define M_TXPKT_ETHHDR_LEN 0x3F
1275 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
1276 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
1278 #define S_T6_TXPKT_ETHHDR_LEN 32
1279 #define M_T6_TXPKT_ETHHDR_LEN 0xFF
1280 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
1281 #define G_T6_TXPKT_ETHHDR_LEN(x) \
1282 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
1284 #define S_TXPKT_CSUM_TYPE 40
1285 #define M_TXPKT_CSUM_TYPE 0xF
1286 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
1287 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
1289 #define S_TXPKT_VLAN 44
1290 #define M_TXPKT_VLAN 0xFFFF
1291 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
1292 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1294 #define S_TXPKT_VLAN_VLD 60
1295 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
1296 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
1298 #define S_TXPKT_IPSEC 61
1299 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC)
1300 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL)
1302 #define S_TXPKT_IPCSUM_DIS 62
1303 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
1304 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
1306 #define S_TXPKT_L4CSUM_DIS 63
1307 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
1308 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
1310 struct cpl_tx_pkt_lso_core {
1314 __be32 seqno_offset;
1316 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1319 struct cpl_tx_pkt_lso {
1321 struct cpl_tx_pkt_lso_core c;
1322 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1325 struct cpl_tx_pkt_ufo_core {
1332 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1335 struct cpl_tx_pkt_ufo {
1337 struct cpl_tx_pkt_ufo_core c;
1338 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1341 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
1342 #define S_LSO_TCPHDR_LEN 0
1343 #define M_LSO_TCPHDR_LEN 0xF
1344 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
1345 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
1347 #define S_LSO_IPHDR_LEN 4
1348 #define M_LSO_IPHDR_LEN 0xFFF
1349 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
1350 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
1352 #define S_LSO_ETHHDR_LEN 16
1353 #define M_LSO_ETHHDR_LEN 0xF
1354 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
1355 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
1357 #define S_LSO_IPV6 20
1358 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1359 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1361 #define S_LSO_OFLD_ENCAP 21
1362 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP)
1363 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U)
1365 #define S_LSO_LAST_SLICE 22
1366 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
1367 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
1369 #define S_LSO_FIRST_SLICE 23
1370 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
1371 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
1373 #define S_LSO_OPCODE 24
1374 #define M_LSO_OPCODE 0xFF
1375 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
1376 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
1378 #define S_LSO_T5_XFER_SIZE 0
1379 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF
1380 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
1381 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
1383 /* cpl_tx_pkt_lso_core.mss fields */
1385 #define M_LSO_MSS 0x3FFF
1386 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1387 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1389 #define S_LSO_IPID_SPLIT 15
1390 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)
1391 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U)
1393 struct cpl_tx_pkt_fso {
1398 __be32 param_offset;
1400 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */
1403 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */
1404 #define S_FSO_XCHG_CLASS 21
1405 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS)
1406 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U)
1408 #define S_FSO_INITIATOR 20
1409 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR)
1410 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U)
1412 #define S_FSO_FCHDR_LEN 12
1413 #define M_FSO_FCHDR_LEN 0xF
1414 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN)
1415 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN)
1417 struct cpl_iscsi_hdr_no_rss {
1418 union opcode_tid ot;
1427 struct cpl_tx_data_iso {
1434 __be32 reserved2_seglen_offset;
1435 __be32 datasn_offset;
1436 __be32 buffer_offset;
1439 /* encapsulated CPL_TX_DATA follows here */
1442 /* cpl_tx_data_iso.op_to_scsi fields */
1443 #define S_CPL_TX_DATA_ISO_OP 24
1444 #define M_CPL_TX_DATA_ISO_OP 0xff
1445 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP)
1446 #define G_CPL_TX_DATA_ISO_OP(x) \
1447 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP)
1449 #define S_CPL_TX_DATA_ISO_FIRST 23
1450 #define M_CPL_TX_DATA_ISO_FIRST 0x1
1451 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST)
1452 #define G_CPL_TX_DATA_ISO_FIRST(x) \
1453 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST)
1454 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U)
1456 #define S_CPL_TX_DATA_ISO_LAST 22
1457 #define M_CPL_TX_DATA_ISO_LAST 0x1
1458 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST)
1459 #define G_CPL_TX_DATA_ISO_LAST(x) \
1460 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST)
1461 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U)
1463 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21
1464 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1
1465 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN)
1466 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \
1467 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN)
1468 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U)
1470 #define S_CPL_TX_DATA_ISO_HDRCRC 20
1471 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1
1472 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC)
1473 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \
1474 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC)
1475 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U)
1477 #define S_CPL_TX_DATA_ISO_PLDCRC 19
1478 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1
1479 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC)
1480 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \
1481 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC)
1482 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U)
1484 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18
1485 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1
1486 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE)
1487 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \
1488 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE)
1489 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U)
1491 #define S_CPL_TX_DATA_ISO_SCSI 16
1492 #define M_CPL_TX_DATA_ISO_SCSI 0x3
1493 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI)
1494 #define G_CPL_TX_DATA_ISO_SCSI(x) \
1495 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI)
1497 /* cpl_tx_data_iso.reserved2_seglen_offset fields */
1498 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0
1499 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff
1500 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \
1501 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET)
1502 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \
1503 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \
1504 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET)
1506 struct cpl_iscsi_hdr {
1508 union opcode_tid ot;
1517 /* cpl_iscsi_hdr.pdu_len_ddp fields */
1518 #define S_ISCSI_PDU_LEN 0
1519 #define M_ISCSI_PDU_LEN 0x7FFF
1520 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
1521 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
1523 #define S_ISCSI_DDP 15
1524 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
1525 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
1527 struct cpl_iscsi_data {
1529 union opcode_tid ot;
1538 struct cpl_rx_data {
1540 union opcode_tid ot;
1545 #if defined(__LITTLE_ENDIAN_BITFIELD)
1561 struct cpl_fcoe_hdr {
1563 union opcode_tid ot;
1577 /* cpl_fcoe_hdr.rctl_fctl fields */
1578 #define S_FCOE_FCHDR_RCTL 24
1579 #define M_FCOE_FCHDR_RCTL 0xff
1580 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL)
1581 #define G_FCOE_FCHDR_RCTL(x) \
1582 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL)
1584 #define S_FCOE_FCHDR_FCTL 0
1585 #define M_FCOE_FCHDR_FCTL 0xffffff
1586 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL)
1587 #define G_FCOE_FCHDR_FCTL(x) \
1588 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL)
1590 struct cpl_fcoe_data {
1592 union opcode_tid ot;
1600 struct cpl_rx_urg_notify {
1602 union opcode_tid ot;
1606 struct cpl_rx_urg_pkt {
1608 union opcode_tid ot;
1613 struct cpl_rx_data_ack {
1615 union opcode_tid ot;
1619 struct cpl_rx_data_ack_core {
1620 union opcode_tid ot;
1624 /* cpl_rx_data_ack.ack_seq fields */
1625 #define S_RX_CREDITS 0
1626 #define M_RX_CREDITS 0x3FFFFFF
1627 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1628 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1630 #define S_RX_MODULATE_TX 26
1631 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX)
1632 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U)
1634 #define S_RX_MODULATE_RX 27
1635 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX)
1636 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U)
1638 #define S_RX_FORCE_ACK 28
1639 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1640 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
1642 #define S_RX_DACK_MODE 29
1643 #define M_RX_DACK_MODE 0x3
1644 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1645 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1647 #define S_RX_DACK_CHANGE 31
1648 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1649 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
1651 struct cpl_rx_ddp_complete {
1653 union opcode_tid ot;
1659 struct cpl_rx_data_ddp {
1661 union opcode_tid ot;
1673 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
1675 struct cpl_rx_fcoe_ddp {
1677 union opcode_tid ot;
1686 struct cpl_rx_data_dif {
1688 union opcode_tid ot;
1700 struct cpl_rx_iscsi_dif {
1702 union opcode_tid ot;
1717 struct cpl_rx_iscsi_cmp {
1719 union opcode_tid ot;
1730 struct cpl_rx_fcoe_dif {
1732 union opcode_tid ot;
1741 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */
1742 #define S_DDP_VALID 15
1743 #define M_DDP_VALID 0x1FFFF
1744 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1745 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1747 #define S_DDP_PPOD_MISMATCH 15
1748 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1749 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1751 #define S_DDP_PDU 16
1752 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1753 #define F_DDP_PDU V_DDP_PDU(1U)
1755 #define S_DDP_LLIMIT_ERR 17
1756 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1757 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1759 #define S_DDP_PPOD_PARITY_ERR 18
1760 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1761 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1763 #define S_DDP_PADDING_ERR 19
1764 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1765 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1767 #define S_DDP_HDRCRC_ERR 20
1768 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1769 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1771 #define S_DDP_DATACRC_ERR 21
1772 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1773 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1775 #define S_DDP_INVALID_TAG 22
1776 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1777 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1779 #define S_DDP_ULIMIT_ERR 23
1780 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1781 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1783 #define S_DDP_OFFSET_ERR 24
1784 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1785 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1787 #define S_DDP_COLOR_ERR 25
1788 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1789 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1791 #define S_DDP_TID_MISMATCH 26
1792 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1793 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1795 #define S_DDP_INVALID_PPOD 27
1796 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1797 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1799 #define S_DDP_ULP_MODE 28
1800 #define M_DDP_ULP_MODE 0xF
1801 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1802 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1804 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */
1805 #define S_DDP_OFFSET 0
1806 #define M_DDP_OFFSET 0xFFFFFF
1807 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1808 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1810 #define S_DDP_DACK_MODE 24
1811 #define M_DDP_DACK_MODE 0x3
1812 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1813 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1815 #define S_DDP_BUF_IDX 26
1816 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1817 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1819 #define S_DDP_URG 27
1820 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1821 #define F_DDP_URG V_DDP_URG(1U)
1823 #define S_DDP_PSH 28
1824 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1825 #define F_DDP_PSH V_DDP_PSH(1U)
1827 #define S_DDP_BUF_COMPLETE 29
1828 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1829 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1831 #define S_DDP_BUF_TIMED_OUT 30
1832 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1833 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1835 #define S_DDP_INV 31
1836 #define V_DDP_INV(x) ((x) << S_DDP_INV)
1837 #define F_DDP_INV V_DDP_INV(1U)
1842 #if defined(__LITTLE_ENDIAN_BITFIELD)
1863 /* rx_pkt.l2info fields */
1864 #define S_RX_ETHHDR_LEN 0
1865 #define M_RX_ETHHDR_LEN 0x1F
1866 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
1867 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
1869 #define S_RX_T5_ETHHDR_LEN 0
1870 #define M_RX_T5_ETHHDR_LEN 0x3F
1871 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
1872 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
1874 #define M_RX_T6_ETHHDR_LEN 0xFF
1875 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN)
1877 #define S_RX_PKTYPE 5
1878 #define M_RX_PKTYPE 0x7
1879 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE)
1880 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE)
1882 #define S_RX_T5_DATYPE 6
1883 #define M_RX_T5_DATYPE 0x3
1884 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE)
1885 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE)
1887 #define S_RX_MACIDX 8
1888 #define M_RX_MACIDX 0x1FF
1889 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
1890 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
1892 #define S_RX_T5_PKTYPE 17
1893 #define M_RX_T5_PKTYPE 0x7
1894 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE)
1895 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE)
1897 #define S_RX_DATYPE 18
1898 #define M_RX_DATYPE 0x3
1899 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE)
1900 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE)
1902 #define S_RXF_PSH 20
1903 #define V_RXF_PSH(x) ((x) << S_RXF_PSH)
1904 #define F_RXF_PSH V_RXF_PSH(1U)
1906 #define S_RXF_SYN 21
1907 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
1908 #define F_RXF_SYN V_RXF_SYN(1U)
1910 #define S_RXF_UDP 22
1911 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
1912 #define F_RXF_UDP V_RXF_UDP(1U)
1914 #define S_RXF_TCP 23
1915 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
1916 #define F_RXF_TCP V_RXF_TCP(1U)
1919 #define V_RXF_IP(x) ((x) << S_RXF_IP)
1920 #define F_RXF_IP V_RXF_IP(1U)
1922 #define S_RXF_IP6 25
1923 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
1924 #define F_RXF_IP6 V_RXF_IP6(1U)
1926 #define S_RXF_SYN_COOKIE 26
1927 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE)
1928 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U)
1930 #define S_RXF_FCOE 26
1931 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE)
1932 #define F_RXF_FCOE V_RXF_FCOE(1U)
1934 #define S_RXF_LRO 27
1935 #define V_RXF_LRO(x) ((x) << S_RXF_LRO)
1936 #define F_RXF_LRO V_RXF_LRO(1U)
1938 #define S_RX_CHAN 28
1939 #define M_RX_CHAN 0xF
1940 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
1941 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
1943 /* rx_pkt.hdr_len fields */
1944 #define S_RX_TCPHDR_LEN 0
1945 #define M_RX_TCPHDR_LEN 0x3F
1946 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
1947 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
1949 #define S_RX_IPHDR_LEN 6
1950 #define M_RX_IPHDR_LEN 0x3FF
1951 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
1952 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
1954 /* rx_pkt.err_vec fields */
1955 #define S_RXERR_OR 0
1956 #define V_RXERR_OR(x) ((x) << S_RXERR_OR)
1957 #define F_RXERR_OR V_RXERR_OR(1U)
1959 #define S_RXERR_MAC 1
1960 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC)
1961 #define F_RXERR_MAC V_RXERR_MAC(1U)
1963 #define S_RXERR_IPVERS 2
1964 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS)
1965 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U)
1967 #define S_RXERR_FRAG 3
1968 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG)
1969 #define F_RXERR_FRAG V_RXERR_FRAG(1U)
1971 #define S_RXERR_ATTACK 4
1972 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK)
1973 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U)
1975 #define S_RXERR_ETHHDR_LEN 5
1976 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN)
1977 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U)
1979 #define S_RXERR_IPHDR_LEN 6
1980 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN)
1981 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U)
1983 #define S_RXERR_TCPHDR_LEN 7
1984 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN)
1985 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U)
1987 #define S_RXERR_PKT_LEN 8
1988 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN)
1989 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U)
1991 #define S_RXERR_TCP_OPT 9
1992 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT)
1993 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U)
1995 #define S_RXERR_IPCSUM 12
1996 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM)
1997 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U)
1999 #define S_RXERR_CSUM 13
2000 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM)
2001 #define F_RXERR_CSUM V_RXERR_CSUM(1U)
2003 #define S_RXERR_PING 14
2004 #define V_RXERR_PING(x) ((x) << S_RXERR_PING)
2005 #define F_RXERR_PING V_RXERR_PING(1U)
2007 /* In T6, rx_pkt.err_vec indicates
2008 * RxError Error vector (16b) or
2009 * Encapsulating header length (8b),
2010 * Outer encapsulation type (2b) and
2011 * compressed error vector (6b) if CRxPktEnc is
2012 * enabled in TP_OUT_CONFIG
2015 #define S_T6_COMPR_RXERR_VEC 0
2016 #define M_T6_COMPR_RXERR_VEC 0x3F
2017 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_LEN)
2018 #define G_T6_COMPR_RXERR_VEC(x) \
2019 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
2021 #define S_T6_COMPR_RXERR_MAC 0
2022 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC)
2023 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U)
2025 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN
2026 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN
2028 #define S_T6_COMPR_RXERR_LEN 1
2029 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_COMPR_T6_RXERR_LEN)
2030 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U)
2032 #define S_T6_COMPR_RXERR_TCP_OPT 2
2033 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT)
2034 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U)
2036 #define S_T6_COMPR_RXERR_IPV6_EXT 3
2037 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT)
2038 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U)
2040 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */
2041 #define S_T6_COMPR_RXERR_SUM 4
2042 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM)
2043 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U)
2045 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP,
2046 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION
2048 #define S_T6_COMPR_RXERR_MISC 5
2049 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC)
2050 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U)
2052 #define S_T6_RX_TNL_TYPE 6
2053 #define M_T6_RX_TNL_TYPE 0x3
2054 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE)
2055 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE)
2057 #define RX_PKT_TNL_TYPE_NVGRE 1
2058 #define RX_PKT_TNL_TYPE_VXLAN 2
2059 #define RX_PKT_TNL_TYPE_GENEVE 3
2061 #define S_T6_RX_TNLHDR_LEN 8
2062 #define M_T6_RX_TNLHDR_LEN 0xFF
2063 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN)
2064 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN)
2066 struct cpl_trace_pkt {
2070 #if defined(__LITTLE_ENDIAN_BITFIELD)
2088 struct cpl_t5_trace_pkt {
2092 #if defined(__LITTLE_ENDIAN_BITFIELD)
2111 struct cpl_rte_delete_req {
2113 union opcode_tid ot;
2117 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */
2118 #define S_RTE_REQ_LUT_IX 8
2119 #define M_RTE_REQ_LUT_IX 0x7FF
2120 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
2121 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
2123 #define S_RTE_REQ_LUT_BASE 19
2124 #define M_RTE_REQ_LUT_BASE 0x7FF
2125 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
2126 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
2128 #define S_RTE_READ_REQ_SELECT 31
2129 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
2130 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
2132 struct cpl_rte_delete_rpl {
2134 union opcode_tid ot;
2139 struct cpl_rte_write_req {
2141 union opcode_tid ot;
2149 /* cpl_rte_write_req.write_sel fields */
2150 #define S_RTE_WR_L2TIDX 31
2151 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX)
2152 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U)
2154 #define S_RTE_WR_FADDR 30
2155 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR)
2156 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U)
2158 /* cpl_rte_write_req.lut_params fields */
2159 #define S_RTE_WR_LUT_IX 10
2160 #define M_RTE_WR_LUT_IX 0x7FF
2161 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX)
2162 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX)
2164 #define S_RTE_WR_LUT_BASE 21
2165 #define M_RTE_WR_LUT_BASE 0x7FF
2166 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE)
2167 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE)
2169 struct cpl_rte_write_rpl {
2171 union opcode_tid ot;
2176 struct cpl_rte_read_req {
2178 union opcode_tid ot;
2182 struct cpl_rte_read_rpl {
2184 union opcode_tid ot;
2188 #if defined(__LITTLE_ENDIAN_BITFIELD)
2198 struct cpl_l2t_write_req {
2200 union opcode_tid ot;
2207 /* cpl_l2t_write_req.params fields */
2208 #define S_L2T_W_INFO 2
2209 #define M_L2T_W_INFO 0x3F
2210 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
2211 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
2213 #define S_L2T_W_PORT 8
2214 #define M_L2T_W_PORT 0x3
2215 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
2216 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
2218 #define S_L2T_W_LPBK 10
2219 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK)
2220 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U)
2222 #define S_L2T_W_ARPMISS 11
2223 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS)
2224 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U)
2226 #define S_L2T_W_NOREPLY 15
2227 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
2228 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
2230 #define CPL_L2T_VLAN_NONE 0xfff
2232 struct cpl_l2t_write_rpl {
2234 union opcode_tid ot;
2239 struct cpl_l2t_read_req {
2241 union opcode_tid ot;
2245 struct cpl_l2t_read_rpl {
2247 union opcode_tid ot;
2249 #if defined(__LITTLE_ENDIAN_BITFIELD)
2261 struct cpl_srq_table_req {
2263 union opcode_tid ot;
2273 struct cpl_srq_table_rpl {
2275 union opcode_tid ot;
2285 /* cpl_srq_table_{req,rpl}.params fields */
2286 #define S_SRQT_QLEN 28
2287 #define M_SRQT_QLEN 0xF
2288 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN)
2289 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN)
2291 #define S_SRQT_QBASE 0
2292 #define M_SRQT_QBASE 0x3FFFFFF
2293 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE)
2294 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE)
2296 #define S_SRQT_PDID 0
2297 #define M_SRQT_PDID 0xFF
2298 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID)
2299 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID)
2301 #define S_SRQT_IDX 0
2302 #define M_SRQT_IDX 0xF
2303 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX)
2304 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX)
2306 struct cpl_smt_write_req {
2308 union opcode_tid ot;
2316 struct cpl_t6_smt_write_req {
2318 union opcode_tid ot;
2327 struct cpl_smt_write_rpl {
2329 union opcode_tid ot;
2334 struct cpl_smt_read_req {
2336 union opcode_tid ot;
2340 struct cpl_smt_read_rpl {
2342 union opcode_tid ot;
2352 /* cpl_smt_{read,write}_req.params fields */
2353 #define S_SMTW_OVLAN_IDX 16
2354 #define M_SMTW_OVLAN_IDX 0xF
2355 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX)
2356 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX)
2358 #define S_SMTW_IDX 20
2359 #define M_SMTW_IDX 0x7F
2360 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX)
2361 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX)
2363 #define M_T6_SMTW_IDX 0xFF
2364 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX)
2366 #define S_SMTW_NORPL 31
2367 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL)
2368 #define F_SMTW_NORPL V_SMTW_NORPL(1U)
2370 /* cpl_smt_{read,write}_req.pfvf? fields */
2372 #define M_SMTW_VF 0xFF
2373 #define V_SMTW_VF(x) ((x) << S_SMTW_VF)
2374 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF)
2377 #define M_SMTW_PF 0x7
2378 #define V_SMTW_PF(x) ((x) << S_SMTW_PF)
2379 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF)
2381 #define S_SMTW_VF_VLD 11
2382 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD)
2383 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U)
2385 struct cpl_tag_write_req {
2387 union opcode_tid ot;
2392 struct cpl_tag_write_rpl {
2394 union opcode_tid ot;
2400 struct cpl_tag_read_req {
2402 union opcode_tid ot;
2406 struct cpl_tag_read_rpl {
2408 union opcode_tid ot;
2410 #if defined(__LITTLE_ENDIAN_BITFIELD)
2426 /* cpl_tag{read,write}_req.params fields */
2427 #define S_TAGW_IDX 0
2428 #define M_TAGW_IDX 0x7F
2429 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX)
2430 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX)
2432 #define S_TAGW_LEN 20
2433 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN)
2434 #define F_TAGW_LEN V_TAGW_LEN(1U)
2436 #define S_TAGW_INS_ENABLE 23
2437 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE)
2438 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U)
2440 #define S_TAGW_NORPL 31
2441 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL)
2442 #define F_TAGW_NORPL V_TAGW_NORPL(1U)
2444 struct cpl_barrier {
2452 /* cpl_barrier.chan_map fields */
2453 #define S_CHAN_MAP 4
2454 #define M_CHAN_MAP 0xF
2455 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP)
2456 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP)
2460 union opcode_tid ot;
2464 struct cpl_hit_notify {
2466 union opcode_tid ot;
2472 struct cpl_pkt_notify {
2474 union opcode_tid ot;
2481 /* cpl_{hit,pkt}_notify.info fields */
2482 #define S_NTFY_MAC_IDX 0
2483 #define M_NTFY_MAC_IDX 0x1FF
2484 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX)
2485 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX)
2487 #define S_NTFY_INTF 10
2488 #define M_NTFY_INTF 0xF
2489 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF)
2490 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF)
2492 #define S_NTFY_TCPHDR_LEN 14
2493 #define M_NTFY_TCPHDR_LEN 0xF
2494 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN)
2495 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN)
2497 #define S_NTFY_IPHDR_LEN 18
2498 #define M_NTFY_IPHDR_LEN 0x1FF
2499 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN)
2500 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN)
2502 #define S_NTFY_ETHHDR_LEN 27
2503 #define M_NTFY_ETHHDR_LEN 0x1F
2504 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN)
2505 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN)
2507 #define S_NTFY_T5_IPHDR_LEN 18
2508 #define M_NTFY_T5_IPHDR_LEN 0xFF
2509 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN)
2510 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN)
2512 #define S_NTFY_T5_ETHHDR_LEN 26
2513 #define M_NTFY_T5_ETHHDR_LEN 0x3F
2514 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN)
2515 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN)
2517 struct cpl_rdma_terminate {
2519 union opcode_tid ot;
2524 struct cpl_set_le_req {
2526 union opcode_tid ot;
2535 /* cpl_set_le_req.reply_ctrl additional fields */
2536 #define S_LE_REQ_IP6 13
2537 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6)
2538 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U)
2540 /* cpl_set_le_req.params fields */
2542 #define M_LE_CHAN 0x3
2543 #define V_LE_CHAN(x) ((x) << S_LE_CHAN)
2544 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN)
2546 #define S_LE_OFFSET 5
2547 #define M_LE_OFFSET 0x7
2548 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET)
2549 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET)
2552 #define V_LE_MORE(x) ((x) << S_LE_MORE)
2553 #define F_LE_MORE V_LE_MORE(1U)
2555 #define S_LE_REQSIZE 9
2556 #define M_LE_REQSIZE 0x7
2557 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE)
2558 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE)
2560 #define S_LE_REQCMD 12
2561 #define M_LE_REQCMD 0xF
2562 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD)
2563 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD)
2565 struct cpl_set_le_rpl {
2567 union opcode_tid ot;
2573 /* cpl_set_le_rpl.info fields */
2574 #define S_LE_RSPCMD 0
2575 #define M_LE_RSPCMD 0xF
2576 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD)
2577 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD)
2579 #define S_LE_RSPSIZE 4
2580 #define M_LE_RSPSIZE 0x7
2581 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE)
2582 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE)
2584 #define S_LE_RSPTYPE 7
2585 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE)
2586 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U)
2588 struct cpl_sge_egr_update {
2595 /* cpl_sge_egr_update.ot fields */
2596 #define S_AUTOEQU 22
2597 #define M_AUTOEQU 0x1
2598 #define V_AUTOEQU(x) ((x) << S_AUTOEQU)
2599 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU)
2602 #define M_EGR_QID 0x1FFFF
2603 #define V_EGR_QID(x) ((x) << S_EGR_QID)
2604 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID)
2606 /* cpl_fw*.type values */
2608 FW_TYPE_CMD_RPL = 0,
2611 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
2613 FW_TYPE_WRERR_RPL = 5,
2617 struct cpl_fw2_pld {
2624 struct cpl_fw4_pld {
2635 struct cpl_fw6_pld {
2643 struct cpl_fw2_msg {
2645 union opcode_info oi;
2648 struct cpl_fw4_msg {
2657 struct cpl_fw4_ack {
2659 union opcode_tid ot;
2669 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
2670 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
2671 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
2674 struct cpl_fw6_msg {
2683 /* cpl_fw6_msg.type values */
2685 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL,
2686 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL,
2687 FW6_TYPE_CQE = FW_TYPE_CQE,
2688 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL,
2689 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
2690 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL,
2691 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR,
2695 struct cpl_fw6_msg_ofld_connection_wr_rpl {
2697 __be32 tid; /* or atid in case of active failure */
2703 /* ULP_TX opcodes */
2705 ULP_TX_MEM_READ = 2,
2706 ULP_TX_MEM_WRITE = 3,
2711 ULP_TX_SC_NOOP = 0x80,
2712 ULP_TX_SC_IMM = 0x81,
2713 ULP_TX_SC_DSGL = 0x82,
2714 ULP_TX_SC_ISGL = 0x83,
2715 ULP_TX_SC_PICTRL = 0x84
2718 #define S_ULPTX_CMD 24
2719 #define M_ULPTX_CMD 0xFF
2720 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
2722 #define S_ULPTX_LEN16 0
2723 #define M_ULPTX_LEN16 0xFF
2724 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16)
2726 #define S_ULP_TX_SC_MORE 23
2727 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
2728 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
2730 struct ulptx_sge_pair {
2739 #if !(defined C99_NOT_SUPPORTED)
2740 struct ulptx_sge_pair sge[0];
2753 #if !(defined C99_NOT_SUPPORTED)
2754 struct ulptx_isge sge[0];
2758 struct ulptx_idata {
2763 #define S_ULPTX_NSGE 0
2764 #define M_ULPTX_NSGE 0xFFFF
2765 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
2770 __be32 len16; /* command length */
2771 __be32 dlen; /* data length in 32-byte units */
2775 /* additional ulp_mem_io.cmd fields */
2776 #define S_ULP_MEMIO_ORDER 23
2777 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
2778 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
2780 #define S_T5_ULP_MEMIO_IMM 23
2781 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
2782 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
2784 #define S_T5_ULP_MEMIO_ORDER 22
2785 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
2786 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
2788 #define S_T5_ULP_MEMIO_FID 4
2789 #define M_T5_ULP_MEMIO_FID 0x7ff
2790 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID)
2792 /* ulp_mem_io.lock_addr fields */
2793 #define S_ULP_MEMIO_ADDR 0
2794 #define M_ULP_MEMIO_ADDR 0x7FFFFFF
2795 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
2797 #define S_ULP_MEMIO_LOCK 31
2798 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
2799 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
2801 /* ulp_mem_io.dlen fields */
2802 #define S_ULP_MEMIO_DATA_LEN 0
2803 #define M_ULP_MEMIO_DATA_LEN 0x1F
2804 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
2806 /* ULP_TXPKT field values */
2808 ULP_TXPKT_DEST_TP = 0,
2811 ULP_TXPKT_DEST_DEVNULL,
2819 /* ulp_txpkt.cmd_dest fields */
2820 #define S_ULP_TXPKT_DEST 16
2821 #define M_ULP_TXPKT_DEST 0x3
2822 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
2824 #define S_ULP_TXPKT_FID 4
2825 #define M_ULP_TXPKT_FID 0x7ff
2826 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
2828 #define S_ULP_TXPKT_RO 3
2829 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
2830 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
2832 enum cpl_tx_tnl_lso_type {
2839 struct cpl_tx_tnl_lso {
2840 __be32 op_to_IpIdSplitOut;
2841 __be16 IpIdOffsetOut;
2842 __be16 UdpLenSetOut_to_TnlHdrLen;
2844 __be32 Flow_to_TcpHdrLen;
2846 __be16 IpIdSplit_to_Mss;
2847 __be32 TCPSeqOffset;
2848 __be32 EthLenOffset_Size;
2849 /* encapsulated CPL (TX_PKT_XT) follows here */
2852 #define S_CPL_TX_TNL_LSO_OPCODE 24
2853 #define M_CPL_TX_TNL_LSO_OPCODE 0xff
2854 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE)
2855 #define G_CPL_TX_TNL_LSO_OPCODE(x) \
2856 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE)
2858 #define S_CPL_TX_TNL_LSO_FIRST 23
2859 #define M_CPL_TX_TNL_LSO_FIRST 0x1
2860 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST)
2861 #define G_CPL_TX_TNL_LSO_FIRST(x) \
2862 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST)
2863 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U)
2865 #define S_CPL_TX_TNL_LSO_LAST 22
2866 #define M_CPL_TX_TNL_LSO_LAST 0x1
2867 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST)
2868 #define G_CPL_TX_TNL_LSO_LAST(x) \
2869 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST)
2870 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U)
2872 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21
2873 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1
2874 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \
2875 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT)
2876 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \
2877 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT)
2878 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U)
2880 #define S_CPL_TX_TNL_LSO_IPV6OUT 20
2881 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1
2882 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT)
2883 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \
2884 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT)
2885 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U)
2887 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16
2888 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf
2889 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \
2890 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT)
2891 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \
2892 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT)
2894 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4
2895 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff
2896 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT)
2897 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \
2898 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT)
2900 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3
2901 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1
2902 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT)
2903 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \
2904 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT)
2905 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U)
2907 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2
2908 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1
2909 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT)
2910 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \
2911 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT)
2912 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U)
2914 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1
2915 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1
2916 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT)
2917 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \
2918 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT)
2919 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U)
2921 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0
2922 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1
2923 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \
2924 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT)
2925 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \
2926 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT)
2927 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U)
2929 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15
2930 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1
2931 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \
2932 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT)
2933 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \
2934 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT)
2935 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U)
2937 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14
2938 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1
2939 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \
2940 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT)
2941 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \
2942 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT)
2943 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U)
2945 #define S_CPL_TX_TNL_LSO_TNLTYPE 12
2946 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3
2947 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE)
2948 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \
2949 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE)
2951 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0
2952 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff
2953 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN)
2954 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \
2955 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN)
2957 #define S_CPL_TX_TNL_LSO_FLOW 21
2958 #define M_CPL_TX_TNL_LSO_FLOW 0x1
2959 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW)
2960 #define G_CPL_TX_TNL_LSO_FLOW(x) \
2961 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW)
2962 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U)
2964 #define S_CPL_TX_TNL_LSO_IPV6 20
2965 #define M_CPL_TX_TNL_LSO_IPV6 0x1
2966 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6)
2967 #define G_CPL_TX_TNL_LSO_IPV6(x) \
2968 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6)
2969 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U)
2971 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
2972 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
2973 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
2974 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
2975 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
2977 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4
2978 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff
2979 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN)
2980 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \
2981 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN)
2983 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0
2984 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf
2985 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN)
2986 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \
2987 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN)
2989 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15
2990 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1
2991 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT)
2992 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \
2993 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT)
2994 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U)
2996 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14
2997 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1
2998 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX)
2999 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \
3000 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX)
3001 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U)
3003 #define S_CPL_TX_TNL_LSO_MSS 0
3004 #define M_CPL_TX_TNL_LSO_MSS 0x3fff
3005 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS)
3006 #define G_CPL_TX_TNL_LSO_MSS(x) \
3007 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS)
3009 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28
3010 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf
3011 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \
3012 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET)
3013 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \
3014 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET)
3016 #define S_CPL_TX_TNL_LSO_SIZE 0
3017 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff
3018 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE)
3019 #define G_CPL_TX_TNL_LSO_SIZE(x) \
3020 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE)
3022 struct cpl_rx_mps_pkt {
3024 __be32 r1_lo_length;
3027 #define S_CPL_RX_MPS_PKT_OP 24
3028 #define M_CPL_RX_MPS_PKT_OP 0xff
3029 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP)
3030 #define G_CPL_RX_MPS_PKT_OP(x) \
3031 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP)
3033 #define S_CPL_RX_MPS_PKT_TYPE 20
3034 #define M_CPL_RX_MPS_PKT_TYPE 0xf
3035 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE)
3036 #define G_CPL_RX_MPS_PKT_TYPE(x) \
3037 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE)
3040 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field.
3042 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0)
3043 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1)
3044 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2)
3045 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3)
3047 #endif /* T4_MSG_H */