2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include "opt_inet6.h"
35 #include <sys/param.h>
38 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/counter.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
46 #include <sys/pciio.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pci_private.h>
50 #include <sys/firmware.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_types.h>
59 #include <net/if_dl.h>
60 #include <net/if_vlan_var.h>
62 #include <net/rss_config.h>
64 #if defined(__i386__) || defined(__amd64__)
70 #include <ddb/db_lex.h>
73 #include "common/common.h"
74 #include "common/t4_msg.h"
75 #include "common/t4_regs.h"
76 #include "common/t4_regs_values.h"
79 #include "t4_mp_ring.h"
81 /* T4 bus driver interface */
82 static int t4_probe(device_t);
83 static int t4_attach(device_t);
84 static int t4_detach(device_t);
85 static device_method_t t4_methods[] = {
86 DEVMETHOD(device_probe, t4_probe),
87 DEVMETHOD(device_attach, t4_attach),
88 DEVMETHOD(device_detach, t4_detach),
92 static driver_t t4_driver = {
95 sizeof(struct adapter)
99 /* T4 port (cxgbe) interface */
100 static int cxgbe_probe(device_t);
101 static int cxgbe_attach(device_t);
102 static int cxgbe_detach(device_t);
103 device_method_t cxgbe_methods[] = {
104 DEVMETHOD(device_probe, cxgbe_probe),
105 DEVMETHOD(device_attach, cxgbe_attach),
106 DEVMETHOD(device_detach, cxgbe_detach),
109 static driver_t cxgbe_driver = {
112 sizeof(struct port_info)
115 /* T4 VI (vcxgbe) interface */
116 static int vcxgbe_probe(device_t);
117 static int vcxgbe_attach(device_t);
118 static int vcxgbe_detach(device_t);
119 static device_method_t vcxgbe_methods[] = {
120 DEVMETHOD(device_probe, vcxgbe_probe),
121 DEVMETHOD(device_attach, vcxgbe_attach),
122 DEVMETHOD(device_detach, vcxgbe_detach),
125 static driver_t vcxgbe_driver = {
128 sizeof(struct vi_info)
131 static d_ioctl_t t4_ioctl;
133 static struct cdevsw t4_cdevsw = {
134 .d_version = D_VERSION,
139 /* T5 bus driver interface */
140 static int t5_probe(device_t);
141 static device_method_t t5_methods[] = {
142 DEVMETHOD(device_probe, t5_probe),
143 DEVMETHOD(device_attach, t4_attach),
144 DEVMETHOD(device_detach, t4_detach),
148 static driver_t t5_driver = {
151 sizeof(struct adapter)
155 /* T5 port (cxl) interface */
156 static driver_t cxl_driver = {
159 sizeof(struct port_info)
162 /* T5 VI (vcxl) interface */
163 static driver_t vcxl_driver = {
166 sizeof(struct vi_info)
169 /* ifnet + media interface */
170 static void cxgbe_init(void *);
171 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
172 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
173 static void cxgbe_qflush(struct ifnet *);
174 static int cxgbe_media_change(struct ifnet *);
175 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
177 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
180 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
181 * then ADAPTER_LOCK, then t4_uld_list_lock.
183 static struct sx t4_list_lock;
184 SLIST_HEAD(, adapter) t4_list;
186 static struct sx t4_uld_list_lock;
187 SLIST_HEAD(, uld_info) t4_uld_list;
191 * Tunables. See tweak_tunables() too.
193 * Each tunable is set to a default value here if it's known at compile-time.
194 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
195 * provide a reasonable default when the driver is loaded.
197 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
198 * T5 are under hw.cxl.
202 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
206 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
210 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
214 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
218 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
221 static int t4_ntxq_vi = -1;
222 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
225 static int t4_nrxq_vi = -1;
226 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
228 static int t4_rsrv_noflowq = 0;
229 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
232 #define NOFLDTXQ_10G 8
233 static int t4_nofldtxq10g = -1;
234 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
236 #define NOFLDRXQ_10G 2
237 static int t4_nofldrxq10g = -1;
238 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
240 #define NOFLDTXQ_1G 2
241 static int t4_nofldtxq1g = -1;
242 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
244 #define NOFLDRXQ_1G 1
245 static int t4_nofldrxq1g = -1;
246 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
248 #define NOFLDTXQ_VI 1
249 static int t4_nofldtxq_vi = -1;
250 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
252 #define NOFLDRXQ_VI 1
253 static int t4_nofldrxq_vi = -1;
254 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
259 static int t4_nnmtxq_vi = -1;
260 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
263 static int t4_nnmrxq_vi = -1;
264 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
268 * Holdoff parameters for 10G and 1G ports.
270 #define TMR_IDX_10G 1
271 int t4_tmr_idx_10g = TMR_IDX_10G;
272 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
274 #define PKTC_IDX_10G (-1)
275 int t4_pktc_idx_10g = PKTC_IDX_10G;
276 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
279 int t4_tmr_idx_1g = TMR_IDX_1G;
280 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
282 #define PKTC_IDX_1G (-1)
283 int t4_pktc_idx_1g = PKTC_IDX_1G;
284 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
287 * Size (# of entries) of each tx and rx queue.
289 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
290 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
292 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
293 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
296 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
298 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
299 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
302 * Configuration file.
304 #define DEFAULT_CF "default"
305 #define FLASH_CF "flash"
306 #define UWIRE_CF "uwire"
307 #define FPGA_CF "fpga"
308 static char t4_cfg_file[32] = DEFAULT_CF;
309 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
312 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
313 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
314 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
315 * mark or when signalled to do so, 0 to never emit PAUSE.
317 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
318 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
321 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
322 * encouraged respectively).
324 static unsigned int t4_fw_install = 1;
325 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
328 * ASIC features that will be used. Disable the ones you don't want so that the
329 * chip resources aren't wasted on features that will not be used.
331 static int t4_nbmcaps_allowed = 0;
332 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
334 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
335 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
337 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
338 FW_CAPS_CONFIG_SWITCH_EGRESS;
339 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
341 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
342 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
344 static int t4_toecaps_allowed = -1;
345 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
347 static int t4_rdmacaps_allowed = -1;
348 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
350 static int t4_tlscaps_allowed = 0;
351 TUNABLE_INT("hw.cxgbe.tlscaps_allowed", &t4_tlscaps_allowed);
353 static int t4_iscsicaps_allowed = -1;
354 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
356 static int t4_fcoecaps_allowed = 0;
357 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
359 static int t5_write_combine = 0;
360 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
362 static int t4_num_vis = 1;
363 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
365 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
366 static int vi_mac_funcs[] = {
369 FW_VI_FUNC_OPENISCSI,
375 struct intrs_and_queues {
376 uint16_t intr_type; /* INTx, MSI, or MSI-X */
377 uint16_t nirq; /* Total # of vectors */
378 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
379 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
380 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
381 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
382 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
383 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
384 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
385 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
386 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
387 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
388 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
390 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
391 uint16_t ntxq_vi; /* # of NIC txq's */
392 uint16_t nrxq_vi; /* # of NIC rxq's */
393 uint16_t nofldtxq_vi; /* # of TOE txq's */
394 uint16_t nofldrxq_vi; /* # of TOE rxq's */
395 uint16_t nnmtxq_vi; /* # of netmap txq's */
396 uint16_t nnmrxq_vi; /* # of netmap rxq's */
399 struct filter_entry {
400 uint32_t valid:1; /* filter allocated and valid */
401 uint32_t locked:1; /* filter is administratively locked */
402 uint32_t pending:1; /* filter action is pending firmware reply */
403 uint32_t smtidx:8; /* Source MAC Table index for smac */
404 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
406 struct t4_filter_specification fs;
409 static void setup_memwin(struct adapter *);
410 static void position_memwin(struct adapter *, int, uint32_t);
411 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
412 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
414 static inline int write_via_memwin(struct adapter *, int, uint32_t,
415 const uint32_t *, int);
416 static int validate_mem_range(struct adapter *, uint32_t, int);
417 static int fwmtype_to_hwmtype(int);
418 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
420 static int fixup_devlog_params(struct adapter *);
421 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
422 struct intrs_and_queues *);
423 static int prep_firmware(struct adapter *);
424 static int partition_resources(struct adapter *, const struct firmware *,
426 static int get_params__pre_init(struct adapter *);
427 static int get_params__post_init(struct adapter *);
428 static int set_params__post_init(struct adapter *);
429 static void t4_set_desc(struct adapter *);
430 static void build_medialist(struct port_info *, struct ifmedia *);
431 static int cxgbe_init_synchronized(struct vi_info *);
432 static int cxgbe_uninit_synchronized(struct vi_info *);
433 static void quiesce_txq(struct adapter *, struct sge_txq *);
434 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
435 static void quiesce_iq(struct adapter *, struct sge_iq *);
436 static void quiesce_fl(struct adapter *, struct sge_fl *);
437 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
438 driver_intr_t *, void *, char *);
439 static int t4_free_irq(struct adapter *, struct irq *);
440 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
441 static void vi_refresh_stats(struct adapter *, struct vi_info *);
442 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
443 static void cxgbe_tick(void *);
444 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
445 static void cxgbe_sysctls(struct port_info *);
446 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
447 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
448 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
449 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
450 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
451 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
452 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
453 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
454 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
455 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
456 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
458 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
459 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
460 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
461 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
462 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
463 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
464 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
465 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
466 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
467 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
468 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
469 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
470 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
471 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
472 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
473 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
474 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
475 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
476 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
477 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
478 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
479 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
480 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
481 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
482 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
483 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
484 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
485 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
486 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
489 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
490 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
491 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
493 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
494 static uint32_t mode_to_fconf(uint32_t);
495 static uint32_t mode_to_iconf(uint32_t);
496 static int check_fspec_against_fconf_iconf(struct adapter *,
497 struct t4_filter_specification *);
498 static int get_filter_mode(struct adapter *, uint32_t *);
499 static int set_filter_mode(struct adapter *, uint32_t);
500 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
501 static int get_filter(struct adapter *, struct t4_filter *);
502 static int set_filter(struct adapter *, struct t4_filter *);
503 static int del_filter(struct adapter *, struct t4_filter *);
504 static void clear_filter(struct filter_entry *);
505 static int set_filter_wr(struct adapter *, int);
506 static int del_filter_wr(struct adapter *, int);
507 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
509 static int get_sge_context(struct adapter *, struct t4_sge_context *);
510 static int load_fw(struct adapter *, struct t4_data *);
511 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
512 static int read_i2c(struct adapter *, struct t4_i2c_data *);
514 static int toe_capability(struct vi_info *, int);
516 static int mod_event(module_t, int, void *);
522 {0xa000, "Chelsio Terminator 4 FPGA"},
523 {0x4400, "Chelsio T440-dbg"},
524 {0x4401, "Chelsio T420-CR"},
525 {0x4402, "Chelsio T422-CR"},
526 {0x4403, "Chelsio T440-CR"},
527 {0x4404, "Chelsio T420-BCH"},
528 {0x4405, "Chelsio T440-BCH"},
529 {0x4406, "Chelsio T440-CH"},
530 {0x4407, "Chelsio T420-SO"},
531 {0x4408, "Chelsio T420-CX"},
532 {0x4409, "Chelsio T420-BT"},
533 {0x440a, "Chelsio T404-BT"},
534 {0x440e, "Chelsio T440-LP-CR"},
536 {0xb000, "Chelsio Terminator 5 FPGA"},
537 {0x5400, "Chelsio T580-dbg"},
538 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
539 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
540 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
541 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
542 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
543 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
544 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
545 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
546 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
547 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
548 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
549 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
550 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
552 {0x5404, "Chelsio T520-BCH"},
553 {0x5405, "Chelsio T540-BCH"},
554 {0x5406, "Chelsio T540-CH"},
555 {0x5408, "Chelsio T520-CX"},
556 {0x540b, "Chelsio B520-SR"},
557 {0x540c, "Chelsio B504-BT"},
558 {0x540f, "Chelsio Amsterdam"},
559 {0x5413, "Chelsio T580-CHR"},
565 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
566 * exactly the same for both rxq and ofld_rxq.
568 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
569 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
571 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
574 t4_probe(device_t dev)
577 uint16_t v = pci_get_vendor(dev);
578 uint16_t d = pci_get_device(dev);
579 uint8_t f = pci_get_function(dev);
581 if (v != PCI_VENDOR_ID_CHELSIO)
584 /* Attach only to PF0 of the FPGA */
585 if (d == 0xa000 && f != 0)
588 for (i = 0; i < nitems(t4_pciids); i++) {
589 if (d == t4_pciids[i].device) {
590 device_set_desc(dev, t4_pciids[i].desc);
591 return (BUS_PROBE_DEFAULT);
599 t5_probe(device_t dev)
602 uint16_t v = pci_get_vendor(dev);
603 uint16_t d = pci_get_device(dev);
604 uint8_t f = pci_get_function(dev);
606 if (v != PCI_VENDOR_ID_CHELSIO)
609 /* Attach only to PF0 of the FPGA */
610 if (d == 0xb000 && f != 0)
613 for (i = 0; i < nitems(t5_pciids); i++) {
614 if (d == t5_pciids[i].device) {
615 device_set_desc(dev, t5_pciids[i].desc);
616 return (BUS_PROBE_DEFAULT);
624 t5_attribute_workaround(device_t dev)
630 * The T5 chips do not properly echo the No Snoop and Relaxed
631 * Ordering attributes when replying to a TLP from a Root
632 * Port. As a workaround, find the parent Root Port and
633 * disable No Snoop and Relaxed Ordering. Note that this
634 * affects all devices under this root port.
636 root_port = pci_find_pcie_root_port(dev);
637 if (root_port == NULL) {
638 device_printf(dev, "Unable to find parent root port\n");
642 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
643 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
644 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
646 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
647 device_get_nameunit(root_port));
651 t4_attach(device_t dev)
654 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
655 struct make_dev_args mda;
656 struct intrs_and_queues iaq;
660 int ofld_rqidx, ofld_tqidx;
663 int nm_rqidx, nm_tqidx;
667 sc = device_get_softc(dev);
669 TUNABLE_INT_FETCH("hw.cxgbe.debug_flags", &sc->debug_flags);
671 if ((pci_get_device(dev) & 0xff00) == 0x5400)
672 t5_attribute_workaround(dev);
673 pci_enable_busmaster(dev);
674 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
677 pci_set_max_read_req(dev, 4096);
678 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
679 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
680 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
682 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
685 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
686 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
688 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
689 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
690 device_get_nameunit(dev));
692 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
693 device_get_nameunit(dev));
694 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
697 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
698 TAILQ_INIT(&sc->sfl);
699 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
701 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
703 rc = t4_map_bars_0_and_4(sc);
705 goto done; /* error message displayed already */
708 * This is the real PF# to which we're attaching. Works from within PCI
709 * passthrough environments too, where pci_get_function() could return a
710 * different PF# depending on the passthrough configuration. We need to
711 * use the real PF# in all our communication with the firmware.
713 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
716 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
718 /* Prepare the adapter for operation. */
719 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
720 rc = -t4_prep_adapter(sc, buf);
723 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
728 * Do this really early, with the memory windows set up even before the
729 * character device. The userland tool's register i/o and mem read
730 * will work even in "recovery mode".
733 if (t4_init_devlog_params(sc, 0) == 0)
734 fixup_devlog_params(sc);
735 make_dev_args_init(&mda);
736 mda.mda_devsw = &t4_cdevsw;
737 mda.mda_uid = UID_ROOT;
738 mda.mda_gid = GID_WHEEL;
740 mda.mda_si_drv1 = sc;
741 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
743 device_printf(dev, "failed to create nexus char device: %d.\n",
746 /* Go no further if recovery mode has been requested. */
747 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
748 device_printf(dev, "recovery mode.\n");
752 #if defined(__i386__)
753 if ((cpu_feature & CPUID_CX8) == 0) {
754 device_printf(dev, "64 bit atomics not available.\n");
760 /* Prepare the firmware for operation */
761 rc = prep_firmware(sc);
763 goto done; /* error message displayed already */
765 rc = get_params__post_init(sc);
767 goto done; /* error message displayed already */
769 rc = set_params__post_init(sc);
771 goto done; /* error message displayed already */
773 rc = t4_map_bar_2(sc);
775 goto done; /* error message displayed already */
777 rc = t4_create_dma_tag(sc);
779 goto done; /* error message displayed already */
782 * Number of VIs to create per-port. The first VI is the "main" regular
783 * VI for the port. The rest are additional virtual interfaces on the
784 * same physical port. Note that the main VI does not have native
785 * netmap support but the extra VIs do.
787 * Limit the number of VIs per port to the number of available
788 * MAC addresses per port.
791 num_vis = t4_num_vis;
794 if (num_vis > nitems(vi_mac_funcs)) {
795 num_vis = nitems(vi_mac_funcs);
796 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
800 * First pass over all the ports - allocate VIs and initialize some
801 * basic parameters like mac address, port type, etc. We also figure
802 * out whether a port is 10G or 1G and use that information when
803 * calculating how many interrupts to attempt to allocate.
806 for_each_port(sc, i) {
807 struct port_info *pi;
809 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
812 /* These must be set before t4_port_init */
816 * XXX: vi[0] is special so we can't delay this allocation until
817 * pi->nvi's final value is known.
819 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
823 * Allocate the "main" VI and initialize parameters
826 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
828 device_printf(dev, "unable to initialize port %d: %d\n",
830 free(pi->vi, M_CXGBE);
836 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX);
837 pi->link_cfg.requested_fc |= t4_pause_settings;
838 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX);
839 pi->link_cfg.fc |= t4_pause_settings;
841 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
843 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
844 free(pi->vi, M_CXGBE);
850 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
851 device_get_nameunit(dev), i);
852 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
853 sc->chan_map[pi->tx_chan] = i;
855 pi->tc = malloc(sizeof(struct tx_sched_class) *
856 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
858 if (is_10G_port(pi) || is_40G_port(pi)) {
866 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
867 if (pi->dev == NULL) {
869 "failed to add device for port %d.\n", i);
873 pi->vi[0].dev = pi->dev;
874 device_set_softc(pi->dev, pi);
878 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
880 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
882 goto done; /* error message displayed already */
883 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
886 sc->intr_type = iaq.intr_type;
887 sc->intr_count = iaq.nirq;
890 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
891 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
893 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
894 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
896 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
897 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
898 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
900 if (is_offload(sc)) {
901 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
902 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
904 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
906 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
909 s->neq += s->nofldtxq + s->nofldrxq;
910 s->niq += s->nofldrxq;
912 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
913 M_CXGBE, M_ZERO | M_WAITOK);
914 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
915 M_CXGBE, M_ZERO | M_WAITOK);
920 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
921 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
923 s->neq += s->nnmtxq + s->nnmrxq;
926 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
927 M_CXGBE, M_ZERO | M_WAITOK);
928 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
929 M_CXGBE, M_ZERO | M_WAITOK);
932 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
934 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
936 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
938 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
940 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
943 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
946 t4_init_l2t(sc, M_WAITOK);
949 * Second pass over the ports. This time we know the number of rx and
950 * tx queues that each port should get.
954 ofld_rqidx = ofld_tqidx = 0;
957 nm_rqidx = nm_tqidx = 0;
959 for_each_port(sc, i) {
960 struct port_info *pi = sc->port[i];
967 for_each_vi(pi, j, vi) {
969 vi->qsize_rxq = t4_qsize_rxq;
970 vi->qsize_txq = t4_qsize_txq;
972 vi->first_rxq = rqidx;
973 vi->first_txq = tqidx;
974 if (is_10G_port(pi) || is_40G_port(pi)) {
975 vi->tmr_idx = t4_tmr_idx_10g;
976 vi->pktc_idx = t4_pktc_idx_10g;
977 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
978 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
979 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
981 vi->tmr_idx = t4_tmr_idx_1g;
982 vi->pktc_idx = t4_pktc_idx_1g;
983 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
984 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
985 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
990 if (j == 0 && vi->ntxq > 1)
991 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
993 vi->rsrv_noflowq = 0;
996 vi->first_ofld_rxq = ofld_rqidx;
997 vi->first_ofld_txq = ofld_tqidx;
998 if (is_10G_port(pi) || is_40G_port(pi)) {
999 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1000 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1002 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1005 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1006 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1008 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1011 ofld_rqidx += vi->nofldrxq;
1012 ofld_tqidx += vi->nofldtxq;
1016 vi->first_nm_rxq = nm_rqidx;
1017 vi->first_nm_txq = nm_tqidx;
1018 vi->nnmrxq = iaq.nnmrxq_vi;
1019 vi->nnmtxq = iaq.nnmtxq_vi;
1020 nm_rqidx += vi->nnmrxq;
1021 nm_tqidx += vi->nnmtxq;
1027 rc = t4_setup_intr_handlers(sc);
1030 "failed to setup interrupt handlers: %d\n", rc);
1034 rc = bus_generic_attach(dev);
1037 "failed to attach all child ports: %d\n", rc);
1042 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1043 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1044 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1045 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1046 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1051 if (rc != 0 && sc->cdev) {
1052 /* cdev was created and so cxgbetool works; recover that way. */
1054 "error during attach, adapter is now in recovery mode.\n");
1059 t4_detach_common(dev);
1070 t4_detach(device_t dev)
1074 sc = device_get_softc(dev);
1076 return (t4_detach_common(dev));
1080 t4_detach_common(device_t dev)
1083 struct port_info *pi;
1086 sc = device_get_softc(dev);
1088 if (sc->flags & FULL_INIT_DONE) {
1089 if (!(sc->flags & IS_VF))
1090 t4_intr_disable(sc);
1094 destroy_dev(sc->cdev);
1098 if (device_is_attached(dev)) {
1099 rc = bus_generic_detach(dev);
1102 "failed to detach child devices: %d\n", rc);
1107 for (i = 0; i < sc->intr_count; i++)
1108 t4_free_irq(sc, &sc->irq[i]);
1110 for (i = 0; i < MAX_NPORTS; i++) {
1113 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1115 device_delete_child(dev, pi->dev);
1117 mtx_destroy(&pi->pi_lock);
1118 free(pi->vi, M_CXGBE);
1119 free(pi->tc, M_CXGBE);
1124 if (sc->flags & FULL_INIT_DONE)
1125 adapter_full_uninit(sc);
1127 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1128 t4_fw_bye(sc, sc->mbox);
1130 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1131 pci_release_msi(dev);
1134 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1138 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1142 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1146 t4_free_l2t(sc->l2t);
1149 free(sc->sge.ofld_rxq, M_CXGBE);
1150 free(sc->sge.ofld_txq, M_CXGBE);
1153 free(sc->sge.nm_rxq, M_CXGBE);
1154 free(sc->sge.nm_txq, M_CXGBE);
1156 free(sc->irq, M_CXGBE);
1157 free(sc->sge.rxq, M_CXGBE);
1158 free(sc->sge.txq, M_CXGBE);
1159 free(sc->sge.ctrlq, M_CXGBE);
1160 free(sc->sge.iqmap, M_CXGBE);
1161 free(sc->sge.eqmap, M_CXGBE);
1162 free(sc->tids.ftid_tab, M_CXGBE);
1163 t4_destroy_dma_tag(sc);
1164 if (mtx_initialized(&sc->sc_lock)) {
1165 sx_xlock(&t4_list_lock);
1166 SLIST_REMOVE(&t4_list, sc, adapter, link);
1167 sx_xunlock(&t4_list_lock);
1168 mtx_destroy(&sc->sc_lock);
1171 callout_drain(&sc->sfl_callout);
1172 if (mtx_initialized(&sc->tids.ftid_lock))
1173 mtx_destroy(&sc->tids.ftid_lock);
1174 if (mtx_initialized(&sc->sfl_lock))
1175 mtx_destroy(&sc->sfl_lock);
1176 if (mtx_initialized(&sc->ifp_lock))
1177 mtx_destroy(&sc->ifp_lock);
1178 if (mtx_initialized(&sc->reg_lock))
1179 mtx_destroy(&sc->reg_lock);
1181 for (i = 0; i < NUM_MEMWIN; i++) {
1182 struct memwin *mw = &sc->memwin[i];
1184 if (rw_initialized(&mw->mw_lock))
1185 rw_destroy(&mw->mw_lock);
1188 bzero(sc, sizeof(*sc));
1194 cxgbe_probe(device_t dev)
1197 struct port_info *pi = device_get_softc(dev);
1199 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1200 device_set_desc_copy(dev, buf);
1202 return (BUS_PROBE_DEFAULT);
1205 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1206 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1207 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1208 #define T4_CAP_ENABLE (T4_CAP)
1211 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1216 vi->xact_addr_filt = -1;
1217 callout_init(&vi->tick, 1);
1219 /* Allocate an ifnet and set it up */
1220 ifp = if_alloc(IFT_ETHER);
1222 device_printf(dev, "Cannot allocate ifnet\n");
1228 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1229 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1231 ifp->if_init = cxgbe_init;
1232 ifp->if_ioctl = cxgbe_ioctl;
1233 ifp->if_transmit = cxgbe_transmit;
1234 ifp->if_qflush = cxgbe_qflush;
1236 ifp->if_capabilities = T4_CAP;
1238 if (vi->nofldrxq != 0)
1239 ifp->if_capabilities |= IFCAP_TOE;
1241 ifp->if_capenable = T4_CAP_ENABLE;
1242 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1243 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1245 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1246 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1247 ifp->if_hw_tsomaxsegsize = 65536;
1249 /* Initialize ifmedia for this VI */
1250 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change,
1251 cxgbe_media_status);
1252 build_medialist(vi->pi, &vi->media);
1254 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1255 EVENTHANDLER_PRI_ANY);
1257 ether_ifattach(ifp, vi->hw_addr);
1259 if (vi->nnmrxq != 0)
1260 cxgbe_nm_attach(vi);
1262 sb = sbuf_new_auto();
1263 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1265 if (ifp->if_capabilities & IFCAP_TOE)
1266 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1267 vi->nofldtxq, vi->nofldrxq);
1270 if (ifp->if_capabilities & IFCAP_NETMAP)
1271 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1272 vi->nnmtxq, vi->nnmrxq);
1275 device_printf(dev, "%s\n", sbuf_data(sb));
1284 cxgbe_attach(device_t dev)
1286 struct port_info *pi = device_get_softc(dev);
1290 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1292 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1296 for_each_vi(pi, i, vi) {
1299 vi->dev = device_add_child(dev, is_t4(pi->adapter) ?
1300 "vcxgbe" : "vcxl", -1);
1301 if (vi->dev == NULL) {
1302 device_printf(dev, "failed to add VI %d\n", i);
1305 device_set_softc(vi->dev, vi);
1310 bus_generic_attach(dev);
1316 cxgbe_vi_detach(struct vi_info *vi)
1318 struct ifnet *ifp = vi->ifp;
1320 ether_ifdetach(ifp);
1323 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1325 /* Let detach proceed even if these fail. */
1327 if (ifp->if_capabilities & IFCAP_NETMAP)
1328 cxgbe_nm_detach(vi);
1330 cxgbe_uninit_synchronized(vi);
1331 callout_drain(&vi->tick);
1334 ifmedia_removeall(&vi->media);
1340 cxgbe_detach(device_t dev)
1342 struct port_info *pi = device_get_softc(dev);
1343 struct adapter *sc = pi->adapter;
1346 /* Detach the extra VIs first. */
1347 rc = bus_generic_detach(dev);
1350 device_delete_children(dev);
1352 doom_vi(sc, &pi->vi[0]);
1354 if (pi->flags & HAS_TRACEQ) {
1355 sc->traceq = -1; /* cloner should not create ifnet */
1356 t4_tracer_port_detach(sc);
1359 cxgbe_vi_detach(&pi->vi[0]);
1360 callout_drain(&pi->tick);
1362 end_synchronized_op(sc, 0);
1368 cxgbe_init(void *arg)
1370 struct vi_info *vi = arg;
1371 struct adapter *sc = vi->pi->adapter;
1373 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1375 cxgbe_init_synchronized(vi);
1376 end_synchronized_op(sc, 0);
1380 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1382 int rc = 0, mtu, flags, can_sleep;
1383 struct vi_info *vi = ifp->if_softc;
1384 struct adapter *sc = vi->pi->adapter;
1385 struct ifreq *ifr = (struct ifreq *)data;
1391 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1394 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1398 if (vi->flags & VI_INIT_DONE) {
1399 t4_update_fl_bufsize(ifp);
1400 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1401 rc = update_mac_settings(ifp, XGMAC_MTU);
1403 end_synchronized_op(sc, 0);
1409 rc = begin_synchronized_op(sc, vi,
1410 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1414 if (ifp->if_flags & IFF_UP) {
1415 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1416 flags = vi->if_flags;
1417 if ((ifp->if_flags ^ flags) &
1418 (IFF_PROMISC | IFF_ALLMULTI)) {
1419 if (can_sleep == 1) {
1420 end_synchronized_op(sc, 0);
1424 rc = update_mac_settings(ifp,
1425 XGMAC_PROMISC | XGMAC_ALLMULTI);
1428 if (can_sleep == 0) {
1429 end_synchronized_op(sc, LOCK_HELD);
1433 rc = cxgbe_init_synchronized(vi);
1435 vi->if_flags = ifp->if_flags;
1436 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1437 if (can_sleep == 0) {
1438 end_synchronized_op(sc, LOCK_HELD);
1442 rc = cxgbe_uninit_synchronized(vi);
1444 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1448 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1449 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1452 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1453 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1454 end_synchronized_op(sc, LOCK_HELD);
1458 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1462 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1463 if (mask & IFCAP_TXCSUM) {
1464 ifp->if_capenable ^= IFCAP_TXCSUM;
1465 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1467 if (IFCAP_TSO4 & ifp->if_capenable &&
1468 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1469 ifp->if_capenable &= ~IFCAP_TSO4;
1471 "tso4 disabled due to -txcsum.\n");
1474 if (mask & IFCAP_TXCSUM_IPV6) {
1475 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1476 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1478 if (IFCAP_TSO6 & ifp->if_capenable &&
1479 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1480 ifp->if_capenable &= ~IFCAP_TSO6;
1482 "tso6 disabled due to -txcsum6.\n");
1485 if (mask & IFCAP_RXCSUM)
1486 ifp->if_capenable ^= IFCAP_RXCSUM;
1487 if (mask & IFCAP_RXCSUM_IPV6)
1488 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1491 * Note that we leave CSUM_TSO alone (it is always set). The
1492 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1493 * sending a TSO request our way, so it's sufficient to toggle
1496 if (mask & IFCAP_TSO4) {
1497 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1498 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1499 if_printf(ifp, "enable txcsum first.\n");
1503 ifp->if_capenable ^= IFCAP_TSO4;
1505 if (mask & IFCAP_TSO6) {
1506 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1507 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1508 if_printf(ifp, "enable txcsum6 first.\n");
1512 ifp->if_capenable ^= IFCAP_TSO6;
1514 if (mask & IFCAP_LRO) {
1515 #if defined(INET) || defined(INET6)
1517 struct sge_rxq *rxq;
1519 ifp->if_capenable ^= IFCAP_LRO;
1520 for_each_rxq(vi, i, rxq) {
1521 if (ifp->if_capenable & IFCAP_LRO)
1522 rxq->iq.flags |= IQ_LRO_ENABLED;
1524 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1529 if (mask & IFCAP_TOE) {
1530 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1532 rc = toe_capability(vi, enable);
1536 ifp->if_capenable ^= mask;
1539 if (mask & IFCAP_VLAN_HWTAGGING) {
1540 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1541 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1542 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1544 if (mask & IFCAP_VLAN_MTU) {
1545 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1547 /* Need to find out how to disable auto-mtu-inflation */
1549 if (mask & IFCAP_VLAN_HWTSO)
1550 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1551 if (mask & IFCAP_VLAN_HWCSUM)
1552 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1554 #ifdef VLAN_CAPABILITIES
1555 VLAN_CAPABILITIES(ifp);
1558 end_synchronized_op(sc, 0);
1563 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1567 struct ifi2creq i2c;
1569 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1572 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1576 if (i2c.len > sizeof(i2c.data)) {
1580 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1583 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr,
1584 i2c.offset, i2c.len, &i2c.data[0]);
1585 end_synchronized_op(sc, 0);
1587 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1592 rc = ether_ioctl(ifp, cmd, data);
1599 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1601 struct vi_info *vi = ifp->if_softc;
1602 struct port_info *pi = vi->pi;
1603 struct adapter *sc = pi->adapter;
1604 struct sge_txq *txq;
1609 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1611 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1616 rc = parse_pkt(sc, &m);
1617 if (__predict_false(rc != 0)) {
1618 MPASS(m == NULL); /* was freed already */
1619 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1624 txq = &sc->sge.txq[vi->first_txq];
1625 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1626 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1630 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1631 if (__predict_false(rc != 0))
1638 cxgbe_qflush(struct ifnet *ifp)
1640 struct vi_info *vi = ifp->if_softc;
1641 struct sge_txq *txq;
1644 /* queues do not exist if !VI_INIT_DONE. */
1645 if (vi->flags & VI_INIT_DONE) {
1646 for_each_txq(vi, i, txq) {
1648 txq->eq.flags &= ~EQ_ENABLED;
1650 while (!mp_ring_is_idle(txq->r)) {
1651 mp_ring_check_drainage(txq->r, 0);
1660 cxgbe_media_change(struct ifnet *ifp)
1662 struct vi_info *vi = ifp->if_softc;
1664 device_printf(vi->dev, "%s unimplemented.\n", __func__);
1666 return (EOPNOTSUPP);
1670 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1672 struct vi_info *vi = ifp->if_softc;
1673 struct port_info *pi = vi->pi;
1674 struct ifmedia_entry *cur;
1675 int speed = pi->link_cfg.speed;
1677 cur = vi->media.ifm_cur;
1679 ifmr->ifm_status = IFM_AVALID;
1680 if (!pi->link_cfg.link_ok)
1683 ifmr->ifm_status |= IFM_ACTIVE;
1685 /* active and current will differ iff current media is autoselect. */
1686 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1689 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1691 ifmr->ifm_active |= IFM_10G_T;
1692 else if (speed == 1000)
1693 ifmr->ifm_active |= IFM_1000_T;
1694 else if (speed == 100)
1695 ifmr->ifm_active |= IFM_100_TX;
1696 else if (speed == 10)
1697 ifmr->ifm_active |= IFM_10_T;
1699 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1704 vcxgbe_probe(device_t dev)
1707 struct vi_info *vi = device_get_softc(dev);
1709 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
1711 device_set_desc_copy(dev, buf);
1713 return (BUS_PROBE_DEFAULT);
1717 vcxgbe_attach(device_t dev)
1720 struct port_info *pi;
1722 int func, index, rc;
1725 vi = device_get_softc(dev);
1729 index = vi - pi->vi;
1730 KASSERT(index < nitems(vi_mac_funcs),
1731 ("%s: VI %s doesn't have a MAC func", __func__,
1732 device_get_nameunit(dev)));
1733 func = vi_mac_funcs[index];
1734 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1735 vi->hw_addr, &vi->rss_size, func, 0);
1737 device_printf(dev, "Failed to allocate virtual interface "
1738 "for port %d: %d\n", pi->port_id, -rc);
1743 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1744 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1745 V_FW_PARAMS_PARAM_YZ(vi->viid);
1746 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
1748 vi->rss_base = 0xffff;
1750 /* MPASS((val >> 16) == rss_size); */
1751 vi->rss_base = val & 0xffff;
1754 rc = cxgbe_vi_attach(dev, vi);
1756 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1763 vcxgbe_detach(device_t dev)
1768 vi = device_get_softc(dev);
1769 sc = vi->pi->adapter;
1773 cxgbe_vi_detach(vi);
1774 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1776 end_synchronized_op(sc, 0);
1782 t4_fatal_err(struct adapter *sc)
1784 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1785 t4_intr_disable(sc);
1786 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1787 device_get_nameunit(sc->dev));
1791 t4_add_adapter(struct adapter *sc)
1793 sx_xlock(&t4_list_lock);
1794 SLIST_INSERT_HEAD(&t4_list, sc, link);
1795 sx_xunlock(&t4_list_lock);
1799 t4_map_bars_0_and_4(struct adapter *sc)
1801 sc->regs_rid = PCIR_BAR(0);
1802 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1803 &sc->regs_rid, RF_ACTIVE);
1804 if (sc->regs_res == NULL) {
1805 device_printf(sc->dev, "cannot map registers.\n");
1808 sc->bt = rman_get_bustag(sc->regs_res);
1809 sc->bh = rman_get_bushandle(sc->regs_res);
1810 sc->mmio_len = rman_get_size(sc->regs_res);
1811 setbit(&sc->doorbells, DOORBELL_KDB);
1813 sc->msix_rid = PCIR_BAR(4);
1814 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1815 &sc->msix_rid, RF_ACTIVE);
1816 if (sc->msix_res == NULL) {
1817 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1825 t4_map_bar_2(struct adapter *sc)
1829 * T4: only iWARP driver uses the userspace doorbells. There is no need
1830 * to map it if RDMA is disabled.
1832 if (is_t4(sc) && sc->rdmacaps == 0)
1835 sc->udbs_rid = PCIR_BAR(2);
1836 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1837 &sc->udbs_rid, RF_ACTIVE);
1838 if (sc->udbs_res == NULL) {
1839 device_printf(sc->dev, "cannot map doorbell BAR.\n");
1842 sc->udbs_base = rman_get_virtual(sc->udbs_res);
1845 setbit(&sc->doorbells, DOORBELL_UDB);
1846 #if defined(__i386__) || defined(__amd64__)
1847 if (t5_write_combine) {
1851 * Enable write combining on BAR2. This is the
1852 * userspace doorbell BAR and is split into 128B
1853 * (UDBS_SEG_SIZE) doorbell regions, each associated
1854 * with an egress queue. The first 64B has the doorbell
1855 * and the second 64B can be used to submit a tx work
1856 * request with an implicit doorbell.
1859 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
1860 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
1862 clrbit(&sc->doorbells, DOORBELL_UDB);
1863 setbit(&sc->doorbells, DOORBELL_WCWR);
1864 setbit(&sc->doorbells, DOORBELL_UDBWC);
1866 device_printf(sc->dev,
1867 "couldn't enable write combining: %d\n",
1871 t4_write_reg(sc, A_SGE_STAT_CFG,
1872 V_STATSOURCE_T5(7) | V_STATMODE(0));
1880 struct memwin_init {
1885 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
1886 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1887 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1888 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
1891 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
1892 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1893 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1894 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
1898 setup_memwin(struct adapter *sc)
1900 const struct memwin_init *mw_init;
1907 * Read low 32b of bar0 indirectly via the hardware backdoor
1908 * mechanism. Works from within PCI passthrough environments
1909 * too, where rman_get_start() can return a different value. We
1910 * need to program the T4 memory window decoders with the actual
1911 * addresses that will be coming across the PCIe link.
1913 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
1914 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
1916 mw_init = &t4_memwin[0];
1918 /* T5+ use the relative offset inside the PCIe BAR */
1921 mw_init = &t5_memwin[0];
1924 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
1925 rw_init(&mw->mw_lock, "memory window access");
1926 mw->mw_base = mw_init->base;
1927 mw->mw_aperture = mw_init->aperture;
1930 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
1931 (mw->mw_base + bar0) | V_BIR(0) |
1932 V_WINDOW(ilog2(mw->mw_aperture) - 10));
1933 rw_wlock(&mw->mw_lock);
1934 position_memwin(sc, i, 0);
1935 rw_wunlock(&mw->mw_lock);
1939 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
1943 * Positions the memory window at the given address in the card's address space.
1944 * There are some alignment requirements and the actual position may be at an
1945 * address prior to the requested address. mw->mw_curpos always has the actual
1946 * position of the window.
1949 position_memwin(struct adapter *sc, int idx, uint32_t addr)
1955 MPASS(idx >= 0 && idx < NUM_MEMWIN);
1956 mw = &sc->memwin[idx];
1957 rw_assert(&mw->mw_lock, RA_WLOCKED);
1961 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
1963 pf = V_PFNUM(sc->pf);
1964 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
1966 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
1967 t4_write_reg(sc, reg, mw->mw_curpos | pf);
1968 t4_read_reg(sc, reg); /* flush */
1972 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1978 MPASS(idx >= 0 && idx < NUM_MEMWIN);
1980 /* Memory can only be accessed in naturally aligned 4 byte units */
1981 if (addr & 3 || len & 3 || len <= 0)
1984 mw = &sc->memwin[idx];
1986 rw_rlock(&mw->mw_lock);
1987 mw_end = mw->mw_curpos + mw->mw_aperture;
1988 if (addr >= mw_end || addr < mw->mw_curpos) {
1989 /* Will need to reposition the window */
1990 if (!rw_try_upgrade(&mw->mw_lock)) {
1991 rw_runlock(&mw->mw_lock);
1992 rw_wlock(&mw->mw_lock);
1994 rw_assert(&mw->mw_lock, RA_WLOCKED);
1995 position_memwin(sc, idx, addr);
1996 rw_downgrade(&mw->mw_lock);
1997 mw_end = mw->mw_curpos + mw->mw_aperture;
1999 rw_assert(&mw->mw_lock, RA_RLOCKED);
2000 while (addr < mw_end && len > 0) {
2002 v = t4_read_reg(sc, mw->mw_base + addr -
2004 *val++ = le32toh(v);
2007 t4_write_reg(sc, mw->mw_base + addr -
2008 mw->mw_curpos, htole32(v));;
2013 rw_runlock(&mw->mw_lock);
2020 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2024 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2028 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2029 const uint32_t *val, int len)
2032 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2036 t4_range_cmp(const void *a, const void *b)
2038 return ((const struct t4_range *)a)->start -
2039 ((const struct t4_range *)b)->start;
2043 * Verify that the memory range specified by the addr/len pair is valid within
2044 * the card's address space.
2047 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2049 struct t4_range mem_ranges[4], *r, *next;
2050 uint32_t em, addr_len;
2051 int i, n, remaining;
2053 /* Memory can only be accessed in naturally aligned 4 byte units */
2054 if (addr & 3 || len & 3 || len <= 0)
2057 /* Enabled memories */
2058 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2062 bzero(r, sizeof(mem_ranges));
2063 if (em & F_EDRAM0_ENABLE) {
2064 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2065 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2067 r->start = G_EDRAM0_BASE(addr_len) << 20;
2068 if (addr >= r->start &&
2069 addr + len <= r->start + r->size)
2075 if (em & F_EDRAM1_ENABLE) {
2076 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2077 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2079 r->start = G_EDRAM1_BASE(addr_len) << 20;
2080 if (addr >= r->start &&
2081 addr + len <= r->start + r->size)
2087 if (em & F_EXT_MEM_ENABLE) {
2088 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2089 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2091 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2092 if (addr >= r->start &&
2093 addr + len <= r->start + r->size)
2099 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2100 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2101 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2103 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2104 if (addr >= r->start &&
2105 addr + len <= r->start + r->size)
2111 MPASS(n <= nitems(mem_ranges));
2114 /* Sort and merge the ranges. */
2115 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2117 /* Start from index 0 and examine the next n - 1 entries. */
2119 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2121 MPASS(r->size > 0); /* r is a valid entry. */
2123 MPASS(next->size > 0); /* and so is the next one. */
2125 while (r->start + r->size >= next->start) {
2126 /* Merge the next one into the current entry. */
2127 r->size = max(r->start + r->size,
2128 next->start + next->size) - r->start;
2129 n--; /* One fewer entry in total. */
2130 if (--remaining == 0)
2131 goto done; /* short circuit */
2134 if (next != r + 1) {
2136 * Some entries were merged into r and next
2137 * points to the first valid entry that couldn't
2140 MPASS(next->size > 0); /* must be valid */
2141 memcpy(r + 1, next, remaining * sizeof(*r));
2144 * This so that the foo->size assertion in the
2145 * next iteration of the loop do the right
2146 * thing for entries that were pulled up and are
2149 MPASS(n < nitems(mem_ranges));
2150 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2151 sizeof(struct t4_range));
2156 /* Done merging the ranges. */
2159 for (i = 0; i < n; i++, r++) {
2160 if (addr >= r->start &&
2161 addr + len <= r->start + r->size)
2170 fwmtype_to_hwmtype(int mtype)
2174 case FW_MEMTYPE_EDC0:
2176 case FW_MEMTYPE_EDC1:
2178 case FW_MEMTYPE_EXTMEM:
2180 case FW_MEMTYPE_EXTMEM1:
2183 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2188 * Verify that the memory range specified by the memtype/offset/len pair is
2189 * valid and lies entirely within the memtype specified. The global address of
2190 * the start of the range is returned in addr.
2193 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2196 uint32_t em, addr_len, maddr;
2198 /* Memory can only be accessed in naturally aligned 4 byte units */
2199 if (off & 3 || len & 3 || len == 0)
2202 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2203 switch (fwmtype_to_hwmtype(mtype)) {
2205 if (!(em & F_EDRAM0_ENABLE))
2207 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2208 maddr = G_EDRAM0_BASE(addr_len) << 20;
2211 if (!(em & F_EDRAM1_ENABLE))
2213 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2214 maddr = G_EDRAM1_BASE(addr_len) << 20;
2217 if (!(em & F_EXT_MEM_ENABLE))
2219 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2220 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2223 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2225 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2226 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2232 *addr = maddr + off; /* global address */
2233 return (validate_mem_range(sc, *addr, len));
2237 fixup_devlog_params(struct adapter *sc)
2239 struct devlog_params *dparams = &sc->params.devlog;
2242 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2243 dparams->size, &dparams->addr);
2249 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2250 struct intrs_and_queues *iaq)
2252 int rc, itype, navail, nrxq10g, nrxq1g, n;
2253 int nofldrxq10g = 0, nofldrxq1g = 0;
2255 bzero(iaq, sizeof(*iaq));
2257 iaq->ntxq10g = t4_ntxq10g;
2258 iaq->ntxq1g = t4_ntxq1g;
2259 iaq->ntxq_vi = t4_ntxq_vi;
2260 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2261 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2262 iaq->nrxq_vi = t4_nrxq_vi;
2263 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2265 if (is_offload(sc)) {
2266 iaq->nofldtxq10g = t4_nofldtxq10g;
2267 iaq->nofldtxq1g = t4_nofldtxq1g;
2268 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2269 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2270 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2271 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2275 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2276 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2279 for (itype = INTR_MSIX; itype; itype >>= 1) {
2281 if ((itype & t4_intr_types) == 0)
2282 continue; /* not allowed */
2284 if (itype == INTR_MSIX)
2285 navail = pci_msix_count(sc->dev);
2286 else if (itype == INTR_MSI)
2287 navail = pci_msi_count(sc->dev);
2294 iaq->intr_type = itype;
2295 iaq->intr_flags_10g = 0;
2296 iaq->intr_flags_1g = 0;
2299 * Best option: an interrupt vector for errors, one for the
2300 * firmware event queue, and one for every rxq (NIC and TOE) of
2301 * every VI. The VIs that support netmap use the same
2302 * interrupts for the NIC rx queues and the netmap rx queues
2303 * because only one set of queues is active at a time.
2305 iaq->nirq = T4_EXTRA_INTR;
2306 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2307 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2308 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2309 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2310 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2311 if (iaq->nirq <= navail &&
2312 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2313 iaq->intr_flags_10g = INTR_ALL;
2314 iaq->intr_flags_1g = INTR_ALL;
2318 /* Disable the VIs (and netmap) if there aren't enough intrs */
2320 device_printf(sc->dev, "virtual interfaces disabled "
2321 "because num_vis=%u with current settings "
2322 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2323 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2324 "nnmrxq_vi=%u) would need %u interrupts but "
2325 "only %u are available.\n", num_vis, nrxq10g,
2326 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2327 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2330 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2331 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2332 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2337 * Second best option: a vector for errors, one for the firmware
2338 * event queue, and vectors for either all the NIC rx queues or
2339 * all the TOE rx queues. The queues that don't get vectors
2340 * will forward their interrupts to those that do.
2342 iaq->nirq = T4_EXTRA_INTR;
2343 if (nrxq10g >= nofldrxq10g) {
2344 iaq->intr_flags_10g = INTR_RXQ;
2345 iaq->nirq += n10g * nrxq10g;
2347 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2348 iaq->nirq += n10g * nofldrxq10g;
2350 if (nrxq1g >= nofldrxq1g) {
2351 iaq->intr_flags_1g = INTR_RXQ;
2352 iaq->nirq += n1g * nrxq1g;
2354 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2355 iaq->nirq += n1g * nofldrxq1g;
2357 if (iaq->nirq <= navail &&
2358 (itype != INTR_MSI || powerof2(iaq->nirq)))
2362 * Next best option: an interrupt vector for errors, one for the
2363 * firmware event queue, and at least one per main-VI. At this
2364 * point we know we'll have to downsize nrxq and/or nofldrxq to
2365 * fit what's available to us.
2367 iaq->nirq = T4_EXTRA_INTR;
2368 iaq->nirq += n10g + n1g;
2369 if (iaq->nirq <= navail) {
2370 int leftover = navail - iaq->nirq;
2373 int target = max(nrxq10g, nofldrxq10g);
2375 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2376 INTR_RXQ : INTR_OFLD_RXQ;
2379 while (n < target && leftover >= n10g) {
2384 iaq->nrxq10g = min(n, nrxq10g);
2386 iaq->nofldrxq10g = min(n, nofldrxq10g);
2391 int target = max(nrxq1g, nofldrxq1g);
2393 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2394 INTR_RXQ : INTR_OFLD_RXQ;
2397 while (n < target && leftover >= n1g) {
2402 iaq->nrxq1g = min(n, nrxq1g);
2404 iaq->nofldrxq1g = min(n, nofldrxq1g);
2408 if (itype != INTR_MSI || powerof2(iaq->nirq))
2413 * Least desirable option: one interrupt vector for everything.
2415 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2416 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2419 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2424 if (itype == INTR_MSIX)
2425 rc = pci_alloc_msix(sc->dev, &navail);
2426 else if (itype == INTR_MSI)
2427 rc = pci_alloc_msi(sc->dev, &navail);
2430 if (navail == iaq->nirq)
2434 * Didn't get the number requested. Use whatever number
2435 * the kernel is willing to allocate (it's in navail).
2437 device_printf(sc->dev, "fewer vectors than requested, "
2438 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2439 itype, iaq->nirq, navail);
2440 pci_release_msi(sc->dev);
2444 device_printf(sc->dev,
2445 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2446 itype, rc, iaq->nirq, navail);
2449 device_printf(sc->dev,
2450 "failed to find a usable interrupt type. "
2451 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2452 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2457 #define FW_VERSION(chip) ( \
2458 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2459 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2460 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2461 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2462 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2468 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2472 .kld_name = "t4fw_cfg",
2473 .fw_mod_name = "t4fw",
2475 .chip = FW_HDR_CHIP_T4,
2476 .fw_ver = htobe32_const(FW_VERSION(T4)),
2477 .intfver_nic = FW_INTFVER(T4, NIC),
2478 .intfver_vnic = FW_INTFVER(T4, VNIC),
2479 .intfver_ofld = FW_INTFVER(T4, OFLD),
2480 .intfver_ri = FW_INTFVER(T4, RI),
2481 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2482 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2483 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2484 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2488 .kld_name = "t5fw_cfg",
2489 .fw_mod_name = "t5fw",
2491 .chip = FW_HDR_CHIP_T5,
2492 .fw_ver = htobe32_const(FW_VERSION(T5)),
2493 .intfver_nic = FW_INTFVER(T5, NIC),
2494 .intfver_vnic = FW_INTFVER(T5, VNIC),
2495 .intfver_ofld = FW_INTFVER(T5, OFLD),
2496 .intfver_ri = FW_INTFVER(T5, RI),
2497 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2498 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2499 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2500 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2505 static struct fw_info *
2506 find_fw_info(int chip)
2510 for (i = 0; i < nitems(fw_info); i++) {
2511 if (fw_info[i].chip == chip)
2512 return (&fw_info[i]);
2518 * Is the given firmware API compatible with the one the driver was compiled
2522 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2525 /* short circuit if it's the exact same firmware version */
2526 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2530 * XXX: Is this too conservative? Perhaps I should limit this to the
2531 * features that are supported in the driver.
2533 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2534 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2535 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2536 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2544 * The firmware in the KLD is usable, but should it be installed? This routine
2545 * explains itself in detail if it indicates the KLD firmware should be
2549 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2553 if (!card_fw_usable) {
2554 reason = "incompatible or unusable";
2559 reason = "older than the version bundled with this driver";
2563 if (t4_fw_install == 2 && k != c) {
2564 reason = "different than the version bundled with this driver";
2571 if (t4_fw_install == 0) {
2572 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2573 "but the driver is prohibited from installing a different "
2574 "firmware on the card.\n",
2575 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2576 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2581 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2582 "installing firmware %u.%u.%u.%u on card.\n",
2583 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2584 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2585 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2586 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2591 * Establish contact with the firmware and determine if we are the master driver
2592 * or not, and whether we are responsible for chip initialization.
2595 prep_firmware(struct adapter *sc)
2597 const struct firmware *fw = NULL, *default_cfg;
2598 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2599 enum dev_state state;
2600 struct fw_info *fw_info;
2601 struct fw_hdr *card_fw; /* fw on the card */
2602 const struct fw_hdr *kld_fw; /* fw in the KLD */
2603 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2606 /* Contact firmware. */
2607 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2608 if (rc < 0 || state == DEV_STATE_ERR) {
2610 device_printf(sc->dev,
2611 "failed to connect to the firmware: %d, %d.\n", rc, state);
2616 sc->flags |= MASTER_PF;
2617 else if (state == DEV_STATE_UNINIT) {
2619 * We didn't get to be the master so we definitely won't be
2620 * configuring the chip. It's a bug if someone else hasn't
2621 * configured it already.
2623 device_printf(sc->dev, "couldn't be master(%d), "
2624 "device not already initialized either(%d).\n", rc, state);
2628 /* This is the firmware whose headers the driver was compiled against */
2629 fw_info = find_fw_info(chip_id(sc));
2630 if (fw_info == NULL) {
2631 device_printf(sc->dev,
2632 "unable to look up firmware information for chip %d.\n",
2636 drv_fw = &fw_info->fw_hdr;
2639 * The firmware KLD contains many modules. The KLD name is also the
2640 * name of the module that contains the default config file.
2642 default_cfg = firmware_get(fw_info->kld_name);
2644 /* Read the header of the firmware on the card */
2645 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2646 rc = -t4_read_flash(sc, FLASH_FW_START,
2647 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2649 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2651 device_printf(sc->dev,
2652 "Unable to read card's firmware header: %d\n", rc);
2656 /* This is the firmware in the KLD */
2657 fw = firmware_get(fw_info->fw_mod_name);
2659 kld_fw = (const void *)fw->data;
2660 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2666 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2667 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2669 * Common case: the firmware on the card is an exact match and
2670 * the KLD is an exact match too, or the KLD is
2671 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2672 * here -- use cxgbetool loadfw if you want to reinstall the
2673 * same firmware as the one on the card.
2675 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2676 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2677 be32toh(card_fw->fw_ver))) {
2679 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2681 device_printf(sc->dev,
2682 "failed to install firmware: %d\n", rc);
2686 /* Installed successfully, update the cached header too. */
2687 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2689 need_fw_reset = 0; /* already reset as part of load_fw */
2692 if (!card_fw_usable) {
2695 d = ntohl(drv_fw->fw_ver);
2696 c = ntohl(card_fw->fw_ver);
2697 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2699 device_printf(sc->dev, "Cannot find a usable firmware: "
2700 "fw_install %d, chip state %d, "
2701 "driver compiled with %d.%d.%d.%d, "
2702 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2703 t4_fw_install, state,
2704 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2705 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2706 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2707 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2708 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2709 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2714 /* We're using whatever's on the card and it's known to be good. */
2715 sc->params.fw_vers = ntohl(card_fw->fw_ver);
2716 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
2717 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
2718 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
2719 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
2720 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
2722 t4_get_tp_version(sc, &sc->params.tp_vers);
2723 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
2724 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
2725 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
2726 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
2727 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
2729 if (t4_get_exprom_version(sc, &sc->params.exprom_vers) != 0)
2730 sc->params.exprom_vers = 0;
2732 snprintf(sc->exprom_version, sizeof(sc->exprom_version),
2734 G_FW_HDR_FW_VER_MAJOR(sc->params.exprom_vers),
2735 G_FW_HDR_FW_VER_MINOR(sc->params.exprom_vers),
2736 G_FW_HDR_FW_VER_MICRO(sc->params.exprom_vers),
2737 G_FW_HDR_FW_VER_BUILD(sc->params.exprom_vers));
2741 if (need_fw_reset &&
2742 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2743 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2744 if (rc != ETIMEDOUT && rc != EIO)
2745 t4_fw_bye(sc, sc->mbox);
2750 rc = get_params__pre_init(sc);
2752 goto done; /* error message displayed already */
2754 /* Partition adapter resources as specified in the config file. */
2755 if (state == DEV_STATE_UNINIT) {
2757 KASSERT(sc->flags & MASTER_PF,
2758 ("%s: trying to change chip settings when not master.",
2761 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2763 goto done; /* error message displayed already */
2765 t4_tweak_chip_settings(sc);
2767 /* get basic stuff going */
2768 rc = -t4_fw_initialize(sc, sc->mbox);
2770 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2774 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2779 free(card_fw, M_CXGBE);
2781 firmware_put(fw, FIRMWARE_UNLOAD);
2782 if (default_cfg != NULL)
2783 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2788 #define FW_PARAM_DEV(param) \
2789 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2790 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2791 #define FW_PARAM_PFVF(param) \
2792 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2793 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2796 * Partition chip resources for use between various PFs, VFs, etc.
2799 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2800 const char *name_prefix)
2802 const struct firmware *cfg = NULL;
2804 struct fw_caps_config_cmd caps;
2805 uint32_t mtype, moff, finicsum, cfcsum;
2808 * Figure out what configuration file to use. Pick the default config
2809 * file for the card if the user hasn't specified one explicitly.
2811 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2812 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2813 /* Card specific overrides go here. */
2814 if (pci_get_device(sc->dev) == 0x440a)
2815 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2817 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2821 * We need to load another module if the profile is anything except
2822 * "default" or "flash".
2824 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2825 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2828 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2829 cfg = firmware_get(s);
2831 if (default_cfg != NULL) {
2832 device_printf(sc->dev,
2833 "unable to load module \"%s\" for "
2834 "configuration profile \"%s\", will use "
2835 "the default config file instead.\n",
2837 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2840 device_printf(sc->dev,
2841 "unable to load module \"%s\" for "
2842 "configuration profile \"%s\", will use "
2843 "the config file on the card's flash "
2844 "instead.\n", s, sc->cfg_file);
2845 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2851 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2852 default_cfg == NULL) {
2853 device_printf(sc->dev,
2854 "default config file not available, will use the config "
2855 "file on the card's flash instead.\n");
2856 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
2859 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2861 const uint32_t *cfdata;
2862 uint32_t param, val, addr;
2864 KASSERT(cfg != NULL || default_cfg != NULL,
2865 ("%s: no config to upload", __func__));
2868 * Ask the firmware where it wants us to upload the config file.
2870 param = FW_PARAM_DEV(CF);
2871 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2873 /* No support for config file? Shouldn't happen. */
2874 device_printf(sc->dev,
2875 "failed to query config file location: %d.\n", rc);
2878 mtype = G_FW_PARAMS_PARAM_Y(val);
2879 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
2882 * XXX: sheer laziness. We deliberately added 4 bytes of
2883 * useless stuffing/comments at the end of the config file so
2884 * it's ok to simply throw away the last remaining bytes when
2885 * the config file is not an exact multiple of 4. This also
2886 * helps with the validate_mt_off_len check.
2889 cflen = cfg->datasize & ~3;
2892 cflen = default_cfg->datasize & ~3;
2893 cfdata = default_cfg->data;
2896 if (cflen > FLASH_CFG_MAX_SIZE) {
2897 device_printf(sc->dev,
2898 "config file too long (%d, max allowed is %d). "
2899 "Will try to use the config on the card, if any.\n",
2900 cflen, FLASH_CFG_MAX_SIZE);
2901 goto use_config_on_flash;
2904 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
2906 device_printf(sc->dev,
2907 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
2908 "Will try to use the config on the card, if any.\n",
2909 __func__, mtype, moff, cflen, rc);
2910 goto use_config_on_flash;
2912 write_via_memwin(sc, 2, addr, cfdata, cflen);
2914 use_config_on_flash:
2915 mtype = FW_MEMTYPE_FLASH;
2916 moff = t4_flash_cfg_addr(sc);
2919 bzero(&caps, sizeof(caps));
2920 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2921 F_FW_CMD_REQUEST | F_FW_CMD_READ);
2922 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
2923 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
2924 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
2925 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
2927 device_printf(sc->dev,
2928 "failed to pre-process config file: %d "
2929 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
2933 finicsum = be32toh(caps.finicsum);
2934 cfcsum = be32toh(caps.cfcsum);
2935 if (finicsum != cfcsum) {
2936 device_printf(sc->dev,
2937 "WARNING: config file checksum mismatch: %08x %08x\n",
2940 sc->cfcsum = cfcsum;
2942 #define LIMIT_CAPS(x) do { \
2943 caps.x &= htobe16(t4_##x##_allowed); \
2947 * Let the firmware know what features will (not) be used so it can tune
2948 * things accordingly.
2950 LIMIT_CAPS(nbmcaps);
2951 LIMIT_CAPS(linkcaps);
2952 LIMIT_CAPS(switchcaps);
2953 LIMIT_CAPS(niccaps);
2954 LIMIT_CAPS(toecaps);
2955 LIMIT_CAPS(rdmacaps);
2956 LIMIT_CAPS(tlscaps);
2957 LIMIT_CAPS(iscsicaps);
2958 LIMIT_CAPS(fcoecaps);
2961 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2962 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
2963 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
2964 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
2966 device_printf(sc->dev,
2967 "failed to process config file: %d.\n", rc);
2971 firmware_put(cfg, FIRMWARE_UNLOAD);
2976 * Retrieve parameters that are needed (or nice to have) very early.
2979 get_params__pre_init(struct adapter *sc)
2982 uint32_t param[2], val[2];
2984 param[0] = FW_PARAM_DEV(PORTVEC);
2985 param[1] = FW_PARAM_DEV(CCLK);
2986 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
2988 device_printf(sc->dev,
2989 "failed to query parameters (pre_init): %d.\n", rc);
2993 sc->params.portvec = val[0];
2994 sc->params.nports = bitcount32(val[0]);
2995 sc->params.vpd.cclk = val[1];
2997 /* Read device log parameters. */
2998 rc = -t4_init_devlog_params(sc, 1);
3000 fixup_devlog_params(sc);
3002 device_printf(sc->dev,
3003 "failed to get devlog parameters: %d.\n", rc);
3004 rc = 0; /* devlog isn't critical for device operation */
3011 * Retrieve various parameters that are of interest to the driver. The device
3012 * has been initialized by the firmware at this point.
3015 get_params__post_init(struct adapter *sc)
3018 uint32_t param[7], val[7];
3019 struct fw_caps_config_cmd caps;
3021 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3022 param[1] = FW_PARAM_PFVF(EQ_START);
3023 param[2] = FW_PARAM_PFVF(FILTER_START);
3024 param[3] = FW_PARAM_PFVF(FILTER_END);
3025 param[4] = FW_PARAM_PFVF(L2T_START);
3026 param[5] = FW_PARAM_PFVF(L2T_END);
3027 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3029 device_printf(sc->dev,
3030 "failed to query parameters (post_init): %d.\n", rc);
3034 sc->sge.iq_start = val[0];
3035 sc->sge.eq_start = val[1];
3036 sc->tids.ftid_base = val[2];
3037 sc->tids.nftids = val[3] - val[2] + 1;
3038 sc->params.ftid_min = val[2];
3039 sc->params.ftid_max = val[3];
3040 sc->vres.l2t.start = val[4];
3041 sc->vres.l2t.size = val[5] - val[4] + 1;
3042 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3043 ("%s: L2 table size (%u) larger than expected (%u)",
3044 __func__, sc->vres.l2t.size, L2T_SIZE));
3046 /* get capabilites */
3047 bzero(&caps, sizeof(caps));
3048 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3049 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3050 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3051 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3053 device_printf(sc->dev,
3054 "failed to get card capabilities: %d.\n", rc);
3058 #define READ_CAPS(x) do { \
3059 sc->x = htobe16(caps.x); \
3062 READ_CAPS(linkcaps);
3063 READ_CAPS(switchcaps);
3066 READ_CAPS(rdmacaps);
3068 READ_CAPS(iscsicaps);
3069 READ_CAPS(fcoecaps);
3071 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3072 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3073 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3074 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3075 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3077 device_printf(sc->dev,
3078 "failed to query NIC parameters: %d.\n", rc);
3081 sc->tids.etid_base = val[0];
3082 sc->params.etid_min = val[0];
3083 sc->tids.netids = val[1] - val[0] + 1;
3084 sc->params.netids = sc->tids.netids;
3085 sc->params.eo_wr_cred = val[2];
3086 sc->params.ethoffload = 1;
3090 /* query offload-related parameters */
3091 param[0] = FW_PARAM_DEV(NTID);
3092 param[1] = FW_PARAM_PFVF(SERVER_START);
3093 param[2] = FW_PARAM_PFVF(SERVER_END);
3094 param[3] = FW_PARAM_PFVF(TDDP_START);
3095 param[4] = FW_PARAM_PFVF(TDDP_END);
3096 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3097 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3099 device_printf(sc->dev,
3100 "failed to query TOE parameters: %d.\n", rc);
3103 sc->tids.ntids = val[0];
3104 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3105 sc->tids.stid_base = val[1];
3106 sc->tids.nstids = val[2] - val[1] + 1;
3107 sc->vres.ddp.start = val[3];
3108 sc->vres.ddp.size = val[4] - val[3] + 1;
3109 sc->params.ofldq_wr_cred = val[5];
3110 sc->params.offload = 1;
3113 param[0] = FW_PARAM_PFVF(STAG_START);
3114 param[1] = FW_PARAM_PFVF(STAG_END);
3115 param[2] = FW_PARAM_PFVF(RQ_START);
3116 param[3] = FW_PARAM_PFVF(RQ_END);
3117 param[4] = FW_PARAM_PFVF(PBL_START);
3118 param[5] = FW_PARAM_PFVF(PBL_END);
3119 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3121 device_printf(sc->dev,
3122 "failed to query RDMA parameters(1): %d.\n", rc);
3125 sc->vres.stag.start = val[0];
3126 sc->vres.stag.size = val[1] - val[0] + 1;
3127 sc->vres.rq.start = val[2];
3128 sc->vres.rq.size = val[3] - val[2] + 1;
3129 sc->vres.pbl.start = val[4];
3130 sc->vres.pbl.size = val[5] - val[4] + 1;
3132 param[0] = FW_PARAM_PFVF(SQRQ_START);
3133 param[1] = FW_PARAM_PFVF(SQRQ_END);
3134 param[2] = FW_PARAM_PFVF(CQ_START);
3135 param[3] = FW_PARAM_PFVF(CQ_END);
3136 param[4] = FW_PARAM_PFVF(OCQ_START);
3137 param[5] = FW_PARAM_PFVF(OCQ_END);
3138 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3140 device_printf(sc->dev,
3141 "failed to query RDMA parameters(2): %d.\n", rc);
3144 sc->vres.qp.start = val[0];
3145 sc->vres.qp.size = val[1] - val[0] + 1;
3146 sc->vres.cq.start = val[2];
3147 sc->vres.cq.size = val[3] - val[2] + 1;
3148 sc->vres.ocq.start = val[4];
3149 sc->vres.ocq.size = val[5] - val[4] + 1;
3151 if (sc->iscsicaps) {
3152 param[0] = FW_PARAM_PFVF(ISCSI_START);
3153 param[1] = FW_PARAM_PFVF(ISCSI_END);
3154 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3156 device_printf(sc->dev,
3157 "failed to query iSCSI parameters: %d.\n", rc);
3160 sc->vres.iscsi.start = val[0];
3161 sc->vres.iscsi.size = val[1] - val[0] + 1;
3164 t4_init_sge_params(sc);
3167 * We've got the params we wanted to query via the firmware. Now grab
3168 * some others directly from the chip.
3170 rc = t4_read_chip_settings(sc);
3176 set_params__post_init(struct adapter *sc)
3178 uint32_t param, val;
3180 /* ask for encapsulated CPLs */
3181 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3183 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3188 #undef FW_PARAM_PFVF
3192 t4_set_desc(struct adapter *sc)
3195 struct adapter_params *p = &sc->params;
3197 snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, "
3198 "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "",
3199 chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec);
3201 device_set_desc_copy(sc->dev, buf);
3205 build_medialist(struct port_info *pi, struct ifmedia *media)
3211 ifmedia_removeall(media);
3213 m = IFM_ETHER | IFM_FDX;
3215 switch(pi->port_type) {
3216 case FW_PORT_TYPE_BT_XFI:
3217 case FW_PORT_TYPE_BT_XAUI:
3218 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3221 case FW_PORT_TYPE_BT_SGMII:
3222 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3223 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3224 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3225 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3228 case FW_PORT_TYPE_CX4:
3229 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3230 ifmedia_set(media, m | IFM_10G_CX4);
3233 case FW_PORT_TYPE_QSFP_10G:
3234 case FW_PORT_TYPE_SFP:
3235 case FW_PORT_TYPE_FIBER_XFI:
3236 case FW_PORT_TYPE_FIBER_XAUI:
3237 switch (pi->mod_type) {
3239 case FW_PORT_MOD_TYPE_LR:
3240 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3241 ifmedia_set(media, m | IFM_10G_LR);
3244 case FW_PORT_MOD_TYPE_SR:
3245 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3246 ifmedia_set(media, m | IFM_10G_SR);
3249 case FW_PORT_MOD_TYPE_LRM:
3250 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3251 ifmedia_set(media, m | IFM_10G_LRM);
3254 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3255 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3256 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3257 ifmedia_set(media, m | IFM_10G_TWINAX);
3260 case FW_PORT_MOD_TYPE_NONE:
3262 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3263 ifmedia_set(media, m | IFM_NONE);
3266 case FW_PORT_MOD_TYPE_NA:
3267 case FW_PORT_MOD_TYPE_ER:
3269 device_printf(pi->dev,
3270 "unknown port_type (%d), mod_type (%d)\n",
3271 pi->port_type, pi->mod_type);
3272 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3273 ifmedia_set(media, m | IFM_UNKNOWN);
3278 case FW_PORT_TYPE_QSFP:
3279 switch (pi->mod_type) {
3281 case FW_PORT_MOD_TYPE_LR:
3282 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3283 ifmedia_set(media, m | IFM_40G_LR4);
3286 case FW_PORT_MOD_TYPE_SR:
3287 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3288 ifmedia_set(media, m | IFM_40G_SR4);
3291 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3292 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3293 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3294 ifmedia_set(media, m | IFM_40G_CR4);
3297 case FW_PORT_MOD_TYPE_NONE:
3299 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3300 ifmedia_set(media, m | IFM_NONE);
3304 device_printf(pi->dev,
3305 "unknown port_type (%d), mod_type (%d)\n",
3306 pi->port_type, pi->mod_type);
3307 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3308 ifmedia_set(media, m | IFM_UNKNOWN);
3314 device_printf(pi->dev,
3315 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3317 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3318 ifmedia_set(media, m | IFM_UNKNOWN);
3325 #define FW_MAC_EXACT_CHUNK 7
3328 * Program the port's XGMAC based on parameters in ifnet. The caller also
3329 * indicates which parameters should be programmed (the rest are left alone).
3332 update_mac_settings(struct ifnet *ifp, int flags)
3335 struct vi_info *vi = ifp->if_softc;
3336 struct port_info *pi = vi->pi;
3337 struct adapter *sc = pi->adapter;
3338 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3340 ASSERT_SYNCHRONIZED_OP(sc);
3341 KASSERT(flags, ("%s: not told what to update.", __func__));
3343 if (flags & XGMAC_MTU)
3346 if (flags & XGMAC_PROMISC)
3347 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3349 if (flags & XGMAC_ALLMULTI)
3350 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3352 if (flags & XGMAC_VLANEX)
3353 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3355 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3356 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3357 allmulti, 1, vlanex, false);
3359 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3365 if (flags & XGMAC_UCADDR) {
3366 uint8_t ucaddr[ETHER_ADDR_LEN];
3368 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3369 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3370 ucaddr, true, true);
3373 if_printf(ifp, "change_mac failed: %d\n", rc);
3376 vi->xact_addr_filt = rc;
3381 if (flags & XGMAC_MCADDRS) {
3382 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3385 struct ifmultiaddr *ifma;
3388 if_maddr_rlock(ifp);
3389 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3390 if (ifma->ifma_addr->sa_family != AF_LINK)
3393 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3394 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3397 if (i == FW_MAC_EXACT_CHUNK) {
3398 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3399 del, i, mcaddr, NULL, &hash, 0);
3402 for (j = 0; j < i; j++) {
3404 "failed to add mc address"
3406 "%02x:%02x:%02x rc=%d\n",
3407 mcaddr[j][0], mcaddr[j][1],
3408 mcaddr[j][2], mcaddr[j][3],
3409 mcaddr[j][4], mcaddr[j][5],
3419 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3420 mcaddr, NULL, &hash, 0);
3423 for (j = 0; j < i; j++) {
3425 "failed to add mc address"
3427 "%02x:%02x:%02x rc=%d\n",
3428 mcaddr[j][0], mcaddr[j][1],
3429 mcaddr[j][2], mcaddr[j][3],
3430 mcaddr[j][4], mcaddr[j][5],
3437 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3439 if_printf(ifp, "failed to set mc address hash: %d", rc);
3441 if_maddr_runlock(ifp);
3448 * {begin|end}_synchronized_op must be called from the same thread.
3451 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3457 /* the caller thinks it's ok to sleep, but is it really? */
3458 if (flags & SLEEP_OK)
3459 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3460 "begin_synchronized_op");
3471 if (vi && IS_DOOMED(vi)) {
3481 if (!(flags & SLEEP_OK)) {
3486 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3492 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3495 sc->last_op = wmesg;
3496 sc->last_op_thr = curthread;
3497 sc->last_op_flags = flags;
3501 if (!(flags & HOLD_LOCK) || rc)
3508 * Tell if_ioctl and if_init that the VI is going away. This is
3509 * special variant of begin_synchronized_op and must be paired with a
3510 * call to end_synchronized_op.
3513 doom_vi(struct adapter *sc, struct vi_info *vi)
3520 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3523 sc->last_op = "t4detach";
3524 sc->last_op_thr = curthread;
3525 sc->last_op_flags = 0;
3531 * {begin|end}_synchronized_op must be called from the same thread.
3534 end_synchronized_op(struct adapter *sc, int flags)
3537 if (flags & LOCK_HELD)
3538 ADAPTER_LOCK_ASSERT_OWNED(sc);
3542 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3549 cxgbe_init_synchronized(struct vi_info *vi)
3551 struct port_info *pi = vi->pi;
3552 struct adapter *sc = pi->adapter;
3553 struct ifnet *ifp = vi->ifp;
3555 struct sge_txq *txq;
3557 ASSERT_SYNCHRONIZED_OP(sc);
3559 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3560 return (0); /* already running */
3562 if (!(sc->flags & FULL_INIT_DONE) &&
3563 ((rc = adapter_full_init(sc)) != 0))
3564 return (rc); /* error message displayed already */
3566 if (!(vi->flags & VI_INIT_DONE) &&
3567 ((rc = vi_full_init(vi)) != 0))
3568 return (rc); /* error message displayed already */
3570 rc = update_mac_settings(ifp, XGMAC_ALL);
3572 goto done; /* error message displayed already */
3574 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
3576 if_printf(ifp, "enable_vi failed: %d\n", rc);
3581 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
3585 for_each_txq(vi, i, txq) {
3587 txq->eq.flags |= EQ_ENABLED;
3592 * The first iq of the first port to come up is used for tracing.
3594 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
3595 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
3596 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
3597 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3598 V_QUEUENUMBER(sc->traceq));
3599 pi->flags |= HAS_TRACEQ;
3604 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3607 if (pi->nvi > 1 || sc->flags & IS_VF)
3608 callout_reset(&vi->tick, hz, vi_tick, vi);
3610 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3614 cxgbe_uninit_synchronized(vi);
3623 cxgbe_uninit_synchronized(struct vi_info *vi)
3625 struct port_info *pi = vi->pi;
3626 struct adapter *sc = pi->adapter;
3627 struct ifnet *ifp = vi->ifp;
3629 struct sge_txq *txq;
3631 ASSERT_SYNCHRONIZED_OP(sc);
3633 if (!(vi->flags & VI_INIT_DONE)) {
3634 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
3635 ("uninited VI is running"));
3640 * Disable the VI so that all its data in either direction is discarded
3641 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
3642 * tick) intact as the TP can deliver negative advice or data that it's
3643 * holding in its RAM (for an offloaded connection) even after the VI is
3646 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
3648 if_printf(ifp, "disable_vi failed: %d\n", rc);
3652 for_each_txq(vi, i, txq) {
3654 txq->eq.flags &= ~EQ_ENABLED;
3659 if (pi->nvi > 1 || sc->flags & IS_VF)
3660 callout_stop(&vi->tick);
3662 callout_stop(&pi->tick);
3663 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3667 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3669 if (pi->up_vis > 0) {
3675 pi->link_cfg.link_ok = 0;
3676 pi->link_cfg.speed = 0;
3678 t4_os_link_changed(sc, pi->port_id, 0, -1);
3684 * It is ok for this function to fail midway and return right away. t4_detach
3685 * will walk the entire sc->irq list and clean up whatever is valid.
3688 t4_setup_intr_handlers(struct adapter *sc)
3690 int rc, rid, p, q, v;
3693 struct port_info *pi;
3695 struct sge *sge = &sc->sge;
3696 struct sge_rxq *rxq;
3698 struct sge_ofld_rxq *ofld_rxq;
3701 struct sge_nm_rxq *nm_rxq;
3708 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3709 if (sc->intr_count == 1)
3710 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3712 /* Multiple interrupts. */
3713 if (sc->flags & IS_VF)
3714 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
3715 ("%s: too few intr.", __func__));
3717 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3718 ("%s: too few intr.", __func__));
3720 /* The first one is always error intr on PFs */
3721 if (!(sc->flags & IS_VF)) {
3722 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3729 /* The second one is always the firmware event queue (first on VFs) */
3730 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
3736 for_each_port(sc, p) {
3738 for_each_vi(pi, v, vi) {
3739 vi->first_intr = rid - 1;
3741 if (vi->nnmrxq > 0) {
3742 int n = max(vi->nrxq, vi->nnmrxq);
3744 MPASS(vi->flags & INTR_RXQ);
3746 rxq = &sge->rxq[vi->first_rxq];
3748 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
3750 for (q = 0; q < n; q++) {
3751 snprintf(s, sizeof(s), "%x%c%x", p,
3757 irq->nm_rxq = nm_rxq++;
3759 rc = t4_alloc_irq(sc, irq, rid,
3760 t4_vi_intr, irq, s);
3767 } else if (vi->flags & INTR_RXQ) {
3768 for_each_rxq(vi, q, rxq) {
3769 snprintf(s, sizeof(s), "%x%c%x", p,
3771 rc = t4_alloc_irq(sc, irq, rid,
3781 if (vi->flags & INTR_OFLD_RXQ) {
3782 for_each_ofld_rxq(vi, q, ofld_rxq) {
3783 snprintf(s, sizeof(s), "%x%c%x", p,
3785 rc = t4_alloc_irq(sc, irq, rid,
3786 t4_intr, ofld_rxq, s);
3797 MPASS(irq == &sc->irq[sc->intr_count]);
3803 adapter_full_init(struct adapter *sc)
3807 ASSERT_SYNCHRONIZED_OP(sc);
3808 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3809 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3810 ("%s: FULL_INIT_DONE already", __func__));
3813 * queues that belong to the adapter (not any particular port).
3815 rc = t4_setup_adapter_queues(sc);
3819 for (i = 0; i < nitems(sc->tq); i++) {
3820 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
3821 taskqueue_thread_enqueue, &sc->tq[i]);
3822 if (sc->tq[i] == NULL) {
3823 device_printf(sc->dev,
3824 "failed to allocate task queue %d\n", i);
3828 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
3829 device_get_nameunit(sc->dev), i);
3832 if (!(sc->flags & IS_VF))
3834 sc->flags |= FULL_INIT_DONE;
3837 adapter_full_uninit(sc);
3843 adapter_full_uninit(struct adapter *sc)
3847 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3849 t4_teardown_adapter_queues(sc);
3851 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
3852 taskqueue_free(sc->tq[i]);
3856 sc->flags &= ~FULL_INIT_DONE;
3862 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
3863 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
3864 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
3865 RSS_HASHTYPE_RSS_UDP_IPV6)
3867 /* Translates kernel hash types to hardware. */
3869 hashconfig_to_hashen(int hashconfig)
3873 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
3874 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
3875 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
3876 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
3877 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
3878 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
3879 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
3881 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
3882 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
3883 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
3885 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
3886 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
3887 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
3888 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
3893 /* Translates hardware hash types to kernel. */
3895 hashen_to_hashconfig(int hashen)
3899 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
3901 * If UDP hashing was enabled it must have been enabled for
3902 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
3903 * enabling any 4-tuple hash is nonsense configuration.
3905 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
3906 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
3908 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3909 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
3910 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3911 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
3913 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3914 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
3915 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3916 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
3917 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3918 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
3919 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3920 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
3922 return (hashconfig);
3927 vi_full_init(struct vi_info *vi)
3929 struct adapter *sc = vi->pi->adapter;
3930 struct ifnet *ifp = vi->ifp;
3932 struct sge_rxq *rxq;
3933 int rc, i, j, hashen;
3935 int nbuckets = rss_getnumbuckets();
3936 int hashconfig = rss_gethashconfig();
3938 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3939 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3942 ASSERT_SYNCHRONIZED_OP(sc);
3943 KASSERT((vi->flags & VI_INIT_DONE) == 0,
3944 ("%s: VI_INIT_DONE already", __func__));
3946 sysctl_ctx_init(&vi->ctx);
3947 vi->flags |= VI_SYSCTL_CTX;
3950 * Allocate tx/rx/fl queues for this VI.
3952 rc = t4_setup_vi_queues(vi);
3954 goto done; /* error message displayed already */
3957 * Setup RSS for this VI. Save a copy of the RSS table for later use.
3959 if (vi->nrxq > vi->rss_size) {
3960 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
3961 "some queues will never receive traffic.\n", vi->nrxq,
3963 } else if (vi->rss_size % vi->nrxq) {
3964 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
3965 "expect uneven traffic distribution.\n", vi->nrxq,
3969 MPASS(RSS_KEYSIZE == 40);
3970 if (vi->nrxq != nbuckets) {
3971 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
3972 "performance will be impacted.\n", vi->nrxq, nbuckets);
3975 rss_getkey((void *)&raw_rss_key[0]);
3976 for (i = 0; i < nitems(rss_key); i++) {
3977 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
3979 t4_write_rss_key(sc, &rss_key[0], -1);
3981 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
3982 for (i = 0; i < vi->rss_size;) {
3984 j = rss_get_indirection_to_bucket(i);
3986 rxq = &sc->sge.rxq[vi->first_rxq + j];
3987 rss[i++] = rxq->iq.abs_id;
3989 for_each_rxq(vi, j, rxq) {
3990 rss[i++] = rxq->iq.abs_id;
3991 if (i == vi->rss_size)
3997 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
4000 if_printf(ifp, "rss_config failed: %d\n", rc);
4005 hashen = hashconfig_to_hashen(hashconfig);
4008 * We may have had to enable some hashes even though the global config
4009 * wants them disabled. This is a potential problem that must be
4010 * reported to the user.
4012 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4015 * If we consider only the supported hash types, then the enabled hashes
4016 * are a superset of the requested hashes. In other words, there cannot
4017 * be any supported hash that was requested but not enabled, but there
4018 * can be hashes that were not requested but had to be enabled.
4020 extra &= SUPPORTED_RSS_HASHTYPES;
4021 MPASS((extra & hashconfig) == 0);
4025 "global RSS config (0x%x) cannot be accomodated.\n",
4028 if (extra & RSS_HASHTYPE_RSS_IPV4)
4029 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4030 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4031 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4032 if (extra & RSS_HASHTYPE_RSS_IPV6)
4033 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4034 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4035 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4036 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4037 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4038 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4039 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4041 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4042 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4043 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4044 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4046 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
4048 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4053 vi->flags |= VI_INIT_DONE;
4065 vi_full_uninit(struct vi_info *vi)
4067 struct port_info *pi = vi->pi;
4068 struct adapter *sc = pi->adapter;
4070 struct sge_rxq *rxq;
4071 struct sge_txq *txq;
4073 struct sge_ofld_rxq *ofld_rxq;
4074 struct sge_wrq *ofld_txq;
4077 if (vi->flags & VI_INIT_DONE) {
4079 /* Need to quiesce queues. */
4081 /* XXX: Only for the first VI? */
4082 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
4083 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4085 for_each_txq(vi, i, txq) {
4086 quiesce_txq(sc, txq);
4090 for_each_ofld_txq(vi, i, ofld_txq) {
4091 quiesce_wrq(sc, ofld_txq);
4095 for_each_rxq(vi, i, rxq) {
4096 quiesce_iq(sc, &rxq->iq);
4097 quiesce_fl(sc, &rxq->fl);
4101 for_each_ofld_rxq(vi, i, ofld_rxq) {
4102 quiesce_iq(sc, &ofld_rxq->iq);
4103 quiesce_fl(sc, &ofld_rxq->fl);
4106 free(vi->rss, M_CXGBE);
4107 free(vi->nm_rss, M_CXGBE);
4110 t4_teardown_vi_queues(vi);
4111 vi->flags &= ~VI_INIT_DONE;
4117 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4119 struct sge_eq *eq = &txq->eq;
4120 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4122 (void) sc; /* unused */
4126 MPASS((eq->flags & EQ_ENABLED) == 0);
4130 /* Wait for the mp_ring to empty. */
4131 while (!mp_ring_is_idle(txq->r)) {
4132 mp_ring_check_drainage(txq->r, 0);
4133 pause("rquiesce", 1);
4136 /* Then wait for the hardware to finish. */
4137 while (spg->cidx != htobe16(eq->pidx))
4138 pause("equiesce", 1);
4140 /* Finally, wait for the driver to reclaim all descriptors. */
4141 while (eq->cidx != eq->pidx)
4142 pause("dquiesce", 1);
4146 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4153 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4155 (void) sc; /* unused */
4157 /* Synchronize with the interrupt handler */
4158 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4163 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4165 mtx_lock(&sc->sfl_lock);
4167 fl->flags |= FL_DOOMED;
4169 callout_stop(&sc->sfl_callout);
4170 mtx_unlock(&sc->sfl_lock);
4172 KASSERT((fl->flags & FL_STARVING) == 0,
4173 ("%s: still starving", __func__));
4177 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4178 driver_intr_t *handler, void *arg, char *name)
4183 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4184 RF_SHAREABLE | RF_ACTIVE);
4185 if (irq->res == NULL) {
4186 device_printf(sc->dev,
4187 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4191 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4192 NULL, handler, arg, &irq->tag);
4194 device_printf(sc->dev,
4195 "failed to setup interrupt for rid %d, name %s: %d\n",
4198 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
4204 t4_free_irq(struct adapter *sc, struct irq *irq)
4207 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4209 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4211 bzero(irq, sizeof(*irq));
4217 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4220 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4221 t4_get_regs(sc, buf, regs->len);
4224 #define A_PL_INDIR_CMD 0x1f8
4226 #define S_PL_AUTOINC 31
4227 #define M_PL_AUTOINC 0x1U
4228 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4229 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4231 #define S_PL_VFID 20
4232 #define M_PL_VFID 0xffU
4233 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4234 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4237 #define M_PL_ADDR 0xfffffU
4238 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4239 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4241 #define A_PL_INDIR_DATA 0x1fc
4244 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4248 mtx_assert(&sc->reg_lock, MA_OWNED);
4249 if (sc->flags & IS_VF) {
4250 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
4251 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
4253 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4254 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4255 V_PL_ADDR(VF_MPS_REG(reg)));
4256 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4257 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4259 return (((uint64_t)stats[1]) << 32 | stats[0]);
4263 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4264 struct fw_vi_stats_vf *stats)
4267 #define GET_STAT(name) \
4268 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4270 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4271 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4272 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4273 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4274 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4275 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4276 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4277 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4278 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4279 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4280 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4281 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4282 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4283 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4284 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4285 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4291 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4295 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4296 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4297 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4298 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4299 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4300 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4304 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4306 struct ifnet *ifp = vi->ifp;
4307 struct sge_txq *txq;
4309 struct fw_vi_stats_vf *s = &vi->stats;
4311 const struct timeval interval = {0, 250000}; /* 250ms */
4313 if (!(vi->flags & VI_INIT_DONE))
4317 timevalsub(&tv, &interval);
4318 if (timevalcmp(&tv, &vi->last_refreshed, <))
4321 mtx_lock(&sc->reg_lock);
4322 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4324 ifp->if_ipackets = s->rx_bcast_frames + s->rx_mcast_frames +
4326 ifp->if_ierrors = s->rx_err_frames;
4327 ifp->if_opackets = s->tx_bcast_frames + s->tx_mcast_frames +
4328 s->tx_ucast_frames + s->tx_offload_frames;
4329 ifp->if_oerrors = s->tx_drop_frames;
4330 ifp->if_ibytes = s->rx_bcast_bytes + s->rx_mcast_bytes +
4332 ifp->if_obytes = s->tx_bcast_bytes + s->tx_mcast_bytes +
4333 s->tx_ucast_bytes + s->tx_offload_bytes;
4334 ifp->if_imcasts = s->rx_mcast_frames;
4335 ifp->if_omcasts = s->tx_mcast_frames;
4338 for_each_txq(vi, i, txq)
4339 drops += counter_u64_fetch(txq->r->drops);
4340 ifp->if_snd.ifq_drops = drops;
4342 getmicrotime(&vi->last_refreshed);
4343 mtx_unlock(&sc->reg_lock);
4347 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4349 struct vi_info *vi = &pi->vi[0];
4350 struct ifnet *ifp = vi->ifp;
4351 struct sge_txq *txq;
4353 struct port_stats *s = &pi->stats;
4355 const struct timeval interval = {0, 250000}; /* 250ms */
4358 timevalsub(&tv, &interval);
4359 if (timevalcmp(&tv, &pi->last_refreshed, <))
4362 t4_get_port_stats(sc, pi->tx_chan, s);
4364 ifp->if_opackets = s->tx_frames;
4365 ifp->if_ipackets = s->rx_frames;
4366 ifp->if_obytes = s->tx_octets;
4367 ifp->if_ibytes = s->rx_octets;
4368 ifp->if_omcasts = s->tx_mcast_frames;
4369 ifp->if_imcasts = s->rx_mcast_frames;
4370 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4371 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4373 for (i = 0; i < sc->chip_params->nchan; i++) {
4374 if (pi->rx_chan_map & (1 << i)) {
4377 mtx_lock(&sc->reg_lock);
4378 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4379 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4380 mtx_unlock(&sc->reg_lock);
4381 ifp->if_iqdrops += v;
4386 for_each_txq(vi, i, txq)
4387 drops += counter_u64_fetch(txq->r->drops);
4388 ifp->if_snd.ifq_drops = drops;
4390 ifp->if_oerrors = s->tx_error_frames;
4391 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4392 s->rx_fcs_err + s->rx_len_err;
4394 getmicrotime(&pi->last_refreshed);
4398 cxgbe_tick(void *arg)
4400 struct port_info *pi = arg;
4401 struct adapter *sc = pi->adapter;
4403 PORT_LOCK_ASSERT_OWNED(pi);
4404 cxgbe_refresh_stats(sc, pi);
4406 callout_schedule(&pi->tick, hz);
4412 struct vi_info *vi = arg;
4413 struct adapter *sc = vi->pi->adapter;
4415 vi_refresh_stats(sc, vi);
4417 callout_schedule(&vi->tick, hz);
4421 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4425 if (arg != ifp || ifp->if_type != IFT_ETHER)
4428 vlan = VLAN_DEVAT(ifp, vid);
4429 VLAN_SETCOOKIE(vlan, ifp);
4433 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4435 static char *caps_decoder[] = {
4436 "\20\001IPMI\002NCSI", /* 0: NBM */
4437 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4438 "\20\001INGRESS\002EGRESS", /* 2: switch */
4439 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4440 "\006HASHFILTER\007ETHOFLD",
4441 "\20\001TOE", /* 4: TOE */
4442 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4443 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4444 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4445 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4447 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4448 "\20\00KEYS", /* 7: TLS */
4449 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4450 "\004PO_INITIATOR\005PO_TARGET",
4454 t4_sysctls(struct adapter *sc)
4456 struct sysctl_ctx_list *ctx;
4457 struct sysctl_oid *oid;
4458 struct sysctl_oid_list *children, *c0;
4459 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4461 ctx = device_get_sysctl_ctx(sc->dev);
4466 oid = device_get_sysctl_tree(sc->dev);
4467 c0 = children = SYSCTL_CHILDREN(oid);
4469 sc->sc_do_rxcopy = 1;
4470 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4471 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4473 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4474 sc->params.nports, "# of ports");
4476 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4477 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4478 sysctl_bitfield, "A", "available doorbells");
4480 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4481 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4483 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4484 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4485 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4486 "interrupt holdoff timer values (us)");
4488 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4489 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4490 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4491 "interrupt holdoff packet counter values");
4493 t4_sge_sysctls(sc, ctx, children);
4495 sc->lro_timeout = 100;
4496 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4497 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4499 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "debug_flags", CTLFLAG_RW,
4500 &sc->debug_flags, 0, "flags to enable runtime debugging");
4502 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
4503 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
4505 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4506 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4508 if (sc->flags & IS_VF)
4511 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4512 NULL, chip_rev(sc), "chip hardware revision");
4514 if (sc->params.exprom_vers != 0) {
4515 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "exprom_version",
4516 CTLFLAG_RD, sc->exprom_version, 0, "expansion ROM version");
4519 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4520 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4522 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4523 sc->cfcsum, "config file checksum");
4525 #define SYSCTL_CAP(name, n, text) \
4526 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4527 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4528 sysctl_bitfield, "A", "available " text "capabilities")
4530 SYSCTL_CAP(nbmcaps, 0, "NBM");
4531 SYSCTL_CAP(linkcaps, 1, "link");
4532 SYSCTL_CAP(switchcaps, 2, "switch");
4533 SYSCTL_CAP(niccaps, 3, "NIC");
4534 SYSCTL_CAP(toecaps, 4, "TCP offload");
4535 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4536 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4537 SYSCTL_CAP(tlscaps, 7, "TLS");
4538 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4541 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4542 NULL, sc->tids.nftids, "number of filters");
4544 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4545 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4546 "chip temperature (in Celsius)");
4550 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4552 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4553 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4554 "logs and miscellaneous information");
4555 children = SYSCTL_CHILDREN(oid);
4557 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4558 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4559 sysctl_cctrl, "A", "congestion control");
4561 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4562 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4563 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4565 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4566 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4567 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4569 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4570 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4571 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4573 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4574 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4575 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4577 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4578 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4579 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4581 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4582 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4583 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4585 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4586 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4587 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
4588 "A", "CIM logic analyzer");
4590 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4591 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4592 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4594 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4595 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4596 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4598 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4599 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4600 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4603 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4604 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4606 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4607 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4608 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4610 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4611 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4612 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4615 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4616 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4618 if (chip_id(sc) > CHELSIO_T4) {
4619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4620 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4621 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4623 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4624 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4625 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4628 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4629 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4630 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4632 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4633 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4634 sysctl_cim_qcfg, "A", "CIM queue configuration");
4636 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4637 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4638 sysctl_cpl_stats, "A", "CPL statistics");
4640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4641 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4642 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4645 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4646 sysctl_devlog, "A", "firmware's device log");
4648 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4649 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4650 sysctl_fcoe_stats, "A", "FCoE statistics");
4652 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4653 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4654 sysctl_hw_sched, "A", "hardware scheduler ");
4656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4657 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4658 sysctl_l2t, "A", "hardware L2 table");
4660 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4661 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4662 sysctl_lb_stats, "A", "loopback statistics");
4664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4665 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4666 sysctl_meminfo, "A", "memory regions");
4668 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4669 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4670 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
4671 "A", "MPS TCAM entries");
4673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4674 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4675 sysctl_path_mtus, "A", "path MTUs");
4677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4678 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4679 sysctl_pm_stats, "A", "PM statistics");
4681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4682 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4683 sysctl_rdma_stats, "A", "RDMA statistics");
4685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4686 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4687 sysctl_tcp_stats, "A", "TCP statistics");
4689 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4690 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4691 sysctl_tids, "A", "TID information");
4693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4694 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4695 sysctl_tp_err_stats, "A", "TP error statistics");
4697 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
4698 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
4699 "TP logic analyzer event capture mask");
4701 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4702 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4703 sysctl_tp_la, "A", "TP logic analyzer");
4705 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4706 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4707 sysctl_tx_rate, "A", "Tx rate");
4709 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4710 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4711 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4714 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4715 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4716 sysctl_wcwr_stats, "A", "write combined work requests");
4721 if (is_offload(sc)) {
4725 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4726 NULL, "TOE parameters");
4727 children = SYSCTL_CHILDREN(oid);
4729 sc->tt.sndbuf = 256 * 1024;
4730 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4731 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4734 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4735 &sc->tt.ddp, 0, "DDP allowed");
4737 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
4738 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
4739 &sc->tt.indsz, 0, "DDP max indicate size allowed");
4742 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
4743 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
4744 &sc->tt.ddp_thres, 0, "DDP threshold");
4746 sc->tt.rx_coalesce = 1;
4747 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4748 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4750 sc->tt.tx_align = 1;
4751 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4752 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4754 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
4755 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
4756 "TP timer tick (us)");
4758 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
4759 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
4760 "TCP timestamp tick (us)");
4762 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
4763 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
4766 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
4767 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
4768 "IU", "DACK timer (us)");
4770 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
4771 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
4772 sysctl_tp_timer, "LU", "Retransmit min (us)");
4774 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
4775 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
4776 sysctl_tp_timer, "LU", "Retransmit max (us)");
4778 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
4779 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
4780 sysctl_tp_timer, "LU", "Persist timer min (us)");
4782 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
4783 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
4784 sysctl_tp_timer, "LU", "Persist timer max (us)");
4786 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
4787 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
4788 sysctl_tp_timer, "LU", "Keepidle idle timer (us)");
4790 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl",
4791 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
4792 sysctl_tp_timer, "LU", "Keepidle interval (us)");
4794 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
4795 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
4796 sysctl_tp_timer, "LU", "Initial SRTT (us)");
4798 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
4799 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
4800 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
4806 vi_sysctls(struct vi_info *vi)
4808 struct sysctl_ctx_list *ctx;
4809 struct sysctl_oid *oid;
4810 struct sysctl_oid_list *children;
4812 ctx = device_get_sysctl_ctx(vi->dev);
4815 * dev.v?(cxgbe|cxl).X.
4817 oid = device_get_sysctl_tree(vi->dev);
4818 children = SYSCTL_CHILDREN(oid);
4820 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
4821 vi->viid, "VI identifer");
4822 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
4823 &vi->nrxq, 0, "# of rx queues");
4824 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
4825 &vi->ntxq, 0, "# of tx queues");
4826 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
4827 &vi->first_rxq, 0, "index of first rx queue");
4828 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
4829 &vi->first_txq, 0, "index of first tx queue");
4831 if (IS_MAIN_VI(vi)) {
4832 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
4833 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
4834 "Reserve queue 0 for non-flowid packets");
4838 if (vi->nofldrxq != 0) {
4839 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
4841 "# of rx queues for offloaded TCP connections");
4842 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
4844 "# of tx queues for offloaded TCP connections");
4845 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4846 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
4847 "index of first TOE rx queue");
4848 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4849 CTLFLAG_RD, &vi->first_ofld_txq, 0,
4850 "index of first TOE tx queue");
4854 if (vi->nnmrxq != 0) {
4855 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
4856 &vi->nnmrxq, 0, "# of netmap rx queues");
4857 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
4858 &vi->nnmtxq, 0, "# of netmap tx queues");
4859 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
4860 CTLFLAG_RD, &vi->first_nm_rxq, 0,
4861 "index of first netmap rx queue");
4862 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
4863 CTLFLAG_RD, &vi->first_nm_txq, 0,
4864 "index of first netmap tx queue");
4868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4869 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
4870 "holdoff timer index");
4871 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4872 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
4873 "holdoff packet counter index");
4875 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
4876 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
4878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
4879 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
4884 cxgbe_sysctls(struct port_info *pi)
4886 struct sysctl_ctx_list *ctx;
4887 struct sysctl_oid *oid;
4888 struct sysctl_oid_list *children, *children2;
4889 struct adapter *sc = pi->adapter;
4893 ctx = device_get_sysctl_ctx(pi->dev);
4898 oid = device_get_sysctl_tree(pi->dev);
4899 children = SYSCTL_CHILDREN(oid);
4901 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
4902 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
4903 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
4904 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
4905 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
4906 "PHY temperature (in Celsius)");
4907 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
4908 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
4909 "PHY firmware version");
4912 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
4913 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings,
4914 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
4916 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
4917 port_top_speed(pi), "max speed (in Gbps)");
4919 if (sc->flags & IS_VF)
4923 * dev.(cxgbe|cxl).X.tc.
4925 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
4926 "Tx scheduler traffic classes");
4927 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
4928 struct tx_sched_class *tc = &pi->tc[i];
4930 snprintf(name, sizeof(name), "%d", i);
4931 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
4932 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
4934 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
4935 &tc->flags, 0, "flags");
4936 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
4937 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
4939 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
4940 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
4941 sysctl_tc_params, "A", "traffic class parameters");
4946 * dev.cxgbe.X.stats.
4948 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4949 NULL, "port statistics");
4950 children = SYSCTL_CHILDREN(oid);
4951 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
4952 &pi->tx_parse_error, 0,
4953 "# of tx packets with invalid length or # of segments");
4955 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
4956 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
4957 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
4958 sysctl_handle_t4_reg64, "QU", desc)
4960 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
4961 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
4962 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
4963 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
4964 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
4965 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
4966 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
4967 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
4968 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
4969 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
4970 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
4971 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
4972 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
4973 "# of tx frames in this range",
4974 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
4975 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
4976 "# of tx frames in this range",
4977 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
4978 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
4979 "# of tx frames in this range",
4980 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
4981 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
4982 "# of tx frames in this range",
4983 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
4984 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
4985 "# of tx frames in this range",
4986 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
4987 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
4988 "# of tx frames in this range",
4989 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
4990 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
4991 "# of tx frames in this range",
4992 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
4993 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
4994 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
4995 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
4996 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
4997 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
4998 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
4999 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
5000 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
5001 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
5002 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
5003 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
5004 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
5005 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
5006 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
5007 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
5008 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
5009 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
5010 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
5011 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
5012 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
5014 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
5015 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
5016 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
5017 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
5018 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
5019 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
5020 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
5021 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
5022 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
5023 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
5024 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
5025 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
5026 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5027 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5028 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5029 "# of frames received with bad FCS",
5030 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5031 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5032 "# of frames received with length error",
5033 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5034 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5035 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5036 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5037 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5038 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5039 "# of rx frames in this range",
5040 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5041 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5042 "# of rx frames in this range",
5043 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5044 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5045 "# of rx frames in this range",
5046 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5047 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5048 "# of rx frames in this range",
5049 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5050 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5051 "# of rx frames in this range",
5052 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5053 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5054 "# of rx frames in this range",
5055 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5056 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5057 "# of rx frames in this range",
5058 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5059 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5060 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5061 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5062 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5063 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5064 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5065 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5066 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5067 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5068 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5069 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5070 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5071 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5072 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5073 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5074 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5075 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5076 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5078 #undef SYSCTL_ADD_T4_REG64
5080 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5081 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5082 &pi->stats.name, desc)
5084 /* We get these from port_stats and they may be stale by upto 1s */
5085 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5086 "# drops due to buffer-group 0 overflows");
5087 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5088 "# drops due to buffer-group 1 overflows");
5089 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5090 "# drops due to buffer-group 2 overflows");
5091 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5092 "# drops due to buffer-group 3 overflows");
5093 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5094 "# of buffer-group 0 truncated packets");
5095 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5096 "# of buffer-group 1 truncated packets");
5097 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5098 "# of buffer-group 2 truncated packets");
5099 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5100 "# of buffer-group 3 truncated packets");
5102 #undef SYSCTL_ADD_T4_PORTSTAT
5106 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5108 int rc, *i, space = 0;
5111 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5112 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5114 sbuf_printf(&sb, " ");
5115 sbuf_printf(&sb, "%d", *i);
5119 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5125 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5130 rc = sysctl_wire_old_buffer(req, 0);
5134 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5138 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5139 rc = sbuf_finish(sb);
5146 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5148 struct port_info *pi = arg1;
5150 struct adapter *sc = pi->adapter;
5154 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5157 /* XXX: magic numbers */
5158 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5160 end_synchronized_op(sc, 0);
5166 rc = sysctl_handle_int(oidp, &v, 0, req);
5171 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5173 struct vi_info *vi = arg1;
5176 val = vi->rsrv_noflowq;
5177 rc = sysctl_handle_int(oidp, &val, 0, req);
5178 if (rc != 0 || req->newptr == NULL)
5181 if ((val >= 1) && (vi->ntxq > 1))
5182 vi->rsrv_noflowq = 1;
5184 vi->rsrv_noflowq = 0;
5190 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5192 struct vi_info *vi = arg1;
5193 struct adapter *sc = vi->pi->adapter;
5195 struct sge_rxq *rxq;
5197 struct sge_ofld_rxq *ofld_rxq;
5203 rc = sysctl_handle_int(oidp, &idx, 0, req);
5204 if (rc != 0 || req->newptr == NULL)
5207 if (idx < 0 || idx >= SGE_NTIMERS)
5210 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5215 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5216 for_each_rxq(vi, i, rxq) {
5217 #ifdef atomic_store_rel_8
5218 atomic_store_rel_8(&rxq->iq.intr_params, v);
5220 rxq->iq.intr_params = v;
5224 for_each_ofld_rxq(vi, i, ofld_rxq) {
5225 #ifdef atomic_store_rel_8
5226 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5228 ofld_rxq->iq.intr_params = v;
5234 end_synchronized_op(sc, LOCK_HELD);
5239 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5241 struct vi_info *vi = arg1;
5242 struct adapter *sc = vi->pi->adapter;
5247 rc = sysctl_handle_int(oidp, &idx, 0, req);
5248 if (rc != 0 || req->newptr == NULL)
5251 if (idx < -1 || idx >= SGE_NCOUNTERS)
5254 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5259 if (vi->flags & VI_INIT_DONE)
5260 rc = EBUSY; /* cannot be changed once the queues are created */
5264 end_synchronized_op(sc, LOCK_HELD);
5269 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5271 struct vi_info *vi = arg1;
5272 struct adapter *sc = vi->pi->adapter;
5275 qsize = vi->qsize_rxq;
5277 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5278 if (rc != 0 || req->newptr == NULL)
5281 if (qsize < 128 || (qsize & 7))
5284 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5289 if (vi->flags & VI_INIT_DONE)
5290 rc = EBUSY; /* cannot be changed once the queues are created */
5292 vi->qsize_rxq = qsize;
5294 end_synchronized_op(sc, LOCK_HELD);
5299 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5301 struct vi_info *vi = arg1;
5302 struct adapter *sc = vi->pi->adapter;
5305 qsize = vi->qsize_txq;
5307 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5308 if (rc != 0 || req->newptr == NULL)
5311 if (qsize < 128 || qsize > 65536)
5314 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5319 if (vi->flags & VI_INIT_DONE)
5320 rc = EBUSY; /* cannot be changed once the queues are created */
5322 vi->qsize_txq = qsize;
5324 end_synchronized_op(sc, LOCK_HELD);
5329 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5331 struct port_info *pi = arg1;
5332 struct adapter *sc = pi->adapter;
5333 struct link_config *lc = &pi->link_cfg;
5336 if (req->newptr == NULL) {
5338 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5340 rc = sysctl_wire_old_buffer(req, 0);
5344 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5348 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5349 rc = sbuf_finish(sb);
5355 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5358 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5364 if (s[0] < '0' || s[0] > '9')
5365 return (EINVAL); /* not a number */
5367 if (n & ~(PAUSE_TX | PAUSE_RX))
5368 return (EINVAL); /* some other bit is set too */
5370 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5374 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5375 int link_ok = lc->link_ok;
5377 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5378 lc->requested_fc |= n;
5379 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5380 lc->link_ok = link_ok; /* restore */
5382 end_synchronized_op(sc, 0);
5389 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5391 struct adapter *sc = arg1;
5395 val = t4_read_reg64(sc, reg);
5397 return (sysctl_handle_64(oidp, &val, 0, req));
5401 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5403 struct adapter *sc = arg1;
5405 uint32_t param, val;
5407 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5410 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5411 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5412 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5413 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5414 end_synchronized_op(sc, 0);
5418 /* unknown is returned as 0 but we display -1 in that case */
5419 t = val == 0 ? -1 : val;
5421 rc = sysctl_handle_int(oidp, &t, 0, req);
5427 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5429 struct adapter *sc = arg1;
5432 uint16_t incr[NMTUS][NCCTRL_WIN];
5433 static const char *dec_fac[] = {
5434 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5438 rc = sysctl_wire_old_buffer(req, 0);
5442 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5446 t4_read_cong_tbl(sc, incr);
5448 for (i = 0; i < NCCTRL_WIN; ++i) {
5449 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5450 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5451 incr[5][i], incr[6][i], incr[7][i]);
5452 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5453 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5454 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5455 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5458 rc = sbuf_finish(sb);
5464 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5465 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
5466 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5467 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
5471 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5473 struct adapter *sc = arg1;
5475 int rc, i, n, qid = arg2;
5478 u_int cim_num_obq = sc->chip_params->cim_num_obq;
5480 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5481 ("%s: bad qid %d\n", __func__, qid));
5483 if (qid < CIM_NUM_IBQ) {
5486 n = 4 * CIM_IBQ_SIZE;
5487 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5488 rc = t4_read_cim_ibq(sc, qid, buf, n);
5490 /* outbound queue */
5493 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5494 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5495 rc = t4_read_cim_obq(sc, qid, buf, n);
5502 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
5504 rc = sysctl_wire_old_buffer(req, 0);
5508 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5514 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5515 for (i = 0, p = buf; i < n; i += 16, p += 4)
5516 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5519 rc = sbuf_finish(sb);
5527 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5529 struct adapter *sc = arg1;
5535 MPASS(chip_id(sc) <= CHELSIO_T5);
5537 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5541 rc = sysctl_wire_old_buffer(req, 0);
5545 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5549 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5552 rc = -t4_cim_read_la(sc, buf, NULL);
5556 sbuf_printf(sb, "Status Data PC%s",
5557 cfg & F_UPDBGLACAPTPCONLY ? "" :
5558 " LS0Stat LS0Addr LS0Data");
5560 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
5561 if (cfg & F_UPDBGLACAPTPCONLY) {
5562 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5564 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5565 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5566 p[4] & 0xff, p[5] >> 8);
5567 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5568 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5569 p[1] & 0xf, p[2] >> 4);
5572 "\n %02x %x%07x %x%07x %08x %08x "
5574 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5575 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5580 rc = sbuf_finish(sb);
5588 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
5590 struct adapter *sc = arg1;
5596 MPASS(chip_id(sc) > CHELSIO_T5);
5598 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5602 rc = sysctl_wire_old_buffer(req, 0);
5606 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5610 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5613 rc = -t4_cim_read_la(sc, buf, NULL);
5617 sbuf_printf(sb, "Status Inst Data PC%s",
5618 cfg & F_UPDBGLACAPTPCONLY ? "" :
5619 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
5621 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
5622 if (cfg & F_UPDBGLACAPTPCONLY) {
5623 sbuf_printf(sb, "\n %02x %08x %08x %08x",
5624 p[3] & 0xff, p[2], p[1], p[0]);
5625 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
5626 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
5627 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
5628 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
5629 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
5630 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
5633 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
5634 "%08x %08x %08x %08x %08x %08x",
5635 (p[9] >> 16) & 0xff,
5636 p[9] & 0xffff, p[8] >> 16,
5637 p[8] & 0xffff, p[7] >> 16,
5638 p[7] & 0xffff, p[6] >> 16,
5639 p[2], p[1], p[0], p[5], p[4], p[3]);
5643 rc = sbuf_finish(sb);
5651 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5653 struct adapter *sc = arg1;
5659 rc = sysctl_wire_old_buffer(req, 0);
5663 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5667 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5670 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5673 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5674 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5678 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
5679 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5680 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
5681 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5682 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5683 (p[1] >> 2) | ((p[2] & 3) << 30),
5684 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5688 rc = sbuf_finish(sb);
5695 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5697 struct adapter *sc = arg1;
5703 rc = sysctl_wire_old_buffer(req, 0);
5707 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5711 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5714 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5717 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
5718 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5719 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
5720 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5721 p[4], p[3], p[2], p[1], p[0]);
5724 sbuf_printf(sb, "\n\nCntl ID Data");
5725 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5726 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
5727 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5730 rc = sbuf_finish(sb);
5737 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5739 struct adapter *sc = arg1;
5742 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5743 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5744 uint16_t thres[CIM_NUM_IBQ];
5745 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5746 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5747 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5749 cim_num_obq = sc->chip_params->cim_num_obq;
5751 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5752 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5754 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5755 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5757 nq = CIM_NUM_IBQ + cim_num_obq;
5759 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5761 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5765 t4_read_cimq_cfg(sc, base, size, thres);
5767 rc = sysctl_wire_old_buffer(req, 0);
5771 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5775 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
5777 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5778 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
5779 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5780 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5781 G_QUEREMFLITS(p[2]) * 16);
5782 for ( ; i < nq; i++, p += 4, wr += 2)
5783 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
5784 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
5785 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5786 G_QUEREMFLITS(p[2]) * 16);
5788 rc = sbuf_finish(sb);
5795 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
5797 struct adapter *sc = arg1;
5800 struct tp_cpl_stats stats;
5802 rc = sysctl_wire_old_buffer(req, 0);
5806 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5810 mtx_lock(&sc->reg_lock);
5811 t4_tp_get_cpl_stats(sc, &stats);
5812 mtx_unlock(&sc->reg_lock);
5814 if (sc->chip_params->nchan > 2) {
5815 sbuf_printf(sb, " channel 0 channel 1"
5816 " channel 2 channel 3");
5817 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
5818 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
5819 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
5820 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
5822 sbuf_printf(sb, " channel 0 channel 1");
5823 sbuf_printf(sb, "\nCPL requests: %10u %10u",
5824 stats.req[0], stats.req[1]);
5825 sbuf_printf(sb, "\nCPL responses: %10u %10u",
5826 stats.rsp[0], stats.rsp[1]);
5829 rc = sbuf_finish(sb);
5836 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
5838 struct adapter *sc = arg1;
5841 struct tp_usm_stats stats;
5843 rc = sysctl_wire_old_buffer(req, 0);
5847 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5851 t4_get_usm_stats(sc, &stats);
5853 sbuf_printf(sb, "Frames: %u\n", stats.frames);
5854 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
5855 sbuf_printf(sb, "Drops: %u", stats.drops);
5857 rc = sbuf_finish(sb);
5863 static const char * const devlog_level_strings[] = {
5864 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
5865 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
5866 [FW_DEVLOG_LEVEL_ERR] = "ERR",
5867 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
5868 [FW_DEVLOG_LEVEL_INFO] = "INFO",
5869 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
5872 static const char * const devlog_facility_strings[] = {
5873 [FW_DEVLOG_FACILITY_CORE] = "CORE",
5874 [FW_DEVLOG_FACILITY_CF] = "CF",
5875 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
5876 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
5877 [FW_DEVLOG_FACILITY_RES] = "RES",
5878 [FW_DEVLOG_FACILITY_HW] = "HW",
5879 [FW_DEVLOG_FACILITY_FLR] = "FLR",
5880 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
5881 [FW_DEVLOG_FACILITY_PHY] = "PHY",
5882 [FW_DEVLOG_FACILITY_MAC] = "MAC",
5883 [FW_DEVLOG_FACILITY_PORT] = "PORT",
5884 [FW_DEVLOG_FACILITY_VI] = "VI",
5885 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
5886 [FW_DEVLOG_FACILITY_ACL] = "ACL",
5887 [FW_DEVLOG_FACILITY_TM] = "TM",
5888 [FW_DEVLOG_FACILITY_QFC] = "QFC",
5889 [FW_DEVLOG_FACILITY_DCB] = "DCB",
5890 [FW_DEVLOG_FACILITY_ETH] = "ETH",
5891 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
5892 [FW_DEVLOG_FACILITY_RI] = "RI",
5893 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
5894 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
5895 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
5896 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
5897 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
5901 sysctl_devlog(SYSCTL_HANDLER_ARGS)
5903 struct adapter *sc = arg1;
5904 struct devlog_params *dparams = &sc->params.devlog;
5905 struct fw_devlog_e *buf, *e;
5906 int i, j, rc, nentries, first = 0;
5908 uint64_t ftstamp = UINT64_MAX;
5910 if (dparams->addr == 0)
5913 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
5917 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
5921 nentries = dparams->size / sizeof(struct fw_devlog_e);
5922 for (i = 0; i < nentries; i++) {
5925 if (e->timestamp == 0)
5928 e->timestamp = be64toh(e->timestamp);
5929 e->seqno = be32toh(e->seqno);
5930 for (j = 0; j < 8; j++)
5931 e->params[j] = be32toh(e->params[j]);
5933 if (e->timestamp < ftstamp) {
5934 ftstamp = e->timestamp;
5939 if (buf[first].timestamp == 0)
5940 goto done; /* nothing in the log */
5942 rc = sysctl_wire_old_buffer(req, 0);
5946 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5951 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
5952 "Seq#", "Tstamp", "Level", "Facility", "Message");
5957 if (e->timestamp == 0)
5960 sbuf_printf(sb, "%10d %15ju %8s %8s ",
5961 e->seqno, e->timestamp,
5962 (e->level < nitems(devlog_level_strings) ?
5963 devlog_level_strings[e->level] : "UNKNOWN"),
5964 (e->facility < nitems(devlog_facility_strings) ?
5965 devlog_facility_strings[e->facility] : "UNKNOWN"));
5966 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
5967 e->params[2], e->params[3], e->params[4],
5968 e->params[5], e->params[6], e->params[7]);
5970 if (++i == nentries)
5972 } while (i != first);
5974 rc = sbuf_finish(sb);
5982 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
5984 struct adapter *sc = arg1;
5987 struct tp_fcoe_stats stats[MAX_NCHAN];
5988 int i, nchan = sc->chip_params->nchan;
5990 rc = sysctl_wire_old_buffer(req, 0);
5994 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5998 for (i = 0; i < nchan; i++)
5999 t4_get_fcoe_stats(sc, i, &stats[i]);
6002 sbuf_printf(sb, " channel 0 channel 1"
6003 " channel 2 channel 3");
6004 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
6005 stats[0].octets_ddp, stats[1].octets_ddp,
6006 stats[2].octets_ddp, stats[3].octets_ddp);
6007 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
6008 stats[0].frames_ddp, stats[1].frames_ddp,
6009 stats[2].frames_ddp, stats[3].frames_ddp);
6010 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
6011 stats[0].frames_drop, stats[1].frames_drop,
6012 stats[2].frames_drop, stats[3].frames_drop);
6014 sbuf_printf(sb, " channel 0 channel 1");
6015 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
6016 stats[0].octets_ddp, stats[1].octets_ddp);
6017 sbuf_printf(sb, "\nframesDDP: %16u %16u",
6018 stats[0].frames_ddp, stats[1].frames_ddp);
6019 sbuf_printf(sb, "\nframesDrop: %16u %16u",
6020 stats[0].frames_drop, stats[1].frames_drop);
6023 rc = sbuf_finish(sb);
6030 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6032 struct adapter *sc = arg1;
6035 unsigned int map, kbps, ipg, mode;
6036 unsigned int pace_tab[NTX_SCHED];
6038 rc = sysctl_wire_old_buffer(req, 0);
6042 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6046 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6047 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6048 t4_read_pace_tbl(sc, pace_tab);
6050 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6051 "Class IPG (0.1 ns) Flow IPG (us)");
6053 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6054 t4_get_tx_sched(sc, i, &kbps, &ipg);
6055 sbuf_printf(sb, "\n %u %-5s %u ", i,
6056 (mode & (1 << i)) ? "flow" : "class", map & 3);
6058 sbuf_printf(sb, "%9u ", kbps);
6060 sbuf_printf(sb, " disabled ");
6063 sbuf_printf(sb, "%13u ", ipg);
6065 sbuf_printf(sb, " disabled ");
6068 sbuf_printf(sb, "%10u", pace_tab[i]);
6070 sbuf_printf(sb, " disabled");
6073 rc = sbuf_finish(sb);
6080 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6082 struct adapter *sc = arg1;
6086 struct lb_port_stats s[2];
6087 static const char *stat_name[] = {
6088 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6089 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6090 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6091 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6092 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6093 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6094 "BG2FramesTrunc:", "BG3FramesTrunc:"
6097 rc = sysctl_wire_old_buffer(req, 0);
6101 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6105 memset(s, 0, sizeof(s));
6107 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6108 t4_get_lb_stats(sc, i, &s[0]);
6109 t4_get_lb_stats(sc, i + 1, &s[1]);
6113 sbuf_printf(sb, "%s Loopback %u"
6114 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6116 for (j = 0; j < nitems(stat_name); j++)
6117 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6121 rc = sbuf_finish(sb);
6128 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6131 struct port_info *pi = arg1;
6134 rc = sysctl_wire_old_buffer(req, 0);
6137 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6141 if (pi->linkdnrc < 0)
6142 sbuf_printf(sb, "n/a");
6144 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc));
6146 rc = sbuf_finish(sb);
6159 mem_desc_cmp(const void *a, const void *b)
6161 return ((const struct mem_desc *)a)->base -
6162 ((const struct mem_desc *)b)->base;
6166 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6174 size = to - from + 1;
6178 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6179 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6183 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6185 struct adapter *sc = arg1;
6188 uint32_t lo, hi, used, alloc;
6189 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6190 static const char *region[] = {
6191 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6192 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6193 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6194 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6195 "RQUDP region:", "PBL region:", "TXPBL region:",
6196 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6199 struct mem_desc avail[4];
6200 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6201 struct mem_desc *md = mem;
6203 rc = sysctl_wire_old_buffer(req, 0);
6207 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6211 for (i = 0; i < nitems(mem); i++) {
6216 /* Find and sort the populated memory ranges */
6218 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6219 if (lo & F_EDRAM0_ENABLE) {
6220 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6221 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6222 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6226 if (lo & F_EDRAM1_ENABLE) {
6227 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6228 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6229 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6233 if (lo & F_EXT_MEM_ENABLE) {
6234 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6235 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6236 avail[i].limit = avail[i].base +
6237 (G_EXT_MEM_SIZE(hi) << 20);
6238 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6241 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6242 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6243 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6244 avail[i].limit = avail[i].base +
6245 (G_EXT_MEM1_SIZE(hi) << 20);
6249 if (!i) /* no memory available */
6251 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6253 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6254 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6255 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6256 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6257 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6258 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6259 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6260 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6261 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6263 /* the next few have explicit upper bounds */
6264 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6265 md->limit = md->base - 1 +
6266 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6267 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6270 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6271 md->limit = md->base - 1 +
6272 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6273 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6276 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6277 if (chip_id(sc) <= CHELSIO_T5)
6278 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6280 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6284 md->idx = nitems(region); /* hide it */
6288 #define ulp_region(reg) \
6289 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6290 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6292 ulp_region(RX_ISCSI);
6293 ulp_region(RX_TDDP);
6295 ulp_region(RX_STAG);
6297 ulp_region(RX_RQUDP);
6303 md->idx = nitems(region);
6306 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6307 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6310 if (sge_ctrl & F_VFIFO_ENABLE)
6311 size = G_DBVFIFO_SIZE(fifo_size);
6313 size = G_T6_DBVFIFO_SIZE(fifo_size);
6316 md->base = G_BASEADDR(t4_read_reg(sc,
6317 A_SGE_DBVFIFO_BADDR));
6318 md->limit = md->base + (size << 2) - 1;
6323 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6326 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6330 md->base = sc->vres.ocq.start;
6331 if (sc->vres.ocq.size)
6332 md->limit = md->base + sc->vres.ocq.size - 1;
6334 md->idx = nitems(region); /* hide it */
6337 /* add any address-space holes, there can be up to 3 */
6338 for (n = 0; n < i - 1; n++)
6339 if (avail[n].limit < avail[n + 1].base)
6340 (md++)->base = avail[n].limit;
6342 (md++)->base = avail[n].limit;
6345 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6347 for (lo = 0; lo < i; lo++)
6348 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6349 avail[lo].limit - 1);
6351 sbuf_printf(sb, "\n");
6352 for (i = 0; i < n; i++) {
6353 if (mem[i].idx >= nitems(region))
6354 continue; /* skip holes */
6356 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6357 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6361 sbuf_printf(sb, "\n");
6362 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6363 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6364 mem_region_show(sb, "uP RAM:", lo, hi);
6366 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6367 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6368 mem_region_show(sb, "uP Extmem2:", lo, hi);
6370 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6371 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6373 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6374 (lo & F_PMRXNUMCHN) ? 2 : 1);
6376 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6377 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6378 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6380 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6381 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6382 sbuf_printf(sb, "%u p-structs\n",
6383 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6385 for (i = 0; i < 4; i++) {
6386 if (chip_id(sc) > CHELSIO_T5)
6387 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6389 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6391 used = G_T5_USED(lo);
6392 alloc = G_T5_ALLOC(lo);
6395 alloc = G_ALLOC(lo);
6397 /* For T6 these are MAC buffer groups */
6398 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6401 for (i = 0; i < sc->chip_params->nchan; i++) {
6402 if (chip_id(sc) > CHELSIO_T5)
6403 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6405 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6407 used = G_T5_USED(lo);
6408 alloc = G_T5_ALLOC(lo);
6411 alloc = G_ALLOC(lo);
6413 /* For T6 these are MAC buffer groups */
6415 "\nLoopback %d using %u pages out of %u allocated",
6419 rc = sbuf_finish(sb);
6426 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6430 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6434 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6436 struct adapter *sc = arg1;
6440 MPASS(chip_id(sc) <= CHELSIO_T5);
6442 rc = sysctl_wire_old_buffer(req, 0);
6446 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6451 "Idx Ethernet address Mask Vld Ports PF"
6452 " VF Replication P0 P1 P2 P3 ML");
6453 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6454 uint64_t tcamx, tcamy, mask;
6455 uint32_t cls_lo, cls_hi;
6456 uint8_t addr[ETHER_ADDR_LEN];
6458 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6459 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6462 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6463 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6464 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6465 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6466 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
6467 addr[3], addr[4], addr[5], (uintmax_t)mask,
6468 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6469 G_PORTMAP(cls_hi), G_PF(cls_lo),
6470 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6472 if (cls_lo & F_REPLICATE) {
6473 struct fw_ldst_cmd ldst_cmd;
6475 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6476 ldst_cmd.op_to_addrspace =
6477 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6478 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6479 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6480 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6481 ldst_cmd.u.mps.rplc.fid_idx =
6482 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6483 V_FW_LDST_CMD_IDX(i));
6485 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6489 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6490 sizeof(ldst_cmd), &ldst_cmd);
6491 end_synchronized_op(sc, 0);
6494 sbuf_printf(sb, "%36d", rc);
6497 sbuf_printf(sb, " %08x %08x %08x %08x",
6498 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6499 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6500 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6501 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6504 sbuf_printf(sb, "%36s", "");
6506 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6507 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6508 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6512 (void) sbuf_finish(sb);
6514 rc = sbuf_finish(sb);
6521 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
6523 struct adapter *sc = arg1;
6527 MPASS(chip_id(sc) > CHELSIO_T5);
6529 rc = sysctl_wire_old_buffer(req, 0);
6533 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6537 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
6538 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
6540 " P0 P1 P2 P3 ML\n");
6542 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6543 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
6545 uint64_t tcamx, tcamy, val, mask;
6546 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
6547 uint8_t addr[ETHER_ADDR_LEN];
6549 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
6551 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
6553 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
6554 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6555 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6556 tcamy = G_DMACH(val) << 32;
6557 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6558 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6559 lookup_type = G_DATALKPTYPE(data2);
6560 port_num = G_DATAPORTNUM(data2);
6561 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6562 /* Inner header VNI */
6563 vniy = ((data2 & F_DATAVIDH2) << 23) |
6564 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6565 dip_hit = data2 & F_DATADIPHIT;
6570 vlan_vld = data2 & F_DATAVIDH2;
6571 ivlan = G_VIDL(val);
6574 ctl |= V_CTLXYBITSEL(1);
6575 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6576 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6577 tcamx = G_DMACH(val) << 32;
6578 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6579 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6580 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6581 /* Inner header VNI mask */
6582 vnix = ((data2 & F_DATAVIDH2) << 23) |
6583 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6589 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6591 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6592 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6594 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6595 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6596 "%012jx %06x %06x - - %3c"
6597 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
6598 addr[1], addr[2], addr[3], addr[4], addr[5],
6599 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
6600 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6601 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6602 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6604 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6605 "%012jx - - ", i, addr[0], addr[1],
6606 addr[2], addr[3], addr[4], addr[5],
6610 sbuf_printf(sb, "%4u Y ", ivlan);
6612 sbuf_printf(sb, " - N ");
6614 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
6615 lookup_type ? 'I' : 'O', port_num,
6616 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6617 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6618 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6622 if (cls_lo & F_T6_REPLICATE) {
6623 struct fw_ldst_cmd ldst_cmd;
6625 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6626 ldst_cmd.op_to_addrspace =
6627 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6628 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6629 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6630 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6631 ldst_cmd.u.mps.rplc.fid_idx =
6632 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6633 V_FW_LDST_CMD_IDX(i));
6635 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6639 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6640 sizeof(ldst_cmd), &ldst_cmd);
6641 end_synchronized_op(sc, 0);
6644 sbuf_printf(sb, "%72d", rc);
6647 sbuf_printf(sb, " %08x %08x %08x %08x"
6648 " %08x %08x %08x %08x",
6649 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
6650 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
6651 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
6652 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
6653 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6654 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6655 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6656 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6659 sbuf_printf(sb, "%72s", "");
6661 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
6662 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
6663 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
6664 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
6668 (void) sbuf_finish(sb);
6670 rc = sbuf_finish(sb);
6677 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
6679 struct adapter *sc = arg1;
6682 uint16_t mtus[NMTUS];
6684 rc = sysctl_wire_old_buffer(req, 0);
6688 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6692 t4_read_mtu_tbl(sc, mtus, NULL);
6694 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
6695 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
6696 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
6697 mtus[14], mtus[15]);
6699 rc = sbuf_finish(sb);
6706 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
6708 struct adapter *sc = arg1;
6711 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
6712 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
6713 static const char *tx_stats[MAX_PM_NSTATS] = {
6714 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
6715 "Tx FIFO wait", NULL, "Tx latency"
6717 static const char *rx_stats[MAX_PM_NSTATS] = {
6718 "Read:", "Write bypass:", "Write mem:", "Flush:",
6719 " Rx FIFO wait", NULL, "Rx latency"
6722 rc = sysctl_wire_old_buffer(req, 0);
6726 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6730 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
6731 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
6733 sbuf_printf(sb, " Tx pcmds Tx bytes");
6734 for (i = 0; i < 4; i++) {
6735 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6739 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
6740 for (i = 0; i < 4; i++) {
6741 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6745 if (chip_id(sc) > CHELSIO_T5) {
6747 "\n Total wait Total occupancy");
6748 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6750 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6754 MPASS(i < nitems(tx_stats));
6757 "\n Reads Total wait");
6758 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6760 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6764 rc = sbuf_finish(sb);
6771 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
6773 struct adapter *sc = arg1;
6776 struct tp_rdma_stats stats;
6778 rc = sysctl_wire_old_buffer(req, 0);
6782 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6786 mtx_lock(&sc->reg_lock);
6787 t4_tp_get_rdma_stats(sc, &stats);
6788 mtx_unlock(&sc->reg_lock);
6790 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
6791 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
6793 rc = sbuf_finish(sb);
6800 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
6802 struct adapter *sc = arg1;
6805 struct tp_tcp_stats v4, v6;
6807 rc = sysctl_wire_old_buffer(req, 0);
6811 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6815 mtx_lock(&sc->reg_lock);
6816 t4_tp_get_tcp_stats(sc, &v4, &v6);
6817 mtx_unlock(&sc->reg_lock);
6821 sbuf_printf(sb, "OutRsts: %20u %20u\n",
6822 v4.tcp_out_rsts, v6.tcp_out_rsts);
6823 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
6824 v4.tcp_in_segs, v6.tcp_in_segs);
6825 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
6826 v4.tcp_out_segs, v6.tcp_out_segs);
6827 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
6828 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
6830 rc = sbuf_finish(sb);
6837 sysctl_tids(SYSCTL_HANDLER_ARGS)
6839 struct adapter *sc = arg1;
6842 struct tid_info *t = &sc->tids;
6844 rc = sysctl_wire_old_buffer(req, 0);
6848 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6853 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
6858 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6859 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
6862 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
6863 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6866 sbuf_printf(sb, "TID range: %u-%u",
6867 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6871 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
6872 sbuf_printf(sb, ", in use: %u\n",
6873 atomic_load_acq_int(&t->tids_in_use));
6877 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
6878 t->stid_base + t->nstids - 1, t->stids_in_use);
6882 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
6883 t->ftid_base + t->nftids - 1);
6887 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
6888 t->etid_base + t->netids - 1);
6891 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
6892 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
6893 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
6895 rc = sbuf_finish(sb);
6902 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
6904 struct adapter *sc = arg1;
6907 struct tp_err_stats stats;
6909 rc = sysctl_wire_old_buffer(req, 0);
6913 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6917 mtx_lock(&sc->reg_lock);
6918 t4_tp_get_err_stats(sc, &stats);
6919 mtx_unlock(&sc->reg_lock);
6921 if (sc->chip_params->nchan > 2) {
6922 sbuf_printf(sb, " channel 0 channel 1"
6923 " channel 2 channel 3\n");
6924 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
6925 stats.mac_in_errs[0], stats.mac_in_errs[1],
6926 stats.mac_in_errs[2], stats.mac_in_errs[3]);
6927 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
6928 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
6929 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
6930 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
6931 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
6932 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
6933 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
6934 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
6935 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
6936 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
6937 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
6938 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
6939 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
6940 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
6941 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
6942 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
6943 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
6944 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
6945 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
6946 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
6947 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
6949 sbuf_printf(sb, " channel 0 channel 1\n");
6950 sbuf_printf(sb, "macInErrs: %10u %10u\n",
6951 stats.mac_in_errs[0], stats.mac_in_errs[1]);
6952 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
6953 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
6954 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
6955 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
6956 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
6957 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
6958 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
6959 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
6960 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
6961 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
6962 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
6963 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
6964 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
6965 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
6968 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
6969 stats.ofld_no_neigh, stats.ofld_cong_defer);
6971 rc = sbuf_finish(sb);
6978 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
6980 struct adapter *sc = arg1;
6981 struct tp_params *tpp = &sc->params.tp;
6985 mask = tpp->la_mask >> 16;
6986 rc = sysctl_handle_int(oidp, &mask, 0, req);
6987 if (rc != 0 || req->newptr == NULL)
6991 tpp->la_mask = mask << 16;
6992 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
7004 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
7010 uint64_t mask = (1ULL << f->width) - 1;
7011 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
7012 ((uintmax_t)v >> f->start) & mask);
7014 if (line_size + len >= 79) {
7016 sbuf_printf(sb, "\n ");
7018 sbuf_printf(sb, "%s ", buf);
7019 line_size += len + 1;
7022 sbuf_printf(sb, "\n");
7025 static const struct field_desc tp_la0[] = {
7026 { "RcfOpCodeOut", 60, 4 },
7028 { "WcfState", 52, 4 },
7029 { "RcfOpcSrcOut", 50, 2 },
7030 { "CRxError", 49, 1 },
7031 { "ERxError", 48, 1 },
7032 { "SanityFailed", 47, 1 },
7033 { "SpuriousMsg", 46, 1 },
7034 { "FlushInputMsg", 45, 1 },
7035 { "FlushInputCpl", 44, 1 },
7036 { "RssUpBit", 43, 1 },
7037 { "RssFilterHit", 42, 1 },
7039 { "InitTcb", 31, 1 },
7040 { "LineNumber", 24, 7 },
7042 { "EdataOut", 22, 1 },
7044 { "CdataOut", 20, 1 },
7045 { "EreadPdu", 19, 1 },
7046 { "CreadPdu", 18, 1 },
7047 { "TunnelPkt", 17, 1 },
7048 { "RcfPeerFin", 16, 1 },
7049 { "RcfReasonOut", 12, 4 },
7050 { "TxCchannel", 10, 2 },
7051 { "RcfTxChannel", 8, 2 },
7052 { "RxEchannel", 6, 2 },
7053 { "RcfRxChannel", 5, 1 },
7054 { "RcfDataOutSrdy", 4, 1 },
7056 { "RxOoDvld", 2, 1 },
7057 { "RxCongestion", 1, 1 },
7058 { "TxCongestion", 0, 1 },
7062 static const struct field_desc tp_la1[] = {
7063 { "CplCmdIn", 56, 8 },
7064 { "CplCmdOut", 48, 8 },
7065 { "ESynOut", 47, 1 },
7066 { "EAckOut", 46, 1 },
7067 { "EFinOut", 45, 1 },
7068 { "ERstOut", 44, 1 },
7073 { "DataIn", 39, 1 },
7074 { "DataInVld", 38, 1 },
7076 { "RxBufEmpty", 36, 1 },
7078 { "RxFbCongestion", 34, 1 },
7079 { "TxFbCongestion", 33, 1 },
7080 { "TxPktSumSrdy", 32, 1 },
7081 { "RcfUlpType", 28, 4 },
7083 { "Ebypass", 26, 1 },
7085 { "Static0", 24, 1 },
7087 { "Cbypass", 22, 1 },
7089 { "CPktOut", 20, 1 },
7090 { "RxPagePoolFull", 18, 2 },
7091 { "RxLpbkPkt", 17, 1 },
7092 { "TxLpbkPkt", 16, 1 },
7093 { "RxVfValid", 15, 1 },
7094 { "SynLearned", 14, 1 },
7095 { "SetDelEntry", 13, 1 },
7096 { "SetInvEntry", 12, 1 },
7097 { "CpcmdDvld", 11, 1 },
7098 { "CpcmdSave", 10, 1 },
7099 { "RxPstructsFull", 8, 2 },
7100 { "EpcmdDvld", 7, 1 },
7101 { "EpcmdFlush", 6, 1 },
7102 { "EpcmdTrimPrefix", 5, 1 },
7103 { "EpcmdTrimPostfix", 4, 1 },
7104 { "ERssIp4Pkt", 3, 1 },
7105 { "ERssIp6Pkt", 2, 1 },
7106 { "ERssTcpUdpPkt", 1, 1 },
7107 { "ERssFceFipPkt", 0, 1 },
7111 static const struct field_desc tp_la2[] = {
7112 { "CplCmdIn", 56, 8 },
7113 { "MpsVfVld", 55, 1 },
7120 { "DataIn", 39, 1 },
7121 { "DataInVld", 38, 1 },
7123 { "RxBufEmpty", 36, 1 },
7125 { "RxFbCongestion", 34, 1 },
7126 { "TxFbCongestion", 33, 1 },
7127 { "TxPktSumSrdy", 32, 1 },
7128 { "RcfUlpType", 28, 4 },
7130 { "Ebypass", 26, 1 },
7132 { "Static0", 24, 1 },
7134 { "Cbypass", 22, 1 },
7136 { "CPktOut", 20, 1 },
7137 { "RxPagePoolFull", 18, 2 },
7138 { "RxLpbkPkt", 17, 1 },
7139 { "TxLpbkPkt", 16, 1 },
7140 { "RxVfValid", 15, 1 },
7141 { "SynLearned", 14, 1 },
7142 { "SetDelEntry", 13, 1 },
7143 { "SetInvEntry", 12, 1 },
7144 { "CpcmdDvld", 11, 1 },
7145 { "CpcmdSave", 10, 1 },
7146 { "RxPstructsFull", 8, 2 },
7147 { "EpcmdDvld", 7, 1 },
7148 { "EpcmdFlush", 6, 1 },
7149 { "EpcmdTrimPrefix", 5, 1 },
7150 { "EpcmdTrimPostfix", 4, 1 },
7151 { "ERssIp4Pkt", 3, 1 },
7152 { "ERssIp6Pkt", 2, 1 },
7153 { "ERssTcpUdpPkt", 1, 1 },
7154 { "ERssFceFipPkt", 0, 1 },
7159 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7162 field_desc_show(sb, *p, tp_la0);
7166 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7170 sbuf_printf(sb, "\n");
7171 field_desc_show(sb, p[0], tp_la0);
7172 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7173 field_desc_show(sb, p[1], tp_la0);
7177 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7181 sbuf_printf(sb, "\n");
7182 field_desc_show(sb, p[0], tp_la0);
7183 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7184 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7188 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7190 struct adapter *sc = arg1;
7195 void (*show_func)(struct sbuf *, uint64_t *, int);
7197 rc = sysctl_wire_old_buffer(req, 0);
7201 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7205 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7207 t4_tp_read_la(sc, buf, NULL);
7210 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7213 show_func = tp_la_show2;
7217 show_func = tp_la_show3;
7221 show_func = tp_la_show;
7224 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7225 (*show_func)(sb, p, i);
7227 rc = sbuf_finish(sb);
7234 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7236 struct adapter *sc = arg1;
7239 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7241 rc = sysctl_wire_old_buffer(req, 0);
7245 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7249 t4_get_chan_txrate(sc, nrate, orate);
7251 if (sc->chip_params->nchan > 2) {
7252 sbuf_printf(sb, " channel 0 channel 1"
7253 " channel 2 channel 3\n");
7254 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7255 nrate[0], nrate[1], nrate[2], nrate[3]);
7256 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7257 orate[0], orate[1], orate[2], orate[3]);
7259 sbuf_printf(sb, " channel 0 channel 1\n");
7260 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7261 nrate[0], nrate[1]);
7262 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7263 orate[0], orate[1]);
7266 rc = sbuf_finish(sb);
7273 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7275 struct adapter *sc = arg1;
7280 rc = sysctl_wire_old_buffer(req, 0);
7284 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7288 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7291 t4_ulprx_read_la(sc, buf);
7294 sbuf_printf(sb, " Pcmd Type Message"
7296 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7297 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7298 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7301 rc = sbuf_finish(sb);
7308 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7310 struct adapter *sc = arg1;
7314 rc = sysctl_wire_old_buffer(req, 0);
7318 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7322 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7323 if (G_STATSOURCE_T5(v) == 7) {
7324 if (G_STATMODE(v) == 0) {
7325 sbuf_printf(sb, "total %d, incomplete %d",
7326 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7327 t4_read_reg(sc, A_SGE_STAT_MATCH));
7328 } else if (G_STATMODE(v) == 1) {
7329 sbuf_printf(sb, "total %d, data overflow %d",
7330 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7331 t4_read_reg(sc, A_SGE_STAT_MATCH));
7334 rc = sbuf_finish(sb);
7341 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
7343 struct adapter *sc = arg1;
7344 struct tx_sched_class *tc;
7345 struct t4_sched_class_params p;
7347 int i, rc, port_id, flags, mbps, gbps;
7349 rc = sysctl_wire_old_buffer(req, 0);
7353 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7357 port_id = arg2 >> 16;
7358 MPASS(port_id < sc->params.nports);
7359 MPASS(sc->port[port_id] != NULL);
7361 MPASS(i < sc->chip_params->nsched_cls);
7362 tc = &sc->port[port_id]->tc[i];
7364 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7370 end_synchronized_op(sc, LOCK_HELD);
7372 if ((flags & TX_SC_OK) == 0) {
7373 sbuf_printf(sb, "none");
7377 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) {
7378 sbuf_printf(sb, "cl-wrr weight %u", p.weight);
7380 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL)
7381 sbuf_printf(sb, "cl-rl");
7382 else if (p.level == SCHED_CLASS_LEVEL_CH_RL)
7383 sbuf_printf(sb, "ch-rl");
7389 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) {
7390 /* XXX: top speed or actual link speed? */
7391 gbps = port_top_speed(sc->port[port_id]);
7392 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps);
7394 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) {
7395 switch (p.rateunit) {
7396 case SCHED_CLASS_RATEUNIT_BITS:
7397 mbps = p.maxrate / 1000;
7398 gbps = p.maxrate / 1000000;
7399 if (p.maxrate == gbps * 1000000)
7400 sbuf_printf(sb, " %uGbps", gbps);
7401 else if (p.maxrate == mbps * 1000)
7402 sbuf_printf(sb, " %uMbps", mbps);
7404 sbuf_printf(sb, " %uKbps", p.maxrate);
7406 case SCHED_CLASS_RATEUNIT_PKTS:
7407 sbuf_printf(sb, " %upps", p.maxrate);
7416 case SCHED_CLASS_MODE_CLASS:
7417 sbuf_printf(sb, " aggregate");
7419 case SCHED_CLASS_MODE_FLOW:
7420 sbuf_printf(sb, " per-flow");
7429 rc = sbuf_finish(sb);
7438 unit_conv(char *buf, size_t len, u_int val, u_int factor)
7440 u_int rem = val % factor;
7443 snprintf(buf, len, "%u", val / factor);
7445 while (rem % 10 == 0)
7447 snprintf(buf, len, "%u.%u", val / factor, rem);
7452 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
7454 struct adapter *sc = arg1;
7457 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7459 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7463 re = G_TIMERRESOLUTION(res);
7466 /* TCP timestamp tick */
7467 re = G_TIMESTAMPRESOLUTION(res);
7471 re = G_DELAYEDACKRESOLUTION(res);
7477 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
7479 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
7483 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
7485 struct adapter *sc = arg1;
7486 u_int res, dack_re, v;
7487 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7489 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7490 dack_re = G_DELAYEDACKRESOLUTION(res);
7491 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
7493 return (sysctl_handle_int(oidp, &v, 0, req));
7497 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
7499 struct adapter *sc = arg1;
7502 u_long tp_tick_us, v;
7503 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7505 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
7506 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
7507 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT ||
7508 reg == A_TP_FINWAIT2_TIMER);
7510 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
7511 tp_tick_us = (cclk_ps << tre) / 1000000;
7513 if (reg == A_TP_INIT_SRTT)
7514 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
7516 v = tp_tick_us * t4_read_reg(sc, reg);
7518 return (sysctl_handle_long(oidp, &v, 0, req));
7523 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
7527 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
7528 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
7530 if (fconf & F_FRAGMENTATION)
7531 mode |= T4_FILTER_IP_FRAGMENT;
7533 if (fconf & F_MPSHITTYPE)
7534 mode |= T4_FILTER_MPS_HIT_TYPE;
7536 if (fconf & F_MACMATCH)
7537 mode |= T4_FILTER_MAC_IDX;
7539 if (fconf & F_ETHERTYPE)
7540 mode |= T4_FILTER_ETH_TYPE;
7542 if (fconf & F_PROTOCOL)
7543 mode |= T4_FILTER_IP_PROTO;
7546 mode |= T4_FILTER_IP_TOS;
7549 mode |= T4_FILTER_VLAN;
7551 if (fconf & F_VNIC_ID) {
7552 mode |= T4_FILTER_VNIC;
7554 mode |= T4_FILTER_IC_VNIC;
7558 mode |= T4_FILTER_PORT;
7561 mode |= T4_FILTER_FCoE;
7567 mode_to_fconf(uint32_t mode)
7571 if (mode & T4_FILTER_IP_FRAGMENT)
7572 fconf |= F_FRAGMENTATION;
7574 if (mode & T4_FILTER_MPS_HIT_TYPE)
7575 fconf |= F_MPSHITTYPE;
7577 if (mode & T4_FILTER_MAC_IDX)
7578 fconf |= F_MACMATCH;
7580 if (mode & T4_FILTER_ETH_TYPE)
7581 fconf |= F_ETHERTYPE;
7583 if (mode & T4_FILTER_IP_PROTO)
7584 fconf |= F_PROTOCOL;
7586 if (mode & T4_FILTER_IP_TOS)
7589 if (mode & T4_FILTER_VLAN)
7592 if (mode & T4_FILTER_VNIC)
7595 if (mode & T4_FILTER_PORT)
7598 if (mode & T4_FILTER_FCoE)
7605 mode_to_iconf(uint32_t mode)
7608 if (mode & T4_FILTER_IC_VNIC)
7613 static int check_fspec_against_fconf_iconf(struct adapter *sc,
7614 struct t4_filter_specification *fs)
7616 struct tp_params *tpp = &sc->params.tp;
7619 if (fs->val.frag || fs->mask.frag)
7620 fconf |= F_FRAGMENTATION;
7622 if (fs->val.matchtype || fs->mask.matchtype)
7623 fconf |= F_MPSHITTYPE;
7625 if (fs->val.macidx || fs->mask.macidx)
7626 fconf |= F_MACMATCH;
7628 if (fs->val.ethtype || fs->mask.ethtype)
7629 fconf |= F_ETHERTYPE;
7631 if (fs->val.proto || fs->mask.proto)
7632 fconf |= F_PROTOCOL;
7634 if (fs->val.tos || fs->mask.tos)
7637 if (fs->val.vlan_vld || fs->mask.vlan_vld)
7640 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
7642 if (tpp->ingress_config & F_VNIC)
7646 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
7648 if ((tpp->ingress_config & F_VNIC) == 0)
7652 if (fs->val.iport || fs->mask.iport)
7655 if (fs->val.fcoe || fs->mask.fcoe)
7658 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
7665 get_filter_mode(struct adapter *sc, uint32_t *mode)
7667 struct tp_params *tpp = &sc->params.tp;
7670 * We trust the cached values of the relevant TP registers. This means
7671 * things work reliably only if writes to those registers are always via
7672 * t4_set_filter_mode.
7674 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
7680 set_filter_mode(struct adapter *sc, uint32_t mode)
7682 struct tp_params *tpp = &sc->params.tp;
7683 uint32_t fconf, iconf;
7686 iconf = mode_to_iconf(mode);
7687 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
7689 * For now we just complain if A_TP_INGRESS_CONFIG is not
7690 * already set to the correct value for the requested filter
7691 * mode. It's not clear if it's safe to write to this register
7692 * on the fly. (And we trust the cached value of the register).
7697 fconf = mode_to_fconf(mode);
7699 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7704 if (sc->tids.ftids_in_use > 0) {
7710 if (uld_active(sc, ULD_TOM)) {
7716 rc = -t4_set_filter_mode(sc, fconf);
7718 end_synchronized_op(sc, LOCK_HELD);
7722 static inline uint64_t
7723 get_filter_hits(struct adapter *sc, uint32_t fid)
7727 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
7728 (fid + sc->tids.ftid_base) * TCB_SIZE;
7733 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
7734 return (be64toh(hits));
7738 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
7739 return (be32toh(hits));
7744 get_filter(struct adapter *sc, struct t4_filter *t)
7746 int i, rc, nfilters = sc->tids.nftids;
7747 struct filter_entry *f;
7749 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7754 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
7755 t->idx >= nfilters) {
7756 t->idx = 0xffffffff;
7760 f = &sc->tids.ftid_tab[t->idx];
7761 for (i = t->idx; i < nfilters; i++, f++) {
7764 t->l2tidx = f->l2t ? f->l2t->idx : 0;
7765 t->smtidx = f->smtidx;
7767 t->hits = get_filter_hits(sc, t->idx);
7769 t->hits = UINT64_MAX;
7776 t->idx = 0xffffffff;
7778 end_synchronized_op(sc, LOCK_HELD);
7783 set_filter(struct adapter *sc, struct t4_filter *t)
7785 unsigned int nfilters, nports;
7786 struct filter_entry *f;
7789 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
7793 nfilters = sc->tids.nftids;
7794 nports = sc->params.nports;
7796 if (nfilters == 0) {
7801 if (!(sc->flags & FULL_INIT_DONE)) {
7806 if (t->idx >= nfilters) {
7811 /* Validate against the global filter mode and ingress config */
7812 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
7816 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
7821 if (t->fs.val.iport >= nports) {
7826 /* Can't specify an iq if not steering to it */
7827 if (!t->fs.dirsteer && t->fs.iq) {
7832 /* IPv6 filter idx must be 4 aligned */
7833 if (t->fs.type == 1 &&
7834 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
7839 if (sc->tids.ftid_tab == NULL) {
7840 KASSERT(sc->tids.ftids_in_use == 0,
7841 ("%s: no memory allocated but filters_in_use > 0",
7844 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
7845 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
7846 if (sc->tids.ftid_tab == NULL) {
7850 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
7853 for (i = 0; i < 4; i++) {
7854 f = &sc->tids.ftid_tab[t->idx + i];
7856 if (f->pending || f->valid) {
7865 if (t->fs.type == 0)
7869 f = &sc->tids.ftid_tab[t->idx];
7872 rc = set_filter_wr(sc, t->idx);
7874 end_synchronized_op(sc, 0);
7877 mtx_lock(&sc->tids.ftid_lock);
7879 if (f->pending == 0) {
7880 rc = f->valid ? 0 : EIO;
7884 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7885 PCATCH, "t4setfw", 0)) {
7890 mtx_unlock(&sc->tids.ftid_lock);
7896 del_filter(struct adapter *sc, struct t4_filter *t)
7898 unsigned int nfilters;
7899 struct filter_entry *f;
7902 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
7906 nfilters = sc->tids.nftids;
7908 if (nfilters == 0) {
7913 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
7914 t->idx >= nfilters) {
7919 if (!(sc->flags & FULL_INIT_DONE)) {
7924 f = &sc->tids.ftid_tab[t->idx];
7936 t->fs = f->fs; /* extra info for the caller */
7937 rc = del_filter_wr(sc, t->idx);
7941 end_synchronized_op(sc, 0);
7944 mtx_lock(&sc->tids.ftid_lock);
7946 if (f->pending == 0) {
7947 rc = f->valid ? EIO : 0;
7951 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7952 PCATCH, "t4delfw", 0)) {
7957 mtx_unlock(&sc->tids.ftid_lock);
7964 clear_filter(struct filter_entry *f)
7967 t4_l2t_release(f->l2t);
7969 bzero(f, sizeof (*f));
7973 set_filter_wr(struct adapter *sc, int fidx)
7975 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
7976 struct fw_filter_wr *fwr;
7977 unsigned int ftid, vnic_vld, vnic_vld_mask;
7978 struct wrq_cookie cookie;
7980 ASSERT_SYNCHRONIZED_OP(sc);
7982 if (f->fs.newdmac || f->fs.newvlan) {
7983 /* This filter needs an L2T entry; allocate one. */
7984 f->l2t = t4_l2t_alloc_switching(sc->l2t);
7987 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
7989 t4_l2t_release(f->l2t);
7995 /* Already validated against fconf, iconf */
7996 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
7997 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
7998 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
8002 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
8007 ftid = sc->tids.ftid_base + fidx;
8009 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8012 bzero(fwr, sizeof(*fwr));
8014 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
8015 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
8017 htobe32(V_FW_FILTER_WR_TID(ftid) |
8018 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
8019 V_FW_FILTER_WR_NOREPLY(0) |
8020 V_FW_FILTER_WR_IQ(f->fs.iq));
8021 fwr->del_filter_to_l2tix =
8022 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
8023 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
8024 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
8025 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
8026 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8027 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8028 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8029 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8030 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8031 f->fs.newvlan == VLAN_REWRITE) |
8032 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8033 f->fs.newvlan == VLAN_REWRITE) |
8034 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8035 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8036 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8037 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8038 fwr->ethtype = htobe16(f->fs.val.ethtype);
8039 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8040 fwr->frag_to_ovlan_vldm =
8041 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8042 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8043 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8044 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8045 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8046 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8048 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8049 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8050 fwr->maci_to_matchtypem =
8051 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8052 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8053 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8054 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8055 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8056 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8057 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8058 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8059 fwr->ptcl = f->fs.val.proto;
8060 fwr->ptclm = f->fs.mask.proto;
8061 fwr->ttyp = f->fs.val.tos;
8062 fwr->ttypm = f->fs.mask.tos;
8063 fwr->ivlan = htobe16(f->fs.val.vlan);
8064 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8065 fwr->ovlan = htobe16(f->fs.val.vnic);
8066 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8067 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8068 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8069 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8070 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8071 fwr->lp = htobe16(f->fs.val.dport);
8072 fwr->lpm = htobe16(f->fs.mask.dport);
8073 fwr->fp = htobe16(f->fs.val.sport);
8074 fwr->fpm = htobe16(f->fs.mask.sport);
8076 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8079 sc->tids.ftids_in_use++;
8081 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8086 del_filter_wr(struct adapter *sc, int fidx)
8088 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8089 struct fw_filter_wr *fwr;
8091 struct wrq_cookie cookie;
8093 ftid = sc->tids.ftid_base + fidx;
8095 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8098 bzero(fwr, sizeof (*fwr));
8100 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
8103 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8108 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8110 struct adapter *sc = iq->adapter;
8111 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
8112 unsigned int idx = GET_TID(rpl);
8114 struct filter_entry *f;
8116 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
8118 MPASS(iq == &sc->sge.fwq);
8119 MPASS(is_ftid(sc, idx));
8121 idx -= sc->tids.ftid_base;
8122 f = &sc->tids.ftid_tab[idx];
8123 rc = G_COOKIE(rpl->cookie);
8125 mtx_lock(&sc->tids.ftid_lock);
8126 if (rc == FW_FILTER_WR_FLT_ADDED) {
8127 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
8129 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
8130 f->pending = 0; /* asynchronous setup completed */
8133 if (rc != FW_FILTER_WR_FLT_DELETED) {
8134 /* Add or delete failed, display an error */
8136 "filter %u setup failed with error %u\n",
8141 sc->tids.ftids_in_use--;
8143 wakeup(&sc->tids.ftid_tab);
8144 mtx_unlock(&sc->tids.ftid_lock);
8150 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8153 MPASS(iq->set_tcb_rpl != NULL);
8154 return (iq->set_tcb_rpl(iq, rss, m));
8158 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8161 MPASS(iq->l2t_write_rpl != NULL);
8162 return (iq->l2t_write_rpl(iq, rss, m));
8166 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8170 if (cntxt->cid > M_CTXTQID)
8173 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8174 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8177 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8181 if (sc->flags & FW_OK) {
8182 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8189 * Read via firmware failed or wasn't even attempted. Read directly via
8192 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8194 end_synchronized_op(sc, 0);
8199 load_fw(struct adapter *sc, struct t4_data *fw)
8204 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8208 if (sc->flags & FULL_INIT_DONE) {
8213 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8214 if (fw_data == NULL) {
8219 rc = copyin(fw->data, fw_data, fw->len);
8221 rc = -t4_load_fw(sc, fw_data, fw->len);
8223 free(fw_data, M_CXGBE);
8225 end_synchronized_op(sc, 0);
8229 #define MAX_READ_BUF_SIZE (128 * 1024)
8231 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
8233 uint32_t addr, remaining, n;
8238 rc = validate_mem_range(sc, mr->addr, mr->len);
8242 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
8244 remaining = mr->len;
8245 dst = (void *)mr->data;
8248 n = min(remaining, MAX_READ_BUF_SIZE);
8249 read_via_memwin(sc, 2, addr, buf, n);
8251 rc = copyout(buf, dst, n);
8263 #undef MAX_READ_BUF_SIZE
8266 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8270 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8273 if (i2cd->len > sizeof(i2cd->data))
8276 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8279 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8280 i2cd->offset, i2cd->len, &i2cd->data[0]);
8281 end_synchronized_op(sc, 0);
8287 in_range(int val, int lo, int hi)
8290 return (val < 0 || (val <= hi && val >= lo));
8294 set_sched_class_config(struct adapter *sc, int minmax)
8301 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc");
8304 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1);
8305 end_synchronized_op(sc, 0);
8311 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p,
8314 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode;
8315 struct port_info *pi;
8316 struct tx_sched_class *tc;
8318 if (p->level == SCHED_CLASS_LEVEL_CL_RL)
8319 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
8320 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8321 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
8322 else if (p->level == SCHED_CLASS_LEVEL_CH_RL)
8323 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
8327 if (p->mode == SCHED_CLASS_MODE_CLASS)
8328 fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
8329 else if (p->mode == SCHED_CLASS_MODE_FLOW)
8330 fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
8334 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS)
8335 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
8336 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS)
8337 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
8341 if (p->ratemode == SCHED_CLASS_RATEMODE_REL)
8342 fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
8343 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS)
8344 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
8348 /* Vet our parameters ... */
8349 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1))
8352 pi = sc->port[sc->chan_map[p->channel]];
8355 MPASS(pi->tx_chan == p->channel);
8356 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */
8358 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) ||
8359 !in_range(p->minrate, 0, top_speed) ||
8360 !in_range(p->maxrate, 0, top_speed) ||
8361 !in_range(p->weight, 0, 100))
8365 * Translate any unset parameters into the firmware's
8366 * nomenclature and/or fail the call if the parameters
8369 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0)
8374 if (p->maxrate < 0) {
8375 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8376 p->level == SCHED_CLASS_LEVEL_CH_RL)
8381 if (p->weight < 0) {
8382 if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8387 if (p->pktsize < 0) {
8388 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8389 p->level == SCHED_CLASS_LEVEL_CH_RL)
8395 rc = begin_synchronized_op(sc, NULL,
8396 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp");
8399 tc = &pi->tc[p->cl];
8401 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode,
8402 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate,
8403 p->weight, p->pktsize, sleep_ok);
8405 tc->flags |= TX_SC_OK;
8408 * Unknown state at this point, see tc->params for what was
8411 tc->flags &= ~TX_SC_OK;
8413 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD);
8419 t4_set_sched_class(struct adapter *sc, struct t4_sched_params *p)
8422 if (p->type != SCHED_CLASS_TYPE_PACKET)
8425 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
8426 return (set_sched_class_config(sc, p->u.config.minmax));
8428 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
8429 return (set_sched_class_params(sc, &p->u.params, 1));
8435 t4_set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
8437 struct port_info *pi = NULL;
8439 struct sge_txq *txq;
8440 uint32_t fw_mnem, fw_queue, fw_class;
8443 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
8447 if (p->port >= sc->params.nports) {
8452 /* XXX: Only supported for the main VI. */
8453 pi = sc->port[p->port];
8455 if (!(vi->flags & VI_INIT_DONE)) {
8456 /* tx queues not set up yet */
8461 if (!in_range(p->queue, 0, vi->ntxq - 1) ||
8462 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) {
8468 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
8469 * Scheduling Class in this case).
8471 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
8472 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
8473 fw_class = p->cl < 0 ? 0xffffffff : p->cl;
8476 * If op.queue is non-negative, then we're only changing the scheduling
8477 * on a single specified TX queue.
8479 if (p->queue >= 0) {
8480 txq = &sc->sge.txq[vi->first_txq + p->queue];
8481 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8482 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8488 * Change the scheduling on all the TX queues for the
8491 for_each_txq(vi, i, txq) {
8492 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8493 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8501 end_synchronized_op(sc, 0);
8506 t4_os_find_pci_capability(struct adapter *sc, int cap)
8510 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8514 t4_os_pci_save_state(struct adapter *sc)
8517 struct pci_devinfo *dinfo;
8520 dinfo = device_get_ivars(dev);
8522 pci_cfg_save(dev, dinfo, 0);
8527 t4_os_pci_restore_state(struct adapter *sc)
8530 struct pci_devinfo *dinfo;
8533 dinfo = device_get_ivars(dev);
8535 pci_cfg_restore(dev, dinfo);
8540 t4_os_portmod_changed(const struct adapter *sc, int idx)
8542 struct port_info *pi = sc->port[idx];
8546 static const char *mod_str[] = {
8547 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8550 for_each_vi(pi, v, vi) {
8551 build_medialist(pi, &vi->media);
8554 ifp = pi->vi[0].ifp;
8555 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8556 if_printf(ifp, "transceiver unplugged.\n");
8557 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8558 if_printf(ifp, "unknown transceiver inserted.\n");
8559 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8560 if_printf(ifp, "unsupported transceiver inserted.\n");
8561 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8562 if_printf(ifp, "%s transceiver inserted.\n",
8563 mod_str[pi->mod_type]);
8565 if_printf(ifp, "transceiver (type %d) inserted.\n",
8571 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
8573 struct port_info *pi = sc->port[idx];
8582 pi->linkdnrc = reason;
8584 for_each_vi(pi, v, vi) {
8590 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
8591 if_link_state_change(ifp, LINK_STATE_UP);
8593 if_link_state_change(ifp, LINK_STATE_DOWN);
8599 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8603 sx_slock(&t4_list_lock);
8604 SLIST_FOREACH(sc, &t4_list, link) {
8606 * func should not make any assumptions about what state sc is
8607 * in - the only guarantee is that sc->sc_lock is a valid lock.
8611 sx_sunlock(&t4_list_lock);
8615 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
8619 struct adapter *sc = dev->si_drv1;
8621 rc = priv_check(td, PRIV_DRIVER);
8626 case CHELSIO_T4_GETREG: {
8627 struct t4_reg *edata = (struct t4_reg *)data;
8629 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8632 if (edata->size == 4)
8633 edata->val = t4_read_reg(sc, edata->addr);
8634 else if (edata->size == 8)
8635 edata->val = t4_read_reg64(sc, edata->addr);
8641 case CHELSIO_T4_SETREG: {
8642 struct t4_reg *edata = (struct t4_reg *)data;
8644 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8647 if (edata->size == 4) {
8648 if (edata->val & 0xffffffff00000000)
8650 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
8651 } else if (edata->size == 8)
8652 t4_write_reg64(sc, edata->addr, edata->val);
8657 case CHELSIO_T4_REGDUMP: {
8658 struct t4_regdump *regs = (struct t4_regdump *)data;
8659 int reglen = t4_get_regs_len(sc);
8662 if (regs->len < reglen) {
8663 regs->len = reglen; /* hint to the caller */
8668 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
8669 get_regs(sc, regs, buf);
8670 rc = copyout(buf, regs->data, reglen);
8674 case CHELSIO_T4_GET_FILTER_MODE:
8675 rc = get_filter_mode(sc, (uint32_t *)data);
8677 case CHELSIO_T4_SET_FILTER_MODE:
8678 rc = set_filter_mode(sc, *(uint32_t *)data);
8680 case CHELSIO_T4_GET_FILTER:
8681 rc = get_filter(sc, (struct t4_filter *)data);
8683 case CHELSIO_T4_SET_FILTER:
8684 rc = set_filter(sc, (struct t4_filter *)data);
8686 case CHELSIO_T4_DEL_FILTER:
8687 rc = del_filter(sc, (struct t4_filter *)data);
8689 case CHELSIO_T4_GET_SGE_CONTEXT:
8690 rc = get_sge_context(sc, (struct t4_sge_context *)data);
8692 case CHELSIO_T4_LOAD_FW:
8693 rc = load_fw(sc, (struct t4_data *)data);
8695 case CHELSIO_T4_GET_MEM:
8696 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
8698 case CHELSIO_T4_GET_I2C:
8699 rc = read_i2c(sc, (struct t4_i2c_data *)data);
8701 case CHELSIO_T4_CLEAR_STATS: {
8703 u_int port_id = *(uint32_t *)data;
8704 struct port_info *pi;
8707 if (port_id >= sc->params.nports)
8709 pi = sc->port[port_id];
8712 t4_clr_port_stats(sc, pi->tx_chan);
8713 pi->tx_parse_error = 0;
8714 mtx_lock(&sc->reg_lock);
8715 for_each_vi(pi, v, vi) {
8716 if (vi->flags & VI_INIT_DONE)
8717 t4_clr_vi_stats(sc, vi->viid);
8719 mtx_unlock(&sc->reg_lock);
8722 * Since this command accepts a port, clear stats for
8723 * all VIs on this port.
8725 for_each_vi(pi, v, vi) {
8726 if (vi->flags & VI_INIT_DONE) {
8727 struct sge_rxq *rxq;
8728 struct sge_txq *txq;
8729 struct sge_wrq *wrq;
8731 for_each_rxq(vi, i, rxq) {
8732 #if defined(INET) || defined(INET6)
8733 rxq->lro.lro_queued = 0;
8734 rxq->lro.lro_flushed = 0;
8737 rxq->vlan_extraction = 0;
8740 for_each_txq(vi, i, txq) {
8743 txq->vlan_insertion = 0;
8747 txq->txpkts0_wrs = 0;
8748 txq->txpkts1_wrs = 0;
8749 txq->txpkts0_pkts = 0;
8750 txq->txpkts1_pkts = 0;
8751 mp_ring_reset_stats(txq->r);
8755 /* nothing to clear for each ofld_rxq */
8757 for_each_ofld_txq(vi, i, wrq) {
8758 wrq->tx_wrs_direct = 0;
8759 wrq->tx_wrs_copied = 0;
8763 if (IS_MAIN_VI(vi)) {
8764 wrq = &sc->sge.ctrlq[pi->port_id];
8765 wrq->tx_wrs_direct = 0;
8766 wrq->tx_wrs_copied = 0;
8772 case CHELSIO_T4_SCHED_CLASS:
8773 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
8775 case CHELSIO_T4_SCHED_QUEUE:
8776 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
8778 case CHELSIO_T4_GET_TRACER:
8779 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
8781 case CHELSIO_T4_SET_TRACER:
8782 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
8792 t4_db_full(struct adapter *sc)
8795 CXGBE_UNIMPLEMENTED(__func__);
8799 t4_db_dropped(struct adapter *sc)
8802 CXGBE_UNIMPLEMENTED(__func__);
8807 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
8810 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
8811 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
8812 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
8813 V_HPZ3(pgsz_order[3]));
8817 toe_capability(struct vi_info *vi, int enable)
8820 struct port_info *pi = vi->pi;
8821 struct adapter *sc = pi->adapter;
8823 ASSERT_SYNCHRONIZED_OP(sc);
8825 if (!is_offload(sc))
8829 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
8830 /* TOE is already enabled. */
8835 * We need the port's queues around so that we're able to send
8836 * and receive CPLs to/from the TOE even if the ifnet for this
8837 * port has never been UP'd administratively.
8839 if (!(vi->flags & VI_INIT_DONE)) {
8840 rc = vi_full_init(vi);
8844 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
8845 rc = vi_full_init(&pi->vi[0]);
8850 if (isset(&sc->offload_map, pi->port_id)) {
8851 /* TOE is enabled on another VI of this port. */
8856 if (!uld_active(sc, ULD_TOM)) {
8857 rc = t4_activate_uld(sc, ULD_TOM);
8860 "You must kldload t4_tom.ko before trying "
8861 "to enable TOE on a cxgbe interface.\n");
8865 KASSERT(sc->tom_softc != NULL,
8866 ("%s: TOM activated but softc NULL", __func__));
8867 KASSERT(uld_active(sc, ULD_TOM),
8868 ("%s: TOM activated but flag not set", __func__));
8871 /* Activate iWARP and iSCSI too, if the modules are loaded. */
8872 if (!uld_active(sc, ULD_IWARP))
8873 (void) t4_activate_uld(sc, ULD_IWARP);
8874 if (!uld_active(sc, ULD_ISCSI))
8875 (void) t4_activate_uld(sc, ULD_ISCSI);
8878 setbit(&sc->offload_map, pi->port_id);
8882 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
8885 KASSERT(uld_active(sc, ULD_TOM),
8886 ("%s: TOM never initialized?", __func__));
8887 clrbit(&sc->offload_map, pi->port_id);
8894 * Add an upper layer driver to the global list.
8897 t4_register_uld(struct uld_info *ui)
8902 sx_xlock(&t4_uld_list_lock);
8903 SLIST_FOREACH(u, &t4_uld_list, link) {
8904 if (u->uld_id == ui->uld_id) {
8910 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
8913 sx_xunlock(&t4_uld_list_lock);
8918 t4_unregister_uld(struct uld_info *ui)
8923 sx_xlock(&t4_uld_list_lock);
8925 SLIST_FOREACH(u, &t4_uld_list, link) {
8927 if (ui->refcount > 0) {
8932 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
8938 sx_xunlock(&t4_uld_list_lock);
8943 t4_activate_uld(struct adapter *sc, int id)
8946 struct uld_info *ui;
8948 ASSERT_SYNCHRONIZED_OP(sc);
8950 if (id < 0 || id > ULD_MAX)
8952 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
8954 sx_slock(&t4_uld_list_lock);
8956 SLIST_FOREACH(ui, &t4_uld_list, link) {
8957 if (ui->uld_id == id) {
8958 if (!(sc->flags & FULL_INIT_DONE)) {
8959 rc = adapter_full_init(sc);
8964 rc = ui->activate(sc);
8966 setbit(&sc->active_ulds, id);
8973 sx_sunlock(&t4_uld_list_lock);
8979 t4_deactivate_uld(struct adapter *sc, int id)
8982 struct uld_info *ui;
8984 ASSERT_SYNCHRONIZED_OP(sc);
8986 if (id < 0 || id > ULD_MAX)
8990 sx_slock(&t4_uld_list_lock);
8992 SLIST_FOREACH(ui, &t4_uld_list, link) {
8993 if (ui->uld_id == id) {
8994 rc = ui->deactivate(sc);
8996 clrbit(&sc->active_ulds, id);
9003 sx_sunlock(&t4_uld_list_lock);
9009 uld_active(struct adapter *sc, int uld_id)
9012 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9014 return (isset(&sc->active_ulds, uld_id));
9019 * Come up with reasonable defaults for some of the tunables, provided they're
9020 * not set by the user (in which case we'll use the values as is).
9023 tweak_tunables(void)
9025 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9027 if (t4_ntxq10g < 1) {
9029 t4_ntxq10g = rss_getnumbuckets();
9031 t4_ntxq10g = min(nc, NTXQ_10G);
9035 if (t4_ntxq1g < 1) {
9037 /* XXX: way too many for 1GbE? */
9038 t4_ntxq1g = rss_getnumbuckets();
9040 t4_ntxq1g = min(nc, NTXQ_1G);
9045 t4_ntxq_vi = min(nc, NTXQ_VI);
9047 if (t4_nrxq10g < 1) {
9049 t4_nrxq10g = rss_getnumbuckets();
9051 t4_nrxq10g = min(nc, NRXQ_10G);
9055 if (t4_nrxq1g < 1) {
9057 /* XXX: way too many for 1GbE? */
9058 t4_nrxq1g = rss_getnumbuckets();
9060 t4_nrxq1g = min(nc, NRXQ_1G);
9065 t4_nrxq_vi = min(nc, NRXQ_VI);
9068 if (t4_nofldtxq10g < 1)
9069 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
9071 if (t4_nofldtxq1g < 1)
9072 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
9074 if (t4_nofldtxq_vi < 1)
9075 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI);
9077 if (t4_nofldrxq10g < 1)
9078 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
9080 if (t4_nofldrxq1g < 1)
9081 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
9083 if (t4_nofldrxq_vi < 1)
9084 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI);
9086 if (t4_toecaps_allowed == -1)
9087 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9089 if (t4_rdmacaps_allowed == -1) {
9090 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9091 FW_CAPS_CONFIG_RDMA_RDMAC;
9094 if (t4_iscsicaps_allowed == -1) {
9095 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9096 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9097 FW_CAPS_CONFIG_ISCSI_T10DIF;
9100 if (t4_toecaps_allowed == -1)
9101 t4_toecaps_allowed = 0;
9103 if (t4_rdmacaps_allowed == -1)
9104 t4_rdmacaps_allowed = 0;
9106 if (t4_iscsicaps_allowed == -1)
9107 t4_iscsicaps_allowed = 0;
9111 if (t4_nnmtxq_vi < 1)
9112 t4_nnmtxq_vi = min(nc, NNMTXQ_VI);
9114 if (t4_nnmrxq_vi < 1)
9115 t4_nnmrxq_vi = min(nc, NNMRXQ_VI);
9118 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
9119 t4_tmr_idx_10g = TMR_IDX_10G;
9121 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
9122 t4_pktc_idx_10g = PKTC_IDX_10G;
9124 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
9125 t4_tmr_idx_1g = TMR_IDX_1G;
9127 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
9128 t4_pktc_idx_1g = PKTC_IDX_1G;
9130 if (t4_qsize_txq < 128)
9133 if (t4_qsize_rxq < 128)
9135 while (t4_qsize_rxq & 7)
9138 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9143 t4_dump_tcb(struct adapter *sc, int tid)
9145 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9147 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9148 save = t4_read_reg(sc, reg);
9149 base = sc->memwin[2].mw_base;
9151 /* Dump TCB for the tid */
9152 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9153 tcb_addr += tid * TCB_SIZE;
9157 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9159 pf = V_PFNUM(sc->pf);
9160 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9162 t4_write_reg(sc, reg, win_pos | pf);
9163 t4_read_reg(sc, reg);
9165 off = tcb_addr - win_pos;
9166 for (i = 0; i < 4; i++) {
9168 for (j = 0; j < 8; j++, off += 4)
9169 buf[j] = htonl(t4_read_reg(sc, base + off));
9171 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9172 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9176 t4_write_reg(sc, reg, save);
9177 t4_read_reg(sc, reg);
9181 t4_dump_devlog(struct adapter *sc)
9183 struct devlog_params *dparams = &sc->params.devlog;
9184 struct fw_devlog_e e;
9185 int i, first, j, m, nentries, rc;
9186 uint64_t ftstamp = UINT64_MAX;
9188 if (dparams->start == 0) {
9189 db_printf("devlog params not valid\n");
9193 nentries = dparams->size / sizeof(struct fw_devlog_e);
9194 m = fwmtype_to_hwmtype(dparams->memtype);
9196 /* Find the first entry. */
9198 for (i = 0; i < nentries && !db_pager_quit; i++) {
9199 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9200 sizeof(e), (void *)&e);
9204 if (e.timestamp == 0)
9207 e.timestamp = be64toh(e.timestamp);
9208 if (e.timestamp < ftstamp) {
9209 ftstamp = e.timestamp;
9219 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9220 sizeof(e), (void *)&e);
9224 if (e.timestamp == 0)
9227 e.timestamp = be64toh(e.timestamp);
9228 e.seqno = be32toh(e.seqno);
9229 for (j = 0; j < 8; j++)
9230 e.params[j] = be32toh(e.params[j]);
9232 db_printf("%10d %15ju %8s %8s ",
9233 e.seqno, e.timestamp,
9234 (e.level < nitems(devlog_level_strings) ?
9235 devlog_level_strings[e.level] : "UNKNOWN"),
9236 (e.facility < nitems(devlog_facility_strings) ?
9237 devlog_facility_strings[e.facility] : "UNKNOWN"));
9238 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
9239 e.params[3], e.params[4], e.params[5], e.params[6],
9242 if (++i == nentries)
9244 } while (i != first && !db_pager_quit);
9247 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
9248 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
9250 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
9257 t = db_read_token();
9259 dev = device_lookup_by_name(db_tok_string);
9264 db_printf("usage: show t4 devlog <nexus>\n");
9269 db_printf("device not found\n");
9273 t4_dump_devlog(device_get_softc(dev));
9276 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
9285 t = db_read_token();
9287 dev = device_lookup_by_name(db_tok_string);
9288 t = db_read_token();
9290 tid = db_tok_number;
9297 db_printf("usage: show t4 tcb <nexus> <tid>\n");
9302 db_printf("device not found\n");
9306 db_printf("invalid tid\n");
9310 t4_dump_tcb(device_get_softc(dev), tid);
9314 static struct sx mlu; /* mod load unload */
9315 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
9318 mod_event(module_t mod, int cmd, void *arg)
9321 static int loaded = 0;
9326 if (loaded++ == 0) {
9328 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
9329 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
9330 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
9331 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
9332 sx_init(&t4_list_lock, "T4/T5 adapters");
9333 SLIST_INIT(&t4_list);
9335 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
9336 SLIST_INIT(&t4_uld_list);
9338 t4_tracer_modload();
9346 if (--loaded == 0) {
9349 sx_slock(&t4_list_lock);
9350 if (!SLIST_EMPTY(&t4_list)) {
9352 sx_sunlock(&t4_list_lock);
9356 sx_slock(&t4_uld_list_lock);
9357 if (!SLIST_EMPTY(&t4_uld_list)) {
9359 sx_sunlock(&t4_uld_list_lock);
9360 sx_sunlock(&t4_list_lock);
9365 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
9366 uprintf("%ju clusters with custom free routine "
9367 "still is use.\n", t4_sge_extfree_refs());
9368 pause("t4unload", 2 * hz);
9371 sx_sunlock(&t4_uld_list_lock);
9373 sx_sunlock(&t4_list_lock);
9375 if (t4_sge_extfree_refs() == 0) {
9376 t4_tracer_modunload();
9378 sx_destroy(&t4_uld_list_lock);
9380 sx_destroy(&t4_list_lock);
9385 loaded++; /* undo earlier decrement */
9396 static devclass_t t4_devclass, t5_devclass;
9397 static devclass_t cxgbe_devclass, cxl_devclass;
9398 static devclass_t vcxgbe_devclass, vcxl_devclass;
9400 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9401 MODULE_VERSION(t4nex, 1);
9402 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9404 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9405 MODULE_VERSION(t5nex, 1);
9406 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9408 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9409 MODULE_VERSION(cxgbe, 1);
9411 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9412 MODULE_VERSION(cxl, 1);
9414 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9415 MODULE_VERSION(vcxgbe, 1);
9417 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9418 MODULE_VERSION(vcxl, 1);