2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include "opt_inet6.h"
35 #include <sys/param.h>
38 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/counter.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
46 #include <sys/pciio.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pci_private.h>
50 #include <sys/firmware.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_types.h>
59 #include <net/if_dl.h>
60 #include <net/if_vlan_var.h>
62 #include <net/rss_config.h>
64 #if defined(__i386__) || defined(__amd64__)
70 #include <ddb/db_lex.h>
73 #include "common/common.h"
74 #include "common/t4_msg.h"
75 #include "common/t4_regs.h"
76 #include "common/t4_regs_values.h"
79 #include "t4_mp_ring.h"
81 /* T4 bus driver interface */
82 static int t4_probe(device_t);
83 static int t4_attach(device_t);
84 static int t4_detach(device_t);
85 static device_method_t t4_methods[] = {
86 DEVMETHOD(device_probe, t4_probe),
87 DEVMETHOD(device_attach, t4_attach),
88 DEVMETHOD(device_detach, t4_detach),
92 static driver_t t4_driver = {
95 sizeof(struct adapter)
99 /* T4 port (cxgbe) interface */
100 static int cxgbe_probe(device_t);
101 static int cxgbe_attach(device_t);
102 static int cxgbe_detach(device_t);
103 device_method_t cxgbe_methods[] = {
104 DEVMETHOD(device_probe, cxgbe_probe),
105 DEVMETHOD(device_attach, cxgbe_attach),
106 DEVMETHOD(device_detach, cxgbe_detach),
109 static driver_t cxgbe_driver = {
112 sizeof(struct port_info)
115 /* T4 VI (vcxgbe) interface */
116 static int vcxgbe_probe(device_t);
117 static int vcxgbe_attach(device_t);
118 static int vcxgbe_detach(device_t);
119 static device_method_t vcxgbe_methods[] = {
120 DEVMETHOD(device_probe, vcxgbe_probe),
121 DEVMETHOD(device_attach, vcxgbe_attach),
122 DEVMETHOD(device_detach, vcxgbe_detach),
125 static driver_t vcxgbe_driver = {
128 sizeof(struct vi_info)
131 static d_ioctl_t t4_ioctl;
133 static struct cdevsw t4_cdevsw = {
134 .d_version = D_VERSION,
139 /* T5 bus driver interface */
140 static int t5_probe(device_t);
141 static device_method_t t5_methods[] = {
142 DEVMETHOD(device_probe, t5_probe),
143 DEVMETHOD(device_attach, t4_attach),
144 DEVMETHOD(device_detach, t4_detach),
148 static driver_t t5_driver = {
151 sizeof(struct adapter)
155 /* T5 port (cxl) interface */
156 static driver_t cxl_driver = {
159 sizeof(struct port_info)
162 /* T5 VI (vcxl) interface */
163 static driver_t vcxl_driver = {
166 sizeof(struct vi_info)
169 /* T6 bus driver interface */
170 static int t6_probe(device_t);
171 static device_method_t t6_methods[] = {
172 DEVMETHOD(device_probe, t6_probe),
173 DEVMETHOD(device_attach, t4_attach),
174 DEVMETHOD(device_detach, t4_detach),
178 static driver_t t6_driver = {
181 sizeof(struct adapter)
185 /* T6 port (cc) interface */
186 static driver_t cc_driver = {
189 sizeof(struct port_info)
192 /* T6 VI (vcc) interface */
193 static driver_t vcc_driver = {
196 sizeof(struct vi_info)
199 /* ifnet + media interface */
200 static void cxgbe_init(void *);
201 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
202 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
203 static void cxgbe_qflush(struct ifnet *);
204 static int cxgbe_media_change(struct ifnet *);
205 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
207 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
210 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
211 * then ADAPTER_LOCK, then t4_uld_list_lock.
213 static struct sx t4_list_lock;
214 SLIST_HEAD(, adapter) t4_list;
216 static struct sx t4_uld_list_lock;
217 SLIST_HEAD(, uld_info) t4_uld_list;
221 * Tunables. See tweak_tunables() too.
223 * Each tunable is set to a default value here if it's known at compile-time.
224 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
225 * provide a reasonable default when the driver is loaded.
227 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
228 * T5 are under hw.cxl.
232 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
236 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
240 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
244 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
248 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
251 static int t4_ntxq_vi = -1;
252 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
255 static int t4_nrxq_vi = -1;
256 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
258 static int t4_rsrv_noflowq = 0;
259 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
262 #define NOFLDTXQ_10G 8
263 static int t4_nofldtxq10g = -1;
264 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
266 #define NOFLDRXQ_10G 2
267 static int t4_nofldrxq10g = -1;
268 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
270 #define NOFLDTXQ_1G 2
271 static int t4_nofldtxq1g = -1;
272 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
274 #define NOFLDRXQ_1G 1
275 static int t4_nofldrxq1g = -1;
276 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
278 #define NOFLDTXQ_VI 1
279 static int t4_nofldtxq_vi = -1;
280 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
282 #define NOFLDRXQ_VI 1
283 static int t4_nofldrxq_vi = -1;
284 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
289 static int t4_nnmtxq_vi = -1;
290 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
293 static int t4_nnmrxq_vi = -1;
294 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
298 * Holdoff parameters for 10G and 1G ports.
300 #define TMR_IDX_10G 1
301 int t4_tmr_idx_10g = TMR_IDX_10G;
302 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
304 #define PKTC_IDX_10G (-1)
305 int t4_pktc_idx_10g = PKTC_IDX_10G;
306 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
309 int t4_tmr_idx_1g = TMR_IDX_1G;
310 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
312 #define PKTC_IDX_1G (-1)
313 int t4_pktc_idx_1g = PKTC_IDX_1G;
314 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
317 * Size (# of entries) of each tx and rx queue.
319 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
320 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
322 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
323 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
326 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
328 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
329 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
332 * Configuration file.
334 #define DEFAULT_CF "default"
335 #define FLASH_CF "flash"
336 #define UWIRE_CF "uwire"
337 #define FPGA_CF "fpga"
338 static char t4_cfg_file[32] = DEFAULT_CF;
339 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
342 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
343 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
344 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
345 * mark or when signalled to do so, 0 to never emit PAUSE.
347 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
348 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
351 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
352 * encouraged respectively).
354 static unsigned int t4_fw_install = 1;
355 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
358 * ASIC features that will be used. Disable the ones you don't want so that the
359 * chip resources aren't wasted on features that will not be used.
361 static int t4_nbmcaps_allowed = 0;
362 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
364 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
365 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
367 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
368 FW_CAPS_CONFIG_SWITCH_EGRESS;
369 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
371 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
372 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
374 static int t4_toecaps_allowed = -1;
375 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
377 static int t4_rdmacaps_allowed = -1;
378 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
380 static int t4_cryptocaps_allowed = 0;
381 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed);
383 static int t4_iscsicaps_allowed = -1;
384 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
386 static int t4_fcoecaps_allowed = 0;
387 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
389 static int t5_write_combine = 0;
390 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
392 static int t4_num_vis = 1;
393 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
395 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
396 static int vi_mac_funcs[] = {
399 FW_VI_FUNC_OPENISCSI,
405 struct intrs_and_queues {
406 uint16_t intr_type; /* INTx, MSI, or MSI-X */
407 uint16_t nirq; /* Total # of vectors */
408 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
409 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
410 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
411 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
412 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
413 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
414 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
415 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
416 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
417 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
418 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
420 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
421 uint16_t ntxq_vi; /* # of NIC txq's */
422 uint16_t nrxq_vi; /* # of NIC rxq's */
423 uint16_t nofldtxq_vi; /* # of TOE txq's */
424 uint16_t nofldrxq_vi; /* # of TOE rxq's */
425 uint16_t nnmtxq_vi; /* # of netmap txq's */
426 uint16_t nnmrxq_vi; /* # of netmap rxq's */
429 struct filter_entry {
430 uint32_t valid:1; /* filter allocated and valid */
431 uint32_t locked:1; /* filter is administratively locked */
432 uint32_t pending:1; /* filter action is pending firmware reply */
433 uint32_t smtidx:8; /* Source MAC Table index for smac */
434 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
436 struct t4_filter_specification fs;
439 static void setup_memwin(struct adapter *);
440 static void position_memwin(struct adapter *, int, uint32_t);
441 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
442 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
444 static inline int write_via_memwin(struct adapter *, int, uint32_t,
445 const uint32_t *, int);
446 static int validate_mem_range(struct adapter *, uint32_t, int);
447 static int fwmtype_to_hwmtype(int);
448 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
450 static int fixup_devlog_params(struct adapter *);
451 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
452 struct intrs_and_queues *);
453 static int prep_firmware(struct adapter *);
454 static int partition_resources(struct adapter *, const struct firmware *,
456 static int get_params__pre_init(struct adapter *);
457 static int get_params__post_init(struct adapter *);
458 static int set_params__post_init(struct adapter *);
459 static void t4_set_desc(struct adapter *);
460 static void build_medialist(struct port_info *, struct ifmedia *);
461 static int cxgbe_init_synchronized(struct vi_info *);
462 static int cxgbe_uninit_synchronized(struct vi_info *);
463 static void quiesce_txq(struct adapter *, struct sge_txq *);
464 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
465 static void quiesce_iq(struct adapter *, struct sge_iq *);
466 static void quiesce_fl(struct adapter *, struct sge_fl *);
467 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
468 driver_intr_t *, void *, char *);
469 static int t4_free_irq(struct adapter *, struct irq *);
470 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
471 static void vi_refresh_stats(struct adapter *, struct vi_info *);
472 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
473 static void cxgbe_tick(void *);
474 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
475 static void cxgbe_sysctls(struct port_info *);
476 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
477 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
478 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
479 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
480 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
481 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
482 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
483 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
484 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
485 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
486 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
488 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
489 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
490 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
491 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
492 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
493 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
494 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
495 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
496 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
497 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
498 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
499 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
500 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
501 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
502 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
503 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
504 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
505 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
506 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
507 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
508 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
509 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
510 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
511 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
512 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
513 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
514 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
515 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
516 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
519 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
520 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
521 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
523 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
524 static uint32_t mode_to_fconf(uint32_t);
525 static uint32_t mode_to_iconf(uint32_t);
526 static int check_fspec_against_fconf_iconf(struct adapter *,
527 struct t4_filter_specification *);
528 static int get_filter_mode(struct adapter *, uint32_t *);
529 static int set_filter_mode(struct adapter *, uint32_t);
530 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
531 static int get_filter(struct adapter *, struct t4_filter *);
532 static int set_filter(struct adapter *, struct t4_filter *);
533 static int del_filter(struct adapter *, struct t4_filter *);
534 static void clear_filter(struct filter_entry *);
535 static int set_filter_wr(struct adapter *, int);
536 static int del_filter_wr(struct adapter *, int);
537 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
539 static int get_sge_context(struct adapter *, struct t4_sge_context *);
540 static int load_fw(struct adapter *, struct t4_data *);
541 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
542 static int read_i2c(struct adapter *, struct t4_i2c_data *);
544 static int toe_capability(struct vi_info *, int);
546 static int mod_event(module_t, int, void *);
552 {0xa000, "Chelsio Terminator 4 FPGA"},
553 {0x4400, "Chelsio T440-dbg"},
554 {0x4401, "Chelsio T420-CR"},
555 {0x4402, "Chelsio T422-CR"},
556 {0x4403, "Chelsio T440-CR"},
557 {0x4404, "Chelsio T420-BCH"},
558 {0x4405, "Chelsio T440-BCH"},
559 {0x4406, "Chelsio T440-CH"},
560 {0x4407, "Chelsio T420-SO"},
561 {0x4408, "Chelsio T420-CX"},
562 {0x4409, "Chelsio T420-BT"},
563 {0x440a, "Chelsio T404-BT"},
564 {0x440e, "Chelsio T440-LP-CR"},
566 {0xb000, "Chelsio Terminator 5 FPGA"},
567 {0x5400, "Chelsio T580-dbg"},
568 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
569 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
570 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
571 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
572 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
573 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
574 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
575 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
576 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
577 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
578 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
579 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
580 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
582 {0x5404, "Chelsio T520-BCH"},
583 {0x5405, "Chelsio T540-BCH"},
584 {0x5406, "Chelsio T540-CH"},
585 {0x5408, "Chelsio T520-CX"},
586 {0x540b, "Chelsio B520-SR"},
587 {0x540c, "Chelsio B504-BT"},
588 {0x540f, "Chelsio Amsterdam"},
589 {0x5413, "Chelsio T580-CHR"},
592 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
593 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
594 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
595 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
596 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
597 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
598 {0x6410, "Chelsio T62100-DBG"}, /* 2 x 40/50/100G, debug */
603 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
604 * exactly the same for both rxq and ofld_rxq.
606 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
607 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
609 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
612 t4_probe(device_t dev)
615 uint16_t v = pci_get_vendor(dev);
616 uint16_t d = pci_get_device(dev);
617 uint8_t f = pci_get_function(dev);
619 if (v != PCI_VENDOR_ID_CHELSIO)
622 /* Attach only to PF0 of the FPGA */
623 if (d == 0xa000 && f != 0)
626 for (i = 0; i < nitems(t4_pciids); i++) {
627 if (d == t4_pciids[i].device) {
628 device_set_desc(dev, t4_pciids[i].desc);
629 return (BUS_PROBE_DEFAULT);
637 t5_probe(device_t dev)
640 uint16_t v = pci_get_vendor(dev);
641 uint16_t d = pci_get_device(dev);
642 uint8_t f = pci_get_function(dev);
644 if (v != PCI_VENDOR_ID_CHELSIO)
647 /* Attach only to PF0 of the FPGA */
648 if (d == 0xb000 && f != 0)
651 for (i = 0; i < nitems(t5_pciids); i++) {
652 if (d == t5_pciids[i].device) {
653 device_set_desc(dev, t5_pciids[i].desc);
654 return (BUS_PROBE_DEFAULT);
662 t6_probe(device_t dev)
665 uint16_t v = pci_get_vendor(dev);
666 uint16_t d = pci_get_device(dev);
668 if (v != PCI_VENDOR_ID_CHELSIO)
671 for (i = 0; i < nitems(t6_pciids); i++) {
672 if (d == t6_pciids[i].device) {
673 device_set_desc(dev, t6_pciids[i].desc);
674 return (BUS_PROBE_DEFAULT);
682 t5_attribute_workaround(device_t dev)
688 * The T5 chips do not properly echo the No Snoop and Relaxed
689 * Ordering attributes when replying to a TLP from a Root
690 * Port. As a workaround, find the parent Root Port and
691 * disable No Snoop and Relaxed Ordering. Note that this
692 * affects all devices under this root port.
694 root_port = pci_find_pcie_root_port(dev);
695 if (root_port == NULL) {
696 device_printf(dev, "Unable to find parent root port\n");
700 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
701 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
702 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
704 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
705 device_get_nameunit(root_port));
708 static const struct devnames devnames[] = {
710 .nexus_name = "t4nex",
711 .ifnet_name = "cxgbe",
712 .vi_ifnet_name = "vcxgbe",
713 .pf03_drv_name = "t4iov",
714 .vf_nexus_name = "t4vf",
715 .vf_ifnet_name = "cxgbev"
717 .nexus_name = "t5nex",
719 .vi_ifnet_name = "vcxl",
720 .pf03_drv_name = "t5iov",
721 .vf_nexus_name = "t5vf",
722 .vf_ifnet_name = "cxlv"
724 .nexus_name = "t6nex",
726 .vi_ifnet_name = "vcc",
727 .pf03_drv_name = "t6iov",
728 .vf_nexus_name = "t6vf",
729 .vf_ifnet_name = "ccv"
734 t4_init_devnames(struct adapter *sc)
739 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
740 sc->names = &devnames[id - CHELSIO_T4];
742 device_printf(sc->dev, "chip id %d is not supported.\n", id);
748 t4_attach(device_t dev)
751 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
752 struct make_dev_args mda;
753 struct intrs_and_queues iaq;
757 int ofld_rqidx, ofld_tqidx;
760 int nm_rqidx, nm_tqidx;
764 sc = device_get_softc(dev);
766 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
768 if ((pci_get_device(dev) & 0xff00) == 0x5400)
769 t5_attribute_workaround(dev);
770 pci_enable_busmaster(dev);
771 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
774 pci_set_max_read_req(dev, 4096);
775 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
776 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
777 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
779 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
782 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
783 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
785 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
786 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
787 device_get_nameunit(dev));
789 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
790 device_get_nameunit(dev));
791 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
794 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
795 TAILQ_INIT(&sc->sfl);
796 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
798 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
800 rc = t4_map_bars_0_and_4(sc);
802 goto done; /* error message displayed already */
804 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
806 /* Prepare the adapter for operation. */
807 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
808 rc = -t4_prep_adapter(sc, buf);
811 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
816 * This is the real PF# to which we're attaching. Works from within PCI
817 * passthrough environments too, where pci_get_function() could return a
818 * different PF# depending on the passthrough configuration. We need to
819 * use the real PF# in all our communication with the firmware.
821 j = t4_read_reg(sc, A_PL_WHOAMI);
822 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
825 t4_init_devnames(sc);
826 if (sc->names == NULL) {
828 goto done; /* error message displayed already */
832 * Do this really early, with the memory windows set up even before the
833 * character device. The userland tool's register i/o and mem read
834 * will work even in "recovery mode".
837 if (t4_init_devlog_params(sc, 0) == 0)
838 fixup_devlog_params(sc);
839 make_dev_args_init(&mda);
840 mda.mda_devsw = &t4_cdevsw;
841 mda.mda_uid = UID_ROOT;
842 mda.mda_gid = GID_WHEEL;
844 mda.mda_si_drv1 = sc;
845 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
847 device_printf(dev, "failed to create nexus char device: %d.\n",
850 /* Go no further if recovery mode has been requested. */
851 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
852 device_printf(dev, "recovery mode.\n");
856 #if defined(__i386__)
857 if ((cpu_feature & CPUID_CX8) == 0) {
858 device_printf(dev, "64 bit atomics not available.\n");
864 /* Prepare the firmware for operation */
865 rc = prep_firmware(sc);
867 goto done; /* error message displayed already */
869 rc = get_params__post_init(sc);
871 goto done; /* error message displayed already */
873 rc = set_params__post_init(sc);
875 goto done; /* error message displayed already */
877 rc = t4_map_bar_2(sc);
879 goto done; /* error message displayed already */
881 rc = t4_create_dma_tag(sc);
883 goto done; /* error message displayed already */
886 * Number of VIs to create per-port. The first VI is the "main" regular
887 * VI for the port. The rest are additional virtual interfaces on the
888 * same physical port. Note that the main VI does not have native
889 * netmap support but the extra VIs do.
891 * Limit the number of VIs per port to the number of available
892 * MAC addresses per port.
895 num_vis = t4_num_vis;
898 if (num_vis > nitems(vi_mac_funcs)) {
899 num_vis = nitems(vi_mac_funcs);
900 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
904 * First pass over all the ports - allocate VIs and initialize some
905 * basic parameters like mac address, port type, etc. We also figure
906 * out whether a port is 10G or 1G and use that information when
907 * calculating how many interrupts to attempt to allocate.
910 for_each_port(sc, i) {
911 struct port_info *pi;
913 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
916 /* These must be set before t4_port_init */
920 * XXX: vi[0] is special so we can't delay this allocation until
921 * pi->nvi's final value is known.
923 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
927 * Allocate the "main" VI and initialize parameters
930 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
932 device_printf(dev, "unable to initialize port %d: %d\n",
934 free(pi->vi, M_CXGBE);
940 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX);
941 pi->link_cfg.requested_fc |= t4_pause_settings;
942 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX);
943 pi->link_cfg.fc |= t4_pause_settings;
945 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
947 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
948 free(pi->vi, M_CXGBE);
954 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
955 device_get_nameunit(dev), i);
956 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
957 sc->chan_map[pi->tx_chan] = i;
959 pi->tc = malloc(sizeof(struct tx_sched_class) *
960 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
962 if (port_top_speed(pi) >= 10) {
970 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1);
971 if (pi->dev == NULL) {
973 "failed to add device for port %d.\n", i);
977 pi->vi[0].dev = pi->dev;
978 device_set_softc(pi->dev, pi);
982 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
984 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
986 goto done; /* error message displayed already */
987 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
990 sc->intr_type = iaq.intr_type;
991 sc->intr_count = iaq.nirq;
994 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
995 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
997 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
998 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
1000 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1001 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
1002 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1004 if (is_offload(sc)) {
1005 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
1006 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
1008 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
1010 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
1013 s->neq += s->nofldtxq + s->nofldrxq;
1014 s->niq += s->nofldrxq;
1016 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1017 M_CXGBE, M_ZERO | M_WAITOK);
1018 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1019 M_CXGBE, M_ZERO | M_WAITOK);
1024 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
1025 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
1027 s->neq += s->nnmtxq + s->nnmrxq;
1028 s->niq += s->nnmrxq;
1030 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1031 M_CXGBE, M_ZERO | M_WAITOK);
1032 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1033 M_CXGBE, M_ZERO | M_WAITOK);
1036 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
1038 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1040 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1042 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1044 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1047 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1050 t4_init_l2t(sc, M_WAITOK);
1053 * Second pass over the ports. This time we know the number of rx and
1054 * tx queues that each port should get.
1058 ofld_rqidx = ofld_tqidx = 0;
1061 nm_rqidx = nm_tqidx = 0;
1063 for_each_port(sc, i) {
1064 struct port_info *pi = sc->port[i];
1071 for_each_vi(pi, j, vi) {
1073 vi->qsize_rxq = t4_qsize_rxq;
1074 vi->qsize_txq = t4_qsize_txq;
1076 vi->first_rxq = rqidx;
1077 vi->first_txq = tqidx;
1078 if (port_top_speed(pi) >= 10) {
1079 vi->tmr_idx = t4_tmr_idx_10g;
1080 vi->pktc_idx = t4_pktc_idx_10g;
1081 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
1082 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
1083 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
1085 vi->tmr_idx = t4_tmr_idx_1g;
1086 vi->pktc_idx = t4_pktc_idx_1g;
1087 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
1088 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
1089 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
1094 if (j == 0 && vi->ntxq > 1)
1095 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1097 vi->rsrv_noflowq = 0;
1100 vi->first_ofld_rxq = ofld_rqidx;
1101 vi->first_ofld_txq = ofld_tqidx;
1102 if (port_top_speed(pi) >= 10) {
1103 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1104 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1106 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1109 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1110 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1112 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1115 ofld_rqidx += vi->nofldrxq;
1116 ofld_tqidx += vi->nofldtxq;
1120 vi->first_nm_rxq = nm_rqidx;
1121 vi->first_nm_txq = nm_tqidx;
1122 vi->nnmrxq = iaq.nnmrxq_vi;
1123 vi->nnmtxq = iaq.nnmtxq_vi;
1124 nm_rqidx += vi->nnmrxq;
1125 nm_tqidx += vi->nnmtxq;
1131 rc = t4_setup_intr_handlers(sc);
1134 "failed to setup interrupt handlers: %d\n", rc);
1138 rc = bus_generic_attach(dev);
1141 "failed to attach all child ports: %d\n", rc);
1146 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1147 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1148 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1149 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1150 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1155 if (rc != 0 && sc->cdev) {
1156 /* cdev was created and so cxgbetool works; recover that way. */
1158 "error during attach, adapter is now in recovery mode.\n");
1163 t4_detach_common(dev);
1174 t4_detach(device_t dev)
1178 sc = device_get_softc(dev);
1180 return (t4_detach_common(dev));
1184 t4_detach_common(device_t dev)
1187 struct port_info *pi;
1190 sc = device_get_softc(dev);
1192 if (sc->flags & FULL_INIT_DONE) {
1193 if (!(sc->flags & IS_VF))
1194 t4_intr_disable(sc);
1198 destroy_dev(sc->cdev);
1202 if (device_is_attached(dev)) {
1203 rc = bus_generic_detach(dev);
1206 "failed to detach child devices: %d\n", rc);
1211 for (i = 0; i < sc->intr_count; i++)
1212 t4_free_irq(sc, &sc->irq[i]);
1214 for (i = 0; i < MAX_NPORTS; i++) {
1217 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1219 device_delete_child(dev, pi->dev);
1221 mtx_destroy(&pi->pi_lock);
1222 free(pi->vi, M_CXGBE);
1223 free(pi->tc, M_CXGBE);
1228 if (sc->flags & FULL_INIT_DONE)
1229 adapter_full_uninit(sc);
1231 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1232 t4_fw_bye(sc, sc->mbox);
1234 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1235 pci_release_msi(dev);
1238 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1242 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1246 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1250 t4_free_l2t(sc->l2t);
1253 free(sc->sge.ofld_rxq, M_CXGBE);
1254 free(sc->sge.ofld_txq, M_CXGBE);
1257 free(sc->sge.nm_rxq, M_CXGBE);
1258 free(sc->sge.nm_txq, M_CXGBE);
1260 free(sc->irq, M_CXGBE);
1261 free(sc->sge.rxq, M_CXGBE);
1262 free(sc->sge.txq, M_CXGBE);
1263 free(sc->sge.ctrlq, M_CXGBE);
1264 free(sc->sge.iqmap, M_CXGBE);
1265 free(sc->sge.eqmap, M_CXGBE);
1266 free(sc->tids.ftid_tab, M_CXGBE);
1267 t4_destroy_dma_tag(sc);
1268 if (mtx_initialized(&sc->sc_lock)) {
1269 sx_xlock(&t4_list_lock);
1270 SLIST_REMOVE(&t4_list, sc, adapter, link);
1271 sx_xunlock(&t4_list_lock);
1272 mtx_destroy(&sc->sc_lock);
1275 callout_drain(&sc->sfl_callout);
1276 if (mtx_initialized(&sc->tids.ftid_lock))
1277 mtx_destroy(&sc->tids.ftid_lock);
1278 if (mtx_initialized(&sc->sfl_lock))
1279 mtx_destroy(&sc->sfl_lock);
1280 if (mtx_initialized(&sc->ifp_lock))
1281 mtx_destroy(&sc->ifp_lock);
1282 if (mtx_initialized(&sc->reg_lock))
1283 mtx_destroy(&sc->reg_lock);
1285 for (i = 0; i < NUM_MEMWIN; i++) {
1286 struct memwin *mw = &sc->memwin[i];
1288 if (rw_initialized(&mw->mw_lock))
1289 rw_destroy(&mw->mw_lock);
1292 bzero(sc, sizeof(*sc));
1298 cxgbe_probe(device_t dev)
1301 struct port_info *pi = device_get_softc(dev);
1303 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1304 device_set_desc_copy(dev, buf);
1306 return (BUS_PROBE_DEFAULT);
1309 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1310 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1311 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1312 #define T4_CAP_ENABLE (T4_CAP)
1315 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1320 vi->xact_addr_filt = -1;
1321 callout_init(&vi->tick, 1);
1323 /* Allocate an ifnet and set it up */
1324 ifp = if_alloc(IFT_ETHER);
1326 device_printf(dev, "Cannot allocate ifnet\n");
1332 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1333 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1335 ifp->if_init = cxgbe_init;
1336 ifp->if_ioctl = cxgbe_ioctl;
1337 ifp->if_transmit = cxgbe_transmit;
1338 ifp->if_qflush = cxgbe_qflush;
1340 ifp->if_capabilities = T4_CAP;
1342 if (vi->nofldrxq != 0)
1343 ifp->if_capabilities |= IFCAP_TOE;
1345 ifp->if_capenable = T4_CAP_ENABLE;
1346 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1347 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1349 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1350 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1351 ifp->if_hw_tsomaxsegsize = 65536;
1353 /* Initialize ifmedia for this VI */
1354 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change,
1355 cxgbe_media_status);
1356 build_medialist(vi->pi, &vi->media);
1358 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1359 EVENTHANDLER_PRI_ANY);
1361 ether_ifattach(ifp, vi->hw_addr);
1363 if (vi->nnmrxq != 0)
1364 cxgbe_nm_attach(vi);
1366 sb = sbuf_new_auto();
1367 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1369 if (ifp->if_capabilities & IFCAP_TOE)
1370 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1371 vi->nofldtxq, vi->nofldrxq);
1374 if (ifp->if_capabilities & IFCAP_NETMAP)
1375 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1376 vi->nnmtxq, vi->nnmrxq);
1379 device_printf(dev, "%s\n", sbuf_data(sb));
1388 cxgbe_attach(device_t dev)
1390 struct port_info *pi = device_get_softc(dev);
1391 struct adapter *sc = pi->adapter;
1395 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1397 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1401 for_each_vi(pi, i, vi) {
1404 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1405 if (vi->dev == NULL) {
1406 device_printf(dev, "failed to add VI %d\n", i);
1409 device_set_softc(vi->dev, vi);
1414 bus_generic_attach(dev);
1420 cxgbe_vi_detach(struct vi_info *vi)
1422 struct ifnet *ifp = vi->ifp;
1424 ether_ifdetach(ifp);
1427 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1429 /* Let detach proceed even if these fail. */
1431 if (ifp->if_capabilities & IFCAP_NETMAP)
1432 cxgbe_nm_detach(vi);
1434 cxgbe_uninit_synchronized(vi);
1435 callout_drain(&vi->tick);
1438 ifmedia_removeall(&vi->media);
1444 cxgbe_detach(device_t dev)
1446 struct port_info *pi = device_get_softc(dev);
1447 struct adapter *sc = pi->adapter;
1450 /* Detach the extra VIs first. */
1451 rc = bus_generic_detach(dev);
1454 device_delete_children(dev);
1456 doom_vi(sc, &pi->vi[0]);
1458 if (pi->flags & HAS_TRACEQ) {
1459 sc->traceq = -1; /* cloner should not create ifnet */
1460 t4_tracer_port_detach(sc);
1463 cxgbe_vi_detach(&pi->vi[0]);
1464 callout_drain(&pi->tick);
1466 end_synchronized_op(sc, 0);
1472 cxgbe_init(void *arg)
1474 struct vi_info *vi = arg;
1475 struct adapter *sc = vi->pi->adapter;
1477 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1479 cxgbe_init_synchronized(vi);
1480 end_synchronized_op(sc, 0);
1484 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1486 int rc = 0, mtu, flags, can_sleep;
1487 struct vi_info *vi = ifp->if_softc;
1488 struct adapter *sc = vi->pi->adapter;
1489 struct ifreq *ifr = (struct ifreq *)data;
1495 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1498 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1502 if (vi->flags & VI_INIT_DONE) {
1503 t4_update_fl_bufsize(ifp);
1504 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1505 rc = update_mac_settings(ifp, XGMAC_MTU);
1507 end_synchronized_op(sc, 0);
1513 rc = begin_synchronized_op(sc, vi,
1514 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1518 if (ifp->if_flags & IFF_UP) {
1519 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1520 flags = vi->if_flags;
1521 if ((ifp->if_flags ^ flags) &
1522 (IFF_PROMISC | IFF_ALLMULTI)) {
1523 if (can_sleep == 1) {
1524 end_synchronized_op(sc, 0);
1528 rc = update_mac_settings(ifp,
1529 XGMAC_PROMISC | XGMAC_ALLMULTI);
1532 if (can_sleep == 0) {
1533 end_synchronized_op(sc, LOCK_HELD);
1537 rc = cxgbe_init_synchronized(vi);
1539 vi->if_flags = ifp->if_flags;
1540 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1541 if (can_sleep == 0) {
1542 end_synchronized_op(sc, LOCK_HELD);
1546 rc = cxgbe_uninit_synchronized(vi);
1548 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1552 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1553 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1556 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1557 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1558 end_synchronized_op(sc, LOCK_HELD);
1562 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1566 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1567 if (mask & IFCAP_TXCSUM) {
1568 ifp->if_capenable ^= IFCAP_TXCSUM;
1569 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1571 if (IFCAP_TSO4 & ifp->if_capenable &&
1572 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1573 ifp->if_capenable &= ~IFCAP_TSO4;
1575 "tso4 disabled due to -txcsum.\n");
1578 if (mask & IFCAP_TXCSUM_IPV6) {
1579 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1580 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1582 if (IFCAP_TSO6 & ifp->if_capenable &&
1583 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1584 ifp->if_capenable &= ~IFCAP_TSO6;
1586 "tso6 disabled due to -txcsum6.\n");
1589 if (mask & IFCAP_RXCSUM)
1590 ifp->if_capenable ^= IFCAP_RXCSUM;
1591 if (mask & IFCAP_RXCSUM_IPV6)
1592 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1595 * Note that we leave CSUM_TSO alone (it is always set). The
1596 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1597 * sending a TSO request our way, so it's sufficient to toggle
1600 if (mask & IFCAP_TSO4) {
1601 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1602 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1603 if_printf(ifp, "enable txcsum first.\n");
1607 ifp->if_capenable ^= IFCAP_TSO4;
1609 if (mask & IFCAP_TSO6) {
1610 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1611 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1612 if_printf(ifp, "enable txcsum6 first.\n");
1616 ifp->if_capenable ^= IFCAP_TSO6;
1618 if (mask & IFCAP_LRO) {
1619 #if defined(INET) || defined(INET6)
1621 struct sge_rxq *rxq;
1623 ifp->if_capenable ^= IFCAP_LRO;
1624 for_each_rxq(vi, i, rxq) {
1625 if (ifp->if_capenable & IFCAP_LRO)
1626 rxq->iq.flags |= IQ_LRO_ENABLED;
1628 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1633 if (mask & IFCAP_TOE) {
1634 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1636 rc = toe_capability(vi, enable);
1640 ifp->if_capenable ^= mask;
1643 if (mask & IFCAP_VLAN_HWTAGGING) {
1644 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1645 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1646 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1648 if (mask & IFCAP_VLAN_MTU) {
1649 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1651 /* Need to find out how to disable auto-mtu-inflation */
1653 if (mask & IFCAP_VLAN_HWTSO)
1654 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1655 if (mask & IFCAP_VLAN_HWCSUM)
1656 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1658 #ifdef VLAN_CAPABILITIES
1659 VLAN_CAPABILITIES(ifp);
1662 end_synchronized_op(sc, 0);
1668 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1672 struct ifi2creq i2c;
1674 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1677 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1681 if (i2c.len > sizeof(i2c.data)) {
1685 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1688 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr,
1689 i2c.offset, i2c.len, &i2c.data[0]);
1690 end_synchronized_op(sc, 0);
1692 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1697 rc = ether_ioctl(ifp, cmd, data);
1704 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1706 struct vi_info *vi = ifp->if_softc;
1707 struct port_info *pi = vi->pi;
1708 struct adapter *sc = pi->adapter;
1709 struct sge_txq *txq;
1714 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1716 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1721 rc = parse_pkt(sc, &m);
1722 if (__predict_false(rc != 0)) {
1723 MPASS(m == NULL); /* was freed already */
1724 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1729 txq = &sc->sge.txq[vi->first_txq];
1730 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1731 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1735 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1736 if (__predict_false(rc != 0))
1743 cxgbe_qflush(struct ifnet *ifp)
1745 struct vi_info *vi = ifp->if_softc;
1746 struct sge_txq *txq;
1749 /* queues do not exist if !VI_INIT_DONE. */
1750 if (vi->flags & VI_INIT_DONE) {
1751 for_each_txq(vi, i, txq) {
1753 txq->eq.flags &= ~EQ_ENABLED;
1755 while (!mp_ring_is_idle(txq->r)) {
1756 mp_ring_check_drainage(txq->r, 0);
1765 cxgbe_media_change(struct ifnet *ifp)
1767 struct vi_info *vi = ifp->if_softc;
1769 device_printf(vi->dev, "%s unimplemented.\n", __func__);
1771 return (EOPNOTSUPP);
1775 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1777 struct vi_info *vi = ifp->if_softc;
1778 struct port_info *pi = vi->pi;
1779 struct ifmedia_entry *cur;
1780 int speed = pi->link_cfg.speed;
1782 cur = vi->media.ifm_cur;
1784 ifmr->ifm_status = IFM_AVALID;
1785 if (!pi->link_cfg.link_ok)
1788 ifmr->ifm_status |= IFM_ACTIVE;
1790 /* active and current will differ iff current media is autoselect. */
1791 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1794 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1796 ifmr->ifm_active |= IFM_10G_T;
1797 else if (speed == 1000)
1798 ifmr->ifm_active |= IFM_1000_T;
1799 else if (speed == 100)
1800 ifmr->ifm_active |= IFM_100_TX;
1801 else if (speed == 10)
1802 ifmr->ifm_active |= IFM_10_T;
1804 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1809 vcxgbe_probe(device_t dev)
1812 struct vi_info *vi = device_get_softc(dev);
1814 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
1816 device_set_desc_copy(dev, buf);
1818 return (BUS_PROBE_DEFAULT);
1822 vcxgbe_attach(device_t dev)
1825 struct port_info *pi;
1827 int func, index, rc;
1830 vi = device_get_softc(dev);
1834 index = vi - pi->vi;
1835 KASSERT(index < nitems(vi_mac_funcs),
1836 ("%s: VI %s doesn't have a MAC func", __func__,
1837 device_get_nameunit(dev)));
1838 func = vi_mac_funcs[index];
1839 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1840 vi->hw_addr, &vi->rss_size, func, 0);
1842 device_printf(dev, "Failed to allocate virtual interface "
1843 "for port %d: %d\n", pi->port_id, -rc);
1847 if (chip_id(sc) <= CHELSIO_T5)
1848 vi->smt_idx = (rc & 0x7f) << 1;
1850 vi->smt_idx = (rc & 0x7f);
1852 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1853 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1854 V_FW_PARAMS_PARAM_YZ(vi->viid);
1855 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
1857 vi->rss_base = 0xffff;
1859 /* MPASS((val >> 16) == rss_size); */
1860 vi->rss_base = val & 0xffff;
1863 rc = cxgbe_vi_attach(dev, vi);
1865 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1872 vcxgbe_detach(device_t dev)
1877 vi = device_get_softc(dev);
1878 sc = vi->pi->adapter;
1882 cxgbe_vi_detach(vi);
1883 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1885 end_synchronized_op(sc, 0);
1891 t4_fatal_err(struct adapter *sc)
1893 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1894 t4_intr_disable(sc);
1895 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1896 device_get_nameunit(sc->dev));
1900 t4_add_adapter(struct adapter *sc)
1902 sx_xlock(&t4_list_lock);
1903 SLIST_INSERT_HEAD(&t4_list, sc, link);
1904 sx_xunlock(&t4_list_lock);
1908 t4_map_bars_0_and_4(struct adapter *sc)
1910 sc->regs_rid = PCIR_BAR(0);
1911 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1912 &sc->regs_rid, RF_ACTIVE);
1913 if (sc->regs_res == NULL) {
1914 device_printf(sc->dev, "cannot map registers.\n");
1917 sc->bt = rman_get_bustag(sc->regs_res);
1918 sc->bh = rman_get_bushandle(sc->regs_res);
1919 sc->mmio_len = rman_get_size(sc->regs_res);
1920 setbit(&sc->doorbells, DOORBELL_KDB);
1922 sc->msix_rid = PCIR_BAR(4);
1923 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1924 &sc->msix_rid, RF_ACTIVE);
1925 if (sc->msix_res == NULL) {
1926 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1934 t4_map_bar_2(struct adapter *sc)
1938 * T4: only iWARP driver uses the userspace doorbells. There is no need
1939 * to map it if RDMA is disabled.
1941 if (is_t4(sc) && sc->rdmacaps == 0)
1944 sc->udbs_rid = PCIR_BAR(2);
1945 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1946 &sc->udbs_rid, RF_ACTIVE);
1947 if (sc->udbs_res == NULL) {
1948 device_printf(sc->dev, "cannot map doorbell BAR.\n");
1951 sc->udbs_base = rman_get_virtual(sc->udbs_res);
1953 if (chip_id(sc) >= CHELSIO_T5) {
1954 setbit(&sc->doorbells, DOORBELL_UDB);
1955 #if defined(__i386__) || defined(__amd64__)
1956 if (t5_write_combine) {
1960 * Enable write combining on BAR2. This is the
1961 * userspace doorbell BAR and is split into 128B
1962 * (UDBS_SEG_SIZE) doorbell regions, each associated
1963 * with an egress queue. The first 64B has the doorbell
1964 * and the second 64B can be used to submit a tx work
1965 * request with an implicit doorbell.
1968 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
1969 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
1971 clrbit(&sc->doorbells, DOORBELL_UDB);
1972 setbit(&sc->doorbells, DOORBELL_WCWR);
1973 setbit(&sc->doorbells, DOORBELL_UDBWC);
1975 device_printf(sc->dev,
1976 "couldn't enable write combining: %d\n",
1980 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
1981 t4_write_reg(sc, A_SGE_STAT_CFG,
1982 V_STATSOURCE_T5(7) | mode);
1990 struct memwin_init {
1995 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
1996 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1997 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1998 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2001 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2002 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2003 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2004 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2008 setup_memwin(struct adapter *sc)
2010 const struct memwin_init *mw_init;
2017 * Read low 32b of bar0 indirectly via the hardware backdoor
2018 * mechanism. Works from within PCI passthrough environments
2019 * too, where rman_get_start() can return a different value. We
2020 * need to program the T4 memory window decoders with the actual
2021 * addresses that will be coming across the PCIe link.
2023 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2024 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2026 mw_init = &t4_memwin[0];
2028 /* T5+ use the relative offset inside the PCIe BAR */
2031 mw_init = &t5_memwin[0];
2034 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2035 rw_init(&mw->mw_lock, "memory window access");
2036 mw->mw_base = mw_init->base;
2037 mw->mw_aperture = mw_init->aperture;
2040 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2041 (mw->mw_base + bar0) | V_BIR(0) |
2042 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2043 rw_wlock(&mw->mw_lock);
2044 position_memwin(sc, i, 0);
2045 rw_wunlock(&mw->mw_lock);
2049 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2053 * Positions the memory window at the given address in the card's address space.
2054 * There are some alignment requirements and the actual position may be at an
2055 * address prior to the requested address. mw->mw_curpos always has the actual
2056 * position of the window.
2059 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2065 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2066 mw = &sc->memwin[idx];
2067 rw_assert(&mw->mw_lock, RA_WLOCKED);
2071 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2073 pf = V_PFNUM(sc->pf);
2074 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2076 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2077 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2078 t4_read_reg(sc, reg); /* flush */
2082 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2088 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2090 /* Memory can only be accessed in naturally aligned 4 byte units */
2091 if (addr & 3 || len & 3 || len <= 0)
2094 mw = &sc->memwin[idx];
2096 rw_rlock(&mw->mw_lock);
2097 mw_end = mw->mw_curpos + mw->mw_aperture;
2098 if (addr >= mw_end || addr < mw->mw_curpos) {
2099 /* Will need to reposition the window */
2100 if (!rw_try_upgrade(&mw->mw_lock)) {
2101 rw_runlock(&mw->mw_lock);
2102 rw_wlock(&mw->mw_lock);
2104 rw_assert(&mw->mw_lock, RA_WLOCKED);
2105 position_memwin(sc, idx, addr);
2106 rw_downgrade(&mw->mw_lock);
2107 mw_end = mw->mw_curpos + mw->mw_aperture;
2109 rw_assert(&mw->mw_lock, RA_RLOCKED);
2110 while (addr < mw_end && len > 0) {
2112 v = t4_read_reg(sc, mw->mw_base + addr -
2114 *val++ = le32toh(v);
2117 t4_write_reg(sc, mw->mw_base + addr -
2118 mw->mw_curpos, htole32(v));;
2123 rw_runlock(&mw->mw_lock);
2130 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2134 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2138 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2139 const uint32_t *val, int len)
2142 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2146 t4_range_cmp(const void *a, const void *b)
2148 return ((const struct t4_range *)a)->start -
2149 ((const struct t4_range *)b)->start;
2153 * Verify that the memory range specified by the addr/len pair is valid within
2154 * the card's address space.
2157 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2159 struct t4_range mem_ranges[4], *r, *next;
2160 uint32_t em, addr_len;
2161 int i, n, remaining;
2163 /* Memory can only be accessed in naturally aligned 4 byte units */
2164 if (addr & 3 || len & 3 || len <= 0)
2167 /* Enabled memories */
2168 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2172 bzero(r, sizeof(mem_ranges));
2173 if (em & F_EDRAM0_ENABLE) {
2174 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2175 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2177 r->start = G_EDRAM0_BASE(addr_len) << 20;
2178 if (addr >= r->start &&
2179 addr + len <= r->start + r->size)
2185 if (em & F_EDRAM1_ENABLE) {
2186 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2187 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2189 r->start = G_EDRAM1_BASE(addr_len) << 20;
2190 if (addr >= r->start &&
2191 addr + len <= r->start + r->size)
2197 if (em & F_EXT_MEM_ENABLE) {
2198 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2199 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2201 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2202 if (addr >= r->start &&
2203 addr + len <= r->start + r->size)
2209 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2210 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2211 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2213 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2214 if (addr >= r->start &&
2215 addr + len <= r->start + r->size)
2221 MPASS(n <= nitems(mem_ranges));
2224 /* Sort and merge the ranges. */
2225 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2227 /* Start from index 0 and examine the next n - 1 entries. */
2229 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2231 MPASS(r->size > 0); /* r is a valid entry. */
2233 MPASS(next->size > 0); /* and so is the next one. */
2235 while (r->start + r->size >= next->start) {
2236 /* Merge the next one into the current entry. */
2237 r->size = max(r->start + r->size,
2238 next->start + next->size) - r->start;
2239 n--; /* One fewer entry in total. */
2240 if (--remaining == 0)
2241 goto done; /* short circuit */
2244 if (next != r + 1) {
2246 * Some entries were merged into r and next
2247 * points to the first valid entry that couldn't
2250 MPASS(next->size > 0); /* must be valid */
2251 memcpy(r + 1, next, remaining * sizeof(*r));
2254 * This so that the foo->size assertion in the
2255 * next iteration of the loop do the right
2256 * thing for entries that were pulled up and are
2259 MPASS(n < nitems(mem_ranges));
2260 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2261 sizeof(struct t4_range));
2266 /* Done merging the ranges. */
2269 for (i = 0; i < n; i++, r++) {
2270 if (addr >= r->start &&
2271 addr + len <= r->start + r->size)
2280 fwmtype_to_hwmtype(int mtype)
2284 case FW_MEMTYPE_EDC0:
2286 case FW_MEMTYPE_EDC1:
2288 case FW_MEMTYPE_EXTMEM:
2290 case FW_MEMTYPE_EXTMEM1:
2293 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2298 * Verify that the memory range specified by the memtype/offset/len pair is
2299 * valid and lies entirely within the memtype specified. The global address of
2300 * the start of the range is returned in addr.
2303 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2306 uint32_t em, addr_len, maddr;
2308 /* Memory can only be accessed in naturally aligned 4 byte units */
2309 if (off & 3 || len & 3 || len == 0)
2312 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2313 switch (fwmtype_to_hwmtype(mtype)) {
2315 if (!(em & F_EDRAM0_ENABLE))
2317 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2318 maddr = G_EDRAM0_BASE(addr_len) << 20;
2321 if (!(em & F_EDRAM1_ENABLE))
2323 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2324 maddr = G_EDRAM1_BASE(addr_len) << 20;
2327 if (!(em & F_EXT_MEM_ENABLE))
2329 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2330 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2333 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2335 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2336 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2342 *addr = maddr + off; /* global address */
2343 return (validate_mem_range(sc, *addr, len));
2347 fixup_devlog_params(struct adapter *sc)
2349 struct devlog_params *dparams = &sc->params.devlog;
2352 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2353 dparams->size, &dparams->addr);
2359 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2360 struct intrs_and_queues *iaq)
2362 int rc, itype, navail, nrxq10g, nrxq1g, n;
2363 int nofldrxq10g = 0, nofldrxq1g = 0;
2365 bzero(iaq, sizeof(*iaq));
2367 iaq->ntxq10g = t4_ntxq10g;
2368 iaq->ntxq1g = t4_ntxq1g;
2369 iaq->ntxq_vi = t4_ntxq_vi;
2370 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2371 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2372 iaq->nrxq_vi = t4_nrxq_vi;
2373 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2375 if (is_offload(sc)) {
2376 iaq->nofldtxq10g = t4_nofldtxq10g;
2377 iaq->nofldtxq1g = t4_nofldtxq1g;
2378 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2379 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2380 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2381 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2385 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2386 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2389 for (itype = INTR_MSIX; itype; itype >>= 1) {
2391 if ((itype & t4_intr_types) == 0)
2392 continue; /* not allowed */
2394 if (itype == INTR_MSIX)
2395 navail = pci_msix_count(sc->dev);
2396 else if (itype == INTR_MSI)
2397 navail = pci_msi_count(sc->dev);
2404 iaq->intr_type = itype;
2405 iaq->intr_flags_10g = 0;
2406 iaq->intr_flags_1g = 0;
2409 * Best option: an interrupt vector for errors, one for the
2410 * firmware event queue, and one for every rxq (NIC and TOE) of
2411 * every VI. The VIs that support netmap use the same
2412 * interrupts for the NIC rx queues and the netmap rx queues
2413 * because only one set of queues is active at a time.
2415 iaq->nirq = T4_EXTRA_INTR;
2416 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2417 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2418 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2419 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2420 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2421 if (iaq->nirq <= navail &&
2422 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2423 iaq->intr_flags_10g = INTR_ALL;
2424 iaq->intr_flags_1g = INTR_ALL;
2428 /* Disable the VIs (and netmap) if there aren't enough intrs */
2430 device_printf(sc->dev, "virtual interfaces disabled "
2431 "because num_vis=%u with current settings "
2432 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2433 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2434 "nnmrxq_vi=%u) would need %u interrupts but "
2435 "only %u are available.\n", num_vis, nrxq10g,
2436 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2437 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2440 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2441 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2442 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2447 * Second best option: a vector for errors, one for the firmware
2448 * event queue, and vectors for either all the NIC rx queues or
2449 * all the TOE rx queues. The queues that don't get vectors
2450 * will forward their interrupts to those that do.
2452 iaq->nirq = T4_EXTRA_INTR;
2453 if (nrxq10g >= nofldrxq10g) {
2454 iaq->intr_flags_10g = INTR_RXQ;
2455 iaq->nirq += n10g * nrxq10g;
2457 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2458 iaq->nirq += n10g * nofldrxq10g;
2460 if (nrxq1g >= nofldrxq1g) {
2461 iaq->intr_flags_1g = INTR_RXQ;
2462 iaq->nirq += n1g * nrxq1g;
2464 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2465 iaq->nirq += n1g * nofldrxq1g;
2467 if (iaq->nirq <= navail &&
2468 (itype != INTR_MSI || powerof2(iaq->nirq)))
2472 * Next best option: an interrupt vector for errors, one for the
2473 * firmware event queue, and at least one per main-VI. At this
2474 * point we know we'll have to downsize nrxq and/or nofldrxq to
2475 * fit what's available to us.
2477 iaq->nirq = T4_EXTRA_INTR;
2478 iaq->nirq += n10g + n1g;
2479 if (iaq->nirq <= navail) {
2480 int leftover = navail - iaq->nirq;
2483 int target = max(nrxq10g, nofldrxq10g);
2485 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2486 INTR_RXQ : INTR_OFLD_RXQ;
2489 while (n < target && leftover >= n10g) {
2494 iaq->nrxq10g = min(n, nrxq10g);
2496 iaq->nofldrxq10g = min(n, nofldrxq10g);
2501 int target = max(nrxq1g, nofldrxq1g);
2503 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2504 INTR_RXQ : INTR_OFLD_RXQ;
2507 while (n < target && leftover >= n1g) {
2512 iaq->nrxq1g = min(n, nrxq1g);
2514 iaq->nofldrxq1g = min(n, nofldrxq1g);
2518 if (itype != INTR_MSI || powerof2(iaq->nirq))
2523 * Least desirable option: one interrupt vector for everything.
2525 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2526 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2529 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2534 if (itype == INTR_MSIX)
2535 rc = pci_alloc_msix(sc->dev, &navail);
2536 else if (itype == INTR_MSI)
2537 rc = pci_alloc_msi(sc->dev, &navail);
2540 if (navail == iaq->nirq)
2544 * Didn't get the number requested. Use whatever number
2545 * the kernel is willing to allocate (it's in navail).
2547 device_printf(sc->dev, "fewer vectors than requested, "
2548 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2549 itype, iaq->nirq, navail);
2550 pci_release_msi(sc->dev);
2554 device_printf(sc->dev,
2555 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2556 itype, rc, iaq->nirq, navail);
2559 device_printf(sc->dev,
2560 "failed to find a usable interrupt type. "
2561 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2562 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2567 #define FW_VERSION(chip) ( \
2568 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2569 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2570 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2571 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2572 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2578 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2582 .kld_name = "t4fw_cfg",
2583 .fw_mod_name = "t4fw",
2585 .chip = FW_HDR_CHIP_T4,
2586 .fw_ver = htobe32_const(FW_VERSION(T4)),
2587 .intfver_nic = FW_INTFVER(T4, NIC),
2588 .intfver_vnic = FW_INTFVER(T4, VNIC),
2589 .intfver_ofld = FW_INTFVER(T4, OFLD),
2590 .intfver_ri = FW_INTFVER(T4, RI),
2591 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2592 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2593 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2594 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2598 .kld_name = "t5fw_cfg",
2599 .fw_mod_name = "t5fw",
2601 .chip = FW_HDR_CHIP_T5,
2602 .fw_ver = htobe32_const(FW_VERSION(T5)),
2603 .intfver_nic = FW_INTFVER(T5, NIC),
2604 .intfver_vnic = FW_INTFVER(T5, VNIC),
2605 .intfver_ofld = FW_INTFVER(T5, OFLD),
2606 .intfver_ri = FW_INTFVER(T5, RI),
2607 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2608 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2609 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2610 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2614 .kld_name = "t6fw_cfg",
2615 .fw_mod_name = "t6fw",
2617 .chip = FW_HDR_CHIP_T6,
2618 .fw_ver = htobe32_const(FW_VERSION(T6)),
2619 .intfver_nic = FW_INTFVER(T6, NIC),
2620 .intfver_vnic = FW_INTFVER(T6, VNIC),
2621 .intfver_ofld = FW_INTFVER(T6, OFLD),
2622 .intfver_ri = FW_INTFVER(T6, RI),
2623 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
2624 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
2625 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
2626 .intfver_fcoe = FW_INTFVER(T6, FCOE),
2631 static struct fw_info *
2632 find_fw_info(int chip)
2636 for (i = 0; i < nitems(fw_info); i++) {
2637 if (fw_info[i].chip == chip)
2638 return (&fw_info[i]);
2644 * Is the given firmware API compatible with the one the driver was compiled
2648 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2651 /* short circuit if it's the exact same firmware version */
2652 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2656 * XXX: Is this too conservative? Perhaps I should limit this to the
2657 * features that are supported in the driver.
2659 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2660 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2661 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2662 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2670 * The firmware in the KLD is usable, but should it be installed? This routine
2671 * explains itself in detail if it indicates the KLD firmware should be
2675 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2679 if (!card_fw_usable) {
2680 reason = "incompatible or unusable";
2685 reason = "older than the version bundled with this driver";
2689 if (t4_fw_install == 2 && k != c) {
2690 reason = "different than the version bundled with this driver";
2697 if (t4_fw_install == 0) {
2698 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2699 "but the driver is prohibited from installing a different "
2700 "firmware on the card.\n",
2701 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2702 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2707 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2708 "installing firmware %u.%u.%u.%u on card.\n",
2709 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2710 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2711 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2712 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2717 * Establish contact with the firmware and determine if we are the master driver
2718 * or not, and whether we are responsible for chip initialization.
2721 prep_firmware(struct adapter *sc)
2723 const struct firmware *fw = NULL, *default_cfg;
2724 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2725 enum dev_state state;
2726 struct fw_info *fw_info;
2727 struct fw_hdr *card_fw; /* fw on the card */
2728 const struct fw_hdr *kld_fw; /* fw in the KLD */
2729 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2732 /* Contact firmware. */
2733 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2734 if (rc < 0 || state == DEV_STATE_ERR) {
2736 device_printf(sc->dev,
2737 "failed to connect to the firmware: %d, %d.\n", rc, state);
2742 sc->flags |= MASTER_PF;
2743 else if (state == DEV_STATE_UNINIT) {
2745 * We didn't get to be the master so we definitely won't be
2746 * configuring the chip. It's a bug if someone else hasn't
2747 * configured it already.
2749 device_printf(sc->dev, "couldn't be master(%d), "
2750 "device not already initialized either(%d).\n", rc, state);
2754 /* This is the firmware whose headers the driver was compiled against */
2755 fw_info = find_fw_info(chip_id(sc));
2756 if (fw_info == NULL) {
2757 device_printf(sc->dev,
2758 "unable to look up firmware information for chip %d.\n",
2762 drv_fw = &fw_info->fw_hdr;
2765 * The firmware KLD contains many modules. The KLD name is also the
2766 * name of the module that contains the default config file.
2768 default_cfg = firmware_get(fw_info->kld_name);
2770 /* Read the header of the firmware on the card */
2771 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2772 rc = -t4_read_flash(sc, FLASH_FW_START,
2773 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2775 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2777 device_printf(sc->dev,
2778 "Unable to read card's firmware header: %d\n", rc);
2782 /* This is the firmware in the KLD */
2783 fw = firmware_get(fw_info->fw_mod_name);
2785 kld_fw = (const void *)fw->data;
2786 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2792 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2793 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2795 * Common case: the firmware on the card is an exact match and
2796 * the KLD is an exact match too, or the KLD is
2797 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2798 * here -- use cxgbetool loadfw if you want to reinstall the
2799 * same firmware as the one on the card.
2801 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2802 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2803 be32toh(card_fw->fw_ver))) {
2805 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2807 device_printf(sc->dev,
2808 "failed to install firmware: %d\n", rc);
2812 /* Installed successfully, update the cached header too. */
2813 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2815 need_fw_reset = 0; /* already reset as part of load_fw */
2818 if (!card_fw_usable) {
2821 d = ntohl(drv_fw->fw_ver);
2822 c = ntohl(card_fw->fw_ver);
2823 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2825 device_printf(sc->dev, "Cannot find a usable firmware: "
2826 "fw_install %d, chip state %d, "
2827 "driver compiled with %d.%d.%d.%d, "
2828 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2829 t4_fw_install, state,
2830 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2831 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2832 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2833 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2834 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2835 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2841 if (need_fw_reset &&
2842 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2843 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2844 if (rc != ETIMEDOUT && rc != EIO)
2845 t4_fw_bye(sc, sc->mbox);
2850 rc = get_params__pre_init(sc);
2852 goto done; /* error message displayed already */
2854 /* Partition adapter resources as specified in the config file. */
2855 if (state == DEV_STATE_UNINIT) {
2857 KASSERT(sc->flags & MASTER_PF,
2858 ("%s: trying to change chip settings when not master.",
2861 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2863 goto done; /* error message displayed already */
2865 t4_tweak_chip_settings(sc);
2867 /* get basic stuff going */
2868 rc = -t4_fw_initialize(sc, sc->mbox);
2870 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2874 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2879 free(card_fw, M_CXGBE);
2881 firmware_put(fw, FIRMWARE_UNLOAD);
2882 if (default_cfg != NULL)
2883 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2888 #define FW_PARAM_DEV(param) \
2889 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2890 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2891 #define FW_PARAM_PFVF(param) \
2892 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2893 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2896 * Partition chip resources for use between various PFs, VFs, etc.
2899 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2900 const char *name_prefix)
2902 const struct firmware *cfg = NULL;
2904 struct fw_caps_config_cmd caps;
2905 uint32_t mtype, moff, finicsum, cfcsum;
2908 * Figure out what configuration file to use. Pick the default config
2909 * file for the card if the user hasn't specified one explicitly.
2911 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2912 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2913 /* Card specific overrides go here. */
2914 if (pci_get_device(sc->dev) == 0x440a)
2915 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2917 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2921 * We need to load another module if the profile is anything except
2922 * "default" or "flash".
2924 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2925 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2928 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2929 cfg = firmware_get(s);
2931 if (default_cfg != NULL) {
2932 device_printf(sc->dev,
2933 "unable to load module \"%s\" for "
2934 "configuration profile \"%s\", will use "
2935 "the default config file instead.\n",
2937 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2940 device_printf(sc->dev,
2941 "unable to load module \"%s\" for "
2942 "configuration profile \"%s\", will use "
2943 "the config file on the card's flash "
2944 "instead.\n", s, sc->cfg_file);
2945 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2951 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2952 default_cfg == NULL) {
2953 device_printf(sc->dev,
2954 "default config file not available, will use the config "
2955 "file on the card's flash instead.\n");
2956 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
2959 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2961 const uint32_t *cfdata;
2962 uint32_t param, val, addr;
2964 KASSERT(cfg != NULL || default_cfg != NULL,
2965 ("%s: no config to upload", __func__));
2968 * Ask the firmware where it wants us to upload the config file.
2970 param = FW_PARAM_DEV(CF);
2971 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2973 /* No support for config file? Shouldn't happen. */
2974 device_printf(sc->dev,
2975 "failed to query config file location: %d.\n", rc);
2978 mtype = G_FW_PARAMS_PARAM_Y(val);
2979 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
2982 * XXX: sheer laziness. We deliberately added 4 bytes of
2983 * useless stuffing/comments at the end of the config file so
2984 * it's ok to simply throw away the last remaining bytes when
2985 * the config file is not an exact multiple of 4. This also
2986 * helps with the validate_mt_off_len check.
2989 cflen = cfg->datasize & ~3;
2992 cflen = default_cfg->datasize & ~3;
2993 cfdata = default_cfg->data;
2996 if (cflen > FLASH_CFG_MAX_SIZE) {
2997 device_printf(sc->dev,
2998 "config file too long (%d, max allowed is %d). "
2999 "Will try to use the config on the card, if any.\n",
3000 cflen, FLASH_CFG_MAX_SIZE);
3001 goto use_config_on_flash;
3004 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3006 device_printf(sc->dev,
3007 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
3008 "Will try to use the config on the card, if any.\n",
3009 __func__, mtype, moff, cflen, rc);
3010 goto use_config_on_flash;
3012 write_via_memwin(sc, 2, addr, cfdata, cflen);
3014 use_config_on_flash:
3015 mtype = FW_MEMTYPE_FLASH;
3016 moff = t4_flash_cfg_addr(sc);
3019 bzero(&caps, sizeof(caps));
3020 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3021 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3022 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3023 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3024 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3025 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3027 device_printf(sc->dev,
3028 "failed to pre-process config file: %d "
3029 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3033 finicsum = be32toh(caps.finicsum);
3034 cfcsum = be32toh(caps.cfcsum);
3035 if (finicsum != cfcsum) {
3036 device_printf(sc->dev,
3037 "WARNING: config file checksum mismatch: %08x %08x\n",
3040 sc->cfcsum = cfcsum;
3042 #define LIMIT_CAPS(x) do { \
3043 caps.x &= htobe16(t4_##x##_allowed); \
3047 * Let the firmware know what features will (not) be used so it can tune
3048 * things accordingly.
3050 LIMIT_CAPS(nbmcaps);
3051 LIMIT_CAPS(linkcaps);
3052 LIMIT_CAPS(switchcaps);
3053 LIMIT_CAPS(niccaps);
3054 LIMIT_CAPS(toecaps);
3055 LIMIT_CAPS(rdmacaps);
3056 LIMIT_CAPS(cryptocaps);
3057 LIMIT_CAPS(iscsicaps);
3058 LIMIT_CAPS(fcoecaps);
3061 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3062 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3063 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3064 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3066 device_printf(sc->dev,
3067 "failed to process config file: %d.\n", rc);
3071 firmware_put(cfg, FIRMWARE_UNLOAD);
3076 * Retrieve parameters that are needed (or nice to have) very early.
3079 get_params__pre_init(struct adapter *sc)
3082 uint32_t param[2], val[2];
3084 t4_get_version_info(sc);
3086 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3087 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3088 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3089 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3090 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3092 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3093 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3094 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3095 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3096 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3098 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3099 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3100 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3101 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3102 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3104 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3105 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3106 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3107 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3108 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3110 param[0] = FW_PARAM_DEV(PORTVEC);
3111 param[1] = FW_PARAM_DEV(CCLK);
3112 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3114 device_printf(sc->dev,
3115 "failed to query parameters (pre_init): %d.\n", rc);
3119 sc->params.portvec = val[0];
3120 sc->params.nports = bitcount32(val[0]);
3121 sc->params.vpd.cclk = val[1];
3123 /* Read device log parameters. */
3124 rc = -t4_init_devlog_params(sc, 1);
3126 fixup_devlog_params(sc);
3128 device_printf(sc->dev,
3129 "failed to get devlog parameters: %d.\n", rc);
3130 rc = 0; /* devlog isn't critical for device operation */
3137 * Retrieve various parameters that are of interest to the driver. The device
3138 * has been initialized by the firmware at this point.
3141 get_params__post_init(struct adapter *sc)
3144 uint32_t param[7], val[7];
3145 struct fw_caps_config_cmd caps;
3147 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3148 param[1] = FW_PARAM_PFVF(EQ_START);
3149 param[2] = FW_PARAM_PFVF(FILTER_START);
3150 param[3] = FW_PARAM_PFVF(FILTER_END);
3151 param[4] = FW_PARAM_PFVF(L2T_START);
3152 param[5] = FW_PARAM_PFVF(L2T_END);
3153 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3155 device_printf(sc->dev,
3156 "failed to query parameters (post_init): %d.\n", rc);
3160 sc->sge.iq_start = val[0];
3161 sc->sge.eq_start = val[1];
3162 sc->tids.ftid_base = val[2];
3163 sc->tids.nftids = val[3] - val[2] + 1;
3164 sc->params.ftid_min = val[2];
3165 sc->params.ftid_max = val[3];
3166 sc->vres.l2t.start = val[4];
3167 sc->vres.l2t.size = val[5] - val[4] + 1;
3168 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3169 ("%s: L2 table size (%u) larger than expected (%u)",
3170 __func__, sc->vres.l2t.size, L2T_SIZE));
3172 /* get capabilites */
3173 bzero(&caps, sizeof(caps));
3174 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3175 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3176 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3177 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3179 device_printf(sc->dev,
3180 "failed to get card capabilities: %d.\n", rc);
3184 #define READ_CAPS(x) do { \
3185 sc->x = htobe16(caps.x); \
3188 READ_CAPS(linkcaps);
3189 READ_CAPS(switchcaps);
3192 READ_CAPS(rdmacaps);
3193 READ_CAPS(cryptocaps);
3194 READ_CAPS(iscsicaps);
3195 READ_CAPS(fcoecaps);
3197 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3198 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3199 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3200 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3201 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3203 device_printf(sc->dev,
3204 "failed to query NIC parameters: %d.\n", rc);
3207 sc->tids.etid_base = val[0];
3208 sc->params.etid_min = val[0];
3209 sc->tids.netids = val[1] - val[0] + 1;
3210 sc->params.netids = sc->tids.netids;
3211 sc->params.eo_wr_cred = val[2];
3212 sc->params.ethoffload = 1;
3216 /* query offload-related parameters */
3217 param[0] = FW_PARAM_DEV(NTID);
3218 param[1] = FW_PARAM_PFVF(SERVER_START);
3219 param[2] = FW_PARAM_PFVF(SERVER_END);
3220 param[3] = FW_PARAM_PFVF(TDDP_START);
3221 param[4] = FW_PARAM_PFVF(TDDP_END);
3222 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3223 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3225 device_printf(sc->dev,
3226 "failed to query TOE parameters: %d.\n", rc);
3229 sc->tids.ntids = val[0];
3230 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3231 sc->tids.stid_base = val[1];
3232 sc->tids.nstids = val[2] - val[1] + 1;
3233 sc->vres.ddp.start = val[3];
3234 sc->vres.ddp.size = val[4] - val[3] + 1;
3235 sc->params.ofldq_wr_cred = val[5];
3236 sc->params.offload = 1;
3239 param[0] = FW_PARAM_PFVF(STAG_START);
3240 param[1] = FW_PARAM_PFVF(STAG_END);
3241 param[2] = FW_PARAM_PFVF(RQ_START);
3242 param[3] = FW_PARAM_PFVF(RQ_END);
3243 param[4] = FW_PARAM_PFVF(PBL_START);
3244 param[5] = FW_PARAM_PFVF(PBL_END);
3245 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3247 device_printf(sc->dev,
3248 "failed to query RDMA parameters(1): %d.\n", rc);
3251 sc->vres.stag.start = val[0];
3252 sc->vres.stag.size = val[1] - val[0] + 1;
3253 sc->vres.rq.start = val[2];
3254 sc->vres.rq.size = val[3] - val[2] + 1;
3255 sc->vres.pbl.start = val[4];
3256 sc->vres.pbl.size = val[5] - val[4] + 1;
3258 param[0] = FW_PARAM_PFVF(SQRQ_START);
3259 param[1] = FW_PARAM_PFVF(SQRQ_END);
3260 param[2] = FW_PARAM_PFVF(CQ_START);
3261 param[3] = FW_PARAM_PFVF(CQ_END);
3262 param[4] = FW_PARAM_PFVF(OCQ_START);
3263 param[5] = FW_PARAM_PFVF(OCQ_END);
3264 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3266 device_printf(sc->dev,
3267 "failed to query RDMA parameters(2): %d.\n", rc);
3270 sc->vres.qp.start = val[0];
3271 sc->vres.qp.size = val[1] - val[0] + 1;
3272 sc->vres.cq.start = val[2];
3273 sc->vres.cq.size = val[3] - val[2] + 1;
3274 sc->vres.ocq.start = val[4];
3275 sc->vres.ocq.size = val[5] - val[4] + 1;
3277 if (sc->iscsicaps) {
3278 param[0] = FW_PARAM_PFVF(ISCSI_START);
3279 param[1] = FW_PARAM_PFVF(ISCSI_END);
3280 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3282 device_printf(sc->dev,
3283 "failed to query iSCSI parameters: %d.\n", rc);
3286 sc->vres.iscsi.start = val[0];
3287 sc->vres.iscsi.size = val[1] - val[0] + 1;
3290 t4_init_sge_params(sc);
3293 * We've got the params we wanted to query via the firmware. Now grab
3294 * some others directly from the chip.
3296 rc = t4_read_chip_settings(sc);
3302 set_params__post_init(struct adapter *sc)
3304 uint32_t param, val;
3306 /* ask for encapsulated CPLs */
3307 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3309 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3314 #undef FW_PARAM_PFVF
3318 t4_set_desc(struct adapter *sc)
3321 struct adapter_params *p = &sc->params;
3323 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
3325 device_set_desc_copy(sc->dev, buf);
3329 build_medialist(struct port_info *pi, struct ifmedia *media)
3335 ifmedia_removeall(media);
3337 m = IFM_ETHER | IFM_FDX;
3339 switch(pi->port_type) {
3340 case FW_PORT_TYPE_BT_XFI:
3341 case FW_PORT_TYPE_BT_XAUI:
3342 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3345 case FW_PORT_TYPE_BT_SGMII:
3346 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3347 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3348 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3349 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3352 case FW_PORT_TYPE_CX4:
3353 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3354 ifmedia_set(media, m | IFM_10G_CX4);
3357 case FW_PORT_TYPE_QSFP_10G:
3358 case FW_PORT_TYPE_SFP:
3359 case FW_PORT_TYPE_FIBER_XFI:
3360 case FW_PORT_TYPE_FIBER_XAUI:
3361 switch (pi->mod_type) {
3363 case FW_PORT_MOD_TYPE_LR:
3364 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3365 ifmedia_set(media, m | IFM_10G_LR);
3368 case FW_PORT_MOD_TYPE_SR:
3369 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3370 ifmedia_set(media, m | IFM_10G_SR);
3373 case FW_PORT_MOD_TYPE_LRM:
3374 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3375 ifmedia_set(media, m | IFM_10G_LRM);
3378 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3379 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3380 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3381 ifmedia_set(media, m | IFM_10G_TWINAX);
3384 case FW_PORT_MOD_TYPE_NONE:
3386 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3387 ifmedia_set(media, m | IFM_NONE);
3390 case FW_PORT_MOD_TYPE_NA:
3391 case FW_PORT_MOD_TYPE_ER:
3393 device_printf(pi->dev,
3394 "unknown port_type (%d), mod_type (%d)\n",
3395 pi->port_type, pi->mod_type);
3396 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3397 ifmedia_set(media, m | IFM_UNKNOWN);
3402 case FW_PORT_TYPE_CR_QSFP:
3403 case FW_PORT_TYPE_CR_SFP28:
3404 case FW_PORT_TYPE_SFP28:
3405 case FW_PORT_TYPE_KR_SFP28:
3406 switch (pi->mod_type) {
3408 case FW_PORT_MOD_TYPE_SR:
3409 ifmedia_add(media, m | IFM_25G_SR, 0, NULL);
3410 ifmedia_set(media, m | IFM_25G_SR);
3413 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3414 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3415 ifmedia_add(media, m | IFM_25G_CR, 0, NULL);
3416 ifmedia_set(media, m | IFM_25G_CR);
3419 case FW_PORT_MOD_TYPE_NONE:
3421 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3422 ifmedia_set(media, m | IFM_NONE);
3426 device_printf(pi->dev,
3427 "unknown port_type (%d), mod_type (%d)\n",
3428 pi->port_type, pi->mod_type);
3429 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3430 ifmedia_set(media, m | IFM_UNKNOWN);
3435 case FW_PORT_TYPE_QSFP:
3436 switch (pi->mod_type) {
3438 case FW_PORT_MOD_TYPE_LR:
3439 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3440 ifmedia_set(media, m | IFM_40G_LR4);
3443 case FW_PORT_MOD_TYPE_SR:
3444 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3445 ifmedia_set(media, m | IFM_40G_SR4);
3448 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3449 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3450 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3451 ifmedia_set(media, m | IFM_40G_CR4);
3454 case FW_PORT_MOD_TYPE_NONE:
3456 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3457 ifmedia_set(media, m | IFM_NONE);
3461 device_printf(pi->dev,
3462 "unknown port_type (%d), mod_type (%d)\n",
3463 pi->port_type, pi->mod_type);
3464 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3465 ifmedia_set(media, m | IFM_UNKNOWN);
3470 case FW_PORT_TYPE_KR4_100G:
3471 case FW_PORT_TYPE_CR4_QSFP:
3472 switch (pi->mod_type) {
3474 case FW_PORT_MOD_TYPE_LR:
3475 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL);
3476 ifmedia_set(media, m | IFM_100G_LR4);
3479 case FW_PORT_MOD_TYPE_SR:
3480 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL);
3481 ifmedia_set(media, m | IFM_100G_SR4);
3484 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3485 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3486 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL);
3487 ifmedia_set(media, m | IFM_100G_CR4);
3490 case FW_PORT_MOD_TYPE_NONE:
3492 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3493 ifmedia_set(media, m | IFM_NONE);
3497 device_printf(pi->dev,
3498 "unknown port_type (%d), mod_type (%d)\n",
3499 pi->port_type, pi->mod_type);
3500 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3501 ifmedia_set(media, m | IFM_UNKNOWN);
3507 device_printf(pi->dev,
3508 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3510 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3511 ifmedia_set(media, m | IFM_UNKNOWN);
3518 #define FW_MAC_EXACT_CHUNK 7
3521 * Program the port's XGMAC based on parameters in ifnet. The caller also
3522 * indicates which parameters should be programmed (the rest are left alone).
3525 update_mac_settings(struct ifnet *ifp, int flags)
3528 struct vi_info *vi = ifp->if_softc;
3529 struct port_info *pi = vi->pi;
3530 struct adapter *sc = pi->adapter;
3531 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3533 ASSERT_SYNCHRONIZED_OP(sc);
3534 KASSERT(flags, ("%s: not told what to update.", __func__));
3536 if (flags & XGMAC_MTU)
3539 if (flags & XGMAC_PROMISC)
3540 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3542 if (flags & XGMAC_ALLMULTI)
3543 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3545 if (flags & XGMAC_VLANEX)
3546 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3548 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3549 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3550 allmulti, 1, vlanex, false);
3552 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3558 if (flags & XGMAC_UCADDR) {
3559 uint8_t ucaddr[ETHER_ADDR_LEN];
3561 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3562 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3563 ucaddr, true, true);
3566 if_printf(ifp, "change_mac failed: %d\n", rc);
3569 vi->xact_addr_filt = rc;
3574 if (flags & XGMAC_MCADDRS) {
3575 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3578 struct ifmultiaddr *ifma;
3581 if_maddr_rlock(ifp);
3582 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3583 if (ifma->ifma_addr->sa_family != AF_LINK)
3586 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3587 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3590 if (i == FW_MAC_EXACT_CHUNK) {
3591 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3592 del, i, mcaddr, NULL, &hash, 0);
3595 for (j = 0; j < i; j++) {
3597 "failed to add mc address"
3599 "%02x:%02x:%02x rc=%d\n",
3600 mcaddr[j][0], mcaddr[j][1],
3601 mcaddr[j][2], mcaddr[j][3],
3602 mcaddr[j][4], mcaddr[j][5],
3612 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3613 mcaddr, NULL, &hash, 0);
3616 for (j = 0; j < i; j++) {
3618 "failed to add mc address"
3620 "%02x:%02x:%02x rc=%d\n",
3621 mcaddr[j][0], mcaddr[j][1],
3622 mcaddr[j][2], mcaddr[j][3],
3623 mcaddr[j][4], mcaddr[j][5],
3630 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3632 if_printf(ifp, "failed to set mc address hash: %d", rc);
3634 if_maddr_runlock(ifp);
3641 * {begin|end}_synchronized_op must be called from the same thread.
3644 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3650 /* the caller thinks it's ok to sleep, but is it really? */
3651 if (flags & SLEEP_OK)
3652 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3653 "begin_synchronized_op");
3664 if (vi && IS_DOOMED(vi)) {
3674 if (!(flags & SLEEP_OK)) {
3679 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3685 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3688 sc->last_op = wmesg;
3689 sc->last_op_thr = curthread;
3690 sc->last_op_flags = flags;
3694 if (!(flags & HOLD_LOCK) || rc)
3701 * Tell if_ioctl and if_init that the VI is going away. This is
3702 * special variant of begin_synchronized_op and must be paired with a
3703 * call to end_synchronized_op.
3706 doom_vi(struct adapter *sc, struct vi_info *vi)
3713 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3716 sc->last_op = "t4detach";
3717 sc->last_op_thr = curthread;
3718 sc->last_op_flags = 0;
3724 * {begin|end}_synchronized_op must be called from the same thread.
3727 end_synchronized_op(struct adapter *sc, int flags)
3730 if (flags & LOCK_HELD)
3731 ADAPTER_LOCK_ASSERT_OWNED(sc);
3735 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3742 cxgbe_init_synchronized(struct vi_info *vi)
3744 struct port_info *pi = vi->pi;
3745 struct adapter *sc = pi->adapter;
3746 struct ifnet *ifp = vi->ifp;
3748 struct sge_txq *txq;
3750 ASSERT_SYNCHRONIZED_OP(sc);
3752 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3753 return (0); /* already running */
3755 if (!(sc->flags & FULL_INIT_DONE) &&
3756 ((rc = adapter_full_init(sc)) != 0))
3757 return (rc); /* error message displayed already */
3759 if (!(vi->flags & VI_INIT_DONE) &&
3760 ((rc = vi_full_init(vi)) != 0))
3761 return (rc); /* error message displayed already */
3763 rc = update_mac_settings(ifp, XGMAC_ALL);
3765 goto done; /* error message displayed already */
3767 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
3769 if_printf(ifp, "enable_vi failed: %d\n", rc);
3774 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
3778 for_each_txq(vi, i, txq) {
3780 txq->eq.flags |= EQ_ENABLED;
3785 * The first iq of the first port to come up is used for tracing.
3787 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
3788 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
3789 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
3790 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3791 V_QUEUENUMBER(sc->traceq));
3792 pi->flags |= HAS_TRACEQ;
3797 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3800 if (pi->nvi > 1 || sc->flags & IS_VF)
3801 callout_reset(&vi->tick, hz, vi_tick, vi);
3803 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3807 cxgbe_uninit_synchronized(vi);
3816 cxgbe_uninit_synchronized(struct vi_info *vi)
3818 struct port_info *pi = vi->pi;
3819 struct adapter *sc = pi->adapter;
3820 struct ifnet *ifp = vi->ifp;
3822 struct sge_txq *txq;
3824 ASSERT_SYNCHRONIZED_OP(sc);
3826 if (!(vi->flags & VI_INIT_DONE)) {
3827 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
3828 ("uninited VI is running"));
3833 * Disable the VI so that all its data in either direction is discarded
3834 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
3835 * tick) intact as the TP can deliver negative advice or data that it's
3836 * holding in its RAM (for an offloaded connection) even after the VI is
3839 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
3841 if_printf(ifp, "disable_vi failed: %d\n", rc);
3845 for_each_txq(vi, i, txq) {
3847 txq->eq.flags &= ~EQ_ENABLED;
3852 if (pi->nvi > 1 || sc->flags & IS_VF)
3853 callout_stop(&vi->tick);
3855 callout_stop(&pi->tick);
3856 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3860 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3862 if (pi->up_vis > 0) {
3868 pi->link_cfg.link_ok = 0;
3869 pi->link_cfg.speed = 0;
3871 t4_os_link_changed(sc, pi->port_id, 0, -1);
3877 * It is ok for this function to fail midway and return right away. t4_detach
3878 * will walk the entire sc->irq list and clean up whatever is valid.
3881 t4_setup_intr_handlers(struct adapter *sc)
3883 int rc, rid, p, q, v;
3886 struct port_info *pi;
3888 struct sge *sge = &sc->sge;
3889 struct sge_rxq *rxq;
3891 struct sge_ofld_rxq *ofld_rxq;
3894 struct sge_nm_rxq *nm_rxq;
3901 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3902 if (sc->intr_count == 1)
3903 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3905 /* Multiple interrupts. */
3906 if (sc->flags & IS_VF)
3907 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
3908 ("%s: too few intr.", __func__));
3910 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3911 ("%s: too few intr.", __func__));
3913 /* The first one is always error intr on PFs */
3914 if (!(sc->flags & IS_VF)) {
3915 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3922 /* The second one is always the firmware event queue (first on VFs) */
3923 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
3929 for_each_port(sc, p) {
3931 for_each_vi(pi, v, vi) {
3932 vi->first_intr = rid - 1;
3934 if (vi->nnmrxq > 0) {
3935 int n = max(vi->nrxq, vi->nnmrxq);
3937 MPASS(vi->flags & INTR_RXQ);
3939 rxq = &sge->rxq[vi->first_rxq];
3941 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
3943 for (q = 0; q < n; q++) {
3944 snprintf(s, sizeof(s), "%x%c%x", p,
3950 irq->nm_rxq = nm_rxq++;
3952 rc = t4_alloc_irq(sc, irq, rid,
3953 t4_vi_intr, irq, s);
3960 } else if (vi->flags & INTR_RXQ) {
3961 for_each_rxq(vi, q, rxq) {
3962 snprintf(s, sizeof(s), "%x%c%x", p,
3964 rc = t4_alloc_irq(sc, irq, rid,
3974 if (vi->flags & INTR_OFLD_RXQ) {
3975 for_each_ofld_rxq(vi, q, ofld_rxq) {
3976 snprintf(s, sizeof(s), "%x%c%x", p,
3978 rc = t4_alloc_irq(sc, irq, rid,
3979 t4_intr, ofld_rxq, s);
3990 MPASS(irq == &sc->irq[sc->intr_count]);
3996 adapter_full_init(struct adapter *sc)
4000 ASSERT_SYNCHRONIZED_OP(sc);
4001 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4002 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
4003 ("%s: FULL_INIT_DONE already", __func__));
4006 * queues that belong to the adapter (not any particular port).
4008 rc = t4_setup_adapter_queues(sc);
4012 for (i = 0; i < nitems(sc->tq); i++) {
4013 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
4014 taskqueue_thread_enqueue, &sc->tq[i]);
4015 if (sc->tq[i] == NULL) {
4016 device_printf(sc->dev,
4017 "failed to allocate task queue %d\n", i);
4021 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
4022 device_get_nameunit(sc->dev), i);
4025 if (!(sc->flags & IS_VF))
4027 sc->flags |= FULL_INIT_DONE;
4030 adapter_full_uninit(sc);
4036 adapter_full_uninit(struct adapter *sc)
4040 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4042 t4_teardown_adapter_queues(sc);
4044 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4045 taskqueue_free(sc->tq[i]);
4049 sc->flags &= ~FULL_INIT_DONE;
4055 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4056 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4057 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4058 RSS_HASHTYPE_RSS_UDP_IPV6)
4060 /* Translates kernel hash types to hardware. */
4062 hashconfig_to_hashen(int hashconfig)
4066 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4067 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4068 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4069 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4070 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4071 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4072 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4074 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4075 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4076 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4078 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4079 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4080 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4081 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4086 /* Translates hardware hash types to kernel. */
4088 hashen_to_hashconfig(int hashen)
4092 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
4094 * If UDP hashing was enabled it must have been enabled for
4095 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
4096 * enabling any 4-tuple hash is nonsense configuration.
4098 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4099 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
4101 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4102 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
4103 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4104 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
4106 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4107 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
4108 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4109 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
4110 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
4111 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
4112 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
4113 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
4115 return (hashconfig);
4120 vi_full_init(struct vi_info *vi)
4122 struct adapter *sc = vi->pi->adapter;
4123 struct ifnet *ifp = vi->ifp;
4125 struct sge_rxq *rxq;
4126 int rc, i, j, hashen;
4128 int nbuckets = rss_getnumbuckets();
4129 int hashconfig = rss_gethashconfig();
4131 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4132 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4135 ASSERT_SYNCHRONIZED_OP(sc);
4136 KASSERT((vi->flags & VI_INIT_DONE) == 0,
4137 ("%s: VI_INIT_DONE already", __func__));
4139 sysctl_ctx_init(&vi->ctx);
4140 vi->flags |= VI_SYSCTL_CTX;
4143 * Allocate tx/rx/fl queues for this VI.
4145 rc = t4_setup_vi_queues(vi);
4147 goto done; /* error message displayed already */
4150 * Setup RSS for this VI. Save a copy of the RSS table for later use.
4152 if (vi->nrxq > vi->rss_size) {
4153 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
4154 "some queues will never receive traffic.\n", vi->nrxq,
4156 } else if (vi->rss_size % vi->nrxq) {
4157 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
4158 "expect uneven traffic distribution.\n", vi->nrxq,
4162 MPASS(RSS_KEYSIZE == 40);
4163 if (vi->nrxq != nbuckets) {
4164 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
4165 "performance will be impacted.\n", vi->nrxq, nbuckets);
4168 rss_getkey((void *)&raw_rss_key[0]);
4169 for (i = 0; i < nitems(rss_key); i++) {
4170 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4172 t4_write_rss_key(sc, &rss_key[0], -1);
4174 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
4175 for (i = 0; i < vi->rss_size;) {
4177 j = rss_get_indirection_to_bucket(i);
4179 rxq = &sc->sge.rxq[vi->first_rxq + j];
4180 rss[i++] = rxq->iq.abs_id;
4182 for_each_rxq(vi, j, rxq) {
4183 rss[i++] = rxq->iq.abs_id;
4184 if (i == vi->rss_size)
4190 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
4193 if_printf(ifp, "rss_config failed: %d\n", rc);
4198 hashen = hashconfig_to_hashen(hashconfig);
4201 * We may have had to enable some hashes even though the global config
4202 * wants them disabled. This is a potential problem that must be
4203 * reported to the user.
4205 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4208 * If we consider only the supported hash types, then the enabled hashes
4209 * are a superset of the requested hashes. In other words, there cannot
4210 * be any supported hash that was requested but not enabled, but there
4211 * can be hashes that were not requested but had to be enabled.
4213 extra &= SUPPORTED_RSS_HASHTYPES;
4214 MPASS((extra & hashconfig) == 0);
4218 "global RSS config (0x%x) cannot be accomodated.\n",
4221 if (extra & RSS_HASHTYPE_RSS_IPV4)
4222 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4223 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4224 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4225 if (extra & RSS_HASHTYPE_RSS_IPV6)
4226 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4227 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4228 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4229 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4230 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4231 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4232 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4234 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4235 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4236 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4237 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4239 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
4241 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4246 vi->flags |= VI_INIT_DONE;
4258 vi_full_uninit(struct vi_info *vi)
4260 struct port_info *pi = vi->pi;
4261 struct adapter *sc = pi->adapter;
4263 struct sge_rxq *rxq;
4264 struct sge_txq *txq;
4266 struct sge_ofld_rxq *ofld_rxq;
4267 struct sge_wrq *ofld_txq;
4270 if (vi->flags & VI_INIT_DONE) {
4272 /* Need to quiesce queues. */
4274 /* XXX: Only for the first VI? */
4275 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
4276 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4278 for_each_txq(vi, i, txq) {
4279 quiesce_txq(sc, txq);
4283 for_each_ofld_txq(vi, i, ofld_txq) {
4284 quiesce_wrq(sc, ofld_txq);
4288 for_each_rxq(vi, i, rxq) {
4289 quiesce_iq(sc, &rxq->iq);
4290 quiesce_fl(sc, &rxq->fl);
4294 for_each_ofld_rxq(vi, i, ofld_rxq) {
4295 quiesce_iq(sc, &ofld_rxq->iq);
4296 quiesce_fl(sc, &ofld_rxq->fl);
4299 free(vi->rss, M_CXGBE);
4300 free(vi->nm_rss, M_CXGBE);
4303 t4_teardown_vi_queues(vi);
4304 vi->flags &= ~VI_INIT_DONE;
4310 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4312 struct sge_eq *eq = &txq->eq;
4313 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4315 (void) sc; /* unused */
4319 MPASS((eq->flags & EQ_ENABLED) == 0);
4323 /* Wait for the mp_ring to empty. */
4324 while (!mp_ring_is_idle(txq->r)) {
4325 mp_ring_check_drainage(txq->r, 0);
4326 pause("rquiesce", 1);
4329 /* Then wait for the hardware to finish. */
4330 while (spg->cidx != htobe16(eq->pidx))
4331 pause("equiesce", 1);
4333 /* Finally, wait for the driver to reclaim all descriptors. */
4334 while (eq->cidx != eq->pidx)
4335 pause("dquiesce", 1);
4339 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4346 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4348 (void) sc; /* unused */
4350 /* Synchronize with the interrupt handler */
4351 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4356 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4358 mtx_lock(&sc->sfl_lock);
4360 fl->flags |= FL_DOOMED;
4362 callout_stop(&sc->sfl_callout);
4363 mtx_unlock(&sc->sfl_lock);
4365 KASSERT((fl->flags & FL_STARVING) == 0,
4366 ("%s: still starving", __func__));
4370 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4371 driver_intr_t *handler, void *arg, char *name)
4376 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4377 RF_SHAREABLE | RF_ACTIVE);
4378 if (irq->res == NULL) {
4379 device_printf(sc->dev,
4380 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4384 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4385 NULL, handler, arg, &irq->tag);
4387 device_printf(sc->dev,
4388 "failed to setup interrupt for rid %d, name %s: %d\n",
4391 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
4397 t4_free_irq(struct adapter *sc, struct irq *irq)
4400 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4402 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4404 bzero(irq, sizeof(*irq));
4410 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4413 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4414 t4_get_regs(sc, buf, regs->len);
4417 #define A_PL_INDIR_CMD 0x1f8
4419 #define S_PL_AUTOINC 31
4420 #define M_PL_AUTOINC 0x1U
4421 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4422 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4424 #define S_PL_VFID 20
4425 #define M_PL_VFID 0xffU
4426 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4427 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4430 #define M_PL_ADDR 0xfffffU
4431 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4432 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4434 #define A_PL_INDIR_DATA 0x1fc
4437 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4441 mtx_assert(&sc->reg_lock, MA_OWNED);
4442 if (sc->flags & IS_VF) {
4443 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
4444 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
4446 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4447 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4448 V_PL_ADDR(VF_MPS_REG(reg)));
4449 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4450 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4452 return (((uint64_t)stats[1]) << 32 | stats[0]);
4456 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4457 struct fw_vi_stats_vf *stats)
4460 #define GET_STAT(name) \
4461 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4463 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4464 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4465 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4466 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4467 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4468 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4469 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4470 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4471 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4472 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4473 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4474 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4475 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4476 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4477 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4478 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4484 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4488 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4489 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4490 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4491 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4492 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4493 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4497 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4499 struct ifnet *ifp = vi->ifp;
4500 struct sge_txq *txq;
4502 struct fw_vi_stats_vf *s = &vi->stats;
4504 const struct timeval interval = {0, 250000}; /* 250ms */
4506 if (!(vi->flags & VI_INIT_DONE))
4510 timevalsub(&tv, &interval);
4511 if (timevalcmp(&tv, &vi->last_refreshed, <))
4514 mtx_lock(&sc->reg_lock);
4515 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4517 ifp->if_ipackets = s->rx_bcast_frames + s->rx_mcast_frames +
4519 ifp->if_ierrors = s->rx_err_frames;
4520 ifp->if_opackets = s->tx_bcast_frames + s->tx_mcast_frames +
4521 s->tx_ucast_frames + s->tx_offload_frames;
4522 ifp->if_oerrors = s->tx_drop_frames;
4523 ifp->if_ibytes = s->rx_bcast_bytes + s->rx_mcast_bytes +
4525 ifp->if_obytes = s->tx_bcast_bytes + s->tx_mcast_bytes +
4526 s->tx_ucast_bytes + s->tx_offload_bytes;
4527 ifp->if_imcasts = s->rx_mcast_frames;
4528 ifp->if_omcasts = s->tx_mcast_frames;
4531 for_each_txq(vi, i, txq)
4532 drops += counter_u64_fetch(txq->r->drops);
4533 ifp->if_snd.ifq_drops = drops;
4535 getmicrotime(&vi->last_refreshed);
4536 mtx_unlock(&sc->reg_lock);
4540 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4542 struct vi_info *vi = &pi->vi[0];
4543 struct ifnet *ifp = vi->ifp;
4544 struct sge_txq *txq;
4546 struct port_stats *s = &pi->stats;
4548 const struct timeval interval = {0, 250000}; /* 250ms */
4551 timevalsub(&tv, &interval);
4552 if (timevalcmp(&tv, &pi->last_refreshed, <))
4555 t4_get_port_stats(sc, pi->tx_chan, s);
4557 ifp->if_opackets = s->tx_frames;
4558 ifp->if_ipackets = s->rx_frames;
4559 ifp->if_obytes = s->tx_octets;
4560 ifp->if_ibytes = s->rx_octets;
4561 ifp->if_omcasts = s->tx_mcast_frames;
4562 ifp->if_imcasts = s->rx_mcast_frames;
4563 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4564 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4566 for (i = 0; i < sc->chip_params->nchan; i++) {
4567 if (pi->rx_chan_map & (1 << i)) {
4570 mtx_lock(&sc->reg_lock);
4571 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4572 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4573 mtx_unlock(&sc->reg_lock);
4574 ifp->if_iqdrops += v;
4579 for_each_txq(vi, i, txq)
4580 drops += counter_u64_fetch(txq->r->drops);
4581 ifp->if_snd.ifq_drops = drops;
4583 ifp->if_oerrors = s->tx_error_frames;
4584 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4585 s->rx_fcs_err + s->rx_len_err;
4587 getmicrotime(&pi->last_refreshed);
4591 cxgbe_tick(void *arg)
4593 struct port_info *pi = arg;
4594 struct adapter *sc = pi->adapter;
4596 PORT_LOCK_ASSERT_OWNED(pi);
4597 cxgbe_refresh_stats(sc, pi);
4599 callout_schedule(&pi->tick, hz);
4605 struct vi_info *vi = arg;
4606 struct adapter *sc = vi->pi->adapter;
4608 vi_refresh_stats(sc, vi);
4610 callout_schedule(&vi->tick, hz);
4614 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4618 if (arg != ifp || ifp->if_type != IFT_ETHER)
4621 vlan = VLAN_DEVAT(ifp, vid);
4622 VLAN_SETCOOKIE(vlan, ifp);
4626 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4628 static char *caps_decoder[] = {
4629 "\20\001IPMI\002NCSI", /* 0: NBM */
4630 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4631 "\20\001INGRESS\002EGRESS", /* 2: switch */
4632 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4633 "\006HASHFILTER\007ETHOFLD",
4634 "\20\001TOE", /* 4: TOE */
4635 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4636 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4637 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4638 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4640 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4641 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
4642 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4643 "\004PO_INITIATOR\005PO_TARGET",
4647 t4_sysctls(struct adapter *sc)
4649 struct sysctl_ctx_list *ctx;
4650 struct sysctl_oid *oid;
4651 struct sysctl_oid_list *children, *c0;
4652 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4654 ctx = device_get_sysctl_ctx(sc->dev);
4659 oid = device_get_sysctl_tree(sc->dev);
4660 c0 = children = SYSCTL_CHILDREN(oid);
4662 sc->sc_do_rxcopy = 1;
4663 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4664 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4666 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4667 sc->params.nports, "# of ports");
4669 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4670 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4671 sysctl_bitfield, "A", "available doorbells");
4673 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4674 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4676 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4677 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4678 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4679 "interrupt holdoff timer values (us)");
4681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4682 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4683 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4684 "interrupt holdoff packet counter values");
4686 t4_sge_sysctls(sc, ctx, children);
4688 sc->lro_timeout = 100;
4689 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4690 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4692 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
4693 &sc->debug_flags, 0, "flags to enable runtime debugging");
4695 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
4696 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
4698 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4699 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4701 if (sc->flags & IS_VF)
4704 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4705 NULL, chip_rev(sc), "chip hardware revision");
4707 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
4708 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
4710 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
4711 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
4713 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
4714 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
4716 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
4717 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
4719 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
4720 sc->er_version, 0, "expansion ROM version");
4722 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
4723 sc->bs_version, 0, "bootstrap firmware version");
4725 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
4726 NULL, sc->params.scfg_vers, "serial config version");
4728 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
4729 NULL, sc->params.vpd_vers, "VPD version");
4731 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4732 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4734 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4735 sc->cfcsum, "config file checksum");
4737 #define SYSCTL_CAP(name, n, text) \
4738 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4739 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4740 sysctl_bitfield, "A", "available " text " capabilities")
4742 SYSCTL_CAP(nbmcaps, 0, "NBM");
4743 SYSCTL_CAP(linkcaps, 1, "link");
4744 SYSCTL_CAP(switchcaps, 2, "switch");
4745 SYSCTL_CAP(niccaps, 3, "NIC");
4746 SYSCTL_CAP(toecaps, 4, "TCP offload");
4747 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4748 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4749 SYSCTL_CAP(cryptocaps, 7, "crypto");
4750 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4753 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4754 NULL, sc->tids.nftids, "number of filters");
4756 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4757 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4758 "chip temperature (in Celsius)");
4762 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4764 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4765 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4766 "logs and miscellaneous information");
4767 children = SYSCTL_CHILDREN(oid);
4769 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4770 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4771 sysctl_cctrl, "A", "congestion control");
4773 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4774 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4775 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4777 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4778 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4779 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4781 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4782 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4783 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4785 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4786 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4787 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4789 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4790 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4791 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4793 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4794 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4795 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4797 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4798 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4799 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
4800 "A", "CIM logic analyzer");
4802 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4803 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4804 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4806 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4807 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4808 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4810 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4811 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4812 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4814 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4815 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4816 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4818 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4819 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4820 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4822 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4823 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4824 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4826 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4827 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4828 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4830 if (chip_id(sc) > CHELSIO_T4) {
4831 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4832 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4833 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4835 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4836 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4837 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4841 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4842 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4844 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4845 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4846 sysctl_cim_qcfg, "A", "CIM queue configuration");
4848 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4849 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4850 sysctl_cpl_stats, "A", "CPL statistics");
4852 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4853 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4854 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4856 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4857 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4858 sysctl_devlog, "A", "firmware's device log");
4860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4861 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4862 sysctl_fcoe_stats, "A", "FCoE statistics");
4864 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4865 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4866 sysctl_hw_sched, "A", "hardware scheduler ");
4868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4869 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4870 sysctl_l2t, "A", "hardware L2 table");
4872 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4873 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4874 sysctl_lb_stats, "A", "loopback statistics");
4876 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4877 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4878 sysctl_meminfo, "A", "memory regions");
4880 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4881 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4882 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
4883 "A", "MPS TCAM entries");
4885 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4886 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4887 sysctl_path_mtus, "A", "path MTUs");
4889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4890 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4891 sysctl_pm_stats, "A", "PM statistics");
4893 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4894 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4895 sysctl_rdma_stats, "A", "RDMA statistics");
4897 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4898 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4899 sysctl_tcp_stats, "A", "TCP statistics");
4901 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4902 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4903 sysctl_tids, "A", "TID information");
4905 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4906 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4907 sysctl_tp_err_stats, "A", "TP error statistics");
4909 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
4910 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
4911 "TP logic analyzer event capture mask");
4913 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4914 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4915 sysctl_tp_la, "A", "TP logic analyzer");
4917 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4918 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4919 sysctl_tx_rate, "A", "Tx rate");
4921 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4922 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4923 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4925 if (chip_id(sc) >= CHELSIO_T5) {
4926 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4927 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4928 sysctl_wcwr_stats, "A", "write combined work requests");
4933 if (is_offload(sc)) {
4937 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4938 NULL, "TOE parameters");
4939 children = SYSCTL_CHILDREN(oid);
4941 sc->tt.sndbuf = 256 * 1024;
4942 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4943 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4946 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4947 &sc->tt.ddp, 0, "DDP allowed");
4949 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
4950 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
4951 &sc->tt.indsz, 0, "DDP max indicate size allowed");
4954 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
4955 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
4956 &sc->tt.ddp_thres, 0, "DDP threshold");
4958 sc->tt.rx_coalesce = 1;
4959 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4960 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4962 sc->tt.tx_align = 1;
4963 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4964 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4966 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
4967 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
4968 "TP timer tick (us)");
4970 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
4971 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
4972 "TCP timestamp tick (us)");
4974 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
4975 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
4978 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
4979 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
4980 "IU", "DACK timer (us)");
4982 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
4983 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
4984 sysctl_tp_timer, "LU", "Retransmit min (us)");
4986 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
4987 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
4988 sysctl_tp_timer, "LU", "Retransmit max (us)");
4990 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
4991 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
4992 sysctl_tp_timer, "LU", "Persist timer min (us)");
4994 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
4995 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
4996 sysctl_tp_timer, "LU", "Persist timer max (us)");
4998 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
4999 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
5000 sysctl_tp_timer, "LU", "Keepidle idle timer (us)");
5002 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl",
5003 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
5004 sysctl_tp_timer, "LU", "Keepidle interval (us)");
5006 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
5007 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
5008 sysctl_tp_timer, "LU", "Initial SRTT (us)");
5010 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
5011 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
5012 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
5018 vi_sysctls(struct vi_info *vi)
5020 struct sysctl_ctx_list *ctx;
5021 struct sysctl_oid *oid;
5022 struct sysctl_oid_list *children;
5024 ctx = device_get_sysctl_ctx(vi->dev);
5027 * dev.v?(cxgbe|cxl).X.
5029 oid = device_get_sysctl_tree(vi->dev);
5030 children = SYSCTL_CHILDREN(oid);
5032 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
5033 vi->viid, "VI identifer");
5034 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
5035 &vi->nrxq, 0, "# of rx queues");
5036 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
5037 &vi->ntxq, 0, "# of tx queues");
5038 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
5039 &vi->first_rxq, 0, "index of first rx queue");
5040 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
5041 &vi->first_txq, 0, "index of first tx queue");
5042 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
5043 vi->rss_size, "size of RSS indirection table");
5045 if (IS_MAIN_VI(vi)) {
5046 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
5047 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
5048 "Reserve queue 0 for non-flowid packets");
5052 if (vi->nofldrxq != 0) {
5053 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
5055 "# of rx queues for offloaded TCP connections");
5056 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
5058 "# of tx queues for offloaded TCP connections");
5059 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
5060 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
5061 "index of first TOE rx queue");
5062 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
5063 CTLFLAG_RD, &vi->first_ofld_txq, 0,
5064 "index of first TOE tx queue");
5068 if (vi->nnmrxq != 0) {
5069 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
5070 &vi->nnmrxq, 0, "# of netmap rx queues");
5071 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
5072 &vi->nnmtxq, 0, "# of netmap tx queues");
5073 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
5074 CTLFLAG_RD, &vi->first_nm_rxq, 0,
5075 "index of first netmap rx queue");
5076 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
5077 CTLFLAG_RD, &vi->first_nm_txq, 0,
5078 "index of first netmap tx queue");
5082 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
5083 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
5084 "holdoff timer index");
5085 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
5086 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
5087 "holdoff packet counter index");
5089 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
5090 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
5092 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
5093 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
5098 cxgbe_sysctls(struct port_info *pi)
5100 struct sysctl_ctx_list *ctx;
5101 struct sysctl_oid *oid;
5102 struct sysctl_oid_list *children, *children2;
5103 struct adapter *sc = pi->adapter;
5107 ctx = device_get_sysctl_ctx(pi->dev);
5112 oid = device_get_sysctl_tree(pi->dev);
5113 children = SYSCTL_CHILDREN(oid);
5115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
5116 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
5117 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
5118 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
5119 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
5120 "PHY temperature (in Celsius)");
5121 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
5122 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
5123 "PHY firmware version");
5126 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
5127 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings,
5128 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
5130 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
5131 port_top_speed(pi), "max speed (in Gbps)");
5133 if (sc->flags & IS_VF)
5137 * dev.(cxgbe|cxl).X.tc.
5139 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
5140 "Tx scheduler traffic classes");
5141 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
5142 struct tx_sched_class *tc = &pi->tc[i];
5144 snprintf(name, sizeof(name), "%d", i);
5145 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
5146 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
5148 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
5149 &tc->flags, 0, "flags");
5150 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
5151 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
5153 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
5154 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
5155 sysctl_tc_params, "A", "traffic class parameters");
5160 * dev.cxgbe.X.stats.
5162 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
5163 NULL, "port statistics");
5164 children = SYSCTL_CHILDREN(oid);
5165 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
5166 &pi->tx_parse_error, 0,
5167 "# of tx packets with invalid length or # of segments");
5169 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
5170 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
5171 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
5172 sysctl_handle_t4_reg64, "QU", desc)
5174 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
5175 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
5176 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
5177 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
5178 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
5179 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
5180 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
5181 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
5182 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
5183 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
5184 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
5185 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
5186 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
5187 "# of tx frames in this range",
5188 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
5189 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
5190 "# of tx frames in this range",
5191 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
5192 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
5193 "# of tx frames in this range",
5194 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
5195 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
5196 "# of tx frames in this range",
5197 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
5198 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
5199 "# of tx frames in this range",
5200 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
5201 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
5202 "# of tx frames in this range",
5203 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
5204 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
5205 "# of tx frames in this range",
5206 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
5207 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
5208 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
5209 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
5210 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
5211 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
5212 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
5213 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
5214 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
5215 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
5216 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
5217 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
5218 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
5219 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
5220 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
5221 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
5222 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
5223 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
5224 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
5225 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
5226 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
5228 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
5229 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
5230 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
5231 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
5232 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
5233 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
5234 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
5235 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
5236 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
5237 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
5238 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
5239 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
5240 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5241 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5242 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5243 "# of frames received with bad FCS",
5244 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5245 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5246 "# of frames received with length error",
5247 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5248 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5249 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5250 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5251 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5252 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5253 "# of rx frames in this range",
5254 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5255 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5256 "# of rx frames in this range",
5257 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5258 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5259 "# of rx frames in this range",
5260 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5261 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5262 "# of rx frames in this range",
5263 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5264 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5265 "# of rx frames in this range",
5266 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5267 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5268 "# of rx frames in this range",
5269 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5270 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5271 "# of rx frames in this range",
5272 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5273 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5274 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5275 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5276 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5277 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5278 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5279 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5280 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5281 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5282 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5283 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5284 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5285 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5286 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5287 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5288 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5289 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5290 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5292 #undef SYSCTL_ADD_T4_REG64
5294 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5295 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5296 &pi->stats.name, desc)
5298 /* We get these from port_stats and they may be stale by upto 1s */
5299 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5300 "# drops due to buffer-group 0 overflows");
5301 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5302 "# drops due to buffer-group 1 overflows");
5303 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5304 "# drops due to buffer-group 2 overflows");
5305 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5306 "# drops due to buffer-group 3 overflows");
5307 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5308 "# of buffer-group 0 truncated packets");
5309 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5310 "# of buffer-group 1 truncated packets");
5311 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5312 "# of buffer-group 2 truncated packets");
5313 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5314 "# of buffer-group 3 truncated packets");
5316 #undef SYSCTL_ADD_T4_PORTSTAT
5320 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5322 int rc, *i, space = 0;
5325 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5326 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5328 sbuf_printf(&sb, " ");
5329 sbuf_printf(&sb, "%d", *i);
5333 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5339 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5344 rc = sysctl_wire_old_buffer(req, 0);
5348 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5352 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5353 rc = sbuf_finish(sb);
5360 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5362 struct port_info *pi = arg1;
5364 struct adapter *sc = pi->adapter;
5368 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5371 /* XXX: magic numbers */
5372 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5374 end_synchronized_op(sc, 0);
5380 rc = sysctl_handle_int(oidp, &v, 0, req);
5385 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5387 struct vi_info *vi = arg1;
5390 val = vi->rsrv_noflowq;
5391 rc = sysctl_handle_int(oidp, &val, 0, req);
5392 if (rc != 0 || req->newptr == NULL)
5395 if ((val >= 1) && (vi->ntxq > 1))
5396 vi->rsrv_noflowq = 1;
5398 vi->rsrv_noflowq = 0;
5404 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5406 struct vi_info *vi = arg1;
5407 struct adapter *sc = vi->pi->adapter;
5409 struct sge_rxq *rxq;
5411 struct sge_ofld_rxq *ofld_rxq;
5417 rc = sysctl_handle_int(oidp, &idx, 0, req);
5418 if (rc != 0 || req->newptr == NULL)
5421 if (idx < 0 || idx >= SGE_NTIMERS)
5424 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5429 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5430 for_each_rxq(vi, i, rxq) {
5431 #ifdef atomic_store_rel_8
5432 atomic_store_rel_8(&rxq->iq.intr_params, v);
5434 rxq->iq.intr_params = v;
5438 for_each_ofld_rxq(vi, i, ofld_rxq) {
5439 #ifdef atomic_store_rel_8
5440 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5442 ofld_rxq->iq.intr_params = v;
5448 end_synchronized_op(sc, LOCK_HELD);
5453 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5455 struct vi_info *vi = arg1;
5456 struct adapter *sc = vi->pi->adapter;
5461 rc = sysctl_handle_int(oidp, &idx, 0, req);
5462 if (rc != 0 || req->newptr == NULL)
5465 if (idx < -1 || idx >= SGE_NCOUNTERS)
5468 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5473 if (vi->flags & VI_INIT_DONE)
5474 rc = EBUSY; /* cannot be changed once the queues are created */
5478 end_synchronized_op(sc, LOCK_HELD);
5483 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5485 struct vi_info *vi = arg1;
5486 struct adapter *sc = vi->pi->adapter;
5489 qsize = vi->qsize_rxq;
5491 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5492 if (rc != 0 || req->newptr == NULL)
5495 if (qsize < 128 || (qsize & 7))
5498 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5503 if (vi->flags & VI_INIT_DONE)
5504 rc = EBUSY; /* cannot be changed once the queues are created */
5506 vi->qsize_rxq = qsize;
5508 end_synchronized_op(sc, LOCK_HELD);
5513 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5515 struct vi_info *vi = arg1;
5516 struct adapter *sc = vi->pi->adapter;
5519 qsize = vi->qsize_txq;
5521 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5522 if (rc != 0 || req->newptr == NULL)
5525 if (qsize < 128 || qsize > 65536)
5528 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5533 if (vi->flags & VI_INIT_DONE)
5534 rc = EBUSY; /* cannot be changed once the queues are created */
5536 vi->qsize_txq = qsize;
5538 end_synchronized_op(sc, LOCK_HELD);
5543 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5545 struct port_info *pi = arg1;
5546 struct adapter *sc = pi->adapter;
5547 struct link_config *lc = &pi->link_cfg;
5550 if (req->newptr == NULL) {
5552 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5554 rc = sysctl_wire_old_buffer(req, 0);
5558 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5562 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5563 rc = sbuf_finish(sb);
5569 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5572 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5578 if (s[0] < '0' || s[0] > '9')
5579 return (EINVAL); /* not a number */
5581 if (n & ~(PAUSE_TX | PAUSE_RX))
5582 return (EINVAL); /* some other bit is set too */
5584 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5588 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5589 int link_ok = lc->link_ok;
5591 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5592 lc->requested_fc |= n;
5593 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5594 lc->link_ok = link_ok; /* restore */
5596 end_synchronized_op(sc, 0);
5603 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5605 struct adapter *sc = arg1;
5609 val = t4_read_reg64(sc, reg);
5611 return (sysctl_handle_64(oidp, &val, 0, req));
5615 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5617 struct adapter *sc = arg1;
5619 uint32_t param, val;
5621 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5624 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5625 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5626 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5627 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5628 end_synchronized_op(sc, 0);
5632 /* unknown is returned as 0 but we display -1 in that case */
5633 t = val == 0 ? -1 : val;
5635 rc = sysctl_handle_int(oidp, &t, 0, req);
5641 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5643 struct adapter *sc = arg1;
5646 uint16_t incr[NMTUS][NCCTRL_WIN];
5647 static const char *dec_fac[] = {
5648 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5652 rc = sysctl_wire_old_buffer(req, 0);
5656 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5660 t4_read_cong_tbl(sc, incr);
5662 for (i = 0; i < NCCTRL_WIN; ++i) {
5663 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5664 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5665 incr[5][i], incr[6][i], incr[7][i]);
5666 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5667 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5668 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5669 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5672 rc = sbuf_finish(sb);
5678 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5679 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
5680 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5681 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
5685 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5687 struct adapter *sc = arg1;
5689 int rc, i, n, qid = arg2;
5692 u_int cim_num_obq = sc->chip_params->cim_num_obq;
5694 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5695 ("%s: bad qid %d\n", __func__, qid));
5697 if (qid < CIM_NUM_IBQ) {
5700 n = 4 * CIM_IBQ_SIZE;
5701 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5702 rc = t4_read_cim_ibq(sc, qid, buf, n);
5704 /* outbound queue */
5707 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5708 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5709 rc = t4_read_cim_obq(sc, qid, buf, n);
5716 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
5718 rc = sysctl_wire_old_buffer(req, 0);
5722 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5728 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5729 for (i = 0, p = buf; i < n; i += 16, p += 4)
5730 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5733 rc = sbuf_finish(sb);
5741 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5743 struct adapter *sc = arg1;
5749 MPASS(chip_id(sc) <= CHELSIO_T5);
5751 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5755 rc = sysctl_wire_old_buffer(req, 0);
5759 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5763 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5766 rc = -t4_cim_read_la(sc, buf, NULL);
5770 sbuf_printf(sb, "Status Data PC%s",
5771 cfg & F_UPDBGLACAPTPCONLY ? "" :
5772 " LS0Stat LS0Addr LS0Data");
5774 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
5775 if (cfg & F_UPDBGLACAPTPCONLY) {
5776 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5778 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5779 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5780 p[4] & 0xff, p[5] >> 8);
5781 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5782 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5783 p[1] & 0xf, p[2] >> 4);
5786 "\n %02x %x%07x %x%07x %08x %08x "
5788 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5789 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5794 rc = sbuf_finish(sb);
5802 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
5804 struct adapter *sc = arg1;
5810 MPASS(chip_id(sc) > CHELSIO_T5);
5812 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5816 rc = sysctl_wire_old_buffer(req, 0);
5820 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5824 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5827 rc = -t4_cim_read_la(sc, buf, NULL);
5831 sbuf_printf(sb, "Status Inst Data PC%s",
5832 cfg & F_UPDBGLACAPTPCONLY ? "" :
5833 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
5835 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
5836 if (cfg & F_UPDBGLACAPTPCONLY) {
5837 sbuf_printf(sb, "\n %02x %08x %08x %08x",
5838 p[3] & 0xff, p[2], p[1], p[0]);
5839 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
5840 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
5841 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
5842 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
5843 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
5844 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
5847 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
5848 "%08x %08x %08x %08x %08x %08x",
5849 (p[9] >> 16) & 0xff,
5850 p[9] & 0xffff, p[8] >> 16,
5851 p[8] & 0xffff, p[7] >> 16,
5852 p[7] & 0xffff, p[6] >> 16,
5853 p[2], p[1], p[0], p[5], p[4], p[3]);
5857 rc = sbuf_finish(sb);
5865 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5867 struct adapter *sc = arg1;
5873 rc = sysctl_wire_old_buffer(req, 0);
5877 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5881 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5884 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5887 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5888 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5892 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
5893 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5894 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
5895 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5896 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5897 (p[1] >> 2) | ((p[2] & 3) << 30),
5898 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5902 rc = sbuf_finish(sb);
5909 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5911 struct adapter *sc = arg1;
5917 rc = sysctl_wire_old_buffer(req, 0);
5921 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5925 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5928 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5931 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
5932 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5933 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
5934 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5935 p[4], p[3], p[2], p[1], p[0]);
5938 sbuf_printf(sb, "\n\nCntl ID Data");
5939 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5940 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
5941 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5944 rc = sbuf_finish(sb);
5951 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5953 struct adapter *sc = arg1;
5956 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5957 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5958 uint16_t thres[CIM_NUM_IBQ];
5959 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5960 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5961 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5963 cim_num_obq = sc->chip_params->cim_num_obq;
5965 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5966 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5968 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5969 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5971 nq = CIM_NUM_IBQ + cim_num_obq;
5973 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5975 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5979 t4_read_cimq_cfg(sc, base, size, thres);
5981 rc = sysctl_wire_old_buffer(req, 0);
5985 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5990 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
5992 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5993 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
5994 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5995 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5996 G_QUEREMFLITS(p[2]) * 16);
5997 for ( ; i < nq; i++, p += 4, wr += 2)
5998 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
5999 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
6000 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
6001 G_QUEREMFLITS(p[2]) * 16);
6003 rc = sbuf_finish(sb);
6010 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
6012 struct adapter *sc = arg1;
6015 struct tp_cpl_stats stats;
6017 rc = sysctl_wire_old_buffer(req, 0);
6021 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6025 mtx_lock(&sc->reg_lock);
6026 t4_tp_get_cpl_stats(sc, &stats);
6027 mtx_unlock(&sc->reg_lock);
6029 if (sc->chip_params->nchan > 2) {
6030 sbuf_printf(sb, " channel 0 channel 1"
6031 " channel 2 channel 3");
6032 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
6033 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
6034 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
6035 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
6037 sbuf_printf(sb, " channel 0 channel 1");
6038 sbuf_printf(sb, "\nCPL requests: %10u %10u",
6039 stats.req[0], stats.req[1]);
6040 sbuf_printf(sb, "\nCPL responses: %10u %10u",
6041 stats.rsp[0], stats.rsp[1]);
6044 rc = sbuf_finish(sb);
6051 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
6053 struct adapter *sc = arg1;
6056 struct tp_usm_stats stats;
6058 rc = sysctl_wire_old_buffer(req, 0);
6062 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6066 t4_get_usm_stats(sc, &stats);
6068 sbuf_printf(sb, "Frames: %u\n", stats.frames);
6069 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
6070 sbuf_printf(sb, "Drops: %u", stats.drops);
6072 rc = sbuf_finish(sb);
6078 static const char * const devlog_level_strings[] = {
6079 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
6080 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
6081 [FW_DEVLOG_LEVEL_ERR] = "ERR",
6082 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
6083 [FW_DEVLOG_LEVEL_INFO] = "INFO",
6084 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
6087 static const char * const devlog_facility_strings[] = {
6088 [FW_DEVLOG_FACILITY_CORE] = "CORE",
6089 [FW_DEVLOG_FACILITY_CF] = "CF",
6090 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
6091 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
6092 [FW_DEVLOG_FACILITY_RES] = "RES",
6093 [FW_DEVLOG_FACILITY_HW] = "HW",
6094 [FW_DEVLOG_FACILITY_FLR] = "FLR",
6095 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
6096 [FW_DEVLOG_FACILITY_PHY] = "PHY",
6097 [FW_DEVLOG_FACILITY_MAC] = "MAC",
6098 [FW_DEVLOG_FACILITY_PORT] = "PORT",
6099 [FW_DEVLOG_FACILITY_VI] = "VI",
6100 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
6101 [FW_DEVLOG_FACILITY_ACL] = "ACL",
6102 [FW_DEVLOG_FACILITY_TM] = "TM",
6103 [FW_DEVLOG_FACILITY_QFC] = "QFC",
6104 [FW_DEVLOG_FACILITY_DCB] = "DCB",
6105 [FW_DEVLOG_FACILITY_ETH] = "ETH",
6106 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
6107 [FW_DEVLOG_FACILITY_RI] = "RI",
6108 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
6109 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
6110 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
6111 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
6112 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
6116 sysctl_devlog(SYSCTL_HANDLER_ARGS)
6118 struct adapter *sc = arg1;
6119 struct devlog_params *dparams = &sc->params.devlog;
6120 struct fw_devlog_e *buf, *e;
6121 int i, j, rc, nentries, first = 0;
6123 uint64_t ftstamp = UINT64_MAX;
6125 if (dparams->addr == 0)
6128 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
6132 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
6136 nentries = dparams->size / sizeof(struct fw_devlog_e);
6137 for (i = 0; i < nentries; i++) {
6140 if (e->timestamp == 0)
6143 e->timestamp = be64toh(e->timestamp);
6144 e->seqno = be32toh(e->seqno);
6145 for (j = 0; j < 8; j++)
6146 e->params[j] = be32toh(e->params[j]);
6148 if (e->timestamp < ftstamp) {
6149 ftstamp = e->timestamp;
6154 if (buf[first].timestamp == 0)
6155 goto done; /* nothing in the log */
6157 rc = sysctl_wire_old_buffer(req, 0);
6161 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6166 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
6167 "Seq#", "Tstamp", "Level", "Facility", "Message");
6172 if (e->timestamp == 0)
6175 sbuf_printf(sb, "%10d %15ju %8s %8s ",
6176 e->seqno, e->timestamp,
6177 (e->level < nitems(devlog_level_strings) ?
6178 devlog_level_strings[e->level] : "UNKNOWN"),
6179 (e->facility < nitems(devlog_facility_strings) ?
6180 devlog_facility_strings[e->facility] : "UNKNOWN"));
6181 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
6182 e->params[2], e->params[3], e->params[4],
6183 e->params[5], e->params[6], e->params[7]);
6185 if (++i == nentries)
6187 } while (i != first);
6189 rc = sbuf_finish(sb);
6197 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
6199 struct adapter *sc = arg1;
6202 struct tp_fcoe_stats stats[MAX_NCHAN];
6203 int i, nchan = sc->chip_params->nchan;
6205 rc = sysctl_wire_old_buffer(req, 0);
6209 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6213 for (i = 0; i < nchan; i++)
6214 t4_get_fcoe_stats(sc, i, &stats[i]);
6217 sbuf_printf(sb, " channel 0 channel 1"
6218 " channel 2 channel 3");
6219 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
6220 stats[0].octets_ddp, stats[1].octets_ddp,
6221 stats[2].octets_ddp, stats[3].octets_ddp);
6222 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
6223 stats[0].frames_ddp, stats[1].frames_ddp,
6224 stats[2].frames_ddp, stats[3].frames_ddp);
6225 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
6226 stats[0].frames_drop, stats[1].frames_drop,
6227 stats[2].frames_drop, stats[3].frames_drop);
6229 sbuf_printf(sb, " channel 0 channel 1");
6230 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
6231 stats[0].octets_ddp, stats[1].octets_ddp);
6232 sbuf_printf(sb, "\nframesDDP: %16u %16u",
6233 stats[0].frames_ddp, stats[1].frames_ddp);
6234 sbuf_printf(sb, "\nframesDrop: %16u %16u",
6235 stats[0].frames_drop, stats[1].frames_drop);
6238 rc = sbuf_finish(sb);
6245 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6247 struct adapter *sc = arg1;
6250 unsigned int map, kbps, ipg, mode;
6251 unsigned int pace_tab[NTX_SCHED];
6253 rc = sysctl_wire_old_buffer(req, 0);
6257 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6261 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6262 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6263 t4_read_pace_tbl(sc, pace_tab);
6265 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6266 "Class IPG (0.1 ns) Flow IPG (us)");
6268 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6269 t4_get_tx_sched(sc, i, &kbps, &ipg);
6270 sbuf_printf(sb, "\n %u %-5s %u ", i,
6271 (mode & (1 << i)) ? "flow" : "class", map & 3);
6273 sbuf_printf(sb, "%9u ", kbps);
6275 sbuf_printf(sb, " disabled ");
6278 sbuf_printf(sb, "%13u ", ipg);
6280 sbuf_printf(sb, " disabled ");
6283 sbuf_printf(sb, "%10u", pace_tab[i]);
6285 sbuf_printf(sb, " disabled");
6288 rc = sbuf_finish(sb);
6295 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6297 struct adapter *sc = arg1;
6301 struct lb_port_stats s[2];
6302 static const char *stat_name[] = {
6303 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6304 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6305 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6306 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6307 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6308 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6309 "BG2FramesTrunc:", "BG3FramesTrunc:"
6312 rc = sysctl_wire_old_buffer(req, 0);
6316 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6320 memset(s, 0, sizeof(s));
6322 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6323 t4_get_lb_stats(sc, i, &s[0]);
6324 t4_get_lb_stats(sc, i + 1, &s[1]);
6328 sbuf_printf(sb, "%s Loopback %u"
6329 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6331 for (j = 0; j < nitems(stat_name); j++)
6332 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6336 rc = sbuf_finish(sb);
6343 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6346 struct port_info *pi = arg1;
6349 rc = sysctl_wire_old_buffer(req, 0);
6352 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6356 if (pi->linkdnrc < 0)
6357 sbuf_printf(sb, "n/a");
6359 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc));
6361 rc = sbuf_finish(sb);
6374 mem_desc_cmp(const void *a, const void *b)
6376 return ((const struct mem_desc *)a)->base -
6377 ((const struct mem_desc *)b)->base;
6381 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6389 size = to - from + 1;
6393 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6394 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6398 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6400 struct adapter *sc = arg1;
6403 uint32_t lo, hi, used, alloc;
6404 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6405 static const char *region[] = {
6406 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6407 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6408 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6409 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6410 "RQUDP region:", "PBL region:", "TXPBL region:",
6411 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6414 struct mem_desc avail[4];
6415 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6416 struct mem_desc *md = mem;
6418 rc = sysctl_wire_old_buffer(req, 0);
6422 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6426 for (i = 0; i < nitems(mem); i++) {
6431 /* Find and sort the populated memory ranges */
6433 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6434 if (lo & F_EDRAM0_ENABLE) {
6435 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6436 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6437 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6441 if (lo & F_EDRAM1_ENABLE) {
6442 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6443 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6444 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6448 if (lo & F_EXT_MEM_ENABLE) {
6449 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6450 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6451 avail[i].limit = avail[i].base +
6452 (G_EXT_MEM_SIZE(hi) << 20);
6453 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6456 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6457 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6458 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6459 avail[i].limit = avail[i].base +
6460 (G_EXT_MEM1_SIZE(hi) << 20);
6464 if (!i) /* no memory available */
6466 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6468 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6469 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6470 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6471 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6472 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6473 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6474 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6475 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6476 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6478 /* the next few have explicit upper bounds */
6479 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6480 md->limit = md->base - 1 +
6481 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6482 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6485 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6486 md->limit = md->base - 1 +
6487 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6488 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6491 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6492 if (chip_id(sc) <= CHELSIO_T5)
6493 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6495 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6499 md->idx = nitems(region); /* hide it */
6503 #define ulp_region(reg) \
6504 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6505 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6507 ulp_region(RX_ISCSI);
6508 ulp_region(RX_TDDP);
6510 ulp_region(RX_STAG);
6512 ulp_region(RX_RQUDP);
6518 md->idx = nitems(region);
6521 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6522 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6525 if (sge_ctrl & F_VFIFO_ENABLE)
6526 size = G_DBVFIFO_SIZE(fifo_size);
6528 size = G_T6_DBVFIFO_SIZE(fifo_size);
6531 md->base = G_BASEADDR(t4_read_reg(sc,
6532 A_SGE_DBVFIFO_BADDR));
6533 md->limit = md->base + (size << 2) - 1;
6538 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6541 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6545 md->base = sc->vres.ocq.start;
6546 if (sc->vres.ocq.size)
6547 md->limit = md->base + sc->vres.ocq.size - 1;
6549 md->idx = nitems(region); /* hide it */
6552 /* add any address-space holes, there can be up to 3 */
6553 for (n = 0; n < i - 1; n++)
6554 if (avail[n].limit < avail[n + 1].base)
6555 (md++)->base = avail[n].limit;
6557 (md++)->base = avail[n].limit;
6560 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6562 for (lo = 0; lo < i; lo++)
6563 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6564 avail[lo].limit - 1);
6566 sbuf_printf(sb, "\n");
6567 for (i = 0; i < n; i++) {
6568 if (mem[i].idx >= nitems(region))
6569 continue; /* skip holes */
6571 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6572 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6576 sbuf_printf(sb, "\n");
6577 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6578 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6579 mem_region_show(sb, "uP RAM:", lo, hi);
6581 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6582 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6583 mem_region_show(sb, "uP Extmem2:", lo, hi);
6585 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6586 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6588 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6589 (lo & F_PMRXNUMCHN) ? 2 : 1);
6591 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6592 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6593 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6595 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6596 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6597 sbuf_printf(sb, "%u p-structs\n",
6598 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6600 for (i = 0; i < 4; i++) {
6601 if (chip_id(sc) > CHELSIO_T5)
6602 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6604 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6606 used = G_T5_USED(lo);
6607 alloc = G_T5_ALLOC(lo);
6610 alloc = G_ALLOC(lo);
6612 /* For T6 these are MAC buffer groups */
6613 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6616 for (i = 0; i < sc->chip_params->nchan; i++) {
6617 if (chip_id(sc) > CHELSIO_T5)
6618 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6620 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6622 used = G_T5_USED(lo);
6623 alloc = G_T5_ALLOC(lo);
6626 alloc = G_ALLOC(lo);
6628 /* For T6 these are MAC buffer groups */
6630 "\nLoopback %d using %u pages out of %u allocated",
6634 rc = sbuf_finish(sb);
6641 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6645 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6649 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6651 struct adapter *sc = arg1;
6655 MPASS(chip_id(sc) <= CHELSIO_T5);
6657 rc = sysctl_wire_old_buffer(req, 0);
6661 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6666 "Idx Ethernet address Mask Vld Ports PF"
6667 " VF Replication P0 P1 P2 P3 ML");
6668 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6669 uint64_t tcamx, tcamy, mask;
6670 uint32_t cls_lo, cls_hi;
6671 uint8_t addr[ETHER_ADDR_LEN];
6673 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6674 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6677 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6678 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6679 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6680 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6681 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
6682 addr[3], addr[4], addr[5], (uintmax_t)mask,
6683 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6684 G_PORTMAP(cls_hi), G_PF(cls_lo),
6685 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6687 if (cls_lo & F_REPLICATE) {
6688 struct fw_ldst_cmd ldst_cmd;
6690 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6691 ldst_cmd.op_to_addrspace =
6692 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6693 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6694 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6695 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6696 ldst_cmd.u.mps.rplc.fid_idx =
6697 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6698 V_FW_LDST_CMD_IDX(i));
6700 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6704 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6705 sizeof(ldst_cmd), &ldst_cmd);
6706 end_synchronized_op(sc, 0);
6709 sbuf_printf(sb, "%36d", rc);
6712 sbuf_printf(sb, " %08x %08x %08x %08x",
6713 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6714 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6715 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6716 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6719 sbuf_printf(sb, "%36s", "");
6721 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6722 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6723 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6727 (void) sbuf_finish(sb);
6729 rc = sbuf_finish(sb);
6736 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
6738 struct adapter *sc = arg1;
6742 MPASS(chip_id(sc) > CHELSIO_T5);
6744 rc = sysctl_wire_old_buffer(req, 0);
6748 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6752 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
6753 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
6755 " P0 P1 P2 P3 ML\n");
6757 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6758 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
6760 uint64_t tcamx, tcamy, val, mask;
6761 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
6762 uint8_t addr[ETHER_ADDR_LEN];
6764 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
6766 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
6768 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
6769 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6770 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6771 tcamy = G_DMACH(val) << 32;
6772 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6773 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6774 lookup_type = G_DATALKPTYPE(data2);
6775 port_num = G_DATAPORTNUM(data2);
6776 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6777 /* Inner header VNI */
6778 vniy = ((data2 & F_DATAVIDH2) << 23) |
6779 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6780 dip_hit = data2 & F_DATADIPHIT;
6785 vlan_vld = data2 & F_DATAVIDH2;
6786 ivlan = G_VIDL(val);
6789 ctl |= V_CTLXYBITSEL(1);
6790 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6791 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6792 tcamx = G_DMACH(val) << 32;
6793 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6794 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6795 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6796 /* Inner header VNI mask */
6797 vnix = ((data2 & F_DATAVIDH2) << 23) |
6798 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6804 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6806 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6807 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6809 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6810 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6811 "%012jx %06x %06x - - %3c"
6812 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
6813 addr[1], addr[2], addr[3], addr[4], addr[5],
6814 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
6815 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6816 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6817 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6819 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6820 "%012jx - - ", i, addr[0], addr[1],
6821 addr[2], addr[3], addr[4], addr[5],
6825 sbuf_printf(sb, "%4u Y ", ivlan);
6827 sbuf_printf(sb, " - N ");
6829 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
6830 lookup_type ? 'I' : 'O', port_num,
6831 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6832 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6833 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6837 if (cls_lo & F_T6_REPLICATE) {
6838 struct fw_ldst_cmd ldst_cmd;
6840 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6841 ldst_cmd.op_to_addrspace =
6842 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6843 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6844 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6845 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6846 ldst_cmd.u.mps.rplc.fid_idx =
6847 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6848 V_FW_LDST_CMD_IDX(i));
6850 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6854 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6855 sizeof(ldst_cmd), &ldst_cmd);
6856 end_synchronized_op(sc, 0);
6859 sbuf_printf(sb, "%72d", rc);
6862 sbuf_printf(sb, " %08x %08x %08x %08x"
6863 " %08x %08x %08x %08x",
6864 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
6865 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
6866 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
6867 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
6868 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6869 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6870 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6871 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6874 sbuf_printf(sb, "%72s", "");
6876 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
6877 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
6878 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
6879 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
6883 (void) sbuf_finish(sb);
6885 rc = sbuf_finish(sb);
6892 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
6894 struct adapter *sc = arg1;
6897 uint16_t mtus[NMTUS];
6899 rc = sysctl_wire_old_buffer(req, 0);
6903 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6907 t4_read_mtu_tbl(sc, mtus, NULL);
6909 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
6910 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
6911 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
6912 mtus[14], mtus[15]);
6914 rc = sbuf_finish(sb);
6921 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
6923 struct adapter *sc = arg1;
6926 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
6927 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
6928 static const char *tx_stats[MAX_PM_NSTATS] = {
6929 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
6930 "Tx FIFO wait", NULL, "Tx latency"
6932 static const char *rx_stats[MAX_PM_NSTATS] = {
6933 "Read:", "Write bypass:", "Write mem:", "Flush:",
6934 "Rx FIFO wait", NULL, "Rx latency"
6937 rc = sysctl_wire_old_buffer(req, 0);
6941 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6945 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
6946 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
6948 sbuf_printf(sb, " Tx pcmds Tx bytes");
6949 for (i = 0; i < 4; i++) {
6950 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6954 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
6955 for (i = 0; i < 4; i++) {
6956 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6960 if (chip_id(sc) > CHELSIO_T5) {
6962 "\n Total wait Total occupancy");
6963 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6965 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6969 MPASS(i < nitems(tx_stats));
6972 "\n Reads Total wait");
6973 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6975 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6979 rc = sbuf_finish(sb);
6986 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
6988 struct adapter *sc = arg1;
6991 struct tp_rdma_stats stats;
6993 rc = sysctl_wire_old_buffer(req, 0);
6997 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7001 mtx_lock(&sc->reg_lock);
7002 t4_tp_get_rdma_stats(sc, &stats);
7003 mtx_unlock(&sc->reg_lock);
7005 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
7006 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
7008 rc = sbuf_finish(sb);
7015 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
7017 struct adapter *sc = arg1;
7020 struct tp_tcp_stats v4, v6;
7022 rc = sysctl_wire_old_buffer(req, 0);
7026 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7030 mtx_lock(&sc->reg_lock);
7031 t4_tp_get_tcp_stats(sc, &v4, &v6);
7032 mtx_unlock(&sc->reg_lock);
7036 sbuf_printf(sb, "OutRsts: %20u %20u\n",
7037 v4.tcp_out_rsts, v6.tcp_out_rsts);
7038 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
7039 v4.tcp_in_segs, v6.tcp_in_segs);
7040 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
7041 v4.tcp_out_segs, v6.tcp_out_segs);
7042 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
7043 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
7045 rc = sbuf_finish(sb);
7052 sysctl_tids(SYSCTL_HANDLER_ARGS)
7054 struct adapter *sc = arg1;
7057 struct tid_info *t = &sc->tids;
7059 rc = sysctl_wire_old_buffer(req, 0);
7063 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7068 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
7073 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7076 if (chip_id(sc) <= CHELSIO_T5)
7077 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
7079 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
7082 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
7083 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
7086 sbuf_printf(sb, "TID range: %u-%u",
7087 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
7091 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
7092 sbuf_printf(sb, ", in use: %u\n",
7093 atomic_load_acq_int(&t->tids_in_use));
7097 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
7098 t->stid_base + t->nstids - 1, t->stids_in_use);
7102 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
7103 t->ftid_base + t->nftids - 1);
7107 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
7108 t->etid_base + t->netids - 1);
7111 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
7112 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
7113 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
7115 rc = sbuf_finish(sb);
7122 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
7124 struct adapter *sc = arg1;
7127 struct tp_err_stats stats;
7129 rc = sysctl_wire_old_buffer(req, 0);
7133 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7137 mtx_lock(&sc->reg_lock);
7138 t4_tp_get_err_stats(sc, &stats);
7139 mtx_unlock(&sc->reg_lock);
7141 if (sc->chip_params->nchan > 2) {
7142 sbuf_printf(sb, " channel 0 channel 1"
7143 " channel 2 channel 3\n");
7144 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
7145 stats.mac_in_errs[0], stats.mac_in_errs[1],
7146 stats.mac_in_errs[2], stats.mac_in_errs[3]);
7147 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
7148 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
7149 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
7150 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
7151 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
7152 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
7153 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
7154 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
7155 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
7156 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
7157 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
7158 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
7159 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
7160 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
7161 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
7162 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
7163 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
7164 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
7165 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
7166 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
7167 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
7169 sbuf_printf(sb, " channel 0 channel 1\n");
7170 sbuf_printf(sb, "macInErrs: %10u %10u\n",
7171 stats.mac_in_errs[0], stats.mac_in_errs[1]);
7172 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
7173 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
7174 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
7175 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
7176 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
7177 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
7178 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
7179 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
7180 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
7181 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
7182 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
7183 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
7184 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
7185 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
7188 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
7189 stats.ofld_no_neigh, stats.ofld_cong_defer);
7191 rc = sbuf_finish(sb);
7198 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
7200 struct adapter *sc = arg1;
7201 struct tp_params *tpp = &sc->params.tp;
7205 mask = tpp->la_mask >> 16;
7206 rc = sysctl_handle_int(oidp, &mask, 0, req);
7207 if (rc != 0 || req->newptr == NULL)
7211 tpp->la_mask = mask << 16;
7212 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
7224 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
7230 uint64_t mask = (1ULL << f->width) - 1;
7231 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
7232 ((uintmax_t)v >> f->start) & mask);
7234 if (line_size + len >= 79) {
7236 sbuf_printf(sb, "\n ");
7238 sbuf_printf(sb, "%s ", buf);
7239 line_size += len + 1;
7242 sbuf_printf(sb, "\n");
7245 static const struct field_desc tp_la0[] = {
7246 { "RcfOpCodeOut", 60, 4 },
7248 { "WcfState", 52, 4 },
7249 { "RcfOpcSrcOut", 50, 2 },
7250 { "CRxError", 49, 1 },
7251 { "ERxError", 48, 1 },
7252 { "SanityFailed", 47, 1 },
7253 { "SpuriousMsg", 46, 1 },
7254 { "FlushInputMsg", 45, 1 },
7255 { "FlushInputCpl", 44, 1 },
7256 { "RssUpBit", 43, 1 },
7257 { "RssFilterHit", 42, 1 },
7259 { "InitTcb", 31, 1 },
7260 { "LineNumber", 24, 7 },
7262 { "EdataOut", 22, 1 },
7264 { "CdataOut", 20, 1 },
7265 { "EreadPdu", 19, 1 },
7266 { "CreadPdu", 18, 1 },
7267 { "TunnelPkt", 17, 1 },
7268 { "RcfPeerFin", 16, 1 },
7269 { "RcfReasonOut", 12, 4 },
7270 { "TxCchannel", 10, 2 },
7271 { "RcfTxChannel", 8, 2 },
7272 { "RxEchannel", 6, 2 },
7273 { "RcfRxChannel", 5, 1 },
7274 { "RcfDataOutSrdy", 4, 1 },
7276 { "RxOoDvld", 2, 1 },
7277 { "RxCongestion", 1, 1 },
7278 { "TxCongestion", 0, 1 },
7282 static const struct field_desc tp_la1[] = {
7283 { "CplCmdIn", 56, 8 },
7284 { "CplCmdOut", 48, 8 },
7285 { "ESynOut", 47, 1 },
7286 { "EAckOut", 46, 1 },
7287 { "EFinOut", 45, 1 },
7288 { "ERstOut", 44, 1 },
7293 { "DataIn", 39, 1 },
7294 { "DataInVld", 38, 1 },
7296 { "RxBufEmpty", 36, 1 },
7298 { "RxFbCongestion", 34, 1 },
7299 { "TxFbCongestion", 33, 1 },
7300 { "TxPktSumSrdy", 32, 1 },
7301 { "RcfUlpType", 28, 4 },
7303 { "Ebypass", 26, 1 },
7305 { "Static0", 24, 1 },
7307 { "Cbypass", 22, 1 },
7309 { "CPktOut", 20, 1 },
7310 { "RxPagePoolFull", 18, 2 },
7311 { "RxLpbkPkt", 17, 1 },
7312 { "TxLpbkPkt", 16, 1 },
7313 { "RxVfValid", 15, 1 },
7314 { "SynLearned", 14, 1 },
7315 { "SetDelEntry", 13, 1 },
7316 { "SetInvEntry", 12, 1 },
7317 { "CpcmdDvld", 11, 1 },
7318 { "CpcmdSave", 10, 1 },
7319 { "RxPstructsFull", 8, 2 },
7320 { "EpcmdDvld", 7, 1 },
7321 { "EpcmdFlush", 6, 1 },
7322 { "EpcmdTrimPrefix", 5, 1 },
7323 { "EpcmdTrimPostfix", 4, 1 },
7324 { "ERssIp4Pkt", 3, 1 },
7325 { "ERssIp6Pkt", 2, 1 },
7326 { "ERssTcpUdpPkt", 1, 1 },
7327 { "ERssFceFipPkt", 0, 1 },
7331 static const struct field_desc tp_la2[] = {
7332 { "CplCmdIn", 56, 8 },
7333 { "MpsVfVld", 55, 1 },
7340 { "DataIn", 39, 1 },
7341 { "DataInVld", 38, 1 },
7343 { "RxBufEmpty", 36, 1 },
7345 { "RxFbCongestion", 34, 1 },
7346 { "TxFbCongestion", 33, 1 },
7347 { "TxPktSumSrdy", 32, 1 },
7348 { "RcfUlpType", 28, 4 },
7350 { "Ebypass", 26, 1 },
7352 { "Static0", 24, 1 },
7354 { "Cbypass", 22, 1 },
7356 { "CPktOut", 20, 1 },
7357 { "RxPagePoolFull", 18, 2 },
7358 { "RxLpbkPkt", 17, 1 },
7359 { "TxLpbkPkt", 16, 1 },
7360 { "RxVfValid", 15, 1 },
7361 { "SynLearned", 14, 1 },
7362 { "SetDelEntry", 13, 1 },
7363 { "SetInvEntry", 12, 1 },
7364 { "CpcmdDvld", 11, 1 },
7365 { "CpcmdSave", 10, 1 },
7366 { "RxPstructsFull", 8, 2 },
7367 { "EpcmdDvld", 7, 1 },
7368 { "EpcmdFlush", 6, 1 },
7369 { "EpcmdTrimPrefix", 5, 1 },
7370 { "EpcmdTrimPostfix", 4, 1 },
7371 { "ERssIp4Pkt", 3, 1 },
7372 { "ERssIp6Pkt", 2, 1 },
7373 { "ERssTcpUdpPkt", 1, 1 },
7374 { "ERssFceFipPkt", 0, 1 },
7379 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7382 field_desc_show(sb, *p, tp_la0);
7386 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7390 sbuf_printf(sb, "\n");
7391 field_desc_show(sb, p[0], tp_la0);
7392 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7393 field_desc_show(sb, p[1], tp_la0);
7397 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7401 sbuf_printf(sb, "\n");
7402 field_desc_show(sb, p[0], tp_la0);
7403 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7404 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7408 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7410 struct adapter *sc = arg1;
7415 void (*show_func)(struct sbuf *, uint64_t *, int);
7417 rc = sysctl_wire_old_buffer(req, 0);
7421 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7425 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7427 t4_tp_read_la(sc, buf, NULL);
7430 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7433 show_func = tp_la_show2;
7437 show_func = tp_la_show3;
7441 show_func = tp_la_show;
7444 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7445 (*show_func)(sb, p, i);
7447 rc = sbuf_finish(sb);
7454 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7456 struct adapter *sc = arg1;
7459 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7461 rc = sysctl_wire_old_buffer(req, 0);
7465 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7469 t4_get_chan_txrate(sc, nrate, orate);
7471 if (sc->chip_params->nchan > 2) {
7472 sbuf_printf(sb, " channel 0 channel 1"
7473 " channel 2 channel 3\n");
7474 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7475 nrate[0], nrate[1], nrate[2], nrate[3]);
7476 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7477 orate[0], orate[1], orate[2], orate[3]);
7479 sbuf_printf(sb, " channel 0 channel 1\n");
7480 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7481 nrate[0], nrate[1]);
7482 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7483 orate[0], orate[1]);
7486 rc = sbuf_finish(sb);
7493 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7495 struct adapter *sc = arg1;
7500 rc = sysctl_wire_old_buffer(req, 0);
7504 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7508 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7511 t4_ulprx_read_la(sc, buf);
7514 sbuf_printf(sb, " Pcmd Type Message"
7516 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7517 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7518 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7521 rc = sbuf_finish(sb);
7528 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7530 struct adapter *sc = arg1;
7534 MPASS(chip_id(sc) >= CHELSIO_T5);
7536 rc = sysctl_wire_old_buffer(req, 0);
7540 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7544 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7545 if (G_STATSOURCE_T5(v) == 7) {
7548 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
7550 sbuf_printf(sb, "total %d, incomplete %d",
7551 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7552 t4_read_reg(sc, A_SGE_STAT_MATCH));
7553 } else if (mode == 1) {
7554 sbuf_printf(sb, "total %d, data overflow %d",
7555 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7556 t4_read_reg(sc, A_SGE_STAT_MATCH));
7558 sbuf_printf(sb, "unknown mode %d", mode);
7561 rc = sbuf_finish(sb);
7568 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
7570 struct adapter *sc = arg1;
7571 struct tx_sched_class *tc;
7572 struct t4_sched_class_params p;
7574 int i, rc, port_id, flags, mbps, gbps;
7576 rc = sysctl_wire_old_buffer(req, 0);
7580 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7584 port_id = arg2 >> 16;
7585 MPASS(port_id < sc->params.nports);
7586 MPASS(sc->port[port_id] != NULL);
7588 MPASS(i < sc->chip_params->nsched_cls);
7589 tc = &sc->port[port_id]->tc[i];
7591 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7597 end_synchronized_op(sc, LOCK_HELD);
7599 if ((flags & TX_SC_OK) == 0) {
7600 sbuf_printf(sb, "none");
7604 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) {
7605 sbuf_printf(sb, "cl-wrr weight %u", p.weight);
7607 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL)
7608 sbuf_printf(sb, "cl-rl");
7609 else if (p.level == SCHED_CLASS_LEVEL_CH_RL)
7610 sbuf_printf(sb, "ch-rl");
7616 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) {
7617 /* XXX: top speed or actual link speed? */
7618 gbps = port_top_speed(sc->port[port_id]);
7619 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps);
7621 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) {
7622 switch (p.rateunit) {
7623 case SCHED_CLASS_RATEUNIT_BITS:
7624 mbps = p.maxrate / 1000;
7625 gbps = p.maxrate / 1000000;
7626 if (p.maxrate == gbps * 1000000)
7627 sbuf_printf(sb, " %uGbps", gbps);
7628 else if (p.maxrate == mbps * 1000)
7629 sbuf_printf(sb, " %uMbps", mbps);
7631 sbuf_printf(sb, " %uKbps", p.maxrate);
7633 case SCHED_CLASS_RATEUNIT_PKTS:
7634 sbuf_printf(sb, " %upps", p.maxrate);
7643 case SCHED_CLASS_MODE_CLASS:
7644 sbuf_printf(sb, " aggregate");
7646 case SCHED_CLASS_MODE_FLOW:
7647 sbuf_printf(sb, " per-flow");
7656 rc = sbuf_finish(sb);
7665 unit_conv(char *buf, size_t len, u_int val, u_int factor)
7667 u_int rem = val % factor;
7670 snprintf(buf, len, "%u", val / factor);
7672 while (rem % 10 == 0)
7674 snprintf(buf, len, "%u.%u", val / factor, rem);
7679 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
7681 struct adapter *sc = arg1;
7684 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7686 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7690 re = G_TIMERRESOLUTION(res);
7693 /* TCP timestamp tick */
7694 re = G_TIMESTAMPRESOLUTION(res);
7698 re = G_DELAYEDACKRESOLUTION(res);
7704 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
7706 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
7710 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
7712 struct adapter *sc = arg1;
7713 u_int res, dack_re, v;
7714 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7716 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7717 dack_re = G_DELAYEDACKRESOLUTION(res);
7718 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
7720 return (sysctl_handle_int(oidp, &v, 0, req));
7724 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
7726 struct adapter *sc = arg1;
7729 u_long tp_tick_us, v;
7730 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7732 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
7733 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
7734 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT ||
7735 reg == A_TP_FINWAIT2_TIMER);
7737 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
7738 tp_tick_us = (cclk_ps << tre) / 1000000;
7740 if (reg == A_TP_INIT_SRTT)
7741 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
7743 v = tp_tick_us * t4_read_reg(sc, reg);
7745 return (sysctl_handle_long(oidp, &v, 0, req));
7750 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
7754 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
7755 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
7757 if (fconf & F_FRAGMENTATION)
7758 mode |= T4_FILTER_IP_FRAGMENT;
7760 if (fconf & F_MPSHITTYPE)
7761 mode |= T4_FILTER_MPS_HIT_TYPE;
7763 if (fconf & F_MACMATCH)
7764 mode |= T4_FILTER_MAC_IDX;
7766 if (fconf & F_ETHERTYPE)
7767 mode |= T4_FILTER_ETH_TYPE;
7769 if (fconf & F_PROTOCOL)
7770 mode |= T4_FILTER_IP_PROTO;
7773 mode |= T4_FILTER_IP_TOS;
7776 mode |= T4_FILTER_VLAN;
7778 if (fconf & F_VNIC_ID) {
7779 mode |= T4_FILTER_VNIC;
7781 mode |= T4_FILTER_IC_VNIC;
7785 mode |= T4_FILTER_PORT;
7788 mode |= T4_FILTER_FCoE;
7794 mode_to_fconf(uint32_t mode)
7798 if (mode & T4_FILTER_IP_FRAGMENT)
7799 fconf |= F_FRAGMENTATION;
7801 if (mode & T4_FILTER_MPS_HIT_TYPE)
7802 fconf |= F_MPSHITTYPE;
7804 if (mode & T4_FILTER_MAC_IDX)
7805 fconf |= F_MACMATCH;
7807 if (mode & T4_FILTER_ETH_TYPE)
7808 fconf |= F_ETHERTYPE;
7810 if (mode & T4_FILTER_IP_PROTO)
7811 fconf |= F_PROTOCOL;
7813 if (mode & T4_FILTER_IP_TOS)
7816 if (mode & T4_FILTER_VLAN)
7819 if (mode & T4_FILTER_VNIC)
7822 if (mode & T4_FILTER_PORT)
7825 if (mode & T4_FILTER_FCoE)
7832 mode_to_iconf(uint32_t mode)
7835 if (mode & T4_FILTER_IC_VNIC)
7840 static int check_fspec_against_fconf_iconf(struct adapter *sc,
7841 struct t4_filter_specification *fs)
7843 struct tp_params *tpp = &sc->params.tp;
7846 if (fs->val.frag || fs->mask.frag)
7847 fconf |= F_FRAGMENTATION;
7849 if (fs->val.matchtype || fs->mask.matchtype)
7850 fconf |= F_MPSHITTYPE;
7852 if (fs->val.macidx || fs->mask.macidx)
7853 fconf |= F_MACMATCH;
7855 if (fs->val.ethtype || fs->mask.ethtype)
7856 fconf |= F_ETHERTYPE;
7858 if (fs->val.proto || fs->mask.proto)
7859 fconf |= F_PROTOCOL;
7861 if (fs->val.tos || fs->mask.tos)
7864 if (fs->val.vlan_vld || fs->mask.vlan_vld)
7867 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
7869 if (tpp->ingress_config & F_VNIC)
7873 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
7875 if ((tpp->ingress_config & F_VNIC) == 0)
7879 if (fs->val.iport || fs->mask.iport)
7882 if (fs->val.fcoe || fs->mask.fcoe)
7885 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
7892 get_filter_mode(struct adapter *sc, uint32_t *mode)
7894 struct tp_params *tpp = &sc->params.tp;
7897 * We trust the cached values of the relevant TP registers. This means
7898 * things work reliably only if writes to those registers are always via
7899 * t4_set_filter_mode.
7901 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
7907 set_filter_mode(struct adapter *sc, uint32_t mode)
7909 struct tp_params *tpp = &sc->params.tp;
7910 uint32_t fconf, iconf;
7913 iconf = mode_to_iconf(mode);
7914 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
7916 * For now we just complain if A_TP_INGRESS_CONFIG is not
7917 * already set to the correct value for the requested filter
7918 * mode. It's not clear if it's safe to write to this register
7919 * on the fly. (And we trust the cached value of the register).
7924 fconf = mode_to_fconf(mode);
7926 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7931 if (sc->tids.ftids_in_use > 0) {
7937 if (uld_active(sc, ULD_TOM)) {
7943 rc = -t4_set_filter_mode(sc, fconf);
7945 end_synchronized_op(sc, LOCK_HELD);
7949 static inline uint64_t
7950 get_filter_hits(struct adapter *sc, uint32_t fid)
7954 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
7955 (fid + sc->tids.ftid_base) * TCB_SIZE;
7960 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
7961 return (be64toh(hits));
7965 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
7966 return (be32toh(hits));
7971 get_filter(struct adapter *sc, struct t4_filter *t)
7973 int i, rc, nfilters = sc->tids.nftids;
7974 struct filter_entry *f;
7976 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7981 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
7982 t->idx >= nfilters) {
7983 t->idx = 0xffffffff;
7987 f = &sc->tids.ftid_tab[t->idx];
7988 for (i = t->idx; i < nfilters; i++, f++) {
7991 t->l2tidx = f->l2t ? f->l2t->idx : 0;
7992 t->smtidx = f->smtidx;
7994 t->hits = get_filter_hits(sc, t->idx);
7996 t->hits = UINT64_MAX;
8003 t->idx = 0xffffffff;
8005 end_synchronized_op(sc, LOCK_HELD);
8010 set_filter(struct adapter *sc, struct t4_filter *t)
8012 unsigned int nfilters, nports;
8013 struct filter_entry *f;
8016 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
8020 nfilters = sc->tids.nftids;
8021 nports = sc->params.nports;
8023 if (nfilters == 0) {
8028 if (t->idx >= nfilters) {
8033 /* Validate against the global filter mode and ingress config */
8034 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
8038 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
8043 if (t->fs.val.iport >= nports) {
8048 /* Can't specify an iq if not steering to it */
8049 if (!t->fs.dirsteer && t->fs.iq) {
8054 /* IPv6 filter idx must be 4 aligned */
8055 if (t->fs.type == 1 &&
8056 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
8061 if (!(sc->flags & FULL_INIT_DONE) &&
8062 ((rc = adapter_full_init(sc)) != 0))
8065 if (sc->tids.ftid_tab == NULL) {
8066 KASSERT(sc->tids.ftids_in_use == 0,
8067 ("%s: no memory allocated but filters_in_use > 0",
8070 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
8071 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
8072 if (sc->tids.ftid_tab == NULL) {
8076 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
8079 for (i = 0; i < 4; i++) {
8080 f = &sc->tids.ftid_tab[t->idx + i];
8082 if (f->pending || f->valid) {
8091 if (t->fs.type == 0)
8095 f = &sc->tids.ftid_tab[t->idx];
8098 rc = set_filter_wr(sc, t->idx);
8100 end_synchronized_op(sc, 0);
8103 mtx_lock(&sc->tids.ftid_lock);
8105 if (f->pending == 0) {
8106 rc = f->valid ? 0 : EIO;
8110 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8111 PCATCH, "t4setfw", 0)) {
8116 mtx_unlock(&sc->tids.ftid_lock);
8122 del_filter(struct adapter *sc, struct t4_filter *t)
8124 unsigned int nfilters;
8125 struct filter_entry *f;
8128 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
8132 nfilters = sc->tids.nftids;
8134 if (nfilters == 0) {
8139 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
8140 t->idx >= nfilters) {
8145 if (!(sc->flags & FULL_INIT_DONE)) {
8150 f = &sc->tids.ftid_tab[t->idx];
8162 t->fs = f->fs; /* extra info for the caller */
8163 rc = del_filter_wr(sc, t->idx);
8167 end_synchronized_op(sc, 0);
8170 mtx_lock(&sc->tids.ftid_lock);
8172 if (f->pending == 0) {
8173 rc = f->valid ? EIO : 0;
8177 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8178 PCATCH, "t4delfw", 0)) {
8183 mtx_unlock(&sc->tids.ftid_lock);
8190 clear_filter(struct filter_entry *f)
8193 t4_l2t_release(f->l2t);
8195 bzero(f, sizeof (*f));
8199 set_filter_wr(struct adapter *sc, int fidx)
8201 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8202 struct fw_filter_wr *fwr;
8203 unsigned int ftid, vnic_vld, vnic_vld_mask;
8204 struct wrq_cookie cookie;
8206 ASSERT_SYNCHRONIZED_OP(sc);
8208 if (f->fs.newdmac || f->fs.newvlan) {
8209 /* This filter needs an L2T entry; allocate one. */
8210 f->l2t = t4_l2t_alloc_switching(sc->l2t);
8213 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
8215 t4_l2t_release(f->l2t);
8221 /* Already validated against fconf, iconf */
8222 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
8223 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
8224 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
8228 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
8233 ftid = sc->tids.ftid_base + fidx;
8235 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8238 bzero(fwr, sizeof(*fwr));
8240 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
8241 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
8243 htobe32(V_FW_FILTER_WR_TID(ftid) |
8244 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
8245 V_FW_FILTER_WR_NOREPLY(0) |
8246 V_FW_FILTER_WR_IQ(f->fs.iq));
8247 fwr->del_filter_to_l2tix =
8248 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
8249 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
8250 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
8251 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
8252 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8253 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8254 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8255 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8256 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8257 f->fs.newvlan == VLAN_REWRITE) |
8258 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8259 f->fs.newvlan == VLAN_REWRITE) |
8260 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8261 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8262 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8263 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8264 fwr->ethtype = htobe16(f->fs.val.ethtype);
8265 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8266 fwr->frag_to_ovlan_vldm =
8267 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8268 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8269 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8270 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8271 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8272 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8274 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8275 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8276 fwr->maci_to_matchtypem =
8277 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8278 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8279 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8280 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8281 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8282 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8283 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8284 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8285 fwr->ptcl = f->fs.val.proto;
8286 fwr->ptclm = f->fs.mask.proto;
8287 fwr->ttyp = f->fs.val.tos;
8288 fwr->ttypm = f->fs.mask.tos;
8289 fwr->ivlan = htobe16(f->fs.val.vlan);
8290 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8291 fwr->ovlan = htobe16(f->fs.val.vnic);
8292 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8293 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8294 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8295 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8296 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8297 fwr->lp = htobe16(f->fs.val.dport);
8298 fwr->lpm = htobe16(f->fs.mask.dport);
8299 fwr->fp = htobe16(f->fs.val.sport);
8300 fwr->fpm = htobe16(f->fs.mask.sport);
8302 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8305 sc->tids.ftids_in_use++;
8307 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8312 del_filter_wr(struct adapter *sc, int fidx)
8314 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8315 struct fw_filter_wr *fwr;
8317 struct wrq_cookie cookie;
8319 ftid = sc->tids.ftid_base + fidx;
8321 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8324 bzero(fwr, sizeof (*fwr));
8326 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
8329 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8334 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8336 struct adapter *sc = iq->adapter;
8337 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
8338 unsigned int idx = GET_TID(rpl);
8340 struct filter_entry *f;
8342 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
8344 MPASS(iq == &sc->sge.fwq);
8345 MPASS(is_ftid(sc, idx));
8347 idx -= sc->tids.ftid_base;
8348 f = &sc->tids.ftid_tab[idx];
8349 rc = G_COOKIE(rpl->cookie);
8351 mtx_lock(&sc->tids.ftid_lock);
8352 if (rc == FW_FILTER_WR_FLT_ADDED) {
8353 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
8355 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
8356 f->pending = 0; /* asynchronous setup completed */
8359 if (rc != FW_FILTER_WR_FLT_DELETED) {
8360 /* Add or delete failed, display an error */
8362 "filter %u setup failed with error %u\n",
8367 sc->tids.ftids_in_use--;
8369 wakeup(&sc->tids.ftid_tab);
8370 mtx_unlock(&sc->tids.ftid_lock);
8376 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8379 MPASS(iq->set_tcb_rpl != NULL);
8380 return (iq->set_tcb_rpl(iq, rss, m));
8384 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8387 MPASS(iq->l2t_write_rpl != NULL);
8388 return (iq->l2t_write_rpl(iq, rss, m));
8392 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8396 if (cntxt->cid > M_CTXTQID)
8399 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8400 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8403 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8407 if (sc->flags & FW_OK) {
8408 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8415 * Read via firmware failed or wasn't even attempted. Read directly via
8418 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8420 end_synchronized_op(sc, 0);
8425 load_fw(struct adapter *sc, struct t4_data *fw)
8430 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8434 if (sc->flags & FULL_INIT_DONE) {
8439 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8440 if (fw_data == NULL) {
8445 rc = copyin(fw->data, fw_data, fw->len);
8447 rc = -t4_load_fw(sc, fw_data, fw->len);
8449 free(fw_data, M_CXGBE);
8451 end_synchronized_op(sc, 0);
8455 #define MAX_READ_BUF_SIZE (128 * 1024)
8457 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
8459 uint32_t addr, remaining, n;
8464 rc = validate_mem_range(sc, mr->addr, mr->len);
8468 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
8470 remaining = mr->len;
8471 dst = (void *)mr->data;
8474 n = min(remaining, MAX_READ_BUF_SIZE);
8475 read_via_memwin(sc, 2, addr, buf, n);
8477 rc = copyout(buf, dst, n);
8489 #undef MAX_READ_BUF_SIZE
8492 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8496 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8499 if (i2cd->len > sizeof(i2cd->data))
8502 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8505 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8506 i2cd->offset, i2cd->len, &i2cd->data[0]);
8507 end_synchronized_op(sc, 0);
8513 in_range(int val, int lo, int hi)
8516 return (val < 0 || (val <= hi && val >= lo));
8520 set_sched_class_config(struct adapter *sc, int minmax)
8527 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc");
8530 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1);
8531 end_synchronized_op(sc, 0);
8537 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p,
8540 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode;
8541 struct port_info *pi;
8542 struct tx_sched_class *tc;
8544 if (p->level == SCHED_CLASS_LEVEL_CL_RL)
8545 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
8546 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8547 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
8548 else if (p->level == SCHED_CLASS_LEVEL_CH_RL)
8549 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
8553 if (p->mode == SCHED_CLASS_MODE_CLASS)
8554 fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
8555 else if (p->mode == SCHED_CLASS_MODE_FLOW)
8556 fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
8560 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS)
8561 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
8562 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS)
8563 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
8567 if (p->ratemode == SCHED_CLASS_RATEMODE_REL)
8568 fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
8569 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS)
8570 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
8574 /* Vet our parameters ... */
8575 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1))
8578 pi = sc->port[sc->chan_map[p->channel]];
8581 MPASS(pi->tx_chan == p->channel);
8582 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */
8584 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) ||
8585 !in_range(p->minrate, 0, top_speed) ||
8586 !in_range(p->maxrate, 0, top_speed) ||
8587 !in_range(p->weight, 0, 100))
8591 * Translate any unset parameters into the firmware's
8592 * nomenclature and/or fail the call if the parameters
8595 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0)
8600 if (p->maxrate < 0) {
8601 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8602 p->level == SCHED_CLASS_LEVEL_CH_RL)
8607 if (p->weight < 0) {
8608 if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8613 if (p->pktsize < 0) {
8614 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8615 p->level == SCHED_CLASS_LEVEL_CH_RL)
8621 rc = begin_synchronized_op(sc, NULL,
8622 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp");
8625 tc = &pi->tc[p->cl];
8627 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode,
8628 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate,
8629 p->weight, p->pktsize, sleep_ok);
8631 tc->flags |= TX_SC_OK;
8634 * Unknown state at this point, see tc->params for what was
8637 tc->flags &= ~TX_SC_OK;
8639 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD);
8645 t4_set_sched_class(struct adapter *sc, struct t4_sched_params *p)
8648 if (p->type != SCHED_CLASS_TYPE_PACKET)
8651 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
8652 return (set_sched_class_config(sc, p->u.config.minmax));
8654 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
8655 return (set_sched_class_params(sc, &p->u.params, 1));
8661 t4_set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
8663 struct port_info *pi = NULL;
8665 struct sge_txq *txq;
8666 uint32_t fw_mnem, fw_queue, fw_class;
8669 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
8673 if (p->port >= sc->params.nports) {
8678 /* XXX: Only supported for the main VI. */
8679 pi = sc->port[p->port];
8681 if (!(vi->flags & VI_INIT_DONE)) {
8682 /* tx queues not set up yet */
8687 if (!in_range(p->queue, 0, vi->ntxq - 1) ||
8688 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) {
8694 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
8695 * Scheduling Class in this case).
8697 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
8698 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
8699 fw_class = p->cl < 0 ? 0xffffffff : p->cl;
8702 * If op.queue is non-negative, then we're only changing the scheduling
8703 * on a single specified TX queue.
8705 if (p->queue >= 0) {
8706 txq = &sc->sge.txq[vi->first_txq + p->queue];
8707 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8708 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8714 * Change the scheduling on all the TX queues for the
8717 for_each_txq(vi, i, txq) {
8718 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8719 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8727 end_synchronized_op(sc, 0);
8732 t4_os_find_pci_capability(struct adapter *sc, int cap)
8736 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8740 t4_os_pci_save_state(struct adapter *sc)
8743 struct pci_devinfo *dinfo;
8746 dinfo = device_get_ivars(dev);
8748 pci_cfg_save(dev, dinfo, 0);
8753 t4_os_pci_restore_state(struct adapter *sc)
8756 struct pci_devinfo *dinfo;
8759 dinfo = device_get_ivars(dev);
8761 pci_cfg_restore(dev, dinfo);
8766 t4_os_portmod_changed(const struct adapter *sc, int idx)
8768 struct port_info *pi = sc->port[idx];
8772 static const char *mod_str[] = {
8773 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8776 for_each_vi(pi, v, vi) {
8777 build_medialist(pi, &vi->media);
8780 ifp = pi->vi[0].ifp;
8781 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8782 if_printf(ifp, "transceiver unplugged.\n");
8783 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8784 if_printf(ifp, "unknown transceiver inserted.\n");
8785 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8786 if_printf(ifp, "unsupported transceiver inserted.\n");
8787 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8788 if_printf(ifp, "%s transceiver inserted.\n",
8789 mod_str[pi->mod_type]);
8791 if_printf(ifp, "transceiver (type %d) inserted.\n",
8797 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
8799 struct port_info *pi = sc->port[idx];
8808 pi->linkdnrc = reason;
8810 for_each_vi(pi, v, vi) {
8816 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
8817 if_link_state_change(ifp, LINK_STATE_UP);
8819 if_link_state_change(ifp, LINK_STATE_DOWN);
8825 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8829 sx_slock(&t4_list_lock);
8830 SLIST_FOREACH(sc, &t4_list, link) {
8832 * func should not make any assumptions about what state sc is
8833 * in - the only guarantee is that sc->sc_lock is a valid lock.
8837 sx_sunlock(&t4_list_lock);
8841 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
8845 struct adapter *sc = dev->si_drv1;
8847 rc = priv_check(td, PRIV_DRIVER);
8852 case CHELSIO_T4_GETREG: {
8853 struct t4_reg *edata = (struct t4_reg *)data;
8855 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8858 if (edata->size == 4)
8859 edata->val = t4_read_reg(sc, edata->addr);
8860 else if (edata->size == 8)
8861 edata->val = t4_read_reg64(sc, edata->addr);
8867 case CHELSIO_T4_SETREG: {
8868 struct t4_reg *edata = (struct t4_reg *)data;
8870 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8873 if (edata->size == 4) {
8874 if (edata->val & 0xffffffff00000000)
8876 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
8877 } else if (edata->size == 8)
8878 t4_write_reg64(sc, edata->addr, edata->val);
8883 case CHELSIO_T4_REGDUMP: {
8884 struct t4_regdump *regs = (struct t4_regdump *)data;
8885 int reglen = t4_get_regs_len(sc);
8888 if (regs->len < reglen) {
8889 regs->len = reglen; /* hint to the caller */
8894 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
8895 get_regs(sc, regs, buf);
8896 rc = copyout(buf, regs->data, reglen);
8900 case CHELSIO_T4_GET_FILTER_MODE:
8901 rc = get_filter_mode(sc, (uint32_t *)data);
8903 case CHELSIO_T4_SET_FILTER_MODE:
8904 rc = set_filter_mode(sc, *(uint32_t *)data);
8906 case CHELSIO_T4_GET_FILTER:
8907 rc = get_filter(sc, (struct t4_filter *)data);
8909 case CHELSIO_T4_SET_FILTER:
8910 rc = set_filter(sc, (struct t4_filter *)data);
8912 case CHELSIO_T4_DEL_FILTER:
8913 rc = del_filter(sc, (struct t4_filter *)data);
8915 case CHELSIO_T4_GET_SGE_CONTEXT:
8916 rc = get_sge_context(sc, (struct t4_sge_context *)data);
8918 case CHELSIO_T4_LOAD_FW:
8919 rc = load_fw(sc, (struct t4_data *)data);
8921 case CHELSIO_T4_GET_MEM:
8922 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
8924 case CHELSIO_T4_GET_I2C:
8925 rc = read_i2c(sc, (struct t4_i2c_data *)data);
8927 case CHELSIO_T4_CLEAR_STATS: {
8929 u_int port_id = *(uint32_t *)data;
8930 struct port_info *pi;
8933 if (port_id >= sc->params.nports)
8935 pi = sc->port[port_id];
8940 t4_clr_port_stats(sc, pi->tx_chan);
8941 pi->tx_parse_error = 0;
8942 mtx_lock(&sc->reg_lock);
8943 for_each_vi(pi, v, vi) {
8944 if (vi->flags & VI_INIT_DONE)
8945 t4_clr_vi_stats(sc, vi->viid);
8947 mtx_unlock(&sc->reg_lock);
8950 * Since this command accepts a port, clear stats for
8951 * all VIs on this port.
8953 for_each_vi(pi, v, vi) {
8954 if (vi->flags & VI_INIT_DONE) {
8955 struct sge_rxq *rxq;
8956 struct sge_txq *txq;
8957 struct sge_wrq *wrq;
8959 for_each_rxq(vi, i, rxq) {
8960 #if defined(INET) || defined(INET6)
8961 rxq->lro.lro_queued = 0;
8962 rxq->lro.lro_flushed = 0;
8965 rxq->vlan_extraction = 0;
8968 for_each_txq(vi, i, txq) {
8971 txq->vlan_insertion = 0;
8975 txq->txpkts0_wrs = 0;
8976 txq->txpkts1_wrs = 0;
8977 txq->txpkts0_pkts = 0;
8978 txq->txpkts1_pkts = 0;
8979 mp_ring_reset_stats(txq->r);
8983 /* nothing to clear for each ofld_rxq */
8985 for_each_ofld_txq(vi, i, wrq) {
8986 wrq->tx_wrs_direct = 0;
8987 wrq->tx_wrs_copied = 0;
8991 if (IS_MAIN_VI(vi)) {
8992 wrq = &sc->sge.ctrlq[pi->port_id];
8993 wrq->tx_wrs_direct = 0;
8994 wrq->tx_wrs_copied = 0;
9000 case CHELSIO_T4_SCHED_CLASS:
9001 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
9003 case CHELSIO_T4_SCHED_QUEUE:
9004 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
9006 case CHELSIO_T4_GET_TRACER:
9007 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
9009 case CHELSIO_T4_SET_TRACER:
9010 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
9020 t4_db_full(struct adapter *sc)
9023 CXGBE_UNIMPLEMENTED(__func__);
9027 t4_db_dropped(struct adapter *sc)
9030 CXGBE_UNIMPLEMENTED(__func__);
9035 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
9038 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
9039 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
9040 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
9041 V_HPZ3(pgsz_order[3]));
9045 toe_capability(struct vi_info *vi, int enable)
9048 struct port_info *pi = vi->pi;
9049 struct adapter *sc = pi->adapter;
9051 ASSERT_SYNCHRONIZED_OP(sc);
9053 if (!is_offload(sc))
9057 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
9058 /* TOE is already enabled. */
9063 * We need the port's queues around so that we're able to send
9064 * and receive CPLs to/from the TOE even if the ifnet for this
9065 * port has never been UP'd administratively.
9067 if (!(vi->flags & VI_INIT_DONE)) {
9068 rc = vi_full_init(vi);
9072 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
9073 rc = vi_full_init(&pi->vi[0]);
9078 if (isset(&sc->offload_map, pi->port_id)) {
9079 /* TOE is enabled on another VI of this port. */
9084 if (!uld_active(sc, ULD_TOM)) {
9085 rc = t4_activate_uld(sc, ULD_TOM);
9088 "You must kldload t4_tom.ko before trying "
9089 "to enable TOE on a cxgbe interface.\n");
9093 KASSERT(sc->tom_softc != NULL,
9094 ("%s: TOM activated but softc NULL", __func__));
9095 KASSERT(uld_active(sc, ULD_TOM),
9096 ("%s: TOM activated but flag not set", __func__));
9099 /* Activate iWARP and iSCSI too, if the modules are loaded. */
9100 if (!uld_active(sc, ULD_IWARP))
9101 (void) t4_activate_uld(sc, ULD_IWARP);
9102 if (!uld_active(sc, ULD_ISCSI))
9103 (void) t4_activate_uld(sc, ULD_ISCSI);
9106 setbit(&sc->offload_map, pi->port_id);
9110 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
9113 KASSERT(uld_active(sc, ULD_TOM),
9114 ("%s: TOM never initialized?", __func__));
9115 clrbit(&sc->offload_map, pi->port_id);
9122 * Add an upper layer driver to the global list.
9125 t4_register_uld(struct uld_info *ui)
9130 sx_xlock(&t4_uld_list_lock);
9131 SLIST_FOREACH(u, &t4_uld_list, link) {
9132 if (u->uld_id == ui->uld_id) {
9138 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
9141 sx_xunlock(&t4_uld_list_lock);
9146 t4_unregister_uld(struct uld_info *ui)
9151 sx_xlock(&t4_uld_list_lock);
9153 SLIST_FOREACH(u, &t4_uld_list, link) {
9155 if (ui->refcount > 0) {
9160 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
9166 sx_xunlock(&t4_uld_list_lock);
9171 t4_activate_uld(struct adapter *sc, int id)
9174 struct uld_info *ui;
9176 ASSERT_SYNCHRONIZED_OP(sc);
9178 if (id < 0 || id > ULD_MAX)
9180 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
9182 sx_slock(&t4_uld_list_lock);
9184 SLIST_FOREACH(ui, &t4_uld_list, link) {
9185 if (ui->uld_id == id) {
9186 if (!(sc->flags & FULL_INIT_DONE)) {
9187 rc = adapter_full_init(sc);
9192 rc = ui->activate(sc);
9194 setbit(&sc->active_ulds, id);
9201 sx_sunlock(&t4_uld_list_lock);
9207 t4_deactivate_uld(struct adapter *sc, int id)
9210 struct uld_info *ui;
9212 ASSERT_SYNCHRONIZED_OP(sc);
9214 if (id < 0 || id > ULD_MAX)
9218 sx_slock(&t4_uld_list_lock);
9220 SLIST_FOREACH(ui, &t4_uld_list, link) {
9221 if (ui->uld_id == id) {
9222 rc = ui->deactivate(sc);
9224 clrbit(&sc->active_ulds, id);
9231 sx_sunlock(&t4_uld_list_lock);
9237 uld_active(struct adapter *sc, int uld_id)
9240 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9242 return (isset(&sc->active_ulds, uld_id));
9247 * Come up with reasonable defaults for some of the tunables, provided they're
9248 * not set by the user (in which case we'll use the values as is).
9251 tweak_tunables(void)
9253 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9255 if (t4_ntxq10g < 1) {
9257 t4_ntxq10g = rss_getnumbuckets();
9259 t4_ntxq10g = min(nc, NTXQ_10G);
9263 if (t4_ntxq1g < 1) {
9265 /* XXX: way too many for 1GbE? */
9266 t4_ntxq1g = rss_getnumbuckets();
9268 t4_ntxq1g = min(nc, NTXQ_1G);
9273 t4_ntxq_vi = min(nc, NTXQ_VI);
9275 if (t4_nrxq10g < 1) {
9277 t4_nrxq10g = rss_getnumbuckets();
9279 t4_nrxq10g = min(nc, NRXQ_10G);
9283 if (t4_nrxq1g < 1) {
9285 /* XXX: way too many for 1GbE? */
9286 t4_nrxq1g = rss_getnumbuckets();
9288 t4_nrxq1g = min(nc, NRXQ_1G);
9293 t4_nrxq_vi = min(nc, NRXQ_VI);
9296 if (t4_nofldtxq10g < 1)
9297 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
9299 if (t4_nofldtxq1g < 1)
9300 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
9302 if (t4_nofldtxq_vi < 1)
9303 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI);
9305 if (t4_nofldrxq10g < 1)
9306 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
9308 if (t4_nofldrxq1g < 1)
9309 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
9311 if (t4_nofldrxq_vi < 1)
9312 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI);
9314 if (t4_toecaps_allowed == -1)
9315 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9317 if (t4_rdmacaps_allowed == -1) {
9318 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9319 FW_CAPS_CONFIG_RDMA_RDMAC;
9322 if (t4_iscsicaps_allowed == -1) {
9323 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9324 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9325 FW_CAPS_CONFIG_ISCSI_T10DIF;
9328 if (t4_toecaps_allowed == -1)
9329 t4_toecaps_allowed = 0;
9331 if (t4_rdmacaps_allowed == -1)
9332 t4_rdmacaps_allowed = 0;
9334 if (t4_iscsicaps_allowed == -1)
9335 t4_iscsicaps_allowed = 0;
9339 if (t4_nnmtxq_vi < 1)
9340 t4_nnmtxq_vi = min(nc, NNMTXQ_VI);
9342 if (t4_nnmrxq_vi < 1)
9343 t4_nnmrxq_vi = min(nc, NNMRXQ_VI);
9346 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
9347 t4_tmr_idx_10g = TMR_IDX_10G;
9349 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
9350 t4_pktc_idx_10g = PKTC_IDX_10G;
9352 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
9353 t4_tmr_idx_1g = TMR_IDX_1G;
9355 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
9356 t4_pktc_idx_1g = PKTC_IDX_1G;
9358 if (t4_qsize_txq < 128)
9361 if (t4_qsize_rxq < 128)
9363 while (t4_qsize_rxq & 7)
9366 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9371 t4_dump_tcb(struct adapter *sc, int tid)
9373 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9375 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9376 save = t4_read_reg(sc, reg);
9377 base = sc->memwin[2].mw_base;
9379 /* Dump TCB for the tid */
9380 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9381 tcb_addr += tid * TCB_SIZE;
9385 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9387 pf = V_PFNUM(sc->pf);
9388 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9390 t4_write_reg(sc, reg, win_pos | pf);
9391 t4_read_reg(sc, reg);
9393 off = tcb_addr - win_pos;
9394 for (i = 0; i < 4; i++) {
9396 for (j = 0; j < 8; j++, off += 4)
9397 buf[j] = htonl(t4_read_reg(sc, base + off));
9399 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9400 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9404 t4_write_reg(sc, reg, save);
9405 t4_read_reg(sc, reg);
9409 t4_dump_devlog(struct adapter *sc)
9411 struct devlog_params *dparams = &sc->params.devlog;
9412 struct fw_devlog_e e;
9413 int i, first, j, m, nentries, rc;
9414 uint64_t ftstamp = UINT64_MAX;
9416 if (dparams->start == 0) {
9417 db_printf("devlog params not valid\n");
9421 nentries = dparams->size / sizeof(struct fw_devlog_e);
9422 m = fwmtype_to_hwmtype(dparams->memtype);
9424 /* Find the first entry. */
9426 for (i = 0; i < nentries && !db_pager_quit; i++) {
9427 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9428 sizeof(e), (void *)&e);
9432 if (e.timestamp == 0)
9435 e.timestamp = be64toh(e.timestamp);
9436 if (e.timestamp < ftstamp) {
9437 ftstamp = e.timestamp;
9447 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9448 sizeof(e), (void *)&e);
9452 if (e.timestamp == 0)
9455 e.timestamp = be64toh(e.timestamp);
9456 e.seqno = be32toh(e.seqno);
9457 for (j = 0; j < 8; j++)
9458 e.params[j] = be32toh(e.params[j]);
9460 db_printf("%10d %15ju %8s %8s ",
9461 e.seqno, e.timestamp,
9462 (e.level < nitems(devlog_level_strings) ?
9463 devlog_level_strings[e.level] : "UNKNOWN"),
9464 (e.facility < nitems(devlog_facility_strings) ?
9465 devlog_facility_strings[e.facility] : "UNKNOWN"));
9466 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
9467 e.params[3], e.params[4], e.params[5], e.params[6],
9470 if (++i == nentries)
9472 } while (i != first && !db_pager_quit);
9475 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
9476 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
9478 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
9485 t = db_read_token();
9487 dev = device_lookup_by_name(db_tok_string);
9492 db_printf("usage: show t4 devlog <nexus>\n");
9497 db_printf("device not found\n");
9501 t4_dump_devlog(device_get_softc(dev));
9504 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
9513 t = db_read_token();
9515 dev = device_lookup_by_name(db_tok_string);
9516 t = db_read_token();
9518 tid = db_tok_number;
9525 db_printf("usage: show t4 tcb <nexus> <tid>\n");
9530 db_printf("device not found\n");
9534 db_printf("invalid tid\n");
9538 t4_dump_tcb(device_get_softc(dev), tid);
9542 static struct sx mlu; /* mod load unload */
9543 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
9546 mod_event(module_t mod, int cmd, void *arg)
9549 static int loaded = 0;
9554 if (loaded++ == 0) {
9556 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
9557 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
9558 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
9559 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
9560 sx_init(&t4_list_lock, "T4/T5 adapters");
9561 SLIST_INIT(&t4_list);
9563 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
9564 SLIST_INIT(&t4_uld_list);
9566 t4_tracer_modload();
9574 if (--loaded == 0) {
9577 sx_slock(&t4_list_lock);
9578 if (!SLIST_EMPTY(&t4_list)) {
9580 sx_sunlock(&t4_list_lock);
9584 sx_slock(&t4_uld_list_lock);
9585 if (!SLIST_EMPTY(&t4_uld_list)) {
9587 sx_sunlock(&t4_uld_list_lock);
9588 sx_sunlock(&t4_list_lock);
9593 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
9594 uprintf("%ju clusters with custom free routine "
9595 "still is use.\n", t4_sge_extfree_refs());
9596 pause("t4unload", 2 * hz);
9599 sx_sunlock(&t4_uld_list_lock);
9601 sx_sunlock(&t4_list_lock);
9603 if (t4_sge_extfree_refs() == 0) {
9604 t4_tracer_modunload();
9606 sx_destroy(&t4_uld_list_lock);
9608 sx_destroy(&t4_list_lock);
9613 loaded++; /* undo earlier decrement */
9624 static devclass_t t4_devclass, t5_devclass, t6_devclass;
9625 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
9626 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
9628 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9629 MODULE_VERSION(t4nex, 1);
9630 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9632 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9633 MODULE_VERSION(t5nex, 1);
9634 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9636 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
9637 MODULE_VERSION(t6nex, 1);
9638 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
9640 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
9641 #endif /* DEV_NETMAP */
9643 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9644 MODULE_VERSION(cxgbe, 1);
9646 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9647 MODULE_VERSION(cxl, 1);
9649 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
9650 MODULE_VERSION(cc, 1);
9652 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9653 MODULE_VERSION(vcxgbe, 1);
9655 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9656 MODULE_VERSION(vcxl, 1);
9658 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
9659 MODULE_VERSION(vcc, 1);