2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include "opt_inet6.h"
35 #include <sys/param.h>
38 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/counter.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
46 #include <sys/pciio.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pci_private.h>
50 #include <sys/firmware.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_types.h>
59 #include <net/if_dl.h>
60 #include <net/if_vlan_var.h>
62 #include <net/rss_config.h>
64 #if defined(__i386__) || defined(__amd64__)
70 #include <ddb/db_lex.h>
73 #include "common/common.h"
74 #include "common/t4_msg.h"
75 #include "common/t4_regs.h"
76 #include "common/t4_regs_values.h"
79 #include "t4_mp_ring.h"
81 /* T4 bus driver interface */
82 static int t4_probe(device_t);
83 static int t4_attach(device_t);
84 static int t4_detach(device_t);
85 static device_method_t t4_methods[] = {
86 DEVMETHOD(device_probe, t4_probe),
87 DEVMETHOD(device_attach, t4_attach),
88 DEVMETHOD(device_detach, t4_detach),
92 static driver_t t4_driver = {
95 sizeof(struct adapter)
99 /* T4 port (cxgbe) interface */
100 static int cxgbe_probe(device_t);
101 static int cxgbe_attach(device_t);
102 static int cxgbe_detach(device_t);
103 device_method_t cxgbe_methods[] = {
104 DEVMETHOD(device_probe, cxgbe_probe),
105 DEVMETHOD(device_attach, cxgbe_attach),
106 DEVMETHOD(device_detach, cxgbe_detach),
109 static driver_t cxgbe_driver = {
112 sizeof(struct port_info)
115 /* T4 VI (vcxgbe) interface */
116 static int vcxgbe_probe(device_t);
117 static int vcxgbe_attach(device_t);
118 static int vcxgbe_detach(device_t);
119 static device_method_t vcxgbe_methods[] = {
120 DEVMETHOD(device_probe, vcxgbe_probe),
121 DEVMETHOD(device_attach, vcxgbe_attach),
122 DEVMETHOD(device_detach, vcxgbe_detach),
125 static driver_t vcxgbe_driver = {
128 sizeof(struct vi_info)
131 static d_ioctl_t t4_ioctl;
133 static struct cdevsw t4_cdevsw = {
134 .d_version = D_VERSION,
139 /* T5 bus driver interface */
140 static int t5_probe(device_t);
141 static device_method_t t5_methods[] = {
142 DEVMETHOD(device_probe, t5_probe),
143 DEVMETHOD(device_attach, t4_attach),
144 DEVMETHOD(device_detach, t4_detach),
148 static driver_t t5_driver = {
151 sizeof(struct adapter)
155 /* T5 port (cxl) interface */
156 static driver_t cxl_driver = {
159 sizeof(struct port_info)
162 /* T5 VI (vcxl) interface */
163 static driver_t vcxl_driver = {
166 sizeof(struct vi_info)
169 /* ifnet + media interface */
170 static void cxgbe_init(void *);
171 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
172 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
173 static void cxgbe_qflush(struct ifnet *);
174 static int cxgbe_media_change(struct ifnet *);
175 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
177 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
180 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
181 * then ADAPTER_LOCK, then t4_uld_list_lock.
183 static struct sx t4_list_lock;
184 SLIST_HEAD(, adapter) t4_list;
186 static struct sx t4_uld_list_lock;
187 SLIST_HEAD(, uld_info) t4_uld_list;
191 * Tunables. See tweak_tunables() too.
193 * Each tunable is set to a default value here if it's known at compile-time.
194 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
195 * provide a reasonable default when the driver is loaded.
197 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
198 * T5 are under hw.cxl.
202 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
206 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
210 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
214 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
218 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
221 static int t4_ntxq_vi = -1;
222 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
225 static int t4_nrxq_vi = -1;
226 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
228 static int t4_rsrv_noflowq = 0;
229 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
232 #define NOFLDTXQ_10G 8
233 static int t4_nofldtxq10g = -1;
234 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
236 #define NOFLDRXQ_10G 2
237 static int t4_nofldrxq10g = -1;
238 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
240 #define NOFLDTXQ_1G 2
241 static int t4_nofldtxq1g = -1;
242 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
244 #define NOFLDRXQ_1G 1
245 static int t4_nofldrxq1g = -1;
246 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
248 #define NOFLDTXQ_VI 1
249 static int t4_nofldtxq_vi = -1;
250 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
252 #define NOFLDRXQ_VI 1
253 static int t4_nofldrxq_vi = -1;
254 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
259 static int t4_nnmtxq_vi = -1;
260 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
263 static int t4_nnmrxq_vi = -1;
264 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
268 * Holdoff parameters for 10G and 1G ports.
270 #define TMR_IDX_10G 1
271 int t4_tmr_idx_10g = TMR_IDX_10G;
272 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
274 #define PKTC_IDX_10G (-1)
275 int t4_pktc_idx_10g = PKTC_IDX_10G;
276 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
279 int t4_tmr_idx_1g = TMR_IDX_1G;
280 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
282 #define PKTC_IDX_1G (-1)
283 int t4_pktc_idx_1g = PKTC_IDX_1G;
284 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
287 * Size (# of entries) of each tx and rx queue.
289 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
290 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
292 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
293 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
296 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
298 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
299 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
302 * Configuration file.
304 #define DEFAULT_CF "default"
305 #define FLASH_CF "flash"
306 #define UWIRE_CF "uwire"
307 #define FPGA_CF "fpga"
308 static char t4_cfg_file[32] = DEFAULT_CF;
309 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
312 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
313 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
314 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
315 * mark or when signalled to do so, 0 to never emit PAUSE.
317 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
318 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
321 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
322 * encouraged respectively).
324 static unsigned int t4_fw_install = 1;
325 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
328 * ASIC features that will be used. Disable the ones you don't want so that the
329 * chip resources aren't wasted on features that will not be used.
331 static int t4_nbmcaps_allowed = 0;
332 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
334 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
335 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
337 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
338 FW_CAPS_CONFIG_SWITCH_EGRESS;
339 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
341 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
342 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
344 static int t4_toecaps_allowed = -1;
345 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
347 static int t4_rdmacaps_allowed = -1;
348 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
350 static int t4_tlscaps_allowed = 0;
351 TUNABLE_INT("hw.cxgbe.tlscaps_allowed", &t4_tlscaps_allowed);
353 static int t4_iscsicaps_allowed = -1;
354 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
356 static int t4_fcoecaps_allowed = 0;
357 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
359 static int t5_write_combine = 0;
360 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
362 static int t4_num_vis = 1;
363 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
365 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
366 static int vi_mac_funcs[] = {
369 FW_VI_FUNC_OPENISCSI,
375 struct intrs_and_queues {
376 uint16_t intr_type; /* INTx, MSI, or MSI-X */
377 uint16_t nirq; /* Total # of vectors */
378 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
379 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
380 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
381 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
382 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
383 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
384 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
385 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
386 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
387 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
388 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
390 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
391 uint16_t ntxq_vi; /* # of NIC txq's */
392 uint16_t nrxq_vi; /* # of NIC rxq's */
393 uint16_t nofldtxq_vi; /* # of TOE txq's */
394 uint16_t nofldrxq_vi; /* # of TOE rxq's */
395 uint16_t nnmtxq_vi; /* # of netmap txq's */
396 uint16_t nnmrxq_vi; /* # of netmap rxq's */
399 struct filter_entry {
400 uint32_t valid:1; /* filter allocated and valid */
401 uint32_t locked:1; /* filter is administratively locked */
402 uint32_t pending:1; /* filter action is pending firmware reply */
403 uint32_t smtidx:8; /* Source MAC Table index for smac */
404 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
406 struct t4_filter_specification fs;
409 static void setup_memwin(struct adapter *);
410 static void position_memwin(struct adapter *, int, uint32_t);
411 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
412 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
414 static inline int write_via_memwin(struct adapter *, int, uint32_t,
415 const uint32_t *, int);
416 static int validate_mem_range(struct adapter *, uint32_t, int);
417 static int fwmtype_to_hwmtype(int);
418 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
420 static int fixup_devlog_params(struct adapter *);
421 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
422 struct intrs_and_queues *);
423 static int prep_firmware(struct adapter *);
424 static int partition_resources(struct adapter *, const struct firmware *,
426 static int get_params__pre_init(struct adapter *);
427 static int get_params__post_init(struct adapter *);
428 static int set_params__post_init(struct adapter *);
429 static void t4_set_desc(struct adapter *);
430 static void build_medialist(struct port_info *, struct ifmedia *);
431 static int cxgbe_init_synchronized(struct vi_info *);
432 static int cxgbe_uninit_synchronized(struct vi_info *);
433 static void quiesce_txq(struct adapter *, struct sge_txq *);
434 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
435 static void quiesce_iq(struct adapter *, struct sge_iq *);
436 static void quiesce_fl(struct adapter *, struct sge_fl *);
437 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
438 driver_intr_t *, void *, char *);
439 static int t4_free_irq(struct adapter *, struct irq *);
440 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
441 static void vi_refresh_stats(struct adapter *, struct vi_info *);
442 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
443 static void cxgbe_tick(void *);
444 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
445 static void cxgbe_sysctls(struct port_info *);
446 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
447 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
448 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
449 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
450 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
451 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
452 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
453 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
454 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
455 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
456 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
458 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
459 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
460 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
461 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
462 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
463 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
464 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
465 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
466 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
467 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
468 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
469 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
470 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
471 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
472 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
473 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
474 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
475 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
476 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
477 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
478 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
479 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
480 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
481 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
482 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
483 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
484 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
485 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
486 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
489 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
490 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
491 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
493 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
494 static uint32_t mode_to_fconf(uint32_t);
495 static uint32_t mode_to_iconf(uint32_t);
496 static int check_fspec_against_fconf_iconf(struct adapter *,
497 struct t4_filter_specification *);
498 static int get_filter_mode(struct adapter *, uint32_t *);
499 static int set_filter_mode(struct adapter *, uint32_t);
500 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
501 static int get_filter(struct adapter *, struct t4_filter *);
502 static int set_filter(struct adapter *, struct t4_filter *);
503 static int del_filter(struct adapter *, struct t4_filter *);
504 static void clear_filter(struct filter_entry *);
505 static int set_filter_wr(struct adapter *, int);
506 static int del_filter_wr(struct adapter *, int);
507 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
509 static int get_sge_context(struct adapter *, struct t4_sge_context *);
510 static int load_fw(struct adapter *, struct t4_data *);
511 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
512 static int read_i2c(struct adapter *, struct t4_i2c_data *);
514 static int toe_capability(struct vi_info *, int);
516 static int mod_event(module_t, int, void *);
522 {0xa000, "Chelsio Terminator 4 FPGA"},
523 {0x4400, "Chelsio T440-dbg"},
524 {0x4401, "Chelsio T420-CR"},
525 {0x4402, "Chelsio T422-CR"},
526 {0x4403, "Chelsio T440-CR"},
527 {0x4404, "Chelsio T420-BCH"},
528 {0x4405, "Chelsio T440-BCH"},
529 {0x4406, "Chelsio T440-CH"},
530 {0x4407, "Chelsio T420-SO"},
531 {0x4408, "Chelsio T420-CX"},
532 {0x4409, "Chelsio T420-BT"},
533 {0x440a, "Chelsio T404-BT"},
534 {0x440e, "Chelsio T440-LP-CR"},
536 {0xb000, "Chelsio Terminator 5 FPGA"},
537 {0x5400, "Chelsio T580-dbg"},
538 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
539 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
540 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
541 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
542 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
543 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
544 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
545 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
546 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
547 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
548 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
549 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
550 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
552 {0x5404, "Chelsio T520-BCH"},
553 {0x5405, "Chelsio T540-BCH"},
554 {0x5406, "Chelsio T540-CH"},
555 {0x5408, "Chelsio T520-CX"},
556 {0x540b, "Chelsio B520-SR"},
557 {0x540c, "Chelsio B504-BT"},
558 {0x540f, "Chelsio Amsterdam"},
559 {0x5413, "Chelsio T580-CHR"},
565 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
566 * exactly the same for both rxq and ofld_rxq.
568 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
569 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
571 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
574 t4_probe(device_t dev)
577 uint16_t v = pci_get_vendor(dev);
578 uint16_t d = pci_get_device(dev);
579 uint8_t f = pci_get_function(dev);
581 if (v != PCI_VENDOR_ID_CHELSIO)
584 /* Attach only to PF0 of the FPGA */
585 if (d == 0xa000 && f != 0)
588 for (i = 0; i < nitems(t4_pciids); i++) {
589 if (d == t4_pciids[i].device) {
590 device_set_desc(dev, t4_pciids[i].desc);
591 return (BUS_PROBE_DEFAULT);
599 t5_probe(device_t dev)
602 uint16_t v = pci_get_vendor(dev);
603 uint16_t d = pci_get_device(dev);
604 uint8_t f = pci_get_function(dev);
606 if (v != PCI_VENDOR_ID_CHELSIO)
609 /* Attach only to PF0 of the FPGA */
610 if (d == 0xb000 && f != 0)
613 for (i = 0; i < nitems(t5_pciids); i++) {
614 if (d == t5_pciids[i].device) {
615 device_set_desc(dev, t5_pciids[i].desc);
616 return (BUS_PROBE_DEFAULT);
624 t5_attribute_workaround(device_t dev)
630 * The T5 chips do not properly echo the No Snoop and Relaxed
631 * Ordering attributes when replying to a TLP from a Root
632 * Port. As a workaround, find the parent Root Port and
633 * disable No Snoop and Relaxed Ordering. Note that this
634 * affects all devices under this root port.
636 root_port = pci_find_pcie_root_port(dev);
637 if (root_port == NULL) {
638 device_printf(dev, "Unable to find parent root port\n");
642 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
643 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
644 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
646 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
647 device_get_nameunit(root_port));
651 t4_attach(device_t dev)
654 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
655 struct make_dev_args mda;
656 struct intrs_and_queues iaq;
660 int ofld_rqidx, ofld_tqidx;
663 int nm_rqidx, nm_tqidx;
667 sc = device_get_softc(dev);
669 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
671 if ((pci_get_device(dev) & 0xff00) == 0x5400)
672 t5_attribute_workaround(dev);
673 pci_enable_busmaster(dev);
674 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
677 pci_set_max_read_req(dev, 4096);
678 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
679 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
680 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
682 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
685 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
686 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
688 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
689 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
690 device_get_nameunit(dev));
692 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
693 device_get_nameunit(dev));
694 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
697 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
698 TAILQ_INIT(&sc->sfl);
699 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
701 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
703 rc = t4_map_bars_0_and_4(sc);
705 goto done; /* error message displayed already */
708 * This is the real PF# to which we're attaching. Works from within PCI
709 * passthrough environments too, where pci_get_function() could return a
710 * different PF# depending on the passthrough configuration. We need to
711 * use the real PF# in all our communication with the firmware.
713 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
716 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
718 /* Prepare the adapter for operation. */
719 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
720 rc = -t4_prep_adapter(sc, buf);
723 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
728 * Do this really early, with the memory windows set up even before the
729 * character device. The userland tool's register i/o and mem read
730 * will work even in "recovery mode".
733 if (t4_init_devlog_params(sc, 0) == 0)
734 fixup_devlog_params(sc);
735 make_dev_args_init(&mda);
736 mda.mda_devsw = &t4_cdevsw;
737 mda.mda_uid = UID_ROOT;
738 mda.mda_gid = GID_WHEEL;
740 mda.mda_si_drv1 = sc;
741 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
743 device_printf(dev, "failed to create nexus char device: %d.\n",
746 /* Go no further if recovery mode has been requested. */
747 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
748 device_printf(dev, "recovery mode.\n");
752 #if defined(__i386__)
753 if ((cpu_feature & CPUID_CX8) == 0) {
754 device_printf(dev, "64 bit atomics not available.\n");
760 /* Prepare the firmware for operation */
761 rc = prep_firmware(sc);
763 goto done; /* error message displayed already */
765 rc = get_params__post_init(sc);
767 goto done; /* error message displayed already */
769 rc = set_params__post_init(sc);
771 goto done; /* error message displayed already */
773 rc = t4_map_bar_2(sc);
775 goto done; /* error message displayed already */
777 rc = t4_create_dma_tag(sc);
779 goto done; /* error message displayed already */
782 * Number of VIs to create per-port. The first VI is the "main" regular
783 * VI for the port. The rest are additional virtual interfaces on the
784 * same physical port. Note that the main VI does not have native
785 * netmap support but the extra VIs do.
787 * Limit the number of VIs per port to the number of available
788 * MAC addresses per port.
791 num_vis = t4_num_vis;
794 if (num_vis > nitems(vi_mac_funcs)) {
795 num_vis = nitems(vi_mac_funcs);
796 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
800 * First pass over all the ports - allocate VIs and initialize some
801 * basic parameters like mac address, port type, etc. We also figure
802 * out whether a port is 10G or 1G and use that information when
803 * calculating how many interrupts to attempt to allocate.
806 for_each_port(sc, i) {
807 struct port_info *pi;
809 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
812 /* These must be set before t4_port_init */
816 * XXX: vi[0] is special so we can't delay this allocation until
817 * pi->nvi's final value is known.
819 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
823 * Allocate the "main" VI and initialize parameters
826 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
828 device_printf(dev, "unable to initialize port %d: %d\n",
830 free(pi->vi, M_CXGBE);
836 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX);
837 pi->link_cfg.requested_fc |= t4_pause_settings;
838 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX);
839 pi->link_cfg.fc |= t4_pause_settings;
841 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
843 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
844 free(pi->vi, M_CXGBE);
850 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
851 device_get_nameunit(dev), i);
852 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
853 sc->chan_map[pi->tx_chan] = i;
855 pi->tc = malloc(sizeof(struct tx_sched_class) *
856 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
858 if (is_10G_port(pi) || is_40G_port(pi)) {
866 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
867 if (pi->dev == NULL) {
869 "failed to add device for port %d.\n", i);
873 pi->vi[0].dev = pi->dev;
874 device_set_softc(pi->dev, pi);
878 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
880 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
882 goto done; /* error message displayed already */
883 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
886 sc->intr_type = iaq.intr_type;
887 sc->intr_count = iaq.nirq;
890 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
891 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
893 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
894 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
896 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
897 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
898 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
900 if (is_offload(sc)) {
901 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
902 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
904 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
906 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
909 s->neq += s->nofldtxq + s->nofldrxq;
910 s->niq += s->nofldrxq;
912 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
913 M_CXGBE, M_ZERO | M_WAITOK);
914 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
915 M_CXGBE, M_ZERO | M_WAITOK);
920 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
921 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
923 s->neq += s->nnmtxq + s->nnmrxq;
926 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
927 M_CXGBE, M_ZERO | M_WAITOK);
928 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
929 M_CXGBE, M_ZERO | M_WAITOK);
932 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
934 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
936 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
938 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
940 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
943 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
946 t4_init_l2t(sc, M_WAITOK);
949 * Second pass over the ports. This time we know the number of rx and
950 * tx queues that each port should get.
954 ofld_rqidx = ofld_tqidx = 0;
957 nm_rqidx = nm_tqidx = 0;
959 for_each_port(sc, i) {
960 struct port_info *pi = sc->port[i];
967 for_each_vi(pi, j, vi) {
969 vi->qsize_rxq = t4_qsize_rxq;
970 vi->qsize_txq = t4_qsize_txq;
972 vi->first_rxq = rqidx;
973 vi->first_txq = tqidx;
974 if (is_10G_port(pi) || is_40G_port(pi)) {
975 vi->tmr_idx = t4_tmr_idx_10g;
976 vi->pktc_idx = t4_pktc_idx_10g;
977 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
978 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
979 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
981 vi->tmr_idx = t4_tmr_idx_1g;
982 vi->pktc_idx = t4_pktc_idx_1g;
983 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
984 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
985 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
990 if (j == 0 && vi->ntxq > 1)
991 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
993 vi->rsrv_noflowq = 0;
996 vi->first_ofld_rxq = ofld_rqidx;
997 vi->first_ofld_txq = ofld_tqidx;
998 if (is_10G_port(pi) || is_40G_port(pi)) {
999 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1000 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1002 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1005 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1006 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1008 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1011 ofld_rqidx += vi->nofldrxq;
1012 ofld_tqidx += vi->nofldtxq;
1016 vi->first_nm_rxq = nm_rqidx;
1017 vi->first_nm_txq = nm_tqidx;
1018 vi->nnmrxq = iaq.nnmrxq_vi;
1019 vi->nnmtxq = iaq.nnmtxq_vi;
1020 nm_rqidx += vi->nnmrxq;
1021 nm_tqidx += vi->nnmtxq;
1027 rc = t4_setup_intr_handlers(sc);
1030 "failed to setup interrupt handlers: %d\n", rc);
1034 rc = bus_generic_attach(dev);
1037 "failed to attach all child ports: %d\n", rc);
1042 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1043 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1044 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1045 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1046 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1051 if (rc != 0 && sc->cdev) {
1052 /* cdev was created and so cxgbetool works; recover that way. */
1054 "error during attach, adapter is now in recovery mode.\n");
1059 t4_detach_common(dev);
1070 t4_detach(device_t dev)
1074 sc = device_get_softc(dev);
1076 return (t4_detach_common(dev));
1080 t4_detach_common(device_t dev)
1083 struct port_info *pi;
1086 sc = device_get_softc(dev);
1088 if (sc->flags & FULL_INIT_DONE) {
1089 if (!(sc->flags & IS_VF))
1090 t4_intr_disable(sc);
1094 destroy_dev(sc->cdev);
1098 if (device_is_attached(dev)) {
1099 rc = bus_generic_detach(dev);
1102 "failed to detach child devices: %d\n", rc);
1107 for (i = 0; i < sc->intr_count; i++)
1108 t4_free_irq(sc, &sc->irq[i]);
1110 for (i = 0; i < MAX_NPORTS; i++) {
1113 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1115 device_delete_child(dev, pi->dev);
1117 mtx_destroy(&pi->pi_lock);
1118 free(pi->vi, M_CXGBE);
1119 free(pi->tc, M_CXGBE);
1124 if (sc->flags & FULL_INIT_DONE)
1125 adapter_full_uninit(sc);
1127 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1128 t4_fw_bye(sc, sc->mbox);
1130 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1131 pci_release_msi(dev);
1134 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1138 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1142 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1146 t4_free_l2t(sc->l2t);
1149 free(sc->sge.ofld_rxq, M_CXGBE);
1150 free(sc->sge.ofld_txq, M_CXGBE);
1153 free(sc->sge.nm_rxq, M_CXGBE);
1154 free(sc->sge.nm_txq, M_CXGBE);
1156 free(sc->irq, M_CXGBE);
1157 free(sc->sge.rxq, M_CXGBE);
1158 free(sc->sge.txq, M_CXGBE);
1159 free(sc->sge.ctrlq, M_CXGBE);
1160 free(sc->sge.iqmap, M_CXGBE);
1161 free(sc->sge.eqmap, M_CXGBE);
1162 free(sc->tids.ftid_tab, M_CXGBE);
1163 t4_destroy_dma_tag(sc);
1164 if (mtx_initialized(&sc->sc_lock)) {
1165 sx_xlock(&t4_list_lock);
1166 SLIST_REMOVE(&t4_list, sc, adapter, link);
1167 sx_xunlock(&t4_list_lock);
1168 mtx_destroy(&sc->sc_lock);
1171 callout_drain(&sc->sfl_callout);
1172 if (mtx_initialized(&sc->tids.ftid_lock))
1173 mtx_destroy(&sc->tids.ftid_lock);
1174 if (mtx_initialized(&sc->sfl_lock))
1175 mtx_destroy(&sc->sfl_lock);
1176 if (mtx_initialized(&sc->ifp_lock))
1177 mtx_destroy(&sc->ifp_lock);
1178 if (mtx_initialized(&sc->reg_lock))
1179 mtx_destroy(&sc->reg_lock);
1181 for (i = 0; i < NUM_MEMWIN; i++) {
1182 struct memwin *mw = &sc->memwin[i];
1184 if (rw_initialized(&mw->mw_lock))
1185 rw_destroy(&mw->mw_lock);
1188 bzero(sc, sizeof(*sc));
1194 cxgbe_probe(device_t dev)
1197 struct port_info *pi = device_get_softc(dev);
1199 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1200 device_set_desc_copy(dev, buf);
1202 return (BUS_PROBE_DEFAULT);
1205 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1206 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1207 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1208 #define T4_CAP_ENABLE (T4_CAP)
1211 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1216 vi->xact_addr_filt = -1;
1217 callout_init(&vi->tick, 1);
1219 /* Allocate an ifnet and set it up */
1220 ifp = if_alloc(IFT_ETHER);
1222 device_printf(dev, "Cannot allocate ifnet\n");
1228 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1229 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1231 ifp->if_init = cxgbe_init;
1232 ifp->if_ioctl = cxgbe_ioctl;
1233 ifp->if_transmit = cxgbe_transmit;
1234 ifp->if_qflush = cxgbe_qflush;
1236 ifp->if_capabilities = T4_CAP;
1238 if (vi->nofldrxq != 0)
1239 ifp->if_capabilities |= IFCAP_TOE;
1241 ifp->if_capenable = T4_CAP_ENABLE;
1242 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1243 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1245 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1246 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1247 ifp->if_hw_tsomaxsegsize = 65536;
1249 /* Initialize ifmedia for this VI */
1250 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change,
1251 cxgbe_media_status);
1252 build_medialist(vi->pi, &vi->media);
1254 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1255 EVENTHANDLER_PRI_ANY);
1257 ether_ifattach(ifp, vi->hw_addr);
1259 if (vi->nnmrxq != 0)
1260 cxgbe_nm_attach(vi);
1262 sb = sbuf_new_auto();
1263 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1265 if (ifp->if_capabilities & IFCAP_TOE)
1266 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1267 vi->nofldtxq, vi->nofldrxq);
1270 if (ifp->if_capabilities & IFCAP_NETMAP)
1271 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1272 vi->nnmtxq, vi->nnmrxq);
1275 device_printf(dev, "%s\n", sbuf_data(sb));
1284 cxgbe_attach(device_t dev)
1286 struct port_info *pi = device_get_softc(dev);
1290 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1292 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1296 for_each_vi(pi, i, vi) {
1299 vi->dev = device_add_child(dev, is_t4(pi->adapter) ?
1300 "vcxgbe" : "vcxl", -1);
1301 if (vi->dev == NULL) {
1302 device_printf(dev, "failed to add VI %d\n", i);
1305 device_set_softc(vi->dev, vi);
1310 bus_generic_attach(dev);
1316 cxgbe_vi_detach(struct vi_info *vi)
1318 struct ifnet *ifp = vi->ifp;
1320 ether_ifdetach(ifp);
1323 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1325 /* Let detach proceed even if these fail. */
1327 if (ifp->if_capabilities & IFCAP_NETMAP)
1328 cxgbe_nm_detach(vi);
1330 cxgbe_uninit_synchronized(vi);
1331 callout_drain(&vi->tick);
1334 ifmedia_removeall(&vi->media);
1340 cxgbe_detach(device_t dev)
1342 struct port_info *pi = device_get_softc(dev);
1343 struct adapter *sc = pi->adapter;
1346 /* Detach the extra VIs first. */
1347 rc = bus_generic_detach(dev);
1350 device_delete_children(dev);
1352 doom_vi(sc, &pi->vi[0]);
1354 if (pi->flags & HAS_TRACEQ) {
1355 sc->traceq = -1; /* cloner should not create ifnet */
1356 t4_tracer_port_detach(sc);
1359 cxgbe_vi_detach(&pi->vi[0]);
1360 callout_drain(&pi->tick);
1362 end_synchronized_op(sc, 0);
1368 cxgbe_init(void *arg)
1370 struct vi_info *vi = arg;
1371 struct adapter *sc = vi->pi->adapter;
1373 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1375 cxgbe_init_synchronized(vi);
1376 end_synchronized_op(sc, 0);
1380 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1382 int rc = 0, mtu, flags, can_sleep;
1383 struct vi_info *vi = ifp->if_softc;
1384 struct adapter *sc = vi->pi->adapter;
1385 struct ifreq *ifr = (struct ifreq *)data;
1391 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1394 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1398 if (vi->flags & VI_INIT_DONE) {
1399 t4_update_fl_bufsize(ifp);
1400 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1401 rc = update_mac_settings(ifp, XGMAC_MTU);
1403 end_synchronized_op(sc, 0);
1409 rc = begin_synchronized_op(sc, vi,
1410 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1414 if (ifp->if_flags & IFF_UP) {
1415 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1416 flags = vi->if_flags;
1417 if ((ifp->if_flags ^ flags) &
1418 (IFF_PROMISC | IFF_ALLMULTI)) {
1419 if (can_sleep == 1) {
1420 end_synchronized_op(sc, 0);
1424 rc = update_mac_settings(ifp,
1425 XGMAC_PROMISC | XGMAC_ALLMULTI);
1428 if (can_sleep == 0) {
1429 end_synchronized_op(sc, LOCK_HELD);
1433 rc = cxgbe_init_synchronized(vi);
1435 vi->if_flags = ifp->if_flags;
1436 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1437 if (can_sleep == 0) {
1438 end_synchronized_op(sc, LOCK_HELD);
1442 rc = cxgbe_uninit_synchronized(vi);
1444 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1448 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1449 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1452 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1453 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1454 end_synchronized_op(sc, LOCK_HELD);
1458 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1462 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1463 if (mask & IFCAP_TXCSUM) {
1464 ifp->if_capenable ^= IFCAP_TXCSUM;
1465 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1467 if (IFCAP_TSO4 & ifp->if_capenable &&
1468 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1469 ifp->if_capenable &= ~IFCAP_TSO4;
1471 "tso4 disabled due to -txcsum.\n");
1474 if (mask & IFCAP_TXCSUM_IPV6) {
1475 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1476 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1478 if (IFCAP_TSO6 & ifp->if_capenable &&
1479 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1480 ifp->if_capenable &= ~IFCAP_TSO6;
1482 "tso6 disabled due to -txcsum6.\n");
1485 if (mask & IFCAP_RXCSUM)
1486 ifp->if_capenable ^= IFCAP_RXCSUM;
1487 if (mask & IFCAP_RXCSUM_IPV6)
1488 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1491 * Note that we leave CSUM_TSO alone (it is always set). The
1492 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1493 * sending a TSO request our way, so it's sufficient to toggle
1496 if (mask & IFCAP_TSO4) {
1497 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1498 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1499 if_printf(ifp, "enable txcsum first.\n");
1503 ifp->if_capenable ^= IFCAP_TSO4;
1505 if (mask & IFCAP_TSO6) {
1506 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1507 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1508 if_printf(ifp, "enable txcsum6 first.\n");
1512 ifp->if_capenable ^= IFCAP_TSO6;
1514 if (mask & IFCAP_LRO) {
1515 #if defined(INET) || defined(INET6)
1517 struct sge_rxq *rxq;
1519 ifp->if_capenable ^= IFCAP_LRO;
1520 for_each_rxq(vi, i, rxq) {
1521 if (ifp->if_capenable & IFCAP_LRO)
1522 rxq->iq.flags |= IQ_LRO_ENABLED;
1524 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1529 if (mask & IFCAP_TOE) {
1530 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1532 rc = toe_capability(vi, enable);
1536 ifp->if_capenable ^= mask;
1539 if (mask & IFCAP_VLAN_HWTAGGING) {
1540 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1541 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1542 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1544 if (mask & IFCAP_VLAN_MTU) {
1545 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1547 /* Need to find out how to disable auto-mtu-inflation */
1549 if (mask & IFCAP_VLAN_HWTSO)
1550 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1551 if (mask & IFCAP_VLAN_HWCSUM)
1552 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1554 #ifdef VLAN_CAPABILITIES
1555 VLAN_CAPABILITIES(ifp);
1558 end_synchronized_op(sc, 0);
1563 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1567 struct ifi2creq i2c;
1569 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1572 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1576 if (i2c.len > sizeof(i2c.data)) {
1580 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1583 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr,
1584 i2c.offset, i2c.len, &i2c.data[0]);
1585 end_synchronized_op(sc, 0);
1587 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1592 rc = ether_ioctl(ifp, cmd, data);
1599 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1601 struct vi_info *vi = ifp->if_softc;
1602 struct port_info *pi = vi->pi;
1603 struct adapter *sc = pi->adapter;
1604 struct sge_txq *txq;
1609 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1611 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1616 rc = parse_pkt(sc, &m);
1617 if (__predict_false(rc != 0)) {
1618 MPASS(m == NULL); /* was freed already */
1619 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1624 txq = &sc->sge.txq[vi->first_txq];
1625 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1626 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1630 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1631 if (__predict_false(rc != 0))
1638 cxgbe_qflush(struct ifnet *ifp)
1640 struct vi_info *vi = ifp->if_softc;
1641 struct sge_txq *txq;
1644 /* queues do not exist if !VI_INIT_DONE. */
1645 if (vi->flags & VI_INIT_DONE) {
1646 for_each_txq(vi, i, txq) {
1648 txq->eq.flags &= ~EQ_ENABLED;
1650 while (!mp_ring_is_idle(txq->r)) {
1651 mp_ring_check_drainage(txq->r, 0);
1660 cxgbe_media_change(struct ifnet *ifp)
1662 struct vi_info *vi = ifp->if_softc;
1664 device_printf(vi->dev, "%s unimplemented.\n", __func__);
1666 return (EOPNOTSUPP);
1670 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1672 struct vi_info *vi = ifp->if_softc;
1673 struct port_info *pi = vi->pi;
1674 struct ifmedia_entry *cur;
1675 int speed = pi->link_cfg.speed;
1677 cur = vi->media.ifm_cur;
1679 ifmr->ifm_status = IFM_AVALID;
1680 if (!pi->link_cfg.link_ok)
1683 ifmr->ifm_status |= IFM_ACTIVE;
1685 /* active and current will differ iff current media is autoselect. */
1686 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1689 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1691 ifmr->ifm_active |= IFM_10G_T;
1692 else if (speed == 1000)
1693 ifmr->ifm_active |= IFM_1000_T;
1694 else if (speed == 100)
1695 ifmr->ifm_active |= IFM_100_TX;
1696 else if (speed == 10)
1697 ifmr->ifm_active |= IFM_10_T;
1699 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1704 vcxgbe_probe(device_t dev)
1707 struct vi_info *vi = device_get_softc(dev);
1709 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
1711 device_set_desc_copy(dev, buf);
1713 return (BUS_PROBE_DEFAULT);
1717 vcxgbe_attach(device_t dev)
1720 struct port_info *pi;
1722 int func, index, rc;
1725 vi = device_get_softc(dev);
1729 index = vi - pi->vi;
1730 KASSERT(index < nitems(vi_mac_funcs),
1731 ("%s: VI %s doesn't have a MAC func", __func__,
1732 device_get_nameunit(dev)));
1733 func = vi_mac_funcs[index];
1734 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1735 vi->hw_addr, &vi->rss_size, func, 0);
1737 device_printf(dev, "Failed to allocate virtual interface "
1738 "for port %d: %d\n", pi->port_id, -rc);
1743 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1744 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1745 V_FW_PARAMS_PARAM_YZ(vi->viid);
1746 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
1748 vi->rss_base = 0xffff;
1750 /* MPASS((val >> 16) == rss_size); */
1751 vi->rss_base = val & 0xffff;
1754 rc = cxgbe_vi_attach(dev, vi);
1756 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1763 vcxgbe_detach(device_t dev)
1768 vi = device_get_softc(dev);
1769 sc = vi->pi->adapter;
1773 cxgbe_vi_detach(vi);
1774 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1776 end_synchronized_op(sc, 0);
1782 t4_fatal_err(struct adapter *sc)
1784 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1785 t4_intr_disable(sc);
1786 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1787 device_get_nameunit(sc->dev));
1791 t4_add_adapter(struct adapter *sc)
1793 sx_xlock(&t4_list_lock);
1794 SLIST_INSERT_HEAD(&t4_list, sc, link);
1795 sx_xunlock(&t4_list_lock);
1799 t4_map_bars_0_and_4(struct adapter *sc)
1801 sc->regs_rid = PCIR_BAR(0);
1802 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1803 &sc->regs_rid, RF_ACTIVE);
1804 if (sc->regs_res == NULL) {
1805 device_printf(sc->dev, "cannot map registers.\n");
1808 sc->bt = rman_get_bustag(sc->regs_res);
1809 sc->bh = rman_get_bushandle(sc->regs_res);
1810 sc->mmio_len = rman_get_size(sc->regs_res);
1811 setbit(&sc->doorbells, DOORBELL_KDB);
1813 sc->msix_rid = PCIR_BAR(4);
1814 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1815 &sc->msix_rid, RF_ACTIVE);
1816 if (sc->msix_res == NULL) {
1817 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1825 t4_map_bar_2(struct adapter *sc)
1829 * T4: only iWARP driver uses the userspace doorbells. There is no need
1830 * to map it if RDMA is disabled.
1832 if (is_t4(sc) && sc->rdmacaps == 0)
1835 sc->udbs_rid = PCIR_BAR(2);
1836 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1837 &sc->udbs_rid, RF_ACTIVE);
1838 if (sc->udbs_res == NULL) {
1839 device_printf(sc->dev, "cannot map doorbell BAR.\n");
1842 sc->udbs_base = rman_get_virtual(sc->udbs_res);
1845 setbit(&sc->doorbells, DOORBELL_UDB);
1846 #if defined(__i386__) || defined(__amd64__)
1847 if (t5_write_combine) {
1851 * Enable write combining on BAR2. This is the
1852 * userspace doorbell BAR and is split into 128B
1853 * (UDBS_SEG_SIZE) doorbell regions, each associated
1854 * with an egress queue. The first 64B has the doorbell
1855 * and the second 64B can be used to submit a tx work
1856 * request with an implicit doorbell.
1859 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
1860 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
1862 clrbit(&sc->doorbells, DOORBELL_UDB);
1863 setbit(&sc->doorbells, DOORBELL_WCWR);
1864 setbit(&sc->doorbells, DOORBELL_UDBWC);
1866 device_printf(sc->dev,
1867 "couldn't enable write combining: %d\n",
1871 t4_write_reg(sc, A_SGE_STAT_CFG,
1872 V_STATSOURCE_T5(7) | V_STATMODE(0));
1880 struct memwin_init {
1885 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
1886 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1887 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1888 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
1891 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
1892 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1893 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1894 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
1898 setup_memwin(struct adapter *sc)
1900 const struct memwin_init *mw_init;
1907 * Read low 32b of bar0 indirectly via the hardware backdoor
1908 * mechanism. Works from within PCI passthrough environments
1909 * too, where rman_get_start() can return a different value. We
1910 * need to program the T4 memory window decoders with the actual
1911 * addresses that will be coming across the PCIe link.
1913 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
1914 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
1916 mw_init = &t4_memwin[0];
1918 /* T5+ use the relative offset inside the PCIe BAR */
1921 mw_init = &t5_memwin[0];
1924 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
1925 rw_init(&mw->mw_lock, "memory window access");
1926 mw->mw_base = mw_init->base;
1927 mw->mw_aperture = mw_init->aperture;
1930 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
1931 (mw->mw_base + bar0) | V_BIR(0) |
1932 V_WINDOW(ilog2(mw->mw_aperture) - 10));
1933 rw_wlock(&mw->mw_lock);
1934 position_memwin(sc, i, 0);
1935 rw_wunlock(&mw->mw_lock);
1939 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
1943 * Positions the memory window at the given address in the card's address space.
1944 * There are some alignment requirements and the actual position may be at an
1945 * address prior to the requested address. mw->mw_curpos always has the actual
1946 * position of the window.
1949 position_memwin(struct adapter *sc, int idx, uint32_t addr)
1955 MPASS(idx >= 0 && idx < NUM_MEMWIN);
1956 mw = &sc->memwin[idx];
1957 rw_assert(&mw->mw_lock, RA_WLOCKED);
1961 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
1963 pf = V_PFNUM(sc->pf);
1964 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
1966 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
1967 t4_write_reg(sc, reg, mw->mw_curpos | pf);
1968 t4_read_reg(sc, reg); /* flush */
1972 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1978 MPASS(idx >= 0 && idx < NUM_MEMWIN);
1980 /* Memory can only be accessed in naturally aligned 4 byte units */
1981 if (addr & 3 || len & 3 || len <= 0)
1984 mw = &sc->memwin[idx];
1986 rw_rlock(&mw->mw_lock);
1987 mw_end = mw->mw_curpos + mw->mw_aperture;
1988 if (addr >= mw_end || addr < mw->mw_curpos) {
1989 /* Will need to reposition the window */
1990 if (!rw_try_upgrade(&mw->mw_lock)) {
1991 rw_runlock(&mw->mw_lock);
1992 rw_wlock(&mw->mw_lock);
1994 rw_assert(&mw->mw_lock, RA_WLOCKED);
1995 position_memwin(sc, idx, addr);
1996 rw_downgrade(&mw->mw_lock);
1997 mw_end = mw->mw_curpos + mw->mw_aperture;
1999 rw_assert(&mw->mw_lock, RA_RLOCKED);
2000 while (addr < mw_end && len > 0) {
2002 v = t4_read_reg(sc, mw->mw_base + addr -
2004 *val++ = le32toh(v);
2007 t4_write_reg(sc, mw->mw_base + addr -
2008 mw->mw_curpos, htole32(v));;
2013 rw_runlock(&mw->mw_lock);
2020 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2024 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2028 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2029 const uint32_t *val, int len)
2032 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2036 t4_range_cmp(const void *a, const void *b)
2038 return ((const struct t4_range *)a)->start -
2039 ((const struct t4_range *)b)->start;
2043 * Verify that the memory range specified by the addr/len pair is valid within
2044 * the card's address space.
2047 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2049 struct t4_range mem_ranges[4], *r, *next;
2050 uint32_t em, addr_len;
2051 int i, n, remaining;
2053 /* Memory can only be accessed in naturally aligned 4 byte units */
2054 if (addr & 3 || len & 3 || len <= 0)
2057 /* Enabled memories */
2058 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2062 bzero(r, sizeof(mem_ranges));
2063 if (em & F_EDRAM0_ENABLE) {
2064 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2065 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2067 r->start = G_EDRAM0_BASE(addr_len) << 20;
2068 if (addr >= r->start &&
2069 addr + len <= r->start + r->size)
2075 if (em & F_EDRAM1_ENABLE) {
2076 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2077 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2079 r->start = G_EDRAM1_BASE(addr_len) << 20;
2080 if (addr >= r->start &&
2081 addr + len <= r->start + r->size)
2087 if (em & F_EXT_MEM_ENABLE) {
2088 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2089 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2091 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2092 if (addr >= r->start &&
2093 addr + len <= r->start + r->size)
2099 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2100 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2101 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2103 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2104 if (addr >= r->start &&
2105 addr + len <= r->start + r->size)
2111 MPASS(n <= nitems(mem_ranges));
2114 /* Sort and merge the ranges. */
2115 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2117 /* Start from index 0 and examine the next n - 1 entries. */
2119 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2121 MPASS(r->size > 0); /* r is a valid entry. */
2123 MPASS(next->size > 0); /* and so is the next one. */
2125 while (r->start + r->size >= next->start) {
2126 /* Merge the next one into the current entry. */
2127 r->size = max(r->start + r->size,
2128 next->start + next->size) - r->start;
2129 n--; /* One fewer entry in total. */
2130 if (--remaining == 0)
2131 goto done; /* short circuit */
2134 if (next != r + 1) {
2136 * Some entries were merged into r and next
2137 * points to the first valid entry that couldn't
2140 MPASS(next->size > 0); /* must be valid */
2141 memcpy(r + 1, next, remaining * sizeof(*r));
2144 * This so that the foo->size assertion in the
2145 * next iteration of the loop do the right
2146 * thing for entries that were pulled up and are
2149 MPASS(n < nitems(mem_ranges));
2150 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2151 sizeof(struct t4_range));
2156 /* Done merging the ranges. */
2159 for (i = 0; i < n; i++, r++) {
2160 if (addr >= r->start &&
2161 addr + len <= r->start + r->size)
2170 fwmtype_to_hwmtype(int mtype)
2174 case FW_MEMTYPE_EDC0:
2176 case FW_MEMTYPE_EDC1:
2178 case FW_MEMTYPE_EXTMEM:
2180 case FW_MEMTYPE_EXTMEM1:
2183 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2188 * Verify that the memory range specified by the memtype/offset/len pair is
2189 * valid and lies entirely within the memtype specified. The global address of
2190 * the start of the range is returned in addr.
2193 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2196 uint32_t em, addr_len, maddr;
2198 /* Memory can only be accessed in naturally aligned 4 byte units */
2199 if (off & 3 || len & 3 || len == 0)
2202 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2203 switch (fwmtype_to_hwmtype(mtype)) {
2205 if (!(em & F_EDRAM0_ENABLE))
2207 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2208 maddr = G_EDRAM0_BASE(addr_len) << 20;
2211 if (!(em & F_EDRAM1_ENABLE))
2213 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2214 maddr = G_EDRAM1_BASE(addr_len) << 20;
2217 if (!(em & F_EXT_MEM_ENABLE))
2219 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2220 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2223 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2225 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2226 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2232 *addr = maddr + off; /* global address */
2233 return (validate_mem_range(sc, *addr, len));
2237 fixup_devlog_params(struct adapter *sc)
2239 struct devlog_params *dparams = &sc->params.devlog;
2242 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2243 dparams->size, &dparams->addr);
2249 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2250 struct intrs_and_queues *iaq)
2252 int rc, itype, navail, nrxq10g, nrxq1g, n;
2253 int nofldrxq10g = 0, nofldrxq1g = 0;
2255 bzero(iaq, sizeof(*iaq));
2257 iaq->ntxq10g = t4_ntxq10g;
2258 iaq->ntxq1g = t4_ntxq1g;
2259 iaq->ntxq_vi = t4_ntxq_vi;
2260 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2261 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2262 iaq->nrxq_vi = t4_nrxq_vi;
2263 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2265 if (is_offload(sc)) {
2266 iaq->nofldtxq10g = t4_nofldtxq10g;
2267 iaq->nofldtxq1g = t4_nofldtxq1g;
2268 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2269 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2270 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2271 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2275 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2276 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2279 for (itype = INTR_MSIX; itype; itype >>= 1) {
2281 if ((itype & t4_intr_types) == 0)
2282 continue; /* not allowed */
2284 if (itype == INTR_MSIX)
2285 navail = pci_msix_count(sc->dev);
2286 else if (itype == INTR_MSI)
2287 navail = pci_msi_count(sc->dev);
2294 iaq->intr_type = itype;
2295 iaq->intr_flags_10g = 0;
2296 iaq->intr_flags_1g = 0;
2299 * Best option: an interrupt vector for errors, one for the
2300 * firmware event queue, and one for every rxq (NIC and TOE) of
2301 * every VI. The VIs that support netmap use the same
2302 * interrupts for the NIC rx queues and the netmap rx queues
2303 * because only one set of queues is active at a time.
2305 iaq->nirq = T4_EXTRA_INTR;
2306 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2307 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2308 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2309 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2310 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2311 if (iaq->nirq <= navail &&
2312 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2313 iaq->intr_flags_10g = INTR_ALL;
2314 iaq->intr_flags_1g = INTR_ALL;
2318 /* Disable the VIs (and netmap) if there aren't enough intrs */
2320 device_printf(sc->dev, "virtual interfaces disabled "
2321 "because num_vis=%u with current settings "
2322 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2323 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2324 "nnmrxq_vi=%u) would need %u interrupts but "
2325 "only %u are available.\n", num_vis, nrxq10g,
2326 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2327 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2330 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2331 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2332 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2337 * Second best option: a vector for errors, one for the firmware
2338 * event queue, and vectors for either all the NIC rx queues or
2339 * all the TOE rx queues. The queues that don't get vectors
2340 * will forward their interrupts to those that do.
2342 iaq->nirq = T4_EXTRA_INTR;
2343 if (nrxq10g >= nofldrxq10g) {
2344 iaq->intr_flags_10g = INTR_RXQ;
2345 iaq->nirq += n10g * nrxq10g;
2347 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2348 iaq->nirq += n10g * nofldrxq10g;
2350 if (nrxq1g >= nofldrxq1g) {
2351 iaq->intr_flags_1g = INTR_RXQ;
2352 iaq->nirq += n1g * nrxq1g;
2354 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2355 iaq->nirq += n1g * nofldrxq1g;
2357 if (iaq->nirq <= navail &&
2358 (itype != INTR_MSI || powerof2(iaq->nirq)))
2362 * Next best option: an interrupt vector for errors, one for the
2363 * firmware event queue, and at least one per main-VI. At this
2364 * point we know we'll have to downsize nrxq and/or nofldrxq to
2365 * fit what's available to us.
2367 iaq->nirq = T4_EXTRA_INTR;
2368 iaq->nirq += n10g + n1g;
2369 if (iaq->nirq <= navail) {
2370 int leftover = navail - iaq->nirq;
2373 int target = max(nrxq10g, nofldrxq10g);
2375 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2376 INTR_RXQ : INTR_OFLD_RXQ;
2379 while (n < target && leftover >= n10g) {
2384 iaq->nrxq10g = min(n, nrxq10g);
2386 iaq->nofldrxq10g = min(n, nofldrxq10g);
2391 int target = max(nrxq1g, nofldrxq1g);
2393 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2394 INTR_RXQ : INTR_OFLD_RXQ;
2397 while (n < target && leftover >= n1g) {
2402 iaq->nrxq1g = min(n, nrxq1g);
2404 iaq->nofldrxq1g = min(n, nofldrxq1g);
2408 if (itype != INTR_MSI || powerof2(iaq->nirq))
2413 * Least desirable option: one interrupt vector for everything.
2415 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2416 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2419 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2424 if (itype == INTR_MSIX)
2425 rc = pci_alloc_msix(sc->dev, &navail);
2426 else if (itype == INTR_MSI)
2427 rc = pci_alloc_msi(sc->dev, &navail);
2430 if (navail == iaq->nirq)
2434 * Didn't get the number requested. Use whatever number
2435 * the kernel is willing to allocate (it's in navail).
2437 device_printf(sc->dev, "fewer vectors than requested, "
2438 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2439 itype, iaq->nirq, navail);
2440 pci_release_msi(sc->dev);
2444 device_printf(sc->dev,
2445 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2446 itype, rc, iaq->nirq, navail);
2449 device_printf(sc->dev,
2450 "failed to find a usable interrupt type. "
2451 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2452 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2457 #define FW_VERSION(chip) ( \
2458 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2459 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2460 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2461 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2462 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2468 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2472 .kld_name = "t4fw_cfg",
2473 .fw_mod_name = "t4fw",
2475 .chip = FW_HDR_CHIP_T4,
2476 .fw_ver = htobe32_const(FW_VERSION(T4)),
2477 .intfver_nic = FW_INTFVER(T4, NIC),
2478 .intfver_vnic = FW_INTFVER(T4, VNIC),
2479 .intfver_ofld = FW_INTFVER(T4, OFLD),
2480 .intfver_ri = FW_INTFVER(T4, RI),
2481 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2482 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2483 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2484 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2488 .kld_name = "t5fw_cfg",
2489 .fw_mod_name = "t5fw",
2491 .chip = FW_HDR_CHIP_T5,
2492 .fw_ver = htobe32_const(FW_VERSION(T5)),
2493 .intfver_nic = FW_INTFVER(T5, NIC),
2494 .intfver_vnic = FW_INTFVER(T5, VNIC),
2495 .intfver_ofld = FW_INTFVER(T5, OFLD),
2496 .intfver_ri = FW_INTFVER(T5, RI),
2497 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2498 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2499 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2500 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2505 static struct fw_info *
2506 find_fw_info(int chip)
2510 for (i = 0; i < nitems(fw_info); i++) {
2511 if (fw_info[i].chip == chip)
2512 return (&fw_info[i]);
2518 * Is the given firmware API compatible with the one the driver was compiled
2522 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2525 /* short circuit if it's the exact same firmware version */
2526 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2530 * XXX: Is this too conservative? Perhaps I should limit this to the
2531 * features that are supported in the driver.
2533 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2534 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2535 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2536 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2544 * The firmware in the KLD is usable, but should it be installed? This routine
2545 * explains itself in detail if it indicates the KLD firmware should be
2549 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2553 if (!card_fw_usable) {
2554 reason = "incompatible or unusable";
2559 reason = "older than the version bundled with this driver";
2563 if (t4_fw_install == 2 && k != c) {
2564 reason = "different than the version bundled with this driver";
2571 if (t4_fw_install == 0) {
2572 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2573 "but the driver is prohibited from installing a different "
2574 "firmware on the card.\n",
2575 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2576 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2581 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2582 "installing firmware %u.%u.%u.%u on card.\n",
2583 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2584 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2585 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2586 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2591 * Establish contact with the firmware and determine if we are the master driver
2592 * or not, and whether we are responsible for chip initialization.
2595 prep_firmware(struct adapter *sc)
2597 const struct firmware *fw = NULL, *default_cfg;
2598 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2599 enum dev_state state;
2600 struct fw_info *fw_info;
2601 struct fw_hdr *card_fw; /* fw on the card */
2602 const struct fw_hdr *kld_fw; /* fw in the KLD */
2603 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2606 /* Contact firmware. */
2607 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2608 if (rc < 0 || state == DEV_STATE_ERR) {
2610 device_printf(sc->dev,
2611 "failed to connect to the firmware: %d, %d.\n", rc, state);
2616 sc->flags |= MASTER_PF;
2617 else if (state == DEV_STATE_UNINIT) {
2619 * We didn't get to be the master so we definitely won't be
2620 * configuring the chip. It's a bug if someone else hasn't
2621 * configured it already.
2623 device_printf(sc->dev, "couldn't be master(%d), "
2624 "device not already initialized either(%d).\n", rc, state);
2628 /* This is the firmware whose headers the driver was compiled against */
2629 fw_info = find_fw_info(chip_id(sc));
2630 if (fw_info == NULL) {
2631 device_printf(sc->dev,
2632 "unable to look up firmware information for chip %d.\n",
2636 drv_fw = &fw_info->fw_hdr;
2639 * The firmware KLD contains many modules. The KLD name is also the
2640 * name of the module that contains the default config file.
2642 default_cfg = firmware_get(fw_info->kld_name);
2644 /* Read the header of the firmware on the card */
2645 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2646 rc = -t4_read_flash(sc, FLASH_FW_START,
2647 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2649 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2651 device_printf(sc->dev,
2652 "Unable to read card's firmware header: %d\n", rc);
2656 /* This is the firmware in the KLD */
2657 fw = firmware_get(fw_info->fw_mod_name);
2659 kld_fw = (const void *)fw->data;
2660 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2666 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2667 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2669 * Common case: the firmware on the card is an exact match and
2670 * the KLD is an exact match too, or the KLD is
2671 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2672 * here -- use cxgbetool loadfw if you want to reinstall the
2673 * same firmware as the one on the card.
2675 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2676 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2677 be32toh(card_fw->fw_ver))) {
2679 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2681 device_printf(sc->dev,
2682 "failed to install firmware: %d\n", rc);
2686 /* Installed successfully, update the cached header too. */
2687 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2689 need_fw_reset = 0; /* already reset as part of load_fw */
2692 if (!card_fw_usable) {
2695 d = ntohl(drv_fw->fw_ver);
2696 c = ntohl(card_fw->fw_ver);
2697 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2699 device_printf(sc->dev, "Cannot find a usable firmware: "
2700 "fw_install %d, chip state %d, "
2701 "driver compiled with %d.%d.%d.%d, "
2702 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2703 t4_fw_install, state,
2704 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2705 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2706 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2707 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2708 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2709 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2715 if (need_fw_reset &&
2716 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2717 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2718 if (rc != ETIMEDOUT && rc != EIO)
2719 t4_fw_bye(sc, sc->mbox);
2724 rc = get_params__pre_init(sc);
2726 goto done; /* error message displayed already */
2728 /* Partition adapter resources as specified in the config file. */
2729 if (state == DEV_STATE_UNINIT) {
2731 KASSERT(sc->flags & MASTER_PF,
2732 ("%s: trying to change chip settings when not master.",
2735 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2737 goto done; /* error message displayed already */
2739 t4_tweak_chip_settings(sc);
2741 /* get basic stuff going */
2742 rc = -t4_fw_initialize(sc, sc->mbox);
2744 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2748 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2753 free(card_fw, M_CXGBE);
2755 firmware_put(fw, FIRMWARE_UNLOAD);
2756 if (default_cfg != NULL)
2757 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2762 #define FW_PARAM_DEV(param) \
2763 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2764 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2765 #define FW_PARAM_PFVF(param) \
2766 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2767 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2770 * Partition chip resources for use between various PFs, VFs, etc.
2773 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2774 const char *name_prefix)
2776 const struct firmware *cfg = NULL;
2778 struct fw_caps_config_cmd caps;
2779 uint32_t mtype, moff, finicsum, cfcsum;
2782 * Figure out what configuration file to use. Pick the default config
2783 * file for the card if the user hasn't specified one explicitly.
2785 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2786 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2787 /* Card specific overrides go here. */
2788 if (pci_get_device(sc->dev) == 0x440a)
2789 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2791 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2795 * We need to load another module if the profile is anything except
2796 * "default" or "flash".
2798 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2799 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2802 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2803 cfg = firmware_get(s);
2805 if (default_cfg != NULL) {
2806 device_printf(sc->dev,
2807 "unable to load module \"%s\" for "
2808 "configuration profile \"%s\", will use "
2809 "the default config file instead.\n",
2811 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2814 device_printf(sc->dev,
2815 "unable to load module \"%s\" for "
2816 "configuration profile \"%s\", will use "
2817 "the config file on the card's flash "
2818 "instead.\n", s, sc->cfg_file);
2819 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2825 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2826 default_cfg == NULL) {
2827 device_printf(sc->dev,
2828 "default config file not available, will use the config "
2829 "file on the card's flash instead.\n");
2830 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
2833 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2835 const uint32_t *cfdata;
2836 uint32_t param, val, addr;
2838 KASSERT(cfg != NULL || default_cfg != NULL,
2839 ("%s: no config to upload", __func__));
2842 * Ask the firmware where it wants us to upload the config file.
2844 param = FW_PARAM_DEV(CF);
2845 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2847 /* No support for config file? Shouldn't happen. */
2848 device_printf(sc->dev,
2849 "failed to query config file location: %d.\n", rc);
2852 mtype = G_FW_PARAMS_PARAM_Y(val);
2853 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
2856 * XXX: sheer laziness. We deliberately added 4 bytes of
2857 * useless stuffing/comments at the end of the config file so
2858 * it's ok to simply throw away the last remaining bytes when
2859 * the config file is not an exact multiple of 4. This also
2860 * helps with the validate_mt_off_len check.
2863 cflen = cfg->datasize & ~3;
2866 cflen = default_cfg->datasize & ~3;
2867 cfdata = default_cfg->data;
2870 if (cflen > FLASH_CFG_MAX_SIZE) {
2871 device_printf(sc->dev,
2872 "config file too long (%d, max allowed is %d). "
2873 "Will try to use the config on the card, if any.\n",
2874 cflen, FLASH_CFG_MAX_SIZE);
2875 goto use_config_on_flash;
2878 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
2880 device_printf(sc->dev,
2881 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
2882 "Will try to use the config on the card, if any.\n",
2883 __func__, mtype, moff, cflen, rc);
2884 goto use_config_on_flash;
2886 write_via_memwin(sc, 2, addr, cfdata, cflen);
2888 use_config_on_flash:
2889 mtype = FW_MEMTYPE_FLASH;
2890 moff = t4_flash_cfg_addr(sc);
2893 bzero(&caps, sizeof(caps));
2894 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2895 F_FW_CMD_REQUEST | F_FW_CMD_READ);
2896 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
2897 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
2898 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
2899 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
2901 device_printf(sc->dev,
2902 "failed to pre-process config file: %d "
2903 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
2907 finicsum = be32toh(caps.finicsum);
2908 cfcsum = be32toh(caps.cfcsum);
2909 if (finicsum != cfcsum) {
2910 device_printf(sc->dev,
2911 "WARNING: config file checksum mismatch: %08x %08x\n",
2914 sc->cfcsum = cfcsum;
2916 #define LIMIT_CAPS(x) do { \
2917 caps.x &= htobe16(t4_##x##_allowed); \
2921 * Let the firmware know what features will (not) be used so it can tune
2922 * things accordingly.
2924 LIMIT_CAPS(nbmcaps);
2925 LIMIT_CAPS(linkcaps);
2926 LIMIT_CAPS(switchcaps);
2927 LIMIT_CAPS(niccaps);
2928 LIMIT_CAPS(toecaps);
2929 LIMIT_CAPS(rdmacaps);
2930 LIMIT_CAPS(tlscaps);
2931 LIMIT_CAPS(iscsicaps);
2932 LIMIT_CAPS(fcoecaps);
2935 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2936 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
2937 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
2938 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
2940 device_printf(sc->dev,
2941 "failed to process config file: %d.\n", rc);
2945 firmware_put(cfg, FIRMWARE_UNLOAD);
2950 * Retrieve parameters that are needed (or nice to have) very early.
2953 get_params__pre_init(struct adapter *sc)
2956 uint32_t param[2], val[2];
2958 t4_get_version_info(sc);
2960 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
2961 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
2962 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
2963 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
2964 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
2966 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
2967 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
2968 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
2969 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
2970 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
2972 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
2973 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
2974 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
2975 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
2976 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
2978 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
2979 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
2980 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
2981 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
2982 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
2984 param[0] = FW_PARAM_DEV(PORTVEC);
2985 param[1] = FW_PARAM_DEV(CCLK);
2986 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
2988 device_printf(sc->dev,
2989 "failed to query parameters (pre_init): %d.\n", rc);
2993 sc->params.portvec = val[0];
2994 sc->params.nports = bitcount32(val[0]);
2995 sc->params.vpd.cclk = val[1];
2997 /* Read device log parameters. */
2998 rc = -t4_init_devlog_params(sc, 1);
3000 fixup_devlog_params(sc);
3002 device_printf(sc->dev,
3003 "failed to get devlog parameters: %d.\n", rc);
3004 rc = 0; /* devlog isn't critical for device operation */
3011 * Retrieve various parameters that are of interest to the driver. The device
3012 * has been initialized by the firmware at this point.
3015 get_params__post_init(struct adapter *sc)
3018 uint32_t param[7], val[7];
3019 struct fw_caps_config_cmd caps;
3021 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3022 param[1] = FW_PARAM_PFVF(EQ_START);
3023 param[2] = FW_PARAM_PFVF(FILTER_START);
3024 param[3] = FW_PARAM_PFVF(FILTER_END);
3025 param[4] = FW_PARAM_PFVF(L2T_START);
3026 param[5] = FW_PARAM_PFVF(L2T_END);
3027 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3029 device_printf(sc->dev,
3030 "failed to query parameters (post_init): %d.\n", rc);
3034 sc->sge.iq_start = val[0];
3035 sc->sge.eq_start = val[1];
3036 sc->tids.ftid_base = val[2];
3037 sc->tids.nftids = val[3] - val[2] + 1;
3038 sc->params.ftid_min = val[2];
3039 sc->params.ftid_max = val[3];
3040 sc->vres.l2t.start = val[4];
3041 sc->vres.l2t.size = val[5] - val[4] + 1;
3042 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3043 ("%s: L2 table size (%u) larger than expected (%u)",
3044 __func__, sc->vres.l2t.size, L2T_SIZE));
3046 /* get capabilites */
3047 bzero(&caps, sizeof(caps));
3048 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3049 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3050 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3051 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3053 device_printf(sc->dev,
3054 "failed to get card capabilities: %d.\n", rc);
3058 #define READ_CAPS(x) do { \
3059 sc->x = htobe16(caps.x); \
3062 READ_CAPS(linkcaps);
3063 READ_CAPS(switchcaps);
3066 READ_CAPS(rdmacaps);
3068 READ_CAPS(iscsicaps);
3069 READ_CAPS(fcoecaps);
3071 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3072 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3073 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3074 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3075 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3077 device_printf(sc->dev,
3078 "failed to query NIC parameters: %d.\n", rc);
3081 sc->tids.etid_base = val[0];
3082 sc->params.etid_min = val[0];
3083 sc->tids.netids = val[1] - val[0] + 1;
3084 sc->params.netids = sc->tids.netids;
3085 sc->params.eo_wr_cred = val[2];
3086 sc->params.ethoffload = 1;
3090 /* query offload-related parameters */
3091 param[0] = FW_PARAM_DEV(NTID);
3092 param[1] = FW_PARAM_PFVF(SERVER_START);
3093 param[2] = FW_PARAM_PFVF(SERVER_END);
3094 param[3] = FW_PARAM_PFVF(TDDP_START);
3095 param[4] = FW_PARAM_PFVF(TDDP_END);
3096 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3097 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3099 device_printf(sc->dev,
3100 "failed to query TOE parameters: %d.\n", rc);
3103 sc->tids.ntids = val[0];
3104 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3105 sc->tids.stid_base = val[1];
3106 sc->tids.nstids = val[2] - val[1] + 1;
3107 sc->vres.ddp.start = val[3];
3108 sc->vres.ddp.size = val[4] - val[3] + 1;
3109 sc->params.ofldq_wr_cred = val[5];
3110 sc->params.offload = 1;
3113 param[0] = FW_PARAM_PFVF(STAG_START);
3114 param[1] = FW_PARAM_PFVF(STAG_END);
3115 param[2] = FW_PARAM_PFVF(RQ_START);
3116 param[3] = FW_PARAM_PFVF(RQ_END);
3117 param[4] = FW_PARAM_PFVF(PBL_START);
3118 param[5] = FW_PARAM_PFVF(PBL_END);
3119 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3121 device_printf(sc->dev,
3122 "failed to query RDMA parameters(1): %d.\n", rc);
3125 sc->vres.stag.start = val[0];
3126 sc->vres.stag.size = val[1] - val[0] + 1;
3127 sc->vres.rq.start = val[2];
3128 sc->vres.rq.size = val[3] - val[2] + 1;
3129 sc->vres.pbl.start = val[4];
3130 sc->vres.pbl.size = val[5] - val[4] + 1;
3132 param[0] = FW_PARAM_PFVF(SQRQ_START);
3133 param[1] = FW_PARAM_PFVF(SQRQ_END);
3134 param[2] = FW_PARAM_PFVF(CQ_START);
3135 param[3] = FW_PARAM_PFVF(CQ_END);
3136 param[4] = FW_PARAM_PFVF(OCQ_START);
3137 param[5] = FW_PARAM_PFVF(OCQ_END);
3138 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3140 device_printf(sc->dev,
3141 "failed to query RDMA parameters(2): %d.\n", rc);
3144 sc->vres.qp.start = val[0];
3145 sc->vres.qp.size = val[1] - val[0] + 1;
3146 sc->vres.cq.start = val[2];
3147 sc->vres.cq.size = val[3] - val[2] + 1;
3148 sc->vres.ocq.start = val[4];
3149 sc->vres.ocq.size = val[5] - val[4] + 1;
3151 if (sc->iscsicaps) {
3152 param[0] = FW_PARAM_PFVF(ISCSI_START);
3153 param[1] = FW_PARAM_PFVF(ISCSI_END);
3154 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3156 device_printf(sc->dev,
3157 "failed to query iSCSI parameters: %d.\n", rc);
3160 sc->vres.iscsi.start = val[0];
3161 sc->vres.iscsi.size = val[1] - val[0] + 1;
3164 t4_init_sge_params(sc);
3167 * We've got the params we wanted to query via the firmware. Now grab
3168 * some others directly from the chip.
3170 rc = t4_read_chip_settings(sc);
3176 set_params__post_init(struct adapter *sc)
3178 uint32_t param, val;
3180 /* ask for encapsulated CPLs */
3181 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3183 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3188 #undef FW_PARAM_PFVF
3192 t4_set_desc(struct adapter *sc)
3195 struct adapter_params *p = &sc->params;
3197 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
3199 device_set_desc_copy(sc->dev, buf);
3203 build_medialist(struct port_info *pi, struct ifmedia *media)
3209 ifmedia_removeall(media);
3211 m = IFM_ETHER | IFM_FDX;
3213 switch(pi->port_type) {
3214 case FW_PORT_TYPE_BT_XFI:
3215 case FW_PORT_TYPE_BT_XAUI:
3216 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3219 case FW_PORT_TYPE_BT_SGMII:
3220 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3221 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3222 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3223 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3226 case FW_PORT_TYPE_CX4:
3227 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3228 ifmedia_set(media, m | IFM_10G_CX4);
3231 case FW_PORT_TYPE_QSFP_10G:
3232 case FW_PORT_TYPE_SFP:
3233 case FW_PORT_TYPE_FIBER_XFI:
3234 case FW_PORT_TYPE_FIBER_XAUI:
3235 switch (pi->mod_type) {
3237 case FW_PORT_MOD_TYPE_LR:
3238 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3239 ifmedia_set(media, m | IFM_10G_LR);
3242 case FW_PORT_MOD_TYPE_SR:
3243 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3244 ifmedia_set(media, m | IFM_10G_SR);
3247 case FW_PORT_MOD_TYPE_LRM:
3248 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3249 ifmedia_set(media, m | IFM_10G_LRM);
3252 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3253 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3254 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3255 ifmedia_set(media, m | IFM_10G_TWINAX);
3258 case FW_PORT_MOD_TYPE_NONE:
3260 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3261 ifmedia_set(media, m | IFM_NONE);
3264 case FW_PORT_MOD_TYPE_NA:
3265 case FW_PORT_MOD_TYPE_ER:
3267 device_printf(pi->dev,
3268 "unknown port_type (%d), mod_type (%d)\n",
3269 pi->port_type, pi->mod_type);
3270 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3271 ifmedia_set(media, m | IFM_UNKNOWN);
3276 case FW_PORT_TYPE_QSFP:
3277 switch (pi->mod_type) {
3279 case FW_PORT_MOD_TYPE_LR:
3280 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3281 ifmedia_set(media, m | IFM_40G_LR4);
3284 case FW_PORT_MOD_TYPE_SR:
3285 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3286 ifmedia_set(media, m | IFM_40G_SR4);
3289 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3290 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3291 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3292 ifmedia_set(media, m | IFM_40G_CR4);
3295 case FW_PORT_MOD_TYPE_NONE:
3297 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3298 ifmedia_set(media, m | IFM_NONE);
3302 device_printf(pi->dev,
3303 "unknown port_type (%d), mod_type (%d)\n",
3304 pi->port_type, pi->mod_type);
3305 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3306 ifmedia_set(media, m | IFM_UNKNOWN);
3312 device_printf(pi->dev,
3313 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3315 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3316 ifmedia_set(media, m | IFM_UNKNOWN);
3323 #define FW_MAC_EXACT_CHUNK 7
3326 * Program the port's XGMAC based on parameters in ifnet. The caller also
3327 * indicates which parameters should be programmed (the rest are left alone).
3330 update_mac_settings(struct ifnet *ifp, int flags)
3333 struct vi_info *vi = ifp->if_softc;
3334 struct port_info *pi = vi->pi;
3335 struct adapter *sc = pi->adapter;
3336 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3338 ASSERT_SYNCHRONIZED_OP(sc);
3339 KASSERT(flags, ("%s: not told what to update.", __func__));
3341 if (flags & XGMAC_MTU)
3344 if (flags & XGMAC_PROMISC)
3345 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3347 if (flags & XGMAC_ALLMULTI)
3348 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3350 if (flags & XGMAC_VLANEX)
3351 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3353 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3354 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3355 allmulti, 1, vlanex, false);
3357 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3363 if (flags & XGMAC_UCADDR) {
3364 uint8_t ucaddr[ETHER_ADDR_LEN];
3366 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3367 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3368 ucaddr, true, true);
3371 if_printf(ifp, "change_mac failed: %d\n", rc);
3374 vi->xact_addr_filt = rc;
3379 if (flags & XGMAC_MCADDRS) {
3380 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3383 struct ifmultiaddr *ifma;
3386 if_maddr_rlock(ifp);
3387 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3388 if (ifma->ifma_addr->sa_family != AF_LINK)
3391 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3392 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3395 if (i == FW_MAC_EXACT_CHUNK) {
3396 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3397 del, i, mcaddr, NULL, &hash, 0);
3400 for (j = 0; j < i; j++) {
3402 "failed to add mc address"
3404 "%02x:%02x:%02x rc=%d\n",
3405 mcaddr[j][0], mcaddr[j][1],
3406 mcaddr[j][2], mcaddr[j][3],
3407 mcaddr[j][4], mcaddr[j][5],
3417 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3418 mcaddr, NULL, &hash, 0);
3421 for (j = 0; j < i; j++) {
3423 "failed to add mc address"
3425 "%02x:%02x:%02x rc=%d\n",
3426 mcaddr[j][0], mcaddr[j][1],
3427 mcaddr[j][2], mcaddr[j][3],
3428 mcaddr[j][4], mcaddr[j][5],
3435 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3437 if_printf(ifp, "failed to set mc address hash: %d", rc);
3439 if_maddr_runlock(ifp);
3446 * {begin|end}_synchronized_op must be called from the same thread.
3449 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3455 /* the caller thinks it's ok to sleep, but is it really? */
3456 if (flags & SLEEP_OK)
3457 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3458 "begin_synchronized_op");
3469 if (vi && IS_DOOMED(vi)) {
3479 if (!(flags & SLEEP_OK)) {
3484 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3490 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3493 sc->last_op = wmesg;
3494 sc->last_op_thr = curthread;
3495 sc->last_op_flags = flags;
3499 if (!(flags & HOLD_LOCK) || rc)
3506 * Tell if_ioctl and if_init that the VI is going away. This is
3507 * special variant of begin_synchronized_op and must be paired with a
3508 * call to end_synchronized_op.
3511 doom_vi(struct adapter *sc, struct vi_info *vi)
3518 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3521 sc->last_op = "t4detach";
3522 sc->last_op_thr = curthread;
3523 sc->last_op_flags = 0;
3529 * {begin|end}_synchronized_op must be called from the same thread.
3532 end_synchronized_op(struct adapter *sc, int flags)
3535 if (flags & LOCK_HELD)
3536 ADAPTER_LOCK_ASSERT_OWNED(sc);
3540 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3547 cxgbe_init_synchronized(struct vi_info *vi)
3549 struct port_info *pi = vi->pi;
3550 struct adapter *sc = pi->adapter;
3551 struct ifnet *ifp = vi->ifp;
3553 struct sge_txq *txq;
3555 ASSERT_SYNCHRONIZED_OP(sc);
3557 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3558 return (0); /* already running */
3560 if (!(sc->flags & FULL_INIT_DONE) &&
3561 ((rc = adapter_full_init(sc)) != 0))
3562 return (rc); /* error message displayed already */
3564 if (!(vi->flags & VI_INIT_DONE) &&
3565 ((rc = vi_full_init(vi)) != 0))
3566 return (rc); /* error message displayed already */
3568 rc = update_mac_settings(ifp, XGMAC_ALL);
3570 goto done; /* error message displayed already */
3572 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
3574 if_printf(ifp, "enable_vi failed: %d\n", rc);
3579 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
3583 for_each_txq(vi, i, txq) {
3585 txq->eq.flags |= EQ_ENABLED;
3590 * The first iq of the first port to come up is used for tracing.
3592 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
3593 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
3594 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
3595 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3596 V_QUEUENUMBER(sc->traceq));
3597 pi->flags |= HAS_TRACEQ;
3602 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3605 if (pi->nvi > 1 || sc->flags & IS_VF)
3606 callout_reset(&vi->tick, hz, vi_tick, vi);
3608 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3612 cxgbe_uninit_synchronized(vi);
3621 cxgbe_uninit_synchronized(struct vi_info *vi)
3623 struct port_info *pi = vi->pi;
3624 struct adapter *sc = pi->adapter;
3625 struct ifnet *ifp = vi->ifp;
3627 struct sge_txq *txq;
3629 ASSERT_SYNCHRONIZED_OP(sc);
3631 if (!(vi->flags & VI_INIT_DONE)) {
3632 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
3633 ("uninited VI is running"));
3638 * Disable the VI so that all its data in either direction is discarded
3639 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
3640 * tick) intact as the TP can deliver negative advice or data that it's
3641 * holding in its RAM (for an offloaded connection) even after the VI is
3644 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
3646 if_printf(ifp, "disable_vi failed: %d\n", rc);
3650 for_each_txq(vi, i, txq) {
3652 txq->eq.flags &= ~EQ_ENABLED;
3657 if (pi->nvi > 1 || sc->flags & IS_VF)
3658 callout_stop(&vi->tick);
3660 callout_stop(&pi->tick);
3661 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3665 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3667 if (pi->up_vis > 0) {
3673 pi->link_cfg.link_ok = 0;
3674 pi->link_cfg.speed = 0;
3676 t4_os_link_changed(sc, pi->port_id, 0, -1);
3682 * It is ok for this function to fail midway and return right away. t4_detach
3683 * will walk the entire sc->irq list and clean up whatever is valid.
3686 t4_setup_intr_handlers(struct adapter *sc)
3688 int rc, rid, p, q, v;
3691 struct port_info *pi;
3693 struct sge *sge = &sc->sge;
3694 struct sge_rxq *rxq;
3696 struct sge_ofld_rxq *ofld_rxq;
3699 struct sge_nm_rxq *nm_rxq;
3706 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3707 if (sc->intr_count == 1)
3708 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3710 /* Multiple interrupts. */
3711 if (sc->flags & IS_VF)
3712 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
3713 ("%s: too few intr.", __func__));
3715 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3716 ("%s: too few intr.", __func__));
3718 /* The first one is always error intr on PFs */
3719 if (!(sc->flags & IS_VF)) {
3720 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3727 /* The second one is always the firmware event queue (first on VFs) */
3728 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
3734 for_each_port(sc, p) {
3736 for_each_vi(pi, v, vi) {
3737 vi->first_intr = rid - 1;
3739 if (vi->nnmrxq > 0) {
3740 int n = max(vi->nrxq, vi->nnmrxq);
3742 MPASS(vi->flags & INTR_RXQ);
3744 rxq = &sge->rxq[vi->first_rxq];
3746 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
3748 for (q = 0; q < n; q++) {
3749 snprintf(s, sizeof(s), "%x%c%x", p,
3755 irq->nm_rxq = nm_rxq++;
3757 rc = t4_alloc_irq(sc, irq, rid,
3758 t4_vi_intr, irq, s);
3765 } else if (vi->flags & INTR_RXQ) {
3766 for_each_rxq(vi, q, rxq) {
3767 snprintf(s, sizeof(s), "%x%c%x", p,
3769 rc = t4_alloc_irq(sc, irq, rid,
3779 if (vi->flags & INTR_OFLD_RXQ) {
3780 for_each_ofld_rxq(vi, q, ofld_rxq) {
3781 snprintf(s, sizeof(s), "%x%c%x", p,
3783 rc = t4_alloc_irq(sc, irq, rid,
3784 t4_intr, ofld_rxq, s);
3795 MPASS(irq == &sc->irq[sc->intr_count]);
3801 adapter_full_init(struct adapter *sc)
3805 ASSERT_SYNCHRONIZED_OP(sc);
3806 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3807 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3808 ("%s: FULL_INIT_DONE already", __func__));
3811 * queues that belong to the adapter (not any particular port).
3813 rc = t4_setup_adapter_queues(sc);
3817 for (i = 0; i < nitems(sc->tq); i++) {
3818 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
3819 taskqueue_thread_enqueue, &sc->tq[i]);
3820 if (sc->tq[i] == NULL) {
3821 device_printf(sc->dev,
3822 "failed to allocate task queue %d\n", i);
3826 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
3827 device_get_nameunit(sc->dev), i);
3830 if (!(sc->flags & IS_VF))
3832 sc->flags |= FULL_INIT_DONE;
3835 adapter_full_uninit(sc);
3841 adapter_full_uninit(struct adapter *sc)
3845 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3847 t4_teardown_adapter_queues(sc);
3849 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
3850 taskqueue_free(sc->tq[i]);
3854 sc->flags &= ~FULL_INIT_DONE;
3860 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
3861 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
3862 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
3863 RSS_HASHTYPE_RSS_UDP_IPV6)
3865 /* Translates kernel hash types to hardware. */
3867 hashconfig_to_hashen(int hashconfig)
3871 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
3872 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
3873 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
3874 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
3875 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
3876 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
3877 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
3879 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
3880 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
3881 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
3883 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
3884 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
3885 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
3886 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
3891 /* Translates hardware hash types to kernel. */
3893 hashen_to_hashconfig(int hashen)
3897 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
3899 * If UDP hashing was enabled it must have been enabled for
3900 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
3901 * enabling any 4-tuple hash is nonsense configuration.
3903 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
3904 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
3906 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3907 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
3908 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3909 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
3911 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3912 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
3913 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3914 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
3915 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3916 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
3917 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3918 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
3920 return (hashconfig);
3925 vi_full_init(struct vi_info *vi)
3927 struct adapter *sc = vi->pi->adapter;
3928 struct ifnet *ifp = vi->ifp;
3930 struct sge_rxq *rxq;
3931 int rc, i, j, hashen;
3933 int nbuckets = rss_getnumbuckets();
3934 int hashconfig = rss_gethashconfig();
3936 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3937 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3940 ASSERT_SYNCHRONIZED_OP(sc);
3941 KASSERT((vi->flags & VI_INIT_DONE) == 0,
3942 ("%s: VI_INIT_DONE already", __func__));
3944 sysctl_ctx_init(&vi->ctx);
3945 vi->flags |= VI_SYSCTL_CTX;
3948 * Allocate tx/rx/fl queues for this VI.
3950 rc = t4_setup_vi_queues(vi);
3952 goto done; /* error message displayed already */
3955 * Setup RSS for this VI. Save a copy of the RSS table for later use.
3957 if (vi->nrxq > vi->rss_size) {
3958 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
3959 "some queues will never receive traffic.\n", vi->nrxq,
3961 } else if (vi->rss_size % vi->nrxq) {
3962 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
3963 "expect uneven traffic distribution.\n", vi->nrxq,
3967 MPASS(RSS_KEYSIZE == 40);
3968 if (vi->nrxq != nbuckets) {
3969 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
3970 "performance will be impacted.\n", vi->nrxq, nbuckets);
3973 rss_getkey((void *)&raw_rss_key[0]);
3974 for (i = 0; i < nitems(rss_key); i++) {
3975 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
3977 t4_write_rss_key(sc, &rss_key[0], -1);
3979 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
3980 for (i = 0; i < vi->rss_size;) {
3982 j = rss_get_indirection_to_bucket(i);
3984 rxq = &sc->sge.rxq[vi->first_rxq + j];
3985 rss[i++] = rxq->iq.abs_id;
3987 for_each_rxq(vi, j, rxq) {
3988 rss[i++] = rxq->iq.abs_id;
3989 if (i == vi->rss_size)
3995 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
3998 if_printf(ifp, "rss_config failed: %d\n", rc);
4003 hashen = hashconfig_to_hashen(hashconfig);
4006 * We may have had to enable some hashes even though the global config
4007 * wants them disabled. This is a potential problem that must be
4008 * reported to the user.
4010 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4013 * If we consider only the supported hash types, then the enabled hashes
4014 * are a superset of the requested hashes. In other words, there cannot
4015 * be any supported hash that was requested but not enabled, but there
4016 * can be hashes that were not requested but had to be enabled.
4018 extra &= SUPPORTED_RSS_HASHTYPES;
4019 MPASS((extra & hashconfig) == 0);
4023 "global RSS config (0x%x) cannot be accomodated.\n",
4026 if (extra & RSS_HASHTYPE_RSS_IPV4)
4027 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4028 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4029 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4030 if (extra & RSS_HASHTYPE_RSS_IPV6)
4031 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4032 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4033 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4034 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4035 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4036 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4037 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4039 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4040 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4041 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4042 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4044 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
4046 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4051 vi->flags |= VI_INIT_DONE;
4063 vi_full_uninit(struct vi_info *vi)
4065 struct port_info *pi = vi->pi;
4066 struct adapter *sc = pi->adapter;
4068 struct sge_rxq *rxq;
4069 struct sge_txq *txq;
4071 struct sge_ofld_rxq *ofld_rxq;
4072 struct sge_wrq *ofld_txq;
4075 if (vi->flags & VI_INIT_DONE) {
4077 /* Need to quiesce queues. */
4079 /* XXX: Only for the first VI? */
4080 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
4081 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4083 for_each_txq(vi, i, txq) {
4084 quiesce_txq(sc, txq);
4088 for_each_ofld_txq(vi, i, ofld_txq) {
4089 quiesce_wrq(sc, ofld_txq);
4093 for_each_rxq(vi, i, rxq) {
4094 quiesce_iq(sc, &rxq->iq);
4095 quiesce_fl(sc, &rxq->fl);
4099 for_each_ofld_rxq(vi, i, ofld_rxq) {
4100 quiesce_iq(sc, &ofld_rxq->iq);
4101 quiesce_fl(sc, &ofld_rxq->fl);
4104 free(vi->rss, M_CXGBE);
4105 free(vi->nm_rss, M_CXGBE);
4108 t4_teardown_vi_queues(vi);
4109 vi->flags &= ~VI_INIT_DONE;
4115 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4117 struct sge_eq *eq = &txq->eq;
4118 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4120 (void) sc; /* unused */
4124 MPASS((eq->flags & EQ_ENABLED) == 0);
4128 /* Wait for the mp_ring to empty. */
4129 while (!mp_ring_is_idle(txq->r)) {
4130 mp_ring_check_drainage(txq->r, 0);
4131 pause("rquiesce", 1);
4134 /* Then wait for the hardware to finish. */
4135 while (spg->cidx != htobe16(eq->pidx))
4136 pause("equiesce", 1);
4138 /* Finally, wait for the driver to reclaim all descriptors. */
4139 while (eq->cidx != eq->pidx)
4140 pause("dquiesce", 1);
4144 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4151 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4153 (void) sc; /* unused */
4155 /* Synchronize with the interrupt handler */
4156 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4161 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4163 mtx_lock(&sc->sfl_lock);
4165 fl->flags |= FL_DOOMED;
4167 callout_stop(&sc->sfl_callout);
4168 mtx_unlock(&sc->sfl_lock);
4170 KASSERT((fl->flags & FL_STARVING) == 0,
4171 ("%s: still starving", __func__));
4175 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4176 driver_intr_t *handler, void *arg, char *name)
4181 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4182 RF_SHAREABLE | RF_ACTIVE);
4183 if (irq->res == NULL) {
4184 device_printf(sc->dev,
4185 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4189 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4190 NULL, handler, arg, &irq->tag);
4192 device_printf(sc->dev,
4193 "failed to setup interrupt for rid %d, name %s: %d\n",
4196 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
4202 t4_free_irq(struct adapter *sc, struct irq *irq)
4205 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4207 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4209 bzero(irq, sizeof(*irq));
4215 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4218 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4219 t4_get_regs(sc, buf, regs->len);
4222 #define A_PL_INDIR_CMD 0x1f8
4224 #define S_PL_AUTOINC 31
4225 #define M_PL_AUTOINC 0x1U
4226 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4227 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4229 #define S_PL_VFID 20
4230 #define M_PL_VFID 0xffU
4231 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4232 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4235 #define M_PL_ADDR 0xfffffU
4236 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4237 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4239 #define A_PL_INDIR_DATA 0x1fc
4242 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4246 mtx_assert(&sc->reg_lock, MA_OWNED);
4247 if (sc->flags & IS_VF) {
4248 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
4249 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
4251 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4252 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4253 V_PL_ADDR(VF_MPS_REG(reg)));
4254 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4255 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4257 return (((uint64_t)stats[1]) << 32 | stats[0]);
4261 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4262 struct fw_vi_stats_vf *stats)
4265 #define GET_STAT(name) \
4266 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4268 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4269 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4270 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4271 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4272 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4273 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4274 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4275 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4276 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4277 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4278 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4279 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4280 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4281 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4282 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4283 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4289 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4293 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4294 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4295 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4296 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4297 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4298 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4302 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4304 struct ifnet *ifp = vi->ifp;
4305 struct sge_txq *txq;
4307 struct fw_vi_stats_vf *s = &vi->stats;
4309 const struct timeval interval = {0, 250000}; /* 250ms */
4311 if (!(vi->flags & VI_INIT_DONE))
4315 timevalsub(&tv, &interval);
4316 if (timevalcmp(&tv, &vi->last_refreshed, <))
4319 mtx_lock(&sc->reg_lock);
4320 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4322 ifp->if_ipackets = s->rx_bcast_frames + s->rx_mcast_frames +
4324 ifp->if_ierrors = s->rx_err_frames;
4325 ifp->if_opackets = s->tx_bcast_frames + s->tx_mcast_frames +
4326 s->tx_ucast_frames + s->tx_offload_frames;
4327 ifp->if_oerrors = s->tx_drop_frames;
4328 ifp->if_ibytes = s->rx_bcast_bytes + s->rx_mcast_bytes +
4330 ifp->if_obytes = s->tx_bcast_bytes + s->tx_mcast_bytes +
4331 s->tx_ucast_bytes + s->tx_offload_bytes;
4332 ifp->if_imcasts = s->rx_mcast_frames;
4333 ifp->if_omcasts = s->tx_mcast_frames;
4336 for_each_txq(vi, i, txq)
4337 drops += counter_u64_fetch(txq->r->drops);
4338 ifp->if_snd.ifq_drops = drops;
4340 getmicrotime(&vi->last_refreshed);
4341 mtx_unlock(&sc->reg_lock);
4345 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4347 struct vi_info *vi = &pi->vi[0];
4348 struct ifnet *ifp = vi->ifp;
4349 struct sge_txq *txq;
4351 struct port_stats *s = &pi->stats;
4353 const struct timeval interval = {0, 250000}; /* 250ms */
4356 timevalsub(&tv, &interval);
4357 if (timevalcmp(&tv, &pi->last_refreshed, <))
4360 t4_get_port_stats(sc, pi->tx_chan, s);
4362 ifp->if_opackets = s->tx_frames;
4363 ifp->if_ipackets = s->rx_frames;
4364 ifp->if_obytes = s->tx_octets;
4365 ifp->if_ibytes = s->rx_octets;
4366 ifp->if_omcasts = s->tx_mcast_frames;
4367 ifp->if_imcasts = s->rx_mcast_frames;
4368 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4369 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4371 for (i = 0; i < sc->chip_params->nchan; i++) {
4372 if (pi->rx_chan_map & (1 << i)) {
4375 mtx_lock(&sc->reg_lock);
4376 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4377 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4378 mtx_unlock(&sc->reg_lock);
4379 ifp->if_iqdrops += v;
4384 for_each_txq(vi, i, txq)
4385 drops += counter_u64_fetch(txq->r->drops);
4386 ifp->if_snd.ifq_drops = drops;
4388 ifp->if_oerrors = s->tx_error_frames;
4389 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4390 s->rx_fcs_err + s->rx_len_err;
4392 getmicrotime(&pi->last_refreshed);
4396 cxgbe_tick(void *arg)
4398 struct port_info *pi = arg;
4399 struct adapter *sc = pi->adapter;
4401 PORT_LOCK_ASSERT_OWNED(pi);
4402 cxgbe_refresh_stats(sc, pi);
4404 callout_schedule(&pi->tick, hz);
4410 struct vi_info *vi = arg;
4411 struct adapter *sc = vi->pi->adapter;
4413 vi_refresh_stats(sc, vi);
4415 callout_schedule(&vi->tick, hz);
4419 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4423 if (arg != ifp || ifp->if_type != IFT_ETHER)
4426 vlan = VLAN_DEVAT(ifp, vid);
4427 VLAN_SETCOOKIE(vlan, ifp);
4431 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4433 static char *caps_decoder[] = {
4434 "\20\001IPMI\002NCSI", /* 0: NBM */
4435 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4436 "\20\001INGRESS\002EGRESS", /* 2: switch */
4437 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4438 "\006HASHFILTER\007ETHOFLD",
4439 "\20\001TOE", /* 4: TOE */
4440 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4441 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4442 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4443 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4445 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4446 "\20\00KEYS", /* 7: TLS */
4447 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4448 "\004PO_INITIATOR\005PO_TARGET",
4452 t4_sysctls(struct adapter *sc)
4454 struct sysctl_ctx_list *ctx;
4455 struct sysctl_oid *oid;
4456 struct sysctl_oid_list *children, *c0;
4457 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4459 ctx = device_get_sysctl_ctx(sc->dev);
4464 oid = device_get_sysctl_tree(sc->dev);
4465 c0 = children = SYSCTL_CHILDREN(oid);
4467 sc->sc_do_rxcopy = 1;
4468 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4469 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4471 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4472 sc->params.nports, "# of ports");
4474 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4475 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4476 sysctl_bitfield, "A", "available doorbells");
4478 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4479 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4481 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4482 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4483 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4484 "interrupt holdoff timer values (us)");
4486 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4487 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4488 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4489 "interrupt holdoff packet counter values");
4491 t4_sge_sysctls(sc, ctx, children);
4493 sc->lro_timeout = 100;
4494 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4495 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4497 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
4498 &sc->debug_flags, 0, "flags to enable runtime debugging");
4500 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
4501 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
4503 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4504 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4506 if (sc->flags & IS_VF)
4509 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4510 NULL, chip_rev(sc), "chip hardware revision");
4512 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
4513 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
4515 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
4516 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
4518 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
4519 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
4521 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
4522 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
4524 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
4525 sc->er_version, 0, "expansion ROM version");
4527 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
4528 sc->bs_version, 0, "bootstrap firmware version");
4530 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
4531 NULL, sc->params.scfg_vers, "serial config version");
4533 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
4534 NULL, sc->params.vpd_vers, "VPD version");
4536 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4537 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4539 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4540 sc->cfcsum, "config file checksum");
4542 #define SYSCTL_CAP(name, n, text) \
4543 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4544 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4545 sysctl_bitfield, "A", "available " text " capabilities")
4547 SYSCTL_CAP(nbmcaps, 0, "NBM");
4548 SYSCTL_CAP(linkcaps, 1, "link");
4549 SYSCTL_CAP(switchcaps, 2, "switch");
4550 SYSCTL_CAP(niccaps, 3, "NIC");
4551 SYSCTL_CAP(toecaps, 4, "TCP offload");
4552 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4553 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4554 SYSCTL_CAP(tlscaps, 7, "TLS");
4555 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4558 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4559 NULL, sc->tids.nftids, "number of filters");
4561 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4562 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4563 "chip temperature (in Celsius)");
4567 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4569 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4570 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4571 "logs and miscellaneous information");
4572 children = SYSCTL_CHILDREN(oid);
4574 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4575 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4576 sysctl_cctrl, "A", "congestion control");
4578 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4579 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4580 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4582 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4583 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4584 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4586 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4587 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4588 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4590 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4591 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4592 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4594 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4595 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4596 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4598 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4599 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4600 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4603 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4604 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
4605 "A", "CIM logic analyzer");
4607 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4608 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4609 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4611 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4612 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4613 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4615 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4616 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4617 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4620 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4621 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4623 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4624 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4625 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4627 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4628 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4629 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4631 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4632 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4633 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4635 if (chip_id(sc) > CHELSIO_T4) {
4636 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4637 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4638 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4641 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4642 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4645 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4646 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4647 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4649 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4650 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4651 sysctl_cim_qcfg, "A", "CIM queue configuration");
4653 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4654 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4655 sysctl_cpl_stats, "A", "CPL statistics");
4657 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4658 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4659 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4662 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4663 sysctl_devlog, "A", "firmware's device log");
4665 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4666 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4667 sysctl_fcoe_stats, "A", "FCoE statistics");
4669 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4670 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4671 sysctl_hw_sched, "A", "hardware scheduler ");
4673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4674 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4675 sysctl_l2t, "A", "hardware L2 table");
4677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4678 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4679 sysctl_lb_stats, "A", "loopback statistics");
4681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4682 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4683 sysctl_meminfo, "A", "memory regions");
4685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4686 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4687 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
4688 "A", "MPS TCAM entries");
4690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4691 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4692 sysctl_path_mtus, "A", "path MTUs");
4694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4695 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4696 sysctl_pm_stats, "A", "PM statistics");
4698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4699 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4700 sysctl_rdma_stats, "A", "RDMA statistics");
4702 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4703 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4704 sysctl_tcp_stats, "A", "TCP statistics");
4706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4707 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4708 sysctl_tids, "A", "TID information");
4710 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4711 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4712 sysctl_tp_err_stats, "A", "TP error statistics");
4714 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
4715 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
4716 "TP logic analyzer event capture mask");
4718 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4719 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4720 sysctl_tp_la, "A", "TP logic analyzer");
4722 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4723 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4724 sysctl_tx_rate, "A", "Tx rate");
4726 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4727 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4728 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4731 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4732 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4733 sysctl_wcwr_stats, "A", "write combined work requests");
4738 if (is_offload(sc)) {
4742 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4743 NULL, "TOE parameters");
4744 children = SYSCTL_CHILDREN(oid);
4746 sc->tt.sndbuf = 256 * 1024;
4747 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4748 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4751 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4752 &sc->tt.ddp, 0, "DDP allowed");
4754 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
4755 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
4756 &sc->tt.indsz, 0, "DDP max indicate size allowed");
4759 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
4760 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
4761 &sc->tt.ddp_thres, 0, "DDP threshold");
4763 sc->tt.rx_coalesce = 1;
4764 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4765 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4767 sc->tt.tx_align = 1;
4768 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4769 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4771 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
4772 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
4773 "TP timer tick (us)");
4775 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
4776 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
4777 "TCP timestamp tick (us)");
4779 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
4780 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
4783 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
4784 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
4785 "IU", "DACK timer (us)");
4787 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
4788 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
4789 sysctl_tp_timer, "LU", "Retransmit min (us)");
4791 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
4792 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
4793 sysctl_tp_timer, "LU", "Retransmit max (us)");
4795 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
4796 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
4797 sysctl_tp_timer, "LU", "Persist timer min (us)");
4799 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
4800 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
4801 sysctl_tp_timer, "LU", "Persist timer max (us)");
4803 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
4804 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
4805 sysctl_tp_timer, "LU", "Keepidle idle timer (us)");
4807 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl",
4808 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
4809 sysctl_tp_timer, "LU", "Keepidle interval (us)");
4811 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
4812 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
4813 sysctl_tp_timer, "LU", "Initial SRTT (us)");
4815 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
4816 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
4817 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
4823 vi_sysctls(struct vi_info *vi)
4825 struct sysctl_ctx_list *ctx;
4826 struct sysctl_oid *oid;
4827 struct sysctl_oid_list *children;
4829 ctx = device_get_sysctl_ctx(vi->dev);
4832 * dev.v?(cxgbe|cxl).X.
4834 oid = device_get_sysctl_tree(vi->dev);
4835 children = SYSCTL_CHILDREN(oid);
4837 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
4838 vi->viid, "VI identifer");
4839 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
4840 &vi->nrxq, 0, "# of rx queues");
4841 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
4842 &vi->ntxq, 0, "# of tx queues");
4843 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
4844 &vi->first_rxq, 0, "index of first rx queue");
4845 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
4846 &vi->first_txq, 0, "index of first tx queue");
4847 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
4848 vi->rss_size, "size of RSS indirection table");
4850 if (IS_MAIN_VI(vi)) {
4851 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
4852 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
4853 "Reserve queue 0 for non-flowid packets");
4857 if (vi->nofldrxq != 0) {
4858 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
4860 "# of rx queues for offloaded TCP connections");
4861 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
4863 "# of tx queues for offloaded TCP connections");
4864 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4865 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
4866 "index of first TOE rx queue");
4867 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4868 CTLFLAG_RD, &vi->first_ofld_txq, 0,
4869 "index of first TOE tx queue");
4873 if (vi->nnmrxq != 0) {
4874 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
4875 &vi->nnmrxq, 0, "# of netmap rx queues");
4876 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
4877 &vi->nnmtxq, 0, "# of netmap tx queues");
4878 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
4879 CTLFLAG_RD, &vi->first_nm_rxq, 0,
4880 "index of first netmap rx queue");
4881 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
4882 CTLFLAG_RD, &vi->first_nm_txq, 0,
4883 "index of first netmap tx queue");
4887 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4888 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
4889 "holdoff timer index");
4890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4891 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
4892 "holdoff packet counter index");
4894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
4895 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
4897 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
4898 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
4903 cxgbe_sysctls(struct port_info *pi)
4905 struct sysctl_ctx_list *ctx;
4906 struct sysctl_oid *oid;
4907 struct sysctl_oid_list *children, *children2;
4908 struct adapter *sc = pi->adapter;
4912 ctx = device_get_sysctl_ctx(pi->dev);
4917 oid = device_get_sysctl_tree(pi->dev);
4918 children = SYSCTL_CHILDREN(oid);
4920 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
4921 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
4922 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
4923 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
4924 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
4925 "PHY temperature (in Celsius)");
4926 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
4927 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
4928 "PHY firmware version");
4931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
4932 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings,
4933 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
4935 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
4936 port_top_speed(pi), "max speed (in Gbps)");
4938 if (sc->flags & IS_VF)
4942 * dev.(cxgbe|cxl).X.tc.
4944 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
4945 "Tx scheduler traffic classes");
4946 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
4947 struct tx_sched_class *tc = &pi->tc[i];
4949 snprintf(name, sizeof(name), "%d", i);
4950 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
4951 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
4953 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
4954 &tc->flags, 0, "flags");
4955 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
4956 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
4958 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
4959 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
4960 sysctl_tc_params, "A", "traffic class parameters");
4965 * dev.cxgbe.X.stats.
4967 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4968 NULL, "port statistics");
4969 children = SYSCTL_CHILDREN(oid);
4970 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
4971 &pi->tx_parse_error, 0,
4972 "# of tx packets with invalid length or # of segments");
4974 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
4975 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
4976 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
4977 sysctl_handle_t4_reg64, "QU", desc)
4979 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
4980 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
4981 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
4982 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
4983 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
4984 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
4985 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
4986 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
4987 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
4988 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
4989 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
4990 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
4991 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
4992 "# of tx frames in this range",
4993 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
4994 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
4995 "# of tx frames in this range",
4996 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
4997 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
4998 "# of tx frames in this range",
4999 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
5000 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
5001 "# of tx frames in this range",
5002 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
5003 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
5004 "# of tx frames in this range",
5005 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
5006 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
5007 "# of tx frames in this range",
5008 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
5009 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
5010 "# of tx frames in this range",
5011 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
5012 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
5013 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
5014 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
5015 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
5016 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
5017 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
5018 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
5019 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
5020 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
5021 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
5022 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
5023 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
5024 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
5025 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
5026 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
5027 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
5028 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
5029 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
5030 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
5031 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
5033 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
5034 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
5035 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
5036 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
5037 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
5038 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
5039 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
5040 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
5041 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
5042 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
5043 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
5044 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
5045 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5046 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5047 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5048 "# of frames received with bad FCS",
5049 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5050 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5051 "# of frames received with length error",
5052 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5053 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5054 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5055 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5056 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5057 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5058 "# of rx frames in this range",
5059 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5060 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5061 "# of rx frames in this range",
5062 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5063 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5064 "# of rx frames in this range",
5065 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5066 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5067 "# of rx frames in this range",
5068 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5069 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5070 "# of rx frames in this range",
5071 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5072 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5073 "# of rx frames in this range",
5074 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5075 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5076 "# of rx frames in this range",
5077 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5078 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5079 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5080 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5081 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5082 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5083 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5084 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5085 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5086 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5087 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5088 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5089 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5090 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5091 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5092 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5093 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5094 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5095 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5097 #undef SYSCTL_ADD_T4_REG64
5099 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5100 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5101 &pi->stats.name, desc)
5103 /* We get these from port_stats and they may be stale by upto 1s */
5104 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5105 "# drops due to buffer-group 0 overflows");
5106 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5107 "# drops due to buffer-group 1 overflows");
5108 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5109 "# drops due to buffer-group 2 overflows");
5110 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5111 "# drops due to buffer-group 3 overflows");
5112 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5113 "# of buffer-group 0 truncated packets");
5114 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5115 "# of buffer-group 1 truncated packets");
5116 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5117 "# of buffer-group 2 truncated packets");
5118 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5119 "# of buffer-group 3 truncated packets");
5121 #undef SYSCTL_ADD_T4_PORTSTAT
5125 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5127 int rc, *i, space = 0;
5130 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5131 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5133 sbuf_printf(&sb, " ");
5134 sbuf_printf(&sb, "%d", *i);
5138 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5144 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5149 rc = sysctl_wire_old_buffer(req, 0);
5153 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5157 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5158 rc = sbuf_finish(sb);
5165 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5167 struct port_info *pi = arg1;
5169 struct adapter *sc = pi->adapter;
5173 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5176 /* XXX: magic numbers */
5177 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5179 end_synchronized_op(sc, 0);
5185 rc = sysctl_handle_int(oidp, &v, 0, req);
5190 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5192 struct vi_info *vi = arg1;
5195 val = vi->rsrv_noflowq;
5196 rc = sysctl_handle_int(oidp, &val, 0, req);
5197 if (rc != 0 || req->newptr == NULL)
5200 if ((val >= 1) && (vi->ntxq > 1))
5201 vi->rsrv_noflowq = 1;
5203 vi->rsrv_noflowq = 0;
5209 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5211 struct vi_info *vi = arg1;
5212 struct adapter *sc = vi->pi->adapter;
5214 struct sge_rxq *rxq;
5216 struct sge_ofld_rxq *ofld_rxq;
5222 rc = sysctl_handle_int(oidp, &idx, 0, req);
5223 if (rc != 0 || req->newptr == NULL)
5226 if (idx < 0 || idx >= SGE_NTIMERS)
5229 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5234 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5235 for_each_rxq(vi, i, rxq) {
5236 #ifdef atomic_store_rel_8
5237 atomic_store_rel_8(&rxq->iq.intr_params, v);
5239 rxq->iq.intr_params = v;
5243 for_each_ofld_rxq(vi, i, ofld_rxq) {
5244 #ifdef atomic_store_rel_8
5245 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5247 ofld_rxq->iq.intr_params = v;
5253 end_synchronized_op(sc, LOCK_HELD);
5258 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5260 struct vi_info *vi = arg1;
5261 struct adapter *sc = vi->pi->adapter;
5266 rc = sysctl_handle_int(oidp, &idx, 0, req);
5267 if (rc != 0 || req->newptr == NULL)
5270 if (idx < -1 || idx >= SGE_NCOUNTERS)
5273 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5278 if (vi->flags & VI_INIT_DONE)
5279 rc = EBUSY; /* cannot be changed once the queues are created */
5283 end_synchronized_op(sc, LOCK_HELD);
5288 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5290 struct vi_info *vi = arg1;
5291 struct adapter *sc = vi->pi->adapter;
5294 qsize = vi->qsize_rxq;
5296 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5297 if (rc != 0 || req->newptr == NULL)
5300 if (qsize < 128 || (qsize & 7))
5303 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5308 if (vi->flags & VI_INIT_DONE)
5309 rc = EBUSY; /* cannot be changed once the queues are created */
5311 vi->qsize_rxq = qsize;
5313 end_synchronized_op(sc, LOCK_HELD);
5318 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5320 struct vi_info *vi = arg1;
5321 struct adapter *sc = vi->pi->adapter;
5324 qsize = vi->qsize_txq;
5326 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5327 if (rc != 0 || req->newptr == NULL)
5330 if (qsize < 128 || qsize > 65536)
5333 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5338 if (vi->flags & VI_INIT_DONE)
5339 rc = EBUSY; /* cannot be changed once the queues are created */
5341 vi->qsize_txq = qsize;
5343 end_synchronized_op(sc, LOCK_HELD);
5348 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5350 struct port_info *pi = arg1;
5351 struct adapter *sc = pi->adapter;
5352 struct link_config *lc = &pi->link_cfg;
5355 if (req->newptr == NULL) {
5357 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5359 rc = sysctl_wire_old_buffer(req, 0);
5363 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5367 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5368 rc = sbuf_finish(sb);
5374 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5377 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5383 if (s[0] < '0' || s[0] > '9')
5384 return (EINVAL); /* not a number */
5386 if (n & ~(PAUSE_TX | PAUSE_RX))
5387 return (EINVAL); /* some other bit is set too */
5389 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5393 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5394 int link_ok = lc->link_ok;
5396 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5397 lc->requested_fc |= n;
5398 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5399 lc->link_ok = link_ok; /* restore */
5401 end_synchronized_op(sc, 0);
5408 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5410 struct adapter *sc = arg1;
5414 val = t4_read_reg64(sc, reg);
5416 return (sysctl_handle_64(oidp, &val, 0, req));
5420 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5422 struct adapter *sc = arg1;
5424 uint32_t param, val;
5426 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5429 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5430 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5431 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5432 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5433 end_synchronized_op(sc, 0);
5437 /* unknown is returned as 0 but we display -1 in that case */
5438 t = val == 0 ? -1 : val;
5440 rc = sysctl_handle_int(oidp, &t, 0, req);
5446 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5448 struct adapter *sc = arg1;
5451 uint16_t incr[NMTUS][NCCTRL_WIN];
5452 static const char *dec_fac[] = {
5453 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5457 rc = sysctl_wire_old_buffer(req, 0);
5461 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5465 t4_read_cong_tbl(sc, incr);
5467 for (i = 0; i < NCCTRL_WIN; ++i) {
5468 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5469 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5470 incr[5][i], incr[6][i], incr[7][i]);
5471 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5472 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5473 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5474 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5477 rc = sbuf_finish(sb);
5483 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5484 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
5485 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5486 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
5490 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5492 struct adapter *sc = arg1;
5494 int rc, i, n, qid = arg2;
5497 u_int cim_num_obq = sc->chip_params->cim_num_obq;
5499 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5500 ("%s: bad qid %d\n", __func__, qid));
5502 if (qid < CIM_NUM_IBQ) {
5505 n = 4 * CIM_IBQ_SIZE;
5506 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5507 rc = t4_read_cim_ibq(sc, qid, buf, n);
5509 /* outbound queue */
5512 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5513 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5514 rc = t4_read_cim_obq(sc, qid, buf, n);
5521 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
5523 rc = sysctl_wire_old_buffer(req, 0);
5527 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5533 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5534 for (i = 0, p = buf; i < n; i += 16, p += 4)
5535 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5538 rc = sbuf_finish(sb);
5546 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5548 struct adapter *sc = arg1;
5554 MPASS(chip_id(sc) <= CHELSIO_T5);
5556 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5560 rc = sysctl_wire_old_buffer(req, 0);
5564 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5568 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5571 rc = -t4_cim_read_la(sc, buf, NULL);
5575 sbuf_printf(sb, "Status Data PC%s",
5576 cfg & F_UPDBGLACAPTPCONLY ? "" :
5577 " LS0Stat LS0Addr LS0Data");
5579 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
5580 if (cfg & F_UPDBGLACAPTPCONLY) {
5581 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5583 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5584 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5585 p[4] & 0xff, p[5] >> 8);
5586 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5587 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5588 p[1] & 0xf, p[2] >> 4);
5591 "\n %02x %x%07x %x%07x %08x %08x "
5593 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5594 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5599 rc = sbuf_finish(sb);
5607 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
5609 struct adapter *sc = arg1;
5615 MPASS(chip_id(sc) > CHELSIO_T5);
5617 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5621 rc = sysctl_wire_old_buffer(req, 0);
5625 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5629 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5632 rc = -t4_cim_read_la(sc, buf, NULL);
5636 sbuf_printf(sb, "Status Inst Data PC%s",
5637 cfg & F_UPDBGLACAPTPCONLY ? "" :
5638 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
5640 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
5641 if (cfg & F_UPDBGLACAPTPCONLY) {
5642 sbuf_printf(sb, "\n %02x %08x %08x %08x",
5643 p[3] & 0xff, p[2], p[1], p[0]);
5644 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
5645 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
5646 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
5647 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
5648 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
5649 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
5652 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
5653 "%08x %08x %08x %08x %08x %08x",
5654 (p[9] >> 16) & 0xff,
5655 p[9] & 0xffff, p[8] >> 16,
5656 p[8] & 0xffff, p[7] >> 16,
5657 p[7] & 0xffff, p[6] >> 16,
5658 p[2], p[1], p[0], p[5], p[4], p[3]);
5662 rc = sbuf_finish(sb);
5670 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5672 struct adapter *sc = arg1;
5678 rc = sysctl_wire_old_buffer(req, 0);
5682 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5686 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5689 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5692 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5693 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5697 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
5698 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5699 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
5700 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5701 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5702 (p[1] >> 2) | ((p[2] & 3) << 30),
5703 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5707 rc = sbuf_finish(sb);
5714 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5716 struct adapter *sc = arg1;
5722 rc = sysctl_wire_old_buffer(req, 0);
5726 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5730 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5733 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5736 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
5737 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5738 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
5739 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5740 p[4], p[3], p[2], p[1], p[0]);
5743 sbuf_printf(sb, "\n\nCntl ID Data");
5744 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5745 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
5746 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5749 rc = sbuf_finish(sb);
5756 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5758 struct adapter *sc = arg1;
5761 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5762 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5763 uint16_t thres[CIM_NUM_IBQ];
5764 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5765 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5766 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5768 cim_num_obq = sc->chip_params->cim_num_obq;
5770 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5771 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5773 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5774 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5776 nq = CIM_NUM_IBQ + cim_num_obq;
5778 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5780 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5784 t4_read_cimq_cfg(sc, base, size, thres);
5786 rc = sysctl_wire_old_buffer(req, 0);
5790 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5795 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
5797 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5798 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
5799 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5800 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5801 G_QUEREMFLITS(p[2]) * 16);
5802 for ( ; i < nq; i++, p += 4, wr += 2)
5803 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
5804 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
5805 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5806 G_QUEREMFLITS(p[2]) * 16);
5808 rc = sbuf_finish(sb);
5815 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
5817 struct adapter *sc = arg1;
5820 struct tp_cpl_stats stats;
5822 rc = sysctl_wire_old_buffer(req, 0);
5826 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5830 mtx_lock(&sc->reg_lock);
5831 t4_tp_get_cpl_stats(sc, &stats);
5832 mtx_unlock(&sc->reg_lock);
5834 if (sc->chip_params->nchan > 2) {
5835 sbuf_printf(sb, " channel 0 channel 1"
5836 " channel 2 channel 3");
5837 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
5838 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
5839 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
5840 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
5842 sbuf_printf(sb, " channel 0 channel 1");
5843 sbuf_printf(sb, "\nCPL requests: %10u %10u",
5844 stats.req[0], stats.req[1]);
5845 sbuf_printf(sb, "\nCPL responses: %10u %10u",
5846 stats.rsp[0], stats.rsp[1]);
5849 rc = sbuf_finish(sb);
5856 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
5858 struct adapter *sc = arg1;
5861 struct tp_usm_stats stats;
5863 rc = sysctl_wire_old_buffer(req, 0);
5867 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5871 t4_get_usm_stats(sc, &stats);
5873 sbuf_printf(sb, "Frames: %u\n", stats.frames);
5874 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
5875 sbuf_printf(sb, "Drops: %u", stats.drops);
5877 rc = sbuf_finish(sb);
5883 static const char * const devlog_level_strings[] = {
5884 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
5885 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
5886 [FW_DEVLOG_LEVEL_ERR] = "ERR",
5887 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
5888 [FW_DEVLOG_LEVEL_INFO] = "INFO",
5889 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
5892 static const char * const devlog_facility_strings[] = {
5893 [FW_DEVLOG_FACILITY_CORE] = "CORE",
5894 [FW_DEVLOG_FACILITY_CF] = "CF",
5895 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
5896 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
5897 [FW_DEVLOG_FACILITY_RES] = "RES",
5898 [FW_DEVLOG_FACILITY_HW] = "HW",
5899 [FW_DEVLOG_FACILITY_FLR] = "FLR",
5900 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
5901 [FW_DEVLOG_FACILITY_PHY] = "PHY",
5902 [FW_DEVLOG_FACILITY_MAC] = "MAC",
5903 [FW_DEVLOG_FACILITY_PORT] = "PORT",
5904 [FW_DEVLOG_FACILITY_VI] = "VI",
5905 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
5906 [FW_DEVLOG_FACILITY_ACL] = "ACL",
5907 [FW_DEVLOG_FACILITY_TM] = "TM",
5908 [FW_DEVLOG_FACILITY_QFC] = "QFC",
5909 [FW_DEVLOG_FACILITY_DCB] = "DCB",
5910 [FW_DEVLOG_FACILITY_ETH] = "ETH",
5911 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
5912 [FW_DEVLOG_FACILITY_RI] = "RI",
5913 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
5914 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
5915 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
5916 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
5917 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
5921 sysctl_devlog(SYSCTL_HANDLER_ARGS)
5923 struct adapter *sc = arg1;
5924 struct devlog_params *dparams = &sc->params.devlog;
5925 struct fw_devlog_e *buf, *e;
5926 int i, j, rc, nentries, first = 0;
5928 uint64_t ftstamp = UINT64_MAX;
5930 if (dparams->addr == 0)
5933 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
5937 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
5941 nentries = dparams->size / sizeof(struct fw_devlog_e);
5942 for (i = 0; i < nentries; i++) {
5945 if (e->timestamp == 0)
5948 e->timestamp = be64toh(e->timestamp);
5949 e->seqno = be32toh(e->seqno);
5950 for (j = 0; j < 8; j++)
5951 e->params[j] = be32toh(e->params[j]);
5953 if (e->timestamp < ftstamp) {
5954 ftstamp = e->timestamp;
5959 if (buf[first].timestamp == 0)
5960 goto done; /* nothing in the log */
5962 rc = sysctl_wire_old_buffer(req, 0);
5966 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5971 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
5972 "Seq#", "Tstamp", "Level", "Facility", "Message");
5977 if (e->timestamp == 0)
5980 sbuf_printf(sb, "%10d %15ju %8s %8s ",
5981 e->seqno, e->timestamp,
5982 (e->level < nitems(devlog_level_strings) ?
5983 devlog_level_strings[e->level] : "UNKNOWN"),
5984 (e->facility < nitems(devlog_facility_strings) ?
5985 devlog_facility_strings[e->facility] : "UNKNOWN"));
5986 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
5987 e->params[2], e->params[3], e->params[4],
5988 e->params[5], e->params[6], e->params[7]);
5990 if (++i == nentries)
5992 } while (i != first);
5994 rc = sbuf_finish(sb);
6002 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
6004 struct adapter *sc = arg1;
6007 struct tp_fcoe_stats stats[MAX_NCHAN];
6008 int i, nchan = sc->chip_params->nchan;
6010 rc = sysctl_wire_old_buffer(req, 0);
6014 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6018 for (i = 0; i < nchan; i++)
6019 t4_get_fcoe_stats(sc, i, &stats[i]);
6022 sbuf_printf(sb, " channel 0 channel 1"
6023 " channel 2 channel 3");
6024 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
6025 stats[0].octets_ddp, stats[1].octets_ddp,
6026 stats[2].octets_ddp, stats[3].octets_ddp);
6027 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
6028 stats[0].frames_ddp, stats[1].frames_ddp,
6029 stats[2].frames_ddp, stats[3].frames_ddp);
6030 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
6031 stats[0].frames_drop, stats[1].frames_drop,
6032 stats[2].frames_drop, stats[3].frames_drop);
6034 sbuf_printf(sb, " channel 0 channel 1");
6035 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
6036 stats[0].octets_ddp, stats[1].octets_ddp);
6037 sbuf_printf(sb, "\nframesDDP: %16u %16u",
6038 stats[0].frames_ddp, stats[1].frames_ddp);
6039 sbuf_printf(sb, "\nframesDrop: %16u %16u",
6040 stats[0].frames_drop, stats[1].frames_drop);
6043 rc = sbuf_finish(sb);
6050 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6052 struct adapter *sc = arg1;
6055 unsigned int map, kbps, ipg, mode;
6056 unsigned int pace_tab[NTX_SCHED];
6058 rc = sysctl_wire_old_buffer(req, 0);
6062 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6066 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6067 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6068 t4_read_pace_tbl(sc, pace_tab);
6070 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6071 "Class IPG (0.1 ns) Flow IPG (us)");
6073 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6074 t4_get_tx_sched(sc, i, &kbps, &ipg);
6075 sbuf_printf(sb, "\n %u %-5s %u ", i,
6076 (mode & (1 << i)) ? "flow" : "class", map & 3);
6078 sbuf_printf(sb, "%9u ", kbps);
6080 sbuf_printf(sb, " disabled ");
6083 sbuf_printf(sb, "%13u ", ipg);
6085 sbuf_printf(sb, " disabled ");
6088 sbuf_printf(sb, "%10u", pace_tab[i]);
6090 sbuf_printf(sb, " disabled");
6093 rc = sbuf_finish(sb);
6100 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6102 struct adapter *sc = arg1;
6106 struct lb_port_stats s[2];
6107 static const char *stat_name[] = {
6108 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6109 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6110 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6111 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6112 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6113 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6114 "BG2FramesTrunc:", "BG3FramesTrunc:"
6117 rc = sysctl_wire_old_buffer(req, 0);
6121 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6125 memset(s, 0, sizeof(s));
6127 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6128 t4_get_lb_stats(sc, i, &s[0]);
6129 t4_get_lb_stats(sc, i + 1, &s[1]);
6133 sbuf_printf(sb, "%s Loopback %u"
6134 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6136 for (j = 0; j < nitems(stat_name); j++)
6137 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6141 rc = sbuf_finish(sb);
6148 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6151 struct port_info *pi = arg1;
6154 rc = sysctl_wire_old_buffer(req, 0);
6157 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6161 if (pi->linkdnrc < 0)
6162 sbuf_printf(sb, "n/a");
6164 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc));
6166 rc = sbuf_finish(sb);
6179 mem_desc_cmp(const void *a, const void *b)
6181 return ((const struct mem_desc *)a)->base -
6182 ((const struct mem_desc *)b)->base;
6186 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6194 size = to - from + 1;
6198 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6199 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6203 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6205 struct adapter *sc = arg1;
6208 uint32_t lo, hi, used, alloc;
6209 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6210 static const char *region[] = {
6211 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6212 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6213 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6214 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6215 "RQUDP region:", "PBL region:", "TXPBL region:",
6216 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6219 struct mem_desc avail[4];
6220 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6221 struct mem_desc *md = mem;
6223 rc = sysctl_wire_old_buffer(req, 0);
6227 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6231 for (i = 0; i < nitems(mem); i++) {
6236 /* Find and sort the populated memory ranges */
6238 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6239 if (lo & F_EDRAM0_ENABLE) {
6240 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6241 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6242 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6246 if (lo & F_EDRAM1_ENABLE) {
6247 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6248 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6249 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6253 if (lo & F_EXT_MEM_ENABLE) {
6254 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6255 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6256 avail[i].limit = avail[i].base +
6257 (G_EXT_MEM_SIZE(hi) << 20);
6258 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6261 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6262 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6263 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6264 avail[i].limit = avail[i].base +
6265 (G_EXT_MEM1_SIZE(hi) << 20);
6269 if (!i) /* no memory available */
6271 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6273 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6274 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6275 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6276 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6277 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6278 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6279 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6280 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6281 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6283 /* the next few have explicit upper bounds */
6284 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6285 md->limit = md->base - 1 +
6286 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6287 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6290 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6291 md->limit = md->base - 1 +
6292 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6293 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6296 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6297 if (chip_id(sc) <= CHELSIO_T5)
6298 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6300 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6304 md->idx = nitems(region); /* hide it */
6308 #define ulp_region(reg) \
6309 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6310 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6312 ulp_region(RX_ISCSI);
6313 ulp_region(RX_TDDP);
6315 ulp_region(RX_STAG);
6317 ulp_region(RX_RQUDP);
6323 md->idx = nitems(region);
6326 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6327 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6330 if (sge_ctrl & F_VFIFO_ENABLE)
6331 size = G_DBVFIFO_SIZE(fifo_size);
6333 size = G_T6_DBVFIFO_SIZE(fifo_size);
6336 md->base = G_BASEADDR(t4_read_reg(sc,
6337 A_SGE_DBVFIFO_BADDR));
6338 md->limit = md->base + (size << 2) - 1;
6343 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6346 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6350 md->base = sc->vres.ocq.start;
6351 if (sc->vres.ocq.size)
6352 md->limit = md->base + sc->vres.ocq.size - 1;
6354 md->idx = nitems(region); /* hide it */
6357 /* add any address-space holes, there can be up to 3 */
6358 for (n = 0; n < i - 1; n++)
6359 if (avail[n].limit < avail[n + 1].base)
6360 (md++)->base = avail[n].limit;
6362 (md++)->base = avail[n].limit;
6365 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6367 for (lo = 0; lo < i; lo++)
6368 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6369 avail[lo].limit - 1);
6371 sbuf_printf(sb, "\n");
6372 for (i = 0; i < n; i++) {
6373 if (mem[i].idx >= nitems(region))
6374 continue; /* skip holes */
6376 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6377 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6381 sbuf_printf(sb, "\n");
6382 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6383 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6384 mem_region_show(sb, "uP RAM:", lo, hi);
6386 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6387 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6388 mem_region_show(sb, "uP Extmem2:", lo, hi);
6390 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6391 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6393 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6394 (lo & F_PMRXNUMCHN) ? 2 : 1);
6396 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6397 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6398 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6400 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6401 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6402 sbuf_printf(sb, "%u p-structs\n",
6403 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6405 for (i = 0; i < 4; i++) {
6406 if (chip_id(sc) > CHELSIO_T5)
6407 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6409 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6411 used = G_T5_USED(lo);
6412 alloc = G_T5_ALLOC(lo);
6415 alloc = G_ALLOC(lo);
6417 /* For T6 these are MAC buffer groups */
6418 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6421 for (i = 0; i < sc->chip_params->nchan; i++) {
6422 if (chip_id(sc) > CHELSIO_T5)
6423 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6425 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6427 used = G_T5_USED(lo);
6428 alloc = G_T5_ALLOC(lo);
6431 alloc = G_ALLOC(lo);
6433 /* For T6 these are MAC buffer groups */
6435 "\nLoopback %d using %u pages out of %u allocated",
6439 rc = sbuf_finish(sb);
6446 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6450 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6454 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6456 struct adapter *sc = arg1;
6460 MPASS(chip_id(sc) <= CHELSIO_T5);
6462 rc = sysctl_wire_old_buffer(req, 0);
6466 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6471 "Idx Ethernet address Mask Vld Ports PF"
6472 " VF Replication P0 P1 P2 P3 ML");
6473 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6474 uint64_t tcamx, tcamy, mask;
6475 uint32_t cls_lo, cls_hi;
6476 uint8_t addr[ETHER_ADDR_LEN];
6478 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6479 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6482 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6483 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6484 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6485 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6486 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
6487 addr[3], addr[4], addr[5], (uintmax_t)mask,
6488 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6489 G_PORTMAP(cls_hi), G_PF(cls_lo),
6490 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6492 if (cls_lo & F_REPLICATE) {
6493 struct fw_ldst_cmd ldst_cmd;
6495 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6496 ldst_cmd.op_to_addrspace =
6497 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6498 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6499 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6500 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6501 ldst_cmd.u.mps.rplc.fid_idx =
6502 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6503 V_FW_LDST_CMD_IDX(i));
6505 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6509 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6510 sizeof(ldst_cmd), &ldst_cmd);
6511 end_synchronized_op(sc, 0);
6514 sbuf_printf(sb, "%36d", rc);
6517 sbuf_printf(sb, " %08x %08x %08x %08x",
6518 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6519 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6520 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6521 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6524 sbuf_printf(sb, "%36s", "");
6526 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6527 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6528 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6532 (void) sbuf_finish(sb);
6534 rc = sbuf_finish(sb);
6541 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
6543 struct adapter *sc = arg1;
6547 MPASS(chip_id(sc) > CHELSIO_T5);
6549 rc = sysctl_wire_old_buffer(req, 0);
6553 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6557 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
6558 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
6560 " P0 P1 P2 P3 ML\n");
6562 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6563 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
6565 uint64_t tcamx, tcamy, val, mask;
6566 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
6567 uint8_t addr[ETHER_ADDR_LEN];
6569 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
6571 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
6573 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
6574 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6575 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6576 tcamy = G_DMACH(val) << 32;
6577 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6578 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6579 lookup_type = G_DATALKPTYPE(data2);
6580 port_num = G_DATAPORTNUM(data2);
6581 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6582 /* Inner header VNI */
6583 vniy = ((data2 & F_DATAVIDH2) << 23) |
6584 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6585 dip_hit = data2 & F_DATADIPHIT;
6590 vlan_vld = data2 & F_DATAVIDH2;
6591 ivlan = G_VIDL(val);
6594 ctl |= V_CTLXYBITSEL(1);
6595 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6596 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6597 tcamx = G_DMACH(val) << 32;
6598 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6599 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6600 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6601 /* Inner header VNI mask */
6602 vnix = ((data2 & F_DATAVIDH2) << 23) |
6603 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6609 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6611 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6612 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6614 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6615 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6616 "%012jx %06x %06x - - %3c"
6617 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
6618 addr[1], addr[2], addr[3], addr[4], addr[5],
6619 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
6620 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6621 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6622 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6624 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6625 "%012jx - - ", i, addr[0], addr[1],
6626 addr[2], addr[3], addr[4], addr[5],
6630 sbuf_printf(sb, "%4u Y ", ivlan);
6632 sbuf_printf(sb, " - N ");
6634 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
6635 lookup_type ? 'I' : 'O', port_num,
6636 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6637 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6638 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6642 if (cls_lo & F_T6_REPLICATE) {
6643 struct fw_ldst_cmd ldst_cmd;
6645 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6646 ldst_cmd.op_to_addrspace =
6647 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6648 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6649 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6650 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6651 ldst_cmd.u.mps.rplc.fid_idx =
6652 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6653 V_FW_LDST_CMD_IDX(i));
6655 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6659 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6660 sizeof(ldst_cmd), &ldst_cmd);
6661 end_synchronized_op(sc, 0);
6664 sbuf_printf(sb, "%72d", rc);
6667 sbuf_printf(sb, " %08x %08x %08x %08x"
6668 " %08x %08x %08x %08x",
6669 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
6670 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
6671 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
6672 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
6673 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6674 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6675 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6676 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6679 sbuf_printf(sb, "%72s", "");
6681 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
6682 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
6683 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
6684 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
6688 (void) sbuf_finish(sb);
6690 rc = sbuf_finish(sb);
6697 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
6699 struct adapter *sc = arg1;
6702 uint16_t mtus[NMTUS];
6704 rc = sysctl_wire_old_buffer(req, 0);
6708 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6712 t4_read_mtu_tbl(sc, mtus, NULL);
6714 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
6715 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
6716 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
6717 mtus[14], mtus[15]);
6719 rc = sbuf_finish(sb);
6726 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
6728 struct adapter *sc = arg1;
6731 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
6732 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
6733 static const char *tx_stats[MAX_PM_NSTATS] = {
6734 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
6735 "Tx FIFO wait", NULL, "Tx latency"
6737 static const char *rx_stats[MAX_PM_NSTATS] = {
6738 "Read:", "Write bypass:", "Write mem:", "Flush:",
6739 "Rx FIFO wait", NULL, "Rx latency"
6742 rc = sysctl_wire_old_buffer(req, 0);
6746 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6750 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
6751 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
6753 sbuf_printf(sb, " Tx pcmds Tx bytes");
6754 for (i = 0; i < 4; i++) {
6755 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6759 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
6760 for (i = 0; i < 4; i++) {
6761 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6765 if (chip_id(sc) > CHELSIO_T5) {
6767 "\n Total wait Total occupancy");
6768 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6770 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6774 MPASS(i < nitems(tx_stats));
6777 "\n Reads Total wait");
6778 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6780 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6784 rc = sbuf_finish(sb);
6791 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
6793 struct adapter *sc = arg1;
6796 struct tp_rdma_stats stats;
6798 rc = sysctl_wire_old_buffer(req, 0);
6802 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6806 mtx_lock(&sc->reg_lock);
6807 t4_tp_get_rdma_stats(sc, &stats);
6808 mtx_unlock(&sc->reg_lock);
6810 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
6811 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
6813 rc = sbuf_finish(sb);
6820 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
6822 struct adapter *sc = arg1;
6825 struct tp_tcp_stats v4, v6;
6827 rc = sysctl_wire_old_buffer(req, 0);
6831 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6835 mtx_lock(&sc->reg_lock);
6836 t4_tp_get_tcp_stats(sc, &v4, &v6);
6837 mtx_unlock(&sc->reg_lock);
6841 sbuf_printf(sb, "OutRsts: %20u %20u\n",
6842 v4.tcp_out_rsts, v6.tcp_out_rsts);
6843 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
6844 v4.tcp_in_segs, v6.tcp_in_segs);
6845 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
6846 v4.tcp_out_segs, v6.tcp_out_segs);
6847 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
6848 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
6850 rc = sbuf_finish(sb);
6857 sysctl_tids(SYSCTL_HANDLER_ARGS)
6859 struct adapter *sc = arg1;
6862 struct tid_info *t = &sc->tids;
6864 rc = sysctl_wire_old_buffer(req, 0);
6868 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6873 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
6878 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6879 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
6882 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
6883 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6886 sbuf_printf(sb, "TID range: %u-%u",
6887 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6891 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
6892 sbuf_printf(sb, ", in use: %u\n",
6893 atomic_load_acq_int(&t->tids_in_use));
6897 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
6898 t->stid_base + t->nstids - 1, t->stids_in_use);
6902 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
6903 t->ftid_base + t->nftids - 1);
6907 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
6908 t->etid_base + t->netids - 1);
6911 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
6912 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
6913 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
6915 rc = sbuf_finish(sb);
6922 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
6924 struct adapter *sc = arg1;
6927 struct tp_err_stats stats;
6929 rc = sysctl_wire_old_buffer(req, 0);
6933 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6937 mtx_lock(&sc->reg_lock);
6938 t4_tp_get_err_stats(sc, &stats);
6939 mtx_unlock(&sc->reg_lock);
6941 if (sc->chip_params->nchan > 2) {
6942 sbuf_printf(sb, " channel 0 channel 1"
6943 " channel 2 channel 3\n");
6944 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
6945 stats.mac_in_errs[0], stats.mac_in_errs[1],
6946 stats.mac_in_errs[2], stats.mac_in_errs[3]);
6947 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
6948 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
6949 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
6950 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
6951 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
6952 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
6953 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
6954 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
6955 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
6956 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
6957 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
6958 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
6959 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
6960 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
6961 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
6962 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
6963 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
6964 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
6965 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
6966 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
6967 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
6969 sbuf_printf(sb, " channel 0 channel 1\n");
6970 sbuf_printf(sb, "macInErrs: %10u %10u\n",
6971 stats.mac_in_errs[0], stats.mac_in_errs[1]);
6972 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
6973 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
6974 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
6975 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
6976 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
6977 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
6978 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
6979 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
6980 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
6981 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
6982 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
6983 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
6984 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
6985 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
6988 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
6989 stats.ofld_no_neigh, stats.ofld_cong_defer);
6991 rc = sbuf_finish(sb);
6998 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
7000 struct adapter *sc = arg1;
7001 struct tp_params *tpp = &sc->params.tp;
7005 mask = tpp->la_mask >> 16;
7006 rc = sysctl_handle_int(oidp, &mask, 0, req);
7007 if (rc != 0 || req->newptr == NULL)
7011 tpp->la_mask = mask << 16;
7012 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
7024 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
7030 uint64_t mask = (1ULL << f->width) - 1;
7031 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
7032 ((uintmax_t)v >> f->start) & mask);
7034 if (line_size + len >= 79) {
7036 sbuf_printf(sb, "\n ");
7038 sbuf_printf(sb, "%s ", buf);
7039 line_size += len + 1;
7042 sbuf_printf(sb, "\n");
7045 static const struct field_desc tp_la0[] = {
7046 { "RcfOpCodeOut", 60, 4 },
7048 { "WcfState", 52, 4 },
7049 { "RcfOpcSrcOut", 50, 2 },
7050 { "CRxError", 49, 1 },
7051 { "ERxError", 48, 1 },
7052 { "SanityFailed", 47, 1 },
7053 { "SpuriousMsg", 46, 1 },
7054 { "FlushInputMsg", 45, 1 },
7055 { "FlushInputCpl", 44, 1 },
7056 { "RssUpBit", 43, 1 },
7057 { "RssFilterHit", 42, 1 },
7059 { "InitTcb", 31, 1 },
7060 { "LineNumber", 24, 7 },
7062 { "EdataOut", 22, 1 },
7064 { "CdataOut", 20, 1 },
7065 { "EreadPdu", 19, 1 },
7066 { "CreadPdu", 18, 1 },
7067 { "TunnelPkt", 17, 1 },
7068 { "RcfPeerFin", 16, 1 },
7069 { "RcfReasonOut", 12, 4 },
7070 { "TxCchannel", 10, 2 },
7071 { "RcfTxChannel", 8, 2 },
7072 { "RxEchannel", 6, 2 },
7073 { "RcfRxChannel", 5, 1 },
7074 { "RcfDataOutSrdy", 4, 1 },
7076 { "RxOoDvld", 2, 1 },
7077 { "RxCongestion", 1, 1 },
7078 { "TxCongestion", 0, 1 },
7082 static const struct field_desc tp_la1[] = {
7083 { "CplCmdIn", 56, 8 },
7084 { "CplCmdOut", 48, 8 },
7085 { "ESynOut", 47, 1 },
7086 { "EAckOut", 46, 1 },
7087 { "EFinOut", 45, 1 },
7088 { "ERstOut", 44, 1 },
7093 { "DataIn", 39, 1 },
7094 { "DataInVld", 38, 1 },
7096 { "RxBufEmpty", 36, 1 },
7098 { "RxFbCongestion", 34, 1 },
7099 { "TxFbCongestion", 33, 1 },
7100 { "TxPktSumSrdy", 32, 1 },
7101 { "RcfUlpType", 28, 4 },
7103 { "Ebypass", 26, 1 },
7105 { "Static0", 24, 1 },
7107 { "Cbypass", 22, 1 },
7109 { "CPktOut", 20, 1 },
7110 { "RxPagePoolFull", 18, 2 },
7111 { "RxLpbkPkt", 17, 1 },
7112 { "TxLpbkPkt", 16, 1 },
7113 { "RxVfValid", 15, 1 },
7114 { "SynLearned", 14, 1 },
7115 { "SetDelEntry", 13, 1 },
7116 { "SetInvEntry", 12, 1 },
7117 { "CpcmdDvld", 11, 1 },
7118 { "CpcmdSave", 10, 1 },
7119 { "RxPstructsFull", 8, 2 },
7120 { "EpcmdDvld", 7, 1 },
7121 { "EpcmdFlush", 6, 1 },
7122 { "EpcmdTrimPrefix", 5, 1 },
7123 { "EpcmdTrimPostfix", 4, 1 },
7124 { "ERssIp4Pkt", 3, 1 },
7125 { "ERssIp6Pkt", 2, 1 },
7126 { "ERssTcpUdpPkt", 1, 1 },
7127 { "ERssFceFipPkt", 0, 1 },
7131 static const struct field_desc tp_la2[] = {
7132 { "CplCmdIn", 56, 8 },
7133 { "MpsVfVld", 55, 1 },
7140 { "DataIn", 39, 1 },
7141 { "DataInVld", 38, 1 },
7143 { "RxBufEmpty", 36, 1 },
7145 { "RxFbCongestion", 34, 1 },
7146 { "TxFbCongestion", 33, 1 },
7147 { "TxPktSumSrdy", 32, 1 },
7148 { "RcfUlpType", 28, 4 },
7150 { "Ebypass", 26, 1 },
7152 { "Static0", 24, 1 },
7154 { "Cbypass", 22, 1 },
7156 { "CPktOut", 20, 1 },
7157 { "RxPagePoolFull", 18, 2 },
7158 { "RxLpbkPkt", 17, 1 },
7159 { "TxLpbkPkt", 16, 1 },
7160 { "RxVfValid", 15, 1 },
7161 { "SynLearned", 14, 1 },
7162 { "SetDelEntry", 13, 1 },
7163 { "SetInvEntry", 12, 1 },
7164 { "CpcmdDvld", 11, 1 },
7165 { "CpcmdSave", 10, 1 },
7166 { "RxPstructsFull", 8, 2 },
7167 { "EpcmdDvld", 7, 1 },
7168 { "EpcmdFlush", 6, 1 },
7169 { "EpcmdTrimPrefix", 5, 1 },
7170 { "EpcmdTrimPostfix", 4, 1 },
7171 { "ERssIp4Pkt", 3, 1 },
7172 { "ERssIp6Pkt", 2, 1 },
7173 { "ERssTcpUdpPkt", 1, 1 },
7174 { "ERssFceFipPkt", 0, 1 },
7179 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7182 field_desc_show(sb, *p, tp_la0);
7186 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7190 sbuf_printf(sb, "\n");
7191 field_desc_show(sb, p[0], tp_la0);
7192 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7193 field_desc_show(sb, p[1], tp_la0);
7197 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7201 sbuf_printf(sb, "\n");
7202 field_desc_show(sb, p[0], tp_la0);
7203 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7204 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7208 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7210 struct adapter *sc = arg1;
7215 void (*show_func)(struct sbuf *, uint64_t *, int);
7217 rc = sysctl_wire_old_buffer(req, 0);
7221 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7225 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7227 t4_tp_read_la(sc, buf, NULL);
7230 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7233 show_func = tp_la_show2;
7237 show_func = tp_la_show3;
7241 show_func = tp_la_show;
7244 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7245 (*show_func)(sb, p, i);
7247 rc = sbuf_finish(sb);
7254 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7256 struct adapter *sc = arg1;
7259 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7261 rc = sysctl_wire_old_buffer(req, 0);
7265 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7269 t4_get_chan_txrate(sc, nrate, orate);
7271 if (sc->chip_params->nchan > 2) {
7272 sbuf_printf(sb, " channel 0 channel 1"
7273 " channel 2 channel 3\n");
7274 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7275 nrate[0], nrate[1], nrate[2], nrate[3]);
7276 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7277 orate[0], orate[1], orate[2], orate[3]);
7279 sbuf_printf(sb, " channel 0 channel 1\n");
7280 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7281 nrate[0], nrate[1]);
7282 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7283 orate[0], orate[1]);
7286 rc = sbuf_finish(sb);
7293 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7295 struct adapter *sc = arg1;
7300 rc = sysctl_wire_old_buffer(req, 0);
7304 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7308 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7311 t4_ulprx_read_la(sc, buf);
7314 sbuf_printf(sb, " Pcmd Type Message"
7316 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7317 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7318 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7321 rc = sbuf_finish(sb);
7328 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7330 struct adapter *sc = arg1;
7334 rc = sysctl_wire_old_buffer(req, 0);
7338 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7342 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7343 if (G_STATSOURCE_T5(v) == 7) {
7344 if (G_STATMODE(v) == 0) {
7345 sbuf_printf(sb, "total %d, incomplete %d",
7346 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7347 t4_read_reg(sc, A_SGE_STAT_MATCH));
7348 } else if (G_STATMODE(v) == 1) {
7349 sbuf_printf(sb, "total %d, data overflow %d",
7350 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7351 t4_read_reg(sc, A_SGE_STAT_MATCH));
7354 rc = sbuf_finish(sb);
7361 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
7363 struct adapter *sc = arg1;
7364 struct tx_sched_class *tc;
7365 struct t4_sched_class_params p;
7367 int i, rc, port_id, flags, mbps, gbps;
7369 rc = sysctl_wire_old_buffer(req, 0);
7373 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7377 port_id = arg2 >> 16;
7378 MPASS(port_id < sc->params.nports);
7379 MPASS(sc->port[port_id] != NULL);
7381 MPASS(i < sc->chip_params->nsched_cls);
7382 tc = &sc->port[port_id]->tc[i];
7384 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7390 end_synchronized_op(sc, LOCK_HELD);
7392 if ((flags & TX_SC_OK) == 0) {
7393 sbuf_printf(sb, "none");
7397 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) {
7398 sbuf_printf(sb, "cl-wrr weight %u", p.weight);
7400 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL)
7401 sbuf_printf(sb, "cl-rl");
7402 else if (p.level == SCHED_CLASS_LEVEL_CH_RL)
7403 sbuf_printf(sb, "ch-rl");
7409 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) {
7410 /* XXX: top speed or actual link speed? */
7411 gbps = port_top_speed(sc->port[port_id]);
7412 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps);
7414 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) {
7415 switch (p.rateunit) {
7416 case SCHED_CLASS_RATEUNIT_BITS:
7417 mbps = p.maxrate / 1000;
7418 gbps = p.maxrate / 1000000;
7419 if (p.maxrate == gbps * 1000000)
7420 sbuf_printf(sb, " %uGbps", gbps);
7421 else if (p.maxrate == mbps * 1000)
7422 sbuf_printf(sb, " %uMbps", mbps);
7424 sbuf_printf(sb, " %uKbps", p.maxrate);
7426 case SCHED_CLASS_RATEUNIT_PKTS:
7427 sbuf_printf(sb, " %upps", p.maxrate);
7436 case SCHED_CLASS_MODE_CLASS:
7437 sbuf_printf(sb, " aggregate");
7439 case SCHED_CLASS_MODE_FLOW:
7440 sbuf_printf(sb, " per-flow");
7449 rc = sbuf_finish(sb);
7458 unit_conv(char *buf, size_t len, u_int val, u_int factor)
7460 u_int rem = val % factor;
7463 snprintf(buf, len, "%u", val / factor);
7465 while (rem % 10 == 0)
7467 snprintf(buf, len, "%u.%u", val / factor, rem);
7472 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
7474 struct adapter *sc = arg1;
7477 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7479 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7483 re = G_TIMERRESOLUTION(res);
7486 /* TCP timestamp tick */
7487 re = G_TIMESTAMPRESOLUTION(res);
7491 re = G_DELAYEDACKRESOLUTION(res);
7497 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
7499 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
7503 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
7505 struct adapter *sc = arg1;
7506 u_int res, dack_re, v;
7507 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7509 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7510 dack_re = G_DELAYEDACKRESOLUTION(res);
7511 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
7513 return (sysctl_handle_int(oidp, &v, 0, req));
7517 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
7519 struct adapter *sc = arg1;
7522 u_long tp_tick_us, v;
7523 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7525 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
7526 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
7527 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT ||
7528 reg == A_TP_FINWAIT2_TIMER);
7530 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
7531 tp_tick_us = (cclk_ps << tre) / 1000000;
7533 if (reg == A_TP_INIT_SRTT)
7534 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
7536 v = tp_tick_us * t4_read_reg(sc, reg);
7538 return (sysctl_handle_long(oidp, &v, 0, req));
7543 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
7547 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
7548 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
7550 if (fconf & F_FRAGMENTATION)
7551 mode |= T4_FILTER_IP_FRAGMENT;
7553 if (fconf & F_MPSHITTYPE)
7554 mode |= T4_FILTER_MPS_HIT_TYPE;
7556 if (fconf & F_MACMATCH)
7557 mode |= T4_FILTER_MAC_IDX;
7559 if (fconf & F_ETHERTYPE)
7560 mode |= T4_FILTER_ETH_TYPE;
7562 if (fconf & F_PROTOCOL)
7563 mode |= T4_FILTER_IP_PROTO;
7566 mode |= T4_FILTER_IP_TOS;
7569 mode |= T4_FILTER_VLAN;
7571 if (fconf & F_VNIC_ID) {
7572 mode |= T4_FILTER_VNIC;
7574 mode |= T4_FILTER_IC_VNIC;
7578 mode |= T4_FILTER_PORT;
7581 mode |= T4_FILTER_FCoE;
7587 mode_to_fconf(uint32_t mode)
7591 if (mode & T4_FILTER_IP_FRAGMENT)
7592 fconf |= F_FRAGMENTATION;
7594 if (mode & T4_FILTER_MPS_HIT_TYPE)
7595 fconf |= F_MPSHITTYPE;
7597 if (mode & T4_FILTER_MAC_IDX)
7598 fconf |= F_MACMATCH;
7600 if (mode & T4_FILTER_ETH_TYPE)
7601 fconf |= F_ETHERTYPE;
7603 if (mode & T4_FILTER_IP_PROTO)
7604 fconf |= F_PROTOCOL;
7606 if (mode & T4_FILTER_IP_TOS)
7609 if (mode & T4_FILTER_VLAN)
7612 if (mode & T4_FILTER_VNIC)
7615 if (mode & T4_FILTER_PORT)
7618 if (mode & T4_FILTER_FCoE)
7625 mode_to_iconf(uint32_t mode)
7628 if (mode & T4_FILTER_IC_VNIC)
7633 static int check_fspec_against_fconf_iconf(struct adapter *sc,
7634 struct t4_filter_specification *fs)
7636 struct tp_params *tpp = &sc->params.tp;
7639 if (fs->val.frag || fs->mask.frag)
7640 fconf |= F_FRAGMENTATION;
7642 if (fs->val.matchtype || fs->mask.matchtype)
7643 fconf |= F_MPSHITTYPE;
7645 if (fs->val.macidx || fs->mask.macidx)
7646 fconf |= F_MACMATCH;
7648 if (fs->val.ethtype || fs->mask.ethtype)
7649 fconf |= F_ETHERTYPE;
7651 if (fs->val.proto || fs->mask.proto)
7652 fconf |= F_PROTOCOL;
7654 if (fs->val.tos || fs->mask.tos)
7657 if (fs->val.vlan_vld || fs->mask.vlan_vld)
7660 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
7662 if (tpp->ingress_config & F_VNIC)
7666 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
7668 if ((tpp->ingress_config & F_VNIC) == 0)
7672 if (fs->val.iport || fs->mask.iport)
7675 if (fs->val.fcoe || fs->mask.fcoe)
7678 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
7685 get_filter_mode(struct adapter *sc, uint32_t *mode)
7687 struct tp_params *tpp = &sc->params.tp;
7690 * We trust the cached values of the relevant TP registers. This means
7691 * things work reliably only if writes to those registers are always via
7692 * t4_set_filter_mode.
7694 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
7700 set_filter_mode(struct adapter *sc, uint32_t mode)
7702 struct tp_params *tpp = &sc->params.tp;
7703 uint32_t fconf, iconf;
7706 iconf = mode_to_iconf(mode);
7707 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
7709 * For now we just complain if A_TP_INGRESS_CONFIG is not
7710 * already set to the correct value for the requested filter
7711 * mode. It's not clear if it's safe to write to this register
7712 * on the fly. (And we trust the cached value of the register).
7717 fconf = mode_to_fconf(mode);
7719 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7724 if (sc->tids.ftids_in_use > 0) {
7730 if (uld_active(sc, ULD_TOM)) {
7736 rc = -t4_set_filter_mode(sc, fconf);
7738 end_synchronized_op(sc, LOCK_HELD);
7742 static inline uint64_t
7743 get_filter_hits(struct adapter *sc, uint32_t fid)
7747 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
7748 (fid + sc->tids.ftid_base) * TCB_SIZE;
7753 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
7754 return (be64toh(hits));
7758 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
7759 return (be32toh(hits));
7764 get_filter(struct adapter *sc, struct t4_filter *t)
7766 int i, rc, nfilters = sc->tids.nftids;
7767 struct filter_entry *f;
7769 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7774 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
7775 t->idx >= nfilters) {
7776 t->idx = 0xffffffff;
7780 f = &sc->tids.ftid_tab[t->idx];
7781 for (i = t->idx; i < nfilters; i++, f++) {
7784 t->l2tidx = f->l2t ? f->l2t->idx : 0;
7785 t->smtidx = f->smtidx;
7787 t->hits = get_filter_hits(sc, t->idx);
7789 t->hits = UINT64_MAX;
7796 t->idx = 0xffffffff;
7798 end_synchronized_op(sc, LOCK_HELD);
7803 set_filter(struct adapter *sc, struct t4_filter *t)
7805 unsigned int nfilters, nports;
7806 struct filter_entry *f;
7809 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
7813 nfilters = sc->tids.nftids;
7814 nports = sc->params.nports;
7816 if (nfilters == 0) {
7821 if (t->idx >= nfilters) {
7826 /* Validate against the global filter mode and ingress config */
7827 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
7831 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
7836 if (t->fs.val.iport >= nports) {
7841 /* Can't specify an iq if not steering to it */
7842 if (!t->fs.dirsteer && t->fs.iq) {
7847 /* IPv6 filter idx must be 4 aligned */
7848 if (t->fs.type == 1 &&
7849 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
7854 if (!(sc->flags & FULL_INIT_DONE) &&
7855 ((rc = adapter_full_init(sc)) != 0))
7858 if (sc->tids.ftid_tab == NULL) {
7859 KASSERT(sc->tids.ftids_in_use == 0,
7860 ("%s: no memory allocated but filters_in_use > 0",
7863 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
7864 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
7865 if (sc->tids.ftid_tab == NULL) {
7869 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
7872 for (i = 0; i < 4; i++) {
7873 f = &sc->tids.ftid_tab[t->idx + i];
7875 if (f->pending || f->valid) {
7884 if (t->fs.type == 0)
7888 f = &sc->tids.ftid_tab[t->idx];
7891 rc = set_filter_wr(sc, t->idx);
7893 end_synchronized_op(sc, 0);
7896 mtx_lock(&sc->tids.ftid_lock);
7898 if (f->pending == 0) {
7899 rc = f->valid ? 0 : EIO;
7903 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7904 PCATCH, "t4setfw", 0)) {
7909 mtx_unlock(&sc->tids.ftid_lock);
7915 del_filter(struct adapter *sc, struct t4_filter *t)
7917 unsigned int nfilters;
7918 struct filter_entry *f;
7921 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
7925 nfilters = sc->tids.nftids;
7927 if (nfilters == 0) {
7932 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
7933 t->idx >= nfilters) {
7938 if (!(sc->flags & FULL_INIT_DONE)) {
7943 f = &sc->tids.ftid_tab[t->idx];
7955 t->fs = f->fs; /* extra info for the caller */
7956 rc = del_filter_wr(sc, t->idx);
7960 end_synchronized_op(sc, 0);
7963 mtx_lock(&sc->tids.ftid_lock);
7965 if (f->pending == 0) {
7966 rc = f->valid ? EIO : 0;
7970 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7971 PCATCH, "t4delfw", 0)) {
7976 mtx_unlock(&sc->tids.ftid_lock);
7983 clear_filter(struct filter_entry *f)
7986 t4_l2t_release(f->l2t);
7988 bzero(f, sizeof (*f));
7992 set_filter_wr(struct adapter *sc, int fidx)
7994 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
7995 struct fw_filter_wr *fwr;
7996 unsigned int ftid, vnic_vld, vnic_vld_mask;
7997 struct wrq_cookie cookie;
7999 ASSERT_SYNCHRONIZED_OP(sc);
8001 if (f->fs.newdmac || f->fs.newvlan) {
8002 /* This filter needs an L2T entry; allocate one. */
8003 f->l2t = t4_l2t_alloc_switching(sc->l2t);
8006 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
8008 t4_l2t_release(f->l2t);
8014 /* Already validated against fconf, iconf */
8015 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
8016 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
8017 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
8021 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
8026 ftid = sc->tids.ftid_base + fidx;
8028 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8031 bzero(fwr, sizeof(*fwr));
8033 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
8034 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
8036 htobe32(V_FW_FILTER_WR_TID(ftid) |
8037 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
8038 V_FW_FILTER_WR_NOREPLY(0) |
8039 V_FW_FILTER_WR_IQ(f->fs.iq));
8040 fwr->del_filter_to_l2tix =
8041 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
8042 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
8043 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
8044 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
8045 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8046 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8047 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8048 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8049 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8050 f->fs.newvlan == VLAN_REWRITE) |
8051 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8052 f->fs.newvlan == VLAN_REWRITE) |
8053 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8054 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8055 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8056 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8057 fwr->ethtype = htobe16(f->fs.val.ethtype);
8058 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8059 fwr->frag_to_ovlan_vldm =
8060 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8061 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8062 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8063 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8064 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8065 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8067 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8068 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8069 fwr->maci_to_matchtypem =
8070 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8071 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8072 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8073 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8074 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8075 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8076 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8077 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8078 fwr->ptcl = f->fs.val.proto;
8079 fwr->ptclm = f->fs.mask.proto;
8080 fwr->ttyp = f->fs.val.tos;
8081 fwr->ttypm = f->fs.mask.tos;
8082 fwr->ivlan = htobe16(f->fs.val.vlan);
8083 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8084 fwr->ovlan = htobe16(f->fs.val.vnic);
8085 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8086 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8087 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8088 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8089 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8090 fwr->lp = htobe16(f->fs.val.dport);
8091 fwr->lpm = htobe16(f->fs.mask.dport);
8092 fwr->fp = htobe16(f->fs.val.sport);
8093 fwr->fpm = htobe16(f->fs.mask.sport);
8095 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8098 sc->tids.ftids_in_use++;
8100 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8105 del_filter_wr(struct adapter *sc, int fidx)
8107 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8108 struct fw_filter_wr *fwr;
8110 struct wrq_cookie cookie;
8112 ftid = sc->tids.ftid_base + fidx;
8114 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8117 bzero(fwr, sizeof (*fwr));
8119 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
8122 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8127 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8129 struct adapter *sc = iq->adapter;
8130 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
8131 unsigned int idx = GET_TID(rpl);
8133 struct filter_entry *f;
8135 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
8137 MPASS(iq == &sc->sge.fwq);
8138 MPASS(is_ftid(sc, idx));
8140 idx -= sc->tids.ftid_base;
8141 f = &sc->tids.ftid_tab[idx];
8142 rc = G_COOKIE(rpl->cookie);
8144 mtx_lock(&sc->tids.ftid_lock);
8145 if (rc == FW_FILTER_WR_FLT_ADDED) {
8146 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
8148 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
8149 f->pending = 0; /* asynchronous setup completed */
8152 if (rc != FW_FILTER_WR_FLT_DELETED) {
8153 /* Add or delete failed, display an error */
8155 "filter %u setup failed with error %u\n",
8160 sc->tids.ftids_in_use--;
8162 wakeup(&sc->tids.ftid_tab);
8163 mtx_unlock(&sc->tids.ftid_lock);
8169 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8172 MPASS(iq->set_tcb_rpl != NULL);
8173 return (iq->set_tcb_rpl(iq, rss, m));
8177 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8180 MPASS(iq->l2t_write_rpl != NULL);
8181 return (iq->l2t_write_rpl(iq, rss, m));
8185 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8189 if (cntxt->cid > M_CTXTQID)
8192 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8193 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8196 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8200 if (sc->flags & FW_OK) {
8201 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8208 * Read via firmware failed or wasn't even attempted. Read directly via
8211 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8213 end_synchronized_op(sc, 0);
8218 load_fw(struct adapter *sc, struct t4_data *fw)
8223 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8227 if (sc->flags & FULL_INIT_DONE) {
8232 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8233 if (fw_data == NULL) {
8238 rc = copyin(fw->data, fw_data, fw->len);
8240 rc = -t4_load_fw(sc, fw_data, fw->len);
8242 free(fw_data, M_CXGBE);
8244 end_synchronized_op(sc, 0);
8248 #define MAX_READ_BUF_SIZE (128 * 1024)
8250 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
8252 uint32_t addr, remaining, n;
8257 rc = validate_mem_range(sc, mr->addr, mr->len);
8261 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
8263 remaining = mr->len;
8264 dst = (void *)mr->data;
8267 n = min(remaining, MAX_READ_BUF_SIZE);
8268 read_via_memwin(sc, 2, addr, buf, n);
8270 rc = copyout(buf, dst, n);
8282 #undef MAX_READ_BUF_SIZE
8285 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8289 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8292 if (i2cd->len > sizeof(i2cd->data))
8295 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8298 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8299 i2cd->offset, i2cd->len, &i2cd->data[0]);
8300 end_synchronized_op(sc, 0);
8306 in_range(int val, int lo, int hi)
8309 return (val < 0 || (val <= hi && val >= lo));
8313 set_sched_class_config(struct adapter *sc, int minmax)
8320 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc");
8323 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1);
8324 end_synchronized_op(sc, 0);
8330 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p,
8333 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode;
8334 struct port_info *pi;
8335 struct tx_sched_class *tc;
8337 if (p->level == SCHED_CLASS_LEVEL_CL_RL)
8338 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
8339 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8340 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
8341 else if (p->level == SCHED_CLASS_LEVEL_CH_RL)
8342 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
8346 if (p->mode == SCHED_CLASS_MODE_CLASS)
8347 fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
8348 else if (p->mode == SCHED_CLASS_MODE_FLOW)
8349 fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
8353 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS)
8354 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
8355 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS)
8356 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
8360 if (p->ratemode == SCHED_CLASS_RATEMODE_REL)
8361 fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
8362 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS)
8363 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
8367 /* Vet our parameters ... */
8368 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1))
8371 pi = sc->port[sc->chan_map[p->channel]];
8374 MPASS(pi->tx_chan == p->channel);
8375 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */
8377 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) ||
8378 !in_range(p->minrate, 0, top_speed) ||
8379 !in_range(p->maxrate, 0, top_speed) ||
8380 !in_range(p->weight, 0, 100))
8384 * Translate any unset parameters into the firmware's
8385 * nomenclature and/or fail the call if the parameters
8388 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0)
8393 if (p->maxrate < 0) {
8394 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8395 p->level == SCHED_CLASS_LEVEL_CH_RL)
8400 if (p->weight < 0) {
8401 if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8406 if (p->pktsize < 0) {
8407 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8408 p->level == SCHED_CLASS_LEVEL_CH_RL)
8414 rc = begin_synchronized_op(sc, NULL,
8415 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp");
8418 tc = &pi->tc[p->cl];
8420 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode,
8421 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate,
8422 p->weight, p->pktsize, sleep_ok);
8424 tc->flags |= TX_SC_OK;
8427 * Unknown state at this point, see tc->params for what was
8430 tc->flags &= ~TX_SC_OK;
8432 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD);
8438 t4_set_sched_class(struct adapter *sc, struct t4_sched_params *p)
8441 if (p->type != SCHED_CLASS_TYPE_PACKET)
8444 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
8445 return (set_sched_class_config(sc, p->u.config.minmax));
8447 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
8448 return (set_sched_class_params(sc, &p->u.params, 1));
8454 t4_set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
8456 struct port_info *pi = NULL;
8458 struct sge_txq *txq;
8459 uint32_t fw_mnem, fw_queue, fw_class;
8462 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
8466 if (p->port >= sc->params.nports) {
8471 /* XXX: Only supported for the main VI. */
8472 pi = sc->port[p->port];
8474 if (!(vi->flags & VI_INIT_DONE)) {
8475 /* tx queues not set up yet */
8480 if (!in_range(p->queue, 0, vi->ntxq - 1) ||
8481 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) {
8487 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
8488 * Scheduling Class in this case).
8490 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
8491 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
8492 fw_class = p->cl < 0 ? 0xffffffff : p->cl;
8495 * If op.queue is non-negative, then we're only changing the scheduling
8496 * on a single specified TX queue.
8498 if (p->queue >= 0) {
8499 txq = &sc->sge.txq[vi->first_txq + p->queue];
8500 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8501 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8507 * Change the scheduling on all the TX queues for the
8510 for_each_txq(vi, i, txq) {
8511 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8512 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8520 end_synchronized_op(sc, 0);
8525 t4_os_find_pci_capability(struct adapter *sc, int cap)
8529 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8533 t4_os_pci_save_state(struct adapter *sc)
8536 struct pci_devinfo *dinfo;
8539 dinfo = device_get_ivars(dev);
8541 pci_cfg_save(dev, dinfo, 0);
8546 t4_os_pci_restore_state(struct adapter *sc)
8549 struct pci_devinfo *dinfo;
8552 dinfo = device_get_ivars(dev);
8554 pci_cfg_restore(dev, dinfo);
8559 t4_os_portmod_changed(const struct adapter *sc, int idx)
8561 struct port_info *pi = sc->port[idx];
8565 static const char *mod_str[] = {
8566 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8569 for_each_vi(pi, v, vi) {
8570 build_medialist(pi, &vi->media);
8573 ifp = pi->vi[0].ifp;
8574 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8575 if_printf(ifp, "transceiver unplugged.\n");
8576 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8577 if_printf(ifp, "unknown transceiver inserted.\n");
8578 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8579 if_printf(ifp, "unsupported transceiver inserted.\n");
8580 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8581 if_printf(ifp, "%s transceiver inserted.\n",
8582 mod_str[pi->mod_type]);
8584 if_printf(ifp, "transceiver (type %d) inserted.\n",
8590 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
8592 struct port_info *pi = sc->port[idx];
8601 pi->linkdnrc = reason;
8603 for_each_vi(pi, v, vi) {
8609 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
8610 if_link_state_change(ifp, LINK_STATE_UP);
8612 if_link_state_change(ifp, LINK_STATE_DOWN);
8618 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8622 sx_slock(&t4_list_lock);
8623 SLIST_FOREACH(sc, &t4_list, link) {
8625 * func should not make any assumptions about what state sc is
8626 * in - the only guarantee is that sc->sc_lock is a valid lock.
8630 sx_sunlock(&t4_list_lock);
8634 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
8638 struct adapter *sc = dev->si_drv1;
8640 rc = priv_check(td, PRIV_DRIVER);
8645 case CHELSIO_T4_GETREG: {
8646 struct t4_reg *edata = (struct t4_reg *)data;
8648 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8651 if (edata->size == 4)
8652 edata->val = t4_read_reg(sc, edata->addr);
8653 else if (edata->size == 8)
8654 edata->val = t4_read_reg64(sc, edata->addr);
8660 case CHELSIO_T4_SETREG: {
8661 struct t4_reg *edata = (struct t4_reg *)data;
8663 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8666 if (edata->size == 4) {
8667 if (edata->val & 0xffffffff00000000)
8669 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
8670 } else if (edata->size == 8)
8671 t4_write_reg64(sc, edata->addr, edata->val);
8676 case CHELSIO_T4_REGDUMP: {
8677 struct t4_regdump *regs = (struct t4_regdump *)data;
8678 int reglen = t4_get_regs_len(sc);
8681 if (regs->len < reglen) {
8682 regs->len = reglen; /* hint to the caller */
8687 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
8688 get_regs(sc, regs, buf);
8689 rc = copyout(buf, regs->data, reglen);
8693 case CHELSIO_T4_GET_FILTER_MODE:
8694 rc = get_filter_mode(sc, (uint32_t *)data);
8696 case CHELSIO_T4_SET_FILTER_MODE:
8697 rc = set_filter_mode(sc, *(uint32_t *)data);
8699 case CHELSIO_T4_GET_FILTER:
8700 rc = get_filter(sc, (struct t4_filter *)data);
8702 case CHELSIO_T4_SET_FILTER:
8703 rc = set_filter(sc, (struct t4_filter *)data);
8705 case CHELSIO_T4_DEL_FILTER:
8706 rc = del_filter(sc, (struct t4_filter *)data);
8708 case CHELSIO_T4_GET_SGE_CONTEXT:
8709 rc = get_sge_context(sc, (struct t4_sge_context *)data);
8711 case CHELSIO_T4_LOAD_FW:
8712 rc = load_fw(sc, (struct t4_data *)data);
8714 case CHELSIO_T4_GET_MEM:
8715 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
8717 case CHELSIO_T4_GET_I2C:
8718 rc = read_i2c(sc, (struct t4_i2c_data *)data);
8720 case CHELSIO_T4_CLEAR_STATS: {
8722 u_int port_id = *(uint32_t *)data;
8723 struct port_info *pi;
8726 if (port_id >= sc->params.nports)
8728 pi = sc->port[port_id];
8731 t4_clr_port_stats(sc, pi->tx_chan);
8732 pi->tx_parse_error = 0;
8733 mtx_lock(&sc->reg_lock);
8734 for_each_vi(pi, v, vi) {
8735 if (vi->flags & VI_INIT_DONE)
8736 t4_clr_vi_stats(sc, vi->viid);
8738 mtx_unlock(&sc->reg_lock);
8741 * Since this command accepts a port, clear stats for
8742 * all VIs on this port.
8744 for_each_vi(pi, v, vi) {
8745 if (vi->flags & VI_INIT_DONE) {
8746 struct sge_rxq *rxq;
8747 struct sge_txq *txq;
8748 struct sge_wrq *wrq;
8750 for_each_rxq(vi, i, rxq) {
8751 #if defined(INET) || defined(INET6)
8752 rxq->lro.lro_queued = 0;
8753 rxq->lro.lro_flushed = 0;
8756 rxq->vlan_extraction = 0;
8759 for_each_txq(vi, i, txq) {
8762 txq->vlan_insertion = 0;
8766 txq->txpkts0_wrs = 0;
8767 txq->txpkts1_wrs = 0;
8768 txq->txpkts0_pkts = 0;
8769 txq->txpkts1_pkts = 0;
8770 mp_ring_reset_stats(txq->r);
8774 /* nothing to clear for each ofld_rxq */
8776 for_each_ofld_txq(vi, i, wrq) {
8777 wrq->tx_wrs_direct = 0;
8778 wrq->tx_wrs_copied = 0;
8782 if (IS_MAIN_VI(vi)) {
8783 wrq = &sc->sge.ctrlq[pi->port_id];
8784 wrq->tx_wrs_direct = 0;
8785 wrq->tx_wrs_copied = 0;
8791 case CHELSIO_T4_SCHED_CLASS:
8792 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
8794 case CHELSIO_T4_SCHED_QUEUE:
8795 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
8797 case CHELSIO_T4_GET_TRACER:
8798 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
8800 case CHELSIO_T4_SET_TRACER:
8801 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
8811 t4_db_full(struct adapter *sc)
8814 CXGBE_UNIMPLEMENTED(__func__);
8818 t4_db_dropped(struct adapter *sc)
8821 CXGBE_UNIMPLEMENTED(__func__);
8826 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
8829 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
8830 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
8831 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
8832 V_HPZ3(pgsz_order[3]));
8836 toe_capability(struct vi_info *vi, int enable)
8839 struct port_info *pi = vi->pi;
8840 struct adapter *sc = pi->adapter;
8842 ASSERT_SYNCHRONIZED_OP(sc);
8844 if (!is_offload(sc))
8848 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
8849 /* TOE is already enabled. */
8854 * We need the port's queues around so that we're able to send
8855 * and receive CPLs to/from the TOE even if the ifnet for this
8856 * port has never been UP'd administratively.
8858 if (!(vi->flags & VI_INIT_DONE)) {
8859 rc = vi_full_init(vi);
8863 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
8864 rc = vi_full_init(&pi->vi[0]);
8869 if (isset(&sc->offload_map, pi->port_id)) {
8870 /* TOE is enabled on another VI of this port. */
8875 if (!uld_active(sc, ULD_TOM)) {
8876 rc = t4_activate_uld(sc, ULD_TOM);
8879 "You must kldload t4_tom.ko before trying "
8880 "to enable TOE on a cxgbe interface.\n");
8884 KASSERT(sc->tom_softc != NULL,
8885 ("%s: TOM activated but softc NULL", __func__));
8886 KASSERT(uld_active(sc, ULD_TOM),
8887 ("%s: TOM activated but flag not set", __func__));
8890 /* Activate iWARP and iSCSI too, if the modules are loaded. */
8891 if (!uld_active(sc, ULD_IWARP))
8892 (void) t4_activate_uld(sc, ULD_IWARP);
8893 if (!uld_active(sc, ULD_ISCSI))
8894 (void) t4_activate_uld(sc, ULD_ISCSI);
8897 setbit(&sc->offload_map, pi->port_id);
8901 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
8904 KASSERT(uld_active(sc, ULD_TOM),
8905 ("%s: TOM never initialized?", __func__));
8906 clrbit(&sc->offload_map, pi->port_id);
8913 * Add an upper layer driver to the global list.
8916 t4_register_uld(struct uld_info *ui)
8921 sx_xlock(&t4_uld_list_lock);
8922 SLIST_FOREACH(u, &t4_uld_list, link) {
8923 if (u->uld_id == ui->uld_id) {
8929 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
8932 sx_xunlock(&t4_uld_list_lock);
8937 t4_unregister_uld(struct uld_info *ui)
8942 sx_xlock(&t4_uld_list_lock);
8944 SLIST_FOREACH(u, &t4_uld_list, link) {
8946 if (ui->refcount > 0) {
8951 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
8957 sx_xunlock(&t4_uld_list_lock);
8962 t4_activate_uld(struct adapter *sc, int id)
8965 struct uld_info *ui;
8967 ASSERT_SYNCHRONIZED_OP(sc);
8969 if (id < 0 || id > ULD_MAX)
8971 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
8973 sx_slock(&t4_uld_list_lock);
8975 SLIST_FOREACH(ui, &t4_uld_list, link) {
8976 if (ui->uld_id == id) {
8977 if (!(sc->flags & FULL_INIT_DONE)) {
8978 rc = adapter_full_init(sc);
8983 rc = ui->activate(sc);
8985 setbit(&sc->active_ulds, id);
8992 sx_sunlock(&t4_uld_list_lock);
8998 t4_deactivate_uld(struct adapter *sc, int id)
9001 struct uld_info *ui;
9003 ASSERT_SYNCHRONIZED_OP(sc);
9005 if (id < 0 || id > ULD_MAX)
9009 sx_slock(&t4_uld_list_lock);
9011 SLIST_FOREACH(ui, &t4_uld_list, link) {
9012 if (ui->uld_id == id) {
9013 rc = ui->deactivate(sc);
9015 clrbit(&sc->active_ulds, id);
9022 sx_sunlock(&t4_uld_list_lock);
9028 uld_active(struct adapter *sc, int uld_id)
9031 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9033 return (isset(&sc->active_ulds, uld_id));
9038 * Come up with reasonable defaults for some of the tunables, provided they're
9039 * not set by the user (in which case we'll use the values as is).
9042 tweak_tunables(void)
9044 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9046 if (t4_ntxq10g < 1) {
9048 t4_ntxq10g = rss_getnumbuckets();
9050 t4_ntxq10g = min(nc, NTXQ_10G);
9054 if (t4_ntxq1g < 1) {
9056 /* XXX: way too many for 1GbE? */
9057 t4_ntxq1g = rss_getnumbuckets();
9059 t4_ntxq1g = min(nc, NTXQ_1G);
9064 t4_ntxq_vi = min(nc, NTXQ_VI);
9066 if (t4_nrxq10g < 1) {
9068 t4_nrxq10g = rss_getnumbuckets();
9070 t4_nrxq10g = min(nc, NRXQ_10G);
9074 if (t4_nrxq1g < 1) {
9076 /* XXX: way too many for 1GbE? */
9077 t4_nrxq1g = rss_getnumbuckets();
9079 t4_nrxq1g = min(nc, NRXQ_1G);
9084 t4_nrxq_vi = min(nc, NRXQ_VI);
9087 if (t4_nofldtxq10g < 1)
9088 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
9090 if (t4_nofldtxq1g < 1)
9091 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
9093 if (t4_nofldtxq_vi < 1)
9094 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI);
9096 if (t4_nofldrxq10g < 1)
9097 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
9099 if (t4_nofldrxq1g < 1)
9100 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
9102 if (t4_nofldrxq_vi < 1)
9103 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI);
9105 if (t4_toecaps_allowed == -1)
9106 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9108 if (t4_rdmacaps_allowed == -1) {
9109 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9110 FW_CAPS_CONFIG_RDMA_RDMAC;
9113 if (t4_iscsicaps_allowed == -1) {
9114 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9115 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9116 FW_CAPS_CONFIG_ISCSI_T10DIF;
9119 if (t4_toecaps_allowed == -1)
9120 t4_toecaps_allowed = 0;
9122 if (t4_rdmacaps_allowed == -1)
9123 t4_rdmacaps_allowed = 0;
9125 if (t4_iscsicaps_allowed == -1)
9126 t4_iscsicaps_allowed = 0;
9130 if (t4_nnmtxq_vi < 1)
9131 t4_nnmtxq_vi = min(nc, NNMTXQ_VI);
9133 if (t4_nnmrxq_vi < 1)
9134 t4_nnmrxq_vi = min(nc, NNMRXQ_VI);
9137 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
9138 t4_tmr_idx_10g = TMR_IDX_10G;
9140 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
9141 t4_pktc_idx_10g = PKTC_IDX_10G;
9143 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
9144 t4_tmr_idx_1g = TMR_IDX_1G;
9146 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
9147 t4_pktc_idx_1g = PKTC_IDX_1G;
9149 if (t4_qsize_txq < 128)
9152 if (t4_qsize_rxq < 128)
9154 while (t4_qsize_rxq & 7)
9157 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9162 t4_dump_tcb(struct adapter *sc, int tid)
9164 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9166 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9167 save = t4_read_reg(sc, reg);
9168 base = sc->memwin[2].mw_base;
9170 /* Dump TCB for the tid */
9171 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9172 tcb_addr += tid * TCB_SIZE;
9176 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9178 pf = V_PFNUM(sc->pf);
9179 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9181 t4_write_reg(sc, reg, win_pos | pf);
9182 t4_read_reg(sc, reg);
9184 off = tcb_addr - win_pos;
9185 for (i = 0; i < 4; i++) {
9187 for (j = 0; j < 8; j++, off += 4)
9188 buf[j] = htonl(t4_read_reg(sc, base + off));
9190 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9191 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9195 t4_write_reg(sc, reg, save);
9196 t4_read_reg(sc, reg);
9200 t4_dump_devlog(struct adapter *sc)
9202 struct devlog_params *dparams = &sc->params.devlog;
9203 struct fw_devlog_e e;
9204 int i, first, j, m, nentries, rc;
9205 uint64_t ftstamp = UINT64_MAX;
9207 if (dparams->start == 0) {
9208 db_printf("devlog params not valid\n");
9212 nentries = dparams->size / sizeof(struct fw_devlog_e);
9213 m = fwmtype_to_hwmtype(dparams->memtype);
9215 /* Find the first entry. */
9217 for (i = 0; i < nentries && !db_pager_quit; i++) {
9218 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9219 sizeof(e), (void *)&e);
9223 if (e.timestamp == 0)
9226 e.timestamp = be64toh(e.timestamp);
9227 if (e.timestamp < ftstamp) {
9228 ftstamp = e.timestamp;
9238 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9239 sizeof(e), (void *)&e);
9243 if (e.timestamp == 0)
9246 e.timestamp = be64toh(e.timestamp);
9247 e.seqno = be32toh(e.seqno);
9248 for (j = 0; j < 8; j++)
9249 e.params[j] = be32toh(e.params[j]);
9251 db_printf("%10d %15ju %8s %8s ",
9252 e.seqno, e.timestamp,
9253 (e.level < nitems(devlog_level_strings) ?
9254 devlog_level_strings[e.level] : "UNKNOWN"),
9255 (e.facility < nitems(devlog_facility_strings) ?
9256 devlog_facility_strings[e.facility] : "UNKNOWN"));
9257 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
9258 e.params[3], e.params[4], e.params[5], e.params[6],
9261 if (++i == nentries)
9263 } while (i != first && !db_pager_quit);
9266 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
9267 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
9269 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
9276 t = db_read_token();
9278 dev = device_lookup_by_name(db_tok_string);
9283 db_printf("usage: show t4 devlog <nexus>\n");
9288 db_printf("device not found\n");
9292 t4_dump_devlog(device_get_softc(dev));
9295 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
9304 t = db_read_token();
9306 dev = device_lookup_by_name(db_tok_string);
9307 t = db_read_token();
9309 tid = db_tok_number;
9316 db_printf("usage: show t4 tcb <nexus> <tid>\n");
9321 db_printf("device not found\n");
9325 db_printf("invalid tid\n");
9329 t4_dump_tcb(device_get_softc(dev), tid);
9333 static struct sx mlu; /* mod load unload */
9334 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
9337 mod_event(module_t mod, int cmd, void *arg)
9340 static int loaded = 0;
9345 if (loaded++ == 0) {
9347 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
9348 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
9349 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
9350 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
9351 sx_init(&t4_list_lock, "T4/T5 adapters");
9352 SLIST_INIT(&t4_list);
9354 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
9355 SLIST_INIT(&t4_uld_list);
9357 t4_tracer_modload();
9365 if (--loaded == 0) {
9368 sx_slock(&t4_list_lock);
9369 if (!SLIST_EMPTY(&t4_list)) {
9371 sx_sunlock(&t4_list_lock);
9375 sx_slock(&t4_uld_list_lock);
9376 if (!SLIST_EMPTY(&t4_uld_list)) {
9378 sx_sunlock(&t4_uld_list_lock);
9379 sx_sunlock(&t4_list_lock);
9384 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
9385 uprintf("%ju clusters with custom free routine "
9386 "still is use.\n", t4_sge_extfree_refs());
9387 pause("t4unload", 2 * hz);
9390 sx_sunlock(&t4_uld_list_lock);
9392 sx_sunlock(&t4_list_lock);
9394 if (t4_sge_extfree_refs() == 0) {
9395 t4_tracer_modunload();
9397 sx_destroy(&t4_uld_list_lock);
9399 sx_destroy(&t4_list_lock);
9404 loaded++; /* undo earlier decrement */
9415 static devclass_t t4_devclass, t5_devclass;
9416 static devclass_t cxgbe_devclass, cxl_devclass;
9417 static devclass_t vcxgbe_devclass, vcxl_devclass;
9419 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9420 MODULE_VERSION(t4nex, 1);
9421 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9423 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9424 MODULE_VERSION(t5nex, 1);
9425 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9427 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9428 MODULE_VERSION(cxgbe, 1);
9430 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9431 MODULE_VERSION(cxl, 1);
9433 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9434 MODULE_VERSION(vcxgbe, 1);
9436 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9437 MODULE_VERSION(vcxl, 1);