2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
36 #include <sys/socket.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/queue.h>
41 #include <sys/taskqueue.h>
43 #include <sys/sglist.h>
44 #include <sys/sysctl.h>
46 #include <sys/counter.h>
48 #include <net/ethernet.h>
50 #include <net/if_vlan_var.h>
51 #include <netinet/in.h>
52 #include <netinet/ip.h>
53 #include <netinet/ip6.h>
54 #include <netinet/tcp.h>
55 #include <machine/md_var.h>
59 #include <machine/bus.h>
60 #include <sys/selinfo.h>
61 #include <net/if_var.h>
62 #include <net/netmap.h>
63 #include <dev/netmap/netmap_kern.h>
66 #include "common/common.h"
67 #include "common/t4_regs.h"
68 #include "common/t4_regs_values.h"
69 #include "common/t4_msg.h"
70 #include "t4_mp_ring.h"
72 #ifdef T4_PKT_TIMESTAMP
73 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
75 #define RX_COPY_THRESHOLD MINCLSIZE
79 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
80 * 0-7 are valid values.
83 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
86 * Pad ethernet payload up to this boundary.
87 * -1: driver should figure out a good value.
89 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
92 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
96 * -1: driver should figure out a good value.
97 * 64 or 128 are the only other valid values.
100 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
104 * -1: no congestion feedback (not recommended).
105 * 0: backpressure the channel instead of dropping packets right away.
106 * 1: no backpressure, drop packets for the congested queue immediately.
108 static int cong_drop = 0;
109 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
112 * Deliver multiple frames in the same free list buffer if they fit.
113 * -1: let the driver decide whether to enable buffer packing or not.
114 * 0: disable buffer packing.
115 * 1: enable buffer packing.
117 static int buffer_packing = -1;
118 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
121 * Start next frame in a packed buffer at this boundary.
122 * -1: driver should figure out a good value.
123 * T4: driver will ignore this and use the same value as fl_pad above.
124 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
126 static int fl_pack = -1;
127 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
130 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
131 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
132 * 1: ok to create mbuf(s) within a cluster if there is room.
134 static int allow_mbufs_in_cluster = 1;
135 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
138 * Largest rx cluster size that the driver is allowed to allocate.
140 static int largest_rx_cluster = MJUM16BYTES;
141 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
144 * Size of cluster allocation that's most likely to succeed. The driver will
145 * fall back to this size if it fails to allocate clusters larger than this.
147 static int safest_rx_cluster = PAGE_SIZE;
148 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
151 u_int wr_type; /* type 0 or type 1 */
152 u_int npkt; /* # of packets in this work request */
153 u_int plen; /* total payload (sum of all packets) */
154 u_int len16; /* # of 16B pieces used by this work request */
157 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
160 struct sglist_seg seg[TX_SGL_SEGS];
163 static int service_iq(struct sge_iq *, int);
164 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
165 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
166 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
167 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
168 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
170 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
171 bus_addr_t *, void **);
172 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
174 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
176 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
177 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
179 static int alloc_fwq(struct adapter *);
180 static int free_fwq(struct adapter *);
181 static int alloc_mgmtq(struct adapter *);
182 static int free_mgmtq(struct adapter *);
183 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
184 struct sysctl_oid *);
185 static int free_rxq(struct vi_info *, struct sge_rxq *);
187 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
188 struct sysctl_oid *);
189 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
192 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
193 struct sysctl_oid *);
194 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
195 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
196 struct sysctl_oid *);
197 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
199 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
200 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
202 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
204 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
205 static int free_eq(struct adapter *, struct sge_eq *);
206 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
207 struct sysctl_oid *);
208 static int free_wrq(struct adapter *, struct sge_wrq *);
209 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
210 struct sysctl_oid *);
211 static int free_txq(struct vi_info *, struct sge_txq *);
212 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
213 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
214 static int refill_fl(struct adapter *, struct sge_fl *, int);
215 static void refill_sfl(void *);
216 static int alloc_fl_sdesc(struct sge_fl *);
217 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
218 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
219 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
220 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
222 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
223 static inline u_int txpkt_len16(u_int, u_int);
224 static inline u_int txpkts0_len16(u_int);
225 static inline u_int txpkts1_len16(void);
226 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
227 struct mbuf *, u_int);
228 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
229 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
230 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
231 struct mbuf *, const struct txpkts *, u_int);
232 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
233 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
234 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
235 static inline uint16_t read_hw_cidx(struct sge_eq *);
236 static inline u_int reclaimable_tx_desc(struct sge_eq *);
237 static inline u_int total_available_tx_desc(struct sge_eq *);
238 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
239 static void tx_reclaim(void *, int);
240 static __be64 get_flit(struct sglist_seg *, int, int);
241 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
243 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
245 static void wrq_tx_drain(void *, int);
246 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
248 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
249 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
251 static counter_u64_t extfree_refs;
252 static counter_u64_t extfree_rels;
255 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
261 if (fl_pktshift < 0 || fl_pktshift > 7) {
262 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
263 " using 2 instead.\n", fl_pktshift);
267 if (spg_len != 64 && spg_len != 128) {
270 #if defined(__i386__) || defined(__amd64__)
271 len = cpu_clflush_line_size > 64 ? 128 : 64;
276 printf("Invalid hw.cxgbe.spg_len value (%d),"
277 " using %d instead.\n", spg_len, len);
282 if (cong_drop < -1 || cong_drop > 1) {
283 printf("Invalid hw.cxgbe.cong_drop value (%d),"
284 " using 0 instead.\n", cong_drop);
288 extfree_refs = counter_u64_alloc(M_WAITOK);
289 extfree_rels = counter_u64_alloc(M_WAITOK);
290 counter_u64_zero(extfree_refs);
291 counter_u64_zero(extfree_rels);
295 t4_sge_modunload(void)
298 counter_u64_free(extfree_refs);
299 counter_u64_free(extfree_rels);
303 t4_sge_extfree_refs(void)
307 rels = counter_u64_fetch(extfree_rels);
308 refs = counter_u64_fetch(extfree_refs);
310 return (refs - rels);
314 t4_init_sge_cpl_handlers(struct adapter *sc)
317 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg);
318 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg);
319 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
320 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
321 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
325 setup_pad_and_pack_boundaries(struct adapter *sc)
331 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) {
333 * If there is any chance that we might use buffer packing and
334 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
335 * it to 32 in all other cases.
337 pad = is_t4(sc) && buffer_packing ? 64 : 32;
340 * For fl_pad = 0 we'll still write a reasonable value to the
341 * register but all the freelists will opt out of padding.
342 * We'll complain here only if the user tried to set it to a
343 * value greater than 0 that was invalid.
346 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
347 " (%d), using %d instead.\n", fl_pad, pad);
350 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
351 v = V_INGPADBOUNDARY(ilog2(pad) - 5);
352 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
355 if (fl_pack != -1 && fl_pack != pad) {
356 /* Complain but carry on. */
357 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
358 " using %d instead.\n", fl_pack, pad);
364 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
365 !powerof2(fl_pack)) {
366 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
367 MPASS(powerof2(pack));
375 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
376 " (%d), using %d instead.\n", fl_pack, pack);
379 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
381 v = V_INGPACKBOUNDARY(0);
383 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
385 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
386 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
390 * adap->params.vpd.cclk must be set up before this is called.
393 t4_tweak_chip_settings(struct adapter *sc)
397 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
398 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
399 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
400 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
401 static int sge_flbuf_sizes[] = {
403 #if MJUMPAGESIZE != MCLBYTES
405 MJUMPAGESIZE - CL_METADATA_SIZE,
406 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
410 MCLBYTES - MSIZE - CL_METADATA_SIZE,
411 MJUM9BYTES - CL_METADATA_SIZE,
412 MJUM16BYTES - CL_METADATA_SIZE,
415 KASSERT(sc->flags & MASTER_PF,
416 ("%s: trying to change chip settings when not master.", __func__));
418 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
419 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
420 V_EGRSTATUSPAGESIZE(spg_len == 128);
421 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
423 setup_pad_and_pack_boundaries(sc);
425 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
426 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
427 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
428 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
429 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
430 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
431 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
432 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
433 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
435 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
436 ("%s: hw buffer size table too big", __func__));
437 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
438 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
442 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
443 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
444 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
446 KASSERT(intr_timer[0] <= timer_max,
447 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
449 for (i = 1; i < nitems(intr_timer); i++) {
450 KASSERT(intr_timer[i] >= intr_timer[i - 1],
451 ("%s: timers not listed in increasing order (%d)",
454 while (intr_timer[i] > timer_max) {
455 if (i == nitems(intr_timer) - 1) {
456 intr_timer[i] = timer_max;
459 intr_timer[i] += intr_timer[i - 1];
464 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
465 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
466 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
467 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
468 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
469 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
470 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
471 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
472 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
474 /* 4K, 16K, 64K, 256K DDP "page sizes" */
475 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
476 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
478 m = v = F_TDDPTAGTCB;
479 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
481 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
483 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
484 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
488 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
489 * padding is is use the buffer's start and end need to be aligned to the pad
490 * boundary as well. We'll just make sure that the size is a multiple of the
491 * boundary here, it is up to the buffer allocation code to make sure the start
492 * of the buffer is aligned as well.
495 hwsz_ok(struct adapter *sc, int hwsz)
497 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
499 return (hwsz >= 64 && (hwsz & mask) == 0);
503 * XXX: driver really should be able to deal with unexpected settings.
506 t4_read_chip_settings(struct adapter *sc)
508 struct sge *s = &sc->sge;
509 struct sge_params *sp = &sc->params.sge;
512 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
513 static int sw_buf_sizes[] = { /* Sorted by size */
515 #if MJUMPAGESIZE != MCLBYTES
521 struct sw_zone_info *swz, *safe_swz;
522 struct hw_buf_info *hwb;
524 t4_init_sge_params(sc);
528 r = t4_read_reg(sc, A_SGE_CONTROL);
530 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
535 * If this changes then every single use of PAGE_SHIFT in the driver
536 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
538 if (sp->page_shift != PAGE_SHIFT) {
539 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
543 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
544 hwb = &s->hw_buf_info[0];
545 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
546 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
548 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
553 * Create a sorted list in decreasing order of hw buffer sizes (and so
554 * increasing order of spare area) for each software zone.
556 * If padding is enabled then the start and end of the buffer must align
557 * to the pad boundary; if packing is enabled then they must align with
558 * the pack boundary as well. Allocations from the cluster zones are
559 * aligned to min(size, 4K), so the buffer starts at that alignment and
560 * ends at hwb->size alignment. If mbuf inlining is allowed the
561 * starting alignment will be reduced to MSIZE and the driver will
562 * exercise appropriate caution when deciding on the best buffer layout
565 n = 0; /* no usable buffer size to begin with */
566 swz = &s->sw_zone_info[0];
568 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
569 int8_t head = -1, tail = -1;
571 swz->size = sw_buf_sizes[i];
572 swz->zone = m_getzone(swz->size);
573 swz->type = m_gettype(swz->size);
575 if (swz->size < PAGE_SIZE) {
576 MPASS(powerof2(swz->size));
577 if (fl_pad && (swz->size % sp->pad_boundary != 0))
581 if (swz->size == safest_rx_cluster)
584 hwb = &s->hw_buf_info[0];
585 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
586 if (hwb->zidx != -1 || hwb->size > swz->size)
590 MPASS(hwb->size % sp->pad_boundary == 0);
595 else if (hwb->size < s->hw_buf_info[tail].size) {
596 s->hw_buf_info[tail].next = j;
600 struct hw_buf_info *t;
602 for (cur = &head; *cur != -1; cur = &t->next) {
603 t = &s->hw_buf_info[*cur];
604 if (hwb->size == t->size) {
608 if (hwb->size > t->size) {
616 swz->head_hwidx = head;
617 swz->tail_hwidx = tail;
621 if (swz->size - s->hw_buf_info[tail].size >=
623 sc->flags |= BUF_PACKING_OK;
627 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
633 if (safe_swz != NULL) {
634 s->safe_hwidx1 = safe_swz->head_hwidx;
635 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
638 hwb = &s->hw_buf_info[i];
641 MPASS(hwb->size % sp->pad_boundary == 0);
643 spare = safe_swz->size - hwb->size;
644 if (spare >= CL_METADATA_SIZE) {
651 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
652 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
654 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
658 m = v = F_TDDPTAGTCB;
659 r = t4_read_reg(sc, A_ULP_RX_CTL);
661 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
665 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
667 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
668 r = t4_read_reg(sc, A_TP_PARA_REG5);
670 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
674 t4_init_tp_params(sc);
676 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
677 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
683 t4_create_dma_tag(struct adapter *sc)
687 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
688 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
689 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
692 device_printf(sc->dev,
693 "failed to create main DMA tag: %d\n", rc);
700 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
701 struct sysctl_oid_list *children)
703 struct sge_params *sp = &sc->params.sge;
705 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
706 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
707 "freelist buffer sizes");
709 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
710 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
712 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
713 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
715 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
716 NULL, sp->spg_len, "status page size (bytes)");
718 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
719 NULL, cong_drop, "congestion drop setting");
721 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
722 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
726 t4_destroy_dma_tag(struct adapter *sc)
729 bus_dma_tag_destroy(sc->dmat);
735 * Allocate and initialize the firmware event queue and the management queue.
737 * Returns errno on failure. Resources allocated up to that point may still be
738 * allocated. Caller is responsible for cleanup in case this function fails.
741 t4_setup_adapter_queues(struct adapter *sc)
745 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
747 sysctl_ctx_init(&sc->ctx);
748 sc->flags |= ADAP_SYSCTL_CTX;
751 * Firmware event queue
758 * Management queue. This is just a control queue that uses the fwq as
761 rc = alloc_mgmtq(sc);
770 t4_teardown_adapter_queues(struct adapter *sc)
773 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
775 /* Do this before freeing the queue */
776 if (sc->flags & ADAP_SYSCTL_CTX) {
777 sysctl_ctx_free(&sc->ctx);
778 sc->flags &= ~ADAP_SYSCTL_CTX;
788 first_vector(struct vi_info *vi)
790 struct adapter *sc = vi->pi->adapter;
792 if (sc->intr_count == 1)
795 return (vi->first_intr);
799 * Given an arbitrary "index," come up with an iq that can be used by other
800 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc.
801 * The iq returned is guaranteed to be something that takes direct interrupts.
803 static struct sge_iq *
804 vi_intr_iq(struct vi_info *vi, int idx)
806 struct adapter *sc = vi->pi->adapter;
807 struct sge *s = &sc->sge;
808 struct sge_iq *iq = NULL;
811 if (sc->intr_count == 1)
812 return (&sc->sge.fwq);
816 ("%s: vi %p has no exclusive interrupts, total interrupts = %d",
817 __func__, vi, sc->intr_count));
820 if (vi->flags & INTR_RXQ) {
822 iq = &s->rxq[vi->first_rxq + i].iq;
828 if (vi->flags & INTR_OFLD_RXQ) {
829 if (i < vi->nofldrxq) {
830 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq;
836 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
837 vi, vi->flags & INTR_ALL, idx, nintr);
840 KASSERT(iq->flags & IQ_INTR,
841 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi,
842 vi->flags & INTR_ALL, idx));
846 /* Maximum payload that can be delivered with a single iq descriptor */
848 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
854 payload = sc->tt.rx_coalesce ?
855 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
858 /* large enough even when hw VLAN extraction is disabled */
859 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
860 ETHER_VLAN_ENCAP_LEN + mtu;
869 t4_setup_vi_queues(struct vi_info *vi)
871 int rc = 0, i, j, intr_idx, iqid;
874 struct sge_wrq *ctrlq;
876 struct sge_ofld_rxq *ofld_rxq;
877 struct sge_wrq *ofld_txq;
881 struct sge_nm_rxq *nm_rxq;
882 struct sge_nm_txq *nm_txq;
885 struct port_info *pi = vi->pi;
886 struct adapter *sc = pi->adapter;
887 struct ifnet *ifp = vi->ifp;
888 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
889 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
890 int maxp, mtu = ifp->if_mtu;
892 /* Interrupt vector to start from (when using multiple vectors) */
893 intr_idx = first_vector(vi);
896 saved_idx = intr_idx;
897 if (ifp->if_capabilities & IFCAP_NETMAP) {
899 /* netmap is supported with direct interrupts only. */
900 MPASS(vi->flags & INTR_RXQ);
903 * We don't have buffers to back the netmap rx queues
904 * right now so we create the queues in a way that
905 * doesn't set off any congestion signal in the chip.
907 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
908 CTLFLAG_RD, NULL, "rx queues");
909 for_each_nm_rxq(vi, i, nm_rxq) {
910 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
916 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
917 CTLFLAG_RD, NULL, "tx queues");
918 for_each_nm_txq(vi, i, nm_txq) {
919 iqid = vi->first_nm_rxq + (i % vi->nnmrxq);
920 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid);
926 /* Normal rx queues and netmap rx queues share the same interrupts. */
927 intr_idx = saved_idx;
931 * First pass over all NIC and TOE rx queues:
932 * a) initialize iq and fl
933 * b) allocate queue iff it will take direct interrupts.
935 maxp = mtu_to_max_payload(sc, mtu, 0);
936 if (vi->flags & INTR_RXQ) {
937 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
938 CTLFLAG_RD, NULL, "rx queues");
940 for_each_rxq(vi, i, rxq) {
942 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
944 snprintf(name, sizeof(name), "%s rxq%d-fl",
945 device_get_nameunit(vi->dev), i);
946 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
948 if (vi->flags & INTR_RXQ) {
949 rxq->iq.flags |= IQ_INTR;
950 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
957 if (ifp->if_capabilities & IFCAP_NETMAP)
958 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
961 maxp = mtu_to_max_payload(sc, mtu, 1);
962 if (vi->flags & INTR_OFLD_RXQ) {
963 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
965 "rx queues for offloaded TCP connections");
967 for_each_ofld_rxq(vi, i, ofld_rxq) {
969 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx,
972 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
973 device_get_nameunit(vi->dev), i);
974 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
976 if (vi->flags & INTR_OFLD_RXQ) {
977 ofld_rxq->iq.flags |= IQ_INTR;
978 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
987 * Second pass over all NIC and TOE rx queues. The queues forwarding
988 * their interrupts are allocated now.
991 if (!(vi->flags & INTR_RXQ)) {
992 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
993 CTLFLAG_RD, NULL, "rx queues");
994 for_each_rxq(vi, i, rxq) {
995 MPASS(!(rxq->iq.flags & IQ_INTR));
997 intr_idx = vi_intr_iq(vi, j)->abs_id;
999 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1006 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) {
1007 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1009 "rx queues for offloaded TCP connections");
1010 for_each_ofld_rxq(vi, i, ofld_rxq) {
1011 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1013 intr_idx = vi_intr_iq(vi, j)->abs_id;
1015 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1024 * Now the tx queues. Only one pass needed.
1026 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1029 for_each_txq(vi, i, txq) {
1030 iqid = vi_intr_iq(vi, j)->cntxt_id;
1031 snprintf(name, sizeof(name), "%s txq%d",
1032 device_get_nameunit(vi->dev), i);
1033 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid,
1036 rc = alloc_txq(vi, txq, i, oid);
1042 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1043 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1044 for_each_ofld_txq(vi, i, ofld_txq) {
1045 struct sysctl_oid *oid2;
1047 iqid = vi_intr_iq(vi, j)->cntxt_id;
1048 snprintf(name, sizeof(name), "%s ofld_txq%d",
1049 device_get_nameunit(vi->dev), i);
1050 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1053 snprintf(name, sizeof(name), "%d", i);
1054 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1055 name, CTLFLAG_RD, NULL, "offload tx queue");
1057 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1065 * Finally, the control queue.
1067 if (!IS_MAIN_VI(vi))
1069 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1070 NULL, "ctrl queue");
1071 ctrlq = &sc->sge.ctrlq[pi->port_id];
1072 iqid = vi_intr_iq(vi, 0)->cntxt_id;
1073 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1074 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid,
1076 rc = alloc_wrq(sc, vi, ctrlq, oid);
1080 t4_teardown_vi_queues(vi);
1089 t4_teardown_vi_queues(struct vi_info *vi)
1092 struct port_info *pi = vi->pi;
1093 struct adapter *sc = pi->adapter;
1094 struct sge_rxq *rxq;
1095 struct sge_txq *txq;
1097 struct sge_ofld_rxq *ofld_rxq;
1098 struct sge_wrq *ofld_txq;
1101 struct sge_nm_rxq *nm_rxq;
1102 struct sge_nm_txq *nm_txq;
1105 /* Do this before freeing the queues */
1106 if (vi->flags & VI_SYSCTL_CTX) {
1107 sysctl_ctx_free(&vi->ctx);
1108 vi->flags &= ~VI_SYSCTL_CTX;
1112 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1113 for_each_nm_txq(vi, i, nm_txq) {
1114 free_nm_txq(vi, nm_txq);
1117 for_each_nm_rxq(vi, i, nm_rxq) {
1118 free_nm_rxq(vi, nm_rxq);
1124 * Take down all the tx queues first, as they reference the rx queues
1125 * (for egress updates, etc.).
1129 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1131 for_each_txq(vi, i, txq) {
1135 for_each_ofld_txq(vi, i, ofld_txq) {
1136 free_wrq(sc, ofld_txq);
1141 * Then take down the rx queues that forward their interrupts, as they
1142 * reference other rx queues.
1145 for_each_rxq(vi, i, rxq) {
1146 if ((rxq->iq.flags & IQ_INTR) == 0)
1150 for_each_ofld_rxq(vi, i, ofld_rxq) {
1151 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1152 free_ofld_rxq(vi, ofld_rxq);
1157 * Then take down the rx queues that take direct interrupts.
1160 for_each_rxq(vi, i, rxq) {
1161 if (rxq->iq.flags & IQ_INTR)
1165 for_each_ofld_rxq(vi, i, ofld_rxq) {
1166 if (ofld_rxq->iq.flags & IQ_INTR)
1167 free_ofld_rxq(vi, ofld_rxq);
1175 * Deals with errors and the firmware event queue. All data rx queues forward
1176 * their interrupt to the firmware event queue.
1179 t4_intr_all(void *arg)
1181 struct adapter *sc = arg;
1182 struct sge_iq *fwq = &sc->sge.fwq;
1185 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1187 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1191 /* Deals with error interrupts */
1193 t4_intr_err(void *arg)
1195 struct adapter *sc = arg;
1197 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1198 t4_slow_intr_handler(sc);
1202 t4_intr_evt(void *arg)
1204 struct sge_iq *iq = arg;
1206 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1208 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1215 struct sge_iq *iq = arg;
1217 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1219 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1224 t4_vi_intr(void *arg)
1226 struct irq *irq = arg;
1229 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) {
1230 t4_nm_intr(irq->nm_rxq);
1231 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON);
1234 if (irq->rxq != NULL)
1239 * Deals with anything and everything on the given ingress queue.
1242 service_iq(struct sge_iq *iq, int budget)
1245 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1246 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1247 struct adapter *sc = iq->adapter;
1248 struct iq_desc *d = &iq->desc[iq->cidx];
1249 int ndescs = 0, limit;
1250 int rsp_type, refill;
1252 uint16_t fl_hw_cidx;
1254 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1255 #if defined(INET) || defined(INET6)
1256 const struct timeval lro_timeout = {0, sc->lro_timeout};
1259 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1261 limit = budget ? budget : iq->qsize / 16;
1263 if (iq->flags & IQ_HAS_FL) {
1265 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1268 fl_hw_cidx = 0; /* to silence gcc warning */
1272 * We always come back and check the descriptor ring for new indirect
1273 * interrupts and other responses after running a single handler.
1276 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1282 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1283 lq = be32toh(d->rsp.pldbuflen_qid);
1286 case X_RSPD_TYPE_FLBUF:
1288 KASSERT(iq->flags & IQ_HAS_FL,
1289 ("%s: data for an iq (%p) with no freelist",
1292 m0 = get_fl_payload(sc, fl, lq);
1293 if (__predict_false(m0 == NULL))
1295 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1296 #ifdef T4_PKT_TIMESTAMP
1298 * 60 bit timestamp for the payload is
1299 * *(uint64_t *)m0->m_pktdat. Note that it is
1300 * in the leading free-space in the mbuf. The
1301 * kernel can clobber it during a pullup,
1302 * m_copymdata, etc. You need to make sure that
1303 * the mbuf reaches you unmolested if you care
1304 * about the timestamp.
1306 *(uint64_t *)m0->m_pktdat =
1307 be64toh(ctrl->u.last_flit) &
1313 case X_RSPD_TYPE_CPL:
1314 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1315 ("%s: bad opcode %02x.", __func__,
1317 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1320 case X_RSPD_TYPE_INTR:
1323 * Interrupts should be forwarded only to queues
1324 * that are not forwarding their interrupts.
1325 * This means service_iq can recurse but only 1
1328 KASSERT(budget == 0,
1329 ("%s: budget %u, rsp_type %u", __func__,
1333 * There are 1K interrupt-capable queues (qids 0
1334 * through 1023). A response type indicating a
1335 * forwarded interrupt with a qid >= 1K is an
1336 * iWARP async notification.
1339 sc->an_handler(iq, &d->rsp);
1343 q = sc->sge.iqmap[lq - sc->sge.iq_start];
1344 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1346 if (service_iq(q, q->qsize / 16) == 0) {
1347 atomic_cmpset_int(&q->state,
1348 IQS_BUSY, IQS_IDLE);
1350 STAILQ_INSERT_TAIL(&iql, q,
1358 ("%s: illegal response type %d on iq %p",
1359 __func__, rsp_type, iq));
1361 "%s: illegal response type %d on iq %p",
1362 device_get_nameunit(sc->dev), rsp_type, iq);
1367 if (__predict_false(++iq->cidx == iq->sidx)) {
1369 iq->gen ^= F_RSPD_GEN;
1372 if (__predict_false(++ndescs == limit)) {
1373 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1375 V_INGRESSQID(iq->cntxt_id) |
1376 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1379 #if defined(INET) || defined(INET6)
1380 if (iq->flags & IQ_LRO_ENABLED &&
1381 sc->lro_timeout != 0) {
1382 tcp_lro_flush_inactive(&rxq->lro,
1388 if (iq->flags & IQ_HAS_FL) {
1390 refill_fl(sc, fl, 32);
1393 return (EINPROGRESS);
1398 refill_fl(sc, fl, 32);
1400 fl_hw_cidx = fl->hw_cidx;
1405 if (STAILQ_EMPTY(&iql))
1409 * Process the head only, and send it to the back of the list if
1410 * it's still not done.
1412 q = STAILQ_FIRST(&iql);
1413 STAILQ_REMOVE_HEAD(&iql, link);
1414 if (service_iq(q, q->qsize / 8) == 0)
1415 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1417 STAILQ_INSERT_TAIL(&iql, q, link);
1420 #if defined(INET) || defined(INET6)
1421 if (iq->flags & IQ_LRO_ENABLED) {
1422 struct lro_ctrl *lro = &rxq->lro;
1423 struct lro_entry *l;
1425 while (!SLIST_EMPTY(&lro->lro_active)) {
1426 l = SLIST_FIRST(&lro->lro_active);
1427 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1428 tcp_lro_flush(lro, l);
1433 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
1434 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1436 if (iq->flags & IQ_HAS_FL) {
1440 starved = refill_fl(sc, fl, 64);
1442 if (__predict_false(starved != 0))
1443 add_fl_to_sfl(sc, fl);
1450 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1452 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1455 MPASS(cll->region3 >= CL_METADATA_SIZE);
1460 static inline struct cluster_metadata *
1461 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1465 if (cl_has_metadata(fl, cll)) {
1466 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1468 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1474 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1476 uma_zone_t zone = arg1;
1479 uma_zfree(zone, cl);
1480 counter_u64_add(extfree_rels, 1);
1482 return (EXT_FREE_OK);
1486 * The mbuf returned by this function could be allocated from zone_mbuf or
1487 * constructed in spare room in the cluster.
1489 * The mbuf carries the payload in one of these ways
1490 * a) frame inside the mbuf (mbuf from zone_mbuf)
1491 * b) m_cljset (for clusters without metadata) zone_mbuf
1492 * c) m_extaddref (cluster with metadata) inline mbuf
1493 * d) m_extaddref (cluster with metadata) zone_mbuf
1495 static struct mbuf *
1496 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1500 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1501 struct cluster_layout *cll = &sd->cll;
1502 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1503 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1504 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1508 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1509 len = min(remaining, blen);
1510 payload = sd->cl + cll->region1 + fl->rx_offset;
1511 if (fl->flags & FL_BUF_PACKING) {
1512 const u_int l = fr_offset + len;
1513 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1515 if (fl->rx_offset + len + pad < hwb->size)
1517 MPASS(fl->rx_offset + blen <= hwb->size);
1519 MPASS(fl->rx_offset == 0); /* not packing */
1523 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1526 * Copy payload into a freshly allocated mbuf.
1529 m = fr_offset == 0 ?
1530 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1533 fl->mbuf_allocated++;
1534 #ifdef T4_PKT_TIMESTAMP
1535 /* Leave room for a timestamp */
1538 /* copy data to mbuf */
1539 bcopy(payload, mtod(m, caddr_t), len);
1541 } else if (sd->nmbuf * MSIZE < cll->region1) {
1544 * There's spare room in the cluster for an mbuf. Create one
1545 * and associate it with the payload that's in the cluster.
1549 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1550 /* No bzero required */
1551 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA,
1552 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1555 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1557 if (sd->nmbuf++ == 0)
1558 counter_u64_add(extfree_refs, 1);
1563 * Grab an mbuf from zone_mbuf and associate it with the
1564 * payload in the cluster.
1567 m = fr_offset == 0 ?
1568 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1571 fl->mbuf_allocated++;
1573 m_extaddref(m, payload, blen, &clm->refcount,
1574 rxb_free, swz->zone, sd->cl);
1575 if (sd->nmbuf++ == 0)
1576 counter_u64_add(extfree_refs, 1);
1578 m_cljset(m, sd->cl, swz->type);
1579 sd->cl = NULL; /* consumed, not a recycle candidate */
1583 m->m_pkthdr.len = remaining;
1586 if (fl->flags & FL_BUF_PACKING) {
1587 fl->rx_offset += blen;
1588 MPASS(fl->rx_offset <= hwb->size);
1589 if (fl->rx_offset < hwb->size)
1590 return (m); /* without advancing the cidx */
1593 if (__predict_false(++fl->cidx % 8 == 0)) {
1594 uint16_t cidx = fl->cidx / 8;
1596 if (__predict_false(cidx == fl->sidx))
1597 fl->cidx = cidx = 0;
1605 static struct mbuf *
1606 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1608 struct mbuf *m0, *m, **pnext;
1610 const u_int total = G_RSPD_LEN(len_newbuf);
1612 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1613 M_ASSERTPKTHDR(fl->m0);
1614 MPASS(fl->m0->m_pkthdr.len == total);
1615 MPASS(fl->remaining < total);
1619 remaining = fl->remaining;
1620 fl->flags &= ~FL_BUF_RESUME;
1624 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1626 if (__predict_false(++fl->cidx % 8 == 0)) {
1627 uint16_t cidx = fl->cidx / 8;
1629 if (__predict_false(cidx == fl->sidx))
1630 fl->cidx = cidx = 0;
1636 * Payload starts at rx_offset in the current hw buffer. Its length is
1637 * 'len' and it may span multiple hw buffers.
1640 m0 = get_scatter_segment(sc, fl, 0, total);
1643 remaining = total - m0->m_len;
1644 pnext = &m0->m_next;
1645 while (remaining > 0) {
1647 MPASS(fl->rx_offset == 0);
1648 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1649 if (__predict_false(m == NULL)) {
1652 fl->remaining = remaining;
1653 fl->flags |= FL_BUF_RESUME;
1658 remaining -= m->m_len;
1667 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1669 struct sge_rxq *rxq = iq_to_rxq(iq);
1670 struct ifnet *ifp = rxq->ifp;
1671 struct adapter *sc = iq->adapter;
1672 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1673 #if defined(INET) || defined(INET6)
1674 struct lro_ctrl *lro = &rxq->lro;
1677 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1680 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1681 m0->m_len -= sc->params.sge.fl_pktshift;
1682 m0->m_data += sc->params.sge.fl_pktshift;
1684 m0->m_pkthdr.rcvif = ifp;
1685 M_HASHTYPE_SET(m0, M_HASHTYPE_OPAQUE);
1686 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1688 if (cpl->csum_calc && !cpl->err_vec) {
1689 if (ifp->if_capenable & IFCAP_RXCSUM &&
1690 cpl->l2info & htobe32(F_RXF_IP)) {
1691 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1692 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1694 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1695 cpl->l2info & htobe32(F_RXF_IP6)) {
1696 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1701 if (__predict_false(cpl->ip_frag))
1702 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1704 m0->m_pkthdr.csum_data = 0xffff;
1708 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1709 m0->m_flags |= M_VLANTAG;
1710 rxq->vlan_extraction++;
1713 #if defined(INET) || defined(INET6)
1714 if (cpl->l2info & htobe32(F_RXF_LRO) &&
1715 iq->flags & IQ_LRO_ENABLED &&
1716 tcp_lro_rx(lro, m0, 0) == 0) {
1717 /* queued for LRO */
1720 ifp->if_input(ifp, m0);
1726 * Must drain the wrq or make sure that someone else will.
1729 wrq_tx_drain(void *arg, int n)
1731 struct sge_wrq *wrq = arg;
1732 struct sge_eq *eq = &wrq->eq;
1735 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1736 drain_wrq_wr_list(wrq->adapter, wrq);
1741 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1743 struct sge_eq *eq = &wrq->eq;
1744 u_int available, dbdiff; /* # of hardware descriptors */
1747 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1749 EQ_LOCK_ASSERT_OWNED(eq);
1750 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1751 wr = STAILQ_FIRST(&wrq->wr_list);
1752 MPASS(wr != NULL); /* Must be called with something useful to do */
1753 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
1756 eq->cidx = read_hw_cidx(eq);
1757 if (eq->pidx == eq->cidx)
1758 available = eq->sidx - 1;
1760 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1762 MPASS(wr->wrq == wrq);
1763 n = howmany(wr->wr_len, EQ_ESIZE);
1767 dst = (void *)&eq->desc[eq->pidx];
1768 if (__predict_true(eq->sidx - eq->pidx > n)) {
1769 /* Won't wrap, won't end exactly at the status page. */
1770 bcopy(&wr->wr[0], dst, wr->wr_len);
1773 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1775 bcopy(&wr->wr[0], dst, first_portion);
1776 if (wr->wr_len > first_portion) {
1777 bcopy(&wr->wr[first_portion], &eq->desc[0],
1778 wr->wr_len - first_portion);
1780 eq->pidx = n - (eq->sidx - eq->pidx);
1783 if (available < eq->sidx / 4 &&
1784 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1785 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1787 eq->equeqidx = eq->pidx;
1788 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1789 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1790 eq->equeqidx = eq->pidx;
1795 ring_eq_db(sc, eq, dbdiff);
1799 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1801 MPASS(wrq->nwr_pending > 0);
1803 MPASS(wrq->ndesc_needed >= n);
1804 wrq->ndesc_needed -= n;
1805 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1808 ring_eq_db(sc, eq, dbdiff);
1812 * Doesn't fail. Holds on to work requests it can't send right away.
1815 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1818 struct sge_eq *eq = &wrq->eq;
1821 EQ_LOCK_ASSERT_OWNED(eq);
1823 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1824 MPASS((wr->wr_len & 0x7) == 0);
1826 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1828 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1830 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1831 return; /* commit_wrq_wr will drain wr_list as well. */
1833 drain_wrq_wr_list(sc, wrq);
1835 /* Doorbell must have caught up to the pidx. */
1836 MPASS(eq->pidx == eq->dbidx);
1840 t4_update_fl_bufsize(struct ifnet *ifp)
1842 struct vi_info *vi = ifp->if_softc;
1843 struct adapter *sc = vi->pi->adapter;
1844 struct sge_rxq *rxq;
1846 struct sge_ofld_rxq *ofld_rxq;
1849 int i, maxp, mtu = ifp->if_mtu;
1851 maxp = mtu_to_max_payload(sc, mtu, 0);
1852 for_each_rxq(vi, i, rxq) {
1856 find_best_refill_source(sc, fl, maxp);
1860 maxp = mtu_to_max_payload(sc, mtu, 1);
1861 for_each_ofld_rxq(vi, i, ofld_rxq) {
1865 find_best_refill_source(sc, fl, maxp);
1872 mbuf_nsegs(struct mbuf *m)
1876 KASSERT(m->m_pkthdr.l5hlen > 0,
1877 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1879 return (m->m_pkthdr.l5hlen);
1883 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
1887 m->m_pkthdr.l5hlen = nsegs;
1891 mbuf_len16(struct mbuf *m)
1896 n = m->m_pkthdr.PH_loc.eigth[0];
1897 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
1903 set_mbuf_len16(struct mbuf *m, uint8_t len16)
1907 m->m_pkthdr.PH_loc.eigth[0] = len16;
1911 needs_tso(struct mbuf *m)
1916 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1917 KASSERT(m->m_pkthdr.tso_segsz > 0,
1918 ("%s: TSO requested in mbuf %p but MSS not provided",
1927 needs_l3_csum(struct mbuf *m)
1932 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
1938 needs_l4_csum(struct mbuf *m)
1943 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
1944 CSUM_TCP_IPV6 | CSUM_TSO))
1950 needs_vlan_insertion(struct mbuf *m)
1955 if (m->m_flags & M_VLANTAG) {
1956 KASSERT(m->m_pkthdr.ether_vtag != 0,
1957 ("%s: HWVLAN requested in mbuf %p but tag not provided",
1965 m_advance(struct mbuf **pm, int *poffset, int len)
1967 struct mbuf *m = *pm;
1968 int offset = *poffset;
1974 if (offset + len < m->m_len) {
1976 p = mtod(m, uintptr_t) + offset;
1979 len -= m->m_len - offset;
1990 same_paddr(char *a, char *b)
1995 else if (a != NULL && b != NULL) {
1996 vm_offset_t x = (vm_offset_t)a;
1997 vm_offset_t y = (vm_offset_t)b;
1999 if ((x & PAGE_MASK) == (y & PAGE_MASK) &&
2000 pmap_kextract(x) == pmap_kextract(y))
2008 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2009 * must have at least one mbuf that's not empty.
2012 count_mbuf_nsegs(struct mbuf *m)
2014 char *prev_end, *start;
2021 for (; m; m = m->m_next) {
2024 if (__predict_false(len == 0))
2026 start = mtod(m, char *);
2028 nsegs += sglist_count(start, len);
2029 if (same_paddr(prev_end, start))
2031 prev_end = start + len;
2039 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2040 * a) caller can assume it's been freed if this function returns with an error.
2041 * b) it may get defragged up if the gather list is too long for the hardware.
2044 parse_pkt(struct mbuf **mp)
2046 struct mbuf *m0 = *mp, *m;
2047 int rc, nsegs, defragged = 0, offset;
2048 struct ether_header *eh;
2050 #if defined(INET) || defined(INET6)
2056 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2065 * First count the number of gather list segments in the payload.
2066 * Defrag the mbuf if nsegs exceeds the hardware limit.
2069 MPASS(m0->m_pkthdr.len > 0);
2070 nsegs = count_mbuf_nsegs(m0);
2071 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2072 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2076 *mp = m0 = m; /* update caller's copy after defrag */
2080 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2081 m0 = m_pullup(m0, m0->m_pkthdr.len);
2083 /* Should have left well enough alone. */
2087 *mp = m0; /* update caller's copy after pullup */
2090 set_mbuf_nsegs(m0, nsegs);
2091 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2097 eh = mtod(m, struct ether_header *);
2098 eh_type = ntohs(eh->ether_type);
2099 if (eh_type == ETHERTYPE_VLAN) {
2100 struct ether_vlan_header *evh = (void *)eh;
2102 eh_type = ntohs(evh->evl_proto);
2103 m0->m_pkthdr.l2hlen = sizeof(*evh);
2105 m0->m_pkthdr.l2hlen = sizeof(*eh);
2108 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2112 case ETHERTYPE_IPV6:
2114 struct ip6_hdr *ip6 = l3hdr;
2116 MPASS(ip6->ip6_nxt == IPPROTO_TCP);
2118 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2125 struct ip *ip = l3hdr;
2127 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2132 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2133 " with the same INET/INET6 options as the kernel.",
2137 #if defined(INET) || defined(INET6)
2138 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2139 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2146 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2148 struct sge_eq *eq = &wrq->eq;
2149 struct adapter *sc = wrq->adapter;
2150 int ndesc, available;
2155 ndesc = howmany(len16, EQ_ESIZE / 16);
2156 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2160 if (!STAILQ_EMPTY(&wrq->wr_list))
2161 drain_wrq_wr_list(sc, wrq);
2163 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2166 wr = alloc_wrqe(len16 * 16, wrq);
2167 if (__predict_false(wr == NULL))
2170 cookie->ndesc = ndesc;
2174 eq->cidx = read_hw_cidx(eq);
2175 if (eq->pidx == eq->cidx)
2176 available = eq->sidx - 1;
2178 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2179 if (available < ndesc)
2182 cookie->pidx = eq->pidx;
2183 cookie->ndesc = ndesc;
2184 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2186 w = &eq->desc[eq->pidx];
2187 IDXINCR(eq->pidx, ndesc, eq->sidx);
2188 if (__predict_false(eq->pidx < ndesc - 1)) {
2190 wrq->ss_pidx = cookie->pidx;
2191 wrq->ss_len = len16 * 16;
2200 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2202 struct sge_eq *eq = &wrq->eq;
2203 struct adapter *sc = wrq->adapter;
2205 struct wrq_cookie *prev, *next;
2207 if (cookie->pidx == -1) {
2208 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2214 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2215 pidx = cookie->pidx;
2216 MPASS(pidx >= 0 && pidx < eq->sidx);
2217 if (__predict_false(w == &wrq->ss[0])) {
2218 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2220 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2221 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2222 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2225 wrq->tx_wrs_direct++;
2228 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2229 next = TAILQ_NEXT(cookie, link);
2231 MPASS(pidx == eq->dbidx);
2232 if (next == NULL || ndesc >= 16)
2233 ring_eq_db(wrq->adapter, eq, ndesc);
2235 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2237 next->ndesc += ndesc;
2240 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2241 prev->ndesc += ndesc;
2243 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2245 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2246 drain_wrq_wr_list(sc, wrq);
2249 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2250 /* Doorbell must have caught up to the pidx. */
2251 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2258 can_resume_eth_tx(struct mp_ring *r)
2260 struct sge_eq *eq = r->cookie;
2262 return (total_available_tx_desc(eq) > eq->sidx / 8);
2266 cannot_use_txpkts(struct mbuf *m)
2268 /* maybe put a GL limit too, to avoid silliness? */
2270 return (needs_tso(m));
2274 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2275 * be consumed. Return the actual number consumed. 0 indicates a stall.
2278 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2280 struct sge_txq *txq = r->cookie;
2281 struct sge_eq *eq = &txq->eq;
2282 struct ifnet *ifp = txq->ifp;
2283 struct vi_info *vi = ifp->if_softc;
2284 struct port_info *pi = vi->pi;
2285 struct adapter *sc = pi->adapter;
2286 u_int total, remaining; /* # of packets */
2287 u_int available, dbdiff; /* # of hardware descriptors */
2289 struct mbuf *m0, *tail;
2291 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2293 remaining = IDXDIFF(pidx, cidx, r->size);
2294 MPASS(remaining > 0); /* Must not be called without work to do. */
2298 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) {
2299 while (cidx != pidx) {
2300 m0 = r->items[cidx];
2302 if (++cidx == r->size)
2305 reclaim_tx_descs(txq, 2048);
2310 /* How many hardware descriptors do we have readily available. */
2311 if (eq->pidx == eq->cidx)
2312 available = eq->sidx - 1;
2314 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2315 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2317 while (remaining > 0) {
2319 m0 = r->items[cidx];
2321 MPASS(m0->m_nextpkt == NULL);
2323 if (available < SGE_MAX_WR_NDESC) {
2324 available += reclaim_tx_descs(txq, 64);
2325 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2326 break; /* out of descriptors */
2329 next_cidx = cidx + 1;
2330 if (__predict_false(next_cidx == r->size))
2333 wr = (void *)&eq->desc[eq->pidx];
2334 if (remaining > 1 &&
2335 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2337 /* pkts at cidx, next_cidx should both be in txp. */
2338 MPASS(txp.npkt == 2);
2339 tail = r->items[next_cidx];
2340 MPASS(tail->m_nextpkt == NULL);
2341 ETHER_BPF_MTAP(ifp, m0);
2342 ETHER_BPF_MTAP(ifp, tail);
2343 m0->m_nextpkt = tail;
2345 if (__predict_false(++next_cidx == r->size))
2348 while (next_cidx != pidx) {
2349 if (add_to_txpkts(r->items[next_cidx], &txp,
2352 tail->m_nextpkt = r->items[next_cidx];
2353 tail = tail->m_nextpkt;
2354 ETHER_BPF_MTAP(ifp, tail);
2355 if (__predict_false(++next_cidx == r->size))
2359 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2361 remaining -= txp.npkt;
2365 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2366 ETHER_BPF_MTAP(ifp, m0);
2368 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2372 IDXINCR(eq->pidx, n, eq->sidx);
2374 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2375 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2376 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2378 eq->equeqidx = eq->pidx;
2379 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2380 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2381 eq->equeqidx = eq->pidx;
2384 if (dbdiff >= 16 && remaining >= 4) {
2385 ring_eq_db(sc, eq, dbdiff);
2386 available += reclaim_tx_descs(txq, 4 * dbdiff);
2393 ring_eq_db(sc, eq, dbdiff);
2394 reclaim_tx_descs(txq, 32);
2403 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2407 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2408 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2409 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2410 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2414 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2415 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2416 if (pktc_idx >= 0) {
2417 iq->intr_params |= F_QINTR_CNT_EN;
2418 iq->intr_pktc_idx = pktc_idx;
2420 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2421 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2425 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2429 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2430 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2431 if (sc->flags & BUF_PACKING_OK &&
2432 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2433 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2434 fl->flags |= FL_BUF_PACKING;
2435 find_best_refill_source(sc, fl, maxp);
2436 find_safe_refill_source(sc, fl);
2440 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2441 uint8_t tx_chan, uint16_t iqid, char *name)
2443 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2445 eq->flags = eqtype & EQ_TYPEMASK;
2446 eq->tx_chan = tx_chan;
2448 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2449 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2453 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2454 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2458 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2459 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2461 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2465 rc = bus_dmamem_alloc(*tag, va,
2466 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2468 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2472 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2474 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2479 free_ring(sc, *tag, *map, *pa, *va);
2485 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2486 bus_addr_t pa, void *va)
2489 bus_dmamap_unload(tag, map);
2491 bus_dmamem_free(tag, va, map);
2493 bus_dma_tag_destroy(tag);
2499 * Allocates the ring for an ingress queue and an optional freelist. If the
2500 * freelist is specified it will be allocated and then associated with the
2503 * Returns errno on failure. Resources allocated up to that point may still be
2504 * allocated. Caller is responsible for cleanup in case this function fails.
2506 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2507 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2508 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2511 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2512 int intr_idx, int cong)
2514 int rc, i, cntxt_id;
2517 struct port_info *pi = vi->pi;
2518 struct adapter *sc = iq->adapter;
2519 struct sge_params *sp = &sc->params.sge;
2522 len = iq->qsize * IQ_ESIZE;
2523 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2524 (void **)&iq->desc);
2528 bzero(&c, sizeof(c));
2529 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2530 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2531 V_FW_IQ_CMD_VFN(0));
2533 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2536 /* Special handling for firmware event queue */
2537 if (iq == &sc->sge.fwq)
2538 v |= F_FW_IQ_CMD_IQASYNCH;
2540 if (iq->flags & IQ_INTR) {
2541 KASSERT(intr_idx < sc->intr_count,
2542 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2544 v |= F_FW_IQ_CMD_IQANDST;
2545 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2547 c.type_to_iqandstindex = htobe32(v |
2548 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2549 V_FW_IQ_CMD_VIID(vi->viid) |
2550 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2551 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2552 F_FW_IQ_CMD_IQGTSMODE |
2553 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2554 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2555 c.iqsize = htobe16(iq->qsize);
2556 c.iqaddr = htobe64(iq->ba);
2558 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2561 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2563 len = fl->qsize * EQ_ESIZE;
2564 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2565 &fl->ba, (void **)&fl->desc);
2569 /* Allocate space for one software descriptor per buffer. */
2570 rc = alloc_fl_sdesc(fl);
2572 device_printf(sc->dev,
2573 "failed to setup fl software descriptors: %d\n",
2578 if (fl->flags & FL_BUF_PACKING) {
2579 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2580 fl->buf_boundary = sp->pack_boundary;
2582 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2583 fl->buf_boundary = 16;
2585 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2586 fl->buf_boundary = sp->pad_boundary;
2588 c.iqns_to_fl0congen |=
2589 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2590 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2591 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2592 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2595 c.iqns_to_fl0congen |=
2596 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2597 F_FW_IQ_CMD_FL0CONGCIF |
2598 F_FW_IQ_CMD_FL0CONGEN);
2600 c.fl0dcaen_to_fl0cidxfthresh =
2601 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |
2602 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
2603 c.fl0size = htobe16(fl->qsize);
2604 c.fl0addr = htobe64(fl->ba);
2607 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2609 device_printf(sc->dev,
2610 "failed to create ingress queue: %d\n", rc);
2615 iq->gen = F_RSPD_GEN;
2616 iq->intr_next = iq->intr_params;
2617 iq->cntxt_id = be16toh(c.iqid);
2618 iq->abs_id = be16toh(c.physiqid);
2619 iq->flags |= IQ_ALLOCATED;
2621 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2622 if (cntxt_id >= sc->sge.niq) {
2623 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2624 cntxt_id, sc->sge.niq - 1);
2626 sc->sge.iqmap[cntxt_id] = iq;
2631 iq->flags |= IQ_HAS_FL;
2632 fl->cntxt_id = be16toh(c.fl0id);
2633 fl->pidx = fl->cidx = 0;
2635 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2636 if (cntxt_id >= sc->sge.neq) {
2637 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2638 __func__, cntxt_id, sc->sge.neq - 1);
2640 sc->sge.eqmap[cntxt_id] = (void *)fl;
2643 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2644 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2645 uint32_t mask = (1 << s_qpp) - 1;
2646 volatile uint8_t *udb;
2648 udb = sc->udbs_base + UDBS_DB_OFFSET;
2649 udb += (qid >> s_qpp) << PAGE_SHIFT;
2651 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2652 udb += qid << UDBS_SEG_SHIFT;
2655 fl->udb = (volatile void *)udb;
2657 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2660 /* Enough to make sure the SGE doesn't think it's starved */
2661 refill_fl(sc, fl, fl->lowat);
2665 if (is_t5(sc) && cong >= 0) {
2666 uint32_t param, val;
2668 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2669 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2670 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2675 for (i = 0; i < 4; i++) {
2676 if (cong & (1 << i))
2677 val |= 1 << (i << 2);
2681 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2683 /* report error but carry on */
2684 device_printf(sc->dev,
2685 "failed to set congestion manager context for "
2686 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2690 /* Enable IQ interrupts */
2691 atomic_store_rel_int(&iq->state, IQS_IDLE);
2692 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
2693 V_INGRESSQID(iq->cntxt_id));
2699 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2702 struct adapter *sc = iq->adapter;
2706 return (0); /* nothing to do */
2708 dev = vi ? vi->dev : sc->dev;
2710 if (iq->flags & IQ_ALLOCATED) {
2711 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2712 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2713 fl ? fl->cntxt_id : 0xffff, 0xffff);
2716 "failed to free queue %p: %d\n", iq, rc);
2719 iq->flags &= ~IQ_ALLOCATED;
2722 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2724 bzero(iq, sizeof(*iq));
2727 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2731 free_fl_sdesc(sc, fl);
2733 if (mtx_initialized(&fl->fl_lock))
2734 mtx_destroy(&fl->fl_lock);
2736 bzero(fl, sizeof(*fl));
2743 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
2746 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2748 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2750 children = SYSCTL_CHILDREN(oid);
2752 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2753 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2754 "SGE context id of the freelist");
2755 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2756 fl_pad ? 1 : 0, "padding enabled");
2757 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2758 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2759 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2760 0, "consumer index");
2761 if (fl->flags & FL_BUF_PACKING) {
2762 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2763 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2765 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2766 0, "producer index");
2767 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2768 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2769 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2770 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2771 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2772 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2773 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2774 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2775 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2776 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2780 alloc_fwq(struct adapter *sc)
2783 struct sge_iq *fwq = &sc->sge.fwq;
2784 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2785 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2787 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2788 fwq->flags |= IQ_INTR; /* always */
2789 intr_idx = sc->intr_count > 1 ? 1 : 0;
2790 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
2792 device_printf(sc->dev,
2793 "failed to create firmware event queue: %d\n", rc);
2797 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2798 NULL, "firmware event queue");
2799 children = SYSCTL_CHILDREN(oid);
2801 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2802 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2803 "absolute id of the queue");
2804 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2805 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2806 "SGE context id of the queue");
2807 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2808 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2815 free_fwq(struct adapter *sc)
2817 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2821 alloc_mgmtq(struct adapter *sc)
2824 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2826 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2827 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2829 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2830 NULL, "management queue");
2832 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2833 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2834 sc->sge.fwq.cntxt_id, name);
2835 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2837 device_printf(sc->dev,
2838 "failed to create management queue: %d\n", rc);
2846 free_mgmtq(struct adapter *sc)
2849 return free_wrq(sc, &sc->sge.mgmtq);
2853 tnl_cong(struct port_info *pi, int drop)
2861 return (pi->rx_chan_map);
2865 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
2866 struct sysctl_oid *oid)
2869 struct sysctl_oid_list *children;
2872 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
2873 tnl_cong(vi->pi, cong_drop));
2878 * The freelist is just barely above the starvation threshold right now,
2879 * fill it up a bit more.
2882 refill_fl(vi->pi->adapter, &rxq->fl, 128);
2883 FL_UNLOCK(&rxq->fl);
2885 #if defined(INET) || defined(INET6)
2886 rc = tcp_lro_init(&rxq->lro);
2889 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */
2891 if (vi->ifp->if_capenable & IFCAP_LRO)
2892 rxq->iq.flags |= IQ_LRO_ENABLED;
2896 children = SYSCTL_CHILDREN(oid);
2898 snprintf(name, sizeof(name), "%d", idx);
2899 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2901 children = SYSCTL_CHILDREN(oid);
2903 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
2904 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
2905 "absolute id of the queue");
2906 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
2907 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
2908 "SGE context id of the queue");
2909 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
2910 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
2912 #if defined(INET) || defined(INET6)
2913 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
2914 &rxq->lro.lro_queued, 0, NULL);
2915 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
2916 &rxq->lro.lro_flushed, 0, NULL);
2918 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
2919 &rxq->rxcsum, "# of times hardware assisted with checksum");
2920 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
2921 CTLFLAG_RD, &rxq->vlan_extraction,
2922 "# of times hardware extracted 802.1Q tag");
2924 add_fl_sysctls(&vi->ctx, oid, &rxq->fl);
2930 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
2934 #if defined(INET) || defined(INET6)
2936 tcp_lro_free(&rxq->lro);
2937 rxq->lro.ifp = NULL;
2941 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
2943 bzero(rxq, sizeof(*rxq));
2950 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
2951 int intr_idx, int idx, struct sysctl_oid *oid)
2954 struct sysctl_oid_list *children;
2957 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
2958 vi->pi->rx_chan_map);
2962 children = SYSCTL_CHILDREN(oid);
2964 snprintf(name, sizeof(name), "%d", idx);
2965 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2967 children = SYSCTL_CHILDREN(oid);
2969 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
2970 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
2971 "I", "absolute id of the queue");
2972 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
2973 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
2974 "I", "SGE context id of the queue");
2975 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
2976 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
2979 add_fl_sysctls(&vi->ctx, oid, &ofld_rxq->fl);
2985 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
2989 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
2991 bzero(ofld_rxq, sizeof(*ofld_rxq));
2999 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3000 int idx, struct sysctl_oid *oid)
3003 struct sysctl_oid_list *children;
3004 struct sysctl_ctx_list *ctx;
3007 struct adapter *sc = vi->pi->adapter;
3008 struct netmap_adapter *na = NA(vi->ifp);
3012 len = vi->qsize_rxq * IQ_ESIZE;
3013 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3014 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3018 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3019 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3020 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3026 nm_rxq->iq_cidx = 0;
3027 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3028 nm_rxq->iq_gen = F_RSPD_GEN;
3029 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3030 nm_rxq->fl_sidx = na->num_rx_desc;
3031 nm_rxq->intr_idx = intr_idx;
3034 children = SYSCTL_CHILDREN(oid);
3036 snprintf(name, sizeof(name), "%d", idx);
3037 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3039 children = SYSCTL_CHILDREN(oid);
3041 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3042 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3043 "I", "absolute id of the queue");
3044 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3045 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3046 "I", "SGE context id of the queue");
3047 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3048 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3051 children = SYSCTL_CHILDREN(oid);
3052 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3054 children = SYSCTL_CHILDREN(oid);
3056 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3057 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3058 "I", "SGE context id of the freelist");
3059 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3060 &nm_rxq->fl_cidx, 0, "consumer index");
3061 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3062 &nm_rxq->fl_pidx, 0, "producer index");
3069 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3071 struct adapter *sc = vi->pi->adapter;
3073 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3075 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3082 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3083 struct sysctl_oid *oid)
3087 struct port_info *pi = vi->pi;
3088 struct adapter *sc = pi->adapter;
3089 struct netmap_adapter *na = NA(vi->ifp);
3091 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3093 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3094 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3095 &nm_txq->ba, (void **)&nm_txq->desc);
3099 nm_txq->pidx = nm_txq->cidx = 0;
3100 nm_txq->sidx = na->num_tx_desc;
3102 nm_txq->iqidx = iqidx;
3103 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3104 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) |
3105 V_TXPKT_VF(vi->viid));
3107 snprintf(name, sizeof(name), "%d", idx);
3108 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3109 NULL, "netmap tx queue");
3110 children = SYSCTL_CHILDREN(oid);
3112 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3113 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3114 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3115 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3117 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3118 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3125 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3127 struct adapter *sc = vi->pi->adapter;
3129 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3137 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3140 struct fw_eq_ctrl_cmd c;
3141 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3143 bzero(&c, sizeof(c));
3145 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3146 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3147 V_FW_EQ_CTRL_CMD_VFN(0));
3148 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3149 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3150 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3151 c.physeqid_pkd = htobe32(0);
3152 c.fetchszm_to_iqid =
3153 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3154 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3155 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3157 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3158 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3159 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3160 c.eqaddr = htobe64(eq->ba);
3162 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3164 device_printf(sc->dev,
3165 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3168 eq->flags |= EQ_ALLOCATED;
3170 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3171 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3172 if (cntxt_id >= sc->sge.neq)
3173 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3174 cntxt_id, sc->sge.neq - 1);
3175 sc->sge.eqmap[cntxt_id] = eq;
3181 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3184 struct fw_eq_eth_cmd c;
3185 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3187 bzero(&c, sizeof(c));
3189 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3190 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3191 V_FW_EQ_ETH_CMD_VFN(0));
3192 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3193 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3194 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3195 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3196 c.fetchszm_to_iqid =
3197 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3198 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3199 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3200 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3201 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3202 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3203 c.eqaddr = htobe64(eq->ba);
3205 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3207 device_printf(vi->dev,
3208 "failed to create Ethernet egress queue: %d\n", rc);
3211 eq->flags |= EQ_ALLOCATED;
3213 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3214 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3215 if (cntxt_id >= sc->sge.neq)
3216 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3217 cntxt_id, sc->sge.neq - 1);
3218 sc->sge.eqmap[cntxt_id] = eq;
3225 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3228 struct fw_eq_ofld_cmd c;
3229 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3231 bzero(&c, sizeof(c));
3233 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3234 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3235 V_FW_EQ_OFLD_CMD_VFN(0));
3236 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3237 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3238 c.fetchszm_to_iqid =
3239 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3240 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3241 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3243 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3244 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3245 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3246 c.eqaddr = htobe64(eq->ba);
3248 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3250 device_printf(vi->dev,
3251 "failed to create egress queue for TCP offload: %d\n", rc);
3254 eq->flags |= EQ_ALLOCATED;
3256 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3257 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3258 if (cntxt_id >= sc->sge.neq)
3259 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3260 cntxt_id, sc->sge.neq - 1);
3261 sc->sge.eqmap[cntxt_id] = eq;
3268 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3273 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3275 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3276 len = qsize * EQ_ESIZE;
3277 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3278 &eq->ba, (void **)&eq->desc);
3282 eq->pidx = eq->cidx = 0;
3283 eq->equeqidx = eq->dbidx = 0;
3284 eq->doorbells = sc->doorbells;
3286 switch (eq->flags & EQ_TYPEMASK) {
3288 rc = ctrl_eq_alloc(sc, eq);
3292 rc = eth_eq_alloc(sc, vi, eq);
3297 rc = ofld_eq_alloc(sc, vi, eq);
3302 panic("%s: invalid eq type %d.", __func__,
3303 eq->flags & EQ_TYPEMASK);
3306 device_printf(sc->dev,
3307 "failed to allocate egress queue(%d): %d\n",
3308 eq->flags & EQ_TYPEMASK, rc);
3311 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3312 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3313 isset(&eq->doorbells, DOORBELL_WCWR)) {
3314 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3315 uint32_t mask = (1 << s_qpp) - 1;
3316 volatile uint8_t *udb;
3318 udb = sc->udbs_base + UDBS_DB_OFFSET;
3319 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3320 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3321 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3322 clrbit(&eq->doorbells, DOORBELL_WCWR);
3324 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3327 eq->udb = (volatile void *)udb;
3334 free_eq(struct adapter *sc, struct sge_eq *eq)
3338 if (eq->flags & EQ_ALLOCATED) {
3339 switch (eq->flags & EQ_TYPEMASK) {
3341 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3346 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3352 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3358 panic("%s: invalid eq type %d.", __func__,
3359 eq->flags & EQ_TYPEMASK);
3362 device_printf(sc->dev,
3363 "failed to free egress queue (%d): %d\n",
3364 eq->flags & EQ_TYPEMASK, rc);
3367 eq->flags &= ~EQ_ALLOCATED;
3370 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3372 if (mtx_initialized(&eq->eq_lock))
3373 mtx_destroy(&eq->eq_lock);
3375 bzero(eq, sizeof(*eq));
3380 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3381 struct sysctl_oid *oid)
3384 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3385 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3387 rc = alloc_eq(sc, vi, &wrq->eq);
3392 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3393 TAILQ_INIT(&wrq->incomplete_wrs);
3394 STAILQ_INIT(&wrq->wr_list);
3395 wrq->nwr_pending = 0;
3396 wrq->ndesc_needed = 0;
3398 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3399 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3400 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3401 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3403 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3404 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3406 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3407 &wrq->tx_wrs_direct, "# of work requests (direct)");
3408 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3409 &wrq->tx_wrs_copied, "# of work requests (copied)");
3415 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3419 rc = free_eq(sc, &wrq->eq);
3423 bzero(wrq, sizeof(*wrq));
3428 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3429 struct sysctl_oid *oid)
3432 struct port_info *pi = vi->pi;
3433 struct adapter *sc = pi->adapter;
3434 struct sge_eq *eq = &txq->eq;
3436 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3438 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3441 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3445 rc = alloc_eq(sc, vi, eq);
3447 mp_ring_free(txq->r);
3452 /* Can't fail after this point. */
3454 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3456 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3457 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3458 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) |
3459 V_TXPKT_VF(vi->viid));
3460 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3463 snprintf(name, sizeof(name), "%d", idx);
3464 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3466 children = SYSCTL_CHILDREN(oid);
3468 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3469 &eq->cntxt_id, 0, "SGE context id of the queue");
3470 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3471 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3473 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3474 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3477 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3478 &txq->txcsum, "# of times hardware assisted with checksum");
3479 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3480 CTLFLAG_RD, &txq->vlan_insertion,
3481 "# of times hardware inserted 802.1Q tag");
3482 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3483 &txq->tso_wrs, "# of TSO work requests");
3484 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3485 &txq->imm_wrs, "# of work requests with immediate data");
3486 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3487 &txq->sgl_wrs, "# of work requests with direct SGL");
3488 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3489 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3490 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3491 CTLFLAG_RD, &txq->txpkts0_wrs,
3492 "# of txpkts (type 0) work requests");
3493 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3494 CTLFLAG_RD, &txq->txpkts1_wrs,
3495 "# of txpkts (type 1) work requests");
3496 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3497 CTLFLAG_RD, &txq->txpkts0_pkts,
3498 "# of frames tx'd using type0 txpkts work requests");
3499 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3500 CTLFLAG_RD, &txq->txpkts1_pkts,
3501 "# of frames tx'd using type1 txpkts work requests");
3503 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3504 CTLFLAG_RD, &txq->r->enqueues,
3505 "# of enqueues to the mp_ring for this queue");
3506 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3507 CTLFLAG_RD, &txq->r->drops,
3508 "# of drops in the mp_ring for this queue");
3509 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3510 CTLFLAG_RD, &txq->r->starts,
3511 "# of normal consumer starts in the mp_ring for this queue");
3512 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3513 CTLFLAG_RD, &txq->r->stalls,
3514 "# of consumer stalls in the mp_ring for this queue");
3515 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3516 CTLFLAG_RD, &txq->r->restarts,
3517 "# of consumer restarts in the mp_ring for this queue");
3518 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3519 CTLFLAG_RD, &txq->r->abdications,
3520 "# of consumer abdications in the mp_ring for this queue");
3526 free_txq(struct vi_info *vi, struct sge_txq *txq)
3529 struct adapter *sc = vi->pi->adapter;
3530 struct sge_eq *eq = &txq->eq;
3532 rc = free_eq(sc, eq);
3536 sglist_free(txq->gl);
3537 free(txq->sdesc, M_CXGBE);
3538 mp_ring_free(txq->r);
3540 bzero(txq, sizeof(*txq));
3545 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3547 bus_addr_t *ba = arg;
3550 ("%s meant for single segment mappings only.", __func__));
3552 *ba = error ? 0 : segs->ds_addr;
3556 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3560 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3564 v = fl->dbval | V_PIDX(n);
3566 *fl->udb = htole32(v);
3568 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
3569 IDXINCR(fl->dbidx, n, fl->sidx);
3573 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are
3574 * recycled do not count towards this allocation budget.
3576 * Returns non-zero to indicate that this freelist should be added to the list
3577 * of starving freelists.
3580 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3583 struct fl_sdesc *sd;
3586 struct cluster_layout *cll;
3587 struct sw_zone_info *swz;
3588 struct cluster_metadata *clm;
3590 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3592 FL_LOCK_ASSERT_OWNED(fl);
3595 * We always stop at the begining of the hardware descriptor that's just
3596 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3597 * which would mean an empty freelist to the chip.
3599 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3600 if (fl->pidx == max_pidx * 8)
3603 d = &fl->desc[fl->pidx];
3604 sd = &fl->sdesc[fl->pidx];
3605 cll = &fl->cll_def; /* default layout */
3606 swz = &sc->sge.sw_zone_info[cll->zidx];
3610 if (sd->cl != NULL) {
3612 if (sd->nmbuf == 0) {
3614 * Fast recycle without involving any atomics on
3615 * the cluster's metadata (if the cluster has
3616 * metadata). This happens when all frames
3617 * received in the cluster were small enough to
3618 * fit within a single mbuf each.
3620 fl->cl_fast_recycled++;
3622 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3624 MPASS(clm->refcount == 1);
3630 * Cluster is guaranteed to have metadata. Clusters
3631 * without metadata always take the fast recycle path
3632 * when they're recycled.
3634 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3637 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3639 counter_u64_add(extfree_rels, 1);
3642 sd->cl = NULL; /* gave up my reference */
3644 MPASS(sd->cl == NULL);
3646 cl = uma_zalloc(swz->zone, M_NOWAIT);
3647 if (__predict_false(cl == NULL)) {
3648 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3649 fl->cll_def.zidx == fl->cll_alt.zidx)
3652 /* fall back to the safe zone */
3654 swz = &sc->sge.sw_zone_info[cll->zidx];
3660 pa = pmap_kextract((vm_offset_t)cl);
3664 *d = htobe64(pa | cll->hwidx);
3665 clm = cl_metadata(sc, fl, cll, cl);
3677 if (__predict_false(++fl->pidx % 8 == 0)) {
3678 uint16_t pidx = fl->pidx / 8;
3680 if (__predict_false(pidx == fl->sidx)) {
3686 if (pidx == max_pidx)
3689 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3694 if (fl->pidx / 8 != fl->dbidx)
3697 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3701 * Attempt to refill all starving freelists.
3704 refill_sfl(void *arg)
3706 struct adapter *sc = arg;
3707 struct sge_fl *fl, *fl_temp;
3709 mtx_assert(&sc->sfl_lock, MA_OWNED);
3710 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3712 refill_fl(sc, fl, 64);
3713 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3714 TAILQ_REMOVE(&sc->sfl, fl, link);
3715 fl->flags &= ~FL_STARVING;
3720 if (!TAILQ_EMPTY(&sc->sfl))
3721 callout_schedule(&sc->sfl_callout, hz / 5);
3725 alloc_fl_sdesc(struct sge_fl *fl)
3728 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3735 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3737 struct fl_sdesc *sd;
3738 struct cluster_metadata *clm;
3739 struct cluster_layout *cll;
3743 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3748 clm = cl_metadata(sc, fl, cll, sd->cl);
3750 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3751 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3752 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3753 counter_u64_add(extfree_rels, 1);
3758 free(fl->sdesc, M_CXGBE);
3763 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3770 rc = sglist_append_mbuf(gl, m);
3771 if (__predict_false(rc != 0)) {
3772 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3773 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3776 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3777 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3778 mbuf_nsegs(m), gl->sg_nseg));
3779 KASSERT(gl->sg_nseg > 0 &&
3780 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3781 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3782 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
3786 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
3789 txpkt_len16(u_int nsegs, u_int tso)
3795 nsegs--; /* first segment is part of ulptx_sgl */
3796 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
3797 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3799 n += sizeof(struct cpl_tx_pkt_lso_core);
3801 return (howmany(n, 16));
3805 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
3809 txpkts0_len16(u_int nsegs)
3815 nsegs--; /* first segment is part of ulptx_sgl */
3816 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
3817 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
3818 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3820 return (howmany(n, 16));
3824 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
3832 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
3834 return (howmany(n, 16));
3838 imm_payload(u_int ndesc)
3842 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
3843 sizeof(struct cpl_tx_pkt_core);
3849 * Write a txpkt WR for this packet to the hardware descriptors, update the
3850 * software descriptor, and advance the pidx. It is guaranteed that enough
3851 * descriptors are available.
3853 * The return value is the # of hardware descriptors used.
3856 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
3857 struct mbuf *m0, u_int available)
3859 struct sge_eq *eq = &txq->eq;
3860 struct tx_sdesc *txsd;
3861 struct cpl_tx_pkt_core *cpl;
3862 uint32_t ctrl; /* used in many unrelated places */
3864 int len16, ndesc, pktlen, nsegs;
3867 TXQ_LOCK_ASSERT_OWNED(txq);
3869 MPASS(available > 0 && available < eq->sidx);
3871 len16 = mbuf_len16(m0);
3872 nsegs = mbuf_nsegs(m0);
3873 pktlen = m0->m_pkthdr.len;
3874 ctrl = sizeof(struct cpl_tx_pkt_core);
3876 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
3877 else if (pktlen <= imm_payload(2) && available >= 2) {
3878 /* Immediate data. Recalculate len16 and set nsegs to 0. */
3880 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
3881 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
3884 ndesc = howmany(len16, EQ_ESIZE / 16);
3885 MPASS(ndesc <= available);
3887 /* Firmware work request header */
3888 MPASS(wr == (void *)&eq->desc[eq->pidx]);
3889 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
3890 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
3892 ctrl = V_FW_WR_LEN16(len16);
3893 wr->equiq_to_len16 = htobe32(ctrl);
3896 if (needs_tso(m0)) {
3897 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
3899 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
3900 m0->m_pkthdr.l4hlen > 0,
3901 ("%s: mbuf %p needs TSO but missing header lengths",
3904 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
3905 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
3906 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
3907 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
3908 ctrl |= V_LSO_ETHHDR_LEN(1);
3909 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
3912 lso->lso_ctrl = htobe32(ctrl);
3913 lso->ipid_ofst = htobe16(0);
3914 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
3915 lso->seqno_offset = htobe32(0);
3916 lso->len = htobe32(pktlen);
3918 cpl = (void *)(lso + 1);
3922 cpl = (void *)(wr + 1);
3924 /* Checksum offload */
3926 if (needs_l3_csum(m0) == 0)
3927 ctrl1 |= F_TXPKT_IPCSUM_DIS;
3928 if (needs_l4_csum(m0) == 0)
3929 ctrl1 |= F_TXPKT_L4CSUM_DIS;
3930 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3931 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3932 txq->txcsum++; /* some hardware assistance provided */
3934 /* VLAN tag insertion */
3935 if (needs_vlan_insertion(m0)) {
3936 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
3937 txq->vlan_insertion++;
3941 cpl->ctrl0 = txq->cpl_ctrl0;
3943 cpl->len = htobe16(pktlen);
3944 cpl->ctrl1 = htobe64(ctrl1);
3947 dst = (void *)(cpl + 1);
3950 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
3955 for (m = m0; m != NULL; m = m->m_next) {
3956 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
3962 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
3969 txsd = &txq->sdesc[eq->pidx];
3971 txsd->desc_used = ndesc;
3977 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
3979 u_int needed, nsegs1, nsegs2, l1, l2;
3981 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
3984 nsegs1 = mbuf_nsegs(m);
3985 nsegs2 = mbuf_nsegs(n);
3986 if (nsegs1 + nsegs2 == 2) {
3988 l1 = l2 = txpkts1_len16();
3991 l1 = txpkts0_len16(nsegs1);
3992 l2 = txpkts0_len16(nsegs2);
3994 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
3995 needed = howmany(txp->len16, EQ_ESIZE / 16);
3996 if (needed > SGE_MAX_WR_NDESC || needed > available)
3999 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4000 if (txp->plen > 65535)
4004 set_mbuf_len16(m, l1);
4005 set_mbuf_len16(n, l2);
4011 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4013 u_int plen, len16, needed, nsegs;
4015 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4017 nsegs = mbuf_nsegs(m);
4018 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4021 plen = txp->plen + m->m_pkthdr.len;
4025 if (txp->wr_type == 0)
4026 len16 = txpkts0_len16(nsegs);
4028 len16 = txpkts1_len16();
4029 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4030 if (needed > SGE_MAX_WR_NDESC || needed > available)
4035 txp->len16 += len16;
4036 set_mbuf_len16(m, len16);
4042 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4043 * the software descriptor, and advance the pidx. It is guaranteed that enough
4044 * descriptors are available.
4046 * The return value is the # of hardware descriptors used.
4049 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4050 struct mbuf *m0, const struct txpkts *txp, u_int available)
4052 struct sge_eq *eq = &txq->eq;
4053 struct tx_sdesc *txsd;
4054 struct cpl_tx_pkt_core *cpl;
4057 int ndesc, checkwrap;
4061 TXQ_LOCK_ASSERT_OWNED(txq);
4062 MPASS(txp->npkt > 0);
4063 MPASS(txp->plen < 65536);
4065 MPASS(m0->m_nextpkt != NULL);
4066 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4067 MPASS(available > 0 && available < eq->sidx);
4069 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4070 MPASS(ndesc <= available);
4072 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4073 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4074 ctrl = V_FW_WR_LEN16(txp->len16);
4075 wr->equiq_to_len16 = htobe32(ctrl);
4076 wr->plen = htobe16(txp->plen);
4077 wr->npkt = txp->npkt;
4079 wr->type = txp->wr_type;
4083 * At this point we are 16B into a hardware descriptor. If checkwrap is
4084 * set then we know the WR is going to wrap around somewhere. We'll
4085 * check for that at appropriate points.
4087 checkwrap = eq->sidx - ndesc < eq->pidx;
4088 for (m = m0; m != NULL; m = m->m_nextpkt) {
4089 if (txp->wr_type == 0) {
4090 struct ulp_txpkt *ulpmc;
4091 struct ulptx_idata *ulpsc;
4093 /* ULP master command */
4095 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4096 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4097 ulpmc->len = htobe32(mbuf_len16(m));
4099 /* ULP subcommand */
4100 ulpsc = (void *)(ulpmc + 1);
4101 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4103 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4105 cpl = (void *)(ulpsc + 1);
4107 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4108 cpl = (void *)&eq->desc[0];
4109 txq->txpkts0_pkts += txp->npkt;
4113 txq->txpkts1_pkts += txp->npkt;
4117 /* Checksum offload */
4119 if (needs_l3_csum(m) == 0)
4120 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4121 if (needs_l4_csum(m) == 0)
4122 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4123 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4124 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4125 txq->txcsum++; /* some hardware assistance provided */
4127 /* VLAN tag insertion */
4128 if (needs_vlan_insertion(m)) {
4129 ctrl1 |= F_TXPKT_VLAN_VLD |
4130 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4131 txq->vlan_insertion++;
4135 cpl->ctrl0 = txq->cpl_ctrl0;
4137 cpl->len = htobe16(m->m_pkthdr.len);
4138 cpl->ctrl1 = htobe64(ctrl1);
4142 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4143 flitp = (void *)&eq->desc[0];
4145 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4149 txsd = &txq->sdesc[eq->pidx];
4151 txsd->desc_used = ndesc;
4157 * If the SGL ends on an address that is not 16 byte aligned, this function will
4158 * add a 0 filled flit at the end.
4161 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4163 struct sge_eq *eq = &txq->eq;
4164 struct sglist *gl = txq->gl;
4165 struct sglist_seg *seg;
4166 __be64 *flitp, *wrap;
4167 struct ulptx_sgl *usgl;
4168 int i, nflits, nsegs;
4170 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4171 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4172 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4173 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4176 nsegs = gl->sg_nseg;
4179 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4180 flitp = (__be64 *)(*to);
4181 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4182 seg = &gl->sg_segs[0];
4183 usgl = (void *)flitp;
4186 * We start at a 16 byte boundary somewhere inside the tx descriptor
4187 * ring, so we're at least 16 bytes away from the status page. There is
4188 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4191 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4192 V_ULPTX_NSGE(nsegs));
4193 usgl->len0 = htobe32(seg->ss_len);
4194 usgl->addr0 = htobe64(seg->ss_paddr);
4197 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4199 /* Won't wrap around at all */
4201 for (i = 0; i < nsegs - 1; i++, seg++) {
4202 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4203 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4206 usgl->sge[i / 2].len[1] = htobe32(0);
4210 /* Will wrap somewhere in the rest of the SGL */
4212 /* 2 flits already written, write the rest flit by flit */
4213 flitp = (void *)(usgl + 1);
4214 for (i = 0; i < nflits - 2; i++) {
4216 flitp = (void *)eq->desc;
4217 *flitp++ = get_flit(seg, nsegs - 1, i);
4222 MPASS(((uintptr_t)flitp) & 0xf);
4226 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4227 if (__predict_false(flitp == wrap))
4228 *to = (void *)eq->desc;
4230 *to = (void *)flitp;
4234 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4237 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4238 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4240 if (__predict_true((uintptr_t)(*to) + len <=
4241 (uintptr_t)&eq->desc[eq->sidx])) {
4242 bcopy(from, *to, len);
4245 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4247 bcopy(from, *to, portion);
4249 portion = len - portion; /* remaining */
4250 bcopy(from, (void *)eq->desc, portion);
4251 (*to) = (caddr_t)eq->desc + portion;
4256 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4264 clrbit(&db, DOORBELL_WCWR);
4267 switch (ffs(db) - 1) {
4269 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4272 case DOORBELL_WCWR: {
4273 volatile uint64_t *dst, *src;
4277 * Queues whose 128B doorbell segment fits in the page do not
4278 * use relative qid (udb_qid is always 0). Only queues with
4279 * doorbell segments can do WCWR.
4281 KASSERT(eq->udb_qid == 0 && n == 1,
4282 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4283 __func__, eq->doorbells, n, eq->dbidx, eq));
4285 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4288 src = (void *)&eq->desc[i];
4289 while (src != (void *)&eq->desc[i + 1])
4295 case DOORBELL_UDBWC:
4296 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4301 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
4302 V_QID(eq->cntxt_id) | V_PIDX(n));
4306 IDXINCR(eq->dbidx, n, eq->sidx);
4310 reclaimable_tx_desc(struct sge_eq *eq)
4314 hw_cidx = read_hw_cidx(eq);
4315 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4319 total_available_tx_desc(struct sge_eq *eq)
4321 uint16_t hw_cidx, pidx;
4323 hw_cidx = read_hw_cidx(eq);
4326 if (pidx == hw_cidx)
4327 return (eq->sidx - 1);
4329 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4332 static inline uint16_t
4333 read_hw_cidx(struct sge_eq *eq)
4335 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4336 uint16_t cidx = spg->cidx; /* stable snapshot */
4338 return (be16toh(cidx));
4342 * Reclaim 'n' descriptors approximately.
4345 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4347 struct tx_sdesc *txsd;
4348 struct sge_eq *eq = &txq->eq;
4349 u_int can_reclaim, reclaimed;
4351 TXQ_LOCK_ASSERT_OWNED(txq);
4355 can_reclaim = reclaimable_tx_desc(eq);
4356 while (can_reclaim && reclaimed < n) {
4358 struct mbuf *m, *nextpkt;
4360 txsd = &txq->sdesc[eq->cidx];
4361 ndesc = txsd->desc_used;
4363 /* Firmware doesn't return "partial" credits. */
4364 KASSERT(can_reclaim >= ndesc,
4365 ("%s: unexpected number of credits: %d, %d",
4366 __func__, can_reclaim, ndesc));
4368 for (m = txsd->m; m != NULL; m = nextpkt) {
4369 nextpkt = m->m_nextpkt;
4370 m->m_nextpkt = NULL;
4374 can_reclaim -= ndesc;
4375 IDXINCR(eq->cidx, ndesc, eq->sidx);
4382 tx_reclaim(void *arg, int n)
4384 struct sge_txq *txq = arg;
4385 struct sge_eq *eq = &txq->eq;
4388 if (TXQ_TRYLOCK(txq) == 0)
4390 n = reclaim_tx_descs(txq, 32);
4391 if (eq->cidx == eq->pidx)
4392 eq->equeqidx = eq->pidx;
4398 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4400 int i = (idx / 3) * 2;
4406 rc = htobe32(segs[i].ss_len);
4408 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4413 return (htobe64(segs[i].ss_paddr));
4415 return (htobe64(segs[i + 1].ss_paddr));
4422 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4424 int8_t zidx, hwidx, idx;
4425 uint16_t region1, region3;
4426 int spare, spare_needed, n;
4427 struct sw_zone_info *swz;
4428 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4431 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4432 * large enough for the max payload and cluster metadata. Otherwise
4433 * settle for the largest bufsize that leaves enough room in the cluster
4436 * Without buffer packing: Look for the smallest zone which has a
4437 * bufsize large enough for the max payload. Settle for the largest
4438 * bufsize available if there's nothing big enough for max payload.
4440 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4441 swz = &sc->sge.sw_zone_info[0];
4443 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4444 if (swz->size > largest_rx_cluster) {
4445 if (__predict_true(hwidx != -1))
4449 * This is a misconfiguration. largest_rx_cluster is
4450 * preventing us from finding a refill source. See
4451 * dev.t5nex.<n>.buffer_sizes to figure out why.
4453 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4454 " refill source for fl %p (dma %u). Ignored.\n",
4455 largest_rx_cluster, fl, maxp);
4457 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4458 hwb = &hwb_list[idx];
4459 spare = swz->size - hwb->size;
4460 if (spare < spare_needed)
4463 hwidx = idx; /* best option so far */
4464 if (hwb->size >= maxp) {
4466 if ((fl->flags & FL_BUF_PACKING) == 0)
4467 goto done; /* stop looking (not packing) */
4469 if (swz->size >= safest_rx_cluster)
4470 goto done; /* stop looking (packing) */
4472 break; /* keep looking, next zone */
4476 /* A usable hwidx has been located. */
4478 hwb = &hwb_list[hwidx];
4480 swz = &sc->sge.sw_zone_info[zidx];
4482 region3 = swz->size - hwb->size;
4485 * Stay within this zone and see if there is a better match when mbuf
4486 * inlining is allowed. Remember that the hwidx's are sorted in
4487 * decreasing order of size (so in increasing order of spare area).
4489 for (idx = hwidx; idx != -1; idx = hwb->next) {
4490 hwb = &hwb_list[idx];
4491 spare = swz->size - hwb->size;
4493 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4497 * Do not inline mbufs if doing so would violate the pad/pack
4498 * boundary alignment requirement.
4500 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
4502 if (fl->flags & FL_BUF_PACKING &&
4503 (MSIZE % sc->params.sge.pack_boundary) != 0)
4506 if (spare < CL_METADATA_SIZE + MSIZE)
4508 n = (spare - CL_METADATA_SIZE) / MSIZE;
4509 if (n > howmany(hwb->size, maxp))
4513 if (fl->flags & FL_BUF_PACKING) {
4514 region1 = n * MSIZE;
4515 region3 = spare - region1;
4518 region3 = spare - region1;
4523 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4524 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4525 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4526 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4527 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4528 sc->sge.sw_zone_info[zidx].size,
4529 ("%s: bad buffer layout for fl %p, maxp %d. "
4530 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4531 sc->sge.sw_zone_info[zidx].size, region1,
4532 sc->sge.hw_buf_info[hwidx].size, region3));
4533 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4534 KASSERT(region3 >= CL_METADATA_SIZE,
4535 ("%s: no room for metadata. fl %p, maxp %d; "
4536 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4537 sc->sge.sw_zone_info[zidx].size, region1,
4538 sc->sge.hw_buf_info[hwidx].size, region3));
4539 KASSERT(region1 % MSIZE == 0,
4540 ("%s: bad mbuf region for fl %p, maxp %d. "
4541 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4542 sc->sge.sw_zone_info[zidx].size, region1,
4543 sc->sge.hw_buf_info[hwidx].size, region3));
4546 fl->cll_def.zidx = zidx;
4547 fl->cll_def.hwidx = hwidx;
4548 fl->cll_def.region1 = region1;
4549 fl->cll_def.region3 = region3;
4553 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4555 struct sge *s = &sc->sge;
4556 struct hw_buf_info *hwb;
4557 struct sw_zone_info *swz;
4561 if (fl->flags & FL_BUF_PACKING)
4562 hwidx = s->safe_hwidx2; /* with room for metadata */
4563 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4564 hwidx = s->safe_hwidx2;
4565 hwb = &s->hw_buf_info[hwidx];
4566 swz = &s->sw_zone_info[hwb->zidx];
4567 spare = swz->size - hwb->size;
4569 /* no good if there isn't room for an mbuf as well */
4570 if (spare < CL_METADATA_SIZE + MSIZE)
4571 hwidx = s->safe_hwidx1;
4573 hwidx = s->safe_hwidx1;
4576 /* No fallback source */
4577 fl->cll_alt.hwidx = -1;
4578 fl->cll_alt.zidx = -1;
4583 hwb = &s->hw_buf_info[hwidx];
4584 swz = &s->sw_zone_info[hwb->zidx];
4585 spare = swz->size - hwb->size;
4586 fl->cll_alt.hwidx = hwidx;
4587 fl->cll_alt.zidx = hwb->zidx;
4588 if (allow_mbufs_in_cluster &&
4589 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
4590 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4592 fl->cll_alt.region1 = 0;
4593 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4597 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4599 mtx_lock(&sc->sfl_lock);
4601 if ((fl->flags & FL_DOOMED) == 0) {
4602 fl->flags |= FL_STARVING;
4603 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4604 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
4607 mtx_unlock(&sc->sfl_lock);
4611 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
4613 struct sge_wrq *wrq = (void *)eq;
4615 atomic_readandclear_int(&eq->equiq);
4616 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
4620 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
4622 struct sge_txq *txq = (void *)eq;
4624 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
4626 atomic_readandclear_int(&eq->equiq);
4627 mp_ring_check_drainage(txq->r, 0);
4628 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
4632 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
4635 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
4636 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
4637 struct adapter *sc = iq->adapter;
4638 struct sge *s = &sc->sge;
4640 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
4641 &handle_wrq_egr_update, &handle_eth_egr_update,
4642 &handle_wrq_egr_update};
4644 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4647 eq = s->eqmap[qid - s->eq_start];
4648 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
4653 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
4654 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
4655 offsetof(struct cpl_fw6_msg, data));
4658 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4660 struct adapter *sc = iq->adapter;
4661 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
4663 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4666 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
4667 const struct rss_header *rss2;
4669 rss2 = (const struct rss_header *)&cpl->data[0];
4670 return (sc->cpl_handler[rss2->opcode](iq, rss2, m));
4673 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0]));
4677 sysctl_uint16(SYSCTL_HANDLER_ARGS)
4679 uint16_t *id = arg1;
4682 return sysctl_handle_int(oidp, &i, 0, req);
4686 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
4688 struct sge *s = arg1;
4689 struct hw_buf_info *hwb = &s->hw_buf_info[0];
4690 struct sw_zone_info *swz = &s->sw_zone_info[0];
4695 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4696 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
4697 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
4702 sbuf_printf(&sb, "%u%c ", hwb->size, c);
4706 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);