1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 /* 82571EB Gigabit Ethernet Controller
36 * 82571EB Gigabit Ethernet Controller (Copper)
37 * 82571EB Gigabit Ethernet Controller (Fiber)
38 * 82571EB Dual Port Gigabit Mezzanine Adapter
39 * 82571EB Quad Port Gigabit Mezzanine Adapter
40 * 82571PT Gigabit PT Quad Port Server ExpressModule
41 * 82572EI Gigabit Ethernet Controller (Copper)
42 * 82572EI Gigabit Ethernet Controller (Fiber)
43 * 82572EI Gigabit Ethernet Controller
44 * 82573V Gigabit Ethernet Controller (Copper)
45 * 82573E Gigabit Ethernet Controller (Copper)
46 * 82573L Gigabit Ethernet Controller
47 * 82574L Gigabit Network Connection
48 * 82583V Gigabit Network Connection
51 #include "e1000_api.h"
53 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
54 static void e1000_release_nvm_82571(struct e1000_hw *hw);
55 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
58 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
59 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
60 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
62 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
63 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
64 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
65 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
66 static s32 e1000_led_on_82574(struct e1000_hw *hw);
67 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
68 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
69 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
70 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
71 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
74 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
75 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
77 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
78 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
79 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
80 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
84 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
85 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
86 u16 words, u16 *data);
87 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
88 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
91 * e1000_init_phy_params_82571 - Init PHY func ptrs.
92 * @hw: pointer to the HW structure
94 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
96 struct e1000_phy_info *phy = &hw->phy;
99 DEBUGFUNC("e1000_init_phy_params_82571");
101 if (hw->phy.media_type != e1000_media_type_copper) {
102 phy->type = e1000_phy_none;
103 return E1000_SUCCESS;
107 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
108 phy->reset_delay_us = 100;
110 phy->ops.check_reset_block = e1000_check_reset_block_generic;
111 phy->ops.reset = e1000_phy_hw_reset_generic;
112 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
113 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
114 phy->ops.power_up = e1000_power_up_phy_copper;
115 phy->ops.power_down = e1000_power_down_phy_copper_82571;
117 switch (hw->mac.type) {
120 phy->type = e1000_phy_igp_2;
121 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
122 phy->ops.get_info = e1000_get_phy_info_igp;
123 phy->ops.check_polarity = e1000_check_polarity_igp;
124 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
125 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
126 phy->ops.read_reg = e1000_read_phy_reg_igp;
127 phy->ops.write_reg = e1000_write_phy_reg_igp;
128 phy->ops.acquire = e1000_get_hw_semaphore_82571;
129 phy->ops.release = e1000_put_hw_semaphore_82571;
132 phy->type = e1000_phy_m88;
133 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
134 phy->ops.get_info = e1000_get_phy_info_m88;
135 phy->ops.check_polarity = e1000_check_polarity_m88;
136 phy->ops.commit = e1000_phy_sw_reset_generic;
137 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
138 phy->ops.get_cable_length = e1000_get_cable_length_m88;
139 phy->ops.read_reg = e1000_read_phy_reg_m88;
140 phy->ops.write_reg = e1000_write_phy_reg_m88;
141 phy->ops.acquire = e1000_get_hw_semaphore_82571;
142 phy->ops.release = e1000_put_hw_semaphore_82571;
146 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
148 phy->type = e1000_phy_bm;
149 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
150 phy->ops.get_info = e1000_get_phy_info_m88;
151 phy->ops.check_polarity = e1000_check_polarity_m88;
152 phy->ops.commit = e1000_phy_sw_reset_generic;
153 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
154 phy->ops.get_cable_length = e1000_get_cable_length_m88;
155 phy->ops.read_reg = e1000_read_phy_reg_bm2;
156 phy->ops.write_reg = e1000_write_phy_reg_bm2;
157 phy->ops.acquire = e1000_get_hw_semaphore_82574;
158 phy->ops.release = e1000_put_hw_semaphore_82574;
159 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
160 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
163 return -E1000_ERR_PHY;
167 /* This can only be done after all function pointers are setup. */
168 ret_val = e1000_get_phy_id_82571(hw);
170 DEBUGOUT("Error getting PHY ID\n");
175 switch (hw->mac.type) {
178 if (phy->id != IGP01E1000_I_PHY_ID)
179 ret_val = -E1000_ERR_PHY;
182 if (phy->id != M88E1111_I_PHY_ID)
183 ret_val = -E1000_ERR_PHY;
187 if (phy->id != BME1000_E_PHY_ID_R2)
188 ret_val = -E1000_ERR_PHY;
191 ret_val = -E1000_ERR_PHY;
196 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
202 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
203 * @hw: pointer to the HW structure
205 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
207 struct e1000_nvm_info *nvm = &hw->nvm;
208 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
211 DEBUGFUNC("e1000_init_nvm_params_82571");
213 nvm->opcode_bits = 8;
215 switch (nvm->override) {
216 case e1000_nvm_override_spi_large:
218 nvm->address_bits = 16;
220 case e1000_nvm_override_spi_small:
222 nvm->address_bits = 8;
225 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
226 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
230 switch (hw->mac.type) {
234 if (((eecd >> 15) & 0x3) == 0x3) {
235 nvm->type = e1000_nvm_flash_hw;
236 nvm->word_size = 2048;
237 /* Autonomous Flash update bit must be cleared due
238 * to Flash update issue.
240 eecd &= ~E1000_EECD_AUPDEN;
241 E1000_WRITE_REG(hw, E1000_EECD, eecd);
246 nvm->type = e1000_nvm_eeprom_spi;
247 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
248 E1000_EECD_SIZE_EX_SHIFT);
249 /* Added to a constant, "size" becomes the left-shift value
250 * for setting word_size.
252 size += NVM_WORD_SIZE_BASE_SHIFT;
254 /* EEPROM access above 16k is unsupported */
257 nvm->word_size = 1 << size;
261 /* Function Pointers */
262 switch (hw->mac.type) {
265 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
266 nvm->ops.release = e1000_put_hw_semaphore_82574;
269 nvm->ops.acquire = e1000_acquire_nvm_82571;
270 nvm->ops.release = e1000_release_nvm_82571;
273 nvm->ops.read = e1000_read_nvm_eerd;
274 nvm->ops.update = e1000_update_nvm_checksum_82571;
275 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
276 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
277 nvm->ops.write = e1000_write_nvm_82571;
279 return E1000_SUCCESS;
283 * e1000_init_mac_params_82571 - Init MAC func ptrs.
284 * @hw: pointer to the HW structure
286 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
288 struct e1000_mac_info *mac = &hw->mac;
291 bool force_clear_smbi = FALSE;
293 DEBUGFUNC("e1000_init_mac_params_82571");
295 /* Set media type and media-dependent function pointers */
296 switch (hw->device_id) {
297 case E1000_DEV_ID_82571EB_FIBER:
298 case E1000_DEV_ID_82572EI_FIBER:
299 case E1000_DEV_ID_82571EB_QUAD_FIBER:
300 hw->phy.media_type = e1000_media_type_fiber;
301 mac->ops.setup_physical_interface =
302 e1000_setup_fiber_serdes_link_82571;
303 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
304 mac->ops.get_link_up_info =
305 e1000_get_speed_and_duplex_fiber_serdes_generic;
307 case E1000_DEV_ID_82571EB_SERDES:
308 case E1000_DEV_ID_82571EB_SERDES_DUAL:
309 case E1000_DEV_ID_82571EB_SERDES_QUAD:
310 case E1000_DEV_ID_82572EI_SERDES:
311 hw->phy.media_type = e1000_media_type_internal_serdes;
312 mac->ops.setup_physical_interface =
313 e1000_setup_fiber_serdes_link_82571;
314 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
315 mac->ops.get_link_up_info =
316 e1000_get_speed_and_duplex_fiber_serdes_generic;
319 hw->phy.media_type = e1000_media_type_copper;
320 mac->ops.setup_physical_interface =
321 e1000_setup_copper_link_82571;
322 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
323 mac->ops.get_link_up_info =
324 e1000_get_speed_and_duplex_copper_generic;
328 /* Set mta register count */
329 mac->mta_reg_count = 128;
330 /* Set rar entry count */
331 mac->rar_entry_count = E1000_RAR_ENTRIES;
332 /* Set if part includes ASF firmware */
333 mac->asf_firmware_present = TRUE;
334 /* Adaptive IFS supported */
335 mac->adaptive_ifs = TRUE;
337 /* Function pointers */
339 /* bus type/speed/width */
340 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
342 mac->ops.reset_hw = e1000_reset_hw_82571;
343 /* hw initialization */
344 mac->ops.init_hw = e1000_init_hw_82571;
346 mac->ops.setup_link = e1000_setup_link_82571;
347 /* multicast address update */
348 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
350 mac->ops.write_vfta = e1000_write_vfta_generic;
352 mac->ops.clear_vfta = e1000_clear_vfta_82571;
353 /* read mac address */
354 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
356 mac->ops.id_led_init = e1000_id_led_init_generic;
358 mac->ops.setup_led = e1000_setup_led_generic;
360 mac->ops.cleanup_led = e1000_cleanup_led_generic;
362 mac->ops.led_off = e1000_led_off_generic;
363 /* clear hardware counters */
364 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
366 /* MAC-specific function pointers */
367 switch (hw->mac.type) {
369 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
370 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
371 mac->ops.led_on = e1000_led_on_generic;
372 mac->ops.blink_led = e1000_blink_led_generic;
375 mac->has_fwsm = TRUE;
376 /* ARC supported; valid only if manageability features are
379 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
380 E1000_FWSM_MODE_MASK);
384 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
385 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
386 mac->ops.led_on = e1000_led_on_82574;
389 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
390 mac->ops.led_on = e1000_led_on_generic;
391 mac->ops.blink_led = e1000_blink_led_generic;
394 mac->has_fwsm = TRUE;
398 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
399 * first NVM or PHY acess. This should be done for single-port
400 * devices, and for one port only on dual-port devices so that
401 * for those devices we can still use the SMBI lock to synchronize
402 * inter-port accesses to the PHY & NVM.
404 switch (hw->mac.type) {
407 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
409 if (!(swsm2 & E1000_SWSM2_LOCK)) {
410 /* Only do this for the first interface on this card */
411 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
413 force_clear_smbi = TRUE;
415 force_clear_smbi = FALSE;
419 force_clear_smbi = TRUE;
423 if (force_clear_smbi) {
424 /* Make sure SWSM.SMBI is clear */
425 swsm = E1000_READ_REG(hw, E1000_SWSM);
426 if (swsm & E1000_SWSM_SMBI) {
427 /* This bit should not be set on a first interface, and
428 * indicates that the bootagent or EFI code has
429 * improperly left this bit enabled
431 DEBUGOUT("Please update your 82571 Bootagent\n");
433 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
436 /* Initialze device specific counter of SMBI acquisition timeouts. */
437 hw->dev_spec._82571.smb_counter = 0;
439 return E1000_SUCCESS;
443 * e1000_init_function_pointers_82571 - Init func ptrs.
444 * @hw: pointer to the HW structure
446 * Called to initialize all function pointers and parameters.
448 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
450 DEBUGFUNC("e1000_init_function_pointers_82571");
452 hw->mac.ops.init_params = e1000_init_mac_params_82571;
453 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
454 hw->phy.ops.init_params = e1000_init_phy_params_82571;
458 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
459 * @hw: pointer to the HW structure
461 * Reads the PHY registers and stores the PHY ID and possibly the PHY
462 * revision in the hardware structure.
464 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
466 struct e1000_phy_info *phy = &hw->phy;
470 DEBUGFUNC("e1000_get_phy_id_82571");
472 switch (hw->mac.type) {
475 /* The 82571 firmware may still be configuring the PHY.
476 * In this case, we cannot access the PHY until the
477 * configuration is done. So we explicitly set the
480 phy->id = IGP01E1000_I_PHY_ID;
483 return e1000_get_phy_id(hw);
487 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
491 phy->id = (u32)(phy_id << 16);
493 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
497 phy->id |= (u32)(phy_id);
498 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
501 return -E1000_ERR_PHY;
505 return E1000_SUCCESS;
509 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
510 * @hw: pointer to the HW structure
512 * Acquire the HW semaphore to access the PHY or NVM
514 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
517 s32 sw_timeout = hw->nvm.word_size + 1;
518 s32 fw_timeout = hw->nvm.word_size + 1;
521 DEBUGFUNC("e1000_get_hw_semaphore_82571");
523 /* If we have timedout 3 times on trying to acquire
524 * the inter-port SMBI semaphore, there is old code
525 * operating on the other port, and it is not
526 * releasing SMBI. Modify the number of times that
527 * we try for the semaphore to interwork with this
530 if (hw->dev_spec._82571.smb_counter > 2)
533 /* Get the SW semaphore */
534 while (i < sw_timeout) {
535 swsm = E1000_READ_REG(hw, E1000_SWSM);
536 if (!(swsm & E1000_SWSM_SMBI))
543 if (i == sw_timeout) {
544 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
545 hw->dev_spec._82571.smb_counter++;
547 /* Get the FW semaphore. */
548 for (i = 0; i < fw_timeout; i++) {
549 swsm = E1000_READ_REG(hw, E1000_SWSM);
550 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
552 /* Semaphore acquired if bit latched */
553 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
559 if (i == fw_timeout) {
560 /* Release semaphores */
561 e1000_put_hw_semaphore_82571(hw);
562 DEBUGOUT("Driver can't access the NVM\n");
563 return -E1000_ERR_NVM;
566 return E1000_SUCCESS;
570 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
571 * @hw: pointer to the HW structure
573 * Release hardware semaphore used to access the PHY or NVM
575 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
579 DEBUGFUNC("e1000_put_hw_semaphore_generic");
581 swsm = E1000_READ_REG(hw, E1000_SWSM);
583 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
585 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
589 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
590 * @hw: pointer to the HW structure
592 * Acquire the HW semaphore during reset.
595 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
600 DEBUGFUNC("e1000_get_hw_semaphore_82573");
602 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
604 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
605 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
606 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
608 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
613 } while (i < MDIO_OWNERSHIP_TIMEOUT);
615 if (i == MDIO_OWNERSHIP_TIMEOUT) {
616 /* Release semaphores */
617 e1000_put_hw_semaphore_82573(hw);
618 DEBUGOUT("Driver can't access the PHY\n");
619 return -E1000_ERR_PHY;
622 return E1000_SUCCESS;
626 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
627 * @hw: pointer to the HW structure
629 * Release hardware semaphore used during reset.
632 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
636 DEBUGFUNC("e1000_put_hw_semaphore_82573");
638 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
639 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
640 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
644 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
645 * @hw: pointer to the HW structure
647 * Acquire the HW semaphore to access the PHY or NVM.
650 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
654 DEBUGFUNC("e1000_get_hw_semaphore_82574");
656 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
657 ret_val = e1000_get_hw_semaphore_82573(hw);
659 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
664 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
665 * @hw: pointer to the HW structure
667 * Release hardware semaphore used to access the PHY or NVM
670 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
672 DEBUGFUNC("e1000_put_hw_semaphore_82574");
674 e1000_put_hw_semaphore_82573(hw);
675 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
679 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
680 * @hw: pointer to the HW structure
681 * @active: TRUE to enable LPLU, FALSE to disable
683 * Sets the LPLU D0 state according to the active flag.
684 * LPLU will not be activated unless the
685 * device autonegotiation advertisement meets standards of
686 * either 10 or 10/100 or 10/100/1000 at all duplexes.
687 * This is a function pointer entry point only called by
688 * PHY setup routines.
690 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
692 u32 data = E1000_READ_REG(hw, E1000_POEMB);
694 DEBUGFUNC("e1000_set_d0_lplu_state_82574");
697 data |= E1000_PHY_CTRL_D0A_LPLU;
699 data &= ~E1000_PHY_CTRL_D0A_LPLU;
701 E1000_WRITE_REG(hw, E1000_POEMB, data);
702 return E1000_SUCCESS;
706 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
707 * @hw: pointer to the HW structure
708 * @active: boolean used to enable/disable lplu
710 * The low power link up (lplu) state is set to the power management level D3
711 * when active is TRUE, else clear lplu for D3. LPLU
712 * is used during Dx states where the power conservation is most important.
713 * During driver activity, SmartSpeed should be enabled so performance is
716 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
718 u32 data = E1000_READ_REG(hw, E1000_POEMB);
720 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
723 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
724 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
725 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
726 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
727 data |= E1000_PHY_CTRL_NOND0A_LPLU;
730 E1000_WRITE_REG(hw, E1000_POEMB, data);
731 return E1000_SUCCESS;
735 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
736 * @hw: pointer to the HW structure
738 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
739 * Then for non-82573 hardware, set the EEPROM access request bit and wait
740 * for EEPROM access grant bit. If the access grant bit is not set, release
741 * hardware semaphore.
743 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
747 DEBUGFUNC("e1000_acquire_nvm_82571");
749 ret_val = e1000_get_hw_semaphore_82571(hw);
753 switch (hw->mac.type) {
757 ret_val = e1000_acquire_nvm_generic(hw);
762 e1000_put_hw_semaphore_82571(hw);
768 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
769 * @hw: pointer to the HW structure
771 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
773 static void e1000_release_nvm_82571(struct e1000_hw *hw)
775 DEBUGFUNC("e1000_release_nvm_82571");
777 e1000_release_nvm_generic(hw);
778 e1000_put_hw_semaphore_82571(hw);
782 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
783 * @hw: pointer to the HW structure
784 * @offset: offset within the EEPROM to be written to
785 * @words: number of words to write
786 * @data: 16 bit word(s) to be written to the EEPROM
788 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
790 * If e1000_update_nvm_checksum is not called after this function, the
791 * EEPROM will most likely contain an invalid checksum.
793 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
798 DEBUGFUNC("e1000_write_nvm_82571");
800 switch (hw->mac.type) {
804 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
808 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
811 ret_val = -E1000_ERR_NVM;
819 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
820 * @hw: pointer to the HW structure
822 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
823 * up to the checksum. Then calculates the EEPROM checksum and writes the
824 * value to the EEPROM.
826 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
832 DEBUGFUNC("e1000_update_nvm_checksum_82571");
834 ret_val = e1000_update_nvm_checksum_generic(hw);
838 /* If our nvm is an EEPROM, then we're done
839 * otherwise, commit the checksum to the flash NVM.
841 if (hw->nvm.type != e1000_nvm_flash_hw)
842 return E1000_SUCCESS;
844 /* Check for pending operations. */
845 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
847 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
851 if (i == E1000_FLASH_UPDATES)
852 return -E1000_ERR_NVM;
854 /* Reset the firmware if using STM opcode. */
855 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
856 /* The enabling of and the actual reset must be done
857 * in two write cycles.
859 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
860 E1000_WRITE_FLUSH(hw);
861 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
864 /* Commit the write to flash */
865 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
866 E1000_WRITE_REG(hw, E1000_EECD, eecd);
868 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
870 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
874 if (i == E1000_FLASH_UPDATES)
875 return -E1000_ERR_NVM;
877 return E1000_SUCCESS;
881 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
882 * @hw: pointer to the HW structure
884 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
885 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
887 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
889 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
891 if (hw->nvm.type == e1000_nvm_flash_hw)
892 e1000_fix_nvm_checksum_82571(hw);
894 return e1000_validate_nvm_checksum_generic(hw);
898 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
899 * @hw: pointer to the HW structure
900 * @offset: offset within the EEPROM to be written to
901 * @words: number of words to write
902 * @data: 16 bit word(s) to be written to the EEPROM
904 * After checking for invalid values, poll the EEPROM to ensure the previous
905 * command has completed before trying to write the next word. After write
906 * poll for completion.
908 * If e1000_update_nvm_checksum is not called after this function, the
909 * EEPROM will most likely contain an invalid checksum.
911 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
912 u16 words, u16 *data)
914 struct e1000_nvm_info *nvm = &hw->nvm;
916 s32 ret_val = E1000_SUCCESS;
918 DEBUGFUNC("e1000_write_nvm_eewr_82571");
920 /* A check for invalid values: offset too large, too many words,
921 * and not enough words.
923 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
925 DEBUGOUT("nvm parameter(s) out of bounds\n");
926 return -E1000_ERR_NVM;
929 for (i = 0; i < words; i++) {
930 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
931 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
932 E1000_NVM_RW_REG_START);
934 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
938 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
940 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
949 * e1000_get_cfg_done_82571 - Poll for configuration done
950 * @hw: pointer to the HW structure
952 * Reads the management control register for the config done bit to be set.
954 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
956 s32 timeout = PHY_CFG_TIMEOUT;
958 DEBUGFUNC("e1000_get_cfg_done_82571");
961 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
962 E1000_NVM_CFG_DONE_PORT_0)
968 DEBUGOUT("MNG configuration cycle has not completed.\n");
969 return -E1000_ERR_RESET;
972 return E1000_SUCCESS;
976 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
977 * @hw: pointer to the HW structure
978 * @active: TRUE to enable LPLU, FALSE to disable
980 * Sets the LPLU D0 state according to the active flag. When activating LPLU
981 * this function also disables smart speed and vice versa. LPLU will not be
982 * activated unless the device autonegotiation advertisement meets standards
983 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
984 * pointer entry point only called by PHY setup routines.
986 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
988 struct e1000_phy_info *phy = &hw->phy;
992 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
994 if (!(phy->ops.read_reg))
995 return E1000_SUCCESS;
997 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1002 data |= IGP02E1000_PM_D0_LPLU;
1003 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1008 /* When LPLU is enabled, we should disable SmartSpeed */
1009 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1013 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1019 data &= ~IGP02E1000_PM_D0_LPLU;
1020 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1022 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1023 * during Dx states where the power conservation is most
1024 * important. During driver activity we should enable
1025 * SmartSpeed, so performance is maintained.
1027 if (phy->smart_speed == e1000_smart_speed_on) {
1028 ret_val = phy->ops.read_reg(hw,
1029 IGP01E1000_PHY_PORT_CONFIG,
1034 data |= IGP01E1000_PSCFR_SMART_SPEED;
1035 ret_val = phy->ops.write_reg(hw,
1036 IGP01E1000_PHY_PORT_CONFIG,
1040 } else if (phy->smart_speed == e1000_smart_speed_off) {
1041 ret_val = phy->ops.read_reg(hw,
1042 IGP01E1000_PHY_PORT_CONFIG,
1047 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1048 ret_val = phy->ops.write_reg(hw,
1049 IGP01E1000_PHY_PORT_CONFIG,
1056 return E1000_SUCCESS;
1060 * e1000_reset_hw_82571 - Reset hardware
1061 * @hw: pointer to the HW structure
1063 * This resets the hardware into a known state.
1065 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1067 u32 ctrl, ctrl_ext, eecd, tctl;
1070 DEBUGFUNC("e1000_reset_hw_82571");
1072 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1073 * on the last TLP read/write transaction when MAC is reset.
1075 ret_val = e1000_disable_pcie_master_generic(hw);
1077 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1079 DEBUGOUT("Masking off all interrupts\n");
1080 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1082 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1083 tctl = E1000_READ_REG(hw, E1000_TCTL);
1084 tctl &= ~E1000_TCTL_EN;
1085 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1086 E1000_WRITE_FLUSH(hw);
1090 /* Must acquire the MDIO ownership before MAC reset.
1091 * Ownership defaults to firmware after a reset.
1093 switch (hw->mac.type) {
1095 ret_val = e1000_get_hw_semaphore_82573(hw);
1099 ret_val = e1000_get_hw_semaphore_82574(hw);
1105 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1107 DEBUGOUT("Issuing a global reset to MAC\n");
1108 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1110 /* Must release MDIO ownership and mutex after MAC reset. */
1111 switch (hw->mac.type) {
1113 /* Release mutex only if the hw semaphore is acquired */
1115 e1000_put_hw_semaphore_82573(hw);
1119 /* Release mutex only if the hw semaphore is acquired */
1121 e1000_put_hw_semaphore_82574(hw);
1127 if (hw->nvm.type == e1000_nvm_flash_hw) {
1129 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1130 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1131 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1132 E1000_WRITE_FLUSH(hw);
1135 ret_val = e1000_get_auto_rd_done_generic(hw);
1137 /* We don't want to continue accessing MAC registers. */
1140 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1141 * Need to wait for Phy configuration completion before accessing
1145 switch (hw->mac.type) {
1148 /* REQ and GNT bits need to be cleared when using AUTO_RD
1149 * to access the EEPROM.
1151 eecd = E1000_READ_REG(hw, E1000_EECD);
1152 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1153 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1164 /* Clear any pending interrupt events. */
1165 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1166 E1000_READ_REG(hw, E1000_ICR);
1168 if (hw->mac.type == e1000_82571) {
1169 /* Install any alternate MAC address into RAR0 */
1170 ret_val = e1000_check_alt_mac_addr_generic(hw);
1174 e1000_set_laa_state_82571(hw, TRUE);
1177 /* Reinitialize the 82571 serdes link state machine */
1178 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1179 hw->mac.serdes_link_state = e1000_serdes_link_down;
1181 return E1000_SUCCESS;
1185 * e1000_init_hw_82571 - Initialize hardware
1186 * @hw: pointer to the HW structure
1188 * This inits the hardware readying it for operation.
1190 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1192 struct e1000_mac_info *mac = &hw->mac;
1195 u16 i, rar_count = mac->rar_entry_count;
1197 DEBUGFUNC("e1000_init_hw_82571");
1199 e1000_initialize_hw_bits_82571(hw);
1201 /* Initialize identification LED */
1202 ret_val = mac->ops.id_led_init(hw);
1203 /* An error is not fatal and we should not stop init due to this */
1205 DEBUGOUT("Error initializing identification LED\n");
1207 /* Disabling VLAN filtering */
1208 DEBUGOUT("Initializing the IEEE VLAN\n");
1209 mac->ops.clear_vfta(hw);
1211 /* Setup the receive address.
1212 * If, however, a locally administered address was assigned to the
1213 * 82571, we must reserve a RAR for it to work around an issue where
1214 * resetting one port will reload the MAC on the other port.
1216 if (e1000_get_laa_state_82571(hw))
1218 e1000_init_rx_addrs_generic(hw, rar_count);
1220 /* Zero out the Multicast HASH table */
1221 DEBUGOUT("Zeroing the MTA\n");
1222 for (i = 0; i < mac->mta_reg_count; i++)
1223 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1225 /* Setup link and flow control */
1226 ret_val = mac->ops.setup_link(hw);
1228 /* Set the transmit descriptor write-back policy */
1229 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1230 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1231 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1232 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1234 /* ...for both queues. */
1235 switch (mac->type) {
1237 e1000_enable_tx_pkt_filtering_generic(hw);
1241 reg_data = E1000_READ_REG(hw, E1000_GCR);
1242 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1243 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1246 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1247 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1248 E1000_TXDCTL_FULL_TX_DESC_WB |
1249 E1000_TXDCTL_COUNT_DESC);
1250 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1254 /* Clear all of the statistics registers (clear on read). It is
1255 * important that we do this after we have tried to establish link
1256 * because the symbol error count will increment wildly if there
1259 e1000_clear_hw_cntrs_82571(hw);
1265 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1266 * @hw: pointer to the HW structure
1268 * Initializes required hardware-dependent bits needed for normal operation.
1270 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1274 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1276 /* Transmit Descriptor Control 0 */
1277 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1279 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1281 /* Transmit Descriptor Control 1 */
1282 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1284 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1286 /* Transmit Arbitration Control 0 */
1287 reg = E1000_READ_REG(hw, E1000_TARC(0));
1288 reg &= ~(0xF << 27); /* 30:27 */
1289 switch (hw->mac.type) {
1292 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1301 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1303 /* Transmit Arbitration Control 1 */
1304 reg = E1000_READ_REG(hw, E1000_TARC(1));
1305 switch (hw->mac.type) {
1308 reg &= ~((1 << 29) | (1 << 30));
1309 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1310 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1314 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1320 /* Device Control */
1321 switch (hw->mac.type) {
1325 reg = E1000_READ_REG(hw, E1000_CTRL);
1327 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1333 /* Extended Device Control */
1334 switch (hw->mac.type) {
1338 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1341 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1347 if (hw->mac.type == e1000_82571) {
1348 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1349 reg |= E1000_PBA_ECC_CORR_EN;
1350 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1353 /* Workaround for hardware errata.
1354 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1356 if ((hw->mac.type == e1000_82571) ||
1357 (hw->mac.type == e1000_82572)) {
1358 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1359 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1360 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1363 /* Disable IPv6 extension header parsing because some malformed
1364 * IPv6 headers can hang the Rx.
1366 if (hw->mac.type <= e1000_82573) {
1367 reg = E1000_READ_REG(hw, E1000_RFCTL);
1368 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1369 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1372 /* PCI-Ex Control Registers */
1373 switch (hw->mac.type) {
1376 reg = E1000_READ_REG(hw, E1000_GCR);
1378 E1000_WRITE_REG(hw, E1000_GCR, reg);
1380 /* Workaround for hardware errata.
1381 * apply workaround for hardware errata documented in errata
1382 * docs Fixes issue where some error prone or unreliable PCIe
1383 * completions are occurring, particularly with ASPM enabled.
1384 * Without fix, issue can cause Tx timeouts.
1386 reg = E1000_READ_REG(hw, E1000_GCR2);
1388 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1398 * e1000_clear_vfta_82571 - Clear VLAN filter table
1399 * @hw: pointer to the HW structure
1401 * Clears the register array which contains the VLAN filter table by
1402 * setting all the values to 0.
1404 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1408 u32 vfta_offset = 0;
1409 u32 vfta_bit_in_reg = 0;
1411 DEBUGFUNC("e1000_clear_vfta_82571");
1413 switch (hw->mac.type) {
1417 if (hw->mng_cookie.vlan_id != 0) {
1418 /* The VFTA is a 4096b bit-field, each identifying
1419 * a single VLAN ID. The following operations
1420 * determine which 32b entry (i.e. offset) into the
1421 * array we want to set the VLAN ID (i.e. bit) of
1422 * the manageability unit.
1424 vfta_offset = (hw->mng_cookie.vlan_id >>
1425 E1000_VFTA_ENTRY_SHIFT) &
1426 E1000_VFTA_ENTRY_MASK;
1428 1 << (hw->mng_cookie.vlan_id &
1429 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1435 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1436 /* If the offset we want to clear is the same offset of the
1437 * manageability VLAN ID, then clear all bits except that of
1438 * the manageability unit.
1440 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1441 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1442 E1000_WRITE_FLUSH(hw);
1447 * e1000_check_mng_mode_82574 - Check manageability is enabled
1448 * @hw: pointer to the HW structure
1450 * Reads the NVM Initialization Control Word 2 and returns TRUE
1451 * (>0) if any manageability is enabled, else FALSE (0).
1453 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1457 DEBUGFUNC("e1000_check_mng_mode_82574");
1459 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1460 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1464 * e1000_led_on_82574 - Turn LED on
1465 * @hw: pointer to the HW structure
1469 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1474 DEBUGFUNC("e1000_led_on_82574");
1476 ctrl = hw->mac.ledctl_mode2;
1477 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1478 /* If no link, then turn LED on by setting the invert bit
1479 * for each LED that's "on" (0x0E) in ledctl_mode2.
1481 for (i = 0; i < 4; i++)
1482 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1483 E1000_LEDCTL_MODE_LED_ON)
1484 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1486 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1488 return E1000_SUCCESS;
1492 * e1000_check_phy_82574 - check 82574 phy hung state
1493 * @hw: pointer to the HW structure
1495 * Returns whether phy is hung or not
1497 bool e1000_check_phy_82574(struct e1000_hw *hw)
1499 u16 status_1kbt = 0;
1500 u16 receive_errors = 0;
1503 DEBUGFUNC("e1000_check_phy_82574");
1505 /* Read PHY Receive Error counter first, if its is max - all F's then
1506 * read the Base1000T status register If both are max then PHY is hung.
1508 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1512 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1513 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1517 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1518 E1000_IDLE_ERROR_COUNT_MASK)
1527 * e1000_setup_link_82571 - Setup flow control and link settings
1528 * @hw: pointer to the HW structure
1530 * Determines which flow control settings to use, then configures flow
1531 * control. Calls the appropriate media-specific link configuration
1532 * function. Assuming the adapter has a valid link partner, a valid link
1533 * should be established. Assumes the hardware has previously been reset
1534 * and the transmitter and receiver are not enabled.
1536 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1538 DEBUGFUNC("e1000_setup_link_82571");
1540 /* 82573 does not have a word in the NVM to determine
1541 * the default flow control setting, so we explicitly
1544 switch (hw->mac.type) {
1548 if (hw->fc.requested_mode == e1000_fc_default)
1549 hw->fc.requested_mode = e1000_fc_full;
1555 return e1000_setup_link_generic(hw);
1559 * e1000_setup_copper_link_82571 - Configure copper link settings
1560 * @hw: pointer to the HW structure
1562 * Configures the link for auto-neg or forced speed and duplex. Then we check
1563 * for link, once link is established calls to configure collision distance
1564 * and flow control are called.
1566 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1571 DEBUGFUNC("e1000_setup_copper_link_82571");
1573 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1574 ctrl |= E1000_CTRL_SLU;
1575 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1576 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1578 switch (hw->phy.type) {
1581 ret_val = e1000_copper_link_setup_m88(hw);
1583 case e1000_phy_igp_2:
1584 ret_val = e1000_copper_link_setup_igp(hw);
1587 return -E1000_ERR_PHY;
1594 return e1000_setup_copper_link_generic(hw);
1598 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1599 * @hw: pointer to the HW structure
1601 * Configures collision distance and flow control for fiber and serdes links.
1602 * Upon successful setup, poll for link.
1604 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1606 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1608 switch (hw->mac.type) {
1611 /* If SerDes loopback mode is entered, there is no form
1612 * of reset to take the adapter out of that mode. So we
1613 * have to explicitly take the adapter out of loopback
1614 * mode. This prevents drivers from twiddling their thumbs
1615 * if another tool failed to take it out of loopback mode.
1617 E1000_WRITE_REG(hw, E1000_SCTL,
1618 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1624 return e1000_setup_fiber_serdes_link_generic(hw);
1628 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1629 * @hw: pointer to the HW structure
1631 * Reports the link state as up or down.
1633 * If autonegotiation is supported by the link partner, the link state is
1634 * determined by the result of autonegotiation. This is the most likely case.
1635 * If autonegotiation is not supported by the link partner, and the link
1636 * has a valid signal, force the link up.
1638 * The link state is represented internally here by 4 states:
1641 * 2) autoneg_progress
1642 * 3) autoneg_complete (the link successfully autonegotiated)
1643 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1646 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1648 struct e1000_mac_info *mac = &hw->mac;
1654 s32 ret_val = E1000_SUCCESS;
1656 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1658 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1659 status = E1000_READ_REG(hw, E1000_STATUS);
1660 E1000_READ_REG(hw, E1000_RXCW);
1661 /* SYNCH bit and IV bit are sticky */
1663 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1665 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1666 /* Receiver is synchronized with no invalid bits. */
1667 switch (mac->serdes_link_state) {
1668 case e1000_serdes_link_autoneg_complete:
1669 if (!(status & E1000_STATUS_LU)) {
1670 /* We have lost link, retry autoneg before
1671 * reporting link failure
1673 mac->serdes_link_state =
1674 e1000_serdes_link_autoneg_progress;
1675 mac->serdes_has_link = FALSE;
1676 DEBUGOUT("AN_UP -> AN_PROG\n");
1678 mac->serdes_has_link = TRUE;
1682 case e1000_serdes_link_forced_up:
1683 /* If we are receiving /C/ ordered sets, re-enable
1684 * auto-negotiation in the TXCW register and disable
1685 * forced link in the Device Control register in an
1686 * attempt to auto-negotiate with our link partner.
1688 if (rxcw & E1000_RXCW_C) {
1689 /* Enable autoneg, and unforce link up */
1690 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1691 E1000_WRITE_REG(hw, E1000_CTRL,
1692 (ctrl & ~E1000_CTRL_SLU));
1693 mac->serdes_link_state =
1694 e1000_serdes_link_autoneg_progress;
1695 mac->serdes_has_link = FALSE;
1696 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1698 mac->serdes_has_link = TRUE;
1702 case e1000_serdes_link_autoneg_progress:
1703 if (rxcw & E1000_RXCW_C) {
1704 /* We received /C/ ordered sets, meaning the
1705 * link partner has autonegotiated, and we can
1706 * trust the Link Up (LU) status bit.
1708 if (status & E1000_STATUS_LU) {
1709 mac->serdes_link_state =
1710 e1000_serdes_link_autoneg_complete;
1711 DEBUGOUT("AN_PROG -> AN_UP\n");
1712 mac->serdes_has_link = TRUE;
1714 /* Autoneg completed, but failed. */
1715 mac->serdes_link_state =
1716 e1000_serdes_link_down;
1717 DEBUGOUT("AN_PROG -> DOWN\n");
1720 /* The link partner did not autoneg.
1721 * Force link up and full duplex, and change
1724 E1000_WRITE_REG(hw, E1000_TXCW,
1725 (mac->txcw & ~E1000_TXCW_ANE));
1726 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1727 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1729 /* Configure Flow Control after link up. */
1731 e1000_config_fc_after_link_up_generic(hw);
1733 DEBUGOUT("Error config flow control\n");
1736 mac->serdes_link_state =
1737 e1000_serdes_link_forced_up;
1738 mac->serdes_has_link = TRUE;
1739 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1743 case e1000_serdes_link_down:
1745 /* The link was down but the receiver has now gained
1746 * valid sync, so lets see if we can bring the link
1749 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1750 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1752 mac->serdes_link_state =
1753 e1000_serdes_link_autoneg_progress;
1754 mac->serdes_has_link = FALSE;
1755 DEBUGOUT("DOWN -> AN_PROG\n");
1759 if (!(rxcw & E1000_RXCW_SYNCH)) {
1760 mac->serdes_has_link = FALSE;
1761 mac->serdes_link_state = e1000_serdes_link_down;
1762 DEBUGOUT("ANYSTATE -> DOWN\n");
1764 /* Check several times, if SYNCH bit and CONFIG
1765 * bit both are consistently 1 then simply ignore
1766 * the IV bit and restart Autoneg
1768 for (i = 0; i < AN_RETRY_COUNT; i++) {
1770 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1771 if ((rxcw & E1000_RXCW_SYNCH) &&
1772 (rxcw & E1000_RXCW_C))
1775 if (rxcw & E1000_RXCW_IV) {
1776 mac->serdes_has_link = FALSE;
1777 mac->serdes_link_state =
1778 e1000_serdes_link_down;
1779 DEBUGOUT("ANYSTATE -> DOWN\n");
1784 if (i == AN_RETRY_COUNT) {
1785 txcw = E1000_READ_REG(hw, E1000_TXCW);
1786 txcw |= E1000_TXCW_ANE;
1787 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1788 mac->serdes_link_state =
1789 e1000_serdes_link_autoneg_progress;
1790 mac->serdes_has_link = FALSE;
1791 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1800 * e1000_valid_led_default_82571 - Verify a valid default LED config
1801 * @hw: pointer to the HW structure
1802 * @data: pointer to the NVM (EEPROM)
1804 * Read the EEPROM for the current default LED configuration. If the
1805 * LED configuration is not valid, set to a valid LED configuration.
1807 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1811 DEBUGFUNC("e1000_valid_led_default_82571");
1813 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1815 DEBUGOUT("NVM Read Error\n");
1819 switch (hw->mac.type) {
1823 if (*data == ID_LED_RESERVED_F746)
1824 *data = ID_LED_DEFAULT_82573;
1827 if (*data == ID_LED_RESERVED_0000 ||
1828 *data == ID_LED_RESERVED_FFFF)
1829 *data = ID_LED_DEFAULT;
1833 return E1000_SUCCESS;
1837 * e1000_get_laa_state_82571 - Get locally administered address state
1838 * @hw: pointer to the HW structure
1840 * Retrieve and return the current locally administered address state.
1842 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1844 DEBUGFUNC("e1000_get_laa_state_82571");
1846 if (hw->mac.type != e1000_82571)
1849 return hw->dev_spec._82571.laa_is_present;
1853 * e1000_set_laa_state_82571 - Set locally administered address state
1854 * @hw: pointer to the HW structure
1855 * @state: enable/disable locally administered address
1857 * Enable/Disable the current locally administered address state.
1859 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1861 DEBUGFUNC("e1000_set_laa_state_82571");
1863 if (hw->mac.type != e1000_82571)
1866 hw->dev_spec._82571.laa_is_present = state;
1868 /* If workaround is activated... */
1870 /* Hold a copy of the LAA in RAR[14] This is done so that
1871 * between the time RAR[0] gets clobbered and the time it
1872 * gets fixed, the actual LAA is in one of the RARs and no
1873 * incoming packets directed to this port are dropped.
1874 * Eventually the LAA will be in RAR[0] and RAR[14].
1876 hw->mac.ops.rar_set(hw, hw->mac.addr,
1877 hw->mac.rar_entry_count - 1);
1882 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1883 * @hw: pointer to the HW structure
1885 * Verifies that the EEPROM has completed the update. After updating the
1886 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1887 * the checksum fix is not implemented, we need to set the bit and update
1888 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1889 * we need to return bad checksum.
1891 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1893 struct e1000_nvm_info *nvm = &hw->nvm;
1897 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1899 if (nvm->type != e1000_nvm_flash_hw)
1900 return E1000_SUCCESS;
1902 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1903 * 10h-12h. Checksum may need to be fixed.
1905 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1909 if (!(data & 0x10)) {
1910 /* Read 0x23 and check bit 15. This bit is a 1
1911 * when the checksum has already been fixed. If
1912 * the checksum is still wrong and this bit is a
1913 * 1, we need to return bad checksum. Otherwise,
1914 * we need to set this bit to a 1 and update the
1917 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1921 if (!(data & 0x8000)) {
1923 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1926 ret_val = nvm->ops.update(hw);
1932 return E1000_SUCCESS;
1937 * e1000_read_mac_addr_82571 - Read device MAC address
1938 * @hw: pointer to the HW structure
1940 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1942 DEBUGFUNC("e1000_read_mac_addr_82571");
1944 if (hw->mac.type == e1000_82571) {
1947 /* If there's an alternate MAC address place it in RAR0
1948 * so that it will override the Si installed default perm
1951 ret_val = e1000_check_alt_mac_addr_generic(hw);
1956 return e1000_read_mac_addr_generic(hw);
1960 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1961 * @hw: pointer to the HW structure
1963 * In the case of a PHY power down to save power, or to turn off link during a
1964 * driver unload, or wake on lan is not enabled, remove the link.
1966 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1968 struct e1000_phy_info *phy = &hw->phy;
1969 struct e1000_mac_info *mac = &hw->mac;
1971 if (!phy->ops.check_reset_block)
1974 /* If the management interface is not enabled, then power down */
1975 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1976 e1000_power_down_phy_copper(hw);
1982 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1983 * @hw: pointer to the HW structure
1985 * Clears the hardware counters by reading the counter registers.
1987 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1989 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1991 e1000_clear_hw_cntrs_base_generic(hw);
1993 E1000_READ_REG(hw, E1000_PRC64);
1994 E1000_READ_REG(hw, E1000_PRC127);
1995 E1000_READ_REG(hw, E1000_PRC255);
1996 E1000_READ_REG(hw, E1000_PRC511);
1997 E1000_READ_REG(hw, E1000_PRC1023);
1998 E1000_READ_REG(hw, E1000_PRC1522);
1999 E1000_READ_REG(hw, E1000_PTC64);
2000 E1000_READ_REG(hw, E1000_PTC127);
2001 E1000_READ_REG(hw, E1000_PTC255);
2002 E1000_READ_REG(hw, E1000_PTC511);
2003 E1000_READ_REG(hw, E1000_PTC1023);
2004 E1000_READ_REG(hw, E1000_PTC1522);
2006 E1000_READ_REG(hw, E1000_ALGNERRC);
2007 E1000_READ_REG(hw, E1000_RXERRC);
2008 E1000_READ_REG(hw, E1000_TNCRS);
2009 E1000_READ_REG(hw, E1000_CEXTERR);
2010 E1000_READ_REG(hw, E1000_TSCTC);
2011 E1000_READ_REG(hw, E1000_TSCTFC);
2013 E1000_READ_REG(hw, E1000_MGTPRC);
2014 E1000_READ_REG(hw, E1000_MGTPDC);
2015 E1000_READ_REG(hw, E1000_MGTPTC);
2017 E1000_READ_REG(hw, E1000_IAC);
2018 E1000_READ_REG(hw, E1000_ICRXOC);
2020 E1000_READ_REG(hw, E1000_ICRXPTC);
2021 E1000_READ_REG(hw, E1000_ICRXATC);
2022 E1000_READ_REG(hw, E1000_ICTXPTC);
2023 E1000_READ_REG(hw, E1000_ICTXATC);
2024 E1000_READ_REG(hw, E1000_ICTXQEC);
2025 E1000_READ_REG(hw, E1000_ICTXQMTC);
2026 E1000_READ_REG(hw, E1000_ICRXDMTC);