sys/dev/e1000/e1000_82575.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2013, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82575EB Gigabit Network Connection
  37  * 82575EB Gigabit Backplane Connection
  38  * 82575GB Gigabit Network Connection
  39  * 82576 Gigabit Network Connection
  40  * 82576 Quad Port Gigabit Mezzanine Adapter
  41  * 82580 Gigabit Network Connection
  42  * I350 Gigabit Network Connection
  43  */
  44
  45 #include "e1000_api.h"
  46 #include "e1000_i210.h"
  47
  48 static s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  49 static s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  50 static s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  51 static void e1000_release_phy_82575(struct e1000_hw *hw);
  52 static s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
  54 static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  55 static s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  56 static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  57 static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  58                                          u16 *duplex);
  59 static s32  e1000_init_hw_82575(struct e1000_hw *hw);
  60 static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  61 static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  62                                            u16 *data);
  63 static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  64 static s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  65 static s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  66                                      u32 offset, u16 *data);
  67 static s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  68                                       u32 offset, u16 data);
  69 static s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  70                                           bool active);
  71 static s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  72                                           bool active);
  73 static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  74                                           bool active);
  75 static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  76 static s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  77 static s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  78 static s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  79 static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  80 static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  81                                             u32 offset, u16 data);
  82 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  83 static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  84 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  85                                                  u16 *speed, u16 *duplex);
  86 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  87 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  88 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  89 static s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  90 static s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  91 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  92 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  93 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  94 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  95 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  96 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  97 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  98 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  99 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
 100                                                  u16 offset);
 101 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 102                                                    u16 offset);
 103 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 104 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 105 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 106 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
 107
 108 static void e1000_i2c_start(struct e1000_hw *hw);
 109 static void e1000_i2c_stop(struct e1000_hw *hw);
 110 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 111 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 112 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 113 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 114 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 115 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 116 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 117 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 118 static bool e1000_get_i2c_data(u32 *i2cctl);
 119
 120 static const u16 e1000_82580_rxpbs_table[] = {
 121         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 122 #define E1000_82580_RXPBS_TABLE_SIZE \
 123         (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
 124
 125
 126 /**
 127  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 128  *  @hw: pointer to the HW structure
 129  *
 130  *  Called to determine if the I2C pins are being used for I2C or as an
 131  *  external MDIO interface since the two options are mutually exclusive.
 132  **/
 133 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 134 {
 135         u32 reg = 0;
 136         bool ext_mdio = FALSE;
 137
 138         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 139
 140         switch (hw->mac.type) {
 141         case e1000_82575:
 142         case e1000_82576:
 143                 reg = E1000_READ_REG(hw, E1000_MDIC);
 144                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 145                 break;
 146         case e1000_82580:
 147         case e1000_i350:
 148         case e1000_i354:
 149         case e1000_i210:
 150         case e1000_i211:
 151                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 152                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 153                 break;
 154         default:
 155                 break;
 156         }
 157         return ext_mdio;
 158 }
 159
 160 /**
 161  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 162  *  @hw: pointer to the HW structure
 163  **/
 164 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 165 {
 166         struct e1000_phy_info *phy = &hw->phy;
 167         s32 ret_val = E1000_SUCCESS;
 168         u32 ctrl_ext;
 169
 170         DEBUGFUNC("e1000_init_phy_params_82575");
 171
 172         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 173         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 174
 175         if (hw->phy.media_type != e1000_media_type_copper) {
 176                 phy->type = e1000_phy_none;
 177                 goto out;
 178         }
 179
 180         phy->ops.power_up   = e1000_power_up_phy_copper;
 181         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 182
 183         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 184         phy->reset_delay_us     = 100;
 185
 186         phy->ops.acquire        = e1000_acquire_phy_82575;
 187         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 188         phy->ops.commit         = e1000_phy_sw_reset_generic;
 189         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 190         phy->ops.release        = e1000_release_phy_82575;
 191
 192         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 193
 194         if (e1000_sgmii_active_82575(hw)) {
 195                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 196                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 197         } else {
 198                 phy->ops.reset = e1000_phy_hw_reset_generic;
 199                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 200         }
 201
 202         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 203         e1000_reset_mdicnfg_82580(hw);
 204
 205         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 206                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 207                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 208         } else {
 209                 switch (hw->mac.type) {
 210                 case e1000_82580:
 211                 case e1000_i350:
 212                 case e1000_i354:
 213                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 214                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 215                         break;
 216                 case e1000_i210:
 217                 case e1000_i211:
 218                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 219                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 220                         break;
 221                 default:
 222                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 223                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 224                 }
 225         }
 226
 227         /* Set phy->phy_addr and phy->id. */
 228         ret_val = e1000_get_phy_id_82575(hw);
 229
 230         /* Verify phy id and set remaining function pointers */
 231         switch (phy->id) {
 232         case M88E1543_E_PHY_ID:
 233         case M88E1512_E_PHY_ID:
 234         case I347AT4_E_PHY_ID:
 235         case M88E1112_E_PHY_ID:
 236         case M88E1340M_E_PHY_ID:
 237         case M88E1111_I_PHY_ID:
 238                 phy->type               = e1000_phy_m88;
 239                 phy->ops.check_polarity = e1000_check_polarity_m88;
 240                 phy->ops.get_info       = e1000_get_phy_info_m88;
 241                 if (phy->id == I347AT4_E_PHY_ID ||
 242                     phy->id == M88E1112_E_PHY_ID ||
 243                     phy->id == M88E1340M_E_PHY_ID)
 244                         phy->ops.get_cable_length =
 245                                          e1000_get_cable_length_m88_gen2;
 246                 else if (phy->id == M88E1543_E_PHY_ID ||
 247                          phy->id == M88E1512_E_PHY_ID)
 248                         phy->ops.get_cable_length =
 249                                          e1000_get_cable_length_m88_gen2;
 250                 else
 251                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 252                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 253                 /* Check if this PHY is confgured for media swap. */
 254                 if (phy->id == M88E1112_E_PHY_ID) {
 255                         u16 data;
 256
 257                         ret_val = phy->ops.write_reg(hw,
 258                                                      E1000_M88E1112_PAGE_ADDR,
 259                                                      2);
 260                         if (ret_val)
 261                                 goto out;
 262
 263                         ret_val = phy->ops.read_reg(hw,
 264                                                     E1000_M88E1112_MAC_CTRL_1,
 265                                                     &data);
 266                         if (ret_val)
 267                                 goto out;
 268
 269                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 270                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 271                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 272                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 273                                 hw->mac.ops.check_for_link =
 274                                                 e1000_check_for_link_media_swap;
 275                 }
 276                 break;
 277         case IGP03E1000_E_PHY_ID:
 278         case IGP04E1000_E_PHY_ID:
 279                 phy->type = e1000_phy_igp_3;
 280                 phy->ops.check_polarity = e1000_check_polarity_igp;
 281                 phy->ops.get_info = e1000_get_phy_info_igp;
 282                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 283                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 284                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 285                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 286                 break;
 287         case I82580_I_PHY_ID:
 288         case I350_I_PHY_ID:
 289                 phy->type = e1000_phy_82580;
 290                 phy->ops.check_polarity = e1000_check_polarity_82577;
 291                 phy->ops.force_speed_duplex =
 292                                          e1000_phy_force_speed_duplex_82577;
 293                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 294                 phy->ops.get_info = e1000_get_phy_info_82577;
 295                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 296                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 297                 break;
 298         case I210_I_PHY_ID:
 299                 phy->type               = e1000_phy_i210;
 300                 phy->ops.check_polarity = e1000_check_polarity_m88;
 301                 phy->ops.get_info       = e1000_get_phy_info_m88;
 302                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 303                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 304                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 305                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 306                 break;
 307         default:
 308                 ret_val = -E1000_ERR_PHY;
 309                 goto out;
 310         }
 311
 312 out:
 313         return ret_val;
 314 }
 315
 316 /**
 317  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 318  *  @hw: pointer to the HW structure
 319  **/
 320 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 321 {
 322         struct e1000_nvm_info *nvm = &hw->nvm;
 323         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 324         u16 size;
 325
 326         DEBUGFUNC("e1000_init_nvm_params_82575");
 327
 328         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 329                      E1000_EECD_SIZE_EX_SHIFT);
 330         /*
 331          * Added to a constant, "size" becomes the left-shift value
 332          * for setting word_size.
 333          */
 334         size += NVM_WORD_SIZE_BASE_SHIFT;
 335
 336         /* Just in case size is out of range, cap it to the largest
 337          * EEPROM size supported
 338          */
 339         if (size > 15)
 340                 size = 15;
 341
 342         nvm->word_size = 1 << size;
 343         if (hw->mac.type < e1000_i210) {
 344                 nvm->opcode_bits = 8;
 345                 nvm->delay_usec = 1;
 346
 347                 switch (nvm->override) {
 348                 case e1000_nvm_override_spi_large:
 349                         nvm->page_size = 32;
 350                         nvm->address_bits = 16;
 351                         break;
 352                 case e1000_nvm_override_spi_small:
 353                         nvm->page_size = 8;
 354                         nvm->address_bits = 8;
 355                         break;
 356                 default:
 357                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 358                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 359                                             16 : 8;
 360                         break;
 361                 }
 362                 if (nvm->word_size == (1 << 15))
 363                         nvm->page_size = 128;
 364
 365                 nvm->type = e1000_nvm_eeprom_spi;
 366         } else {
 367                 nvm->type = e1000_nvm_flash_hw;
 368         }
 369
 370         /* Function Pointers */
 371         nvm->ops.acquire = e1000_acquire_nvm_82575;
 372         nvm->ops.release = e1000_release_nvm_82575;
 373         if (nvm->word_size < (1 << 15))
 374                 nvm->ops.read = e1000_read_nvm_eerd;
 375         else
 376                 nvm->ops.read = e1000_read_nvm_spi;
 377
 378         nvm->ops.write = e1000_write_nvm_spi;
 379         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 380         nvm->ops.update = e1000_update_nvm_checksum_generic;
 381         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 382
 383         /* override generic family function pointers for specific descendants */
 384         switch (hw->mac.type) {
 385         case e1000_82580:
 386                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 387                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 388                 break;
 389         case e1000_i350:
 390         case e1000_i354:
 391                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 392                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 393                 break;
 394         default:
 395                 break;
 396         }
 397
 398         return E1000_SUCCESS;
 399 }
 400
 401 /**
 402  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 403  *  @hw: pointer to the HW structure
 404  **/
 405 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 406 {
 407         struct e1000_mac_info *mac = &hw->mac;
 408         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 409
 410         DEBUGFUNC("e1000_init_mac_params_82575");
 411
 412         /* Derives media type */
 413         e1000_get_media_type_82575(hw);
 414         /* Set mta register count */
 415         mac->mta_reg_count = 128;
 416         /* Set uta register count */
 417         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 418         /* Set rar entry count */
 419         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 420         if (mac->type == e1000_82576)
 421                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 422         if (mac->type == e1000_82580)
 423                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 424         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 425                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 426
 427         /* Enable EEE default settings for EEE supported devices */
 428         if (mac->type >= e1000_i350)
 429                 dev_spec->eee_disable = FALSE;
 430
 431         /* Allow a single clear of the SW semaphore on I210 and newer */
 432         if (mac->type >= e1000_i210)
 433                 dev_spec->clear_semaphore_once = TRUE;
 434
 435         /* Set if part includes ASF firmware */
 436         mac->asf_firmware_present = TRUE;
 437         /* FWSM register */
 438         mac->has_fwsm = TRUE;
 439         /* ARC supported; valid only if manageability features are enabled. */
 440         mac->arc_subsystem_valid =
 441                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 442
 443         /* Function pointers */
 444
 445         /* bus type/speed/width */
 446         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 447         /* reset */
 448         if (mac->type >= e1000_82580)
 449                 mac->ops.reset_hw = e1000_reset_hw_82580;
 450         else
 451         mac->ops.reset_hw = e1000_reset_hw_82575;
 452         /* hw initialization */
 453         mac->ops.init_hw = e1000_init_hw_82575;
 454         /* link setup */
 455         mac->ops.setup_link = e1000_setup_link_generic;
 456         /* physical interface link setup */
 457         mac->ops.setup_physical_interface =
 458                 (hw->phy.media_type == e1000_media_type_copper)
 459                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 460         /* physical interface shutdown */
 461         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 462         /* physical interface power up */
 463         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 464         /* check for link */
 465         mac->ops.check_for_link = e1000_check_for_link_82575;
 466         /* read mac address */
 467         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 468         /* configure collision distance */
 469         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 470         /* multicast address update */
 471         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 472         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 473                 /* writing VFTA */
 474                 mac->ops.write_vfta = e1000_write_vfta_i350;
 475                 /* clearing VFTA */
 476                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 477         } else {
 478                 /* writing VFTA */
 479                 mac->ops.write_vfta = e1000_write_vfta_generic;
 480                 /* clearing VFTA */
 481                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 482         }
 483         if (hw->mac.type >= e1000_82580)
 484                 mac->ops.validate_mdi_setting =
 485                                 e1000_validate_mdi_setting_crossover_generic;
 486         /* ID LED init */
 487         mac->ops.id_led_init = e1000_id_led_init_generic;
 488         /* blink LED */
 489         mac->ops.blink_led = e1000_blink_led_generic;
 490         /* setup LED */
 491         mac->ops.setup_led = e1000_setup_led_generic;
 492         /* cleanup LED */
 493         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 494         /* turn on/off LED */
 495         mac->ops.led_on = e1000_led_on_generic;
 496         mac->ops.led_off = e1000_led_off_generic;
 497         /* clear hardware counters */
 498         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 499         /* link info */
 500         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 501         /* acquire SW_FW sync */
 502         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 503         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 504         if (mac->type >= e1000_i210) {
 505                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 506                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 507         }
 508
 509         /* set lan id for port to determine which phy lock to use */
 510         hw->mac.ops.set_lan_id(hw);
 511
 512         return E1000_SUCCESS;
 513 }
 514
 515 /**
 516  *  e1000_init_function_pointers_82575 - Init func ptrs.
 517  *  @hw: pointer to the HW structure
 518  *
 519  *  Called to initialize all function pointers and parameters.
 520  **/
 521 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 522 {
 523         DEBUGFUNC("e1000_init_function_pointers_82575");
 524
 525         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 526         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 527         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 528         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 529 }
 530
 531 /**
 532  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 533  *  @hw: pointer to the HW structure
 534  *
 535  *  Acquire access rights to the correct PHY.
 536  **/
 537 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 538 {
 539         u16 mask = E1000_SWFW_PHY0_SM;
 540
 541         DEBUGFUNC("e1000_acquire_phy_82575");
 542
 543         if (hw->bus.func == E1000_FUNC_1)
 544                 mask = E1000_SWFW_PHY1_SM;
 545         else if (hw->bus.func == E1000_FUNC_2)
 546                 mask = E1000_SWFW_PHY2_SM;
 547         else if (hw->bus.func == E1000_FUNC_3)
 548                 mask = E1000_SWFW_PHY3_SM;
 549
 550         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 551 }
 552
 553 /**
 554  *  e1000_release_phy_82575 - Release rights to access PHY
 555  *  @hw: pointer to the HW structure
 556  *
 557  *  A wrapper to release access rights to the correct PHY.
 558  **/
 559 static void e1000_release_phy_82575(struct e1000_hw *hw)
 560 {
 561         u16 mask = E1000_SWFW_PHY0_SM;
 562
 563         DEBUGFUNC("e1000_release_phy_82575");
 564
 565         if (hw->bus.func == E1000_FUNC_1)
 566                 mask = E1000_SWFW_PHY1_SM;
 567         else if (hw->bus.func == E1000_FUNC_2)
 568                 mask = E1000_SWFW_PHY2_SM;
 569         else if (hw->bus.func == E1000_FUNC_3)
 570                 mask = E1000_SWFW_PHY3_SM;
 571
 572         hw->mac.ops.release_swfw_sync(hw, mask);
 573 }
 574
 575 /**
 576  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 577  *  @hw: pointer to the HW structure
 578  *  @offset: register offset to be read
 579  *  @data: pointer to the read data
 580  *
 581  *  Reads the PHY register at offset using the serial gigabit media independent
 582  *  interface and stores the retrieved information in data.
 583  **/
 584 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 585                                           u16 *data)
 586 {
 587         s32 ret_val = -E1000_ERR_PARAM;
 588
 589         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 590
 591         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 592                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 593                 goto out;
 594         }
 595
 596         ret_val = hw->phy.ops.acquire(hw);
 597         if (ret_val)
 598                 goto out;
 599
 600         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 601
 602         hw->phy.ops.release(hw);
 603
 604 out:
 605         return ret_val;
 606 }
 607
 608 /**
 609  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 610  *  @hw: pointer to the HW structure
 611  *  @offset: register offset to write to
 612  *  @data: data to write at register offset
 613  *
 614  *  Writes the data to PHY register at the offset using the serial gigabit
 615  *  media independent interface.
 616  **/
 617 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 618                                            u16 data)
 619 {
 620         s32 ret_val = -E1000_ERR_PARAM;
 621
 622         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 623
 624         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 625                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 626                 goto out;
 627         }
 628
 629         ret_val = hw->phy.ops.acquire(hw);
 630         if (ret_val)
 631                 goto out;
 632
 633         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 634
 635         hw->phy.ops.release(hw);
 636
 637 out:
 638         return ret_val;
 639 }
 640
 641 /**
 642  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 643  *  @hw: pointer to the HW structure
 644  *
 645  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 646  *  sgmi interface.
 647  **/
 648 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 649 {
 650         struct e1000_phy_info *phy = &hw->phy;
 651         s32  ret_val = E1000_SUCCESS;
 652         u16 phy_id;
 653         u32 ctrl_ext;
 654         u32 mdic;
 655
 656         DEBUGFUNC("e1000_get_phy_id_82575");
 657
 658         /* some i354 devices need an extra read for phy id */
 659         if (hw->mac.type == e1000_i354)
 660                 e1000_get_phy_id(hw);
 661
 662         /*
 663          * For SGMII PHYs, we try the list of possible addresses until
 664          * we find one that works.  For non-SGMII PHYs
 665          * (e.g. integrated copper PHYs), an address of 1 should
 666          * work.  The result of this function should mean phy->phy_addr
 667          * and phy->id are set correctly.
 668          */
 669         if (!e1000_sgmii_active_82575(hw)) {
 670                 phy->addr = 1;
 671                 ret_val = e1000_get_phy_id(hw);
 672                 goto out;
 673         }
 674
 675         if (e1000_sgmii_uses_mdio_82575(hw)) {
 676                 switch (hw->mac.type) {
 677                 case e1000_82575:
 678                 case e1000_82576:
 679                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 680                         mdic &= E1000_MDIC_PHY_MASK;
 681                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 682                         break;
 683                 case e1000_82580:
 684                 case e1000_i350:
 685                 case e1000_i354:
 686                 case e1000_i210:
 687                 case e1000_i211:
 688                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 689                         mdic &= E1000_MDICNFG_PHY_MASK;
 690                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 691                         break;
 692                 default:
 693                         ret_val = -E1000_ERR_PHY;
 694                         goto out;
 695                         break;
 696                 }
 697                 ret_val = e1000_get_phy_id(hw);
 698                 goto out;
 699         }
 700
 701         /* Power on sgmii phy if it is disabled */
 702         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 703         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 704                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 705         E1000_WRITE_FLUSH(hw);
 706         msec_delay(300);
 707
 708         /*
 709          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 710          * Therefore, we need to test 1-7
 711          */
 712         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 713                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 714                 if (ret_val == E1000_SUCCESS) {
 715                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 716                                   phy_id, phy->addr);
 717                         /*
 718                          * At the time of this writing, The M88 part is
 719                          * the only supported SGMII PHY product.
 720                          */
 721                         if (phy_id == M88_VENDOR)
 722                                 break;
 723                 } else {
 724                         DEBUGOUT1("PHY address %u was unreadable\n",
 725                                   phy->addr);
 726                 }
 727         }
 728
 729         /* A valid PHY type couldn't be found. */
 730         if (phy->addr == 8) {
 731                 phy->addr = 0;
 732                 ret_val = -E1000_ERR_PHY;
 733         } else {
 734                 ret_val = e1000_get_phy_id(hw);
 735         }
 736
 737         /* restore previous sfp cage power state */
 738         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 739
 740 out:
 741         return ret_val;
 742 }
 743
 744 /**
 745  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 746  *  @hw: pointer to the HW structure
 747  *
 748  *  Resets the PHY using the serial gigabit media independent interface.
 749  **/
 750 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 751 {
 752         s32 ret_val = E1000_SUCCESS;
 753
 754         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 755
 756         /*
 757          * This isn't a TRUE "hard" reset, but is the only reset
 758          * available to us at this time.
 759          */
 760
 761         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 762
 763         if (!(hw->phy.ops.write_reg))
 764                 goto out;
 765
 766         /*
 767          * SFP documentation requires the following to configure the SPF module
 768          * to work on SGMII.  No further documentation is given.
 769          */
 770         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 771         if (ret_val)
 772                 goto out;
 773
 774         ret_val = hw->phy.ops.commit(hw);
 775
 776 out:
 777         return ret_val;
 778 }
 779
 780 /**
 781  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 782  *  @hw: pointer to the HW structure
 783  *  @active: TRUE to enable LPLU, FALSE to disable
 784  *
 785  *  Sets the LPLU D0 state according to the active flag.  When
 786  *  activating LPLU this function also disables smart speed
 787  *  and vice versa.  LPLU will not be activated unless the
 788  *  device autonegotiation advertisement meets standards of
 789  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 790  *  This is a function pointer entry point only called by
 791  *  PHY setup routines.
 792  **/
 793 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 794 {
 795         struct e1000_phy_info *phy = &hw->phy;
 796         s32 ret_val = E1000_SUCCESS;
 797         u16 data;
 798
 799         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 800
 801         if (!(hw->phy.ops.read_reg))
 802                 goto out;
 803
 804         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 805         if (ret_val)
 806                 goto out;
 807
 808         if (active) {
 809                 data |= IGP02E1000_PM_D0_LPLU;
 810                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 811                                              data);
 812                 if (ret_val)
 813                         goto out;
 814
 815                 /* When LPLU is enabled, we should disable SmartSpeed */
 816                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 817                                             &data);
 818                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 819                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 820                                              data);
 821                 if (ret_val)
 822                         goto out;
 823         } else {
 824                 data &= ~IGP02E1000_PM_D0_LPLU;
 825                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 826                                              data);
 827                 /*
 828                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 829                  * during Dx states where the power conservation is most
 830                  * important.  During driver activity we should enable
 831                  * SmartSpeed, so performance is maintained.
 832                  */
 833                 if (phy->smart_speed == e1000_smart_speed_on) {
 834                         ret_val = phy->ops.read_reg(hw,
 835                                                     IGP01E1000_PHY_PORT_CONFIG,
 836                                                     &data);
 837                         if (ret_val)
 838                                 goto out;
 839
 840                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 841                         ret_val = phy->ops.write_reg(hw,
 842                                                      IGP01E1000_PHY_PORT_CONFIG,
 843                                                      data);
 844                         if (ret_val)
 845                                 goto out;
 846                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 847                         ret_val = phy->ops.read_reg(hw,
 848                                                     IGP01E1000_PHY_PORT_CONFIG,
 849                                                     &data);
 850                         if (ret_val)
 851                                 goto out;
 852
 853                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 854                         ret_val = phy->ops.write_reg(hw,
 855                                                      IGP01E1000_PHY_PORT_CONFIG,
 856                                                      data);
 857                         if (ret_val)
 858                                 goto out;
 859                 }
 860         }
 861
 862 out:
 863         return ret_val;
 864 }
 865
 866 /**
 867  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 868  *  @hw: pointer to the HW structure
 869  *  @active: TRUE to enable LPLU, FALSE to disable
 870  *
 871  *  Sets the LPLU D0 state according to the active flag.  When
 872  *  activating LPLU this function also disables smart speed
 873  *  and vice versa.  LPLU will not be activated unless the
 874  *  device autonegotiation advertisement meets standards of
 875  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 876  *  This is a function pointer entry point only called by
 877  *  PHY setup routines.
 878  **/
 879 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 880 {
 881         struct e1000_phy_info *phy = &hw->phy;
 882         s32 ret_val = E1000_SUCCESS;
 883         u32 data;
 884
 885         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 886
 887         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 888
 889         if (active) {
 890                 data |= E1000_82580_PM_D0_LPLU;
 891
 892                 /* When LPLU is enabled, we should disable SmartSpeed */
 893                 data &= ~E1000_82580_PM_SPD;
 894         } else {
 895                 data &= ~E1000_82580_PM_D0_LPLU;
 896
 897                 /*
 898                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 899                  * during Dx states where the power conservation is most
 900                  * important.  During driver activity we should enable
 901                  * SmartSpeed, so performance is maintained.
 902                  */
 903                 if (phy->smart_speed == e1000_smart_speed_on)
 904                         data |= E1000_82580_PM_SPD;
 905                 else if (phy->smart_speed == e1000_smart_speed_off)
 906                         data &= ~E1000_82580_PM_SPD;
 907         }
 908
 909         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 910         return ret_val;
 911 }
 912
 913 /**
 914  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 915  *  @hw: pointer to the HW structure
 916  *  @active: boolean used to enable/disable lplu
 917  *
 918  *  Success returns 0, Failure returns 1
 919  *
 920  *  The low power link up (lplu) state is set to the power management level D3
 921  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
 922  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 923  *  is used during Dx states where the power conservation is most important.
 924  *  During driver activity, SmartSpeed should be enabled so performance is
 925  *  maintained.
 926  **/
 927 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 928 {
 929         struct e1000_phy_info *phy = &hw->phy;
 930         s32 ret_val = E1000_SUCCESS;
 931         u32 data;
 932
 933         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 934
 935         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 936
 937         if (!active) {
 938                 data &= ~E1000_82580_PM_D3_LPLU;
 939                 /*
 940                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 941                  * during Dx states where the power conservation is most
 942                  * important.  During driver activity we should enable
 943                  * SmartSpeed, so performance is maintained.
 944                  */
 945                 if (phy->smart_speed == e1000_smart_speed_on)
 946                         data |= E1000_82580_PM_SPD;
 947                 else if (phy->smart_speed == e1000_smart_speed_off)
 948                         data &= ~E1000_82580_PM_SPD;
 949         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 950                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 951                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 952                 data |= E1000_82580_PM_D3_LPLU;
 953                 /* When LPLU is enabled, we should disable SmartSpeed */
 954                 data &= ~E1000_82580_PM_SPD;
 955         }
 956
 957         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 958         return ret_val;
 959 }
 960
 961 /**
 962  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 963  *  @hw: pointer to the HW structure
 964  *
 965  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 966  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 967  *  Return successful if access grant bit set, else clear the request for
 968  *  EEPROM access and return -E1000_ERR_NVM (-1).
 969  **/
 970 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 971 {
 972         s32 ret_val;
 973
 974         DEBUGFUNC("e1000_acquire_nvm_82575");
 975
 976         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 977         if (ret_val)
 978                 goto out;
 979
 980         /*
 981          * Check if there is some access
 982          * error this access may hook on
 983          */
 984         if (hw->mac.type == e1000_i350) {
 985                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 986                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 987                     E1000_EECD_TIMEOUT)) {
 988                         /* Clear all access error flags */
 989                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 990                                         E1000_EECD_ERROR_CLR);
 991                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
 992                 }
 993         }
 994         if (hw->mac.type == e1000_82580) {
 995                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 996                 if (eecd & E1000_EECD_BLOCKED) {
 997                         /* Clear access error flag */
 998                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
 999                                         E1000_EECD_BLOCKED);
1000                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1001                 }
1002         }
1003
1004
1005         ret_val = e1000_acquire_nvm_generic(hw);
1006         if (ret_val)
1007                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1008
1009 out:
1010         return ret_val;
1011 }
1012
1013 /**
1014  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1015  *  @hw: pointer to the HW structure
1016  *
1017  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1018  *  then release the semaphores acquired.
1019  **/
1020 static void e1000_release_nvm_82575(struct e1000_hw *hw)
1021 {
1022         DEBUGFUNC("e1000_release_nvm_82575");
1023
1024         e1000_release_nvm_generic(hw);
1025
1026         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1027 }
1028
1029 /**
1030  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1031  *  @hw: pointer to the HW structure
1032  *  @mask: specifies which semaphore to acquire
1033  *
1034  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1035  *  will also specify which port we're acquiring the lock for.
1036  **/
1037 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1038 {
1039         u32 swfw_sync;
1040         u32 swmask = mask;
1041         u32 fwmask = mask << 16;
1042         s32 ret_val = E1000_SUCCESS;
1043         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1044
1045         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1046
1047         while (i < timeout) {
1048                 if (e1000_get_hw_semaphore_generic(hw)) {
1049                         ret_val = -E1000_ERR_SWFW_SYNC;
1050                         goto out;
1051                 }
1052
1053                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1054                 if (!(swfw_sync & (fwmask | swmask)))
1055                         break;
1056
1057                 /*
1058                  * Firmware currently using resource (fwmask)
1059                  * or other software thread using resource (swmask)
1060                  */
1061                 e1000_put_hw_semaphore_generic(hw);
1062                 msec_delay_irq(5);
1063                 i++;
1064         }
1065
1066         if (i == timeout) {
1067                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1068                 ret_val = -E1000_ERR_SWFW_SYNC;
1069                 goto out;
1070         }
1071
1072         swfw_sync |= swmask;
1073         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1074
1075         e1000_put_hw_semaphore_generic(hw);
1076
1077 out:
1078         return ret_val;
1079 }
1080
1081 /**
1082  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1083  *  @hw: pointer to the HW structure
1084  *  @mask: specifies which semaphore to acquire
1085  *
1086  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1087  *  will also specify which port we're releasing the lock for.
1088  **/
1089 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1090 {
1091         u32 swfw_sync;
1092
1093         DEBUGFUNC("e1000_release_swfw_sync_82575");
1094
1095         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1096                 ; /* Empty */
1097
1098         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1099         swfw_sync &= ~mask;
1100         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1101
1102         e1000_put_hw_semaphore_generic(hw);
1103 }
1104
1105 /**
1106  *  e1000_get_cfg_done_82575 - Read config done bit
1107  *  @hw: pointer to the HW structure
1108  *
1109  *  Read the management control register for the config done bit for
1110  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1111  *  to read the config done bit, so an error is *ONLY* logged and returns
1112  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1113  *  would not be able to be reset or change link.
1114  **/
1115 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1116 {
1117         s32 timeout = PHY_CFG_TIMEOUT;
1118         s32 ret_val = E1000_SUCCESS;
1119         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1120
1121         DEBUGFUNC("e1000_get_cfg_done_82575");
1122
1123         if (hw->bus.func == E1000_FUNC_1)
1124                 mask = E1000_NVM_CFG_DONE_PORT_1;
1125         else if (hw->bus.func == E1000_FUNC_2)
1126                 mask = E1000_NVM_CFG_DONE_PORT_2;
1127         else if (hw->bus.func == E1000_FUNC_3)
1128                 mask = E1000_NVM_CFG_DONE_PORT_3;
1129         while (timeout) {
1130                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1131                         break;
1132                 msec_delay(1);
1133                 timeout--;
1134         }
1135         if (!timeout)
1136                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1137
1138         /* If EEPROM is not marked present, init the PHY manually */
1139         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1140             (hw->phy.type == e1000_phy_igp_3))
1141                 e1000_phy_init_script_igp3(hw);
1142
1143         return ret_val;
1144 }
1145
1146 /**
1147  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1148  *  @hw: pointer to the HW structure
1149  *  @speed: stores the current speed
1150  *  @duplex: stores the current duplex
1151  *
1152  *  This is a wrapper function, if using the serial gigabit media independent
1153  *  interface, use PCS to retrieve the link speed and duplex information.
1154  *  Otherwise, use the generic function to get the link speed and duplex info.
1155  **/
1156 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1157                                         u16 *duplex)
1158 {
1159         s32 ret_val;
1160
1161         DEBUGFUNC("e1000_get_link_up_info_82575");
1162
1163         if (hw->phy.media_type != e1000_media_type_copper)
1164                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1165                                                                duplex);
1166         else
1167                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1168                                                                     duplex);
1169
1170         return ret_val;
1171 }
1172
1173 /**
1174  *  e1000_check_for_link_82575 - Check for link
1175  *  @hw: pointer to the HW structure
1176  *
1177  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1178  *  use the generic interface for determining link.
1179  **/
1180 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1181 {
1182         s32 ret_val;
1183         u16 speed, duplex;
1184
1185         DEBUGFUNC("e1000_check_for_link_82575");
1186
1187         if (hw->phy.media_type != e1000_media_type_copper) {
1188                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1189                                                                &duplex);
1190                 /*
1191                  * Use this flag to determine if link needs to be checked or
1192                  * not.  If we have link clear the flag so that we do not
1193                  * continue to check for link.
1194                  */
1195                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1196
1197                 /*
1198                  * Configure Flow Control now that Auto-Neg has completed.
1199                  * First, we need to restore the desired flow control
1200                  * settings because we may have had to re-autoneg with a
1201                  * different link partner.
1202                  */
1203                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1204                 if (ret_val)
1205                         DEBUGOUT("Error configuring flow control\n");
1206         } else {
1207                 ret_val = e1000_check_for_copper_link_generic(hw);
1208         }
1209
1210         return ret_val;
1211 }
1212
1213 /**
1214  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1215  *  @hw: pointer to the HW structure
1216  *
1217  *  Poll the M88E1112 interfaces to see which interface achieved link.
1218  */
1219 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1220 {
1221         struct e1000_phy_info *phy = &hw->phy;
1222         s32 ret_val;
1223         u16 data;
1224         u8 port = 0;
1225
1226         DEBUGFUNC("e1000_check_for_link_media_swap");
1227
1228         /* Check the copper medium. */
1229         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1230         if (ret_val)
1231                 return ret_val;
1232
1233         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1234         if (ret_val)
1235                 return ret_val;
1236
1237         if (data & E1000_M88E1112_STATUS_LINK)
1238                 port = E1000_MEDIA_PORT_COPPER;
1239
1240         /* Check the other medium. */
1241         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1242         if (ret_val)
1243                 return ret_val;
1244
1245         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1246         if (ret_val)
1247                 return ret_val;
1248
1249         /* reset page to 0 */
1250         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1251         if (ret_val)
1252                 return ret_val;
1253
1254         if (data & E1000_M88E1112_STATUS_LINK)
1255                 port = E1000_MEDIA_PORT_OTHER;
1256
1257         /* Determine if a swap needs to happen. */
1258         if (port && (hw->dev_spec._82575.media_port != port)) {
1259                 hw->dev_spec._82575.media_port = port;
1260                 hw->dev_spec._82575.media_changed = TRUE;
1261         } else {
1262                 ret_val = e1000_check_for_link_82575(hw);
1263         }
1264
1265         return E1000_SUCCESS;
1266 }
1267
1268 /**
1269  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1270  *  @hw: pointer to the HW structure
1271  **/
1272 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1273 {
1274         u32 reg;
1275
1276         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1277
1278         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1279             !e1000_sgmii_active_82575(hw))
1280                 return;
1281
1282         /* Enable PCS to turn on link */
1283         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1284         reg |= E1000_PCS_CFG_PCS_EN;
1285         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1286
1287         /* Power up the laser */
1288         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1289         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1290         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1291
1292         /* flush the write to verify completion */
1293         E1000_WRITE_FLUSH(hw);
1294         msec_delay(1);
1295 }
1296
1297 /**
1298  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1299  *  @hw: pointer to the HW structure
1300  *  @speed: stores the current speed
1301  *  @duplex: stores the current duplex
1302  *
1303  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1304  *  duplex, then store the values in the pointers provided.
1305  **/
1306 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1307                                                 u16 *speed, u16 *duplex)
1308 {
1309         struct e1000_mac_info *mac = &hw->mac;
1310         u32 pcs;
1311         u32 status;
1312
1313         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1314
1315         /*
1316          * Read the PCS Status register for link state. For non-copper mode,
1317          * the status register is not accurate. The PCS status register is
1318          * used instead.
1319          */
1320         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1321
1322         /*
1323          * The link up bit determines when link is up on autoneg.
1324          */
1325         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1326                 mac->serdes_has_link = TRUE;
1327
1328                 /* Detect and store PCS speed */
1329                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1330                         *speed = SPEED_1000;
1331                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1332                         *speed = SPEED_100;
1333                 else
1334                         *speed = SPEED_10;
1335
1336                 /* Detect and store PCS duplex */
1337                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1338                         *duplex = FULL_DUPLEX;
1339                 else
1340                         *duplex = HALF_DUPLEX;
1341
1342                 /* Check if it is an I354 2.5Gb backplane connection. */
1343                 if (mac->type == e1000_i354) {
1344                         status = E1000_READ_REG(hw, E1000_STATUS);
1345                         if ((status & E1000_STATUS_2P5_SKU) &&
1346                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1347                                 *speed = SPEED_2500;
1348                                 *duplex = FULL_DUPLEX;
1349                                 DEBUGOUT("2500 Mbs, ");
1350                                 DEBUGOUT("Full Duplex\n");
1351                         }
1352                 }
1353
1354         } else {
1355                 mac->serdes_has_link = FALSE;
1356                 *speed = 0;
1357                 *duplex = 0;
1358         }
1359
1360         return E1000_SUCCESS;
1361 }
1362
1363 /**
1364  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1365  *  @hw: pointer to the HW structure
1366  *
1367  *  In the case of serdes shut down sfp and PCS on driver unload
1368  *  when management pass thru is not enabled.
1369  **/
1370 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1371 {
1372         u32 reg;
1373
1374         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1375
1376         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1377             !e1000_sgmii_active_82575(hw))
1378                 return;
1379
1380         if (!e1000_enable_mng_pass_thru(hw)) {
1381                 /* Disable PCS to turn off link */
1382                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1383                 reg &= ~E1000_PCS_CFG_PCS_EN;
1384                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1385
1386                 /* shutdown the laser */
1387                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1388                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1389                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1390
1391                 /* flush the write to verify completion */
1392                 E1000_WRITE_FLUSH(hw);
1393                 msec_delay(1);
1394         }
1395
1396         return;
1397 }
1398
1399 /**
1400  *  e1000_reset_hw_82575 - Reset hardware
1401  *  @hw: pointer to the HW structure
1402  *
1403  *  This resets the hardware into a known state.
1404  **/
1405 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1406 {
1407         u32 ctrl;
1408         s32 ret_val;
1409
1410         DEBUGFUNC("e1000_reset_hw_82575");
1411
1412         /*
1413          * Prevent the PCI-E bus from sticking if there is no TLP connection
1414          * on the last TLP read/write transaction when MAC is reset.
1415          */
1416         ret_val = e1000_disable_pcie_master_generic(hw);
1417         if (ret_val)
1418                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1419
1420         /* set the completion timeout for interface */
1421         ret_val = e1000_set_pcie_completion_timeout(hw);
1422         if (ret_val)
1423                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1424
1425         DEBUGOUT("Masking off all interrupts\n");
1426         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1427
1428         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1429         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1430         E1000_WRITE_FLUSH(hw);
1431
1432         msec_delay(10);
1433
1434         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1435
1436         DEBUGOUT("Issuing a global reset to MAC\n");
1437         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1438
1439         ret_val = e1000_get_auto_rd_done_generic(hw);
1440         if (ret_val) {
1441                 /*
1442                  * When auto config read does not complete, do not
1443                  * return with an error. This can happen in situations
1444                  * where there is no eeprom and prevents getting link.
1445                  */
1446                 DEBUGOUT("Auto Read Done did not complete\n");
1447         }
1448
1449         /* If EEPROM is not present, run manual init scripts */
1450         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1451                 e1000_reset_init_script_82575(hw);
1452
1453         /* Clear any pending interrupt events. */
1454         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1455         E1000_READ_REG(hw, E1000_ICR);
1456
1457         /* Install any alternate MAC address into RAR0 */
1458         ret_val = e1000_check_alt_mac_addr_generic(hw);
1459
1460         return ret_val;
1461 }
1462
1463 /**
1464  *  e1000_init_hw_82575 - Initialize hardware
1465  *  @hw: pointer to the HW structure
1466  *
1467  *  This inits the hardware readying it for operation.
1468  **/
1469 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1470 {
1471         struct e1000_mac_info *mac = &hw->mac;
1472         s32 ret_val;
1473         u16 i, rar_count = mac->rar_entry_count;
1474
1475         DEBUGFUNC("e1000_init_hw_82575");
1476
1477         /* Initialize identification LED */
1478         ret_val = mac->ops.id_led_init(hw);
1479         if (ret_val) {
1480                 DEBUGOUT("Error initializing identification LED\n");
1481                 /* This is not fatal and we should not stop init due to this */
1482         }
1483
1484         /* Disabling VLAN filtering */
1485         DEBUGOUT("Initializing the IEEE VLAN\n");
1486         mac->ops.clear_vfta(hw);
1487
1488         /* Setup the receive address */
1489         e1000_init_rx_addrs_generic(hw, rar_count);
1490
1491         /* Zero out the Multicast HASH table */
1492         DEBUGOUT("Zeroing the MTA\n");
1493         for (i = 0; i < mac->mta_reg_count; i++)
1494                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1495
1496         /* Zero out the Unicast HASH table */
1497         DEBUGOUT("Zeroing the UTA\n");
1498         for (i = 0; i < mac->uta_reg_count; i++)
1499                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1500
1501         /* Setup link and flow control */
1502         ret_val = mac->ops.setup_link(hw);
1503
1504         /* Set the default MTU size */
1505         hw->dev_spec._82575.mtu = 1500;
1506
1507         /*
1508          * Clear all of the statistics registers (clear on read).  It is
1509          * important that we do this after we have tried to establish link
1510          * because the symbol error count will increment wildly if there
1511          * is no link.
1512          */
1513         e1000_clear_hw_cntrs_82575(hw);
1514
1515         return ret_val;
1516 }
1517
1518 /**
1519  *  e1000_setup_copper_link_82575 - Configure copper link settings
1520  *  @hw: pointer to the HW structure
1521  *
1522  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1523  *  for link, once link is established calls to configure collision distance
1524  *  and flow control are called.
1525  **/
1526 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1527 {
1528         u32 ctrl;
1529         s32 ret_val;
1530         u32 phpm_reg;
1531
1532         DEBUGFUNC("e1000_setup_copper_link_82575");
1533
1534         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1535         ctrl |= E1000_CTRL_SLU;
1536         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1537         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1538
1539         /* Clear Go Link Disconnect bit on supported devices */
1540         switch (hw->mac.type) {
1541         case e1000_82580:
1542         case e1000_i350:
1543         case e1000_i210:
1544         case e1000_i211:
1545                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1546                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1547                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1548                 break;
1549         default:
1550                 break;
1551         }
1552
1553         ret_val = e1000_setup_serdes_link_82575(hw);
1554         if (ret_val)
1555                 goto out;
1556
1557         if (e1000_sgmii_active_82575(hw)) {
1558                 /* allow time for SFP cage time to power up phy */
1559                 msec_delay(300);
1560
1561                 ret_val = hw->phy.ops.reset(hw);
1562                 if (ret_val) {
1563                         DEBUGOUT("Error resetting the PHY.\n");
1564                         goto out;
1565                 }
1566         }
1567         switch (hw->phy.type) {
1568         case e1000_phy_i210:
1569         case e1000_phy_m88:
1570                 switch (hw->phy.id) {
1571                 case I347AT4_E_PHY_ID:
1572                 case M88E1112_E_PHY_ID:
1573                 case M88E1340M_E_PHY_ID:
1574                 case M88E1543_E_PHY_ID:
1575                 case M88E1512_E_PHY_ID:
1576                 case I210_I_PHY_ID:
1577                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1578                         break;
1579                 default:
1580                         ret_val = e1000_copper_link_setup_m88(hw);
1581                         break;
1582                 }
1583                 break;
1584         case e1000_phy_igp_3:
1585                 ret_val = e1000_copper_link_setup_igp(hw);
1586                 break;
1587         case e1000_phy_82580:
1588                 ret_val = e1000_copper_link_setup_82577(hw);
1589                 break;
1590         default:
1591                 ret_val = -E1000_ERR_PHY;
1592                 break;
1593         }
1594
1595         if (ret_val)
1596                 goto out;
1597
1598         ret_val = e1000_setup_copper_link_generic(hw);
1599 out:
1600         return ret_val;
1601 }
1602
1603 /**
1604  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1605  *  @hw: pointer to the HW structure
1606  *
1607  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1608  *  used on copper connections where the serialized gigabit media independent
1609  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1610  *  for auto-negotiation or forces speed/duplex.
1611  **/
1612 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1613 {
1614         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1615         bool pcs_autoneg;
1616         s32 ret_val = E1000_SUCCESS;
1617         u16 data;
1618
1619         DEBUGFUNC("e1000_setup_serdes_link_82575");
1620
1621         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1622             !e1000_sgmii_active_82575(hw))
1623                 return ret_val;
1624
1625         /*
1626          * On the 82575, SerDes loopback mode persists until it is
1627          * explicitly turned off or a power cycle is performed.  A read to
1628          * the register does not indicate its status.  Therefore, we ensure
1629          * loopback mode is disabled during initialization.
1630          */
1631         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1632
1633         /* power on the sfp cage if present */
1634         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1635         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1636         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1637
1638         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1639         ctrl_reg |= E1000_CTRL_SLU;
1640
1641         /* set both sw defined pins on 82575/82576*/
1642         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1643                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1644
1645         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1646
1647         /* default pcs_autoneg to the same setting as mac autoneg */
1648         pcs_autoneg = hw->mac.autoneg;
1649
1650         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1651         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1652                 /* sgmii mode lets the phy handle forcing speed/duplex */
1653                 pcs_autoneg = TRUE;
1654                 /* autoneg time out should be disabled for SGMII mode */
1655                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1656                 break;
1657         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1658                 /* disable PCS autoneg and support parallel detect only */
1659                 pcs_autoneg = FALSE;
1660                 /* fall through to default case */
1661         default:
1662                 if (hw->mac.type == e1000_82575 ||
1663                     hw->mac.type == e1000_82576) {
1664                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1665                         if (ret_val) {
1666                                 DEBUGOUT("NVM Read Error\n");
1667                                 return ret_val;
1668                         }
1669
1670                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1671                                 pcs_autoneg = FALSE;
1672                 }
1673
1674                 /*
1675                  * non-SGMII modes only supports a speed of 1000/Full for the
1676                  * link so it is best to just force the MAC and let the pcs
1677                  * link either autoneg or be forced to 1000/Full
1678                  */
1679                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1680                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1681
1682                 /* set speed of 1000/Full if speed/duplex is forced */
1683                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1684                 break;
1685         }
1686
1687         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1688
1689         /*
1690          * New SerDes mode allows for forcing speed or autonegotiating speed
1691          * at 1gb. Autoneg should be default set by most drivers. This is the
1692          * mode that will be compatible with older link partners and switches.
1693          * However, both are supported by the hardware and some drivers/tools.
1694          */
1695         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1696                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1697
1698         if (pcs_autoneg) {
1699                 /* Set PCS register for autoneg */
1700                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1701                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1702
1703                 /* Disable force flow control for autoneg */
1704                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1705
1706                 /* Configure flow control advertisement for autoneg */
1707                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1708                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1709
1710                 switch (hw->fc.requested_mode) {
1711                 case e1000_fc_full:
1712                 case e1000_fc_rx_pause:
1713                         anadv_reg |= E1000_TXCW_ASM_DIR;
1714                         anadv_reg |= E1000_TXCW_PAUSE;
1715                         break;
1716                 case e1000_fc_tx_pause:
1717                         anadv_reg |= E1000_TXCW_ASM_DIR;
1718                         break;
1719                 default:
1720                         break;
1721                 }
1722
1723                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1724
1725                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1726         } else {
1727                 /* Set PCS register for forced link */
1728                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1729
1730                 /* Force flow control for forced link */
1731                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1732
1733                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1734         }
1735
1736         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1737
1738         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1739                 e1000_force_mac_fc_generic(hw);
1740
1741         return ret_val;
1742 }
1743
1744 /**
1745  *  e1000_get_media_type_82575 - derives current media type.
1746  *  @hw: pointer to the HW structure
1747  *
1748  *  The media type is chosen reflecting few settings.
1749  *  The following are taken into account:
1750  *  - link mode set in the current port Init Control Word #3
1751  *  - current link mode settings in CSR register
1752  *  - MDIO vs. I2C PHY control interface chosen
1753  *  - SFP module media type
1754  **/
1755 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1756 {
1757         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1758         s32 ret_val = E1000_SUCCESS;
1759         u32 ctrl_ext = 0;
1760         u32 link_mode = 0;
1761
1762         /* Set internal phy as default */
1763         dev_spec->sgmii_active = FALSE;
1764         dev_spec->module_plugged = FALSE;
1765
1766         /* Get CSR setting */
1767         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1768
1769         /* extract link mode setting */
1770         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1771
1772         switch (link_mode) {
1773         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1774                 hw->phy.media_type = e1000_media_type_internal_serdes;
1775                 break;
1776         case E1000_CTRL_EXT_LINK_MODE_GMII:
1777                 hw->phy.media_type = e1000_media_type_copper;
1778                 break;
1779         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1780                 /* Get phy control interface type set (MDIO vs. I2C)*/
1781                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1782                         hw->phy.media_type = e1000_media_type_copper;
1783                         dev_spec->sgmii_active = TRUE;
1784                         break;
1785                 }
1786                 /* fall through for I2C based SGMII */
1787         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1788                 /* read media type from SFP EEPROM */
1789                 ret_val = e1000_set_sfp_media_type_82575(hw);
1790                 if ((ret_val != E1000_SUCCESS) ||
1791                     (hw->phy.media_type == e1000_media_type_unknown)) {
1792                         /*
1793                          * If media type was not identified then return media
1794                          * type defined by the CTRL_EXT settings.
1795                          */
1796                         hw->phy.media_type = e1000_media_type_internal_serdes;
1797
1798                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1799                                 hw->phy.media_type = e1000_media_type_copper;
1800                                 dev_spec->sgmii_active = TRUE;
1801                         }
1802
1803                         break;
1804                 }
1805
1806                 /* do not change link mode for 100BaseFX */
1807                 if (dev_spec->eth_flags.e100_base_fx)
1808                         break;
1809
1810                 /* change current link mode setting */
1811                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1812
1813                 if (hw->phy.media_type == e1000_media_type_copper)
1814                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1815                 else
1816                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1817
1818                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1819
1820                 break;
1821         }
1822
1823         return ret_val;
1824 }
1825
1826 /**
1827  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1828  *  @hw: pointer to the HW structure
1829  *
1830  *  The media type is chosen based on SFP module.
1831  *  compatibility flags retrieved from SFP ID EEPROM.
1832  **/
1833 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1834 {
1835         s32 ret_val = E1000_ERR_CONFIG;
1836         u32 ctrl_ext = 0;
1837         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1838         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1839         u8 tranceiver_type = 0;
1840         s32 timeout = 3;
1841
1842         /* Turn I2C interface ON and power on sfp cage */
1843         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1844         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1845         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1846
1847         E1000_WRITE_FLUSH(hw);
1848
1849         /* Read SFP module data */
1850         while (timeout) {
1851                 ret_val = e1000_read_sfp_data_byte(hw,
1852                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1853                         &tranceiver_type);
1854                 if (ret_val == E1000_SUCCESS)
1855                         break;
1856                 msec_delay(100);
1857                 timeout--;
1858         }
1859         if (ret_val != E1000_SUCCESS)
1860                 goto out;
1861
1862         ret_val = e1000_read_sfp_data_byte(hw,
1863                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1864                         (u8 *)eth_flags);
1865         if (ret_val != E1000_SUCCESS)
1866                 goto out;
1867
1868         /* Check if there is some SFP module plugged and powered */
1869         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1870             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1871                 dev_spec->module_plugged = TRUE;
1872                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1873                         hw->phy.media_type = e1000_media_type_internal_serdes;
1874                 } else if (eth_flags->e100_base_fx) {
1875                         dev_spec->sgmii_active = TRUE;
1876                         hw->phy.media_type = e1000_media_type_internal_serdes;
1877                 } else if (eth_flags->e1000_base_t) {
1878                         dev_spec->sgmii_active = TRUE;
1879                         hw->phy.media_type = e1000_media_type_copper;
1880                 } else {
1881                         hw->phy.media_type = e1000_media_type_unknown;
1882                         DEBUGOUT("PHY module has not been recognized\n");
1883                         goto out;
1884                 }
1885         } else {
1886                 hw->phy.media_type = e1000_media_type_unknown;
1887         }
1888         ret_val = E1000_SUCCESS;
1889 out:
1890         /* Restore I2C interface setting */
1891         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1892         return ret_val;
1893 }
1894
1895 /**
1896  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1897  *  @hw: pointer to the HW structure
1898  *  @data: pointer to the NVM (EEPROM)
1899  *
1900  *  Read the EEPROM for the current default LED configuration.  If the
1901  *  LED configuration is not valid, set to a valid LED configuration.
1902  **/
1903 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1904 {
1905         s32 ret_val;
1906
1907         DEBUGFUNC("e1000_valid_led_default_82575");
1908
1909         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1910         if (ret_val) {
1911                 DEBUGOUT("NVM Read Error\n");
1912                 goto out;
1913         }
1914
1915         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1916                 switch (hw->phy.media_type) {
1917                 case e1000_media_type_internal_serdes:
1918                         *data = ID_LED_DEFAULT_82575_SERDES;
1919                         break;
1920                 case e1000_media_type_copper:
1921                 default:
1922                         *data = ID_LED_DEFAULT;
1923                         break;
1924                 }
1925         }
1926 out:
1927         return ret_val;
1928 }
1929
1930 /**
1931  *  e1000_sgmii_active_82575 - Return sgmii state
1932  *  @hw: pointer to the HW structure
1933  *
1934  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1935  *  which can be enabled for use in the embedded applications.  Simply
1936  *  return the current state of the sgmii interface.
1937  **/
1938 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1939 {
1940         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1941         return dev_spec->sgmii_active;
1942 }
1943
1944 /**
1945  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1946  *  @hw: pointer to the HW structure
1947  *
1948  *  Inits recommended HW defaults after a reset when there is no EEPROM
1949  *  detected. This is only for the 82575.
1950  **/
1951 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1952 {
1953         DEBUGFUNC("e1000_reset_init_script_82575");
1954
1955         if (hw->mac.type == e1000_82575) {
1956                 DEBUGOUT("Running reset init script for 82575\n");
1957                 /* SerDes configuration via SERDESCTRL */
1958                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1959                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1960                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1961                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1962
1963                 /* CCM configuration via CCMCTL register */
1964                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1965                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1966
1967                 /* PCIe lanes configuration */
1968                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1969                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1970                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1971                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1972
1973                 /* PCIe PLL Configuration */
1974                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1975                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1976                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1977         }
1978
1979         return E1000_SUCCESS;
1980 }
1981
1982 /**
1983  *  e1000_read_mac_addr_82575 - Read device MAC address
1984  *  @hw: pointer to the HW structure
1985  **/
1986 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1987 {
1988         s32 ret_val = E1000_SUCCESS;
1989
1990         DEBUGFUNC("e1000_read_mac_addr_82575");
1991
1992         /*
1993          * If there's an alternate MAC address place it in RAR0
1994          * so that it will override the Si installed default perm
1995          * address.
1996          */
1997         ret_val = e1000_check_alt_mac_addr_generic(hw);
1998         if (ret_val)
1999                 goto out;
2000
2001         ret_val = e1000_read_mac_addr_generic(hw);
2002
2003 out:
2004         return ret_val;
2005 }
2006
2007 /**
2008  *  e1000_config_collision_dist_82575 - Configure collision distance
2009  *  @hw: pointer to the HW structure
2010  *
2011  *  Configures the collision distance to the default value and is used
2012  *  during link setup.
2013  **/
2014 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2015 {
2016         u32 tctl_ext;
2017
2018         DEBUGFUNC("e1000_config_collision_dist_82575");
2019
2020         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2021
2022         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2023         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2024
2025         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2026         E1000_WRITE_FLUSH(hw);
2027 }
2028
2029 /**
2030  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2031  * @hw: pointer to the HW structure
2032  *
2033  * In the case of a PHY power down to save power, or to turn off link during a
2034  * driver unload, or wake on lan is not enabled, remove the link.
2035  **/
2036 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2037 {
2038         struct e1000_phy_info *phy = &hw->phy;
2039
2040         if (!(phy->ops.check_reset_block))
2041                 return;
2042
2043         /* If the management interface is not enabled, then power down */
2044         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2045                 e1000_power_down_phy_copper(hw);
2046
2047         return;
2048 }
2049
2050 /**
2051  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2052  *  @hw: pointer to the HW structure
2053  *
2054  *  Clears the hardware counters by reading the counter registers.
2055  **/
2056 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2057 {
2058         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2059
2060         e1000_clear_hw_cntrs_base_generic(hw);
2061
2062         E1000_READ_REG(hw, E1000_PRC64);
2063         E1000_READ_REG(hw, E1000_PRC127);
2064         E1000_READ_REG(hw, E1000_PRC255);
2065         E1000_READ_REG(hw, E1000_PRC511);
2066         E1000_READ_REG(hw, E1000_PRC1023);
2067         E1000_READ_REG(hw, E1000_PRC1522);
2068         E1000_READ_REG(hw, E1000_PTC64);
2069         E1000_READ_REG(hw, E1000_PTC127);
2070         E1000_READ_REG(hw, E1000_PTC255);
2071         E1000_READ_REG(hw, E1000_PTC511);
2072         E1000_READ_REG(hw, E1000_PTC1023);
2073         E1000_READ_REG(hw, E1000_PTC1522);
2074
2075         E1000_READ_REG(hw, E1000_ALGNERRC);
2076         E1000_READ_REG(hw, E1000_RXERRC);
2077         E1000_READ_REG(hw, E1000_TNCRS);
2078         E1000_READ_REG(hw, E1000_CEXTERR);
2079         E1000_READ_REG(hw, E1000_TSCTC);
2080         E1000_READ_REG(hw, E1000_TSCTFC);
2081
2082         E1000_READ_REG(hw, E1000_MGTPRC);
2083         E1000_READ_REG(hw, E1000_MGTPDC);
2084         E1000_READ_REG(hw, E1000_MGTPTC);
2085
2086         E1000_READ_REG(hw, E1000_IAC);
2087         E1000_READ_REG(hw, E1000_ICRXOC);
2088
2089         E1000_READ_REG(hw, E1000_ICRXPTC);
2090         E1000_READ_REG(hw, E1000_ICRXATC);
2091         E1000_READ_REG(hw, E1000_ICTXPTC);
2092         E1000_READ_REG(hw, E1000_ICTXATC);
2093         E1000_READ_REG(hw, E1000_ICTXQEC);
2094         E1000_READ_REG(hw, E1000_ICTXQMTC);
2095         E1000_READ_REG(hw, E1000_ICRXDMTC);
2096
2097         E1000_READ_REG(hw, E1000_CBTMPC);
2098         E1000_READ_REG(hw, E1000_HTDPMC);
2099         E1000_READ_REG(hw, E1000_CBRMPC);
2100         E1000_READ_REG(hw, E1000_RPTHC);
2101         E1000_READ_REG(hw, E1000_HGPTC);
2102         E1000_READ_REG(hw, E1000_HTCBDPC);
2103         E1000_READ_REG(hw, E1000_HGORCL);
2104         E1000_READ_REG(hw, E1000_HGORCH);
2105         E1000_READ_REG(hw, E1000_HGOTCL);
2106         E1000_READ_REG(hw, E1000_HGOTCH);
2107         E1000_READ_REG(hw, E1000_LENERRS);
2108
2109         /* This register should not be read in copper configurations */
2110         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2111             e1000_sgmii_active_82575(hw))
2112                 E1000_READ_REG(hw, E1000_SCVPC);
2113 }
2114
2115 /**
2116  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2117  *  @hw: pointer to the HW structure
2118  *
2119  *  After rx enable if managability is enabled then there is likely some
2120  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2121  *  function clears the fifos and flushes any packets that came in as rx was
2122  *  being enabled.
2123  **/
2124 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2125 {
2126         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2127         int i, ms_wait;
2128
2129         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2130         if (hw->mac.type != e1000_82575 ||
2131             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2132                 return;
2133
2134         /* Disable all Rx queues */
2135         for (i = 0; i < 4; i++) {
2136                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2137                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2138                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2139         }
2140         /* Poll all queues to verify they have shut down */
2141         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2142                 msec_delay(1);
2143                 rx_enabled = 0;
2144                 for (i = 0; i < 4; i++)
2145                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2146                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2147                         break;
2148         }
2149
2150         if (ms_wait == 10)
2151                 DEBUGOUT("Queue disable timed out after 10ms\n");
2152
2153         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2154          * incoming packets are rejected.  Set enable and wait 2ms so that
2155          * any packet that was coming in as RCTL.EN was set is flushed
2156          */
2157         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2158         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2159
2160         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2161         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2162
2163         rctl = E1000_READ_REG(hw, E1000_RCTL);
2164         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2165         temp_rctl |= E1000_RCTL_LPE;
2166
2167         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2168         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2169         E1000_WRITE_FLUSH(hw);
2170         msec_delay(2);
2171
2172         /* Enable Rx queues that were previously enabled and restore our
2173          * previous state
2174          */
2175         for (i = 0; i < 4; i++)
2176                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2177         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2178         E1000_WRITE_FLUSH(hw);
2179
2180         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2181         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2182
2183         /* Flush receive errors generated by workaround */
2184         E1000_READ_REG(hw, E1000_ROC);
2185         E1000_READ_REG(hw, E1000_RNBC);
2186         E1000_READ_REG(hw, E1000_MPC);
2187 }
2188
2189 /**
2190  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2191  *  @hw: pointer to the HW structure
2192  *
2193  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2194  *  however the hardware default for these parts is 500us to 1ms which is less
2195  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2196  *  increase the value to either 10ms to 200ms for capability version 1 config,
2197  *  or 16ms to 55ms for version 2.
2198  **/
2199 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2200 {
2201         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2202         s32 ret_val = E1000_SUCCESS;
2203         u16 pcie_devctl2;
2204
2205         /* only take action if timeout value is defaulted to 0 */
2206         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2207                 goto out;
2208
2209         /*
2210          * if capababilities version is type 1 we can write the
2211          * timeout of 10ms to 200ms through the GCR register
2212          */
2213         if (!(gcr & E1000_GCR_CAP_VER2)) {
2214                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2215                 goto out;
2216         }
2217
2218         /*
2219          * for version 2 capabilities we need to write the config space
2220          * directly in order to set the completion timeout value for
2221          * 16ms to 55ms
2222          */
2223         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2224                                           &pcie_devctl2);
2225         if (ret_val)
2226                 goto out;
2227
2228         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2229
2230         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2231                                            &pcie_devctl2);
2232 out:
2233         /* disable completion timeout resend */
2234         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2235
2236         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2237         return ret_val;
2238 }
2239
2240 /**
2241  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2242  *  @hw: pointer to the hardware struct
2243  *  @enable: state to enter, either enabled or disabled
2244  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2245  *
2246  *  enables/disables L2 switch anti-spoofing functionality.
2247  **/
2248 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2249 {
2250         u32 reg_val, reg_offset;
2251
2252         switch (hw->mac.type) {
2253         case e1000_82576:
2254                 reg_offset = E1000_DTXSWC;
2255                 break;
2256         case e1000_i350:
2257         case e1000_i354:
2258                 reg_offset = E1000_TXSWC;
2259                 break;
2260         default:
2261                 return;
2262         }
2263
2264         reg_val = E1000_READ_REG(hw, reg_offset);
2265         if (enable) {
2266                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2267                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2268                 /* The PF can spoof - it has to in order to
2269                  * support emulation mode NICs
2270                  */
2271                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2272         } else {
2273                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2274                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2275         }
2276         E1000_WRITE_REG(hw, reg_offset, reg_val);
2277 }
2278
2279 /**
2280  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2281  *  @hw: pointer to the hardware struct
2282  *  @enable: state to enter, either enabled or disabled
2283  *
2284  *  enables/disables L2 switch loopback functionality.
2285  **/
2286 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2287 {
2288         u32 dtxswc;
2289
2290         switch (hw->mac.type) {
2291         case e1000_82576:
2292                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2293                 if (enable)
2294                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2295                 else
2296                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2297                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2298                 break;
2299         case e1000_i350:
2300         case e1000_i354:
2301                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2302                 if (enable)
2303                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2304                 else
2305                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2306                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2307                 break;
2308         default:
2309                 /* Currently no other hardware supports loopback */
2310                 break;
2311         }
2312
2313
2314 }
2315
2316 /**
2317  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2318  *  @hw: pointer to the hardware struct
2319  *  @enable: state to enter, either enabled or disabled
2320  *
2321  *  enables/disables replication of packets across multiple pools.
2322  **/
2323 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2324 {
2325         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2326
2327         if (enable)
2328                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2329         else
2330                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2331
2332         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2333 }
2334
2335 /**
2336  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2337  *  @hw: pointer to the HW structure
2338  *  @offset: register offset to be read
2339  *  @data: pointer to the read data
2340  *
2341  *  Reads the MDI control register in the PHY at offset and stores the
2342  *  information read to data.
2343  **/
2344 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2345 {
2346         s32 ret_val;
2347
2348         DEBUGFUNC("e1000_read_phy_reg_82580");
2349
2350         ret_val = hw->phy.ops.acquire(hw);
2351         if (ret_val)
2352                 goto out;
2353
2354         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2355
2356         hw->phy.ops.release(hw);
2357
2358 out:
2359         return ret_val;
2360 }
2361
2362 /**
2363  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2364  *  @hw: pointer to the HW structure
2365  *  @offset: register offset to write to
2366  *  @data: data to write to register at offset
2367  *
2368  *  Writes data to MDI control register in the PHY at offset.
2369  **/
2370 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2371 {
2372         s32 ret_val;
2373
2374         DEBUGFUNC("e1000_write_phy_reg_82580");
2375
2376         ret_val = hw->phy.ops.acquire(hw);
2377         if (ret_val)
2378                 goto out;
2379
2380         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2381
2382         hw->phy.ops.release(hw);
2383
2384 out:
2385         return ret_val;
2386 }
2387
2388 /**
2389  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2390  *  @hw: pointer to the HW structure
2391  *
2392  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2393  *  the values found in the EEPROM.  This addresses an issue in which these
2394  *  bits are not restored from EEPROM after reset.
2395  **/
2396 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2397 {
2398         s32 ret_val = E1000_SUCCESS;
2399         u32 mdicnfg;
2400         u16 nvm_data = 0;
2401
2402         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2403
2404         if (hw->mac.type != e1000_82580)
2405                 goto out;
2406         if (!e1000_sgmii_active_82575(hw))
2407                 goto out;
2408
2409         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2410                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2411                                    &nvm_data);
2412         if (ret_val) {
2413                 DEBUGOUT("NVM Read Error\n");
2414                 goto out;
2415         }
2416
2417         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2418         if (nvm_data & NVM_WORD24_EXT_MDIO)
2419                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2420         if (nvm_data & NVM_WORD24_COM_MDIO)
2421                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2422         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2423 out:
2424         return ret_val;
2425 }
2426
2427 /**
2428  *  e1000_reset_hw_82580 - Reset hardware
2429  *  @hw: pointer to the HW structure
2430  *
2431  *  This resets function or entire device (all ports, etc.)
2432  *  to a known state.
2433  **/
2434 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2435 {
2436         s32 ret_val = E1000_SUCCESS;
2437         /* BH SW mailbox bit in SW_FW_SYNC */
2438         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2439         u32 ctrl;
2440         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2441
2442         DEBUGFUNC("e1000_reset_hw_82580");
2443
2444         hw->dev_spec._82575.global_device_reset = FALSE;
2445
2446         /* 82580 does not reliably do global_device_reset due to hw errata */
2447         if (hw->mac.type == e1000_82580)
2448                 global_device_reset = FALSE;
2449
2450         /* Get current control state. */
2451         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2452
2453         /*
2454          * Prevent the PCI-E bus from sticking if there is no TLP connection
2455          * on the last TLP read/write transaction when MAC is reset.
2456          */
2457         ret_val = e1000_disable_pcie_master_generic(hw);
2458         if (ret_val)
2459                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2460
2461         DEBUGOUT("Masking off all interrupts\n");
2462         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2463         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2464         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2465         E1000_WRITE_FLUSH(hw);
2466
2467         msec_delay(10);
2468
2469         /* Determine whether or not a global dev reset is requested */
2470         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2471             swmbsw_mask))
2472                         global_device_reset = FALSE;
2473
2474         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2475             E1000_STAT_DEV_RST_SET))
2476                 ctrl |= E1000_CTRL_DEV_RST;
2477         else
2478                 ctrl |= E1000_CTRL_RST;
2479
2480         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2481         E1000_WRITE_FLUSH(hw);
2482
2483         /* Add delay to insure DEV_RST has time to complete */
2484         if (global_device_reset)
2485                 msec_delay(5);
2486
2487         ret_val = e1000_get_auto_rd_done_generic(hw);
2488         if (ret_val) {
2489                 /*
2490                  * When auto config read does not complete, do not
2491                  * return with an error. This can happen in situations
2492                  * where there is no eeprom and prevents getting link.
2493                  */
2494                 DEBUGOUT("Auto Read Done did not complete\n");
2495         }
2496
2497         /* clear global device reset status bit */
2498         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2499
2500         /* Clear any pending interrupt events. */
2501         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2502         E1000_READ_REG(hw, E1000_ICR);
2503
2504         ret_val = e1000_reset_mdicnfg_82580(hw);
2505         if (ret_val)
2506                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2507
2508         /* Install any alternate MAC address into RAR0 */
2509         ret_val = e1000_check_alt_mac_addr_generic(hw);
2510
2511         /* Release semaphore */
2512         if (global_device_reset)
2513                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2514
2515         return ret_val;
2516 }
2517
2518 /**
2519  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2520  *  @data: data received by reading RXPBS register
2521  *
2522  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2523  *  This function converts the retrieved value into the correct table value
2524  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2525  *  0x0 36  72 144   1   2   4   8  16
2526  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2527  */
2528 u16 e1000_rxpbs_adjust_82580(u32 data)
2529 {
2530         u16 ret_val = 0;
2531
2532         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2533                 ret_val = e1000_82580_rxpbs_table[data];
2534
2535         return ret_val;
2536 }
2537
2538 /**
2539  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2540  *  checksum
2541  *  @hw: pointer to the HW structure
2542  *  @offset: offset in words of the checksum protected region
2543  *
2544  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2545  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2546  **/
2547 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2548 {
2549         s32 ret_val = E1000_SUCCESS;
2550         u16 checksum = 0;
2551         u16 i, nvm_data;
2552
2553         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2554
2555         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2556                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2557                 if (ret_val) {
2558                         DEBUGOUT("NVM Read Error\n");
2559                         goto out;
2560                 }
2561                 checksum += nvm_data;
2562         }
2563
2564         if (checksum != (u16) NVM_SUM) {
2565                 DEBUGOUT("NVM Checksum Invalid\n");
2566                 ret_val = -E1000_ERR_NVM;
2567                 goto out;
2568         }
2569
2570 out:
2571         return ret_val;
2572 }
2573
2574 /**
2575  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2576  *  checksum
2577  *  @hw: pointer to the HW structure
2578  *  @offset: offset in words of the checksum protected region
2579  *
2580  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2581  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2582  *  value to the EEPROM.
2583  **/
2584 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2585 {
2586         s32 ret_val;
2587         u16 checksum = 0;
2588         u16 i, nvm_data;
2589
2590         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2591
2592         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2593                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2594                 if (ret_val) {
2595                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2596                         goto out;
2597                 }
2598                 checksum += nvm_data;
2599         }
2600         checksum = (u16) NVM_SUM - checksum;
2601         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2602                                     &checksum);
2603         if (ret_val)
2604                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2605
2606 out:
2607         return ret_val;
2608 }
2609
2610 /**
2611  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2612  *  @hw: pointer to the HW structure
2613  *
2614  *  Calculates the EEPROM section checksum by reading/adding each word of
2615  *  the EEPROM and then verifies that the sum of the EEPROM is
2616  *  equal to 0xBABA.
2617  **/
2618 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2619 {
2620         s32 ret_val = E1000_SUCCESS;
2621         u16 eeprom_regions_count = 1;
2622         u16 j, nvm_data;
2623         u16 nvm_offset;
2624
2625         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2626
2627         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2628         if (ret_val) {
2629                 DEBUGOUT("NVM Read Error\n");
2630                 goto out;
2631         }
2632
2633         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2634                 /* if chekcsums compatibility bit is set validate checksums
2635                  * for all 4 ports. */
2636                 eeprom_regions_count = 4;
2637         }
2638
2639         for (j = 0; j < eeprom_regions_count; j++) {
2640                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2641                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2642                                                                   nvm_offset);
2643                 if (ret_val != E1000_SUCCESS)
2644                         goto out;
2645         }
2646
2647 out:
2648         return ret_val;
2649 }
2650
2651 /**
2652  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2653  *  @hw: pointer to the HW structure
2654  *
2655  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2656  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2657  *  checksum and writes the value to the EEPROM.
2658  **/
2659 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2660 {
2661         s32 ret_val;
2662         u16 j, nvm_data;
2663         u16 nvm_offset;
2664
2665         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2666
2667         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2668         if (ret_val) {
2669                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2670                 goto out;
2671         }
2672
2673         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2674                 /* set compatibility bit to validate checksums appropriately */
2675                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2676                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2677                                             &nvm_data);
2678                 if (ret_val) {
2679                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2680                         goto out;
2681                 }
2682         }
2683
2684         for (j = 0; j < 4; j++) {
2685                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2686                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2687                 if (ret_val)
2688                         goto out;
2689         }
2690
2691 out:
2692         return ret_val;
2693 }
2694
2695 /**
2696  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2697  *  @hw: pointer to the HW structure
2698  *
2699  *  Calculates the EEPROM section checksum by reading/adding each word of
2700  *  the EEPROM and then verifies that the sum of the EEPROM is
2701  *  equal to 0xBABA.
2702  **/
2703 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2704 {
2705         s32 ret_val = E1000_SUCCESS;
2706         u16 j;
2707         u16 nvm_offset;
2708
2709         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2710
2711         for (j = 0; j < 4; j++) {
2712                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2713                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2714                                                                   nvm_offset);
2715                 if (ret_val != E1000_SUCCESS)
2716                         goto out;
2717         }
2718
2719 out:
2720         return ret_val;
2721 }
2722
2723 /**
2724  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2725  *  @hw: pointer to the HW structure
2726  *
2727  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2728  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2729  *  checksum and writes the value to the EEPROM.
2730  **/
2731 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2732 {
2733         s32 ret_val = E1000_SUCCESS;
2734         u16 j;
2735         u16 nvm_offset;
2736
2737         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2738
2739         for (j = 0; j < 4; j++) {
2740                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2741                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2742                 if (ret_val != E1000_SUCCESS)
2743                         goto out;
2744         }
2745
2746 out:
2747         return ret_val;
2748 }
2749
2750 /**
2751  *  __e1000_access_emi_reg - Read/write EMI register
2752  *  @hw: pointer to the HW structure
2753  *  @addr: EMI address to program
2754  *  @data: pointer to value to read/write from/to the EMI address
2755  *  @read: boolean flag to indicate read or write
2756  **/
2757 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2758                                   u16 *data, bool read)
2759 {
2760         s32 ret_val = E1000_SUCCESS;
2761
2762         DEBUGFUNC("__e1000_access_emi_reg");
2763
2764         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2765         if (ret_val)
2766                 return ret_val;
2767
2768         if (read)
2769                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2770         else
2771                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2772
2773         return ret_val;
2774 }
2775
2776 /**
2777  *  e1000_read_emi_reg - Read Extended Management Interface register
2778  *  @hw: pointer to the HW structure
2779  *  @addr: EMI address to program
2780  *  @data: value to be read from the EMI address
2781  **/
2782 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2783 {
2784         DEBUGFUNC("e1000_read_emi_reg");
2785
2786         return __e1000_access_emi_reg(hw, addr, data, TRUE);
2787 }
2788
2789 /**
2790  *  e1000_set_eee_i350 - Enable/disable EEE support
2791  *  @hw: pointer to the HW structure
2792  *
2793  *  Enable/disable EEE based on setting in dev_spec structure.
2794  *
2795  **/
2796 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2797 {
2798         s32 ret_val = E1000_SUCCESS;
2799         u32 ipcnfg, eeer;
2800
2801         DEBUGFUNC("e1000_set_eee_i350");
2802
2803         if ((hw->mac.type < e1000_i350) ||
2804             (hw->phy.media_type != e1000_media_type_copper))
2805                 goto out;
2806         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2807         eeer = E1000_READ_REG(hw, E1000_EEER);
2808
2809         /* enable or disable per user setting */
2810         if (!(hw->dev_spec._82575.eee_disable)) {
2811                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2812
2813                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2814                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2815                          E1000_EEER_LPI_FC);
2816
2817                 /* This bit should not be set in normal operation. */
2818                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2819                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2820         } else {
2821                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2822                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2823                           E1000_EEER_LPI_FC);
2824         }
2825         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2826         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2827         E1000_READ_REG(hw, E1000_IPCNFG);
2828         E1000_READ_REG(hw, E1000_EEER);
2829 out:
2830
2831         return ret_val;
2832 }
2833
2834 /**
2835  *  e1000_set_eee_i354 - Enable/disable EEE support
2836  *  @hw: pointer to the HW structure
2837  *
2838  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2839  *
2840  **/
2841 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2842 {
2843         struct e1000_phy_info *phy = &hw->phy;
2844         s32 ret_val = E1000_SUCCESS;
2845         u16 phy_data;
2846
2847         DEBUGFUNC("e1000_set_eee_i354");
2848
2849         if ((hw->phy.media_type != e1000_media_type_copper) ||
2850             ((phy->id != M88E1543_E_PHY_ID) &&
2851             (phy->id != M88E1512_E_PHY_ID)))
2852                 goto out;
2853
2854         if (!hw->dev_spec._82575.eee_disable) {
2855                 /* Switch to PHY page 18. */
2856                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2857                 if (ret_val)
2858                         goto out;
2859
2860                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2861                                             &phy_data);
2862                 if (ret_val)
2863                         goto out;
2864
2865                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2866                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2867                                              phy_data);
2868                 if (ret_val)
2869                         goto out;
2870
2871                 /* Return the PHY to page 0. */
2872                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2873                 if (ret_val)
2874                         goto out;
2875
2876                 /* Turn on EEE advertisement. */
2877                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2878                                                E1000_EEE_ADV_DEV_I354,
2879                                                &phy_data);
2880                 if (ret_val)
2881                         goto out;
2882
2883                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2884                             E1000_EEE_ADV_1000_SUPPORTED;
2885                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2886                                                 E1000_EEE_ADV_DEV_I354,
2887                                                 phy_data);
2888         } else {
2889                 /* Turn off EEE advertisement. */
2890                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2891                                                E1000_EEE_ADV_DEV_I354,
2892                                                &phy_data);
2893                 if (ret_val)
2894                         goto out;
2895
2896                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2897                               E1000_EEE_ADV_1000_SUPPORTED);
2898                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2899                                                 E1000_EEE_ADV_DEV_I354,
2900                                                 phy_data);
2901         }
2902
2903 out:
2904         return ret_val;
2905 }
2906
2907 /**
2908  *  e1000_get_eee_status_i354 - Get EEE status
2909  *  @hw: pointer to the HW structure
2910  *  @status: EEE status
2911  *
2912  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2913  *  been received.
2914  **/
2915 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2916 {
2917         struct e1000_phy_info *phy = &hw->phy;
2918         s32 ret_val = E1000_SUCCESS;
2919         u16 phy_data;
2920
2921         DEBUGFUNC("e1000_get_eee_status_i354");
2922
2923         /* Check if EEE is supported on this device. */
2924         if ((hw->phy.media_type != e1000_media_type_copper) ||
2925             ((phy->id != M88E1543_E_PHY_ID) &&
2926             (phy->id != M88E1512_E_PHY_ID)))
2927                 goto out;
2928
2929         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2930                                        E1000_PCS_STATUS_DEV_I354,
2931                                        &phy_data);
2932         if (ret_val)
2933                 goto out;
2934
2935         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2936                               E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE;
2937
2938 out:
2939         return ret_val;
2940 }
2941
2942 /* Due to a hw errata, if the host tries to  configure the VFTA register
2943  * while performing queries from the BMC or DMA, then the VFTA in some
2944  * cases won't be written.
2945  */
2946
2947 /**
2948  *  e1000_clear_vfta_i350 - Clear VLAN filter table
2949  *  @hw: pointer to the HW structure
2950  *
2951  *  Clears the register array which contains the VLAN filter table by
2952  *  setting all the values to 0.
2953  **/
2954 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2955 {
2956         u32 offset;
2957         int i;
2958
2959         DEBUGFUNC("e1000_clear_vfta_350");
2960
2961         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2962                 for (i = 0; i < 10; i++)
2963                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2964
2965                 E1000_WRITE_FLUSH(hw);
2966         }
2967 }
2968
2969 /**
2970  *  e1000_write_vfta_i350 - Write value to VLAN filter table
2971  *  @hw: pointer to the HW structure
2972  *  @offset: register offset in VLAN filter table
2973  *  @value: register value written to VLAN filter table
2974  *
2975  *  Writes value at the given offset in the register array which stores
2976  *  the VLAN filter table.
2977  **/
2978 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2979 {
2980         int i;
2981
2982         DEBUGFUNC("e1000_write_vfta_350");
2983
2984         for (i = 0; i < 10; i++)
2985                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2986
2987         E1000_WRITE_FLUSH(hw);
2988 }
2989
2990
2991 /**
2992  *  e1000_set_i2c_bb - Enable I2C bit-bang
2993  *  @hw: pointer to the HW structure
2994  *
2995  *  Enable I2C bit-bang interface
2996  *
2997  **/
2998 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2999 {
3000         s32 ret_val = E1000_SUCCESS;
3001         u32 ctrl_ext, i2cparams;
3002
3003         DEBUGFUNC("e1000_set_i2c_bb");
3004
3005         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3006         ctrl_ext |= E1000_CTRL_I2C_ENA;
3007         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3008         E1000_WRITE_FLUSH(hw);
3009
3010         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3011         i2cparams |= E1000_I2CBB_EN;
3012         i2cparams |= E1000_I2C_DATA_OE_N;
3013         i2cparams |= E1000_I2C_CLK_OE_N;
3014         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3015         E1000_WRITE_FLUSH(hw);
3016
3017         return ret_val;
3018 }
3019
3020 /**
3021  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3022  *  @hw: pointer to hardware structure
3023  *  @byte_offset: byte offset to read
3024  *  @dev_addr: device address
3025  *  @data: value read
3026  *
3027  *  Performs byte read operation over I2C interface at
3028  *  a specified device address.
3029  **/
3030 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3031                                 u8 dev_addr, u8 *data)
3032 {
3033         s32 status = E1000_SUCCESS;
3034         u32 max_retry = 10;
3035         u32 retry = 1;
3036         u16 swfw_mask = 0;
3037
3038         bool nack = TRUE;
3039
3040         DEBUGFUNC("e1000_read_i2c_byte_generic");
3041
3042         swfw_mask = E1000_SWFW_PHY0_SM;
3043
3044         do {
3045                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3046                     != E1000_SUCCESS) {
3047                         status = E1000_ERR_SWFW_SYNC;
3048                         goto read_byte_out;
3049                 }
3050
3051                 e1000_i2c_start(hw);
3052
3053                 /* Device Address and write indication */
3054                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3055                 if (status != E1000_SUCCESS)
3056                         goto fail;
3057
3058                 status = e1000_get_i2c_ack(hw);
3059                 if (status != E1000_SUCCESS)
3060                         goto fail;
3061
3062                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3063                 if (status != E1000_SUCCESS)
3064                         goto fail;
3065
3066                 status = e1000_get_i2c_ack(hw);
3067                 if (status != E1000_SUCCESS)
3068                         goto fail;
3069
3070                 e1000_i2c_start(hw);
3071
3072                 /* Device Address and read indication */
3073                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3074                 if (status != E1000_SUCCESS)
3075                         goto fail;
3076
3077                 status = e1000_get_i2c_ack(hw);
3078                 if (status != E1000_SUCCESS)
3079                         goto fail;
3080
3081                 status = e1000_clock_in_i2c_byte(hw, data);
3082                 if (status != E1000_SUCCESS)
3083                         goto fail;
3084
3085                 status = e1000_clock_out_i2c_bit(hw, nack);
3086                 if (status != E1000_SUCCESS)
3087                         goto fail;
3088
3089                 e1000_i2c_stop(hw);
3090                 break;
3091
3092 fail:
3093                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3094                 msec_delay(100);
3095                 e1000_i2c_bus_clear(hw);
3096                 retry++;
3097                 if (retry < max_retry)
3098                         DEBUGOUT("I2C byte read error - Retrying.\n");
3099                 else
3100                         DEBUGOUT("I2C byte read error.\n");
3101
3102         } while (retry < max_retry);
3103
3104         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3105
3106 read_byte_out:
3107
3108         return status;
3109 }
3110
3111 /**
3112  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3113  *  @hw: pointer to hardware structure
3114  *  @byte_offset: byte offset to write
3115  *  @dev_addr: device address
3116  *  @data: value to write
3117  *
3118  *  Performs byte write operation over I2C interface at
3119  *  a specified device address.
3120  **/
3121 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3122                                  u8 dev_addr, u8 data)
3123 {
3124         s32 status = E1000_SUCCESS;
3125         u32 max_retry = 1;
3126         u32 retry = 0;
3127         u16 swfw_mask = 0;
3128
3129         DEBUGFUNC("e1000_write_i2c_byte_generic");
3130
3131         swfw_mask = E1000_SWFW_PHY0_SM;
3132
3133         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3134                 status = E1000_ERR_SWFW_SYNC;
3135                 goto write_byte_out;
3136         }
3137
3138         do {
3139                 e1000_i2c_start(hw);
3140
3141                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3142                 if (status != E1000_SUCCESS)
3143                         goto fail;
3144
3145                 status = e1000_get_i2c_ack(hw);
3146                 if (status != E1000_SUCCESS)
3147                         goto fail;
3148
3149                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3150                 if (status != E1000_SUCCESS)
3151                         goto fail;
3152
3153                 status = e1000_get_i2c_ack(hw);
3154                 if (status != E1000_SUCCESS)
3155                         goto fail;
3156
3157                 status = e1000_clock_out_i2c_byte(hw, data);
3158                 if (status != E1000_SUCCESS)
3159                         goto fail;
3160
3161                 status = e1000_get_i2c_ack(hw);
3162                 if (status != E1000_SUCCESS)
3163                         goto fail;
3164
3165                 e1000_i2c_stop(hw);
3166                 break;
3167
3168 fail:
3169                 e1000_i2c_bus_clear(hw);
3170                 retry++;
3171                 if (retry < max_retry)
3172                         DEBUGOUT("I2C byte write error - Retrying.\n");
3173                 else
3174                         DEBUGOUT("I2C byte write error.\n");
3175         } while (retry < max_retry);
3176
3177         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3178
3179 write_byte_out:
3180
3181         return status;
3182 }
3183
3184 /**
3185  *  e1000_i2c_start - Sets I2C start condition
3186  *  @hw: pointer to hardware structure
3187  *
3188  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3189  **/
3190 static void e1000_i2c_start(struct e1000_hw *hw)
3191 {
3192         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3193
3194         DEBUGFUNC("e1000_i2c_start");
3195
3196         /* Start condition must begin with data and clock high */
3197         e1000_set_i2c_data(hw, &i2cctl, 1);
3198         e1000_raise_i2c_clk(hw, &i2cctl);
3199
3200         /* Setup time for start condition (4.7us) */
3201         usec_delay(E1000_I2C_T_SU_STA);
3202
3203         e1000_set_i2c_data(hw, &i2cctl, 0);
3204
3205         /* Hold time for start condition (4us) */
3206         usec_delay(E1000_I2C_T_HD_STA);
3207
3208         e1000_lower_i2c_clk(hw, &i2cctl);
3209
3210         /* Minimum low period of clock is 4.7 us */
3211         usec_delay(E1000_I2C_T_LOW);
3212
3213 }
3214
3215 /**
3216  *  e1000_i2c_stop - Sets I2C stop condition
3217  *  @hw: pointer to hardware structure
3218  *
3219  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3220  **/
3221 static void e1000_i2c_stop(struct e1000_hw *hw)
3222 {
3223         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3224
3225         DEBUGFUNC("e1000_i2c_stop");
3226
3227         /* Stop condition must begin with data low and clock high */
3228         e1000_set_i2c_data(hw, &i2cctl, 0);
3229         e1000_raise_i2c_clk(hw, &i2cctl);
3230
3231         /* Setup time for stop condition (4us) */
3232         usec_delay(E1000_I2C_T_SU_STO);
3233
3234         e1000_set_i2c_data(hw, &i2cctl, 1);
3235
3236         /* bus free time between stop and start (4.7us)*/
3237         usec_delay(E1000_I2C_T_BUF);
3238 }
3239
3240 /**
3241  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3242  *  @hw: pointer to hardware structure
3243  *  @data: data byte to clock in
3244  *
3245  *  Clocks in one byte data via I2C data/clock
3246  **/
3247 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3248 {
3249         s32 i;
3250         bool bit = 0;
3251
3252         DEBUGFUNC("e1000_clock_in_i2c_byte");
3253
3254         *data = 0;
3255         for (i = 7; i >= 0; i--) {
3256                 e1000_clock_in_i2c_bit(hw, &bit);
3257                 *data |= bit << i;
3258         }
3259
3260         return E1000_SUCCESS;
3261 }
3262
3263 /**
3264  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3265  *  @hw: pointer to hardware structure
3266  *  @data: data byte clocked out
3267  *
3268  *  Clocks out one byte data via I2C data/clock
3269  **/
3270 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3271 {
3272         s32 status = E1000_SUCCESS;
3273         s32 i;
3274         u32 i2cctl;
3275         bool bit = 0;
3276
3277         DEBUGFUNC("e1000_clock_out_i2c_byte");
3278
3279         for (i = 7; i >= 0; i--) {
3280                 bit = (data >> i) & 0x1;
3281                 status = e1000_clock_out_i2c_bit(hw, bit);
3282
3283                 if (status != E1000_SUCCESS)
3284                         break;
3285         }
3286
3287         /* Release SDA line (set high) */
3288         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3289
3290         i2cctl |= E1000_I2C_DATA_OE_N;
3291         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3292         E1000_WRITE_FLUSH(hw);
3293
3294         return status;
3295 }
3296
3297 /**
3298  *  e1000_get_i2c_ack - Polls for I2C ACK
3299  *  @hw: pointer to hardware structure
3300  *
3301  *  Clocks in/out one bit via I2C data/clock
3302  **/
3303 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3304 {
3305         s32 status = E1000_SUCCESS;
3306         u32 i = 0;
3307         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3308         u32 timeout = 10;
3309         bool ack = TRUE;
3310
3311         DEBUGFUNC("e1000_get_i2c_ack");
3312
3313         e1000_raise_i2c_clk(hw, &i2cctl);
3314
3315         /* Minimum high period of clock is 4us */
3316         usec_delay(E1000_I2C_T_HIGH);
3317
3318         /* Wait until SCL returns high */
3319         for (i = 0; i < timeout; i++) {
3320                 usec_delay(1);
3321                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3322                 if (i2cctl & E1000_I2C_CLK_IN)
3323                         break;
3324         }
3325         if (!(i2cctl & E1000_I2C_CLK_IN))
3326                 return E1000_ERR_I2C;
3327
3328         ack = e1000_get_i2c_data(&i2cctl);
3329         if (ack) {
3330                 DEBUGOUT("I2C ack was not received.\n");
3331                 status = E1000_ERR_I2C;
3332         }
3333
3334         e1000_lower_i2c_clk(hw, &i2cctl);
3335
3336         /* Minimum low period of clock is 4.7 us */
3337         usec_delay(E1000_I2C_T_LOW);
3338
3339         return status;
3340 }
3341
3342 /**
3343  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3344  *  @hw: pointer to hardware structure
3345  *  @data: read data value
3346  *
3347  *  Clocks in one bit via I2C data/clock
3348  **/
3349 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3350 {
3351         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3352
3353         DEBUGFUNC("e1000_clock_in_i2c_bit");
3354
3355         e1000_raise_i2c_clk(hw, &i2cctl);
3356
3357         /* Minimum high period of clock is 4us */
3358         usec_delay(E1000_I2C_T_HIGH);
3359
3360         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3361         *data = e1000_get_i2c_data(&i2cctl);
3362
3363         e1000_lower_i2c_clk(hw, &i2cctl);
3364
3365         /* Minimum low period of clock is 4.7 us */
3366         usec_delay(E1000_I2C_T_LOW);
3367
3368         return E1000_SUCCESS;
3369 }
3370
3371 /**
3372  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3373  *  @hw: pointer to hardware structure
3374  *  @data: data value to write
3375  *
3376  *  Clocks out one bit via I2C data/clock
3377  **/
3378 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3379 {
3380         s32 status;
3381         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3382
3383         DEBUGFUNC("e1000_clock_out_i2c_bit");
3384
3385         status = e1000_set_i2c_data(hw, &i2cctl, data);
3386         if (status == E1000_SUCCESS) {
3387                 e1000_raise_i2c_clk(hw, &i2cctl);
3388
3389                 /* Minimum high period of clock is 4us */
3390                 usec_delay(E1000_I2C_T_HIGH);
3391
3392                 e1000_lower_i2c_clk(hw, &i2cctl);
3393
3394                 /* Minimum low period of clock is 4.7 us.
3395                  * This also takes care of the data hold time.
3396                  */
3397                 usec_delay(E1000_I2C_T_LOW);
3398         } else {
3399                 status = E1000_ERR_I2C;
3400                 DEBUGOUT1("I2C data was not set to %X\n", data);
3401         }
3402
3403         return status;
3404 }
3405 /**
3406  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3407  *  @hw: pointer to hardware structure
3408  *  @i2cctl: Current value of I2CCTL register
3409  *
3410  *  Raises the I2C clock line '0'->'1'
3411  **/
3412 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3413 {
3414         DEBUGFUNC("e1000_raise_i2c_clk");
3415
3416         *i2cctl |= E1000_I2C_CLK_OUT;
3417         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3418         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3419         E1000_WRITE_FLUSH(hw);
3420
3421         /* SCL rise time (1000ns) */
3422         usec_delay(E1000_I2C_T_RISE);
3423 }
3424
3425 /**
3426  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3427  *  @hw: pointer to hardware structure
3428  *  @i2cctl: Current value of I2CCTL register
3429  *
3430  *  Lowers the I2C clock line '1'->'0'
3431  **/
3432 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3433 {
3434
3435         DEBUGFUNC("e1000_lower_i2c_clk");
3436
3437         *i2cctl &= ~E1000_I2C_CLK_OUT;
3438         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3439         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3440         E1000_WRITE_FLUSH(hw);
3441
3442         /* SCL fall time (300ns) */
3443         usec_delay(E1000_I2C_T_FALL);
3444 }
3445
3446 /**
3447  *  e1000_set_i2c_data - Sets the I2C data bit
3448  *  @hw: pointer to hardware structure
3449  *  @i2cctl: Current value of I2CCTL register
3450  *  @data: I2C data value (0 or 1) to set
3451  *
3452  *  Sets the I2C data bit
3453  **/
3454 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3455 {
3456         s32 status = E1000_SUCCESS;
3457
3458         DEBUGFUNC("e1000_set_i2c_data");
3459
3460         if (data)
3461                 *i2cctl |= E1000_I2C_DATA_OUT;
3462         else
3463                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3464
3465         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3466         *i2cctl |= E1000_I2C_CLK_OE_N;
3467         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3468         E1000_WRITE_FLUSH(hw);
3469
3470         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3471         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3472
3473         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3474         if (data != e1000_get_i2c_data(i2cctl)) {
3475                 status = E1000_ERR_I2C;
3476                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3477         }
3478
3479         return status;
3480 }
3481
3482 /**
3483  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3484  *  @hw: pointer to hardware structure
3485  *  @i2cctl: Current value of I2CCTL register
3486  *
3487  *  Returns the I2C data bit value
3488  **/
3489 static bool e1000_get_i2c_data(u32 *i2cctl)
3490 {
3491         bool data;
3492
3493         DEBUGFUNC("e1000_get_i2c_data");
3494
3495         if (*i2cctl & E1000_I2C_DATA_IN)
3496                 data = 1;
3497         else
3498                 data = 0;
3499
3500         return data;
3501 }
3502
3503 /**
3504  *  e1000_i2c_bus_clear - Clears the I2C bus
3505  *  @hw: pointer to hardware structure
3506  *
3507  *  Clears the I2C bus by sending nine clock pulses.
3508  *  Used when data line is stuck low.
3509  **/
3510 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3511 {
3512         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3513         u32 i;
3514
3515         DEBUGFUNC("e1000_i2c_bus_clear");
3516
3517         e1000_i2c_start(hw);
3518
3519         e1000_set_i2c_data(hw, &i2cctl, 1);
3520
3521         for (i = 0; i < 9; i++) {
3522                 e1000_raise_i2c_clk(hw, &i2cctl);
3523
3524                 /* Min high period of clock is 4us */
3525                 usec_delay(E1000_I2C_T_HIGH);
3526
3527                 e1000_lower_i2c_clk(hw, &i2cctl);
3528
3529                 /* Min low period of clock is 4.7us*/
3530                 usec_delay(E1000_I2C_T_LOW);
3531         }
3532
3533         e1000_i2c_start(hw);
3534
3535         /* Put the i2c bus back to default state */
3536         e1000_i2c_stop(hw);
3537 }
3538