2 * Copyright (c) 2012 Robert N. M. Watson
3 * Copyright (c) 2012 SRI International
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
8 * ("CTSRD"), as part of the DARPA CRASH research programme.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
37 #include <sys/condvar.h>
40 #include <sys/kernel.h>
42 #include <sys/malloc.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
46 #include <sys/systm.h>
47 #include <sys/taskqueue.h>
49 #include <machine/bus.h>
50 #include <machine/resource.h>
52 #include <geom/geom_disk.h>
54 #include <dev/isf/isf.h>
57 * Nexus bus attachment for the Intel Strata Flash devices. Appropriate for
58 * most Altera FPGA SoC-style configurations in which the part will be exposed
59 * to the processor via a memory-mapped Avalon bus.
62 isf_nexus_probe(device_t dev)
65 device_set_desc(dev, "Intel StrataFlash NOR flash device");
66 return (BUS_PROBE_DEFAULT);
70 isf_nexus_attach(device_t dev)
75 sc = device_get_softc(dev);
77 sc->isf_unit = device_get_unit(dev);
79 sc->isf_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
80 &sc->isf_rid, RF_ACTIVE);
81 if (sc->isf_res == NULL) {
82 device_printf(dev, "couldn't map memory\n");
85 error = isf_attach(sc);
87 bus_release_resource(dev, SYS_RES_MEMORY, sc->isf_rid,
93 isf_nexus_detach(device_t dev)
97 sc = device_get_softc(dev);
98 KASSERT(sc->isf_res != NULL, ("%s: resources not allocated",
101 bus_release_resource(dev, SYS_RES_MEMORY, sc->isf_rid, sc->isf_res);
105 static device_method_t isf_nexus_methods[] = {
106 DEVMETHOD(device_probe, isf_nexus_probe),
107 DEVMETHOD(device_attach, isf_nexus_attach),
108 DEVMETHOD(device_detach, isf_nexus_detach),
112 static driver_t isf_nexus_driver = {
115 sizeof(struct isf_softc),
118 DRIVER_MODULE(isf, nexus, isf_nexus_driver, isf_devclass, 0, 0);