sys/dev/ixl/i40e_common.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2013-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #include "i40e_type.h"
  36 #include "i40e_adminq.h"
  37 #include "i40e_prototype.h"
  38 #include "i40e_virtchnl.h"
  39
  40
  41 /**
  42  * i40e_set_mac_type - Sets MAC type
  43  * @hw: pointer to the HW structure
  44  *
  45  * This function sets the mac type of the adapter based on the
  46  * vendor ID and device ID stored in the hw structure.
  47  **/
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 {
  50         enum i40e_status_code status = I40E_SUCCESS;
  51
  52         DEBUGFUNC("i40e_set_mac_type\n");
  53
  54         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  55                 switch (hw->device_id) {
  56                 case I40E_DEV_ID_SFP_XL710:
  57                 case I40E_DEV_ID_QEMU:
  58                 case I40E_DEV_ID_KX_A:
  59                 case I40E_DEV_ID_KX_B:
  60                 case I40E_DEV_ID_KX_C:
  61                 case I40E_DEV_ID_QSFP_A:
  62                 case I40E_DEV_ID_QSFP_B:
  63                 case I40E_DEV_ID_QSFP_C:
  64                 case I40E_DEV_ID_10G_BASE_T:
  65                 case I40E_DEV_ID_10G_BASE_T4:
  66                 case I40E_DEV_ID_20G_KR2:
  67                 case I40E_DEV_ID_20G_KR2_A:
  68                         hw->mac.type = I40E_MAC_XL710;
  69                         break;
  70 #ifdef X722_SUPPORT
  71                 case I40E_DEV_ID_SFP_X722:
  72                 case I40E_DEV_ID_1G_BASE_T_X722:
  73                 case I40E_DEV_ID_10G_BASE_T_X722:
  74                         hw->mac.type = I40E_MAC_X722;
  75                         break;
  76 #endif
  77 #ifdef X722_SUPPORT
  78                 case I40E_DEV_ID_X722_VF:
  79                 case I40E_DEV_ID_X722_VF_HV:
  80                         hw->mac.type = I40E_MAC_X722_VF;
  81                         break;
  82 #endif
  83                 case I40E_DEV_ID_VF:
  84                 case I40E_DEV_ID_VF_HV:
  85                         hw->mac.type = I40E_MAC_VF;
  86                         break;
  87                 default:
  88                         hw->mac.type = I40E_MAC_GENERIC;
  89                         break;
  90                 }
  91         } else {
  92                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  93         }
  94
  95         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  96                   hw->mac.type, status);
  97         return status;
  98 }
  99
 100 /**
 101  * i40e_aq_str - convert AQ err code to a string
 102  * @hw: pointer to the HW structure
 103  * @aq_err: the AQ error code to convert
 104  **/
 105 char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 106 {
 107         switch (aq_err) {
 108         case I40E_AQ_RC_OK:
 109                 return "OK";
 110         case I40E_AQ_RC_EPERM:
 111                 return "I40E_AQ_RC_EPERM";
 112         case I40E_AQ_RC_ENOENT:
 113                 return "I40E_AQ_RC_ENOENT";
 114         case I40E_AQ_RC_ESRCH:
 115                 return "I40E_AQ_RC_ESRCH";
 116         case I40E_AQ_RC_EINTR:
 117                 return "I40E_AQ_RC_EINTR";
 118         case I40E_AQ_RC_EIO:
 119                 return "I40E_AQ_RC_EIO";
 120         case I40E_AQ_RC_ENXIO:
 121                 return "I40E_AQ_RC_ENXIO";
 122         case I40E_AQ_RC_E2BIG:
 123                 return "I40E_AQ_RC_E2BIG";
 124         case I40E_AQ_RC_EAGAIN:
 125                 return "I40E_AQ_RC_EAGAIN";
 126         case I40E_AQ_RC_ENOMEM:
 127                 return "I40E_AQ_RC_ENOMEM";
 128         case I40E_AQ_RC_EACCES:
 129                 return "I40E_AQ_RC_EACCES";
 130         case I40E_AQ_RC_EFAULT:
 131                 return "I40E_AQ_RC_EFAULT";
 132         case I40E_AQ_RC_EBUSY:
 133                 return "I40E_AQ_RC_EBUSY";
 134         case I40E_AQ_RC_EEXIST:
 135                 return "I40E_AQ_RC_EEXIST";
 136         case I40E_AQ_RC_EINVAL:
 137                 return "I40E_AQ_RC_EINVAL";
 138         case I40E_AQ_RC_ENOTTY:
 139                 return "I40E_AQ_RC_ENOTTY";
 140         case I40E_AQ_RC_ENOSPC:
 141                 return "I40E_AQ_RC_ENOSPC";
 142         case I40E_AQ_RC_ENOSYS:
 143                 return "I40E_AQ_RC_ENOSYS";
 144         case I40E_AQ_RC_ERANGE:
 145                 return "I40E_AQ_RC_ERANGE";
 146         case I40E_AQ_RC_EFLUSHED:
 147                 return "I40E_AQ_RC_EFLUSHED";
 148         case I40E_AQ_RC_BAD_ADDR:
 149                 return "I40E_AQ_RC_BAD_ADDR";
 150         case I40E_AQ_RC_EMODE:
 151                 return "I40E_AQ_RC_EMODE";
 152         case I40E_AQ_RC_EFBIG:
 153                 return "I40E_AQ_RC_EFBIG";
 154         }
 155
 156         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 157         return hw->err_str;
 158 }
 159
 160 /**
 161  * i40e_stat_str - convert status err code to a string
 162  * @hw: pointer to the HW structure
 163  * @stat_err: the status error code to convert
 164  **/
 165 char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 166 {
 167         switch (stat_err) {
 168         case I40E_SUCCESS:
 169                 return "OK";
 170         case I40E_ERR_NVM:
 171                 return "I40E_ERR_NVM";
 172         case I40E_ERR_NVM_CHECKSUM:
 173                 return "I40E_ERR_NVM_CHECKSUM";
 174         case I40E_ERR_PHY:
 175                 return "I40E_ERR_PHY";
 176         case I40E_ERR_CONFIG:
 177                 return "I40E_ERR_CONFIG";
 178         case I40E_ERR_PARAM:
 179                 return "I40E_ERR_PARAM";
 180         case I40E_ERR_MAC_TYPE:
 181                 return "I40E_ERR_MAC_TYPE";
 182         case I40E_ERR_UNKNOWN_PHY:
 183                 return "I40E_ERR_UNKNOWN_PHY";
 184         case I40E_ERR_LINK_SETUP:
 185                 return "I40E_ERR_LINK_SETUP";
 186         case I40E_ERR_ADAPTER_STOPPED:
 187                 return "I40E_ERR_ADAPTER_STOPPED";
 188         case I40E_ERR_INVALID_MAC_ADDR:
 189                 return "I40E_ERR_INVALID_MAC_ADDR";
 190         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 191                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 192         case I40E_ERR_MASTER_REQUESTS_PENDING:
 193                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 194         case I40E_ERR_INVALID_LINK_SETTINGS:
 195                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 196         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 197                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 198         case I40E_ERR_RESET_FAILED:
 199                 return "I40E_ERR_RESET_FAILED";
 200         case I40E_ERR_SWFW_SYNC:
 201                 return "I40E_ERR_SWFW_SYNC";
 202         case I40E_ERR_NO_AVAILABLE_VSI:
 203                 return "I40E_ERR_NO_AVAILABLE_VSI";
 204         case I40E_ERR_NO_MEMORY:
 205                 return "I40E_ERR_NO_MEMORY";
 206         case I40E_ERR_BAD_PTR:
 207                 return "I40E_ERR_BAD_PTR";
 208         case I40E_ERR_RING_FULL:
 209                 return "I40E_ERR_RING_FULL";
 210         case I40E_ERR_INVALID_PD_ID:
 211                 return "I40E_ERR_INVALID_PD_ID";
 212         case I40E_ERR_INVALID_QP_ID:
 213                 return "I40E_ERR_INVALID_QP_ID";
 214         case I40E_ERR_INVALID_CQ_ID:
 215                 return "I40E_ERR_INVALID_CQ_ID";
 216         case I40E_ERR_INVALID_CEQ_ID:
 217                 return "I40E_ERR_INVALID_CEQ_ID";
 218         case I40E_ERR_INVALID_AEQ_ID:
 219                 return "I40E_ERR_INVALID_AEQ_ID";
 220         case I40E_ERR_INVALID_SIZE:
 221                 return "I40E_ERR_INVALID_SIZE";
 222         case I40E_ERR_INVALID_ARP_INDEX:
 223                 return "I40E_ERR_INVALID_ARP_INDEX";
 224         case I40E_ERR_INVALID_FPM_FUNC_ID:
 225                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 226         case I40E_ERR_QP_INVALID_MSG_SIZE:
 227                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 228         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 229                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 230         case I40E_ERR_INVALID_FRAG_COUNT:
 231                 return "I40E_ERR_INVALID_FRAG_COUNT";
 232         case I40E_ERR_QUEUE_EMPTY:
 233                 return "I40E_ERR_QUEUE_EMPTY";
 234         case I40E_ERR_INVALID_ALIGNMENT:
 235                 return "I40E_ERR_INVALID_ALIGNMENT";
 236         case I40E_ERR_FLUSHED_QUEUE:
 237                 return "I40E_ERR_FLUSHED_QUEUE";
 238         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 239                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 240         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 241                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 242         case I40E_ERR_TIMEOUT:
 243                 return "I40E_ERR_TIMEOUT";
 244         case I40E_ERR_OPCODE_MISMATCH:
 245                 return "I40E_ERR_OPCODE_MISMATCH";
 246         case I40E_ERR_CQP_COMPL_ERROR:
 247                 return "I40E_ERR_CQP_COMPL_ERROR";
 248         case I40E_ERR_INVALID_VF_ID:
 249                 return "I40E_ERR_INVALID_VF_ID";
 250         case I40E_ERR_INVALID_HMCFN_ID:
 251                 return "I40E_ERR_INVALID_HMCFN_ID";
 252         case I40E_ERR_BACKING_PAGE_ERROR:
 253                 return "I40E_ERR_BACKING_PAGE_ERROR";
 254         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 255                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 256         case I40E_ERR_INVALID_PBLE_INDEX:
 257                 return "I40E_ERR_INVALID_PBLE_INDEX";
 258         case I40E_ERR_INVALID_SD_INDEX:
 259                 return "I40E_ERR_INVALID_SD_INDEX";
 260         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 261                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 262         case I40E_ERR_INVALID_SD_TYPE:
 263                 return "I40E_ERR_INVALID_SD_TYPE";
 264         case I40E_ERR_MEMCPY_FAILED:
 265                 return "I40E_ERR_MEMCPY_FAILED";
 266         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 267                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 268         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 269                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 270         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 271                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 272         case I40E_ERR_SRQ_ENABLED:
 273                 return "I40E_ERR_SRQ_ENABLED";
 274         case I40E_ERR_ADMIN_QUEUE_ERROR:
 275                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 276         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 277                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 278         case I40E_ERR_BUF_TOO_SHORT:
 279                 return "I40E_ERR_BUF_TOO_SHORT";
 280         case I40E_ERR_ADMIN_QUEUE_FULL:
 281                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 282         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 283                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 284         case I40E_ERR_BAD_IWARP_CQE:
 285                 return "I40E_ERR_BAD_IWARP_CQE";
 286         case I40E_ERR_NVM_BLANK_MODE:
 287                 return "I40E_ERR_NVM_BLANK_MODE";
 288         case I40E_ERR_NOT_IMPLEMENTED:
 289                 return "I40E_ERR_NOT_IMPLEMENTED";
 290         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 291                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 292         case I40E_ERR_DIAG_TEST_FAILED:
 293                 return "I40E_ERR_DIAG_TEST_FAILED";
 294         case I40E_ERR_NOT_READY:
 295                 return "I40E_ERR_NOT_READY";
 296         case I40E_NOT_SUPPORTED:
 297                 return "I40E_NOT_SUPPORTED";
 298         case I40E_ERR_FIRMWARE_API_VERSION:
 299                 return "I40E_ERR_FIRMWARE_API_VERSION";
 300         }
 301
 302         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 303         return hw->err_str;
 304 }
 305
 306 /**
 307  * i40e_debug_aq
 308  * @hw: debug mask related to admin queue
 309  * @mask: debug mask
 310  * @desc: pointer to admin queue descriptor
 311  * @buffer: pointer to command buffer
 312  * @buf_len: max length of buffer
 313  *
 314  * Dumps debug log about adminq command with descriptor contents.
 315  **/
 316 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 317                    void *buffer, u16 buf_len)
 318 {
 319         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 320         u16 len = LE16_TO_CPU(aq_desc->datalen);
 321         u8 *buf = (u8 *)buffer;
 322         u16 i = 0;
 323
 324         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 325                 return;
 326
 327         i40e_debug(hw, mask,
 328                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 329                    LE16_TO_CPU(aq_desc->opcode),
 330                    LE16_TO_CPU(aq_desc->flags),
 331                    LE16_TO_CPU(aq_desc->datalen),
 332                    LE16_TO_CPU(aq_desc->retval));
 333         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 334                    LE32_TO_CPU(aq_desc->cookie_high),
 335                    LE32_TO_CPU(aq_desc->cookie_low));
 336         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 337                    LE32_TO_CPU(aq_desc->params.internal.param0),
 338                    LE32_TO_CPU(aq_desc->params.internal.param1));
 339         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 340                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 341                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 342
 343         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 344                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 345                 if (buf_len < len)
 346                         len = buf_len;
 347                 /* write the full 16-byte chunks */
 348                 for (i = 0; i < (len - 16); i += 16)
 349                         i40e_debug(hw, mask,
 350                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 351                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 352                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 353                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 354                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 355                 /* write whatever's left over without overrunning the buffer */
 356                 if (i < len) {
 357                         char d_buf[80];
 358                         int j = 0;
 359
 360                         memset(d_buf, 0, sizeof(d_buf));
 361                         j += sprintf(d_buf, "\t0x%04X ", i);
 362                         while (i < len)
 363                                 j += sprintf(&d_buf[j], " %02X", buf[i++]);
 364                         i40e_debug(hw, mask, "%s\n", d_buf);
 365                 }
 366         }
 367 }
 368
 369 /**
 370  * i40e_check_asq_alive
 371  * @hw: pointer to the hw struct
 372  *
 373  * Returns TRUE if Queue is enabled else FALSE.
 374  **/
 375 bool i40e_check_asq_alive(struct i40e_hw *hw)
 376 {
 377         if (hw->aq.asq.len) {
 378                 if (!i40e_is_vf(hw))
 379                         return !!(rd32(hw, hw->aq.asq.len) &
 380                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 381                 else
 382                         return !!(rd32(hw, hw->aq.asq.len) &
 383                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 384         }
 385         return FALSE;
 386 }
 387
 388 /**
 389  * i40e_aq_queue_shutdown
 390  * @hw: pointer to the hw struct
 391  * @unloading: is the driver unloading itself
 392  *
 393  * Tell the Firmware that we're shutting down the AdminQ and whether
 394  * or not the driver is unloading as well.
 395  **/
 396 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 397                                              bool unloading)
 398 {
 399         struct i40e_aq_desc desc;
 400         struct i40e_aqc_queue_shutdown *cmd =
 401                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 402         enum i40e_status_code status;
 403
 404         i40e_fill_default_direct_cmd_desc(&desc,
 405                                           i40e_aqc_opc_queue_shutdown);
 406
 407         if (unloading)
 408                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 409         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 410
 411         return status;
 412 }
 413 #ifdef X722_SUPPORT
 414
 415 /**
 416  * i40e_aq_get_set_rss_lut
 417  * @hw: pointer to the hardware structure
 418  * @vsi_id: vsi fw index
 419  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
 420  * @lut: pointer to the lut buffer provided by the caller
 421  * @lut_size: size of the lut buffer
 422  * @set: set TRUE to set the table, FALSE to get the table
 423  *
 424  * Internal function to get or set RSS look up table
 425  **/
 426 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 427                                                      u16 vsi_id, bool pf_lut,
 428                                                      u8 *lut, u16 lut_size,
 429                                                      bool set)
 430 {
 431         enum i40e_status_code status;
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 434                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 435
 436         if (set)
 437                 i40e_fill_default_direct_cmd_desc(&desc,
 438                                                   i40e_aqc_opc_set_rss_lut);
 439         else
 440                 i40e_fill_default_direct_cmd_desc(&desc,
 441                                                   i40e_aqc_opc_get_rss_lut);
 442
 443         /* Indirect command */
 444         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 445         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 446
 447         cmd_resp->vsi_id =
 448                         CPU_TO_LE16((u16)((vsi_id <<
 449                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 450                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 451         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 452
 453         if (pf_lut)
 454                 cmd_resp->flags |= CPU_TO_LE16((u16)
 455                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 456                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 457                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 458         else
 459                 cmd_resp->flags |= CPU_TO_LE16((u16)
 460                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 461                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 462                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 463
 464         cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)lut));
 465         cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)lut));
 466
 467         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 468
 469         return status;
 470 }
 471
 472 /**
 473  * i40e_aq_get_rss_lut
 474  * @hw: pointer to the hardware structure
 475  * @vsi_id: vsi fw index
 476  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
 477  * @lut: pointer to the lut buffer provided by the caller
 478  * @lut_size: size of the lut buffer
 479  *
 480  * get the RSS lookup table, PF or VSI type
 481  **/
 482 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 483                                           bool pf_lut, u8 *lut, u16 lut_size)
 484 {
 485         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 486                                        FALSE);
 487 }
 488
 489 /**
 490  * i40e_aq_set_rss_lut
 491  * @hw: pointer to the hardware structure
 492  * @vsi_id: vsi fw index
 493  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
 494  * @lut: pointer to the lut buffer provided by the caller
 495  * @lut_size: size of the lut buffer
 496  *
 497  * set the RSS lookup table, PF or VSI type
 498  **/
 499 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 500                                           bool pf_lut, u8 *lut, u16 lut_size)
 501 {
 502         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
 503 }
 504
 505 /**
 506  * i40e_aq_get_set_rss_key
 507  * @hw: pointer to the hw struct
 508  * @vsi_id: vsi fw index
 509  * @key: pointer to key info struct
 510  * @set: set TRUE to set the key, FALSE to get the key
 511  *
 512  * get the RSS key per VSI
 513  **/
 514 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 515                                       u16 vsi_id,
 516                                       struct i40e_aqc_get_set_rss_key_data *key,
 517                                       bool set)
 518 {
 519         enum i40e_status_code status;
 520         struct i40e_aq_desc desc;
 521         struct i40e_aqc_get_set_rss_key *cmd_resp =
 522                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 523         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 524
 525         if (set)
 526                 i40e_fill_default_direct_cmd_desc(&desc,
 527                                                   i40e_aqc_opc_set_rss_key);
 528         else
 529                 i40e_fill_default_direct_cmd_desc(&desc,
 530                                                   i40e_aqc_opc_get_rss_key);
 531
 532         /* Indirect command */
 533         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 534         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 535
 536         cmd_resp->vsi_id =
 537                         CPU_TO_LE16((u16)((vsi_id <<
 538                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 539                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 540         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 541         cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)key));
 542         cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)key));
 543
 544         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 545
 546         return status;
 547 }
 548
 549 /**
 550  * i40e_aq_get_rss_key
 551  * @hw: pointer to the hw struct
 552  * @vsi_id: vsi fw index
 553  * @key: pointer to key info struct
 554  *
 555  **/
 556 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 557                                       u16 vsi_id,
 558                                       struct i40e_aqc_get_set_rss_key_data *key)
 559 {
 560         return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
 561 }
 562
 563 /**
 564  * i40e_aq_set_rss_key
 565  * @hw: pointer to the hw struct
 566  * @vsi_id: vsi fw index
 567  * @key: pointer to key info struct
 568  *
 569  * set the RSS key per VSI
 570  **/
 571 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 572                                       u16 vsi_id,
 573                                       struct i40e_aqc_get_set_rss_key_data *key)
 574 {
 575         return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
 576 }
 577 #endif /* X722_SUPPORT */
 578
 579 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 580  * hardware to a bit-field that can be used by SW to more easily determine the
 581  * packet type.
 582  *
 583  * Macros are used to shorten the table lines and make this table human
 584  * readable.
 585  *
 586  * We store the PTYPE in the top byte of the bit field - this is just so that
 587  * we can check that the table doesn't have a row missing, as the index into
 588  * the table should be the PTYPE.
 589  *
 590  * Typical work flow:
 591  *
 592  * IF NOT i40e_ptype_lookup[ptype].known
 593  * THEN
 594  *      Packet is unknown
 595  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 596  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 597  * ELSE
 598  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 599  * ENDIF
 600  */
 601
 602 /* macro to make the table lines short */
 603 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 604         {       PTYPE, \
 605                 1, \
 606                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 607                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 608                 I40E_RX_PTYPE_##OUTER_FRAG, \
 609                 I40E_RX_PTYPE_TUNNEL_##T, \
 610                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 611                 I40E_RX_PTYPE_##TEF, \
 612                 I40E_RX_PTYPE_INNER_PROT_##I, \
 613                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 614
 615 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 616                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 617
 618 /* shorter macros makes the table fit but are terse */
 619 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 620 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 621 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 622
 623 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 624 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 625         /* L2 Packet types */
 626         I40E_PTT_UNUSED_ENTRY(0),
 627         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 628         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 629         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 630         I40E_PTT_UNUSED_ENTRY(4),
 631         I40E_PTT_UNUSED_ENTRY(5),
 632         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 633         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 634         I40E_PTT_UNUSED_ENTRY(8),
 635         I40E_PTT_UNUSED_ENTRY(9),
 636         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 637         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 638         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 639         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 640         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 641         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648
 649         /* Non Tunneled IPv4 */
 650         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 651         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 652         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 653         I40E_PTT_UNUSED_ENTRY(25),
 654         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 655         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 656         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 657
 658         /* IPv4 --> IPv4 */
 659         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 660         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 661         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 662         I40E_PTT_UNUSED_ENTRY(32),
 663         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 664         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 665         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 666
 667         /* IPv4 --> IPv6 */
 668         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 669         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 670         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 671         I40E_PTT_UNUSED_ENTRY(39),
 672         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 673         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 674         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 675
 676         /* IPv4 --> GRE/NAT */
 677         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 678
 679         /* IPv4 --> GRE/NAT --> IPv4 */
 680         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 681         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 682         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 683         I40E_PTT_UNUSED_ENTRY(47),
 684         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 685         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 686         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 687
 688         /* IPv4 --> GRE/NAT --> IPv6 */
 689         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 690         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 691         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 692         I40E_PTT_UNUSED_ENTRY(54),
 693         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 694         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 695         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 696
 697         /* IPv4 --> GRE/NAT --> MAC */
 698         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 699
 700         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 701         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 702         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 703         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 704         I40E_PTT_UNUSED_ENTRY(62),
 705         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 706         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 707         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 708
 709         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 710         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 711         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 712         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 713         I40E_PTT_UNUSED_ENTRY(69),
 714         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 715         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 716         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 717
 718         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 719         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 720
 721         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 722         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 723         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 724         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 725         I40E_PTT_UNUSED_ENTRY(77),
 726         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 727         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 728         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 729
 730         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 731         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 732         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 733         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 734         I40E_PTT_UNUSED_ENTRY(84),
 735         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 736         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 737         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 738
 739         /* Non Tunneled IPv6 */
 740         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 741         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 742         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 743         I40E_PTT_UNUSED_ENTRY(91),
 744         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 745         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 746         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 747
 748         /* IPv6 --> IPv4 */
 749         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 750         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 751         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 752         I40E_PTT_UNUSED_ENTRY(98),
 753         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 754         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 755         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 756
 757         /* IPv6 --> IPv6 */
 758         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 759         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 760         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 761         I40E_PTT_UNUSED_ENTRY(105),
 762         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 763         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 764         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 765
 766         /* IPv6 --> GRE/NAT */
 767         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 768
 769         /* IPv6 --> GRE/NAT -> IPv4 */
 770         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 771         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 772         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 773         I40E_PTT_UNUSED_ENTRY(113),
 774         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 775         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 776         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 777
 778         /* IPv6 --> GRE/NAT -> IPv6 */
 779         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 780         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 781         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 782         I40E_PTT_UNUSED_ENTRY(120),
 783         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 784         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 785         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 786
 787         /* IPv6 --> GRE/NAT -> MAC */
 788         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 789
 790         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 791         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 792         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 793         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 794         I40E_PTT_UNUSED_ENTRY(128),
 795         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 796         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 797         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 798
 799         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 800         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 801         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 802         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 803         I40E_PTT_UNUSED_ENTRY(135),
 804         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 805         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 806         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 807
 808         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 809         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 810
 811         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 812         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 813         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 814         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 815         I40E_PTT_UNUSED_ENTRY(143),
 816         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 817         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 818         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 819
 820         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 821         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 822         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 823         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 824         I40E_PTT_UNUSED_ENTRY(150),
 825         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 826         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 827         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 828
 829         /* unused entries */
 830         I40E_PTT_UNUSED_ENTRY(154),
 831         I40E_PTT_UNUSED_ENTRY(155),
 832         I40E_PTT_UNUSED_ENTRY(156),
 833         I40E_PTT_UNUSED_ENTRY(157),
 834         I40E_PTT_UNUSED_ENTRY(158),
 835         I40E_PTT_UNUSED_ENTRY(159),
 836
 837         I40E_PTT_UNUSED_ENTRY(160),
 838         I40E_PTT_UNUSED_ENTRY(161),
 839         I40E_PTT_UNUSED_ENTRY(162),
 840         I40E_PTT_UNUSED_ENTRY(163),
 841         I40E_PTT_UNUSED_ENTRY(164),
 842         I40E_PTT_UNUSED_ENTRY(165),
 843         I40E_PTT_UNUSED_ENTRY(166),
 844         I40E_PTT_UNUSED_ENTRY(167),
 845         I40E_PTT_UNUSED_ENTRY(168),
 846         I40E_PTT_UNUSED_ENTRY(169),
 847
 848         I40E_PTT_UNUSED_ENTRY(170),
 849         I40E_PTT_UNUSED_ENTRY(171),
 850         I40E_PTT_UNUSED_ENTRY(172),
 851         I40E_PTT_UNUSED_ENTRY(173),
 852         I40E_PTT_UNUSED_ENTRY(174),
 853         I40E_PTT_UNUSED_ENTRY(175),
 854         I40E_PTT_UNUSED_ENTRY(176),
 855         I40E_PTT_UNUSED_ENTRY(177),
 856         I40E_PTT_UNUSED_ENTRY(178),
 857         I40E_PTT_UNUSED_ENTRY(179),
 858
 859         I40E_PTT_UNUSED_ENTRY(180),
 860         I40E_PTT_UNUSED_ENTRY(181),
 861         I40E_PTT_UNUSED_ENTRY(182),
 862         I40E_PTT_UNUSED_ENTRY(183),
 863         I40E_PTT_UNUSED_ENTRY(184),
 864         I40E_PTT_UNUSED_ENTRY(185),
 865         I40E_PTT_UNUSED_ENTRY(186),
 866         I40E_PTT_UNUSED_ENTRY(187),
 867         I40E_PTT_UNUSED_ENTRY(188),
 868         I40E_PTT_UNUSED_ENTRY(189),
 869
 870         I40E_PTT_UNUSED_ENTRY(190),
 871         I40E_PTT_UNUSED_ENTRY(191),
 872         I40E_PTT_UNUSED_ENTRY(192),
 873         I40E_PTT_UNUSED_ENTRY(193),
 874         I40E_PTT_UNUSED_ENTRY(194),
 875         I40E_PTT_UNUSED_ENTRY(195),
 876         I40E_PTT_UNUSED_ENTRY(196),
 877         I40E_PTT_UNUSED_ENTRY(197),
 878         I40E_PTT_UNUSED_ENTRY(198),
 879         I40E_PTT_UNUSED_ENTRY(199),
 880
 881         I40E_PTT_UNUSED_ENTRY(200),
 882         I40E_PTT_UNUSED_ENTRY(201),
 883         I40E_PTT_UNUSED_ENTRY(202),
 884         I40E_PTT_UNUSED_ENTRY(203),
 885         I40E_PTT_UNUSED_ENTRY(204),
 886         I40E_PTT_UNUSED_ENTRY(205),
 887         I40E_PTT_UNUSED_ENTRY(206),
 888         I40E_PTT_UNUSED_ENTRY(207),
 889         I40E_PTT_UNUSED_ENTRY(208),
 890         I40E_PTT_UNUSED_ENTRY(209),
 891
 892         I40E_PTT_UNUSED_ENTRY(210),
 893         I40E_PTT_UNUSED_ENTRY(211),
 894         I40E_PTT_UNUSED_ENTRY(212),
 895         I40E_PTT_UNUSED_ENTRY(213),
 896         I40E_PTT_UNUSED_ENTRY(214),
 897         I40E_PTT_UNUSED_ENTRY(215),
 898         I40E_PTT_UNUSED_ENTRY(216),
 899         I40E_PTT_UNUSED_ENTRY(217),
 900         I40E_PTT_UNUSED_ENTRY(218),
 901         I40E_PTT_UNUSED_ENTRY(219),
 902
 903         I40E_PTT_UNUSED_ENTRY(220),
 904         I40E_PTT_UNUSED_ENTRY(221),
 905         I40E_PTT_UNUSED_ENTRY(222),
 906         I40E_PTT_UNUSED_ENTRY(223),
 907         I40E_PTT_UNUSED_ENTRY(224),
 908         I40E_PTT_UNUSED_ENTRY(225),
 909         I40E_PTT_UNUSED_ENTRY(226),
 910         I40E_PTT_UNUSED_ENTRY(227),
 911         I40E_PTT_UNUSED_ENTRY(228),
 912         I40E_PTT_UNUSED_ENTRY(229),
 913
 914         I40E_PTT_UNUSED_ENTRY(230),
 915         I40E_PTT_UNUSED_ENTRY(231),
 916         I40E_PTT_UNUSED_ENTRY(232),
 917         I40E_PTT_UNUSED_ENTRY(233),
 918         I40E_PTT_UNUSED_ENTRY(234),
 919         I40E_PTT_UNUSED_ENTRY(235),
 920         I40E_PTT_UNUSED_ENTRY(236),
 921         I40E_PTT_UNUSED_ENTRY(237),
 922         I40E_PTT_UNUSED_ENTRY(238),
 923         I40E_PTT_UNUSED_ENTRY(239),
 924
 925         I40E_PTT_UNUSED_ENTRY(240),
 926         I40E_PTT_UNUSED_ENTRY(241),
 927         I40E_PTT_UNUSED_ENTRY(242),
 928         I40E_PTT_UNUSED_ENTRY(243),
 929         I40E_PTT_UNUSED_ENTRY(244),
 930         I40E_PTT_UNUSED_ENTRY(245),
 931         I40E_PTT_UNUSED_ENTRY(246),
 932         I40E_PTT_UNUSED_ENTRY(247),
 933         I40E_PTT_UNUSED_ENTRY(248),
 934         I40E_PTT_UNUSED_ENTRY(249),
 935
 936         I40E_PTT_UNUSED_ENTRY(250),
 937         I40E_PTT_UNUSED_ENTRY(251),
 938         I40E_PTT_UNUSED_ENTRY(252),
 939         I40E_PTT_UNUSED_ENTRY(253),
 940         I40E_PTT_UNUSED_ENTRY(254),
 941         I40E_PTT_UNUSED_ENTRY(255)
 942 };
 943
 944
 945 /**
 946  * i40e_validate_mac_addr - Validate unicast MAC address
 947  * @mac_addr: pointer to MAC address
 948  *
 949  * Tests a MAC address to ensure it is a valid Individual Address
 950  **/
 951 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 952 {
 953         enum i40e_status_code status = I40E_SUCCESS;
 954
 955         DEBUGFUNC("i40e_validate_mac_addr");
 956
 957         /* Broadcast addresses ARE multicast addresses
 958          * Make sure it is not a multicast address
 959          * Reject the zero address
 960          */
 961         if (I40E_IS_MULTICAST(mac_addr) ||
 962             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 963               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 964                 status = I40E_ERR_INVALID_MAC_ADDR;
 965
 966         return status;
 967 }
 968
 969 /**
 970  * i40e_init_shared_code - Initialize the shared code
 971  * @hw: pointer to hardware structure
 972  *
 973  * This assigns the MAC type and PHY code and inits the NVM.
 974  * Does not touch the hardware. This function must be called prior to any
 975  * other function in the shared code. The i40e_hw structure should be
 976  * memset to 0 prior to calling this function.  The following fields in
 977  * hw structure should be filled in prior to calling this function:
 978  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 979  * subsystem_vendor_id, and revision_id
 980  **/
 981 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 982 {
 983         enum i40e_status_code status = I40E_SUCCESS;
 984         u32 port, ari, func_rid;
 985
 986         DEBUGFUNC("i40e_init_shared_code");
 987
 988         i40e_set_mac_type(hw);
 989
 990         switch (hw->mac.type) {
 991         case I40E_MAC_XL710:
 992 #ifdef X722_SUPPORT
 993         case I40E_MAC_X722:
 994 #endif
 995                 break;
 996         default:
 997                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 998         }
 999
1000         hw->phy.get_link_info = TRUE;
1001
1002         /* Determine port number and PF number*/
1003         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1004                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1005         hw->port = (u8)port;
1006         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1007                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1008         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1009         if (ari)
1010                 hw->pf_id = (u8)(func_rid & 0xff);
1011         else
1012                 hw->pf_id = (u8)(func_rid & 0x7);
1013
1014         status = i40e_init_nvm(hw);
1015         return status;
1016 }
1017
1018 /**
1019  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1020  * @hw: pointer to the hw struct
1021  * @flags: a return indicator of what addresses were added to the addr store
1022  * @addrs: the requestor's mac addr store
1023  * @cmd_details: pointer to command details structure or NULL
1024  **/
1025 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1026                                    u16 *flags,
1027                                    struct i40e_aqc_mac_address_read_data *addrs,
1028                                    struct i40e_asq_cmd_details *cmd_details)
1029 {
1030         struct i40e_aq_desc desc;
1031         struct i40e_aqc_mac_address_read *cmd_data =
1032                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1033         enum i40e_status_code status;
1034
1035         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1036         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1037
1038         status = i40e_asq_send_command(hw, &desc, addrs,
1039                                        sizeof(*addrs), cmd_details);
1040         *flags = LE16_TO_CPU(cmd_data->command_flags);
1041
1042         return status;
1043 }
1044
1045 /**
1046  * i40e_aq_mac_address_write - Change the MAC addresses
1047  * @hw: pointer to the hw struct
1048  * @flags: indicates which MAC to be written
1049  * @mac_addr: address to write
1050  * @cmd_details: pointer to command details structure or NULL
1051  **/
1052 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1053                                     u16 flags, u8 *mac_addr,
1054                                     struct i40e_asq_cmd_details *cmd_details)
1055 {
1056         struct i40e_aq_desc desc;
1057         struct i40e_aqc_mac_address_write *cmd_data =
1058                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1059         enum i40e_status_code status;
1060
1061         i40e_fill_default_direct_cmd_desc(&desc,
1062                                           i40e_aqc_opc_mac_address_write);
1063         cmd_data->command_flags = CPU_TO_LE16(flags);
1064         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1065         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1066                                         ((u32)mac_addr[3] << 16) |
1067                                         ((u32)mac_addr[4] << 8) |
1068                                         mac_addr[5]);
1069
1070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1071
1072         return status;
1073 }
1074
1075 /**
1076  * i40e_get_mac_addr - get MAC address
1077  * @hw: pointer to the HW structure
1078  * @mac_addr: pointer to MAC address
1079  *
1080  * Reads the adapter's MAC address from register
1081  **/
1082 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1083 {
1084         struct i40e_aqc_mac_address_read_data addrs;
1085         enum i40e_status_code status;
1086         u16 flags = 0;
1087
1088         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1089
1090         if (flags & I40E_AQC_LAN_ADDR_VALID)
1091                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1092
1093         return status;
1094 }
1095
1096 /**
1097  * i40e_get_port_mac_addr - get Port MAC address
1098  * @hw: pointer to the HW structure
1099  * @mac_addr: pointer to Port MAC address
1100  *
1101  * Reads the adapter's Port MAC address
1102  **/
1103 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1104 {
1105         struct i40e_aqc_mac_address_read_data addrs;
1106         enum i40e_status_code status;
1107         u16 flags = 0;
1108
1109         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1110         if (status)
1111                 return status;
1112
1113         if (flags & I40E_AQC_PORT_ADDR_VALID)
1114                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1115         else
1116                 status = I40E_ERR_INVALID_MAC_ADDR;
1117
1118         return status;
1119 }
1120
1121 /**
1122  * i40e_pre_tx_queue_cfg - pre tx queue configure
1123  * @hw: pointer to the HW structure
1124  * @queue: target pf queue index
1125  * @enable: state change request
1126  *
1127  * Handles hw requirement to indicate intention to enable
1128  * or disable target queue.
1129  **/
1130 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1131 {
1132         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1133         u32 reg_block = 0;
1134         u32 reg_val;
1135
1136         if (abs_queue_idx >= 128) {
1137                 reg_block = abs_queue_idx / 128;
1138                 abs_queue_idx %= 128;
1139         }
1140
1141         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1142         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1143         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1144
1145         if (enable)
1146                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1147         else
1148                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1149
1150         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1151 }
1152
1153 /**
1154  *  i40e_read_pba_string - Reads part number string from EEPROM
1155  *  @hw: pointer to hardware structure
1156  *  @pba_num: stores the part number string from the EEPROM
1157  *  @pba_num_size: part number string buffer length
1158  *
1159  *  Reads the part number string from the EEPROM.
1160  **/
1161 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1162                                             u32 pba_num_size)
1163 {
1164         enum i40e_status_code status = I40E_SUCCESS;
1165         u16 pba_word = 0;
1166         u16 pba_size = 0;
1167         u16 pba_ptr = 0;
1168         u16 i = 0;
1169
1170         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1171         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1172                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1173                 return status;
1174         }
1175
1176         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1177         if (status != I40E_SUCCESS) {
1178                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1179                 return status;
1180         }
1181
1182         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1183         if (status != I40E_SUCCESS) {
1184                 DEBUGOUT("Failed to read PBA Block size.\n");
1185                 return status;
1186         }
1187
1188         /* Subtract one to get PBA word count (PBA Size word is included in
1189          * total size)
1190          */
1191         pba_size--;
1192         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1193                 DEBUGOUT("Buffer to small for PBA data.\n");
1194                 return I40E_ERR_PARAM;
1195         }
1196
1197         for (i = 0; i < pba_size; i++) {
1198                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1199                 if (status != I40E_SUCCESS) {
1200                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1201                         return status;
1202                 }
1203
1204                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1205                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1206         }
1207         pba_num[(pba_size * 2)] = '\0';
1208
1209         return status;
1210 }
1211
1212 /**
1213  * i40e_get_media_type - Gets media type
1214  * @hw: pointer to the hardware structure
1215  **/
1216 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1217 {
1218         enum i40e_media_type media;
1219
1220         switch (hw->phy.link_info.phy_type) {
1221         case I40E_PHY_TYPE_10GBASE_SR:
1222         case I40E_PHY_TYPE_10GBASE_LR:
1223         case I40E_PHY_TYPE_1000BASE_SX:
1224         case I40E_PHY_TYPE_1000BASE_LX:
1225         case I40E_PHY_TYPE_40GBASE_SR4:
1226         case I40E_PHY_TYPE_40GBASE_LR4:
1227                 media = I40E_MEDIA_TYPE_FIBER;
1228                 break;
1229         case I40E_PHY_TYPE_100BASE_TX:
1230         case I40E_PHY_TYPE_1000BASE_T:
1231         case I40E_PHY_TYPE_10GBASE_T:
1232                 media = I40E_MEDIA_TYPE_BASET;
1233                 break;
1234         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1235         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1236         case I40E_PHY_TYPE_10GBASE_CR1:
1237         case I40E_PHY_TYPE_40GBASE_CR4:
1238         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1239         case I40E_PHY_TYPE_40GBASE_AOC:
1240         case I40E_PHY_TYPE_10GBASE_AOC:
1241                 media = I40E_MEDIA_TYPE_DA;
1242                 break;
1243         case I40E_PHY_TYPE_1000BASE_KX:
1244         case I40E_PHY_TYPE_10GBASE_KX4:
1245         case I40E_PHY_TYPE_10GBASE_KR:
1246         case I40E_PHY_TYPE_40GBASE_KR4:
1247         case I40E_PHY_TYPE_20GBASE_KR2:
1248                 media = I40E_MEDIA_TYPE_BACKPLANE;
1249                 break;
1250         case I40E_PHY_TYPE_SGMII:
1251         case I40E_PHY_TYPE_XAUI:
1252         case I40E_PHY_TYPE_XFI:
1253         case I40E_PHY_TYPE_XLAUI:
1254         case I40E_PHY_TYPE_XLPPI:
1255         default:
1256                 media = I40E_MEDIA_TYPE_UNKNOWN;
1257                 break;
1258         }
1259
1260         return media;
1261 }
1262
1263 #define I40E_PF_RESET_WAIT_COUNT        200
1264 /**
1265  * i40e_pf_reset - Reset the PF
1266  * @hw: pointer to the hardware structure
1267  *
1268  * Assuming someone else has triggered a global reset,
1269  * assure the global reset is complete and then reset the PF
1270  **/
1271 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1272 {
1273         u32 cnt = 0;
1274         u32 cnt1 = 0;
1275         u32 reg = 0;
1276         u32 grst_del;
1277
1278         /* Poll for Global Reset steady state in case of recent GRST.
1279          * The grst delay value is in 100ms units, and we'll wait a
1280          * couple counts longer to be sure we don't just miss the end.
1281          */
1282         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1283                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1284                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1285         for (cnt = 0; cnt < grst_del + 10; cnt++) {
1286                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1287                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1288                         break;
1289                 i40e_msec_delay(100);
1290         }
1291         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1292                 DEBUGOUT("Global reset polling failed to complete.\n");
1293                 return I40E_ERR_RESET_FAILED;
1294         }
1295
1296         /* Now Wait for the FW to be ready */
1297         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1298                 reg = rd32(hw, I40E_GLNVM_ULD);
1299                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1300                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1301                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1302                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1303                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1304                         break;
1305                 }
1306                 i40e_msec_delay(10);
1307         }
1308         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1309                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1310                 DEBUGOUT("wait for FW Reset complete timedout\n");
1311                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1312                 return I40E_ERR_RESET_FAILED;
1313         }
1314
1315         /* If there was a Global Reset in progress when we got here,
1316          * we don't need to do the PF Reset
1317          */
1318         if (!cnt) {
1319                 reg = rd32(hw, I40E_PFGEN_CTRL);
1320                 wr32(hw, I40E_PFGEN_CTRL,
1321                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1322                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1323                         reg = rd32(hw, I40E_PFGEN_CTRL);
1324                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1325                                 break;
1326                         i40e_msec_delay(1);
1327                 }
1328                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1329                         DEBUGOUT("PF reset polling failed to complete.\n");
1330                         return I40E_ERR_RESET_FAILED;
1331                 }
1332         }
1333
1334         i40e_clear_pxe_mode(hw);
1335
1336
1337         return I40E_SUCCESS;
1338 }
1339
1340 /**
1341  * i40e_clear_hw - clear out any left over hw state
1342  * @hw: pointer to the hw struct
1343  *
1344  * Clear queues and interrupts, typically called at init time,
1345  * but after the capabilities have been found so we know how many
1346  * queues and msix vectors have been allocated.
1347  **/
1348 void i40e_clear_hw(struct i40e_hw *hw)
1349 {
1350         u32 num_queues, base_queue;
1351         u32 num_pf_int;
1352         u32 num_vf_int;
1353         u32 num_vfs;
1354         u32 i, j;
1355         u32 val;
1356         u32 eol = 0x7ff;
1357
1358         /* get number of interrupts, queues, and vfs */
1359         val = rd32(hw, I40E_GLPCI_CNF2);
1360         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1361                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1362         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1363                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1364
1365         val = rd32(hw, I40E_PFLAN_QALLOC);
1366         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1367                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1368         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1369                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1370         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1371                 num_queues = (j - base_queue) + 1;
1372         else
1373                 num_queues = 0;
1374
1375         val = rd32(hw, I40E_PF_VT_PFALLOC);
1376         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1377                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1378         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1379                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1380         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1381                 num_vfs = (j - i) + 1;
1382         else
1383                 num_vfs = 0;
1384
1385         /* stop all the interrupts */
1386         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1387         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1388         for (i = 0; i < num_pf_int - 2; i++)
1389                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1390
1391         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1392         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1393         wr32(hw, I40E_PFINT_LNKLST0, val);
1394         for (i = 0; i < num_pf_int - 2; i++)
1395                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1396         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1397         for (i = 0; i < num_vfs; i++)
1398                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1399         for (i = 0; i < num_vf_int - 2; i++)
1400                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1401
1402         /* warn the HW of the coming Tx disables */
1403         for (i = 0; i < num_queues; i++) {
1404                 u32 abs_queue_idx = base_queue + i;
1405                 u32 reg_block = 0;
1406
1407                 if (abs_queue_idx >= 128) {
1408                         reg_block = abs_queue_idx / 128;
1409                         abs_queue_idx %= 128;
1410                 }
1411
1412                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1413                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1414                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1415                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1416
1417                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1418         }
1419         i40e_usec_delay(400);
1420
1421         /* stop all the queues */
1422         for (i = 0; i < num_queues; i++) {
1423                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1424                 wr32(hw, I40E_QTX_ENA(i), 0);
1425                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1426                 wr32(hw, I40E_QRX_ENA(i), 0);
1427         }
1428
1429         /* short wait for all queue disables to settle */
1430         i40e_usec_delay(50);
1431 }
1432
1433 /**
1434  * i40e_clear_pxe_mode - clear pxe operations mode
1435  * @hw: pointer to the hw struct
1436  *
1437  * Make sure all PXE mode settings are cleared, including things
1438  * like descriptor fetch/write-back mode.
1439  **/
1440 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1441 {
1442         if (i40e_check_asq_alive(hw))
1443                 i40e_aq_clear_pxe_mode(hw, NULL);
1444 }
1445
1446 /**
1447  * i40e_led_is_mine - helper to find matching led
1448  * @hw: pointer to the hw struct
1449  * @idx: index into GPIO registers
1450  *
1451  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1452  */
1453 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1454 {
1455         u32 gpio_val = 0;
1456         u32 port;
1457
1458         if (!hw->func_caps.led[idx])
1459                 return 0;
1460
1461         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1462         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1463                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1464
1465         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1466          * if it is not our port then ignore
1467          */
1468         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1469             (port != hw->port))
1470                 return 0;
1471
1472         return gpio_val;
1473 }
1474
1475 #define I40E_COMBINED_ACTIVITY 0xA
1476 #define I40E_FILTER_ACTIVITY 0xE
1477 #define I40E_LINK_ACTIVITY 0xC
1478 #define I40E_MAC_ACTIVITY 0xD
1479 #define I40E_LED0 22
1480
1481 /**
1482  * i40e_led_get - return current on/off mode
1483  * @hw: pointer to the hw struct
1484  *
1485  * The value returned is the 'mode' field as defined in the
1486  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1487  * values are variations of possible behaviors relating to
1488  * blink, link, and wire.
1489  **/
1490 u32 i40e_led_get(struct i40e_hw *hw)
1491 {
1492         u32 current_mode = 0;
1493         u32 mode = 0;
1494         int i;
1495
1496         /* as per the documentation GPIO 22-29 are the LED
1497          * GPIO pins named LED0..LED7
1498          */
1499         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1500                 u32 gpio_val = i40e_led_is_mine(hw, i);
1501
1502                 if (!gpio_val)
1503                         continue;
1504
1505                 /* ignore gpio LED src mode entries related to the activity
1506                  *  LEDs
1507                  */
1508                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1509                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1510                 switch (current_mode) {
1511                 case I40E_COMBINED_ACTIVITY:
1512                 case I40E_FILTER_ACTIVITY:
1513                 case I40E_MAC_ACTIVITY:
1514                         continue;
1515                 default:
1516                         break;
1517                 }
1518
1519                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1520                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1521                 break;
1522         }
1523
1524         return mode;
1525 }
1526
1527 /**
1528  * i40e_led_set - set new on/off mode
1529  * @hw: pointer to the hw struct
1530  * @mode: 0=off, 0xf=on (else see manual for mode details)
1531  * @blink: TRUE if the LED should blink when on, FALSE if steady
1532  *
1533  * if this function is used to turn on the blink it should
1534  * be used to disable the blink when restoring the original state.
1535  **/
1536 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1537 {
1538         u32 current_mode = 0;
1539         int i;
1540
1541         if (mode & 0xfffffff0)
1542                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1543
1544         /* as per the documentation GPIO 22-29 are the LED
1545          * GPIO pins named LED0..LED7
1546          */
1547         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1548                 u32 gpio_val = i40e_led_is_mine(hw, i);
1549
1550                 if (!gpio_val)
1551                         continue;
1552
1553                 /* ignore gpio LED src mode entries related to the activity
1554                  * LEDs
1555                  */
1556                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1557                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1558                 switch (current_mode) {
1559                 case I40E_COMBINED_ACTIVITY:
1560                 case I40E_FILTER_ACTIVITY:
1561                 case I40E_MAC_ACTIVITY:
1562                         continue;
1563                 default:
1564                         break;
1565                 }
1566
1567                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1568                 /* this & is a bit of paranoia, but serves as a range check */
1569                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1570                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1571
1572                 if (mode == I40E_LINK_ACTIVITY)
1573                         blink = FALSE;
1574
1575                 if (blink)
1576                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1577                 else
1578                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1579
1580                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1581                 break;
1582         }
1583 }
1584
1585 /* Admin command wrappers */
1586
1587 /**
1588  * i40e_aq_get_phy_capabilities
1589  * @hw: pointer to the hw struct
1590  * @abilities: structure for PHY capabilities to be filled
1591  * @qualified_modules: report Qualified Modules
1592  * @report_init: report init capabilities (active are default)
1593  * @cmd_details: pointer to command details structure or NULL
1594  *
1595  * Returns the various PHY abilities supported on the Port.
1596  **/
1597 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1598                         bool qualified_modules, bool report_init,
1599                         struct i40e_aq_get_phy_abilities_resp *abilities,
1600                         struct i40e_asq_cmd_details *cmd_details)
1601 {
1602         struct i40e_aq_desc desc;
1603         enum i40e_status_code status;
1604         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1605
1606         if (!abilities)
1607                 return I40E_ERR_PARAM;
1608
1609         i40e_fill_default_direct_cmd_desc(&desc,
1610                                           i40e_aqc_opc_get_phy_abilities);
1611
1612         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1613         if (abilities_size > I40E_AQ_LARGE_BUF)
1614                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1615
1616         if (qualified_modules)
1617                 desc.params.external.param0 |=
1618                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1619
1620         if (report_init)
1621                 desc.params.external.param0 |=
1622                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1623
1624         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1625                                     cmd_details);
1626
1627         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1628                 status = I40E_ERR_UNKNOWN_PHY;
1629
1630         return status;
1631 }
1632
1633 /**
1634  * i40e_aq_set_phy_config
1635  * @hw: pointer to the hw struct
1636  * @config: structure with PHY configuration to be set
1637  * @cmd_details: pointer to command details structure or NULL
1638  *
1639  * Set the various PHY configuration parameters
1640  * supported on the Port.One or more of the Set PHY config parameters may be
1641  * ignored in an MFP mode as the PF may not have the privilege to set some
1642  * of the PHY Config parameters. This status will be indicated by the
1643  * command response.
1644  **/
1645 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1646                                 struct i40e_aq_set_phy_config *config,
1647                                 struct i40e_asq_cmd_details *cmd_details)
1648 {
1649         struct i40e_aq_desc desc;
1650         struct i40e_aq_set_phy_config *cmd =
1651                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1652         enum i40e_status_code status;
1653
1654         if (!config)
1655                 return I40E_ERR_PARAM;
1656
1657         i40e_fill_default_direct_cmd_desc(&desc,
1658                                           i40e_aqc_opc_set_phy_config);
1659
1660         *cmd = *config;
1661
1662         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1663
1664         return status;
1665 }
1666
1667 /**
1668  * i40e_set_fc
1669  * @hw: pointer to the hw struct
1670  *
1671  * Set the requested flow control mode using set_phy_config.
1672  **/
1673 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1674                                   bool atomic_restart)
1675 {
1676         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1677         struct i40e_aq_get_phy_abilities_resp abilities;
1678         struct i40e_aq_set_phy_config config;
1679         enum i40e_status_code status;
1680         u8 pause_mask = 0x0;
1681
1682         *aq_failures = 0x0;
1683
1684         switch (fc_mode) {
1685         case I40E_FC_FULL:
1686                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1687                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1688                 break;
1689         case I40E_FC_RX_PAUSE:
1690                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1691                 break;
1692         case I40E_FC_TX_PAUSE:
1693                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1694                 break;
1695         default:
1696                 break;
1697         }
1698
1699         /* Get the current phy config */
1700         status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1701                                               NULL);
1702         if (status) {
1703                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1704                 return status;
1705         }
1706
1707         memset(&config, 0, sizeof(config));
1708         /* clear the old pause settings */
1709         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1710                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1711         /* set the new abilities */
1712         config.abilities |= pause_mask;
1713         /* If the abilities have changed, then set the new config */
1714         if (config.abilities != abilities.abilities) {
1715                 /* Auto restart link so settings take effect */
1716                 if (atomic_restart)
1717                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1718                 /* Copy over all the old settings */
1719                 config.phy_type = abilities.phy_type;
1720                 config.link_speed = abilities.link_speed;
1721                 config.eee_capability = abilities.eee_capability;
1722                 config.eeer = abilities.eeer_val;
1723                 config.low_power_ctrl = abilities.d3_lpan;
1724                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1725
1726                 if (status)
1727                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1728         }
1729         /* Update the link info */
1730         status = i40e_update_link_info(hw);
1731         if (status) {
1732                 /* Wait a little bit (on 40G cards it sometimes takes a really
1733                  * long time for link to come back from the atomic reset)
1734                  * and try once more
1735                  */
1736                 i40e_msec_delay(1000);
1737                 status = i40e_update_link_info(hw);
1738         }
1739         if (status)
1740                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1741
1742         return status;
1743 }
1744
1745 /**
1746  * i40e_aq_set_mac_config
1747  * @hw: pointer to the hw struct
1748  * @max_frame_size: Maximum Frame Size to be supported by the port
1749  * @crc_en: Tell HW to append a CRC to outgoing frames
1750  * @pacing: Pacing configurations
1751  * @cmd_details: pointer to command details structure or NULL
1752  *
1753  * Configure MAC settings for frame size, jumbo frame support and the
1754  * addition of a CRC by the hardware.
1755  **/
1756 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1757                                 u16 max_frame_size,
1758                                 bool crc_en, u16 pacing,
1759                                 struct i40e_asq_cmd_details *cmd_details)
1760 {
1761         struct i40e_aq_desc desc;
1762         struct i40e_aq_set_mac_config *cmd =
1763                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1764         enum i40e_status_code status;
1765
1766         if (max_frame_size == 0)
1767                 return I40E_ERR_PARAM;
1768
1769         i40e_fill_default_direct_cmd_desc(&desc,
1770                                           i40e_aqc_opc_set_mac_config);
1771
1772         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1773         cmd->params = ((u8)pacing & 0x0F) << 3;
1774         if (crc_en)
1775                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1776
1777         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1778
1779         return status;
1780 }
1781
1782 /**
1783  * i40e_aq_clear_pxe_mode
1784  * @hw: pointer to the hw struct
1785  * @cmd_details: pointer to command details structure or NULL
1786  *
1787  * Tell the firmware that the driver is taking over from PXE
1788  **/
1789 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1790                         struct i40e_asq_cmd_details *cmd_details)
1791 {
1792         enum i40e_status_code status;
1793         struct i40e_aq_desc desc;
1794         struct i40e_aqc_clear_pxe *cmd =
1795                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1796
1797         i40e_fill_default_direct_cmd_desc(&desc,
1798                                           i40e_aqc_opc_clear_pxe_mode);
1799
1800         cmd->rx_cnt = 0x2;
1801
1802         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1803
1804         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1805
1806         return status;
1807 }
1808
1809 /**
1810  * i40e_aq_set_link_restart_an
1811  * @hw: pointer to the hw struct
1812  * @enable_link: if TRUE: enable link, if FALSE: disable link
1813  * @cmd_details: pointer to command details structure or NULL
1814  *
1815  * Sets up the link and restarts the Auto-Negotiation over the link.
1816  **/
1817 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1818                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1819 {
1820         struct i40e_aq_desc desc;
1821         struct i40e_aqc_set_link_restart_an *cmd =
1822                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1823         enum i40e_status_code status;
1824
1825         i40e_fill_default_direct_cmd_desc(&desc,
1826                                           i40e_aqc_opc_set_link_restart_an);
1827
1828         cmd->command = I40E_AQ_PHY_RESTART_AN;
1829         if (enable_link)
1830                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1831         else
1832                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1833
1834         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1835
1836         return status;
1837 }
1838
1839 /**
1840  * i40e_aq_get_link_info
1841  * @hw: pointer to the hw struct
1842  * @enable_lse: enable/disable LinkStatusEvent reporting
1843  * @link: pointer to link status structure - optional
1844  * @cmd_details: pointer to command details structure or NULL
1845  *
1846  * Returns the link status of the adapter.
1847  **/
1848 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1849                                 bool enable_lse, struct i40e_link_status *link,
1850                                 struct i40e_asq_cmd_details *cmd_details)
1851 {
1852         struct i40e_aq_desc desc;
1853         struct i40e_aqc_get_link_status *resp =
1854                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1855         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1856         enum i40e_status_code status;
1857         bool tx_pause, rx_pause;
1858         u16 command_flags;
1859
1860         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1861
1862         if (enable_lse)
1863                 command_flags = I40E_AQ_LSE_ENABLE;
1864         else
1865                 command_flags = I40E_AQ_LSE_DISABLE;
1866         resp->command_flags = CPU_TO_LE16(command_flags);
1867
1868         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1869
1870         if (status != I40E_SUCCESS)
1871                 goto aq_get_link_info_exit;
1872
1873         /* save off old link status information */
1874         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1875                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1876
1877         /* update link status */
1878         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1879         hw->phy.media_type = i40e_get_media_type(hw);
1880         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1881         hw_link_info->link_info = resp->link_info;
1882         hw_link_info->an_info = resp->an_info;
1883         hw_link_info->ext_info = resp->ext_info;
1884         hw_link_info->loopback = resp->loopback;
1885         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1886         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1887
1888         /* update fc info */
1889         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1890         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1891         if (tx_pause & rx_pause)
1892                 hw->fc.current_mode = I40E_FC_FULL;
1893         else if (tx_pause)
1894                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1895         else if (rx_pause)
1896                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1897         else
1898                 hw->fc.current_mode = I40E_FC_NONE;
1899
1900         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1901                 hw_link_info->crc_enable = TRUE;
1902         else
1903                 hw_link_info->crc_enable = FALSE;
1904
1905         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1906                 hw_link_info->lse_enable = TRUE;
1907         else
1908                 hw_link_info->lse_enable = FALSE;
1909
1910         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1911              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1912                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1913
1914         /* save link status information */
1915         if (link)
1916                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1917                             I40E_NONDMA_TO_NONDMA);
1918
1919         /* flag cleared so helper functions don't call AQ again */
1920         hw->phy.get_link_info = FALSE;
1921
1922 aq_get_link_info_exit:
1923         return status;
1924 }
1925
1926 /**
1927  * i40e_aq_set_phy_int_mask
1928  * @hw: pointer to the hw struct
1929  * @mask: interrupt mask to be set
1930  * @cmd_details: pointer to command details structure or NULL
1931  *
1932  * Set link interrupt mask.
1933  **/
1934 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1935                                 u16 mask,
1936                                 struct i40e_asq_cmd_details *cmd_details)
1937 {
1938         struct i40e_aq_desc desc;
1939         struct i40e_aqc_set_phy_int_mask *cmd =
1940                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1941         enum i40e_status_code status;
1942
1943         i40e_fill_default_direct_cmd_desc(&desc,
1944                                           i40e_aqc_opc_set_phy_int_mask);
1945
1946         cmd->event_mask = CPU_TO_LE16(mask);
1947
1948         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1949
1950         return status;
1951 }
1952
1953 /**
1954  * i40e_aq_get_local_advt_reg
1955  * @hw: pointer to the hw struct
1956  * @advt_reg: local AN advertisement register value
1957  * @cmd_details: pointer to command details structure or NULL
1958  *
1959  * Get the Local AN advertisement register value.
1960  **/
1961 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1962                                 u64 *advt_reg,
1963                                 struct i40e_asq_cmd_details *cmd_details)
1964 {
1965         struct i40e_aq_desc desc;
1966         struct i40e_aqc_an_advt_reg *resp =
1967                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1968         enum i40e_status_code status;
1969
1970         i40e_fill_default_direct_cmd_desc(&desc,
1971                                           i40e_aqc_opc_get_local_advt_reg);
1972
1973         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1974
1975         if (status != I40E_SUCCESS)
1976                 goto aq_get_local_advt_reg_exit;
1977
1978         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1979         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1980
1981 aq_get_local_advt_reg_exit:
1982         return status;
1983 }
1984
1985 /**
1986  * i40e_aq_set_local_advt_reg
1987  * @hw: pointer to the hw struct
1988  * @advt_reg: local AN advertisement register value
1989  * @cmd_details: pointer to command details structure or NULL
1990  *
1991  * Get the Local AN advertisement register value.
1992  **/
1993 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1994                                 u64 advt_reg,
1995                                 struct i40e_asq_cmd_details *cmd_details)
1996 {
1997         struct i40e_aq_desc desc;
1998         struct i40e_aqc_an_advt_reg *cmd =
1999                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2000         enum i40e_status_code status;
2001
2002         i40e_fill_default_direct_cmd_desc(&desc,
2003                                           i40e_aqc_opc_get_local_advt_reg);
2004
2005         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2006         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2007
2008         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2009
2010         return status;
2011 }
2012
2013 /**
2014  * i40e_aq_get_partner_advt
2015  * @hw: pointer to the hw struct
2016  * @advt_reg: AN partner advertisement register value
2017  * @cmd_details: pointer to command details structure or NULL
2018  *
2019  * Get the link partner AN advertisement register value.
2020  **/
2021 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2022                                 u64 *advt_reg,
2023                                 struct i40e_asq_cmd_details *cmd_details)
2024 {
2025         struct i40e_aq_desc desc;
2026         struct i40e_aqc_an_advt_reg *resp =
2027                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2028         enum i40e_status_code status;
2029
2030         i40e_fill_default_direct_cmd_desc(&desc,
2031                                           i40e_aqc_opc_get_partner_advt);
2032
2033         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2034
2035         if (status != I40E_SUCCESS)
2036                 goto aq_get_partner_advt_exit;
2037
2038         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2039         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2040
2041 aq_get_partner_advt_exit:
2042         return status;
2043 }
2044
2045 /**
2046  * i40e_aq_set_lb_modes
2047  * @hw: pointer to the hw struct
2048  * @lb_modes: loopback mode to be set
2049  * @cmd_details: pointer to command details structure or NULL
2050  *
2051  * Sets loopback modes.
2052  **/
2053 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2054                                 u16 lb_modes,
2055                                 struct i40e_asq_cmd_details *cmd_details)
2056 {
2057         struct i40e_aq_desc desc;
2058         struct i40e_aqc_set_lb_mode *cmd =
2059                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2060         enum i40e_status_code status;
2061
2062         i40e_fill_default_direct_cmd_desc(&desc,
2063                                           i40e_aqc_opc_set_lb_modes);
2064
2065         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2066
2067         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2068
2069         return status;
2070 }
2071
2072 /**
2073  * i40e_aq_set_phy_debug
2074  * @hw: pointer to the hw struct
2075  * @cmd_flags: debug command flags
2076  * @cmd_details: pointer to command details structure or NULL
2077  *
2078  * Reset the external PHY.
2079  **/
2080 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2081                                 struct i40e_asq_cmd_details *cmd_details)
2082 {
2083         struct i40e_aq_desc desc;
2084         struct i40e_aqc_set_phy_debug *cmd =
2085                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2086         enum i40e_status_code status;
2087
2088         i40e_fill_default_direct_cmd_desc(&desc,
2089                                           i40e_aqc_opc_set_phy_debug);
2090
2091         cmd->command_flags = cmd_flags;
2092
2093         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2094
2095         return status;
2096 }
2097
2098 /**
2099  * i40e_aq_add_vsi
2100  * @hw: pointer to the hw struct
2101  * @vsi_ctx: pointer to a vsi context struct
2102  * @cmd_details: pointer to command details structure or NULL
2103  *
2104  * Add a VSI context to the hardware.
2105 **/
2106 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2107                                 struct i40e_vsi_context *vsi_ctx,
2108                                 struct i40e_asq_cmd_details *cmd_details)
2109 {
2110         struct i40e_aq_desc desc;
2111         struct i40e_aqc_add_get_update_vsi *cmd =
2112                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2113         struct i40e_aqc_add_get_update_vsi_completion *resp =
2114                 (struct i40e_aqc_add_get_update_vsi_completion *)
2115                 &desc.params.raw;
2116         enum i40e_status_code status;
2117
2118         i40e_fill_default_direct_cmd_desc(&desc,
2119                                           i40e_aqc_opc_add_vsi);
2120
2121         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2122         cmd->connection_type = vsi_ctx->connection_type;
2123         cmd->vf_id = vsi_ctx->vf_num;
2124         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2125
2126         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2127
2128         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2129                                     sizeof(vsi_ctx->info), cmd_details);
2130
2131         if (status != I40E_SUCCESS)
2132                 goto aq_add_vsi_exit;
2133
2134         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2135         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2136         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2137         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2138
2139 aq_add_vsi_exit:
2140         return status;
2141 }
2142
2143 /**
2144  * i40e_aq_set_default_vsi
2145  * @hw: pointer to the hw struct
2146  * @seid: vsi number
2147  * @cmd_details: pointer to command details structure or NULL
2148  **/
2149 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2150                                 u16 seid,
2151                                 struct i40e_asq_cmd_details *cmd_details)
2152 {
2153         struct i40e_aq_desc desc;
2154         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2155                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2156                 &desc.params.raw;
2157         enum i40e_status_code status;
2158
2159         i40e_fill_default_direct_cmd_desc(&desc,
2160                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2161
2162         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2163         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2164         cmd->seid = CPU_TO_LE16(seid);
2165
2166         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2167
2168         return status;
2169 }
2170
2171 /**
2172  * i40e_aq_set_vsi_unicast_promiscuous
2173  * @hw: pointer to the hw struct
2174  * @seid: vsi number
2175  * @set: set unicast promiscuous enable/disable
2176  * @cmd_details: pointer to command details structure or NULL
2177  **/
2178 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2179                                 u16 seid, bool set,
2180                                 struct i40e_asq_cmd_details *cmd_details)
2181 {
2182         struct i40e_aq_desc desc;
2183         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2184                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2185         enum i40e_status_code status;
2186         u16 flags = 0;
2187
2188         i40e_fill_default_direct_cmd_desc(&desc,
2189                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2190
2191         if (set)
2192                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2193
2194         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2195
2196         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2197
2198         cmd->seid = CPU_TO_LE16(seid);
2199         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2200
2201         return status;
2202 }
2203
2204 /**
2205  * i40e_aq_set_vsi_multicast_promiscuous
2206  * @hw: pointer to the hw struct
2207  * @seid: vsi number
2208  * @set: set multicast promiscuous enable/disable
2209  * @cmd_details: pointer to command details structure or NULL
2210  **/
2211 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2212                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2213 {
2214         struct i40e_aq_desc desc;
2215         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2216                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2217         enum i40e_status_code status;
2218         u16 flags = 0;
2219
2220         i40e_fill_default_direct_cmd_desc(&desc,
2221                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2222
2223         if (set)
2224                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2225
2226         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2227
2228         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2229
2230         cmd->seid = CPU_TO_LE16(seid);
2231         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2232
2233         return status;
2234 }
2235
2236 /**
2237  * i40e_aq_set_vsi_mc_promisc_on_vlan
2238  * @hw: pointer to the hw struct
2239  * @seid: vsi number
2240  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2241  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2242  * @cmd_details: pointer to command details structure or NULL
2243  **/
2244 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2245                                 u16 seid, bool enable, u16 vid,
2246                                 struct i40e_asq_cmd_details *cmd_details)
2247 {
2248         struct i40e_aq_desc desc;
2249         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2250                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2251         enum i40e_status_code status;
2252         u16 flags = 0;
2253
2254         i40e_fill_default_direct_cmd_desc(&desc,
2255                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2256
2257         if (enable)
2258                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2259
2260         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2261         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2262         cmd->seid = CPU_TO_LE16(seid);
2263         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2264
2265         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2266
2267         return status;
2268 }
2269
2270 /**
2271  * i40e_aq_set_vsi_uc_promisc_on_vlan
2272  * @hw: pointer to the hw struct
2273  * @seid: vsi number
2274  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2275  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2276  * @cmd_details: pointer to command details structure or NULL
2277  **/
2278 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2279                                 u16 seid, bool enable, u16 vid,
2280                                 struct i40e_asq_cmd_details *cmd_details)
2281 {
2282         struct i40e_aq_desc desc;
2283         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2284                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2285         enum i40e_status_code status;
2286         u16 flags = 0;
2287
2288         i40e_fill_default_direct_cmd_desc(&desc,
2289                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2290
2291         if (enable)
2292                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2293
2294         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2295         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2296         cmd->seid = CPU_TO_LE16(seid);
2297         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2298
2299         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2300
2301         return status;
2302 }
2303
2304 /**
2305  * i40e_aq_set_vsi_broadcast
2306  * @hw: pointer to the hw struct
2307  * @seid: vsi number
2308  * @set_filter: TRUE to set filter, FALSE to clear filter
2309  * @cmd_details: pointer to command details structure or NULL
2310  *
2311  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2312  **/
2313 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2314                                 u16 seid, bool set_filter,
2315                                 struct i40e_asq_cmd_details *cmd_details)
2316 {
2317         struct i40e_aq_desc desc;
2318         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2319                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2320         enum i40e_status_code status;
2321
2322         i40e_fill_default_direct_cmd_desc(&desc,
2323                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2324
2325         if (set_filter)
2326                 cmd->promiscuous_flags
2327                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2328         else
2329                 cmd->promiscuous_flags
2330                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2331
2332         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2333         cmd->seid = CPU_TO_LE16(seid);
2334         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2335
2336         return status;
2337 }
2338
2339 /**
2340  * i40e_get_vsi_params - get VSI configuration info
2341  * @hw: pointer to the hw struct
2342  * @vsi_ctx: pointer to a vsi context struct
2343  * @cmd_details: pointer to command details structure or NULL
2344  **/
2345 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2346                                 struct i40e_vsi_context *vsi_ctx,
2347                                 struct i40e_asq_cmd_details *cmd_details)
2348 {
2349         struct i40e_aq_desc desc;
2350         struct i40e_aqc_add_get_update_vsi *cmd =
2351                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2352         struct i40e_aqc_add_get_update_vsi_completion *resp =
2353                 (struct i40e_aqc_add_get_update_vsi_completion *)
2354                 &desc.params.raw;
2355         enum i40e_status_code status;
2356
2357         i40e_fill_default_direct_cmd_desc(&desc,
2358                                           i40e_aqc_opc_get_vsi_parameters);
2359
2360         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2361
2362         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2363
2364         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2365                                     sizeof(vsi_ctx->info), NULL);
2366
2367         if (status != I40E_SUCCESS)
2368                 goto aq_get_vsi_params_exit;
2369
2370         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2371         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2372         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2373         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2374
2375 aq_get_vsi_params_exit:
2376         return status;
2377 }
2378
2379 /**
2380  * i40e_aq_update_vsi_params
2381  * @hw: pointer to the hw struct
2382  * @vsi_ctx: pointer to a vsi context struct
2383  * @cmd_details: pointer to command details structure or NULL
2384  *
2385  * Update a VSI context.
2386  **/
2387 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2388                                 struct i40e_vsi_context *vsi_ctx,
2389                                 struct i40e_asq_cmd_details *cmd_details)
2390 {
2391         struct i40e_aq_desc desc;
2392         struct i40e_aqc_add_get_update_vsi *cmd =
2393                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2394         enum i40e_status_code status;
2395
2396         i40e_fill_default_direct_cmd_desc(&desc,
2397                                           i40e_aqc_opc_update_vsi_parameters);
2398         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2399
2400         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2401
2402         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2403                                     sizeof(vsi_ctx->info), cmd_details);
2404
2405         return status;
2406 }
2407
2408 /**
2409  * i40e_aq_get_switch_config
2410  * @hw: pointer to the hardware structure
2411  * @buf: pointer to the result buffer
2412  * @buf_size: length of input buffer
2413  * @start_seid: seid to start for the report, 0 == beginning
2414  * @cmd_details: pointer to command details structure or NULL
2415  *
2416  * Fill the buf with switch configuration returned from AdminQ command
2417  **/
2418 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2419                                 struct i40e_aqc_get_switch_config_resp *buf,
2420                                 u16 buf_size, u16 *start_seid,
2421                                 struct i40e_asq_cmd_details *cmd_details)
2422 {
2423         struct i40e_aq_desc desc;
2424         struct i40e_aqc_switch_seid *scfg =
2425                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2426         enum i40e_status_code status;
2427
2428         i40e_fill_default_direct_cmd_desc(&desc,
2429                                           i40e_aqc_opc_get_switch_config);
2430         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2431         if (buf_size > I40E_AQ_LARGE_BUF)
2432                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2433         scfg->seid = CPU_TO_LE16(*start_seid);
2434
2435         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2436         *start_seid = LE16_TO_CPU(scfg->seid);
2437
2438         return status;
2439 }
2440
2441 /**
2442  * i40e_aq_get_firmware_version
2443  * @hw: pointer to the hw struct
2444  * @fw_major_version: firmware major version
2445  * @fw_minor_version: firmware minor version
2446  * @fw_build: firmware build number
2447  * @api_major_version: major queue version
2448  * @api_minor_version: minor queue version
2449  * @cmd_details: pointer to command details structure or NULL
2450  *
2451  * Get the firmware version from the admin queue commands
2452  **/
2453 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2454                                 u16 *fw_major_version, u16 *fw_minor_version,
2455                                 u32 *fw_build,
2456                                 u16 *api_major_version, u16 *api_minor_version,
2457                                 struct i40e_asq_cmd_details *cmd_details)
2458 {
2459         struct i40e_aq_desc desc;
2460         struct i40e_aqc_get_version *resp =
2461                 (struct i40e_aqc_get_version *)&desc.params.raw;
2462         enum i40e_status_code status;
2463
2464         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2465
2466         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2467
2468         if (status == I40E_SUCCESS) {
2469                 if (fw_major_version != NULL)
2470                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2471                 if (fw_minor_version != NULL)
2472                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2473                 if (fw_build != NULL)
2474                         *fw_build = LE32_TO_CPU(resp->fw_build);
2475                 if (api_major_version != NULL)
2476                         *api_major_version = LE16_TO_CPU(resp->api_major);
2477                 if (api_minor_version != NULL)
2478                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2479
2480                 /* A workaround to fix the API version in SW */
2481                 if (api_major_version && api_minor_version &&
2482                     fw_major_version && fw_minor_version &&
2483                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2484                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2485                      (*fw_major_version > 4)))
2486                         *api_minor_version = 2;
2487         }
2488
2489         return status;
2490 }
2491
2492 /**
2493  * i40e_aq_send_driver_version
2494  * @hw: pointer to the hw struct
2495  * @dv: driver's major, minor version
2496  * @cmd_details: pointer to command details structure or NULL
2497  *
2498  * Send the driver version to the firmware
2499  **/
2500 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2501                                 struct i40e_driver_version *dv,
2502                                 struct i40e_asq_cmd_details *cmd_details)
2503 {
2504         struct i40e_aq_desc desc;
2505         struct i40e_aqc_driver_version *cmd =
2506                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2507         enum i40e_status_code status;
2508         u16 len;
2509
2510         if (dv == NULL)
2511                 return I40E_ERR_PARAM;
2512
2513         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2514
2515         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2516         cmd->driver_major_ver = dv->major_version;
2517         cmd->driver_minor_ver = dv->minor_version;
2518         cmd->driver_build_ver = dv->build_version;
2519         cmd->driver_subbuild_ver = dv->subbuild_version;
2520
2521         len = 0;
2522         while (len < sizeof(dv->driver_string) &&
2523                (dv->driver_string[len] < 0x80) &&
2524                dv->driver_string[len])
2525                 len++;
2526         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2527                                        len, cmd_details);
2528
2529         return status;
2530 }
2531
2532 /**
2533  * i40e_get_link_status - get status of the HW network link
2534  * @hw: pointer to the hw struct
2535  * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown)
2536  *
2537  * Variable link_up TRUE if link is up, FALSE if link is down.
2538  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2539  *
2540  * Side effect: LinkStatusEvent reporting becomes enabled
2541  **/
2542 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2543 {
2544         enum i40e_status_code status = I40E_SUCCESS;
2545
2546         if (hw->phy.get_link_info) {
2547                 status = i40e_update_link_info(hw);
2548
2549                 if (status != I40E_SUCCESS)
2550                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2551                                    status);
2552         }
2553
2554         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2555
2556         return status;
2557 }
2558
2559 /**
2560  * i40e_updatelink_status - update status of the HW network link
2561  * @hw: pointer to the hw struct
2562  **/
2563 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2564 {
2565         struct i40e_aq_get_phy_abilities_resp abilities;
2566         enum i40e_status_code status = I40E_SUCCESS;
2567
2568         status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2569         if (status)
2570                 return status;
2571
2572         status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
2573                                               NULL);
2574         if (status)
2575                 return status;
2576
2577         memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2578                 sizeof(hw->phy.link_info.module_type));
2579
2580         return status;
2581 }
2582
2583
2584 /**
2585  * i40e_get_link_speed
2586  * @hw: pointer to the hw struct
2587  *
2588  * Returns the link speed of the adapter.
2589  **/
2590 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2591 {
2592         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2593         enum i40e_status_code status = I40E_SUCCESS;
2594
2595         if (hw->phy.get_link_info) {
2596                 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2597
2598                 if (status != I40E_SUCCESS)
2599                         goto i40e_link_speed_exit;
2600         }
2601
2602         speed = hw->phy.link_info.link_speed;
2603
2604 i40e_link_speed_exit:
2605         return speed;
2606 }
2607
2608 /**
2609  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2610  * @hw: pointer to the hw struct
2611  * @uplink_seid: the MAC or other gizmo SEID
2612  * @downlink_seid: the VSI SEID
2613  * @enabled_tc: bitmap of TCs to be enabled
2614  * @default_port: TRUE for default port VSI, FALSE for control port
2615  * @enable_l2_filtering: TRUE to add L2 filter table rules to regular forwarding rules for cloud support
2616  * @veb_seid: pointer to where to put the resulting VEB SEID
2617  * @cmd_details: pointer to command details structure or NULL
2618  *
2619  * This asks the FW to add a VEB between the uplink and downlink
2620  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2621  **/
2622 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2623                                 u16 downlink_seid, u8 enabled_tc,
2624                                 bool default_port, bool enable_l2_filtering,
2625                                 u16 *veb_seid,
2626                                 struct i40e_asq_cmd_details *cmd_details)
2627 {
2628         struct i40e_aq_desc desc;
2629         struct i40e_aqc_add_veb *cmd =
2630                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2631         struct i40e_aqc_add_veb_completion *resp =
2632                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2633         enum i40e_status_code status;
2634         u16 veb_flags = 0;
2635
2636         /* SEIDs need to either both be set or both be 0 for floating VEB */
2637         if (!!uplink_seid != !!downlink_seid)
2638                 return I40E_ERR_PARAM;
2639
2640         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2641
2642         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2643         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2644         cmd->enable_tcs = enabled_tc;
2645         if (!uplink_seid)
2646                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2647         if (default_port)
2648                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2649         else
2650                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2651
2652         if (enable_l2_filtering)
2653                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2654
2655         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2656
2657         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2658
2659         if (!status && veb_seid)
2660                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2661
2662         return status;
2663 }
2664
2665 /**
2666  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2667  * @hw: pointer to the hw struct
2668  * @veb_seid: the SEID of the VEB to query
2669  * @switch_id: the uplink switch id
2670  * @floating: set to TRUE if the VEB is floating
2671  * @statistic_index: index of the stats counter block for this VEB
2672  * @vebs_used: number of VEB's used by function
2673  * @vebs_free: total VEB's not reserved by any function
2674  * @cmd_details: pointer to command details structure or NULL
2675  *
2676  * This retrieves the parameters for a particular VEB, specified by
2677  * uplink_seid, and returns them to the caller.
2678  **/
2679 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2680                                 u16 veb_seid, u16 *switch_id,
2681                                 bool *floating, u16 *statistic_index,
2682                                 u16 *vebs_used, u16 *vebs_free,
2683                                 struct i40e_asq_cmd_details *cmd_details)
2684 {
2685         struct i40e_aq_desc desc;
2686         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2687                 (struct i40e_aqc_get_veb_parameters_completion *)
2688                 &desc.params.raw;
2689         enum i40e_status_code status;
2690
2691         if (veb_seid == 0)
2692                 return I40E_ERR_PARAM;
2693
2694         i40e_fill_default_direct_cmd_desc(&desc,
2695                                           i40e_aqc_opc_get_veb_parameters);
2696         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2697
2698         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2699         if (status)
2700                 goto get_veb_exit;
2701
2702         if (switch_id)
2703                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2704         if (statistic_index)
2705                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2706         if (vebs_used)
2707                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2708         if (vebs_free)
2709                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2710         if (floating) {
2711                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2712
2713                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2714                         *floating = TRUE;
2715                 else
2716                         *floating = FALSE;
2717         }
2718
2719 get_veb_exit:
2720         return status;
2721 }
2722
2723 /**
2724  * i40e_aq_add_macvlan
2725  * @hw: pointer to the hw struct
2726  * @seid: VSI for the mac address
2727  * @mv_list: list of macvlans to be added
2728  * @count: length of the list
2729  * @cmd_details: pointer to command details structure or NULL
2730  *
2731  * Add MAC/VLAN addresses to the HW filtering
2732  **/
2733 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2734                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2735                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2736 {
2737         struct i40e_aq_desc desc;
2738         struct i40e_aqc_macvlan *cmd =
2739                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2740         enum i40e_status_code status;
2741         u16 buf_size;
2742
2743         if (count == 0 || !mv_list || !hw)
2744                 return I40E_ERR_PARAM;
2745
2746         buf_size = count * sizeof(*mv_list);
2747
2748         /* prep the rest of the request */
2749         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2750         cmd->num_addresses = CPU_TO_LE16(count);
2751         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2752         cmd->seid[1] = 0;
2753         cmd->seid[2] = 0;
2754
2755         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2756         if (buf_size > I40E_AQ_LARGE_BUF)
2757                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2758
2759         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2760                                     cmd_details);
2761
2762         return status;
2763 }
2764
2765 /**
2766  * i40e_aq_remove_macvlan
2767  * @hw: pointer to the hw struct
2768  * @seid: VSI for the mac address
2769  * @mv_list: list of macvlans to be removed
2770  * @count: length of the list
2771  * @cmd_details: pointer to command details structure or NULL
2772  *
2773  * Remove MAC/VLAN addresses from the HW filtering
2774  **/
2775 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2776                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2777                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2778 {
2779         struct i40e_aq_desc desc;
2780         struct i40e_aqc_macvlan *cmd =
2781                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2782         enum i40e_status_code status;
2783         u16 buf_size;
2784
2785         if (count == 0 || !mv_list || !hw)
2786                 return I40E_ERR_PARAM;
2787
2788         buf_size = count * sizeof(*mv_list);
2789
2790         /* prep the rest of the request */
2791         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2792         cmd->num_addresses = CPU_TO_LE16(count);
2793         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2794         cmd->seid[1] = 0;
2795         cmd->seid[2] = 0;
2796
2797         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2798         if (buf_size > I40E_AQ_LARGE_BUF)
2799                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2800
2801         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2802                                        cmd_details);
2803
2804         return status;
2805 }
2806
2807 /**
2808  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2809  * @hw: pointer to the hw struct
2810  * @seid: VSI for the vlan filters
2811  * @v_list: list of vlan filters to be added
2812  * @count: length of the list
2813  * @cmd_details: pointer to command details structure or NULL
2814  **/
2815 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2816                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2817                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2818 {
2819         struct i40e_aq_desc desc;
2820         struct i40e_aqc_macvlan *cmd =
2821                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2822         enum i40e_status_code status;
2823         u16 buf_size;
2824
2825         if (count == 0 || !v_list || !hw)
2826                 return I40E_ERR_PARAM;
2827
2828         buf_size = count * sizeof(*v_list);
2829
2830         /* prep the rest of the request */
2831         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2832         cmd->num_addresses = CPU_TO_LE16(count);
2833         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2834         cmd->seid[1] = 0;
2835         cmd->seid[2] = 0;
2836
2837         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2838         if (buf_size > I40E_AQ_LARGE_BUF)
2839                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2840
2841         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2842                                        cmd_details);
2843
2844         return status;
2845 }
2846
2847 /**
2848  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2849  * @hw: pointer to the hw struct
2850  * @seid: VSI for the vlan filters
2851  * @v_list: list of macvlans to be removed
2852  * @count: length of the list
2853  * @cmd_details: pointer to command details structure or NULL
2854  **/
2855 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2856                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
2857                         u8 count, struct i40e_asq_cmd_details *cmd_details)
2858 {
2859         struct i40e_aq_desc desc;
2860         struct i40e_aqc_macvlan *cmd =
2861                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2862         enum i40e_status_code status;
2863         u16 buf_size;
2864
2865         if (count == 0 || !v_list || !hw)
2866                 return I40E_ERR_PARAM;
2867
2868         buf_size = count * sizeof(*v_list);
2869
2870         /* prep the rest of the request */
2871         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2872         cmd->num_addresses = CPU_TO_LE16(count);
2873         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2874         cmd->seid[1] = 0;
2875         cmd->seid[2] = 0;
2876
2877         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2878         if (buf_size > I40E_AQ_LARGE_BUF)
2879                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2880
2881         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2882                                        cmd_details);
2883
2884         return status;
2885 }
2886
2887 /**
2888  * i40e_aq_send_msg_to_vf
2889  * @hw: pointer to the hardware structure
2890  * @vfid: vf id to send msg
2891  * @v_opcode: opcodes for VF-PF communication
2892  * @v_retval: return error code
2893  * @msg: pointer to the msg buffer
2894  * @msglen: msg length
2895  * @cmd_details: pointer to command details
2896  *
2897  * send msg to vf
2898  **/
2899 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2900                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2901                                 struct i40e_asq_cmd_details *cmd_details)
2902 {
2903         struct i40e_aq_desc desc;
2904         struct i40e_aqc_pf_vf_message *cmd =
2905                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2906         enum i40e_status_code status;
2907
2908         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2909         cmd->id = CPU_TO_LE32(vfid);
2910         desc.cookie_high = CPU_TO_LE32(v_opcode);
2911         desc.cookie_low = CPU_TO_LE32(v_retval);
2912         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2913         if (msglen) {
2914                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2915                                                 I40E_AQ_FLAG_RD));
2916                 if (msglen > I40E_AQ_LARGE_BUF)
2917                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2918                 desc.datalen = CPU_TO_LE16(msglen);
2919         }
2920         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2921
2922         return status;
2923 }
2924
2925 /**
2926  * i40e_aq_debug_read_register
2927  * @hw: pointer to the hw struct
2928  * @reg_addr: register address
2929  * @reg_val: register value
2930  * @cmd_details: pointer to command details structure or NULL
2931  *
2932  * Read the register using the admin queue commands
2933  **/
2934 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2935                                 u32 reg_addr, u64 *reg_val,
2936                                 struct i40e_asq_cmd_details *cmd_details)
2937 {
2938         struct i40e_aq_desc desc;
2939         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2940                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2941         enum i40e_status_code status;
2942
2943         if (reg_val == NULL)
2944                 return I40E_ERR_PARAM;
2945
2946         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2947
2948         cmd_resp->address = CPU_TO_LE32(reg_addr);
2949
2950         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2951
2952         if (status == I40E_SUCCESS) {
2953                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2954                            (u64)LE32_TO_CPU(cmd_resp->value_low);
2955         }
2956
2957         return status;
2958 }
2959
2960 /**
2961  * i40e_aq_debug_write_register
2962  * @hw: pointer to the hw struct
2963  * @reg_addr: register address
2964  * @reg_val: register value
2965  * @cmd_details: pointer to command details structure or NULL
2966  *
2967  * Write to a register using the admin queue commands
2968  **/
2969 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2970                                 u32 reg_addr, u64 reg_val,
2971                                 struct i40e_asq_cmd_details *cmd_details)
2972 {
2973         struct i40e_aq_desc desc;
2974         struct i40e_aqc_debug_reg_read_write *cmd =
2975                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2976         enum i40e_status_code status;
2977
2978         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2979
2980         cmd->address = CPU_TO_LE32(reg_addr);
2981         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2982         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2983
2984         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2985
2986         return status;
2987 }
2988
2989 /**
2990  * i40e_aq_get_hmc_resource_profile
2991  * @hw: pointer to the hw struct
2992  * @profile: type of profile the HMC is to be set as
2993  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2994  * @cmd_details: pointer to command details structure or NULL
2995  *
2996  * query the HMC profile of the device.
2997  **/
2998 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2999                                 enum i40e_aq_hmc_profile *profile,
3000                                 u8 *pe_vf_enabled_count,
3001                                 struct i40e_asq_cmd_details *cmd_details)
3002 {
3003         struct i40e_aq_desc desc;
3004         struct i40e_aq_get_set_hmc_resource_profile *resp =
3005                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3006         enum i40e_status_code status;
3007
3008         i40e_fill_default_direct_cmd_desc(&desc,
3009                                 i40e_aqc_opc_query_hmc_resource_profile);
3010         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3011
3012         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3013                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3014         *pe_vf_enabled_count = resp->pe_vf_enabled &
3015                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3016
3017         return status;
3018 }
3019
3020 /**
3021  * i40e_aq_set_hmc_resource_profile
3022  * @hw: pointer to the hw struct
3023  * @profile: type of profile the HMC is to be set as
3024  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3025  * @cmd_details: pointer to command details structure or NULL
3026  *
3027  * set the HMC profile of the device.
3028  **/
3029 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3030                                 enum i40e_aq_hmc_profile profile,
3031                                 u8 pe_vf_enabled_count,
3032                                 struct i40e_asq_cmd_details *cmd_details)
3033 {
3034         struct i40e_aq_desc desc;
3035         struct i40e_aq_get_set_hmc_resource_profile *cmd =
3036                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3037         enum i40e_status_code status;
3038
3039         i40e_fill_default_direct_cmd_desc(&desc,
3040                                         i40e_aqc_opc_set_hmc_resource_profile);
3041
3042         cmd->pm_profile = (u8)profile;
3043         cmd->pe_vf_enabled = pe_vf_enabled_count;
3044
3045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3046
3047         return status;
3048 }
3049
3050 /**
3051  * i40e_aq_request_resource
3052  * @hw: pointer to the hw struct
3053  * @resource: resource id
3054  * @access: access type
3055  * @sdp_number: resource number
3056  * @timeout: the maximum time in ms that the driver may hold the resource
3057  * @cmd_details: pointer to command details structure or NULL
3058  *
3059  * requests common resource using the admin queue commands
3060  **/
3061 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3062                                 enum i40e_aq_resources_ids resource,
3063                                 enum i40e_aq_resource_access_type access,
3064                                 u8 sdp_number, u64 *timeout,
3065                                 struct i40e_asq_cmd_details *cmd_details)
3066 {
3067         struct i40e_aq_desc desc;
3068         struct i40e_aqc_request_resource *cmd_resp =
3069                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3070         enum i40e_status_code status;
3071
3072         DEBUGFUNC("i40e_aq_request_resource");
3073
3074         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3075
3076         cmd_resp->resource_id = CPU_TO_LE16(resource);
3077         cmd_resp->access_type = CPU_TO_LE16(access);
3078         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3079
3080         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3081         /* The completion specifies the maximum time in ms that the driver
3082          * may hold the resource in the Timeout field.
3083          * If the resource is held by someone else, the command completes with
3084          * busy return value and the timeout field indicates the maximum time
3085          * the current owner of the resource has to free it.
3086          */
3087         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3088                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3089
3090         return status;
3091 }
3092
3093 /**
3094  * i40e_aq_release_resource
3095  * @hw: pointer to the hw struct
3096  * @resource: resource id
3097  * @sdp_number: resource number
3098  * @cmd_details: pointer to command details structure or NULL
3099  *
3100  * release common resource using the admin queue commands
3101  **/
3102 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3103                                 enum i40e_aq_resources_ids resource,
3104                                 u8 sdp_number,
3105                                 struct i40e_asq_cmd_details *cmd_details)
3106 {
3107         struct i40e_aq_desc desc;
3108         struct i40e_aqc_request_resource *cmd =
3109                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3110         enum i40e_status_code status;
3111
3112         DEBUGFUNC("i40e_aq_release_resource");
3113
3114         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3115
3116         cmd->resource_id = CPU_TO_LE16(resource);
3117         cmd->resource_number = CPU_TO_LE32(sdp_number);
3118
3119         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3120
3121         return status;
3122 }
3123
3124 /**
3125  * i40e_aq_read_nvm
3126  * @hw: pointer to the hw struct
3127  * @module_pointer: module pointer location in words from the NVM beginning
3128  * @offset: byte offset from the module beginning
3129  * @length: length of the section to be read (in bytes from the offset)
3130  * @data: command buffer (size [bytes] = length)
3131  * @last_command: tells if this is the last command in a series
3132  * @cmd_details: pointer to command details structure or NULL
3133  *
3134  * Read the NVM using the admin queue commands
3135  **/
3136 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3137                                 u32 offset, u16 length, void *data,
3138                                 bool last_command,
3139                                 struct i40e_asq_cmd_details *cmd_details)
3140 {
3141         struct i40e_aq_desc desc;
3142         struct i40e_aqc_nvm_update *cmd =
3143                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3144         enum i40e_status_code status;
3145
3146         DEBUGFUNC("i40e_aq_read_nvm");
3147
3148         /* In offset the highest byte must be zeroed. */
3149         if (offset & 0xFF000000) {
3150                 status = I40E_ERR_PARAM;
3151                 goto i40e_aq_read_nvm_exit;
3152         }
3153
3154         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3155
3156         /* If this is the last command in a series, set the proper flag. */
3157         if (last_command)
3158                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3159         cmd->module_pointer = module_pointer;
3160         cmd->offset = CPU_TO_LE32(offset);
3161         cmd->length = CPU_TO_LE16(length);
3162
3163         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3164         if (length > I40E_AQ_LARGE_BUF)
3165                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3166
3167         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3168
3169 i40e_aq_read_nvm_exit:
3170         return status;
3171 }
3172
3173 /**
3174  * i40e_aq_read_nvm_config - read an nvm config block
3175  * @hw: pointer to the hw struct
3176  * @cmd_flags: NVM access admin command bits
3177  * @field_id: field or feature id
3178  * @data: buffer for result
3179  * @buf_size: buffer size
3180  * @element_count: pointer to count of elements read by FW
3181  * @cmd_details: pointer to command details structure or NULL
3182  **/
3183 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3184                                 u8 cmd_flags, u32 field_id, void *data,
3185                                 u16 buf_size, u16 *element_count,
3186                                 struct i40e_asq_cmd_details *cmd_details)
3187 {
3188         struct i40e_aq_desc desc;
3189         struct i40e_aqc_nvm_config_read *cmd =
3190                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3191         enum i40e_status_code status;
3192
3193         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3194         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3195         if (buf_size > I40E_AQ_LARGE_BUF)
3196                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3197
3198         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3199         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3200         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3201                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3202         else
3203                 cmd->element_id_msw = 0;
3204
3205         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3206
3207         if (!status && element_count)
3208                 *element_count = LE16_TO_CPU(cmd->element_count);
3209
3210         return status;
3211 }
3212
3213 /**
3214  * i40e_aq_write_nvm_config - write an nvm config block
3215  * @hw: pointer to the hw struct
3216  * @cmd_flags: NVM access admin command bits
3217  * @data: buffer for result
3218  * @buf_size: buffer size
3219  * @element_count: count of elements to be written
3220  * @cmd_details: pointer to command details structure or NULL
3221  **/
3222 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3223                                 u8 cmd_flags, void *data, u16 buf_size,
3224                                 u16 element_count,
3225                                 struct i40e_asq_cmd_details *cmd_details)
3226 {
3227         struct i40e_aq_desc desc;
3228         struct i40e_aqc_nvm_config_write *cmd =
3229                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3230         enum i40e_status_code status;
3231
3232         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3233         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3234         if (buf_size > I40E_AQ_LARGE_BUF)
3235                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3236
3237         cmd->element_count = CPU_TO_LE16(element_count);
3238         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3239         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3240
3241         return status;
3242 }
3243
3244 /**
3245  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3246  * @hw: pointer to the hw struct
3247  * @cmd_details: pointer to command details structure or NULL
3248  **/
3249 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3250                                 void *buff, u16 buff_size,
3251                                 struct i40e_asq_cmd_details *cmd_details)
3252 {
3253         struct i40e_aq_desc desc;
3254         enum i40e_status_code status;
3255
3256
3257         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3258         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3259         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3260                 status = I40E_ERR_NOT_IMPLEMENTED;
3261
3262         return status;
3263 }
3264
3265 /**
3266  * i40e_aq_erase_nvm
3267  * @hw: pointer to the hw struct
3268  * @module_pointer: module pointer location in words from the NVM beginning
3269  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3270  * @length: length of the section to be erased (expressed in 4 KB)
3271  * @last_command: tells if this is the last command in a series
3272  * @cmd_details: pointer to command details structure or NULL
3273  *
3274  * Erase the NVM sector using the admin queue commands
3275  **/
3276 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3277                                 u32 offset, u16 length, bool last_command,
3278                                 struct i40e_asq_cmd_details *cmd_details)
3279 {
3280         struct i40e_aq_desc desc;
3281         struct i40e_aqc_nvm_update *cmd =
3282                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3283         enum i40e_status_code status;
3284
3285         DEBUGFUNC("i40e_aq_erase_nvm");
3286
3287         /* In offset the highest byte must be zeroed. */
3288         if (offset & 0xFF000000) {
3289                 status = I40E_ERR_PARAM;
3290                 goto i40e_aq_erase_nvm_exit;
3291         }
3292
3293         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3294
3295         /* If this is the last command in a series, set the proper flag. */
3296         if (last_command)
3297                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3298         cmd->module_pointer = module_pointer;
3299         cmd->offset = CPU_TO_LE32(offset);
3300         cmd->length = CPU_TO_LE16(length);
3301
3302         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3303
3304 i40e_aq_erase_nvm_exit:
3305         return status;
3306 }
3307
3308 #define I40E_DEV_FUNC_CAP_SWITCH_MODE   0x01
3309 #define I40E_DEV_FUNC_CAP_MGMT_MODE     0x02
3310 #define I40E_DEV_FUNC_CAP_NPAR          0x03
3311 #define I40E_DEV_FUNC_CAP_OS2BMC        0x04
3312 #define I40E_DEV_FUNC_CAP_VALID_FUNC    0x05
3313 #define I40E_DEV_FUNC_CAP_SRIOV_1_1     0x12
3314 #define I40E_DEV_FUNC_CAP_VF            0x13
3315 #define I40E_DEV_FUNC_CAP_VMDQ          0x14
3316 #define I40E_DEV_FUNC_CAP_802_1_QBG     0x15
3317 #define I40E_DEV_FUNC_CAP_802_1_QBH     0x16
3318 #define I40E_DEV_FUNC_CAP_VSI           0x17
3319 #define I40E_DEV_FUNC_CAP_DCB           0x18
3320 #define I40E_DEV_FUNC_CAP_FCOE          0x21
3321 #define I40E_DEV_FUNC_CAP_ISCSI         0x22
3322 #define I40E_DEV_FUNC_CAP_RSS           0x40
3323 #define I40E_DEV_FUNC_CAP_RX_QUEUES     0x41
3324 #define I40E_DEV_FUNC_CAP_TX_QUEUES     0x42
3325 #define I40E_DEV_FUNC_CAP_MSIX          0x43
3326 #define I40E_DEV_FUNC_CAP_MSIX_VF       0x44
3327 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3328 #define I40E_DEV_FUNC_CAP_IEEE_1588     0x46
3329 #define I40E_DEV_FUNC_CAP_FLEX10        0xF1
3330 #define I40E_DEV_FUNC_CAP_CEM           0xF2
3331 #define I40E_DEV_FUNC_CAP_IWARP         0x51
3332 #define I40E_DEV_FUNC_CAP_LED           0x61
3333 #define I40E_DEV_FUNC_CAP_SDP           0x62
3334 #define I40E_DEV_FUNC_CAP_MDIO          0x63
3335 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT   0x64
3336
3337 /**
3338  * i40e_parse_discover_capabilities
3339  * @hw: pointer to the hw struct
3340  * @buff: pointer to a buffer containing device/function capability records
3341  * @cap_count: number of capability records in the list
3342  * @list_type_opc: type of capabilities list to parse
3343  *
3344  * Parse the device/function capabilities list.
3345  **/
3346 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3347                                      u32 cap_count,
3348                                      enum i40e_admin_queue_opc list_type_opc)
3349 {
3350         struct i40e_aqc_list_capabilities_element_resp *cap;
3351         u32 valid_functions, num_functions;
3352         u32 number, logical_id, phys_id;
3353         struct i40e_hw_capabilities *p;
3354         u8 major_rev;
3355         u32 i = 0;
3356         u16 id;
3357
3358         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3359
3360         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3361                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3362         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3363                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3364         else
3365                 return;
3366
3367         for (i = 0; i < cap_count; i++, cap++) {
3368                 id = LE16_TO_CPU(cap->id);
3369                 number = LE32_TO_CPU(cap->number);
3370                 logical_id = LE32_TO_CPU(cap->logical_id);
3371                 phys_id = LE32_TO_CPU(cap->phys_id);
3372                 major_rev = cap->major_rev;
3373
3374                 switch (id) {
3375                 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3376                         p->switch_mode = number;
3377                         break;
3378                 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3379                         p->management_mode = number;
3380                         break;
3381                 case I40E_DEV_FUNC_CAP_NPAR:
3382                         p->npar_enable = number;
3383                         break;
3384                 case I40E_DEV_FUNC_CAP_OS2BMC:
3385                         p->os2bmc = number;
3386                         break;
3387                 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3388                         p->valid_functions = number;
3389                         break;
3390                 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3391                         if (number == 1)
3392                                 p->sr_iov_1_1 = TRUE;
3393                         break;
3394                 case I40E_DEV_FUNC_CAP_VF:
3395                         p->num_vfs = number;
3396                         p->vf_base_id = logical_id;
3397                         break;
3398                 case I40E_DEV_FUNC_CAP_VMDQ:
3399                         if (number == 1)
3400                                 p->vmdq = TRUE;
3401                         break;
3402                 case I40E_DEV_FUNC_CAP_802_1_QBG:
3403                         if (number == 1)
3404                                 p->evb_802_1_qbg = TRUE;
3405                         break;
3406                 case I40E_DEV_FUNC_CAP_802_1_QBH:
3407                         if (number == 1)
3408                                 p->evb_802_1_qbh = TRUE;
3409                         break;
3410                 case I40E_DEV_FUNC_CAP_VSI:
3411                         p->num_vsis = number;
3412                         break;
3413                 case I40E_DEV_FUNC_CAP_DCB:
3414                         if (number == 1) {
3415                                 p->dcb = TRUE;
3416                                 p->enabled_tcmap = logical_id;
3417                                 p->maxtc = phys_id;
3418                         }
3419                         break;
3420                 case I40E_DEV_FUNC_CAP_FCOE:
3421                         if (number == 1)
3422                                 p->fcoe = TRUE;
3423                         break;
3424                 case I40E_DEV_FUNC_CAP_ISCSI:
3425                         if (number == 1)
3426                                 p->iscsi = TRUE;
3427                         break;
3428                 case I40E_DEV_FUNC_CAP_RSS:
3429                         p->rss = TRUE;
3430                         p->rss_table_size = number;
3431                         p->rss_table_entry_width = logical_id;
3432                         break;
3433                 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3434                         p->num_rx_qp = number;
3435                         p->base_queue = phys_id;
3436                         break;
3437                 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3438                         p->num_tx_qp = number;
3439                         p->base_queue = phys_id;
3440                         break;
3441                 case I40E_DEV_FUNC_CAP_MSIX:
3442                         p->num_msix_vectors = number;
3443                         break;
3444                 case I40E_DEV_FUNC_CAP_MSIX_VF:
3445                         p->num_msix_vectors_vf = number;
3446                         break;
3447                 case I40E_DEV_FUNC_CAP_FLEX10:
3448                         if (major_rev == 1) {
3449                                 if (number == 1) {
3450                                         p->flex10_enable = TRUE;
3451                                         p->flex10_capable = TRUE;
3452                                 }
3453                         } else {
3454                                 /* Capability revision >= 2 */
3455                                 if (number & 1)
3456                                         p->flex10_enable = TRUE;
3457                                 if (number & 2)
3458                                         p->flex10_capable = TRUE;
3459                         }
3460                         p->flex10_mode = logical_id;
3461                         p->flex10_status = phys_id;
3462                         break;
3463                 case I40E_DEV_FUNC_CAP_CEM:
3464                         if (number == 1)
3465                                 p->mgmt_cem = TRUE;
3466                         break;
3467                 case I40E_DEV_FUNC_CAP_IWARP:
3468                         if (number == 1)
3469                                 p->iwarp = TRUE;
3470                         break;
3471                 case I40E_DEV_FUNC_CAP_LED:
3472                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3473                                 p->led[phys_id] = TRUE;
3474                         break;
3475                 case I40E_DEV_FUNC_CAP_SDP:
3476                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3477                                 p->sdp[phys_id] = TRUE;
3478                         break;
3479                 case I40E_DEV_FUNC_CAP_MDIO:
3480                         if (number == 1) {
3481                                 p->mdio_port_num = phys_id;
3482                                 p->mdio_port_mode = logical_id;
3483                         }
3484                         break;
3485                 case I40E_DEV_FUNC_CAP_IEEE_1588:
3486                         if (number == 1)
3487                                 p->ieee_1588 = TRUE;
3488                         break;
3489                 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3490                         p->fd = TRUE;
3491                         p->fd_filters_guaranteed = number;
3492                         p->fd_filters_best_effort = logical_id;
3493                         break;
3494                 case I40E_DEV_FUNC_CAP_WR_CSR_PROT:
3495                         p->wr_csr_prot = (u64)number;
3496                         p->wr_csr_prot |= (u64)logical_id << 32;
3497                         break;
3498                 default:
3499                         break;
3500                 }
3501         }
3502
3503         if (p->fcoe)
3504                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3505
3506         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3507         p->fcoe = FALSE;
3508
3509         /* count the enabled ports (aka the "not disabled" ports) */
3510         hw->num_ports = 0;
3511         for (i = 0; i < 4; i++) {
3512                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3513                 u64 port_cfg = 0;
3514
3515                 /* use AQ read to get the physical register offset instead
3516                  * of the port relative offset
3517                  */
3518                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3519                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3520                         hw->num_ports++;
3521         }
3522
3523         valid_functions = p->valid_functions;
3524         num_functions = 0;
3525         while (valid_functions) {
3526                 if (valid_functions & 1)
3527                         num_functions++;
3528                 valid_functions >>= 1;
3529         }
3530
3531         /* partition id is 1-based, and functions are evenly spread
3532          * across the ports as partitions
3533          */
3534         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3535         hw->num_partitions = num_functions / hw->num_ports;
3536
3537         /* additional HW specific goodies that might
3538          * someday be HW version specific
3539          */
3540         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3541 }
3542
3543 /**
3544  * i40e_aq_discover_capabilities
3545  * @hw: pointer to the hw struct
3546  * @buff: a virtual buffer to hold the capabilities
3547  * @buff_size: Size of the virtual buffer
3548  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3549  * @list_type_opc: capabilities type to discover - pass in the command opcode
3550  * @cmd_details: pointer to command details structure or NULL
3551  *
3552  * Get the device capabilities descriptions from the firmware
3553  **/
3554 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3555                                 void *buff, u16 buff_size, u16 *data_size,
3556                                 enum i40e_admin_queue_opc list_type_opc,
3557                                 struct i40e_asq_cmd_details *cmd_details)
3558 {
3559         struct i40e_aqc_list_capabilites *cmd;
3560         struct i40e_aq_desc desc;
3561         enum i40e_status_code status = I40E_SUCCESS;
3562
3563         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3564
3565         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3566                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3567                 status = I40E_ERR_PARAM;
3568                 goto exit;
3569         }
3570
3571         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3572
3573         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3574         if (buff_size > I40E_AQ_LARGE_BUF)
3575                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3576
3577         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3578         *data_size = LE16_TO_CPU(desc.datalen);
3579
3580         if (status)
3581                 goto exit;
3582
3583         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3584                                          list_type_opc);
3585
3586 exit:
3587         return status;
3588 }
3589
3590 /**
3591  * i40e_aq_update_nvm
3592  * @hw: pointer to the hw struct
3593  * @module_pointer: module pointer location in words from the NVM beginning
3594  * @offset: byte offset from the module beginning
3595  * @length: length of the section to be written (in bytes from the offset)
3596  * @data: command buffer (size [bytes] = length)
3597  * @last_command: tells if this is the last command in a series
3598  * @cmd_details: pointer to command details structure or NULL
3599  *
3600  * Update the NVM using the admin queue commands
3601  **/
3602 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3603                                 u32 offset, u16 length, void *data,
3604                                 bool last_command,
3605                                 struct i40e_asq_cmd_details *cmd_details)
3606 {
3607         struct i40e_aq_desc desc;
3608         struct i40e_aqc_nvm_update *cmd =
3609                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3610         enum i40e_status_code status;
3611
3612         DEBUGFUNC("i40e_aq_update_nvm");
3613
3614         /* In offset the highest byte must be zeroed. */
3615         if (offset & 0xFF000000) {
3616                 status = I40E_ERR_PARAM;
3617                 goto i40e_aq_update_nvm_exit;
3618         }
3619
3620         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3621
3622         /* If this is the last command in a series, set the proper flag. */
3623         if (last_command)
3624                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3625         cmd->module_pointer = module_pointer;
3626         cmd->offset = CPU_TO_LE32(offset);
3627         cmd->length = CPU_TO_LE16(length);
3628
3629         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3630         if (length > I40E_AQ_LARGE_BUF)
3631                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3632
3633         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3634
3635 i40e_aq_update_nvm_exit:
3636         return status;
3637 }
3638
3639 /**
3640  * i40e_aq_get_lldp_mib
3641  * @hw: pointer to the hw struct
3642  * @bridge_type: type of bridge requested
3643  * @mib_type: Local, Remote or both Local and Remote MIBs
3644  * @buff: pointer to a user supplied buffer to store the MIB block
3645  * @buff_size: size of the buffer (in bytes)
3646  * @local_len : length of the returned Local LLDP MIB
3647  * @remote_len: length of the returned Remote LLDP MIB
3648  * @cmd_details: pointer to command details structure or NULL
3649  *
3650  * Requests the complete LLDP MIB (entire packet).
3651  **/
3652 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3653                                 u8 mib_type, void *buff, u16 buff_size,
3654                                 u16 *local_len, u16 *remote_len,
3655                                 struct i40e_asq_cmd_details *cmd_details)
3656 {
3657         struct i40e_aq_desc desc;
3658         struct i40e_aqc_lldp_get_mib *cmd =
3659                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3660         struct i40e_aqc_lldp_get_mib *resp =
3661                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3662         enum i40e_status_code status;
3663
3664         if (buff_size == 0 || !buff)
3665                 return I40E_ERR_PARAM;
3666
3667         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3668         /* Indirect Command */
3669         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3670
3671         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3672         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3673                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3674
3675         desc.datalen = CPU_TO_LE16(buff_size);
3676
3677         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3678         if (buff_size > I40E_AQ_LARGE_BUF)
3679                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3680
3681         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3682         if (!status) {
3683                 if (local_len != NULL)
3684                         *local_len = LE16_TO_CPU(resp->local_len);
3685                 if (remote_len != NULL)
3686                         *remote_len = LE16_TO_CPU(resp->remote_len);
3687         }
3688
3689         return status;
3690 }
3691
3692  /**
3693  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3694  * @hw: pointer to the hw struct
3695  * @mib_type: Local, Remote or both Local and Remote MIBs
3696  * @buff: pointer to a user supplied buffer to store the MIB block
3697  * @buff_size: size of the buffer (in bytes)
3698  * @cmd_details: pointer to command details structure or NULL
3699  *
3700  * Set the LLDP MIB.
3701  **/
3702 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3703                                 u8 mib_type, void *buff, u16 buff_size,
3704                                 struct i40e_asq_cmd_details *cmd_details)
3705 {
3706         struct i40e_aq_desc desc;
3707         struct i40e_aqc_lldp_set_local_mib *cmd =
3708                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3709         enum i40e_status_code status;
3710
3711         if (buff_size == 0 || !buff)
3712                 return I40E_ERR_PARAM;
3713
3714         i40e_fill_default_direct_cmd_desc(&desc,
3715                                 i40e_aqc_opc_lldp_set_local_mib);
3716         /* Indirect Command */
3717         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3718         if (buff_size > I40E_AQ_LARGE_BUF)
3719                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3720         desc.datalen = CPU_TO_LE16(buff_size);
3721
3722         cmd->type = mib_type;
3723         cmd->length = CPU_TO_LE16(buff_size);
3724         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3725         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3726
3727         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3728         return status;
3729 }
3730
3731 /**
3732  * i40e_aq_cfg_lldp_mib_change_event
3733  * @hw: pointer to the hw struct
3734  * @enable_update: Enable or Disable event posting
3735  * @cmd_details: pointer to command details structure or NULL
3736  *
3737  * Enable or Disable posting of an event on ARQ when LLDP MIB
3738  * associated with the interface changes
3739  **/
3740 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3741                                 bool enable_update,
3742                                 struct i40e_asq_cmd_details *cmd_details)
3743 {
3744         struct i40e_aq_desc desc;
3745         struct i40e_aqc_lldp_update_mib *cmd =
3746                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3747         enum i40e_status_code status;
3748
3749         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3750
3751         if (!enable_update)
3752                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3753
3754         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3755
3756         return status;
3757 }
3758
3759 /**
3760  * i40e_aq_add_lldp_tlv
3761  * @hw: pointer to the hw struct
3762  * @bridge_type: type of bridge
3763  * @buff: buffer with TLV to add
3764  * @buff_size: length of the buffer
3765  * @tlv_len: length of the TLV to be added
3766  * @mib_len: length of the LLDP MIB returned in response
3767  * @cmd_details: pointer to command details structure or NULL
3768  *
3769  * Add the specified TLV to LLDP Local MIB for the given bridge type,
3770  * it is responsibility of the caller to make sure that the TLV is not
3771  * already present in the LLDPDU.
3772  * In return firmware will write the complete LLDP MIB with the newly
3773  * added TLV in the response buffer.
3774  **/
3775 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3776                                 void *buff, u16 buff_size, u16 tlv_len,
3777                                 u16 *mib_len,
3778                                 struct i40e_asq_cmd_details *cmd_details)
3779 {
3780         struct i40e_aq_desc desc;
3781         struct i40e_aqc_lldp_add_tlv *cmd =
3782                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3783         enum i40e_status_code status;
3784
3785         if (buff_size == 0 || !buff || tlv_len == 0)
3786                 return I40E_ERR_PARAM;
3787
3788         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3789
3790         /* Indirect Command */
3791         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3792         if (buff_size > I40E_AQ_LARGE_BUF)
3793                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3794         desc.datalen = CPU_TO_LE16(buff_size);
3795
3796         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3797                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3798         cmd->len = CPU_TO_LE16(tlv_len);
3799
3800         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3801         if (!status) {
3802                 if (mib_len != NULL)
3803                         *mib_len = LE16_TO_CPU(desc.datalen);
3804         }
3805
3806         return status;
3807 }
3808
3809 /**
3810  * i40e_aq_update_lldp_tlv
3811  * @hw: pointer to the hw struct
3812  * @bridge_type: type of bridge
3813  * @buff: buffer with TLV to update
3814  * @buff_size: size of the buffer holding original and updated TLVs
3815  * @old_len: Length of the Original TLV
3816  * @new_len: Length of the Updated TLV
3817  * @offset: offset of the updated TLV in the buff
3818  * @mib_len: length of the returned LLDP MIB
3819  * @cmd_details: pointer to command details structure or NULL
3820  *
3821  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3822  * Firmware will place the complete LLDP MIB in response buffer with the
3823  * updated TLV.
3824  **/
3825 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3826                                 u8 bridge_type, void *buff, u16 buff_size,
3827                                 u16 old_len, u16 new_len, u16 offset,
3828                                 u16 *mib_len,
3829                                 struct i40e_asq_cmd_details *cmd_details)
3830 {
3831         struct i40e_aq_desc desc;
3832         struct i40e_aqc_lldp_update_tlv *cmd =
3833                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3834         enum i40e_status_code status;
3835
3836         if (buff_size == 0 || !buff || offset == 0 ||
3837             old_len == 0 || new_len == 0)
3838                 return I40E_ERR_PARAM;
3839
3840         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3841
3842         /* Indirect Command */
3843         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3844         if (buff_size > I40E_AQ_LARGE_BUF)
3845                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3846         desc.datalen = CPU_TO_LE16(buff_size);
3847
3848         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3849                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3850         cmd->old_len = CPU_TO_LE16(old_len);
3851         cmd->new_offset = CPU_TO_LE16(offset);
3852         cmd->new_len = CPU_TO_LE16(new_len);
3853
3854         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3855         if (!status) {
3856                 if (mib_len != NULL)
3857                         *mib_len = LE16_TO_CPU(desc.datalen);
3858         }
3859
3860         return status;
3861 }
3862
3863 /**
3864  * i40e_aq_delete_lldp_tlv
3865  * @hw: pointer to the hw struct
3866  * @bridge_type: type of bridge
3867  * @buff: pointer to a user supplied buffer that has the TLV
3868  * @buff_size: length of the buffer
3869  * @tlv_len: length of the TLV to be deleted
3870  * @mib_len: length of the returned LLDP MIB
3871  * @cmd_details: pointer to command details structure or NULL
3872  *
3873  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3874  * The firmware places the entire LLDP MIB in the response buffer.
3875  **/
3876 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3877                                 u8 bridge_type, void *buff, u16 buff_size,
3878                                 u16 tlv_len, u16 *mib_len,
3879                                 struct i40e_asq_cmd_details *cmd_details)
3880 {
3881         struct i40e_aq_desc desc;
3882         struct i40e_aqc_lldp_add_tlv *cmd =
3883                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3884         enum i40e_status_code status;
3885
3886         if (buff_size == 0 || !buff)
3887                 return I40E_ERR_PARAM;
3888
3889         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3890
3891         /* Indirect Command */
3892         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3893         if (buff_size > I40E_AQ_LARGE_BUF)
3894                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3895         desc.datalen = CPU_TO_LE16(buff_size);
3896         cmd->len = CPU_TO_LE16(tlv_len);
3897         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3898                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3899
3900         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3901         if (!status) {
3902                 if (mib_len != NULL)
3903                         *mib_len = LE16_TO_CPU(desc.datalen);
3904         }
3905
3906         return status;
3907 }
3908
3909 /**
3910  * i40e_aq_stop_lldp
3911  * @hw: pointer to the hw struct
3912  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3913  * @cmd_details: pointer to command details structure or NULL
3914  *
3915  * Stop or Shutdown the embedded LLDP Agent
3916  **/
3917 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3918                                 struct i40e_asq_cmd_details *cmd_details)
3919 {
3920         struct i40e_aq_desc desc;
3921         struct i40e_aqc_lldp_stop *cmd =
3922                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3923         enum i40e_status_code status;
3924
3925         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3926
3927         if (shutdown_agent)
3928                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3929
3930         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3931
3932         return status;
3933 }
3934
3935 /**
3936  * i40e_aq_start_lldp
3937  * @hw: pointer to the hw struct
3938  * @cmd_details: pointer to command details structure or NULL
3939  *
3940  * Start the embedded LLDP Agent on all ports.
3941  **/
3942 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3943                                 struct i40e_asq_cmd_details *cmd_details)
3944 {
3945         struct i40e_aq_desc desc;
3946         struct i40e_aqc_lldp_start *cmd =
3947                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3948         enum i40e_status_code status;
3949
3950         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3951
3952         cmd->command = I40E_AQ_LLDP_AGENT_START;
3953
3954         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3955
3956         return status;
3957 }
3958
3959 /**
3960  * i40e_aq_get_cee_dcb_config
3961  * @hw: pointer to the hw struct
3962  * @buff: response buffer that stores CEE operational configuration
3963  * @buff_size: size of the buffer passed
3964  * @cmd_details: pointer to command details structure or NULL
3965  *
3966  * Get CEE DCBX mode operational configuration from firmware
3967  **/
3968 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3969                                 void *buff, u16 buff_size,
3970                                 struct i40e_asq_cmd_details *cmd_details)
3971 {
3972         struct i40e_aq_desc desc;
3973         enum i40e_status_code status;
3974
3975         if (buff_size == 0 || !buff)
3976                 return I40E_ERR_PARAM;
3977
3978         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3979
3980         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3981         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3982                                        cmd_details);
3983
3984         return status;
3985 }
3986
3987 /**
3988  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3989  * @hw: pointer to the hw struct
3990  * @start_agent: True if DCBx Agent needs to be Started
3991  *                              False if DCBx Agent needs to be Stopped
3992  * @cmd_details: pointer to command details structure or NULL
3993  *
3994  * Start/Stop the embedded dcbx Agent
3995  **/
3996 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3997                                 bool start_agent,
3998                                 struct i40e_asq_cmd_details *cmd_details)
3999 {
4000         struct i40e_aq_desc desc;
4001         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4002                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4003                                 &desc.params.raw;
4004         enum i40e_status_code status;
4005
4006         i40e_fill_default_direct_cmd_desc(&desc,
4007                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4008
4009         if (start_agent)
4010                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4011
4012         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4013
4014         return status;
4015 }
4016
4017 /**
4018  * i40e_aq_add_udp_tunnel
4019  * @hw: pointer to the hw struct
4020  * @udp_port: the UDP port to add
4021  * @header_len: length of the tunneling header length in DWords
4022  * @protocol_index: protocol index type
4023  * @filter_index: pointer to filter index
4024  * @cmd_details: pointer to command details structure or NULL
4025  **/
4026 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4027                                 u16 udp_port, u8 protocol_index,
4028                                 u8 *filter_index,
4029                                 struct i40e_asq_cmd_details *cmd_details)
4030 {
4031         struct i40e_aq_desc desc;
4032         struct i40e_aqc_add_udp_tunnel *cmd =
4033                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4034         struct i40e_aqc_del_udp_tunnel_completion *resp =
4035                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4036         enum i40e_status_code status;
4037
4038         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4039
4040         cmd->udp_port = CPU_TO_LE16(udp_port);
4041         cmd->protocol_type = protocol_index;
4042
4043         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4044
4045         if (!status && filter_index)
4046                 *filter_index = resp->index;
4047
4048         return status;
4049 }
4050
4051 /**
4052  * i40e_aq_del_udp_tunnel
4053  * @hw: pointer to the hw struct
4054  * @index: filter index
4055  * @cmd_details: pointer to command details structure or NULL
4056  **/
4057 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4058                                 struct i40e_asq_cmd_details *cmd_details)
4059 {
4060         struct i40e_aq_desc desc;
4061         struct i40e_aqc_remove_udp_tunnel *cmd =
4062                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4063         enum i40e_status_code status;
4064
4065         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4066
4067         cmd->index = index;
4068
4069         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4070
4071         return status;
4072 }
4073
4074 /**
4075  * i40e_aq_get_switch_resource_alloc (0x0204)
4076  * @hw: pointer to the hw struct
4077  * @num_entries: pointer to u8 to store the number of resource entries returned
4078  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4079  *        to store the resource information for all resource types.  Each
4080  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4081  * @count: size, in bytes, of the buffer provided
4082  * @cmd_details: pointer to command details structure or NULL
4083  *
4084  * Query the resources allocated to a function.
4085  **/
4086 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4087                         u8 *num_entries,
4088                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4089                         u16 count,
4090                         struct i40e_asq_cmd_details *cmd_details)
4091 {
4092         struct i40e_aq_desc desc;
4093         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4094                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4095         enum i40e_status_code status;
4096         u16 length = count * sizeof(*buf);
4097
4098         i40e_fill_default_direct_cmd_desc(&desc,
4099                                         i40e_aqc_opc_get_switch_resource_alloc);
4100
4101         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4102         if (length > I40E_AQ_LARGE_BUF)
4103                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4104
4105         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4106
4107         if (!status && num_entries)
4108                 *num_entries = cmd_resp->num_entries;
4109
4110         return status;
4111 }
4112
4113 /**
4114  * i40e_aq_delete_element - Delete switch element
4115  * @hw: pointer to the hw struct
4116  * @seid: the SEID to delete from the switch
4117  * @cmd_details: pointer to command details structure or NULL
4118  *
4119  * This deletes a switch element from the switch.
4120  **/
4121 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4122                                 struct i40e_asq_cmd_details *cmd_details)
4123 {
4124         struct i40e_aq_desc desc;
4125         struct i40e_aqc_switch_seid *cmd =
4126                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4127         enum i40e_status_code status;
4128
4129         if (seid == 0)
4130                 return I40E_ERR_PARAM;
4131
4132         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4133
4134         cmd->seid = CPU_TO_LE16(seid);
4135
4136         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4137
4138         return status;
4139 }
4140
4141 /**
4142  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4143  * @hw: pointer to the hw struct
4144  * @flags: component flags
4145  * @mac_seid: uplink seid (MAC SEID)
4146  * @vsi_seid: connected vsi seid
4147  * @ret_seid: seid of create pv component
4148  *
4149  * This instantiates an i40e port virtualizer with specified flags.
4150  * Depending on specified flags the port virtualizer can act as a
4151  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4152  */
4153 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4154                                        u16 mac_seid, u16 vsi_seid,
4155                                        u16 *ret_seid)
4156 {
4157         struct i40e_aq_desc desc;
4158         struct i40e_aqc_add_update_pv *cmd =
4159                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4160         struct i40e_aqc_add_update_pv_completion *resp =
4161                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4162         enum i40e_status_code status;
4163
4164         if (vsi_seid == 0)
4165                 return I40E_ERR_PARAM;
4166
4167         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4168         cmd->command_flags = CPU_TO_LE16(flags);
4169         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4170         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4171
4172         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4173         if (!status && ret_seid)
4174                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4175
4176         return status;
4177 }
4178
4179 /**
4180  * i40e_aq_add_tag - Add an S/E-tag
4181  * @hw: pointer to the hw struct
4182  * @direct_to_queue: should s-tag direct flow to a specific queue
4183  * @vsi_seid: VSI SEID to use this tag
4184  * @tag: value of the tag
4185  * @queue_num: queue number, only valid is direct_to_queue is TRUE
4186  * @tags_used: return value, number of tags in use by this PF
4187  * @tags_free: return value, number of unallocated tags
4188  * @cmd_details: pointer to command details structure or NULL
4189  *
4190  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4191  * the number of tags allocated by the PF, and the number of unallocated
4192  * tags available.
4193  **/
4194 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4195                                 u16 vsi_seid, u16 tag, u16 queue_num,
4196                                 u16 *tags_used, u16 *tags_free,
4197                                 struct i40e_asq_cmd_details *cmd_details)
4198 {
4199         struct i40e_aq_desc desc;
4200         struct i40e_aqc_add_tag *cmd =
4201                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4202         struct i40e_aqc_add_remove_tag_completion *resp =
4203                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4204         enum i40e_status_code status;
4205
4206         if (vsi_seid == 0)
4207                 return I40E_ERR_PARAM;
4208
4209         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4210
4211         cmd->seid = CPU_TO_LE16(vsi_seid);
4212         cmd->tag = CPU_TO_LE16(tag);
4213         if (direct_to_queue) {
4214                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4215                 cmd->queue_number = CPU_TO_LE16(queue_num);
4216         }
4217
4218         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4219
4220         if (!status) {
4221                 if (tags_used != NULL)
4222                         *tags_used = LE16_TO_CPU(resp->tags_used);
4223                 if (tags_free != NULL)
4224                         *tags_free = LE16_TO_CPU(resp->tags_free);
4225         }
4226
4227         return status;
4228 }
4229
4230 /**
4231  * i40e_aq_remove_tag - Remove an S- or E-tag
4232  * @hw: pointer to the hw struct
4233  * @vsi_seid: VSI SEID this tag is associated with
4234  * @tag: value of the S-tag to delete
4235  * @tags_used: return value, number of tags in use by this PF
4236  * @tags_free: return value, number of unallocated tags
4237  * @cmd_details: pointer to command details structure or NULL
4238  *
4239  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4240  * the number of tags allocated by the PF, and the number of unallocated
4241  * tags available.
4242  **/
4243 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4244                                 u16 tag, u16 *tags_used, u16 *tags_free,
4245                                 struct i40e_asq_cmd_details *cmd_details)
4246 {
4247         struct i40e_aq_desc desc;
4248         struct i40e_aqc_remove_tag *cmd =
4249                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4250         struct i40e_aqc_add_remove_tag_completion *resp =
4251                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4252         enum i40e_status_code status;
4253
4254         if (vsi_seid == 0)
4255                 return I40E_ERR_PARAM;
4256
4257         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4258
4259         cmd->seid = CPU_TO_LE16(vsi_seid);
4260         cmd->tag = CPU_TO_LE16(tag);
4261
4262         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4263
4264         if (!status) {
4265                 if (tags_used != NULL)
4266                         *tags_used = LE16_TO_CPU(resp->tags_used);
4267                 if (tags_free != NULL)
4268                         *tags_free = LE16_TO_CPU(resp->tags_free);
4269         }
4270
4271         return status;
4272 }
4273
4274 /**
4275  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4276  * @hw: pointer to the hw struct
4277  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4278  * @etag: value of E-tag to add
4279  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4280  * @buf: address of indirect buffer
4281  * @tags_used: return value, number of E-tags in use by this port
4282  * @tags_free: return value, number of unallocated M-tags
4283  * @cmd_details: pointer to command details structure or NULL
4284  *
4285  * This associates a multicast E-tag to a port virtualizer.  It will return
4286  * the number of tags allocated by the PF, and the number of unallocated
4287  * tags available.
4288  *
4289  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4290  * num_tags_in_buf long.
4291  **/
4292 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4293                                 u16 etag, u8 num_tags_in_buf, void *buf,
4294                                 u16 *tags_used, u16 *tags_free,
4295                                 struct i40e_asq_cmd_details *cmd_details)
4296 {
4297         struct i40e_aq_desc desc;
4298         struct i40e_aqc_add_remove_mcast_etag *cmd =
4299                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4300         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4301            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4302         enum i40e_status_code status;
4303         u16 length = sizeof(u16) * num_tags_in_buf;
4304
4305         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4306                 return I40E_ERR_PARAM;
4307
4308         i40e_fill_default_direct_cmd_desc(&desc,
4309                                           i40e_aqc_opc_add_multicast_etag);
4310
4311         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4312         cmd->etag = CPU_TO_LE16(etag);
4313         cmd->num_unicast_etags = num_tags_in_buf;
4314
4315         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4316         if (length > I40E_AQ_LARGE_BUF)
4317                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4318
4319         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4320
4321         if (!status) {
4322                 if (tags_used != NULL)
4323                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4324                 if (tags_free != NULL)
4325                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4326         }
4327
4328         return status;
4329 }
4330
4331 /**
4332  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4333  * @hw: pointer to the hw struct
4334  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4335  * @etag: value of the E-tag to remove
4336  * @tags_used: return value, number of tags in use by this port
4337  * @tags_free: return value, number of unallocated tags
4338  * @cmd_details: pointer to command details structure or NULL
4339  *
4340  * This deletes an E-tag from the port virtualizer.  It will return
4341  * the number of tags allocated by the port, and the number of unallocated
4342  * tags available.
4343  **/
4344 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4345                                 u16 etag, u16 *tags_used, u16 *tags_free,
4346                                 struct i40e_asq_cmd_details *cmd_details)
4347 {
4348         struct i40e_aq_desc desc;
4349         struct i40e_aqc_add_remove_mcast_etag *cmd =
4350                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4351         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4352            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4353         enum i40e_status_code status;
4354
4355
4356         if (pv_seid == 0)
4357                 return I40E_ERR_PARAM;
4358
4359         i40e_fill_default_direct_cmd_desc(&desc,
4360                                           i40e_aqc_opc_remove_multicast_etag);
4361
4362         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4363         cmd->etag = CPU_TO_LE16(etag);
4364
4365         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4366
4367         if (!status) {
4368                 if (tags_used != NULL)
4369                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4370                 if (tags_free != NULL)
4371                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4372         }
4373
4374         return status;
4375 }
4376
4377 /**
4378  * i40e_aq_update_tag - Update an S/E-tag
4379  * @hw: pointer to the hw struct
4380  * @vsi_seid: VSI SEID using this S-tag
4381  * @old_tag: old tag value
4382  * @new_tag: new tag value
4383  * @tags_used: return value, number of tags in use by this PF
4384  * @tags_free: return value, number of unallocated tags
4385  * @cmd_details: pointer to command details structure or NULL
4386  *
4387  * This updates the value of the tag currently attached to this VSI
4388  * in the switch complex.  It will return the number of tags allocated
4389  * by the PF, and the number of unallocated tags available.
4390  **/
4391 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4392                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4393                                 u16 *tags_free,
4394                                 struct i40e_asq_cmd_details *cmd_details)
4395 {
4396         struct i40e_aq_desc desc;
4397         struct i40e_aqc_update_tag *cmd =
4398                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4399         struct i40e_aqc_update_tag_completion *resp =
4400                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4401         enum i40e_status_code status;
4402
4403         if (vsi_seid == 0)
4404                 return I40E_ERR_PARAM;
4405
4406         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4407
4408         cmd->seid = CPU_TO_LE16(vsi_seid);
4409         cmd->old_tag = CPU_TO_LE16(old_tag);
4410         cmd->new_tag = CPU_TO_LE16(new_tag);
4411
4412         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4413
4414         if (!status) {
4415                 if (tags_used != NULL)
4416                         *tags_used = LE16_TO_CPU(resp->tags_used);
4417                 if (tags_free != NULL)
4418                         *tags_free = LE16_TO_CPU(resp->tags_free);
4419         }
4420
4421         return status;
4422 }
4423
4424 /**
4425  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4426  * @hw: pointer to the hw struct
4427  * @tcmap: TC map for request/release any ignore PFC condition
4428  * @request: request or release ignore PFC condition
4429  * @tcmap_ret: return TCs for which PFC is currently ignored
4430  * @cmd_details: pointer to command details structure or NULL
4431  *
4432  * This sends out request/release to ignore PFC condition for a TC.
4433  * It will return the TCs for which PFC is currently ignored.
4434  **/
4435 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4436                                 bool request, u8 *tcmap_ret,
4437                                 struct i40e_asq_cmd_details *cmd_details)
4438 {
4439         struct i40e_aq_desc desc;
4440         struct i40e_aqc_pfc_ignore *cmd_resp =
4441                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4442         enum i40e_status_code status;
4443
4444         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4445
4446         if (request)
4447                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4448
4449         cmd_resp->tc_bitmap = tcmap;
4450
4451         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4452
4453         if (!status) {
4454                 if (tcmap_ret != NULL)
4455                         *tcmap_ret = cmd_resp->tc_bitmap;
4456         }
4457
4458         return status;
4459 }
4460
4461 /**
4462  * i40e_aq_dcb_updated - DCB Updated Command
4463  * @hw: pointer to the hw struct
4464  * @cmd_details: pointer to command details structure or NULL
4465  *
4466  * When LLDP is handled in PF this command is used by the PF
4467  * to notify EMP that a DCB setting is modified.
4468  * When LLDP is handled in EMP this command is used by the PF
4469  * to notify EMP whenever one of the following parameters get
4470  * modified:
4471  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4472  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4473  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4474  * EMP will return when the shared RPB settings have been
4475  * recomputed and modified. The retval field in the descriptor
4476  * will be set to 0 when RPB is modified.
4477  **/
4478 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4479                                 struct i40e_asq_cmd_details *cmd_details)
4480 {
4481         struct i40e_aq_desc desc;
4482         enum i40e_status_code status;
4483
4484         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4485
4486         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4487
4488         return status;
4489 }
4490
4491 /**
4492  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4493  * @hw: pointer to the hw struct
4494  * @seid: defines the SEID of the switch for which the stats are requested
4495  * @vlan_id: the VLAN ID for which the statistics are requested
4496  * @stat_index: index of the statistics counters block assigned to this VLAN
4497  * @cmd_details: pointer to command details structure or NULL
4498  *
4499  * XL710 supports 128 smonVlanStats counters.This command is used to
4500  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4501  * switch.
4502  **/
4503 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4504                                 u16 vlan_id, u16 *stat_index,
4505                                 struct i40e_asq_cmd_details *cmd_details)
4506 {
4507         struct i40e_aq_desc desc;
4508         struct i40e_aqc_add_remove_statistics *cmd_resp =
4509                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4510         enum i40e_status_code status;
4511
4512         if ((seid == 0) || (stat_index == NULL))
4513                 return I40E_ERR_PARAM;
4514
4515         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4516
4517         cmd_resp->seid = CPU_TO_LE16(seid);
4518         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4519
4520         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4521
4522         if (!status && stat_index)
4523                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4524
4525         return status;
4526 }
4527
4528 /**
4529  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4530  * @hw: pointer to the hw struct
4531  * @seid: defines the SEID of the switch for which the stats are requested
4532  * @vlan_id: the VLAN ID for which the statistics are requested
4533  * @stat_index: index of the statistics counters block assigned to this VLAN
4534  * @cmd_details: pointer to command details structure or NULL
4535  *
4536  * XL710 supports 128 smonVlanStats counters.This command is used to
4537  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4538  * switch.
4539  **/
4540 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4541                                 u16 vlan_id, u16 stat_index,
4542                                 struct i40e_asq_cmd_details *cmd_details)
4543 {
4544         struct i40e_aq_desc desc;
4545         struct i40e_aqc_add_remove_statistics *cmd =
4546                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4547         enum i40e_status_code status;
4548
4549         if (seid == 0)
4550                 return I40E_ERR_PARAM;
4551
4552         i40e_fill_default_direct_cmd_desc(&desc,
4553                                           i40e_aqc_opc_remove_statistics);
4554
4555         cmd->seid = CPU_TO_LE16(seid);
4556         cmd->vlan  = CPU_TO_LE16(vlan_id);
4557         cmd->stat_index = CPU_TO_LE16(stat_index);
4558
4559         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4560
4561         return status;
4562 }
4563
4564 /**
4565  * i40e_aq_set_port_parameters - set physical port parameters.
4566  * @hw: pointer to the hw struct
4567  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4568  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4569  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4570  * @double_vlan: if set double VLAN is enabled
4571  * @cmd_details: pointer to command details structure or NULL
4572  **/
4573 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4574                                 u16 bad_frame_vsi, bool save_bad_pac,
4575                                 bool pad_short_pac, bool double_vlan,
4576                                 struct i40e_asq_cmd_details *cmd_details)
4577 {
4578         struct i40e_aqc_set_port_parameters *cmd;
4579         enum i40e_status_code status;
4580         struct i40e_aq_desc desc;
4581         u16 command_flags = 0;
4582
4583         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4584
4585         i40e_fill_default_direct_cmd_desc(&desc,
4586                                           i40e_aqc_opc_set_port_parameters);
4587
4588         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4589         if (save_bad_pac)
4590                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4591         if (pad_short_pac)
4592                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4593         if (double_vlan)
4594                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4595         cmd->command_flags = CPU_TO_LE16(command_flags);
4596
4597         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4598
4599         return status;
4600 }
4601
4602 /**
4603  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4604  * @hw: pointer to the hw struct
4605  * @seid: seid for the physical port/switching component/vsi
4606  * @buff: Indirect buffer to hold data parameters and response
4607  * @buff_size: Indirect buffer size
4608  * @opcode: Tx scheduler AQ command opcode
4609  * @cmd_details: pointer to command details structure or NULL
4610  *
4611  * Generic command handler for Tx scheduler AQ commands
4612  **/
4613 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4614                                 void *buff, u16 buff_size,
4615                                  enum i40e_admin_queue_opc opcode,
4616                                 struct i40e_asq_cmd_details *cmd_details)
4617 {
4618         struct i40e_aq_desc desc;
4619         struct i40e_aqc_tx_sched_ind *cmd =
4620                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4621         enum i40e_status_code status;
4622         bool cmd_param_flag = FALSE;
4623
4624         switch (opcode) {
4625         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4626         case i40e_aqc_opc_configure_vsi_tc_bw:
4627         case i40e_aqc_opc_enable_switching_comp_ets:
4628         case i40e_aqc_opc_modify_switching_comp_ets:
4629         case i40e_aqc_opc_disable_switching_comp_ets:
4630         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4631         case i40e_aqc_opc_configure_switching_comp_bw_config:
4632                 cmd_param_flag = TRUE;
4633                 break;
4634         case i40e_aqc_opc_query_vsi_bw_config:
4635         case i40e_aqc_opc_query_vsi_ets_sla_config:
4636         case i40e_aqc_opc_query_switching_comp_ets_config:
4637         case i40e_aqc_opc_query_port_ets_config:
4638         case i40e_aqc_opc_query_switching_comp_bw_config:
4639                 cmd_param_flag = FALSE;
4640                 break;
4641         default:
4642                 return I40E_ERR_PARAM;
4643         }
4644
4645         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4646
4647         /* Indirect command */
4648         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4649         if (cmd_param_flag)
4650                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4651         if (buff_size > I40E_AQ_LARGE_BUF)
4652                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4653
4654         desc.datalen = CPU_TO_LE16(buff_size);
4655
4656         cmd->vsi_seid = CPU_TO_LE16(seid);
4657
4658         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4659
4660         return status;
4661 }
4662
4663 /**
4664  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4665  * @hw: pointer to the hw struct
4666  * @seid: VSI seid
4667  * @credit: BW limit credits (0 = disabled)
4668  * @max_credit: Max BW limit credits
4669  * @cmd_details: pointer to command details structure or NULL
4670  **/
4671 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4672                                 u16 seid, u16 credit, u8 max_credit,
4673                                 struct i40e_asq_cmd_details *cmd_details)
4674 {
4675         struct i40e_aq_desc desc;
4676         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4677                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4678         enum i40e_status_code status;
4679
4680         i40e_fill_default_direct_cmd_desc(&desc,
4681                                           i40e_aqc_opc_configure_vsi_bw_limit);
4682
4683         cmd->vsi_seid = CPU_TO_LE16(seid);
4684         cmd->credit = CPU_TO_LE16(credit);
4685         cmd->max_credit = max_credit;
4686
4687         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4688
4689         return status;
4690 }
4691
4692 /**
4693  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4694  * @hw: pointer to the hw struct
4695  * @seid: switching component seid
4696  * @credit: BW limit credits (0 = disabled)
4697  * @max_bw: Max BW limit credits
4698  * @cmd_details: pointer to command details structure or NULL
4699  **/
4700 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4701                                 u16 seid, u16 credit, u8 max_bw,
4702                                 struct i40e_asq_cmd_details *cmd_details)
4703 {
4704         struct i40e_aq_desc desc;
4705         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4706           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4707         enum i40e_status_code status;
4708
4709         i40e_fill_default_direct_cmd_desc(&desc,
4710                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
4711
4712         cmd->seid = CPU_TO_LE16(seid);
4713         cmd->credit = CPU_TO_LE16(credit);
4714         cmd->max_bw = max_bw;
4715
4716         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4717
4718         return status;
4719 }
4720
4721 /**
4722  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4723  * @hw: pointer to the hw struct
4724  * @seid: VSI seid
4725  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4726  * @cmd_details: pointer to command details structure or NULL
4727  **/
4728 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4729                         u16 seid,
4730                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4731                         struct i40e_asq_cmd_details *cmd_details)
4732 {
4733         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4734                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4735                                     cmd_details);
4736 }
4737
4738 /**
4739  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4740  * @hw: pointer to the hw struct
4741  * @seid: VSI seid
4742  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4743  * @cmd_details: pointer to command details structure or NULL
4744  **/
4745 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4746                         u16 seid,
4747                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4748                         struct i40e_asq_cmd_details *cmd_details)
4749 {
4750         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4751                                     i40e_aqc_opc_configure_vsi_tc_bw,
4752                                     cmd_details);
4753 }
4754
4755 /**
4756  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4757  * @hw: pointer to the hw struct
4758  * @seid: seid of the switching component
4759  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4760  * @cmd_details: pointer to command details structure or NULL
4761  **/
4762 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4763         struct i40e_hw *hw, u16 seid,
4764         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4765         struct i40e_asq_cmd_details *cmd_details)
4766 {
4767         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4768                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4769                             cmd_details);
4770 }
4771
4772 /**
4773  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4774  * @hw: pointer to the hw struct
4775  * @seid: seid of the VSI
4776  * @bw_data: Buffer to hold VSI BW configuration
4777  * @cmd_details: pointer to command details structure or NULL
4778  **/
4779 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4780                         u16 seid,
4781                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4782                         struct i40e_asq_cmd_details *cmd_details)
4783 {
4784         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4785                                     i40e_aqc_opc_query_vsi_bw_config,
4786                                     cmd_details);
4787 }
4788
4789 /**
4790  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4791  * @hw: pointer to the hw struct
4792  * @seid: seid of the VSI
4793  * @bw_data: Buffer to hold VSI BW configuration per TC
4794  * @cmd_details: pointer to command details structure or NULL
4795  **/
4796 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4797                         u16 seid,
4798                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4799                         struct i40e_asq_cmd_details *cmd_details)
4800 {
4801         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4802                                     i40e_aqc_opc_query_vsi_ets_sla_config,
4803                                     cmd_details);
4804 }
4805
4806 /**
4807  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4808  * @hw: pointer to the hw struct
4809  * @seid: seid of the switching component
4810  * @bw_data: Buffer to hold switching component's per TC BW config
4811  * @cmd_details: pointer to command details structure or NULL
4812  **/
4813 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4814                 u16 seid,
4815                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4816                 struct i40e_asq_cmd_details *cmd_details)
4817 {
4818         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4819                                    i40e_aqc_opc_query_switching_comp_ets_config,
4820                                    cmd_details);
4821 }
4822
4823 /**
4824  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4825  * @hw: pointer to the hw struct
4826  * @seid: seid of the VSI or switching component connected to Physical Port
4827  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4828  * @cmd_details: pointer to command details structure or NULL
4829  **/
4830 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4831                         u16 seid,
4832                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
4833                         struct i40e_asq_cmd_details *cmd_details)
4834 {
4835         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4836                                     i40e_aqc_opc_query_port_ets_config,
4837                                     cmd_details);
4838 }
4839
4840 /**
4841  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4842  * @hw: pointer to the hw struct
4843  * @seid: seid of the switching component
4844  * @bw_data: Buffer to hold switching component's BW configuration
4845  * @cmd_details: pointer to command details structure or NULL
4846  **/
4847 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4848                 u16 seid,
4849                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4850                 struct i40e_asq_cmd_details *cmd_details)
4851 {
4852         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4853                                     i40e_aqc_opc_query_switching_comp_bw_config,
4854                                     cmd_details);
4855 }
4856
4857 /**
4858  * i40e_validate_filter_settings
4859  * @hw: pointer to the hardware structure
4860  * @settings: Filter control settings
4861  *
4862  * Check and validate the filter control settings passed.
4863  * The function checks for the valid filter/context sizes being
4864  * passed for FCoE and PE.
4865  *
4866  * Returns I40E_SUCCESS if the values passed are valid and within
4867  * range else returns an error.
4868  **/
4869 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4870                                 struct i40e_filter_control_settings *settings)
4871 {
4872         u32 fcoe_cntx_size, fcoe_filt_size;
4873         u32 pe_cntx_size, pe_filt_size;
4874         u32 fcoe_fmax;
4875
4876         u32 val;
4877
4878         /* Validate FCoE settings passed */
4879         switch (settings->fcoe_filt_num) {
4880         case I40E_HASH_FILTER_SIZE_1K:
4881         case I40E_HASH_FILTER_SIZE_2K:
4882         case I40E_HASH_FILTER_SIZE_4K:
4883         case I40E_HASH_FILTER_SIZE_8K:
4884         case I40E_HASH_FILTER_SIZE_16K:
4885         case I40E_HASH_FILTER_SIZE_32K:
4886                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4887                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4888                 break;
4889         default:
4890                 return I40E_ERR_PARAM;
4891         }
4892
4893         switch (settings->fcoe_cntx_num) {
4894         case I40E_DMA_CNTX_SIZE_512:
4895         case I40E_DMA_CNTX_SIZE_1K:
4896         case I40E_DMA_CNTX_SIZE_2K:
4897         case I40E_DMA_CNTX_SIZE_4K:
4898                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4899                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4900                 break;
4901         default:
4902                 return I40E_ERR_PARAM;
4903         }
4904
4905         /* Validate PE settings passed */
4906         switch (settings->pe_filt_num) {
4907         case I40E_HASH_FILTER_SIZE_1K:
4908         case I40E_HASH_FILTER_SIZE_2K:
4909         case I40E_HASH_FILTER_SIZE_4K:
4910         case I40E_HASH_FILTER_SIZE_8K:
4911         case I40E_HASH_FILTER_SIZE_16K:
4912         case I40E_HASH_FILTER_SIZE_32K:
4913         case I40E_HASH_FILTER_SIZE_64K:
4914         case I40E_HASH_FILTER_SIZE_128K:
4915         case I40E_HASH_FILTER_SIZE_256K:
4916         case I40E_HASH_FILTER_SIZE_512K:
4917         case I40E_HASH_FILTER_SIZE_1M:
4918                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4919                 pe_filt_size <<= (u32)settings->pe_filt_num;
4920                 break;
4921         default:
4922                 return I40E_ERR_PARAM;
4923         }
4924
4925         switch (settings->pe_cntx_num) {
4926         case I40E_DMA_CNTX_SIZE_512:
4927         case I40E_DMA_CNTX_SIZE_1K:
4928         case I40E_DMA_CNTX_SIZE_2K:
4929         case I40E_DMA_CNTX_SIZE_4K:
4930         case I40E_DMA_CNTX_SIZE_8K:
4931         case I40E_DMA_CNTX_SIZE_16K:
4932         case I40E_DMA_CNTX_SIZE_32K:
4933         case I40E_DMA_CNTX_SIZE_64K:
4934         case I40E_DMA_CNTX_SIZE_128K:
4935         case I40E_DMA_CNTX_SIZE_256K:
4936                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4937                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4938                 break;
4939         default:
4940                 return I40E_ERR_PARAM;
4941         }
4942
4943         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4944         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4945         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4946                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4947         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4948                 return I40E_ERR_INVALID_SIZE;
4949
4950         return I40E_SUCCESS;
4951 }
4952
4953 /**
4954  * i40e_set_filter_control
4955  * @hw: pointer to the hardware structure
4956  * @settings: Filter control settings
4957  *
4958  * Set the Queue Filters for PE/FCoE and enable filters required
4959  * for a single PF. It is expected that these settings are programmed
4960  * at the driver initialization time.
4961  **/
4962 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4963                                 struct i40e_filter_control_settings *settings)
4964 {
4965         enum i40e_status_code ret = I40E_SUCCESS;
4966         u32 hash_lut_size = 0;
4967         u32 val;
4968
4969         if (!settings)
4970                 return I40E_ERR_PARAM;
4971
4972         /* Validate the input settings */
4973         ret = i40e_validate_filter_settings(hw, settings);
4974         if (ret)
4975                 return ret;
4976
4977         /* Read the PF Queue Filter control register */
4978         val = rd32(hw, I40E_PFQF_CTL_0);
4979
4980         /* Program required PE hash buckets for the PF */
4981         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4982         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4983                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4984         /* Program required PE contexts for the PF */
4985         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4986         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4987                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4988
4989         /* Program required FCoE hash buckets for the PF */
4990         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4991         val |= ((u32)settings->fcoe_filt_num <<
4992                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4993                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4994         /* Program required FCoE DDP contexts for the PF */
4995         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4996         val |= ((u32)settings->fcoe_cntx_num <<
4997                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4998                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4999
5000         /* Program Hash LUT size for the PF */
5001         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5002         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5003                 hash_lut_size = 1;
5004         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5005                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5006
5007         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5008         if (settings->enable_fdir)
5009                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5010         if (settings->enable_ethtype)
5011                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5012         if (settings->enable_macvlan)
5013                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5014
5015         wr32(hw, I40E_PFQF_CTL_0, val);
5016
5017         return I40E_SUCCESS;
5018 }
5019
5020 /**
5021  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5022  * @hw: pointer to the hw struct
5023  * @mac_addr: MAC address to use in the filter
5024  * @ethtype: Ethertype to use in the filter
5025  * @flags: Flags that needs to be applied to the filter
5026  * @vsi_seid: seid of the control VSI
5027  * @queue: VSI queue number to send the packet to
5028  * @is_add: Add control packet filter if True else remove
5029  * @stats: Structure to hold information on control filter counts
5030  * @cmd_details: pointer to command details structure or NULL
5031  *
5032  * This command will Add or Remove control packet filter for a control VSI.
5033  * In return it will update the total number of perfect filter count in
5034  * the stats member.
5035  **/
5036 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5037                                 u8 *mac_addr, u16 ethtype, u16 flags,
5038                                 u16 vsi_seid, u16 queue, bool is_add,
5039                                 struct i40e_control_filter_stats *stats,
5040                                 struct i40e_asq_cmd_details *cmd_details)
5041 {
5042         struct i40e_aq_desc desc;
5043         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5044                 (struct i40e_aqc_add_remove_control_packet_filter *)
5045                 &desc.params.raw;
5046         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5047                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5048                 &desc.params.raw;
5049         enum i40e_status_code status;
5050
5051         if (vsi_seid == 0)
5052                 return I40E_ERR_PARAM;
5053
5054         if (is_add) {
5055                 i40e_fill_default_direct_cmd_desc(&desc,
5056                                 i40e_aqc_opc_add_control_packet_filter);
5057                 cmd->queue = CPU_TO_LE16(queue);
5058         } else {
5059                 i40e_fill_default_direct_cmd_desc(&desc,
5060                                 i40e_aqc_opc_remove_control_packet_filter);
5061         }
5062
5063         if (mac_addr)
5064                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5065                             I40E_NONDMA_TO_NONDMA);
5066
5067         cmd->etype = CPU_TO_LE16(ethtype);
5068         cmd->flags = CPU_TO_LE16(flags);
5069         cmd->seid = CPU_TO_LE16(vsi_seid);
5070
5071         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5072
5073         if (!status && stats) {
5074                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5075                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5076                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5077                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5078         }
5079
5080         return status;
5081 }
5082
5083 /**
5084  * i40e_aq_add_cloud_filters
5085  * @hw: pointer to the hardware structure
5086  * @seid: VSI seid to add cloud filters from
5087  * @filters: Buffer which contains the filters to be added
5088  * @filter_count: number of filters contained in the buffer
5089  *
5090  * Set the cloud filters for a given VSI.  The contents of the
5091  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5092  * in by the caller of the function.
5093  *
5094  **/
5095 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5096         u16 seid,
5097         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5098         u8 filter_count)
5099 {
5100         struct i40e_aq_desc desc;
5101         struct i40e_aqc_add_remove_cloud_filters *cmd =
5102         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5103         u16 buff_len;
5104         enum i40e_status_code status;
5105
5106         i40e_fill_default_direct_cmd_desc(&desc,
5107                                           i40e_aqc_opc_add_cloud_filters);
5108
5109         buff_len = filter_count * sizeof(*filters);
5110         desc.datalen = CPU_TO_LE16(buff_len);
5111         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5112         cmd->num_filters = filter_count;
5113         cmd->seid = CPU_TO_LE16(seid);
5114
5115         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5116
5117         return status;
5118 }
5119
5120 /**
5121  * i40e_aq_remove_cloud_filters
5122  * @hw: pointer to the hardware structure
5123  * @seid: VSI seid to remove cloud filters from
5124  * @filters: Buffer which contains the filters to be removed
5125  * @filter_count: number of filters contained in the buffer
5126  *
5127  * Remove the cloud filters for a given VSI.  The contents of the
5128  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5129  * in by the caller of the function.
5130  *
5131  **/
5132 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5133                 u16 seid,
5134                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5135                 u8 filter_count)
5136 {
5137         struct i40e_aq_desc desc;
5138         struct i40e_aqc_add_remove_cloud_filters *cmd =
5139         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5140         enum i40e_status_code status;
5141         u16 buff_len;
5142
5143         i40e_fill_default_direct_cmd_desc(&desc,
5144                                           i40e_aqc_opc_remove_cloud_filters);
5145
5146         buff_len = filter_count * sizeof(*filters);
5147         desc.datalen = CPU_TO_LE16(buff_len);
5148         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5149         cmd->num_filters = filter_count;
5150         cmd->seid = CPU_TO_LE16(seid);
5151
5152         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5153
5154         return status;
5155 }
5156
5157 /**
5158  * i40e_aq_alternate_write
5159  * @hw: pointer to the hardware structure
5160  * @reg_addr0: address of first dword to be read
5161  * @reg_val0: value to be written under 'reg_addr0'
5162  * @reg_addr1: address of second dword to be read
5163  * @reg_val1: value to be written under 'reg_addr1'
5164  *
5165  * Write one or two dwords to alternate structure. Fields are indicated
5166  * by 'reg_addr0' and 'reg_addr1' register numbers.
5167  *
5168  **/
5169 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5170                                 u32 reg_addr0, u32 reg_val0,
5171                                 u32 reg_addr1, u32 reg_val1)
5172 {
5173         struct i40e_aq_desc desc;
5174         struct i40e_aqc_alternate_write *cmd_resp =
5175                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5176         enum i40e_status_code status;
5177
5178         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5179         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5180         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5181         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5182         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5183
5184         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5185
5186         return status;
5187 }
5188
5189 /**
5190  * i40e_aq_alternate_write_indirect
5191  * @hw: pointer to the hardware structure
5192  * @addr: address of a first register to be modified
5193  * @dw_count: number of alternate structure fields to write
5194  * @buffer: pointer to the command buffer
5195  *
5196  * Write 'dw_count' dwords from 'buffer' to alternate structure
5197  * starting at 'addr'.
5198  *
5199  **/
5200 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5201                                 u32 addr, u32 dw_count, void *buffer)
5202 {
5203         struct i40e_aq_desc desc;
5204         struct i40e_aqc_alternate_ind_write *cmd_resp =
5205                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5206         enum i40e_status_code status;
5207
5208         if (buffer == NULL)
5209                 return I40E_ERR_PARAM;
5210
5211         /* Indirect command */
5212         i40e_fill_default_direct_cmd_desc(&desc,
5213                                          i40e_aqc_opc_alternate_write_indirect);
5214
5215         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5216         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5217         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5218                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5219
5220         cmd_resp->address = CPU_TO_LE32(addr);
5221         cmd_resp->length = CPU_TO_LE32(dw_count);
5222         cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
5223         cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5224
5225         status = i40e_asq_send_command(hw, &desc, buffer,
5226                                        I40E_LO_DWORD(4*dw_count), NULL);
5227
5228         return status;
5229 }
5230
5231 /**
5232  * i40e_aq_alternate_read
5233  * @hw: pointer to the hardware structure
5234  * @reg_addr0: address of first dword to be read
5235  * @reg_val0: pointer for data read from 'reg_addr0'
5236  * @reg_addr1: address of second dword to be read
5237  * @reg_val1: pointer for data read from 'reg_addr1'
5238  *
5239  * Read one or two dwords from alternate structure. Fields are indicated
5240  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5241  * is not passed then only register at 'reg_addr0' is read.
5242  *
5243  **/
5244 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5245                                 u32 reg_addr0, u32 *reg_val0,
5246                                 u32 reg_addr1, u32 *reg_val1)
5247 {
5248         struct i40e_aq_desc desc;
5249         struct i40e_aqc_alternate_write *cmd_resp =
5250                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5251         enum i40e_status_code status;
5252
5253         if (reg_val0 == NULL)
5254                 return I40E_ERR_PARAM;
5255
5256         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5257         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5258         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5259
5260         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5261
5262         if (status == I40E_SUCCESS) {
5263                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5264
5265                 if (reg_val1 != NULL)
5266                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5267         }
5268
5269         return status;
5270 }
5271
5272 /**
5273  * i40e_aq_alternate_read_indirect
5274  * @hw: pointer to the hardware structure
5275  * @addr: address of the alternate structure field
5276  * @dw_count: number of alternate structure fields to read
5277  * @buffer: pointer to the command buffer
5278  *
5279  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5280  * place them in 'buffer'. The buffer should be allocated by caller.
5281  *
5282  **/
5283 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5284                                 u32 addr, u32 dw_count, void *buffer)
5285 {
5286         struct i40e_aq_desc desc;
5287         struct i40e_aqc_alternate_ind_write *cmd_resp =
5288                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5289         enum i40e_status_code status;
5290
5291         if (buffer == NULL)
5292                 return I40E_ERR_PARAM;
5293
5294         /* Indirect command */
5295         i40e_fill_default_direct_cmd_desc(&desc,
5296                 i40e_aqc_opc_alternate_read_indirect);
5297
5298         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5299         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5300         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5301                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5302
5303         cmd_resp->address = CPU_TO_LE32(addr);
5304         cmd_resp->length = CPU_TO_LE32(dw_count);
5305         cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
5306         cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5307
5308         status = i40e_asq_send_command(hw, &desc, buffer,
5309                                        I40E_LO_DWORD(4*dw_count), NULL);
5310
5311         return status;
5312 }
5313
5314 /**
5315  *  i40e_aq_alternate_clear
5316  *  @hw: pointer to the HW structure.
5317  *
5318  *  Clear the alternate structures of the port from which the function
5319  *  is called.
5320  *
5321  **/
5322 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5323 {
5324         struct i40e_aq_desc desc;
5325         enum i40e_status_code status;
5326
5327         i40e_fill_default_direct_cmd_desc(&desc,
5328                                           i40e_aqc_opc_alternate_clear_port);
5329
5330         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5331
5332         return status;
5333 }
5334
5335 /**
5336  *  i40e_aq_alternate_write_done
5337  *  @hw: pointer to the HW structure.
5338  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5339  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5340  *
5341  *  Indicates to the FW that alternate structures have been changed.
5342  *
5343  **/
5344 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5345                 u8 bios_mode, bool *reset_needed)
5346 {
5347         struct i40e_aq_desc desc;
5348         struct i40e_aqc_alternate_write_done *cmd =
5349                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5350         enum i40e_status_code status;
5351
5352         if (reset_needed == NULL)
5353                 return I40E_ERR_PARAM;
5354
5355         i40e_fill_default_direct_cmd_desc(&desc,
5356                                           i40e_aqc_opc_alternate_write_done);
5357
5358         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5359
5360         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5361         if (!status && reset_needed)
5362                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5363                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5364
5365         return status;
5366 }
5367
5368 /**
5369  *  i40e_aq_set_oem_mode
5370  *  @hw: pointer to the HW structure.
5371  *  @oem_mode: the OEM mode to be used
5372  *
5373  *  Sets the device to a specific operating mode. Currently the only supported
5374  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5375  *
5376  **/
5377 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5378                 u8 oem_mode)
5379 {
5380         struct i40e_aq_desc desc;
5381         struct i40e_aqc_alternate_write_done *cmd =
5382                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5383         enum i40e_status_code status;
5384
5385         i40e_fill_default_direct_cmd_desc(&desc,
5386                                           i40e_aqc_opc_alternate_set_mode);
5387
5388         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5389
5390         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5391
5392         return status;
5393 }
5394
5395 /**
5396  * i40e_aq_resume_port_tx
5397  * @hw: pointer to the hardware structure
5398  * @cmd_details: pointer to command details structure or NULL
5399  *
5400  * Resume port's Tx traffic
5401  **/
5402 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5403                                 struct i40e_asq_cmd_details *cmd_details)
5404 {
5405         struct i40e_aq_desc desc;
5406         enum i40e_status_code status;
5407
5408         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5409
5410         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5411
5412         return status;
5413 }
5414
5415 /**
5416  * i40e_set_pci_config_data - store PCI bus info
5417  * @hw: pointer to hardware structure
5418  * @link_status: the link status word from PCI config space
5419  *
5420  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5421  **/
5422 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5423 {
5424         hw->bus.type = i40e_bus_type_pci_express;
5425
5426         switch (link_status & I40E_PCI_LINK_WIDTH) {
5427         case I40E_PCI_LINK_WIDTH_1:
5428                 hw->bus.width = i40e_bus_width_pcie_x1;
5429                 break;
5430         case I40E_PCI_LINK_WIDTH_2:
5431                 hw->bus.width = i40e_bus_width_pcie_x2;
5432                 break;
5433         case I40E_PCI_LINK_WIDTH_4:
5434                 hw->bus.width = i40e_bus_width_pcie_x4;
5435                 break;
5436         case I40E_PCI_LINK_WIDTH_8:
5437                 hw->bus.width = i40e_bus_width_pcie_x8;
5438                 break;
5439         default:
5440                 hw->bus.width = i40e_bus_width_unknown;
5441                 break;
5442         }
5443
5444         switch (link_status & I40E_PCI_LINK_SPEED) {
5445         case I40E_PCI_LINK_SPEED_2500:
5446                 hw->bus.speed = i40e_bus_speed_2500;
5447                 break;
5448         case I40E_PCI_LINK_SPEED_5000:
5449                 hw->bus.speed = i40e_bus_speed_5000;
5450                 break;
5451         case I40E_PCI_LINK_SPEED_8000:
5452                 hw->bus.speed = i40e_bus_speed_8000;
5453                 break;
5454         default:
5455                 hw->bus.speed = i40e_bus_speed_unknown;
5456                 break;
5457         }
5458 }
5459
5460 /**
5461  * i40e_aq_debug_dump
5462  * @hw: pointer to the hardware structure
5463  * @cluster_id: specific cluster to dump
5464  * @table_id: table id within cluster
5465  * @start_index: index of line in the block to read
5466  * @buff_size: dump buffer size
5467  * @buff: dump buffer
5468  * @ret_buff_size: actual buffer size returned
5469  * @ret_next_table: next block to read
5470  * @ret_next_index: next index to read
5471  *
5472  * Dump internal FW/HW data for debug purposes.
5473  *
5474  **/
5475 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5476                                 u8 table_id, u32 start_index, u16 buff_size,
5477                                 void *buff, u16 *ret_buff_size,
5478                                 u8 *ret_next_table, u32 *ret_next_index,
5479                                 struct i40e_asq_cmd_details *cmd_details)
5480 {
5481         struct i40e_aq_desc desc;
5482         struct i40e_aqc_debug_dump_internals *cmd =
5483                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5484         struct i40e_aqc_debug_dump_internals *resp =
5485                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5486         enum i40e_status_code status;
5487
5488         if (buff_size == 0 || !buff)
5489                 return I40E_ERR_PARAM;
5490
5491         i40e_fill_default_direct_cmd_desc(&desc,
5492                                           i40e_aqc_opc_debug_dump_internals);
5493         /* Indirect Command */
5494         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5495         if (buff_size > I40E_AQ_LARGE_BUF)
5496                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5497
5498         cmd->cluster_id = cluster_id;
5499         cmd->table_id = table_id;
5500         cmd->idx = CPU_TO_LE32(start_index);
5501
5502         desc.datalen = CPU_TO_LE16(buff_size);
5503
5504         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5505         if (!status) {
5506                 if (ret_buff_size != NULL)
5507                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5508                 if (ret_next_table != NULL)
5509                         *ret_next_table = resp->table_id;
5510                 if (ret_next_index != NULL)
5511                         *ret_next_index = LE32_TO_CPU(resp->idx);
5512         }
5513
5514         return status;
5515 }
5516
5517 /**
5518  * i40e_read_bw_from_alt_ram
5519  * @hw: pointer to the hardware structure
5520  * @max_bw: pointer for max_bw read
5521  * @min_bw: pointer for min_bw read
5522  * @min_valid: pointer for bool that is TRUE if min_bw is a valid value
5523  * @max_valid: pointer for bool that is TRUE if max_bw is a valid value
5524  *
5525  * Read bw from the alternate ram for the given pf
5526  **/
5527 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5528                                         u32 *max_bw, u32 *min_bw,
5529                                         bool *min_valid, bool *max_valid)
5530 {
5531         enum i40e_status_code status;
5532         u32 max_bw_addr, min_bw_addr;
5533
5534         /* Calculate the address of the min/max bw registers */
5535         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5536                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5537                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5538         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5539                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5540                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5541
5542         /* Read the bandwidths from alt ram */
5543         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5544                                         min_bw_addr, min_bw);
5545
5546         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5547                 *min_valid = TRUE;
5548         else
5549                 *min_valid = FALSE;
5550
5551         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5552                 *max_valid = TRUE;
5553         else
5554                 *max_valid = FALSE;
5555
5556         return status;
5557 }
5558
5559 /**
5560  * i40e_aq_configure_partition_bw
5561  * @hw: pointer to the hardware structure
5562  * @bw_data: Buffer holding valid pfs and bw limits
5563  * @cmd_details: pointer to command details
5564  *
5565  * Configure partitions guaranteed/max bw
5566  **/
5567 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5568                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5569                         struct i40e_asq_cmd_details *cmd_details)
5570 {
5571         enum i40e_status_code status;
5572         struct i40e_aq_desc desc;
5573         u16 bwd_size = sizeof(*bw_data);
5574
5575         i40e_fill_default_direct_cmd_desc(&desc,
5576                                 i40e_aqc_opc_configure_partition_bw);
5577
5578         /* Indirect command */
5579         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5580         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5581
5582         if (bwd_size > I40E_AQ_LARGE_BUF)
5583                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5584
5585         desc.datalen = CPU_TO_LE16(bwd_size);
5586
5587         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5588
5589         return status;
5590 }
5591
5592 /**
5593  * i40e_aq_send_msg_to_pf
5594  * @hw: pointer to the hardware structure
5595  * @v_opcode: opcodes for VF-PF communication
5596  * @v_retval: return error code
5597  * @msg: pointer to the msg buffer
5598  * @msglen: msg length
5599  * @cmd_details: pointer to command details
5600  *
5601  * Send message to PF driver using admin queue. By default, this message
5602  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5603  * completion before returning.
5604  **/
5605 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5606                                 enum i40e_virtchnl_ops v_opcode,
5607                                 enum i40e_status_code v_retval,
5608                                 u8 *msg, u16 msglen,
5609                                 struct i40e_asq_cmd_details *cmd_details)
5610 {
5611         struct i40e_aq_desc desc;
5612         struct i40e_asq_cmd_details details;
5613         enum i40e_status_code status;
5614
5615         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5616         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5617         desc.cookie_high = CPU_TO_LE32(v_opcode);
5618         desc.cookie_low = CPU_TO_LE32(v_retval);
5619         if (msglen) {
5620                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5621                                                 | I40E_AQ_FLAG_RD));
5622                 if (msglen > I40E_AQ_LARGE_BUF)
5623                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5624                 desc.datalen = CPU_TO_LE16(msglen);
5625         }
5626         if (!cmd_details) {
5627                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5628                 details.async = TRUE;
5629                 cmd_details = &details;
5630         }
5631         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5632                                        msglen, cmd_details);
5633         return status;
5634 }
5635
5636 /**
5637  * i40e_vf_parse_hw_config
5638  * @hw: pointer to the hardware structure
5639  * @msg: pointer to the virtual channel VF resource structure
5640  *
5641  * Given a VF resource message from the PF, populate the hw struct
5642  * with appropriate information.
5643  **/
5644 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5645                              struct i40e_virtchnl_vf_resource *msg)
5646 {
5647         struct i40e_virtchnl_vsi_resource *vsi_res;
5648         int i;
5649
5650         vsi_res = &msg->vsi_res[0];
5651
5652         hw->dev_caps.num_vsis = msg->num_vsis;
5653         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5654         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5655         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5656         hw->dev_caps.dcb = msg->vf_offload_flags &
5657                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
5658         hw->dev_caps.fcoe = (msg->vf_offload_flags &
5659                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5660         hw->dev_caps.iwarp = (msg->vf_offload_flags &
5661                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5662         for (i = 0; i < msg->num_vsis; i++) {
5663                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5664                         i40e_memcpy(hw->mac.perm_addr,
5665                                     vsi_res->default_mac_addr,
5666                                     I40E_ETH_LENGTH_OF_ADDRESS,
5667                                     I40E_NONDMA_TO_NONDMA);
5668                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5669                                     I40E_ETH_LENGTH_OF_ADDRESS,
5670                                     I40E_NONDMA_TO_NONDMA);
5671                 }
5672                 vsi_res++;
5673         }
5674 }
5675
5676 /**
5677  * i40e_vf_reset
5678  * @hw: pointer to the hardware structure
5679  *
5680  * Send a VF_RESET message to the PF. Does not wait for response from PF
5681  * as none will be forthcoming. Immediately after calling this function,
5682  * the admin queue should be shut down and (optionally) reinitialized.
5683  **/
5684 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5685 {
5686         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5687                                       I40E_SUCCESS, NULL, 0, NULL);
5688 }