2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/kmod.h>
29 #include <linux/module.h>
30 #include <linux/errno.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/io-mapping.h>
35 #include <linux/interrupt.h>
36 #include <dev/mlx5/driver.h>
37 #include <dev/mlx5/cq.h>
38 #include <dev/mlx5/qp.h>
39 #include <dev/mlx5/srq.h>
40 #include <linux/delay.h>
41 #include <dev/mlx5/mlx5_ifc.h>
42 #include "mlx5_core.h"
44 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
45 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
46 MODULE_LICENSE("Dual BSD/GPL");
47 #if (__FreeBSD_version >= 1100000)
48 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
50 MODULE_VERSION(mlx5, 1);
52 int mlx5_core_debug_mask;
53 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
54 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
56 #define MLX5_DEFAULT_PROF 2
57 static int prof_sel = MLX5_DEFAULT_PROF;
58 module_param_named(prof_sel, prof_sel, int, 0444);
59 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
61 #define NUMA_NO_NODE -1
63 struct workqueue_struct *mlx5_core_wq;
64 static LIST_HEAD(intf_list);
65 static LIST_HEAD(dev_list);
66 static DEFINE_MUTEX(intf_mutex);
68 struct mlx5_device_context {
69 struct list_head list;
70 struct mlx5_interface *intf;
74 static struct mlx5_profile profiles[] = {
79 .mask = MLX5_PROF_MASK_QP_SIZE,
83 .mask = MLX5_PROF_MASK_QP_SIZE |
84 MLX5_PROF_MASK_MR_CACHE,
148 .mask = MLX5_PROF_MASK_QP_SIZE,
153 static int set_dma_caps(struct pci_dev *pdev)
157 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
159 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
160 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
162 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
167 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
169 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
170 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
172 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
177 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
181 static int request_bar(struct pci_dev *pdev)
185 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
186 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
190 err = pci_request_regions(pdev, DRIVER_NAME);
192 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
197 static void release_bar(struct pci_dev *pdev)
199 pci_release_regions(pdev);
202 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
204 struct mlx5_priv *priv = &dev->priv;
205 struct mlx5_eq_table *table = &priv->eq_table;
206 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
210 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
211 MLX5_EQ_VEC_COMP_BASE;
212 nvec = min_t(int, nvec, num_eqs);
213 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
216 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
218 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
220 for (i = 0; i < nvec; i++)
221 priv->msix_arr[i].entry = i;
223 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
224 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
228 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
234 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
236 struct mlx5_priv *priv = &dev->priv;
238 pci_disable_msix(dev->pdev);
239 kfree(priv->irq_info);
240 kfree(priv->msix_arr);
243 struct mlx5_reg_host_endianess {
249 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
252 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
253 MLX5_DEV_CAP_FLAG_DCT |
254 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
257 static u16 to_fw_pkey_sz(u32 size)
273 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
278 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
279 enum mlx5_cap_mode cap_mode)
281 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
282 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
283 void *out, *hca_caps;
284 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
287 memset(in, 0, sizeof(in));
288 out = kzalloc(out_sz, GFP_KERNEL);
290 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
291 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
292 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
296 err = mlx5_cmd_status_to_err_v2(out);
299 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
300 cap_type, cap_mode, err);
304 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
307 case HCA_CAP_OPMOD_GET_MAX:
308 memcpy(dev->hca_caps_max[cap_type], hca_caps,
309 MLX5_UN_SZ_BYTES(hca_cap_union));
311 case HCA_CAP_OPMOD_GET_CUR:
312 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
313 MLX5_UN_SZ_BYTES(hca_cap_union));
317 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
327 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
329 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
332 memset(out, 0, sizeof(out));
334 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
335 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
339 err = mlx5_cmd_status_to_err_v2(out);
344 static int handle_hca_cap(struct mlx5_core_dev *dev)
346 void *set_ctx = NULL;
347 struct mlx5_profile *prof = dev->profile;
349 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
352 set_ctx = kzalloc(set_sz, GFP_KERNEL);
354 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
358 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
362 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
364 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
365 MLX5_ST_SZ_BYTES(cmd_hca_cap));
367 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
368 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
370 /* we limit the size of the pkey table to 128 entries for now */
371 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
374 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
375 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
378 /* disable cmdif checksum */
379 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
381 /* enable drain sigerr */
382 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
384 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
386 err = set_caps(dev, set_ctx, set_sz);
393 static int set_hca_ctrl(struct mlx5_core_dev *dev)
395 struct mlx5_reg_host_endianess he_in;
396 struct mlx5_reg_host_endianess he_out;
399 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
400 !MLX5_CAP_GEN(dev, roce))
403 memset(&he_in, 0, sizeof(he_in));
404 he_in.he = MLX5_SET_HOST_ENDIANNESS;
405 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
406 &he_out, sizeof(he_out),
407 MLX5_REG_HOST_ENDIANNESS, 0, 1);
411 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
413 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
414 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
416 memset(in, 0, sizeof(in));
417 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
418 memset(out, 0, sizeof(out));
419 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
423 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
425 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
426 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
428 memset(in, 0, sizeof(in));
430 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
431 memset(out, 0, sizeof(out));
432 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
436 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
438 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
439 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
440 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
441 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
445 memset(query_in, 0, sizeof(query_in));
446 memset(query_out, 0, sizeof(query_out));
448 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
450 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
451 query_out, sizeof(query_out));
453 if (((struct mlx5_outbox_hdr *)query_out)->status ==
454 MLX5_CMD_STAT_BAD_OP_ERR) {
455 pr_debug("Only ISSI 0 is supported\n");
459 printf("mlx5_core: ERR: ""failed to query ISSI\n");
463 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
465 if (sup_issi & (1 << 1)) {
466 memset(set_in, 0, sizeof(set_in));
467 memset(set_out, 0, sizeof(set_out));
469 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
470 MLX5_SET(set_issi_in, set_in, current_issi, 1);
472 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
473 set_out, sizeof(set_out));
475 printf("mlx5_core: ERR: ""failed to set ISSI=1\n");
482 } else if (sup_issi & (1 << 0)) {
490 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
492 struct mlx5_eq_table *table = &dev->priv.eq_table;
496 spin_lock(&table->lock);
497 list_for_each_entry(eq, &table->comp_eqs_list, list) {
498 if (eq->index == vector) {
505 spin_unlock(&table->lock);
509 EXPORT_SYMBOL(mlx5_vector2eqn);
511 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
513 struct mlx5_priv *priv = &dev->priv;
514 struct mlx5_eq_table *table = &priv->eq_table;
518 spin_lock(&table->lock);
519 list_for_each_entry(eq, &table->comp_eqs_list, list) {
520 if (eq->index == eq_ix) {
521 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
523 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
524 "%s-%d", name, eq_ix);
530 spin_unlock(&table->lock);
535 static void free_comp_eqs(struct mlx5_core_dev *dev)
537 struct mlx5_eq_table *table = &dev->priv.eq_table;
538 struct mlx5_eq *eq, *n;
540 spin_lock(&table->lock);
541 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
543 spin_unlock(&table->lock);
544 if (mlx5_destroy_unmap_eq(dev, eq))
545 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
548 spin_lock(&table->lock);
550 spin_unlock(&table->lock);
553 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
555 struct mlx5_eq_table *table = &dev->priv.eq_table;
556 char name[MLX5_MAX_IRQ_NAME];
563 INIT_LIST_HEAD(&table->comp_eqs_list);
564 ncomp_vec = table->num_comp_vectors;
565 nent = MLX5_COMP_EQ_SIZE;
566 for (i = 0; i < ncomp_vec; i++) {
567 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
569 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
570 err = mlx5_create_map_eq(dev, eq,
571 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
572 name, &dev->priv.uuari.uars[0]);
577 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
579 spin_lock(&table->lock);
580 list_add_tail(&eq->list, &table->comp_eqs_list);
581 spin_unlock(&table->lock);
591 static int map_bf_area(struct mlx5_core_dev *dev)
593 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
594 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
596 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
598 return dev->priv.bf_mapping ? 0 : -ENOMEM;
601 static void unmap_bf_area(struct mlx5_core_dev *dev)
603 if (dev->priv.bf_mapping)
604 io_mapping_free(dev->priv.bf_mapping);
607 static inline int fw_initializing(struct mlx5_core_dev *dev)
609 return ioread32be(&dev->iseg->initializing) >> 31;
612 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
614 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
617 while (fw_initializing(dev)) {
618 if (time_after(jiffies, end)) {
622 msleep(FW_INIT_WAIT_MS);
628 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
630 struct mlx5_priv *priv = &dev->priv;
634 pci_set_drvdata(dev->pdev, dev);
635 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
636 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
638 mutex_init(&priv->pgdir_mutex);
639 INIT_LIST_HEAD(&priv->pgdir_list);
640 spin_lock_init(&priv->mkey_lock);
642 priv->numa_node = NUMA_NO_NODE;
644 err = pci_enable_device(pdev);
646 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
650 err = request_bar(pdev);
652 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
656 pci_set_master(pdev);
658 err = set_dma_caps(pdev);
660 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
664 dev->iseg = ioremap(pci_resource_start(dev->pdev, 0),
668 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
671 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
674 * On load removing any previous indication of internal error,
677 dev->state = MLX5_DEVICE_STATE_UP;
679 err = mlx5_cmd_init(dev);
681 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
685 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
687 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
688 goto err_cmd_cleanup;
691 mlx5_pagealloc_init(dev);
693 err = mlx5_core_enable_hca(dev);
695 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
696 goto err_pagealloc_cleanup;
699 err = mlx5_core_set_issi(dev);
701 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
702 goto err_disable_hca;
705 err = mlx5_pagealloc_start(dev);
707 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
708 goto err_disable_hca;
711 err = mlx5_satisfy_startup_pages(dev, 1);
713 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
714 goto err_pagealloc_stop;
717 err = handle_hca_cap(dev);
719 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
720 goto reclaim_boot_pages;
723 err = set_hca_ctrl(dev);
725 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
726 goto reclaim_boot_pages;
729 err = mlx5_satisfy_startup_pages(dev, 0);
731 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
732 goto reclaim_boot_pages;
735 err = mlx5_cmd_init_hca(dev);
737 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
738 goto reclaim_boot_pages;
741 mlx5_start_health_poll(dev);
743 err = mlx5_query_hca_caps(dev);
745 device_printf((&pdev->dev)->bsddev, "ERR: ""query hca failed\n");
749 err = mlx5_query_board_id(dev);
751 device_printf((&pdev->dev)->bsddev, "ERR: ""query board id failed\n");
755 err = mlx5_enable_msix(dev);
757 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
761 err = mlx5_eq_init(dev);
763 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to initialize eq\n");
767 err = mlx5_alloc_uuars(dev, &priv->uuari);
769 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
773 err = mlx5_start_eqs(dev);
775 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
779 err = alloc_comp_eqs(dev);
781 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
785 if (map_bf_area(dev))
786 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
788 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
790 mlx5_init_cq_table(dev);
791 mlx5_init_qp_table(dev);
792 mlx5_init_srq_table(dev);
793 mlx5_init_mr_table(dev);
801 mlx5_free_uuars(dev, &priv->uuari);
804 mlx5_eq_cleanup(dev);
807 mlx5_disable_msix(dev);
810 mlx5_stop_health_poll(dev);
811 if (mlx5_cmd_teardown_hca(dev)) {
812 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
817 mlx5_reclaim_startup_pages(dev);
820 mlx5_pagealloc_stop(dev);
823 mlx5_core_disable_hca(dev);
825 err_pagealloc_cleanup:
826 mlx5_pagealloc_cleanup(dev);
828 mlx5_cmd_cleanup(dev);
834 pci_clear_master(dev->pdev);
835 release_bar(dev->pdev);
838 pci_disable_device(dev->pdev);
841 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
845 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
847 struct mlx5_priv *priv = &dev->priv;
849 mlx5_cleanup_mr_table(dev);
850 mlx5_cleanup_srq_table(dev);
851 mlx5_cleanup_qp_table(dev);
852 mlx5_cleanup_cq_table(dev);
854 mlx5_wait_for_reclaim_vfs_pages(dev);
857 mlx5_free_uuars(dev, &priv->uuari);
858 mlx5_eq_cleanup(dev);
859 mlx5_disable_msix(dev);
860 mlx5_stop_health_poll(dev);
861 if (mlx5_cmd_teardown_hca(dev)) {
862 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
865 mlx5_pagealloc_stop(dev);
866 mlx5_reclaim_startup_pages(dev);
867 mlx5_core_disable_hca(dev);
868 mlx5_pagealloc_cleanup(dev);
869 mlx5_cmd_cleanup(dev);
871 pci_clear_master(dev->pdev);
872 release_bar(dev->pdev);
873 pci_disable_device(dev->pdev);
876 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
878 struct mlx5_device_context *dev_ctx;
879 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
881 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
883 dev_ctx->intf = intf;
884 dev_ctx->context = intf->add(dev);
886 if (dev_ctx->context) {
887 spin_lock_irq(&priv->ctx_lock);
888 list_add_tail(&dev_ctx->list, &priv->ctx_list);
889 spin_unlock_irq(&priv->ctx_lock);
895 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
897 struct mlx5_device_context *dev_ctx;
898 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
900 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
901 if (dev_ctx->intf == intf) {
902 spin_lock_irq(&priv->ctx_lock);
903 list_del(&dev_ctx->list);
904 spin_unlock_irq(&priv->ctx_lock);
906 intf->remove(dev, dev_ctx->context);
911 static int mlx5_register_device(struct mlx5_core_dev *dev)
913 struct mlx5_priv *priv = &dev->priv;
914 struct mlx5_interface *intf;
916 mutex_lock(&intf_mutex);
917 list_add_tail(&priv->dev_list, &dev_list);
918 list_for_each_entry(intf, &intf_list, list)
919 mlx5_add_device(intf, priv);
920 mutex_unlock(&intf_mutex);
924 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
926 struct mlx5_priv *priv = &dev->priv;
927 struct mlx5_interface *intf;
929 mutex_lock(&intf_mutex);
930 list_for_each_entry(intf, &intf_list, list)
931 mlx5_remove_device(intf, priv);
932 list_del(&priv->dev_list);
933 mutex_unlock(&intf_mutex);
936 int mlx5_register_interface(struct mlx5_interface *intf)
938 struct mlx5_priv *priv;
940 if (!intf->add || !intf->remove)
943 mutex_lock(&intf_mutex);
944 list_add_tail(&intf->list, &intf_list);
945 list_for_each_entry(priv, &dev_list, dev_list)
946 mlx5_add_device(intf, priv);
947 mutex_unlock(&intf_mutex);
951 EXPORT_SYMBOL(mlx5_register_interface);
953 void mlx5_unregister_interface(struct mlx5_interface *intf)
955 struct mlx5_priv *priv;
957 mutex_lock(&intf_mutex);
958 list_for_each_entry(priv, &dev_list, dev_list)
959 mlx5_remove_device(intf, priv);
960 list_del(&intf->list);
961 mutex_unlock(&intf_mutex);
963 EXPORT_SYMBOL(mlx5_unregister_interface);
965 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
967 struct mlx5_priv *priv = &mdev->priv;
968 struct mlx5_device_context *dev_ctx;
972 spin_lock_irqsave(&priv->ctx_lock, flags);
974 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
975 if ((dev_ctx->intf->protocol == protocol) &&
976 dev_ctx->intf->get_dev) {
977 result = dev_ctx->intf->get_dev(dev_ctx->context);
981 spin_unlock_irqrestore(&priv->ctx_lock, flags);
985 EXPORT_SYMBOL(mlx5_get_protocol_dev);
987 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
990 struct mlx5_priv *priv = &dev->priv;
991 struct mlx5_device_context *dev_ctx;
994 spin_lock_irqsave(&priv->ctx_lock, flags);
996 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
997 if (dev_ctx->intf->event)
998 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1000 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1003 struct mlx5_core_event_handler {
1004 void (*event)(struct mlx5_core_dev *dev,
1005 enum mlx5_dev_event event,
1010 static int init_one(struct pci_dev *pdev,
1011 const struct pci_device_id *id)
1013 struct mlx5_core_dev *dev;
1014 struct mlx5_priv *priv;
1017 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1020 priv->pci_dev_data = id->driver_data;
1022 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) {
1023 printf("mlx5_core: WARN: ""selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1024 prof_sel = MLX5_DEFAULT_PROF;
1026 dev->profile = &profiles[prof_sel];
1027 dev->event = mlx5_core_event;
1029 INIT_LIST_HEAD(&priv->ctx_list);
1030 spin_lock_init(&priv->ctx_lock);
1031 err = mlx5_dev_init(dev, pdev);
1033 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_dev_init failed %d\n", err);
1037 err = mlx5_register_device(dev);
1039 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_register_device failed %d\n", err);
1047 mlx5_dev_cleanup(dev);
1053 static void remove_one(struct pci_dev *pdev)
1055 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1057 mlx5_unregister_device(dev);
1058 mlx5_dev_cleanup(dev);
1062 static const struct pci_device_id mlx5_core_pci_table[] = {
1063 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1064 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1065 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1066 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1067 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1068 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1069 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1070 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1071 { PCI_VDEVICE(MELLANOX, 4121) },
1072 { PCI_VDEVICE(MELLANOX, 4122) },
1073 { PCI_VDEVICE(MELLANOX, 4123) },
1074 { PCI_VDEVICE(MELLANOX, 4124) },
1075 { PCI_VDEVICE(MELLANOX, 4125) },
1076 { PCI_VDEVICE(MELLANOX, 4126) },
1077 { PCI_VDEVICE(MELLANOX, 4127) },
1078 { PCI_VDEVICE(MELLANOX, 4128) },
1079 { PCI_VDEVICE(MELLANOX, 4129) },
1080 { PCI_VDEVICE(MELLANOX, 4130) },
1081 { PCI_VDEVICE(MELLANOX, 4131) },
1082 { PCI_VDEVICE(MELLANOX, 4132) },
1083 { PCI_VDEVICE(MELLANOX, 4133) },
1084 { PCI_VDEVICE(MELLANOX, 4134) },
1085 { PCI_VDEVICE(MELLANOX, 4135) },
1086 { PCI_VDEVICE(MELLANOX, 4136) },
1087 { PCI_VDEVICE(MELLANOX, 4137) },
1088 { PCI_VDEVICE(MELLANOX, 4138) },
1089 { PCI_VDEVICE(MELLANOX, 4139) },
1090 { PCI_VDEVICE(MELLANOX, 4140) },
1091 { PCI_VDEVICE(MELLANOX, 4141) },
1092 { PCI_VDEVICE(MELLANOX, 4142) },
1093 { PCI_VDEVICE(MELLANOX, 4143) },
1094 { PCI_VDEVICE(MELLANOX, 4144) },
1098 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1100 static struct pci_driver mlx5_core_driver = {
1101 .name = DRIVER_NAME,
1102 .id_table = mlx5_core_pci_table,
1104 .remove = remove_one
1107 static int __init init(void)
1111 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1112 if (!mlx5_core_wq) {
1118 err = pci_register_driver(&mlx5_core_driver);
1126 mlx5_health_cleanup();
1127 destroy_workqueue(mlx5_core_wq);
1132 static void __exit cleanup(void)
1134 pci_unregister_driver(&mlx5_core_driver);
1135 mlx5_health_cleanup();
1136 destroy_workqueue(mlx5_core_wq);
1140 module_exit(cleanup);