sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 static void
 310 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 311 {
 312         struct mlx5_core_dev *mdev = priv->mdev;
 313         struct mlx5e_pport_stats *s = &priv->stats.pport;
 314         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 315         u32 *in;
 316         u32 *out;
 317         u64 *ptr;
 318         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 319         unsigned x;
 320         unsigned y;
 321
 322         in = mlx5_vzalloc(sz);
 323         out = mlx5_vzalloc(sz);
 324         if (in == NULL || out == NULL)
 325                 goto free_out;
 326
 327         ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 328
 329         MLX5_SET(ppcnt_reg, in, local_port, 1);
 330
 331         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 332         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 333         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 334                 s->arg[y] = be64toh(ptr[x]);
 335
 336         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 337         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 338         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 339                 s->arg[y] = be64toh(ptr[x]);
 340         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 341             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 342                 s_debug->arg[y] = be64toh(ptr[x]);
 343
 344         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 345         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 346         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 347                 s_debug->arg[y] = be64toh(ptr[x]);
 348
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 352                 s_debug->arg[y] = be64toh(ptr[x]);
 353 free_out:
 354         kvfree(in);
 355         kvfree(out);
 356 }
 357
 358 static void
 359 mlx5e_update_stats_work(struct work_struct *work)
 360 {
 361         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 362             update_stats_work);
 363         struct mlx5_core_dev *mdev = priv->mdev;
 364         struct mlx5e_vport_stats *s = &priv->stats.vport;
 365         struct mlx5e_rq_stats *rq_stats;
 366         struct mlx5e_sq_stats *sq_stats;
 367         struct buf_ring *sq_br;
 368 #if (__FreeBSD_version < 1100000)
 369         struct ifnet *ifp = priv->ifp;
 370 #endif
 371
 372         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 373         u32 *out;
 374         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 375         u64 tso_packets = 0;
 376         u64 tso_bytes = 0;
 377         u64 tx_queue_dropped = 0;
 378         u64 tx_defragged = 0;
 379         u64 tx_offload_none = 0;
 380         u64 lro_packets = 0;
 381         u64 lro_bytes = 0;
 382         u64 sw_lro_queued = 0;
 383         u64 sw_lro_flushed = 0;
 384         u64 rx_csum_none = 0;
 385         u64 rx_wqe_err = 0;
 386         u32 rx_out_of_buffer = 0;
 387         int i;
 388         int j;
 389
 390         PRIV_LOCK(priv);
 391         out = mlx5_vzalloc(outlen);
 392         if (out == NULL)
 393                 goto free_out;
 394         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 395                 goto free_out;
 396
 397         /* Collect firts the SW counters and then HW for consistency */
 398         for (i = 0; i < priv->params.num_channels; i++) {
 399                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 400
 401                 rq_stats = &priv->channel[i]->rq.stats;
 402
 403                 /* collect stats from LRO */
 404                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 405                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 406                 sw_lro_queued += rq_stats->sw_lro_queued;
 407                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 408                 lro_packets += rq_stats->lro_packets;
 409                 lro_bytes += rq_stats->lro_bytes;
 410                 rx_csum_none += rq_stats->csum_none;
 411                 rx_wqe_err += rq_stats->wqe_err;
 412
 413                 for (j = 0; j < priv->num_tc; j++) {
 414                         sq_stats = &priv->channel[i]->sq[j].stats;
 415                         sq_br = priv->channel[i]->sq[j].br;
 416
 417                         tso_packets += sq_stats->tso_packets;
 418                         tso_bytes += sq_stats->tso_bytes;
 419                         tx_queue_dropped += sq_stats->dropped;
 420                         tx_queue_dropped += sq_br->br_drops;
 421                         tx_defragged += sq_stats->defragged;
 422                         tx_offload_none += sq_stats->csum_offload_none;
 423                 }
 424         }
 425
 426         /* update counters */
 427         s->tso_packets = tso_packets;
 428         s->tso_bytes = tso_bytes;
 429         s->tx_queue_dropped = tx_queue_dropped;
 430         s->tx_defragged = tx_defragged;
 431         s->lro_packets = lro_packets;
 432         s->lro_bytes = lro_bytes;
 433         s->sw_lro_queued = sw_lro_queued;
 434         s->sw_lro_flushed = sw_lro_flushed;
 435         s->rx_csum_none = rx_csum_none;
 436         s->rx_wqe_err = rx_wqe_err;
 437
 438         /* HW counters */
 439         memset(in, 0, sizeof(in));
 440
 441         MLX5_SET(query_vport_counter_in, in, opcode,
 442             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 443         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 444         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 445
 446         memset(out, 0, outlen);
 447
 448         /* get number of out-of-buffer drops first */
 449         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 450             &rx_out_of_buffer))
 451                 goto free_out;
 452
 453         /* accumulate difference into a 64-bit counter */
 454         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 455         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 456
 457         /* get port statistics */
 458         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 459                 goto free_out;
 460
 461 #define MLX5_GET_CTR(out, x) \
 462         MLX5_GET64(query_vport_counter_out, out, x)
 463
 464         s->rx_error_packets =
 465             MLX5_GET_CTR(out, received_errors.packets);
 466         s->rx_error_bytes =
 467             MLX5_GET_CTR(out, received_errors.octets);
 468         s->tx_error_packets =
 469             MLX5_GET_CTR(out, transmit_errors.packets);
 470         s->tx_error_bytes =
 471             MLX5_GET_CTR(out, transmit_errors.octets);
 472
 473         s->rx_unicast_packets =
 474             MLX5_GET_CTR(out, received_eth_unicast.packets);
 475         s->rx_unicast_bytes =
 476             MLX5_GET_CTR(out, received_eth_unicast.octets);
 477         s->tx_unicast_packets =
 478             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 479         s->tx_unicast_bytes =
 480             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 481
 482         s->rx_multicast_packets =
 483             MLX5_GET_CTR(out, received_eth_multicast.packets);
 484         s->rx_multicast_bytes =
 485             MLX5_GET_CTR(out, received_eth_multicast.octets);
 486         s->tx_multicast_packets =
 487             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 488         s->tx_multicast_bytes =
 489             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 490
 491         s->rx_broadcast_packets =
 492             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 493         s->rx_broadcast_bytes =
 494             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 495         s->tx_broadcast_packets =
 496             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 497         s->tx_broadcast_bytes =
 498             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 499
 500         s->rx_packets =
 501             s->rx_unicast_packets +
 502             s->rx_multicast_packets +
 503             s->rx_broadcast_packets -
 504             s->rx_out_of_buffer;
 505         s->rx_bytes =
 506             s->rx_unicast_bytes +
 507             s->rx_multicast_bytes +
 508             s->rx_broadcast_bytes;
 509         s->tx_packets =
 510             s->tx_unicast_packets +
 511             s->tx_multicast_packets +
 512             s->tx_broadcast_packets;
 513         s->tx_bytes =
 514             s->tx_unicast_bytes +
 515             s->tx_multicast_bytes +
 516             s->tx_broadcast_bytes;
 517
 518         /* Update calculated offload counters */
 519         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 520         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 521
 522         /* Update per port counters */
 523         mlx5e_update_pport_counters(priv);
 524
 525 #if (__FreeBSD_version < 1100000)
 526         /* no get_counters interface in fbsd 10 */
 527         ifp->if_ipackets = s->rx_packets;
 528         ifp->if_ierrors = s->rx_error_packets;
 529         ifp->if_iqdrops = s->rx_out_of_buffer;
 530         ifp->if_opackets = s->tx_packets;
 531         ifp->if_oerrors = s->tx_error_packets;
 532         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 533         ifp->if_ibytes = s->rx_bytes;
 534         ifp->if_obytes = s->tx_bytes;
 535 #endif
 536
 537 free_out:
 538         kvfree(out);
 539         PRIV_UNLOCK(priv);
 540 }
 541
 542 static void
 543 mlx5e_update_stats(void *arg)
 544 {
 545         struct mlx5e_priv *priv = arg;
 546
 547         schedule_work(&priv->update_stats_work);
 548
 549         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 550 }
 551
 552 static void
 553 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 554     enum mlx5_dev_event event)
 555 {
 556         switch (event) {
 557         case MLX5_DEV_EVENT_PORT_UP:
 558         case MLX5_DEV_EVENT_PORT_DOWN:
 559                 schedule_work(&priv->update_carrier_work);
 560                 break;
 561
 562         default:
 563                 break;
 564         }
 565 }
 566
 567 static void
 568 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 569     enum mlx5_dev_event event, unsigned long param)
 570 {
 571         struct mlx5e_priv *priv = vpriv;
 572
 573         mtx_lock(&priv->async_events_mtx);
 574         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 575                 mlx5e_async_event_sub(priv, event);
 576         mtx_unlock(&priv->async_events_mtx);
 577 }
 578
 579 static void
 580 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 581 {
 582         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 583 }
 584
 585 static void
 586 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 587 {
 588         mtx_lock(&priv->async_events_mtx);
 589         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 590         mtx_unlock(&priv->async_events_mtx);
 591 }
 592
 593 static const char *mlx5e_rq_stats_desc[] = {
 594         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 595 };
 596
 597 static int
 598 mlx5e_create_rq(struct mlx5e_channel *c,
 599     struct mlx5e_rq_param *param,
 600     struct mlx5e_rq *rq)
 601 {
 602         struct mlx5e_priv *priv = c->priv;
 603         struct mlx5_core_dev *mdev = priv->mdev;
 604         char buffer[16];
 605         void *rqc = param->rqc;
 606         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 607         int wq_sz;
 608         int err;
 609         int i;
 610
 611         /* Create DMA descriptor TAG */
 612         if ((err = -bus_dma_tag_create(
 613             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 614             1,                          /* any alignment */
 615             0,                          /* no boundary */
 616             BUS_SPACE_MAXADDR,          /* lowaddr */
 617             BUS_SPACE_MAXADDR,          /* highaddr */
 618             NULL, NULL,                 /* filter, filterarg */
 619             MJUM16BYTES,                /* maxsize */
 620             1,                          /* nsegments */
 621             MJUM16BYTES,                /* maxsegsize */
 622             0,                          /* flags */
 623             NULL, NULL,                 /* lockfunc, lockfuncarg */
 624             &rq->dma_tag)))
 625                 goto done;
 626
 627         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 628             &rq->wq_ctrl);
 629         if (err)
 630                 goto err_free_dma_tag;
 631
 632         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 633
 634         if (priv->params.hw_lro_en) {
 635                 rq->wqe_sz = priv->params.lro_wqe_sz;
 636         } else {
 637                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 638         }
 639         if (rq->wqe_sz > MJUM16BYTES) {
 640                 err = -ENOMEM;
 641                 goto err_rq_wq_destroy;
 642         } else if (rq->wqe_sz > MJUM9BYTES) {
 643                 rq->wqe_sz = MJUM16BYTES;
 644         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 645                 rq->wqe_sz = MJUM9BYTES;
 646         } else if (rq->wqe_sz > MCLBYTES) {
 647                 rq->wqe_sz = MJUMPAGESIZE;
 648         } else {
 649                 rq->wqe_sz = MCLBYTES;
 650         }
 651
 652         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 653         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 654         if (rq->mbuf == NULL) {
 655                 err = -ENOMEM;
 656                 goto err_rq_wq_destroy;
 657         }
 658         for (i = 0; i != wq_sz; i++) {
 659                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 660                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 661
 662                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 663                 if (err != 0) {
 664                         while (i--)
 665                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 666                         goto err_rq_mbuf_free;
 667                 }
 668                 wqe->data.lkey = c->mkey_be;
 669                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 670         }
 671
 672         rq->pdev = c->pdev;
 673         rq->ifp = c->ifp;
 674         rq->channel = c;
 675         rq->ix = c->ix;
 676
 677         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 678         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 679             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 680             rq->stats.arg);
 681
 682 #ifdef HAVE_TURBO_LRO
 683         if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
 684                 rq->lro.mbuf = NULL;
 685 #else
 686         if (tcp_lro_init(&rq->lro))
 687                 rq->lro.lro_cnt = 0;
 688         else
 689                 rq->lro.ifp = c->ifp;
 690 #endif
 691         return (0);
 692
 693 err_rq_mbuf_free:
 694         free(rq->mbuf, M_MLX5EN);
 695 err_rq_wq_destroy:
 696         mlx5_wq_destroy(&rq->wq_ctrl);
 697 err_free_dma_tag:
 698         bus_dma_tag_destroy(rq->dma_tag);
 699 done:
 700         return (err);
 701 }
 702
 703 static void
 704 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 705 {
 706         int wq_sz;
 707         int i;
 708
 709         /* destroy all sysctl nodes */
 710         sysctl_ctx_free(&rq->stats.ctx);
 711
 712         /* free leftover LRO packets, if any */
 713 #ifdef HAVE_TURBO_LRO
 714         tcp_tlro_free(&rq->lro);
 715 #else
 716         tcp_lro_free(&rq->lro);
 717 #endif
 718         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 719         for (i = 0; i != wq_sz; i++) {
 720                 if (rq->mbuf[i].mbuf != NULL) {
 721                         bus_dmamap_unload(rq->dma_tag,
 722                             rq->mbuf[i].dma_map);
 723                         m_freem(rq->mbuf[i].mbuf);
 724                 }
 725                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 726         }
 727         free(rq->mbuf, M_MLX5EN);
 728         mlx5_wq_destroy(&rq->wq_ctrl);
 729 }
 730
 731 static int
 732 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 733 {
 734         struct mlx5e_channel *c = rq->channel;
 735         struct mlx5e_priv *priv = c->priv;
 736         struct mlx5_core_dev *mdev = priv->mdev;
 737
 738         void *in;
 739         void *rqc;
 740         void *wq;
 741         int inlen;
 742         int err;
 743
 744         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 745             sizeof(u64) * rq->wq_ctrl.buf.npages;
 746         in = mlx5_vzalloc(inlen);
 747         if (in == NULL)
 748                 return (-ENOMEM);
 749
 750         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 751         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 752
 753         memcpy(rqc, param->rqc, sizeof(param->rqc));
 754
 755         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 756         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 757         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 758         if (priv->counter_set_id >= 0)
 759                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 760         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 761             PAGE_SHIFT);
 762         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 763
 764         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 765             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 766
 767         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 768
 769         kvfree(in);
 770
 771         return (err);
 772 }
 773
 774 static int
 775 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 776 {
 777         struct mlx5e_channel *c = rq->channel;
 778         struct mlx5e_priv *priv = c->priv;
 779         struct mlx5_core_dev *mdev = priv->mdev;
 780
 781         void *in;
 782         void *rqc;
 783         int inlen;
 784         int err;
 785
 786         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 787         in = mlx5_vzalloc(inlen);
 788         if (in == NULL)
 789                 return (-ENOMEM);
 790
 791         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 792
 793         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 794         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 795         MLX5_SET(rqc, rqc, state, next_state);
 796
 797         err = mlx5_core_modify_rq(mdev, in, inlen);
 798
 799         kvfree(in);
 800
 801         return (err);
 802 }
 803
 804 static void
 805 mlx5e_disable_rq(struct mlx5e_rq *rq)
 806 {
 807         struct mlx5e_channel *c = rq->channel;
 808         struct mlx5e_priv *priv = c->priv;
 809         struct mlx5_core_dev *mdev = priv->mdev;
 810
 811         mlx5_core_destroy_rq(mdev, rq->rqn);
 812 }
 813
 814 static int
 815 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 816 {
 817         struct mlx5e_channel *c = rq->channel;
 818         struct mlx5e_priv *priv = c->priv;
 819         struct mlx5_wq_ll *wq = &rq->wq;
 820         int i;
 821
 822         for (i = 0; i < 1000; i++) {
 823                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 824                         return (0);
 825
 826                 msleep(4);
 827         }
 828         return (-ETIMEDOUT);
 829 }
 830
 831 static int
 832 mlx5e_open_rq(struct mlx5e_channel *c,
 833     struct mlx5e_rq_param *param,
 834     struct mlx5e_rq *rq)
 835 {
 836         int err;
 837
 838         err = mlx5e_create_rq(c, param, rq);
 839         if (err)
 840                 return (err);
 841
 842         err = mlx5e_enable_rq(rq, param);
 843         if (err)
 844                 goto err_destroy_rq;
 845
 846         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 847         if (err)
 848                 goto err_disable_rq;
 849
 850         c->rq.enabled = 1;
 851
 852         return (0);
 853
 854 err_disable_rq:
 855         mlx5e_disable_rq(rq);
 856 err_destroy_rq:
 857         mlx5e_destroy_rq(rq);
 858
 859         return (err);
 860 }
 861
 862 static void
 863 mlx5e_close_rq(struct mlx5e_rq *rq)
 864 {
 865         rq->enabled = 0;
 866         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 867 }
 868
 869 static void
 870 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 871 {
 872         /* wait till RQ is empty */
 873         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 874                 msleep(4);
 875                 rq->cq.mcq.comp(&rq->cq.mcq);
 876         }
 877
 878         mlx5e_disable_rq(rq);
 879         mlx5e_destroy_rq(rq);
 880 }
 881
 882 static void
 883 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 884 {
 885         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 886         int x;
 887
 888         for (x = 0; x != wq_sz; x++)
 889                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 890         free(sq->mbuf, M_MLX5EN);
 891 }
 892
 893 static int
 894 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 895 {
 896         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 897         int err;
 898         int x;
 899
 900         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 901         if (sq->mbuf == NULL)
 902                 return (-ENOMEM);
 903
 904         /* Create DMA descriptor MAPs */
 905         for (x = 0; x != wq_sz; x++) {
 906                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 907                 if (err != 0) {
 908                         while (x--)
 909                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 910                         free(sq->mbuf, M_MLX5EN);
 911                         return (err);
 912                 }
 913         }
 914         return (0);
 915 }
 916
 917 static const char *mlx5e_sq_stats_desc[] = {
 918         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 919 };
 920
 921 static int
 922 mlx5e_create_sq(struct mlx5e_channel *c,
 923     int tc,
 924     struct mlx5e_sq_param *param,
 925     struct mlx5e_sq *sq)
 926 {
 927         struct mlx5e_priv *priv = c->priv;
 928         struct mlx5_core_dev *mdev = priv->mdev;
 929         char buffer[16];
 930
 931         void *sqc = param->sqc;
 932         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 933 #ifdef RSS
 934         cpuset_t cpu_mask;
 935         int cpu_id;
 936 #endif
 937         int err;
 938
 939         /* Create DMA descriptor TAG */
 940         if ((err = -bus_dma_tag_create(
 941             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 942             1,                          /* any alignment */
 943             0,                          /* no boundary */
 944             BUS_SPACE_MAXADDR,          /* lowaddr */
 945             BUS_SPACE_MAXADDR,          /* highaddr */
 946             NULL, NULL,                 /* filter, filterarg */
 947             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 948             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 949             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 950             0,                          /* flags */
 951             NULL, NULL,                 /* lockfunc, lockfuncarg */
 952             &sq->dma_tag)))
 953                 goto done;
 954
 955         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 956         if (err)
 957                 goto err_free_dma_tag;
 958
 959         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 960             &sq->wq_ctrl);
 961         if (err)
 962                 goto err_unmap_free_uar;
 963
 964         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 965         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 966
 967         err = mlx5e_alloc_sq_db(sq);
 968         if (err)
 969                 goto err_sq_wq_destroy;
 970
 971         sq->pdev = c->pdev;
 972         sq->mkey_be = c->mkey_be;
 973         sq->ifp = priv->ifp;
 974         sq->priv = priv;
 975         sq->tc = tc;
 976
 977         sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
 978             M_WAITOK, &sq->lock);
 979         if (sq->br == NULL) {
 980                 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
 981                     __func__);
 982                 err = -ENOMEM;
 983                 goto err_free_sq_db;
 984         }
 985
 986         sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
 987             taskqueue_thread_enqueue, &sq->sq_tq);
 988         if (sq->sq_tq == NULL) {
 989                 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
 990                     __func__);
 991                 err = -ENOMEM;
 992                 goto err_free_drbr;
 993         }
 994
 995         TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
 996 #ifdef RSS
 997         cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
 998         CPU_SETOF(cpu_id, &cpu_mask);
 999         taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1000             "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1001 #else
1002         taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1003             "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1004 #endif
1005         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1006         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1007             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1008             sq->stats.arg);
1009
1010         return (0);
1011
1012 err_free_drbr:
1013         buf_ring_free(sq->br, M_MLX5EN);
1014 err_free_sq_db:
1015         mlx5e_free_sq_db(sq);
1016 err_sq_wq_destroy:
1017         mlx5_wq_destroy(&sq->wq_ctrl);
1018
1019 err_unmap_free_uar:
1020         mlx5_unmap_free_uar(mdev, &sq->uar);
1021
1022 err_free_dma_tag:
1023         bus_dma_tag_destroy(sq->dma_tag);
1024 done:
1025         return (err);
1026 }
1027
1028 static void
1029 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1030 {
1031         /* destroy all sysctl nodes */
1032         sysctl_ctx_free(&sq->stats.ctx);
1033
1034         mlx5e_free_sq_db(sq);
1035         mlx5_wq_destroy(&sq->wq_ctrl);
1036         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1037         taskqueue_drain(sq->sq_tq, &sq->sq_task);
1038         taskqueue_free(sq->sq_tq);
1039         buf_ring_free(sq->br, M_MLX5EN);
1040 }
1041
1042 static int
1043 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1044 {
1045         void *in;
1046         void *sqc;
1047         void *wq;
1048         int inlen;
1049         int err;
1050
1051         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1052             sizeof(u64) * sq->wq_ctrl.buf.npages;
1053         in = mlx5_vzalloc(inlen);
1054         if (in == NULL)
1055                 return (-ENOMEM);
1056
1057         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1058         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1059
1060         memcpy(sqc, param->sqc, sizeof(param->sqc));
1061
1062         MLX5_SET(sqc, sqc, tis_num_0, sq->priv->tisn[sq->tc]);
1063         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1064         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1065         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1066         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1067
1068         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1069         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1070         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1071             PAGE_SHIFT);
1072         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1073
1074         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1075             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1076
1077         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1078
1079         kvfree(in);
1080
1081         return (err);
1082 }
1083
1084 static int
1085 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1086 {
1087         void *in;
1088         void *sqc;
1089         int inlen;
1090         int err;
1091
1092         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1093         in = mlx5_vzalloc(inlen);
1094         if (in == NULL)
1095                 return (-ENOMEM);
1096
1097         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1098
1099         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1100         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1101         MLX5_SET(sqc, sqc, state, next_state);
1102
1103         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1104
1105         kvfree(in);
1106
1107         return (err);
1108 }
1109
1110 static void
1111 mlx5e_disable_sq(struct mlx5e_sq *sq)
1112 {
1113
1114         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1115 }
1116
1117 static int
1118 mlx5e_open_sq(struct mlx5e_channel *c,
1119     int tc,
1120     struct mlx5e_sq_param *param,
1121     struct mlx5e_sq *sq)
1122 {
1123         int err;
1124
1125         err = mlx5e_create_sq(c, tc, param, sq);
1126         if (err)
1127                 return (err);
1128
1129         err = mlx5e_enable_sq(sq, param);
1130         if (err)
1131                 goto err_destroy_sq;
1132
1133         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1134         if (err)
1135                 goto err_disable_sq;
1136
1137         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1138
1139         return (0);
1140
1141 err_disable_sq:
1142         mlx5e_disable_sq(sq);
1143 err_destroy_sq:
1144         mlx5e_destroy_sq(sq);
1145
1146         return (err);
1147 }
1148
1149 static void
1150 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1151 {
1152         /* fill up remainder with NOPs */
1153         while (sq->cev_counter != 0) {
1154                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1155                         if (can_sleep != 0) {
1156                                 mtx_unlock(&sq->lock);
1157                                 msleep(4);
1158                                 mtx_lock(&sq->lock);
1159                         } else {
1160                                 goto done;
1161                         }
1162                 }
1163                 /* send a single NOP */
1164                 mlx5e_send_nop(sq, 1);
1165                 wmb();
1166         }
1167 done:
1168         /* Check if we need to write the doorbell */
1169         if (likely(sq->doorbell.d64 != 0)) {
1170                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1171                 sq->doorbell.d64 = 0;
1172         }
1173         return;
1174 }
1175
1176 void
1177 mlx5e_sq_cev_timeout(void *arg)
1178 {
1179         struct mlx5e_sq *sq = arg;
1180
1181         mtx_assert(&sq->lock, MA_OWNED);
1182
1183         /* check next state */
1184         switch (sq->cev_next_state) {
1185         case MLX5E_CEV_STATE_SEND_NOPS:
1186                 /* fill TX ring with NOPs, if any */
1187                 mlx5e_sq_send_nops_locked(sq, 0);
1188
1189                 /* check if completed */
1190                 if (sq->cev_counter == 0) {
1191                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1192                         return;
1193                 }
1194                 break;
1195         default:
1196                 /* send NOPs on next timeout */
1197                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1198                 break;
1199         }
1200
1201         /* restart timer */
1202         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1203 }
1204
1205 static void
1206 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1207 {
1208
1209         mtx_lock(&sq->lock);
1210         /* teardown event factor timer, if any */
1211         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1212         callout_stop(&sq->cev_callout);
1213
1214         /* send dummy NOPs in order to flush the transmit ring */
1215         mlx5e_sq_send_nops_locked(sq, 1);
1216         mtx_unlock(&sq->lock);
1217
1218         /* make sure it is safe to free the callout */
1219         callout_drain(&sq->cev_callout);
1220
1221         /* error out remaining requests */
1222         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1223
1224         /* wait till SQ is empty */
1225         mtx_lock(&sq->lock);
1226         while (sq->cc != sq->pc) {
1227                 mtx_unlock(&sq->lock);
1228                 msleep(4);
1229                 sq->cq.mcq.comp(&sq->cq.mcq);
1230                 mtx_lock(&sq->lock);
1231         }
1232         mtx_unlock(&sq->lock);
1233
1234         mlx5e_disable_sq(sq);
1235         mlx5e_destroy_sq(sq);
1236 }
1237
1238 static int
1239 mlx5e_create_cq(struct mlx5e_priv *priv,
1240     struct mlx5e_cq_param *param,
1241     struct mlx5e_cq *cq,
1242     mlx5e_cq_comp_t *comp,
1243     int eq_ix)
1244 {
1245         struct mlx5_core_dev *mdev = priv->mdev;
1246         struct mlx5_core_cq *mcq = &cq->mcq;
1247         int eqn_not_used;
1248         int irqn;
1249         int err;
1250         u32 i;
1251
1252         param->wq.buf_numa_node = 0;
1253         param->wq.db_numa_node = 0;
1254
1255         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1256             &cq->wq_ctrl);
1257         if (err)
1258                 return (err);
1259
1260         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1261
1262         mcq->cqe_sz = 64;
1263         mcq->set_ci_db = cq->wq_ctrl.db.db;
1264         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1265         *mcq->set_ci_db = 0;
1266         *mcq->arm_db = 0;
1267         mcq->vector = eq_ix;
1268         mcq->comp = comp;
1269         mcq->event = mlx5e_cq_error_event;
1270         mcq->irqn = irqn;
1271         mcq->uar = &priv->cq_uar;
1272
1273         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1274                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1275
1276                 cqe->op_own = 0xf1;
1277         }
1278
1279         cq->priv = priv;
1280
1281         return (0);
1282 }
1283
1284 static void
1285 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1286 {
1287         mlx5_wq_destroy(&cq->wq_ctrl);
1288 }
1289
1290 static int
1291 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1292 {
1293         struct mlx5_core_cq *mcq = &cq->mcq;
1294         void *in;
1295         void *cqc;
1296         int inlen;
1297         int irqn_not_used;
1298         int eqn;
1299         int err;
1300
1301         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1302             sizeof(u64) * cq->wq_ctrl.buf.npages;
1303         in = mlx5_vzalloc(inlen);
1304         if (in == NULL)
1305                 return (-ENOMEM);
1306
1307         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1308
1309         memcpy(cqc, param->cqc, sizeof(param->cqc));
1310
1311         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1312             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1313
1314         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1315
1316         MLX5_SET(cqc, cqc, c_eqn, eqn);
1317         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1318         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1319             PAGE_SHIFT);
1320         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1321
1322         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1323
1324         kvfree(in);
1325
1326         if (err)
1327                 return (err);
1328
1329         mlx5e_cq_arm(cq);
1330
1331         return (0);
1332 }
1333
1334 static void
1335 mlx5e_disable_cq(struct mlx5e_cq *cq)
1336 {
1337
1338         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1339 }
1340
1341 int
1342 mlx5e_open_cq(struct mlx5e_priv *priv,
1343     struct mlx5e_cq_param *param,
1344     struct mlx5e_cq *cq,
1345     mlx5e_cq_comp_t *comp,
1346     int eq_ix)
1347 {
1348         int err;
1349
1350         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1351         if (err)
1352                 return (err);
1353
1354         err = mlx5e_enable_cq(cq, param, eq_ix);
1355         if (err)
1356                 goto err_destroy_cq;
1357
1358         return (0);
1359
1360 err_destroy_cq:
1361         mlx5e_destroy_cq(cq);
1362
1363         return (err);
1364 }
1365
1366 void
1367 mlx5e_close_cq(struct mlx5e_cq *cq)
1368 {
1369         mlx5e_disable_cq(cq);
1370         mlx5e_destroy_cq(cq);
1371 }
1372
1373 static int
1374 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1375     struct mlx5e_channel_param *cparam)
1376 {
1377         int err;
1378         int tc;
1379
1380         for (tc = 0; tc < c->num_tc; tc++) {
1381                 /* open completion queue */
1382                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1383                     &mlx5e_tx_cq_comp, c->ix);
1384                 if (err)
1385                         goto err_close_tx_cqs;
1386         }
1387         return (0);
1388
1389 err_close_tx_cqs:
1390         for (tc--; tc >= 0; tc--)
1391                 mlx5e_close_cq(&c->sq[tc].cq);
1392
1393         return (err);
1394 }
1395
1396 static void
1397 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1398 {
1399         int tc;
1400
1401         for (tc = 0; tc < c->num_tc; tc++)
1402                 mlx5e_close_cq(&c->sq[tc].cq);
1403 }
1404
1405 static int
1406 mlx5e_open_sqs(struct mlx5e_channel *c,
1407     struct mlx5e_channel_param *cparam)
1408 {
1409         int err;
1410         int tc;
1411
1412         for (tc = 0; tc < c->num_tc; tc++) {
1413                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1414                 if (err)
1415                         goto err_close_sqs;
1416         }
1417
1418         return (0);
1419
1420 err_close_sqs:
1421         for (tc--; tc >= 0; tc--)
1422                 mlx5e_close_sq_wait(&c->sq[tc]);
1423
1424         return (err);
1425 }
1426
1427 static void
1428 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1429 {
1430         int tc;
1431
1432         for (tc = 0; tc < c->num_tc; tc++)
1433                 mlx5e_close_sq_wait(&c->sq[tc]);
1434 }
1435
1436 static void
1437 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1438 {
1439         int tc;
1440
1441         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1442
1443         for (tc = 0; tc < c->num_tc; tc++) {
1444                 struct mlx5e_sq *sq = c->sq + tc;
1445
1446                 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1447                 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1448                     MTX_DEF);
1449
1450                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1451
1452                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1453
1454                 /* ensure the TX completion event factor is not zero */
1455                 if (sq->cev_factor == 0)
1456                         sq->cev_factor = 1;
1457         }
1458 }
1459
1460 static void
1461 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1462 {
1463         int tc;
1464
1465         mtx_destroy(&c->rq.mtx);
1466
1467         for (tc = 0; tc < c->num_tc; tc++) {
1468                 mtx_destroy(&c->sq[tc].lock);
1469                 mtx_destroy(&c->sq[tc].comp_lock);
1470         }
1471 }
1472
1473 static int
1474 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1475     struct mlx5e_channel_param *cparam,
1476     struct mlx5e_channel *volatile *cp)
1477 {
1478         struct mlx5e_channel *c;
1479         int err;
1480
1481         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1482         if (c == NULL)
1483                 return (-ENOMEM);
1484
1485         c->priv = priv;
1486         c->ix = ix;
1487         c->cpu = 0;
1488         c->pdev = &priv->mdev->pdev->dev;
1489         c->ifp = priv->ifp;
1490         c->mkey_be = cpu_to_be32(priv->mr.key);
1491         c->num_tc = priv->num_tc;
1492
1493         /* init mutexes */
1494         mlx5e_chan_mtx_init(c);
1495
1496         /* open transmit completion queue */
1497         err = mlx5e_open_tx_cqs(c, cparam);
1498         if (err)
1499                 goto err_free;
1500
1501         /* open receive completion queue */
1502         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1503             &mlx5e_rx_cq_comp, c->ix);
1504         if (err)
1505                 goto err_close_tx_cqs;
1506
1507         err = mlx5e_open_sqs(c, cparam);
1508         if (err)
1509                 goto err_close_rx_cq;
1510
1511         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1512         if (err)
1513                 goto err_close_sqs;
1514
1515         /* store channel pointer */
1516         *cp = c;
1517
1518         /* poll receive queue initially */
1519         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1520
1521         return (0);
1522
1523 err_close_sqs:
1524         mlx5e_close_sqs_wait(c);
1525
1526 err_close_rx_cq:
1527         mlx5e_close_cq(&c->rq.cq);
1528
1529 err_close_tx_cqs:
1530         mlx5e_close_tx_cqs(c);
1531
1532 err_free:
1533         /* destroy mutexes */
1534         mlx5e_chan_mtx_destroy(c);
1535         free(c, M_MLX5EN);
1536         return (err);
1537 }
1538
1539 static void
1540 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1541 {
1542         struct mlx5e_channel *c = *pp;
1543
1544         /* check if channel is already closed */
1545         if (c == NULL)
1546                 return;
1547         mlx5e_close_rq(&c->rq);
1548 }
1549
1550 static void
1551 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1552 {
1553         struct mlx5e_channel *c = *pp;
1554
1555         /* check if channel is already closed */
1556         if (c == NULL)
1557                 return;
1558         /* ensure channel pointer is no longer used */
1559         *pp = NULL;
1560
1561         mlx5e_close_rq_wait(&c->rq);
1562         mlx5e_close_sqs_wait(c);
1563         mlx5e_close_cq(&c->rq.cq);
1564         mlx5e_close_tx_cqs(c);
1565         /* destroy mutexes */
1566         mlx5e_chan_mtx_destroy(c);
1567         free(c, M_MLX5EN);
1568 }
1569
1570 static void
1571 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1572     struct mlx5e_rq_param *param)
1573 {
1574         void *rqc = param->rqc;
1575         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1576
1577         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1578         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1579         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1580         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1581         MLX5_SET(wq, wq, pd, priv->pdn);
1582
1583         param->wq.buf_numa_node = 0;
1584         param->wq.db_numa_node = 0;
1585         param->wq.linear = 1;
1586 }
1587
1588 static void
1589 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1590     struct mlx5e_sq_param *param)
1591 {
1592         void *sqc = param->sqc;
1593         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1594
1595         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1596         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1597         MLX5_SET(wq, wq, pd, priv->pdn);
1598
1599         param->wq.buf_numa_node = 0;
1600         param->wq.db_numa_node = 0;
1601         param->wq.linear = 1;
1602 }
1603
1604 static void
1605 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1606     struct mlx5e_cq_param *param)
1607 {
1608         void *cqc = param->cqc;
1609
1610         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1611 }
1612
1613 static void
1614 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1615     struct mlx5e_cq_param *param)
1616 {
1617         void *cqc = param->cqc;
1618
1619
1620         /*
1621          * TODO The sysctl to control on/off is a bool value for now, which means
1622          * we only support CSUM, once HASH is implemnted we'll need to address that.
1623          */
1624         if (priv->params.cqe_zipping_en) {
1625                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1626                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1627         }
1628
1629         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1630         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1631         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1632
1633         switch (priv->params.rx_cq_moderation_mode) {
1634         case 0:
1635                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1636                 break;
1637         default:
1638                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1639                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1640                 else
1641                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1642                 break;
1643         }
1644
1645         mlx5e_build_common_cq_param(priv, param);
1646 }
1647
1648 static void
1649 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1650     struct mlx5e_cq_param *param)
1651 {
1652         void *cqc = param->cqc;
1653
1654         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1655         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1656         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1657
1658         switch (priv->params.tx_cq_moderation_mode) {
1659         case 0:
1660                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1661                 break;
1662         default:
1663                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1664                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1665                 else
1666                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1667                 break;
1668         }
1669
1670         mlx5e_build_common_cq_param(priv, param);
1671 }
1672
1673 static void
1674 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1675     struct mlx5e_channel_param *cparam)
1676 {
1677         memset(cparam, 0, sizeof(*cparam));
1678
1679         mlx5e_build_rq_param(priv, &cparam->rq);
1680         mlx5e_build_sq_param(priv, &cparam->sq);
1681         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1682         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1683 }
1684
1685 static int
1686 mlx5e_open_channels(struct mlx5e_priv *priv)
1687 {
1688         struct mlx5e_channel_param cparam;
1689         void *ptr;
1690         int err;
1691         int i;
1692         int j;
1693
1694         priv->channel = malloc(priv->params.num_channels *
1695             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1696         if (priv->channel == NULL)
1697                 return (-ENOMEM);
1698
1699         mlx5e_build_channel_param(priv, &cparam);
1700         for (i = 0; i < priv->params.num_channels; i++) {
1701                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1702                 if (err)
1703                         goto err_close_channels;
1704         }
1705
1706         for (j = 0; j < priv->params.num_channels; j++) {
1707                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1708                 if (err)
1709                         goto err_close_channels;
1710         }
1711
1712         return (0);
1713
1714 err_close_channels:
1715         for (i--; i >= 0; i--) {
1716                 mlx5e_close_channel(&priv->channel[i]);
1717                 mlx5e_close_channel_wait(&priv->channel[i]);
1718         }
1719
1720         /* remove "volatile" attribute from "channel" pointer */
1721         ptr = __DECONST(void *, priv->channel);
1722         priv->channel = NULL;
1723
1724         free(ptr, M_MLX5EN);
1725
1726         return (err);
1727 }
1728
1729 static void
1730 mlx5e_close_channels(struct mlx5e_priv *priv)
1731 {
1732         void *ptr;
1733         int i;
1734
1735         if (priv->channel == NULL)
1736                 return;
1737
1738         for (i = 0; i < priv->params.num_channels; i++)
1739                 mlx5e_close_channel(&priv->channel[i]);
1740         for (i = 0; i < priv->params.num_channels; i++)
1741                 mlx5e_close_channel_wait(&priv->channel[i]);
1742
1743         /* remove "volatile" attribute from "channel" pointer */
1744         ptr = __DECONST(void *, priv->channel);
1745         priv->channel = NULL;
1746
1747         free(ptr, M_MLX5EN);
1748 }
1749
1750 static int
1751 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1752 {
1753         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1754             priv->params.tx_cq_moderation_usec,
1755             priv->params.tx_cq_moderation_pkts));
1756 }
1757
1758 static int
1759 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1760 {
1761         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1762             priv->params.rx_cq_moderation_usec,
1763             priv->params.rx_cq_moderation_pkts));
1764 }
1765
1766 static int
1767 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1768 {
1769         int err;
1770         int i;
1771
1772         if (c == NULL)
1773                 return (EINVAL);
1774
1775         err = mlx5e_refresh_rq_params(priv, &c->rq);
1776         if (err)
1777                 goto done;
1778
1779         for (i = 0; i != c->num_tc; i++) {
1780                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1781                 if (err)
1782                         goto done;
1783         }
1784 done:
1785         return (err);
1786 }
1787
1788 int
1789 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1790 {
1791         int i;
1792
1793         if (priv->channel == NULL)
1794                 return (EINVAL);
1795
1796         for (i = 0; i < priv->params.num_channels; i++) {
1797                 int err;
1798
1799                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1800                 if (err)
1801                         return (err);
1802         }
1803         return (0);
1804 }
1805
1806 static int
1807 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1808 {
1809         struct mlx5_core_dev *mdev = priv->mdev;
1810         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1811         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1812
1813         memset(in, 0, sizeof(in));
1814
1815         MLX5_SET(tisc, tisc, prio, tc);
1816         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1817
1818         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1819 }
1820
1821 static void
1822 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1823 {
1824         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1825 }
1826
1827 static int
1828 mlx5e_open_tises(struct mlx5e_priv *priv)
1829 {
1830         int num_tc = priv->num_tc;
1831         int err;
1832         int tc;
1833
1834         for (tc = 0; tc < num_tc; tc++) {
1835                 err = mlx5e_open_tis(priv, tc);
1836                 if (err)
1837                         goto err_close_tises;
1838         }
1839
1840         return (0);
1841
1842 err_close_tises:
1843         for (tc--; tc >= 0; tc--)
1844                 mlx5e_close_tis(priv, tc);
1845
1846         return (err);
1847 }
1848
1849 static void
1850 mlx5e_close_tises(struct mlx5e_priv *priv)
1851 {
1852         int num_tc = priv->num_tc;
1853         int tc;
1854
1855         for (tc = 0; tc < num_tc; tc++)
1856                 mlx5e_close_tis(priv, tc);
1857 }
1858
1859 static int
1860 mlx5e_open_rqt(struct mlx5e_priv *priv)
1861 {
1862         struct mlx5_core_dev *mdev = priv->mdev;
1863         u32 *in;
1864         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1865         void *rqtc;
1866         int inlen;
1867         int err;
1868         int sz;
1869         int i;
1870
1871         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1872
1873         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1874         in = mlx5_vzalloc(inlen);
1875         if (in == NULL)
1876                 return (-ENOMEM);
1877         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1878
1879         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1880         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1881
1882         for (i = 0; i < sz; i++) {
1883                 int ix;
1884 #ifdef RSS
1885                 ix = rss_get_indirection_to_bucket(i);
1886 #else
1887                 ix = i;
1888 #endif
1889                 /* ensure we don't overflow */
1890                 ix %= priv->params.num_channels;
1891                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1892         }
1893
1894         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1895
1896         memset(out, 0, sizeof(out));
1897         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1898         if (!err)
1899                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1900
1901         kvfree(in);
1902
1903         return (err);
1904 }
1905
1906 static void
1907 mlx5e_close_rqt(struct mlx5e_priv *priv)
1908 {
1909         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1910         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1911
1912         memset(in, 0, sizeof(in));
1913
1914         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1915         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1916
1917         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1918             sizeof(out));
1919 }
1920
1921 static void
1922 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1923 {
1924         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1925         __be32 *hkey;
1926
1927         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1928
1929 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1930
1931 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1932                           MLX5_HASH_FIELD_SEL_DST_IP)
1933
1934 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1935                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1936                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1937                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1938
1939 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1940                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1941                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1942
1943         if (priv->params.hw_lro_en) {
1944                 MLX5_SET(tirc, tirc, lro_enable_mask,
1945                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1946                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1947                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1948                     (priv->params.lro_wqe_sz -
1949                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1950                 /* TODO: add the option to choose timer value dynamically */
1951                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1952                     MLX5_CAP_ETH(priv->mdev,
1953                     lro_timer_supported_periods[2]));
1954         }
1955
1956         /* setup parameters for hashing TIR type, if any */
1957         switch (tt) {
1958         case MLX5E_TT_ANY:
1959                 MLX5_SET(tirc, tirc, disp_type,
1960                     MLX5_TIRC_DISP_TYPE_DIRECT);
1961                 MLX5_SET(tirc, tirc, inline_rqn,
1962                     priv->channel[0]->rq.rqn);
1963                 break;
1964         default:
1965                 MLX5_SET(tirc, tirc, disp_type,
1966                     MLX5_TIRC_DISP_TYPE_INDIRECT);
1967                 MLX5_SET(tirc, tirc, indirect_table,
1968                     priv->rqtn);
1969                 MLX5_SET(tirc, tirc, rx_hash_fn,
1970                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1971                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1972 #ifdef RSS
1973                 /*
1974                  * The FreeBSD RSS implementation does currently not
1975                  * support symmetric Toeplitz hashes:
1976                  */
1977                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
1978                 rss_getkey((uint8_t *)hkey);
1979 #else
1980                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1981                 hkey[0] = cpu_to_be32(0xD181C62C);
1982                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
1983                 hkey[2] = cpu_to_be32(0x1983A2FC);
1984                 hkey[3] = cpu_to_be32(0x943E1ADB);
1985                 hkey[4] = cpu_to_be32(0xD9389E6B);
1986                 hkey[5] = cpu_to_be32(0xD1039C2C);
1987                 hkey[6] = cpu_to_be32(0xA74499AD);
1988                 hkey[7] = cpu_to_be32(0x593D56D9);
1989                 hkey[8] = cpu_to_be32(0xF3253C06);
1990                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
1991 #endif
1992                 break;
1993         }
1994
1995         switch (tt) {
1996         case MLX5E_TT_IPV4_TCP:
1997                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1998                     MLX5_L3_PROT_TYPE_IPV4);
1999                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2000                     MLX5_L4_PROT_TYPE_TCP);
2001 #ifdef RSS
2002                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2003                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2004                             MLX5_HASH_IP);
2005                 } else
2006 #endif
2007                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2008                     MLX5_HASH_ALL);
2009                 break;
2010
2011         case MLX5E_TT_IPV6_TCP:
2012                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2013                     MLX5_L3_PROT_TYPE_IPV6);
2014                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2015                     MLX5_L4_PROT_TYPE_TCP);
2016 #ifdef RSS
2017                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2018                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2019                             MLX5_HASH_IP);
2020                 } else
2021 #endif
2022                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2023                     MLX5_HASH_ALL);
2024                 break;
2025
2026         case MLX5E_TT_IPV4_UDP:
2027                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2028                     MLX5_L3_PROT_TYPE_IPV4);
2029                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2030                     MLX5_L4_PROT_TYPE_UDP);
2031 #ifdef RSS
2032                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2033                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2034                             MLX5_HASH_IP);
2035                 } else
2036 #endif
2037                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2038                     MLX5_HASH_ALL);
2039                 break;
2040
2041         case MLX5E_TT_IPV6_UDP:
2042                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2043                     MLX5_L3_PROT_TYPE_IPV6);
2044                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2045                     MLX5_L4_PROT_TYPE_UDP);
2046 #ifdef RSS
2047                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2048                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2049                             MLX5_HASH_IP);
2050                 } else
2051 #endif
2052                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2053                     MLX5_HASH_ALL);
2054                 break;
2055
2056         case MLX5E_TT_IPV4_IPSEC_AH:
2057                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2058                     MLX5_L3_PROT_TYPE_IPV4);
2059                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2060                     MLX5_HASH_IP_IPSEC_SPI);
2061                 break;
2062
2063         case MLX5E_TT_IPV6_IPSEC_AH:
2064                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2065                     MLX5_L3_PROT_TYPE_IPV6);
2066                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2067                     MLX5_HASH_IP_IPSEC_SPI);
2068                 break;
2069
2070         case MLX5E_TT_IPV4_IPSEC_ESP:
2071                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2072                     MLX5_L3_PROT_TYPE_IPV4);
2073                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2074                     MLX5_HASH_IP_IPSEC_SPI);
2075                 break;
2076
2077         case MLX5E_TT_IPV6_IPSEC_ESP:
2078                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2079                     MLX5_L3_PROT_TYPE_IPV6);
2080                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2081                     MLX5_HASH_IP_IPSEC_SPI);
2082                 break;
2083
2084         case MLX5E_TT_IPV4:
2085                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2086                     MLX5_L3_PROT_TYPE_IPV4);
2087                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2088                     MLX5_HASH_IP);
2089                 break;
2090
2091         case MLX5E_TT_IPV6:
2092                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2093                     MLX5_L3_PROT_TYPE_IPV6);
2094                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095                     MLX5_HASH_IP);
2096                 break;
2097
2098         default:
2099                 break;
2100         }
2101 }
2102
2103 static int
2104 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2105 {
2106         struct mlx5_core_dev *mdev = priv->mdev;
2107         u32 *in;
2108         void *tirc;
2109         int inlen;
2110         int err;
2111
2112         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2113         in = mlx5_vzalloc(inlen);
2114         if (in == NULL)
2115                 return (-ENOMEM);
2116         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2117
2118         mlx5e_build_tir_ctx(priv, tirc, tt);
2119
2120         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2121
2122         kvfree(in);
2123
2124         return (err);
2125 }
2126
2127 static void
2128 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2129 {
2130         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2131 }
2132
2133 static int
2134 mlx5e_open_tirs(struct mlx5e_priv *priv)
2135 {
2136         int err;
2137         int i;
2138
2139         for (i = 0; i < MLX5E_NUM_TT; i++) {
2140                 err = mlx5e_open_tir(priv, i);
2141                 if (err)
2142                         goto err_close_tirs;
2143         }
2144
2145         return (0);
2146
2147 err_close_tirs:
2148         for (i--; i >= 0; i--)
2149                 mlx5e_close_tir(priv, i);
2150
2151         return (err);
2152 }
2153
2154 static void
2155 mlx5e_close_tirs(struct mlx5e_priv *priv)
2156 {
2157         int i;
2158
2159         for (i = 0; i < MLX5E_NUM_TT; i++)
2160                 mlx5e_close_tir(priv, i);
2161 }
2162
2163 /*
2164  * SW MTU does not include headers,
2165  * HW MTU includes all headers and checksums.
2166  */
2167 static int
2168 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2169 {
2170         struct mlx5e_priv *priv = ifp->if_softc;
2171         struct mlx5_core_dev *mdev = priv->mdev;
2172         int hw_mtu;
2173         int err;
2174
2175
2176         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2177         if (err) {
2178                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2179                     __func__, sw_mtu, err);
2180                 return (err);
2181         }
2182         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2183         if (!err) {
2184                 ifp->if_mtu = MLX5E_HW2SW_MTU(hw_mtu);
2185
2186                 if (ifp->if_mtu != sw_mtu) {
2187                         if_printf(ifp, "Port MTU %d is different than "
2188                             "ifp mtu %d\n", sw_mtu, (int)ifp->if_mtu);
2189                 }
2190         } else {
2191                 if_printf(ifp, "Query port MTU, after setting new "
2192                     "MTU value, failed\n");
2193                 ifp->if_mtu = sw_mtu;
2194         }
2195         return (0);
2196 }
2197
2198 int
2199 mlx5e_open_locked(struct ifnet *ifp)
2200 {
2201         struct mlx5e_priv *priv = ifp->if_softc;
2202         int err;
2203         u16 set_id;
2204
2205         /* check if already opened */
2206         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2207                 return (0);
2208
2209 #ifdef RSS
2210         if (rss_getnumbuckets() > priv->params.num_channels) {
2211                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2212                     "channels(%u) available\n", rss_getnumbuckets(),
2213                     priv->params.num_channels);
2214         }
2215 #endif
2216         err = mlx5e_open_tises(priv);
2217         if (err) {
2218                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2219                     __func__, err);
2220                 return (err);
2221         }
2222         err = mlx5_vport_alloc_q_counter(priv->mdev,
2223             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2224         if (err) {
2225                 if_printf(priv->ifp,
2226                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2227                     __func__, err);
2228                 goto err_close_tises;
2229         }
2230         /* store counter set ID */
2231         priv->counter_set_id = set_id;
2232
2233         err = mlx5e_open_channels(priv);
2234         if (err) {
2235                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2236                     __func__, err);
2237                 goto err_dalloc_q_counter;
2238         }
2239         err = mlx5e_open_rqt(priv);
2240         if (err) {
2241                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2242                     __func__, err);
2243                 goto err_close_channels;
2244         }
2245         err = mlx5e_open_tirs(priv);
2246         if (err) {
2247                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2248                     __func__, err);
2249                 goto err_close_rqls;
2250         }
2251         err = mlx5e_open_flow_table(priv);
2252         if (err) {
2253                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2254                     __func__, err);
2255                 goto err_close_tirs;
2256         }
2257         err = mlx5e_add_all_vlan_rules(priv);
2258         if (err) {
2259                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2260                     __func__, err);
2261                 goto err_close_flow_table;
2262         }
2263         set_bit(MLX5E_STATE_OPENED, &priv->state);
2264
2265         mlx5e_update_carrier(priv);
2266         mlx5e_set_rx_mode_core(priv);
2267
2268         return (0);
2269
2270 err_close_flow_table:
2271         mlx5e_close_flow_table(priv);
2272
2273 err_close_tirs:
2274         mlx5e_close_tirs(priv);
2275
2276 err_close_rqls:
2277         mlx5e_close_rqt(priv);
2278
2279 err_close_channels:
2280         mlx5e_close_channels(priv);
2281
2282 err_dalloc_q_counter:
2283         mlx5_vport_dealloc_q_counter(priv->mdev,
2284             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2285
2286 err_close_tises:
2287         mlx5e_close_tises(priv);
2288
2289         return (err);
2290 }
2291
2292 static void
2293 mlx5e_open(void *arg)
2294 {
2295         struct mlx5e_priv *priv = arg;
2296
2297         PRIV_LOCK(priv);
2298         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2299                 if_printf(priv->ifp,
2300                     "%s: Setting port status to up failed\n",
2301                     __func__);
2302
2303         mlx5e_open_locked(priv->ifp);
2304         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2305         PRIV_UNLOCK(priv);
2306 }
2307
2308 int
2309 mlx5e_close_locked(struct ifnet *ifp)
2310 {
2311         struct mlx5e_priv *priv = ifp->if_softc;
2312
2313         /* check if already closed */
2314         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2315                 return (0);
2316
2317         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2318
2319         mlx5e_set_rx_mode_core(priv);
2320         mlx5e_del_all_vlan_rules(priv);
2321         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2322         mlx5e_close_flow_table(priv);
2323         mlx5e_close_tirs(priv);
2324         mlx5e_close_rqt(priv);
2325         mlx5e_close_channels(priv);
2326         mlx5_vport_dealloc_q_counter(priv->mdev,
2327             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2328         mlx5e_close_tises(priv);
2329
2330         return (0);
2331 }
2332
2333 #if (__FreeBSD_version >= 1100000)
2334 static uint64_t
2335 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2336 {
2337         struct mlx5e_priv *priv = ifp->if_softc;
2338         u64 retval;
2339
2340         /* PRIV_LOCK(priv); XXX not allowed */
2341         switch (cnt) {
2342         case IFCOUNTER_IPACKETS:
2343                 retval = priv->stats.vport.rx_packets;
2344                 break;
2345         case IFCOUNTER_IERRORS:
2346                 retval = priv->stats.vport.rx_error_packets;
2347                 break;
2348         case IFCOUNTER_IQDROPS:
2349                 retval = priv->stats.vport.rx_out_of_buffer;
2350                 break;
2351         case IFCOUNTER_OPACKETS:
2352                 retval = priv->stats.vport.tx_packets;
2353                 break;
2354         case IFCOUNTER_OERRORS:
2355                 retval = priv->stats.vport.tx_error_packets;
2356                 break;
2357         case IFCOUNTER_IBYTES:
2358                 retval = priv->stats.vport.rx_bytes;
2359                 break;
2360         case IFCOUNTER_OBYTES:
2361                 retval = priv->stats.vport.tx_bytes;
2362                 break;
2363         case IFCOUNTER_IMCASTS:
2364                 retval = priv->stats.vport.rx_multicast_packets;
2365                 break;
2366         case IFCOUNTER_OMCASTS:
2367                 retval = priv->stats.vport.tx_multicast_packets;
2368                 break;
2369         case IFCOUNTER_OQDROPS:
2370                 retval = priv->stats.vport.tx_queue_dropped;
2371                 break;
2372         default:
2373                 retval = if_get_counter_default(ifp, cnt);
2374                 break;
2375         }
2376         /* PRIV_UNLOCK(priv); XXX not allowed */
2377         return (retval);
2378 }
2379 #endif
2380
2381 static void
2382 mlx5e_set_rx_mode(struct ifnet *ifp)
2383 {
2384         struct mlx5e_priv *priv = ifp->if_softc;
2385
2386         schedule_work(&priv->set_rx_mode_work);
2387 }
2388
2389 static int
2390 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2391 {
2392         struct mlx5e_priv *priv;
2393         struct ifreq *ifr;
2394         struct ifi2creq i2c;
2395         int error = 0;
2396         int mask = 0;
2397         int size_read = 0;
2398         int module_num;
2399         int max_mtu;
2400         uint8_t read_addr;
2401
2402         priv = ifp->if_softc;
2403
2404         /* check if detaching */
2405         if (priv == NULL || priv->gone != 0)
2406                 return (ENXIO);
2407
2408         switch (command) {
2409         case SIOCSIFMTU:
2410                 ifr = (struct ifreq *)data;
2411
2412                 PRIV_LOCK(priv);
2413                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2414
2415                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2416                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2417                         int was_opened;
2418
2419                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2420                         if (was_opened)
2421                                 mlx5e_close_locked(ifp);
2422
2423                         /* set new MTU */
2424                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2425
2426                         if (was_opened)
2427                                 mlx5e_open_locked(ifp);
2428                 } else {
2429                         error = EINVAL;
2430                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2431                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2432                 }
2433                 PRIV_UNLOCK(priv);
2434                 break;
2435         case SIOCSIFFLAGS:
2436                 if ((ifp->if_flags & IFF_UP) &&
2437                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2438                         mlx5e_set_rx_mode(ifp);
2439                         break;
2440                 }
2441                 PRIV_LOCK(priv);
2442                 if (ifp->if_flags & IFF_UP) {
2443                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2444                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2445                                         mlx5e_open_locked(ifp);
2446                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2447                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2448                         }
2449                 } else {
2450                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2451                                 mlx5_set_port_status(priv->mdev,
2452                                     MLX5_PORT_DOWN);
2453                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2454                                         mlx5e_close_locked(ifp);
2455                                 mlx5e_update_carrier(priv);
2456                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2457                         }
2458                 }
2459                 PRIV_UNLOCK(priv);
2460                 break;
2461         case SIOCADDMULTI:
2462         case SIOCDELMULTI:
2463                 mlx5e_set_rx_mode(ifp);
2464                 break;
2465         case SIOCSIFMEDIA:
2466         case SIOCGIFMEDIA:
2467         case SIOCGIFXMEDIA:
2468                 ifr = (struct ifreq *)data;
2469                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2470                 break;
2471         case SIOCSIFCAP:
2472                 ifr = (struct ifreq *)data;
2473                 PRIV_LOCK(priv);
2474                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2475
2476                 if (mask & IFCAP_TXCSUM) {
2477                         ifp->if_capenable ^= IFCAP_TXCSUM;
2478                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2479
2480                         if (IFCAP_TSO4 & ifp->if_capenable &&
2481                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2482                                 ifp->if_capenable &= ~IFCAP_TSO4;
2483                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2484                                 if_printf(ifp,
2485                                     "tso4 disabled due to -txcsum.\n");
2486                         }
2487                 }
2488                 if (mask & IFCAP_TXCSUM_IPV6) {
2489                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2490                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2491
2492                         if (IFCAP_TSO6 & ifp->if_capenable &&
2493                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2494                                 ifp->if_capenable &= ~IFCAP_TSO6;
2495                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2496                                 if_printf(ifp,
2497                                     "tso6 disabled due to -txcsum6.\n");
2498                         }
2499                 }
2500                 if (mask & IFCAP_RXCSUM)
2501                         ifp->if_capenable ^= IFCAP_RXCSUM;
2502                 if (mask & IFCAP_RXCSUM_IPV6)
2503                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2504                 if (mask & IFCAP_TSO4) {
2505                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2506                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2507                                 if_printf(ifp, "enable txcsum first.\n");
2508                                 error = EAGAIN;
2509                                 goto out;
2510                         }
2511                         ifp->if_capenable ^= IFCAP_TSO4;
2512                         ifp->if_hwassist ^= CSUM_IP_TSO;
2513                 }
2514                 if (mask & IFCAP_TSO6) {
2515                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2516                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2517                                 if_printf(ifp, "enable txcsum6 first.\n");
2518                                 error = EAGAIN;
2519                                 goto out;
2520                         }
2521                         ifp->if_capenable ^= IFCAP_TSO6;
2522                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2523                 }
2524                 if (mask & IFCAP_VLAN_HWFILTER) {
2525                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2526                                 mlx5e_disable_vlan_filter(priv);
2527                         else
2528                                 mlx5e_enable_vlan_filter(priv);
2529
2530                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2531                 }
2532                 if (mask & IFCAP_VLAN_HWTAGGING)
2533                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2534                 if (mask & IFCAP_WOL_MAGIC)
2535                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2536
2537                 VLAN_CAPABILITIES(ifp);
2538                 /* turn off LRO means also turn of HW LRO - if it's on */
2539                 if (mask & IFCAP_LRO) {
2540                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2541                         bool need_restart = false;
2542
2543                         ifp->if_capenable ^= IFCAP_LRO;
2544                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2545                                 if (priv->params.hw_lro_en) {
2546                                         priv->params.hw_lro_en = false;
2547                                         need_restart = true;
2548                                         /* Not sure this is the correct way */
2549                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2550                                 }
2551                         }
2552                         if (was_opened && need_restart) {
2553                                 mlx5e_close_locked(ifp);
2554                                 mlx5e_open_locked(ifp);
2555                         }
2556                 }
2557 out:
2558                 PRIV_UNLOCK(priv);
2559                 break;
2560
2561         case SIOCGI2C:
2562                 ifr = (struct ifreq *)data;
2563
2564                 /*
2565                  * Copy from the user-space address ifr_data to the
2566                  * kernel-space address i2c
2567                  */
2568                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2569                 if (error)
2570                         break;
2571
2572                 if (i2c.len > sizeof(i2c.data)) {
2573                         error = EINVAL;
2574                         break;
2575                 }
2576
2577                 PRIV_LOCK(priv);
2578                 /* Get module_num which is required for the query_eeprom */
2579                 error = mlx5_query_module_num(priv->mdev, &module_num);
2580                 if (error) {
2581                         if_printf(ifp, "Query module num failed, eeprom "
2582                             "reading is not supported\n");
2583                         error = EINVAL;
2584                         goto err_i2c;
2585                 }
2586                 /* Check if module is present before doing an access */
2587                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2588                     MLX5_MODULE_STATUS_PLUGGED) {
2589                         error = EINVAL;
2590                         goto err_i2c;
2591                 }
2592                 /*
2593                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2594                  * The internal conversion is as follows:
2595                  */
2596                 if (i2c.dev_addr == 0xA0)
2597                         read_addr = MLX5E_I2C_ADDR_LOW;
2598                 else if (i2c.dev_addr == 0xA2)
2599                         read_addr = MLX5E_I2C_ADDR_HIGH;
2600                 else {
2601                         if_printf(ifp, "Query eeprom failed, "
2602                             "Invalid Address: %X\n", i2c.dev_addr);
2603                         error = EINVAL;
2604                         goto err_i2c;
2605                 }
2606                 error = mlx5_query_eeprom(priv->mdev,
2607                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2608                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2609                     (uint32_t *)i2c.data, &size_read);
2610                 if (error) {
2611                         if_printf(ifp, "Query eeprom failed, eeprom "
2612                             "reading is not supported\n");
2613                         error = EINVAL;
2614                         goto err_i2c;
2615                 }
2616
2617                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2618                         error = mlx5_query_eeprom(priv->mdev,
2619                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2620                             (uint32_t)(i2c.offset + size_read),
2621                             (uint32_t)(i2c.len - size_read), module_num,
2622                             (uint32_t *)(i2c.data + size_read), &size_read);
2623                 }
2624                 if (error) {
2625                         if_printf(ifp, "Query eeprom failed, eeprom "
2626                             "reading is not supported\n");
2627                         error = EINVAL;
2628                         goto err_i2c;
2629                 }
2630
2631                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2632 err_i2c:
2633                 PRIV_UNLOCK(priv);
2634                 break;
2635
2636         default:
2637                 error = ether_ioctl(ifp, command, data);
2638                 break;
2639         }
2640         return (error);
2641 }
2642
2643 static int
2644 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2645 {
2646         /*
2647          * TODO: uncoment once FW really sets all these bits if
2648          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2649          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2650          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2651          * -ENOTSUPP;
2652          */
2653
2654         /* TODO: add more must-to-have features */
2655
2656         return (0);
2657 }
2658
2659 static void
2660 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2661     struct mlx5e_priv *priv,
2662     int num_comp_vectors)
2663 {
2664         /*
2665          * TODO: Consider link speed for setting "log_sq_size",
2666          * "log_rq_size" and "cq_moderation_xxx":
2667          */
2668         priv->params.log_sq_size =
2669             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2670         priv->params.log_rq_size =
2671             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2672         priv->params.rx_cq_moderation_usec =
2673             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2674             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2675             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2676         priv->params.rx_cq_moderation_mode =
2677             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2678         priv->params.rx_cq_moderation_pkts =
2679             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2680         priv->params.tx_cq_moderation_usec =
2681             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2682         priv->params.tx_cq_moderation_pkts =
2683             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2684         priv->params.min_rx_wqes =
2685             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2686         priv->params.rx_hash_log_tbl_sz =
2687             (order_base_2(num_comp_vectors) >
2688             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2689             order_base_2(num_comp_vectors) :
2690             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2691         priv->params.num_tc = 1;
2692         priv->params.default_vlan_prio = 0;
2693         priv->counter_set_id = -1;
2694
2695         /*
2696          * hw lro is currently defaulted to off. when it won't anymore we
2697          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2698          */
2699         priv->params.hw_lro_en = false;
2700         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2701
2702         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2703
2704         priv->mdev = mdev;
2705         priv->params.num_channels = num_comp_vectors;
2706         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2707         priv->queue_mapping_channel_mask =
2708             roundup_pow_of_two(num_comp_vectors) - 1;
2709         priv->num_tc = priv->params.num_tc;
2710         priv->default_vlan_prio = priv->params.default_vlan_prio;
2711
2712         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2713         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2714         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2715 }
2716
2717 static int
2718 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2719     struct mlx5_core_mr *mr)
2720 {
2721         struct ifnet *ifp = priv->ifp;
2722         struct mlx5_core_dev *mdev = priv->mdev;
2723         struct mlx5_create_mkey_mbox_in *in;
2724         int err;
2725
2726         in = mlx5_vzalloc(sizeof(*in));
2727         if (in == NULL) {
2728                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2729                 return (-ENOMEM);
2730         }
2731         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2732             MLX5_PERM_LOCAL_READ |
2733             MLX5_ACCESS_MODE_PA;
2734         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2735         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2736
2737         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2738             NULL);
2739         if (err)
2740                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2741                     __func__, err);
2742
2743         kvfree(in);
2744
2745         return (err);
2746 }
2747
2748 static const char *mlx5e_vport_stats_desc[] = {
2749         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2750 };
2751
2752 static const char *mlx5e_pport_stats_desc[] = {
2753         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2754 };
2755
2756 static void
2757 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2758 {
2759         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2760         sx_init(&priv->state_lock, "mlx5state");
2761         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2762 }
2763
2764 static void
2765 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2766 {
2767         mtx_destroy(&priv->async_events_mtx);
2768         sx_destroy(&priv->state_lock);
2769 }
2770
2771 static int
2772 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2773 {
2774         /*
2775          * %d.%d%.d the string format.
2776          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2777          * We need at most 5 chars to store that.
2778          * It also has: two "." and NULL at the end, which means we need 18
2779          * (5*3 + 3) chars at most.
2780          */
2781         char fw[18];
2782         struct mlx5e_priv *priv = arg1;
2783         int error;
2784
2785         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2786             fw_rev_sub(priv->mdev));
2787         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2788         return (error);
2789 }
2790
2791 static void
2792 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2793 {
2794         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2795             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2796             sysctl_firmware, "A", "HCA firmware version");
2797
2798         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2799             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2800             "Board ID");
2801 }
2802
2803 static void
2804 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2805 {
2806 #if (__FreeBSD_version < 1100000)
2807         char path[64];
2808
2809 #endif
2810         /* Only receiving pauseframes is enabled by default */
2811         priv->params.tx_pauseframe_control = 0;
2812         priv->params.rx_pauseframe_control = 1;
2813
2814 #if (__FreeBSD_version < 1100000)
2815         /* compute path for sysctl */
2816         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2817             device_get_unit(priv->mdev->pdev->dev.bsddev));
2818
2819         /* try to fetch tunable, if any */
2820         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2821
2822         /* compute path for sysctl */
2823         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2824             device_get_unit(priv->mdev->pdev->dev.bsddev));
2825
2826         /* try to fetch tunable, if any */
2827         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2828 #endif
2829
2830         /* register pausframe SYSCTLs */
2831         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2832             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2833             &priv->params.tx_pauseframe_control, 0,
2834             "Set to enable TX pause frames. Clear to disable.");
2835
2836         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2837             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2838             &priv->params.rx_pauseframe_control, 0,
2839             "Set to enable RX pause frames. Clear to disable.");
2840
2841         /* range check */
2842         priv->params.tx_pauseframe_control =
2843             priv->params.tx_pauseframe_control ? 1 : 0;
2844         priv->params.rx_pauseframe_control =
2845             priv->params.rx_pauseframe_control ? 1 : 0;
2846
2847         /* update firmware */
2848         mlx5_set_port_pause(priv->mdev, 1,
2849             priv->params.rx_pauseframe_control,
2850             priv->params.tx_pauseframe_control);
2851 }
2852
2853 static void *
2854 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2855 {
2856         static volatile int mlx5_en_unit;
2857         struct ifnet *ifp;
2858         struct mlx5e_priv *priv;
2859         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2860         struct sysctl_oid_list *child;
2861         int ncv = mdev->priv.eq_table.num_comp_vectors;
2862         char unit[16];
2863         int err;
2864         int i;
2865         u32 eth_proto_cap;
2866
2867         if (mlx5e_check_required_hca_cap(mdev)) {
2868                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2869                 return (NULL);
2870         }
2871         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2872         if (priv == NULL) {
2873                 mlx5_core_err(mdev, "malloc() failed\n");
2874                 return (NULL);
2875         }
2876         mlx5e_priv_mtx_init(priv);
2877
2878         ifp = priv->ifp = if_alloc(IFT_ETHER);
2879         if (ifp == NULL) {
2880                 mlx5_core_err(mdev, "if_alloc() failed\n");
2881                 goto err_free_priv;
2882         }
2883         ifp->if_softc = priv;
2884         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2885         ifp->if_mtu = ETHERMTU;
2886         ifp->if_init = mlx5e_open;
2887         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2888         ifp->if_ioctl = mlx5e_ioctl;
2889         ifp->if_transmit = mlx5e_xmit;
2890         ifp->if_qflush = if_qflush;
2891 #if (__FreeBSD_version >= 1100000)
2892         ifp->if_get_counter = mlx5e_get_counter;
2893 #endif
2894         ifp->if_snd.ifq_maxlen = ifqmaxlen;
2895         /*
2896          * Set driver features
2897          */
2898         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2899         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2900         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2901         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2902         ifp->if_capabilities |= IFCAP_LRO;
2903         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2904
2905         /* set TSO limits so that we don't have to drop TX packets */
2906         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2907         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2908         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2909
2910         ifp->if_capenable = ifp->if_capabilities;
2911         ifp->if_hwassist = 0;
2912         if (ifp->if_capenable & IFCAP_TSO)
2913                 ifp->if_hwassist |= CSUM_TSO;
2914         if (ifp->if_capenable & IFCAP_TXCSUM)
2915                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2916         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2917                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2918
2919         /* ifnet sysctl tree */
2920         sysctl_ctx_init(&priv->sysctl_ctx);
2921         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2922             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2923         if (priv->sysctl_ifnet == NULL) {
2924                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2925                 goto err_free_sysctl;
2926         }
2927         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2928         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2929             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2930         if (priv->sysctl_ifnet == NULL) {
2931                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2932                 goto err_free_sysctl;
2933         }
2934
2935         /* HW sysctl tree */
2936         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2937         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2938             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2939         if (priv->sysctl_hw == NULL) {
2940                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2941                 goto err_free_sysctl;
2942         }
2943         mlx5e_build_ifp_priv(mdev, priv, ncv);
2944         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2945         if (err) {
2946                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2947                     __func__, err);
2948                 goto err_free_sysctl;
2949         }
2950         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2951         if (err) {
2952                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2953                     __func__, err);
2954                 goto err_unmap_free_uar;
2955         }
2956         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2957         if (err) {
2958                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2959                     __func__, err);
2960                 goto err_dealloc_pd;
2961         }
2962         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2963         if (err) {
2964                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
2965                     __func__, err);
2966                 goto err_dealloc_transport_domain;
2967         }
2968         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
2969
2970         /* check if we should generate a random MAC address */
2971         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
2972             is_zero_ether_addr(dev_addr)) {
2973                 random_ether_addr(dev_addr);
2974                 if_printf(ifp, "Assigned random MAC address\n");
2975         }
2976
2977         /* set default MTU */
2978         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
2979
2980         /* Set desc */
2981         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
2982
2983         /* Set default media status */
2984         priv->media_status_last = IFM_AVALID;
2985         priv->media_active_last = IFM_ETHER | IFM_AUTO |
2986             IFM_ETH_RXPAUSE | IFM_FDX;
2987
2988         /* setup default pauseframes configuration */
2989         mlx5e_setup_pauseframes(priv);
2990
2991         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
2992         if (err) {
2993                 eth_proto_cap = 0;
2994                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
2995                     __func__, err);
2996         }
2997
2998         /* Setup supported medias */
2999         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3000             mlx5e_media_change, mlx5e_media_status);
3001
3002         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3003                 if (mlx5e_mode_table[i].baudrate == 0)
3004                         continue;
3005                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3006                         ifmedia_add(&priv->media,
3007                             mlx5e_mode_table[i].subtype |
3008                             IFM_ETHER, 0, NULL);
3009                         ifmedia_add(&priv->media,
3010                             mlx5e_mode_table[i].subtype |
3011                             IFM_ETHER | IFM_FDX |
3012                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3013                 }
3014         }
3015
3016         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3017         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3018             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3019
3020         /* Set autoselect by default */
3021         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3022             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3023         ether_ifattach(ifp, dev_addr);
3024
3025         /* Register for VLAN events */
3026         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3027             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3028         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3029             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3030
3031         /* Link is down by default */
3032         if_link_state_change(ifp, LINK_STATE_DOWN);
3033
3034         mlx5e_enable_async_events(priv);
3035
3036         mlx5e_add_hw_stats(priv);
3037
3038         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3039             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3040             priv->stats.vport.arg);
3041
3042         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3043             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3044             priv->stats.pport.arg);
3045
3046         mlx5e_create_ethtool(priv);
3047
3048         mtx_lock(&priv->async_events_mtx);
3049         mlx5e_update_stats(priv);
3050         mtx_unlock(&priv->async_events_mtx);
3051
3052         return (priv);
3053
3054 err_dealloc_transport_domain:
3055         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3056
3057 err_dealloc_pd:
3058         mlx5_core_dealloc_pd(mdev, priv->pdn);
3059
3060 err_unmap_free_uar:
3061         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3062
3063 err_free_sysctl:
3064         sysctl_ctx_free(&priv->sysctl_ctx);
3065
3066         if_free(ifp);
3067
3068 err_free_priv:
3069         mlx5e_priv_mtx_destroy(priv);
3070         free(priv, M_MLX5EN);
3071         return (NULL);
3072 }
3073
3074 static void
3075 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3076 {
3077         struct mlx5e_priv *priv = vpriv;
3078         struct ifnet *ifp = priv->ifp;
3079
3080         /* don't allow more IOCTLs */
3081         priv->gone = 1;
3082
3083         /*
3084          * Clear the device description to avoid use after free,
3085          * because the bsddev is not destroyed when this module is
3086          * unloaded:
3087          */
3088         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3089
3090         /* XXX wait a bit to allow IOCTL handlers to complete */
3091         pause("W", hz);
3092
3093         /* stop watchdog timer */
3094         callout_drain(&priv->watchdog);
3095
3096         if (priv->vlan_attach != NULL)
3097                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3098         if (priv->vlan_detach != NULL)
3099                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3100
3101         /* make sure device gets closed */
3102         PRIV_LOCK(priv);
3103         mlx5e_close_locked(ifp);
3104         PRIV_UNLOCK(priv);
3105
3106         /* unregister device */
3107         ifmedia_removeall(&priv->media);
3108         ether_ifdetach(ifp);
3109         if_free(ifp);
3110
3111         /* destroy all remaining sysctl nodes */
3112         if (priv->sysctl_debug)
3113                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3114         sysctl_ctx_free(&priv->stats.vport.ctx);
3115         sysctl_ctx_free(&priv->stats.pport.ctx);
3116         sysctl_ctx_free(&priv->sysctl_ctx);
3117
3118         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3119         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3120         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3121         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3122         mlx5e_disable_async_events(priv);
3123         flush_scheduled_work();
3124         mlx5e_priv_mtx_destroy(priv);
3125         free(priv, M_MLX5EN);
3126 }
3127
3128 static void *
3129 mlx5e_get_ifp(void *vpriv)
3130 {
3131         struct mlx5e_priv *priv = vpriv;
3132
3133         return (priv->ifp);
3134 }
3135
3136 static struct mlx5_interface mlx5e_interface = {
3137         .add = mlx5e_create_ifp,
3138         .remove = mlx5e_destroy_ifp,
3139         .event = mlx5e_async_event,
3140         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3141         .get_dev = mlx5e_get_ifp,
3142 };
3143
3144 void
3145 mlx5e_init(void)
3146 {
3147         mlx5_register_interface(&mlx5e_interface);
3148 }
3149
3150 void
3151 mlx5e_cleanup(void)
3152 {
3153         mlx5_unregister_interface(&mlx5e_interface);
3154 }
3155
3156 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3157 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3158
3159 #if (__FreeBSD_version >= 1100000)
3160 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3161 #endif
3162 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3163 MODULE_VERSION(mlx5en, 1);