sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 static void
 310 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 311 {
 312         struct mlx5_core_dev *mdev = priv->mdev;
 313         struct mlx5e_pport_stats *s = &priv->stats.pport;
 314         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 315         u32 *in;
 316         u32 *out;
 317         u64 *ptr;
 318         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 319         unsigned x;
 320         unsigned y;
 321
 322         in = mlx5_vzalloc(sz);
 323         out = mlx5_vzalloc(sz);
 324         if (in == NULL || out == NULL)
 325                 goto free_out;
 326
 327         ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 328
 329         MLX5_SET(ppcnt_reg, in, local_port, 1);
 330
 331         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 332         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 333         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 334                 s->arg[y] = be64toh(ptr[x]);
 335
 336         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 337         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 338         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 339                 s->arg[y] = be64toh(ptr[x]);
 340         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 341             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 342                 s_debug->arg[y] = be64toh(ptr[x]);
 343
 344         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 345         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 346         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 347                 s_debug->arg[y] = be64toh(ptr[x]);
 348
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 352                 s_debug->arg[y] = be64toh(ptr[x]);
 353 free_out:
 354         kvfree(in);
 355         kvfree(out);
 356 }
 357
 358 static void
 359 mlx5e_update_stats_work(struct work_struct *work)
 360 {
 361         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 362             update_stats_work);
 363         struct mlx5_core_dev *mdev = priv->mdev;
 364         struct mlx5e_vport_stats *s = &priv->stats.vport;
 365         struct mlx5e_rq_stats *rq_stats;
 366         struct mlx5e_sq_stats *sq_stats;
 367         struct buf_ring *sq_br;
 368 #if (__FreeBSD_version < 1100000)
 369         struct ifnet *ifp = priv->ifp;
 370 #endif
 371
 372         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 373         u32 *out;
 374         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 375         u64 tso_packets = 0;
 376         u64 tso_bytes = 0;
 377         u64 tx_queue_dropped = 0;
 378         u64 tx_defragged = 0;
 379         u64 tx_offload_none = 0;
 380         u64 lro_packets = 0;
 381         u64 lro_bytes = 0;
 382         u64 sw_lro_queued = 0;
 383         u64 sw_lro_flushed = 0;
 384         u64 rx_csum_none = 0;
 385         u64 rx_wqe_err = 0;
 386         u32 rx_out_of_buffer = 0;
 387         int i;
 388         int j;
 389
 390         PRIV_LOCK(priv);
 391         out = mlx5_vzalloc(outlen);
 392         if (out == NULL)
 393                 goto free_out;
 394         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 395                 goto free_out;
 396
 397         /* Collect firts the SW counters and then HW for consistency */
 398         for (i = 0; i < priv->params.num_channels; i++) {
 399                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 400
 401                 rq_stats = &priv->channel[i]->rq.stats;
 402
 403                 /* collect stats from LRO */
 404                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 405                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 406                 sw_lro_queued += rq_stats->sw_lro_queued;
 407                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 408                 lro_packets += rq_stats->lro_packets;
 409                 lro_bytes += rq_stats->lro_bytes;
 410                 rx_csum_none += rq_stats->csum_none;
 411                 rx_wqe_err += rq_stats->wqe_err;
 412
 413                 for (j = 0; j < priv->num_tc; j++) {
 414                         sq_stats = &priv->channel[i]->sq[j].stats;
 415                         sq_br = priv->channel[i]->sq[j].br;
 416
 417                         tso_packets += sq_stats->tso_packets;
 418                         tso_bytes += sq_stats->tso_bytes;
 419                         tx_queue_dropped += sq_stats->dropped;
 420                         tx_queue_dropped += sq_br->br_drops;
 421                         tx_defragged += sq_stats->defragged;
 422                         tx_offload_none += sq_stats->csum_offload_none;
 423                 }
 424         }
 425
 426         /* update counters */
 427         s->tso_packets = tso_packets;
 428         s->tso_bytes = tso_bytes;
 429         s->tx_queue_dropped = tx_queue_dropped;
 430         s->tx_defragged = tx_defragged;
 431         s->lro_packets = lro_packets;
 432         s->lro_bytes = lro_bytes;
 433         s->sw_lro_queued = sw_lro_queued;
 434         s->sw_lro_flushed = sw_lro_flushed;
 435         s->rx_csum_none = rx_csum_none;
 436         s->rx_wqe_err = rx_wqe_err;
 437
 438         /* HW counters */
 439         memset(in, 0, sizeof(in));
 440
 441         MLX5_SET(query_vport_counter_in, in, opcode,
 442             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 443         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 444         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 445
 446         memset(out, 0, outlen);
 447
 448         /* get number of out-of-buffer drops first */
 449         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 450             &rx_out_of_buffer))
 451                 goto free_out;
 452
 453         /* accumulate difference into a 64-bit counter */
 454         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 455         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 456
 457         /* get port statistics */
 458         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 459                 goto free_out;
 460
 461 #define MLX5_GET_CTR(out, x) \
 462         MLX5_GET64(query_vport_counter_out, out, x)
 463
 464         s->rx_error_packets =
 465             MLX5_GET_CTR(out, received_errors.packets);
 466         s->rx_error_bytes =
 467             MLX5_GET_CTR(out, received_errors.octets);
 468         s->tx_error_packets =
 469             MLX5_GET_CTR(out, transmit_errors.packets);
 470         s->tx_error_bytes =
 471             MLX5_GET_CTR(out, transmit_errors.octets);
 472
 473         s->rx_unicast_packets =
 474             MLX5_GET_CTR(out, received_eth_unicast.packets);
 475         s->rx_unicast_bytes =
 476             MLX5_GET_CTR(out, received_eth_unicast.octets);
 477         s->tx_unicast_packets =
 478             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 479         s->tx_unicast_bytes =
 480             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 481
 482         s->rx_multicast_packets =
 483             MLX5_GET_CTR(out, received_eth_multicast.packets);
 484         s->rx_multicast_bytes =
 485             MLX5_GET_CTR(out, received_eth_multicast.octets);
 486         s->tx_multicast_packets =
 487             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 488         s->tx_multicast_bytes =
 489             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 490
 491         s->rx_broadcast_packets =
 492             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 493         s->rx_broadcast_bytes =
 494             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 495         s->tx_broadcast_packets =
 496             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 497         s->tx_broadcast_bytes =
 498             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 499
 500         s->rx_packets =
 501             s->rx_unicast_packets +
 502             s->rx_multicast_packets +
 503             s->rx_broadcast_packets -
 504             s->rx_out_of_buffer;
 505         s->rx_bytes =
 506             s->rx_unicast_bytes +
 507             s->rx_multicast_bytes +
 508             s->rx_broadcast_bytes;
 509         s->tx_packets =
 510             s->tx_unicast_packets +
 511             s->tx_multicast_packets +
 512             s->tx_broadcast_packets;
 513         s->tx_bytes =
 514             s->tx_unicast_bytes +
 515             s->tx_multicast_bytes +
 516             s->tx_broadcast_bytes;
 517
 518         /* Update calculated offload counters */
 519         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 520         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 521
 522         /* Update per port counters */
 523         mlx5e_update_pport_counters(priv);
 524
 525 #if (__FreeBSD_version < 1100000)
 526         /* no get_counters interface in fbsd 10 */
 527         ifp->if_ipackets = s->rx_packets;
 528         ifp->if_ierrors = s->rx_error_packets;
 529         ifp->if_iqdrops = s->rx_out_of_buffer;
 530         ifp->if_opackets = s->tx_packets;
 531         ifp->if_oerrors = s->tx_error_packets;
 532         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 533         ifp->if_ibytes = s->rx_bytes;
 534         ifp->if_obytes = s->tx_bytes;
 535 #endif
 536
 537 free_out:
 538         kvfree(out);
 539         PRIV_UNLOCK(priv);
 540 }
 541
 542 static void
 543 mlx5e_update_stats(void *arg)
 544 {
 545         struct mlx5e_priv *priv = arg;
 546
 547         schedule_work(&priv->update_stats_work);
 548
 549         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 550 }
 551
 552 static void
 553 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 554     enum mlx5_dev_event event)
 555 {
 556         switch (event) {
 557         case MLX5_DEV_EVENT_PORT_UP:
 558         case MLX5_DEV_EVENT_PORT_DOWN:
 559                 schedule_work(&priv->update_carrier_work);
 560                 break;
 561
 562         default:
 563                 break;
 564         }
 565 }
 566
 567 static void
 568 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 569     enum mlx5_dev_event event, unsigned long param)
 570 {
 571         struct mlx5e_priv *priv = vpriv;
 572
 573         mtx_lock(&priv->async_events_mtx);
 574         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 575                 mlx5e_async_event_sub(priv, event);
 576         mtx_unlock(&priv->async_events_mtx);
 577 }
 578
 579 static void
 580 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 581 {
 582         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 583 }
 584
 585 static void
 586 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 587 {
 588         mtx_lock(&priv->async_events_mtx);
 589         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 590         mtx_unlock(&priv->async_events_mtx);
 591 }
 592
 593 static const char *mlx5e_rq_stats_desc[] = {
 594         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 595 };
 596
 597 static int
 598 mlx5e_create_rq(struct mlx5e_channel *c,
 599     struct mlx5e_rq_param *param,
 600     struct mlx5e_rq *rq)
 601 {
 602         struct mlx5e_priv *priv = c->priv;
 603         struct mlx5_core_dev *mdev = priv->mdev;
 604         char buffer[16];
 605         void *rqc = param->rqc;
 606         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 607         int wq_sz;
 608         int err;
 609         int i;
 610
 611         /* Create DMA descriptor TAG */
 612         if ((err = -bus_dma_tag_create(
 613             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 614             1,                          /* any alignment */
 615             0,                          /* no boundary */
 616             BUS_SPACE_MAXADDR,          /* lowaddr */
 617             BUS_SPACE_MAXADDR,          /* highaddr */
 618             NULL, NULL,                 /* filter, filterarg */
 619             MJUM16BYTES,                /* maxsize */
 620             1,                          /* nsegments */
 621             MJUM16BYTES,                /* maxsegsize */
 622             0,                          /* flags */
 623             NULL, NULL,                 /* lockfunc, lockfuncarg */
 624             &rq->dma_tag)))
 625                 goto done;
 626
 627         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 628             &rq->wq_ctrl);
 629         if (err)
 630                 goto err_free_dma_tag;
 631
 632         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 633
 634         if (priv->params.hw_lro_en) {
 635                 rq->wqe_sz = priv->params.lro_wqe_sz;
 636         } else {
 637                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 638         }
 639         if (rq->wqe_sz > MJUM16BYTES) {
 640                 err = -ENOMEM;
 641                 goto err_rq_wq_destroy;
 642         } else if (rq->wqe_sz > MJUM9BYTES) {
 643                 rq->wqe_sz = MJUM16BYTES;
 644         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 645                 rq->wqe_sz = MJUM9BYTES;
 646         } else if (rq->wqe_sz > MCLBYTES) {
 647                 rq->wqe_sz = MJUMPAGESIZE;
 648         } else {
 649                 rq->wqe_sz = MCLBYTES;
 650         }
 651
 652         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 653         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 654         if (rq->mbuf == NULL) {
 655                 err = -ENOMEM;
 656                 goto err_rq_wq_destroy;
 657         }
 658         for (i = 0; i != wq_sz; i++) {
 659                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 660                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 661
 662                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 663                 if (err != 0) {
 664                         while (i--)
 665                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 666                         goto err_rq_mbuf_free;
 667                 }
 668                 wqe->data.lkey = c->mkey_be;
 669                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 670         }
 671
 672         rq->pdev = c->pdev;
 673         rq->ifp = c->ifp;
 674         rq->channel = c;
 675         rq->ix = c->ix;
 676
 677         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 678         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 679             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 680             rq->stats.arg);
 681
 682 #ifdef HAVE_TURBO_LRO
 683         if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
 684                 rq->lro.mbuf = NULL;
 685 #else
 686         if (tcp_lro_init(&rq->lro))
 687                 rq->lro.lro_cnt = 0;
 688         else
 689                 rq->lro.ifp = c->ifp;
 690 #endif
 691         return (0);
 692
 693 err_rq_mbuf_free:
 694         free(rq->mbuf, M_MLX5EN);
 695 err_rq_wq_destroy:
 696         mlx5_wq_destroy(&rq->wq_ctrl);
 697 err_free_dma_tag:
 698         bus_dma_tag_destroy(rq->dma_tag);
 699 done:
 700         return (err);
 701 }
 702
 703 static void
 704 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 705 {
 706         int wq_sz;
 707         int i;
 708
 709         /* destroy all sysctl nodes */
 710         sysctl_ctx_free(&rq->stats.ctx);
 711
 712         /* free leftover LRO packets, if any */
 713 #ifdef HAVE_TURBO_LRO
 714         tcp_tlro_free(&rq->lro);
 715 #else
 716         tcp_lro_free(&rq->lro);
 717 #endif
 718         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 719         for (i = 0; i != wq_sz; i++) {
 720                 if (rq->mbuf[i].mbuf != NULL) {
 721                         bus_dmamap_unload(rq->dma_tag,
 722                             rq->mbuf[i].dma_map);
 723                         m_freem(rq->mbuf[i].mbuf);
 724                 }
 725                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 726         }
 727         free(rq->mbuf, M_MLX5EN);
 728         mlx5_wq_destroy(&rq->wq_ctrl);
 729 }
 730
 731 static int
 732 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 733 {
 734         struct mlx5e_channel *c = rq->channel;
 735         struct mlx5e_priv *priv = c->priv;
 736         struct mlx5_core_dev *mdev = priv->mdev;
 737
 738         void *in;
 739         void *rqc;
 740         void *wq;
 741         int inlen;
 742         int err;
 743
 744         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 745             sizeof(u64) * rq->wq_ctrl.buf.npages;
 746         in = mlx5_vzalloc(inlen);
 747         if (in == NULL)
 748                 return (-ENOMEM);
 749
 750         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 751         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 752
 753         memcpy(rqc, param->rqc, sizeof(param->rqc));
 754
 755         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 756         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 757         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 758         if (priv->counter_set_id >= 0)
 759                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 760         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 761             PAGE_SHIFT);
 762         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 763
 764         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 765             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 766
 767         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 768
 769         kvfree(in);
 770
 771         return (err);
 772 }
 773
 774 static int
 775 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 776 {
 777         struct mlx5e_channel *c = rq->channel;
 778         struct mlx5e_priv *priv = c->priv;
 779         struct mlx5_core_dev *mdev = priv->mdev;
 780
 781         void *in;
 782         void *rqc;
 783         int inlen;
 784         int err;
 785
 786         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 787         in = mlx5_vzalloc(inlen);
 788         if (in == NULL)
 789                 return (-ENOMEM);
 790
 791         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 792
 793         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 794         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 795         MLX5_SET(rqc, rqc, state, next_state);
 796
 797         err = mlx5_core_modify_rq(mdev, in, inlen);
 798
 799         kvfree(in);
 800
 801         return (err);
 802 }
 803
 804 static void
 805 mlx5e_disable_rq(struct mlx5e_rq *rq)
 806 {
 807         struct mlx5e_channel *c = rq->channel;
 808         struct mlx5e_priv *priv = c->priv;
 809         struct mlx5_core_dev *mdev = priv->mdev;
 810
 811         mlx5_core_destroy_rq(mdev, rq->rqn);
 812 }
 813
 814 static int
 815 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 816 {
 817         struct mlx5e_channel *c = rq->channel;
 818         struct mlx5e_priv *priv = c->priv;
 819         struct mlx5_wq_ll *wq = &rq->wq;
 820         int i;
 821
 822         for (i = 0; i < 1000; i++) {
 823                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 824                         return (0);
 825
 826                 msleep(4);
 827         }
 828         return (-ETIMEDOUT);
 829 }
 830
 831 static int
 832 mlx5e_open_rq(struct mlx5e_channel *c,
 833     struct mlx5e_rq_param *param,
 834     struct mlx5e_rq *rq)
 835 {
 836         int err;
 837
 838         err = mlx5e_create_rq(c, param, rq);
 839         if (err)
 840                 return (err);
 841
 842         err = mlx5e_enable_rq(rq, param);
 843         if (err)
 844                 goto err_destroy_rq;
 845
 846         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 847         if (err)
 848                 goto err_disable_rq;
 849
 850         c->rq.enabled = 1;
 851
 852         return (0);
 853
 854 err_disable_rq:
 855         mlx5e_disable_rq(rq);
 856 err_destroy_rq:
 857         mlx5e_destroy_rq(rq);
 858
 859         return (err);
 860 }
 861
 862 static void
 863 mlx5e_close_rq(struct mlx5e_rq *rq)
 864 {
 865         rq->enabled = 0;
 866         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 867 }
 868
 869 static void
 870 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 871 {
 872         /* wait till RQ is empty */
 873         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 874                 msleep(4);
 875                 rq->cq.mcq.comp(&rq->cq.mcq);
 876         }
 877
 878         mlx5e_disable_rq(rq);
 879         mlx5e_destroy_rq(rq);
 880 }
 881
 882 void
 883 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 884 {
 885         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 886         int x;
 887
 888         for (x = 0; x != wq_sz; x++)
 889                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 890         free(sq->mbuf, M_MLX5EN);
 891 }
 892
 893 int
 894 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 895 {
 896         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 897         int err;
 898         int x;
 899
 900         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 901         if (sq->mbuf == NULL)
 902                 return (-ENOMEM);
 903
 904         /* Create DMA descriptor MAPs */
 905         for (x = 0; x != wq_sz; x++) {
 906                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 907                 if (err != 0) {
 908                         while (x--)
 909                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 910                         free(sq->mbuf, M_MLX5EN);
 911                         return (err);
 912                 }
 913         }
 914         return (0);
 915 }
 916
 917 static const char *mlx5e_sq_stats_desc[] = {
 918         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 919 };
 920
 921 static int
 922 mlx5e_create_sq(struct mlx5e_channel *c,
 923     int tc,
 924     struct mlx5e_sq_param *param,
 925     struct mlx5e_sq *sq)
 926 {
 927         struct mlx5e_priv *priv = c->priv;
 928         struct mlx5_core_dev *mdev = priv->mdev;
 929         char buffer[16];
 930
 931         void *sqc = param->sqc;
 932         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 933 #ifdef RSS
 934         cpuset_t cpu_mask;
 935         int cpu_id;
 936 #endif
 937         int err;
 938
 939         /* Create DMA descriptor TAG */
 940         if ((err = -bus_dma_tag_create(
 941             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 942             1,                          /* any alignment */
 943             0,                          /* no boundary */
 944             BUS_SPACE_MAXADDR,          /* lowaddr */
 945             BUS_SPACE_MAXADDR,          /* highaddr */
 946             NULL, NULL,                 /* filter, filterarg */
 947             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 948             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 949             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 950             0,                          /* flags */
 951             NULL, NULL,                 /* lockfunc, lockfuncarg */
 952             &sq->dma_tag)))
 953                 goto done;
 954
 955         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 956         if (err)
 957                 goto err_free_dma_tag;
 958
 959         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 960             &sq->wq_ctrl);
 961         if (err)
 962                 goto err_unmap_free_uar;
 963
 964         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 965         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 966
 967         err = mlx5e_alloc_sq_db(sq);
 968         if (err)
 969                 goto err_sq_wq_destroy;
 970
 971         sq->pdev = c->pdev;
 972         sq->mkey_be = c->mkey_be;
 973         sq->ifp = priv->ifp;
 974         sq->priv = priv;
 975         sq->tc = tc;
 976
 977         sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
 978             M_WAITOK, &sq->lock);
 979         if (sq->br == NULL) {
 980                 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
 981                     __func__);
 982                 err = -ENOMEM;
 983                 goto err_free_sq_db;
 984         }
 985
 986         sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
 987             taskqueue_thread_enqueue, &sq->sq_tq);
 988         if (sq->sq_tq == NULL) {
 989                 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
 990                     __func__);
 991                 err = -ENOMEM;
 992                 goto err_free_drbr;
 993         }
 994
 995         TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
 996 #ifdef RSS
 997         cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
 998         CPU_SETOF(cpu_id, &cpu_mask);
 999         taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1000             "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1001 #else
1002         taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1003             "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1004 #endif
1005         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1006         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1007             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1008             sq->stats.arg);
1009
1010         return (0);
1011
1012 err_free_drbr:
1013         buf_ring_free(sq->br, M_MLX5EN);
1014 err_free_sq_db:
1015         mlx5e_free_sq_db(sq);
1016 err_sq_wq_destroy:
1017         mlx5_wq_destroy(&sq->wq_ctrl);
1018
1019 err_unmap_free_uar:
1020         mlx5_unmap_free_uar(mdev, &sq->uar);
1021
1022 err_free_dma_tag:
1023         bus_dma_tag_destroy(sq->dma_tag);
1024 done:
1025         return (err);
1026 }
1027
1028 static void
1029 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1030 {
1031         /* destroy all sysctl nodes */
1032         sysctl_ctx_free(&sq->stats.ctx);
1033
1034         mlx5e_free_sq_db(sq);
1035         mlx5_wq_destroy(&sq->wq_ctrl);
1036         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1037         taskqueue_drain(sq->sq_tq, &sq->sq_task);
1038         taskqueue_free(sq->sq_tq);
1039         buf_ring_free(sq->br, M_MLX5EN);
1040 }
1041
1042 int
1043 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1044     int tis_num)
1045 {
1046         void *in;
1047         void *sqc;
1048         void *wq;
1049         int inlen;
1050         int err;
1051
1052         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1053             sizeof(u64) * sq->wq_ctrl.buf.npages;
1054         in = mlx5_vzalloc(inlen);
1055         if (in == NULL)
1056                 return (-ENOMEM);
1057
1058         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1059         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1060
1061         memcpy(sqc, param->sqc, sizeof(param->sqc));
1062
1063         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1064         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1065         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1066         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1067         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1068
1069         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1070         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1071         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1072             PAGE_SHIFT);
1073         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1074
1075         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1076             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1077
1078         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1079
1080         kvfree(in);
1081
1082         return (err);
1083 }
1084
1085 int
1086 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1087 {
1088         void *in;
1089         void *sqc;
1090         int inlen;
1091         int err;
1092
1093         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1094         in = mlx5_vzalloc(inlen);
1095         if (in == NULL)
1096                 return (-ENOMEM);
1097
1098         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1099
1100         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1101         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1102         MLX5_SET(sqc, sqc, state, next_state);
1103
1104         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1105
1106         kvfree(in);
1107
1108         return (err);
1109 }
1110
1111 void
1112 mlx5e_disable_sq(struct mlx5e_sq *sq)
1113 {
1114
1115         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1116 }
1117
1118 static int
1119 mlx5e_open_sq(struct mlx5e_channel *c,
1120     int tc,
1121     struct mlx5e_sq_param *param,
1122     struct mlx5e_sq *sq)
1123 {
1124         int err;
1125
1126         err = mlx5e_create_sq(c, tc, param, sq);
1127         if (err)
1128                 return (err);
1129
1130         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1131         if (err)
1132                 goto err_destroy_sq;
1133
1134         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1135         if (err)
1136                 goto err_disable_sq;
1137
1138         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1139
1140         return (0);
1141
1142 err_disable_sq:
1143         mlx5e_disable_sq(sq);
1144 err_destroy_sq:
1145         mlx5e_destroy_sq(sq);
1146
1147         return (err);
1148 }
1149
1150 static void
1151 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1152 {
1153         /* fill up remainder with NOPs */
1154         while (sq->cev_counter != 0) {
1155                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1156                         if (can_sleep != 0) {
1157                                 mtx_unlock(&sq->lock);
1158                                 msleep(4);
1159                                 mtx_lock(&sq->lock);
1160                         } else {
1161                                 goto done;
1162                         }
1163                 }
1164                 /* send a single NOP */
1165                 mlx5e_send_nop(sq, 1);
1166                 wmb();
1167         }
1168 done:
1169         /* Check if we need to write the doorbell */
1170         if (likely(sq->doorbell.d64 != 0)) {
1171                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1172                 sq->doorbell.d64 = 0;
1173         }
1174         return;
1175 }
1176
1177 void
1178 mlx5e_sq_cev_timeout(void *arg)
1179 {
1180         struct mlx5e_sq *sq = arg;
1181
1182         mtx_assert(&sq->lock, MA_OWNED);
1183
1184         /* check next state */
1185         switch (sq->cev_next_state) {
1186         case MLX5E_CEV_STATE_SEND_NOPS:
1187                 /* fill TX ring with NOPs, if any */
1188                 mlx5e_sq_send_nops_locked(sq, 0);
1189
1190                 /* check if completed */
1191                 if (sq->cev_counter == 0) {
1192                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1193                         return;
1194                 }
1195                 break;
1196         default:
1197                 /* send NOPs on next timeout */
1198                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1199                 break;
1200         }
1201
1202         /* restart timer */
1203         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1204 }
1205
1206 void
1207 mlx5e_drain_sq(struct mlx5e_sq *sq)
1208 {
1209
1210         mtx_lock(&sq->lock);
1211         /* teardown event factor timer, if any */
1212         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1213         callout_stop(&sq->cev_callout);
1214
1215         /* send dummy NOPs in order to flush the transmit ring */
1216         mlx5e_sq_send_nops_locked(sq, 1);
1217         mtx_unlock(&sq->lock);
1218
1219         /* make sure it is safe to free the callout */
1220         callout_drain(&sq->cev_callout);
1221
1222         /* error out remaining requests */
1223         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1224
1225         /* wait till SQ is empty */
1226         mtx_lock(&sq->lock);
1227         while (sq->cc != sq->pc) {
1228                 mtx_unlock(&sq->lock);
1229                 msleep(4);
1230                 sq->cq.mcq.comp(&sq->cq.mcq);
1231                 mtx_lock(&sq->lock);
1232         }
1233         mtx_unlock(&sq->lock);
1234 }
1235
1236 static void
1237 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1238 {
1239
1240         mlx5e_drain_sq(sq);
1241         mlx5e_disable_sq(sq);
1242         mlx5e_destroy_sq(sq);
1243 }
1244
1245 static int
1246 mlx5e_create_cq(struct mlx5e_priv *priv,
1247     struct mlx5e_cq_param *param,
1248     struct mlx5e_cq *cq,
1249     mlx5e_cq_comp_t *comp,
1250     int eq_ix)
1251 {
1252         struct mlx5_core_dev *mdev = priv->mdev;
1253         struct mlx5_core_cq *mcq = &cq->mcq;
1254         int eqn_not_used;
1255         int irqn;
1256         int err;
1257         u32 i;
1258
1259         param->wq.buf_numa_node = 0;
1260         param->wq.db_numa_node = 0;
1261
1262         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1263             &cq->wq_ctrl);
1264         if (err)
1265                 return (err);
1266
1267         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1268
1269         mcq->cqe_sz = 64;
1270         mcq->set_ci_db = cq->wq_ctrl.db.db;
1271         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1272         *mcq->set_ci_db = 0;
1273         *mcq->arm_db = 0;
1274         mcq->vector = eq_ix;
1275         mcq->comp = comp;
1276         mcq->event = mlx5e_cq_error_event;
1277         mcq->irqn = irqn;
1278         mcq->uar = &priv->cq_uar;
1279
1280         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1281                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1282
1283                 cqe->op_own = 0xf1;
1284         }
1285
1286         cq->priv = priv;
1287
1288         return (0);
1289 }
1290
1291 static void
1292 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1293 {
1294         mlx5_wq_destroy(&cq->wq_ctrl);
1295 }
1296
1297 static int
1298 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1299 {
1300         struct mlx5_core_cq *mcq = &cq->mcq;
1301         void *in;
1302         void *cqc;
1303         int inlen;
1304         int irqn_not_used;
1305         int eqn;
1306         int err;
1307
1308         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1309             sizeof(u64) * cq->wq_ctrl.buf.npages;
1310         in = mlx5_vzalloc(inlen);
1311         if (in == NULL)
1312                 return (-ENOMEM);
1313
1314         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1315
1316         memcpy(cqc, param->cqc, sizeof(param->cqc));
1317
1318         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1319             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1320
1321         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1322
1323         MLX5_SET(cqc, cqc, c_eqn, eqn);
1324         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1325         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1326             PAGE_SHIFT);
1327         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1328
1329         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1330
1331         kvfree(in);
1332
1333         if (err)
1334                 return (err);
1335
1336         mlx5e_cq_arm(cq);
1337
1338         return (0);
1339 }
1340
1341 static void
1342 mlx5e_disable_cq(struct mlx5e_cq *cq)
1343 {
1344
1345         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1346 }
1347
1348 int
1349 mlx5e_open_cq(struct mlx5e_priv *priv,
1350     struct mlx5e_cq_param *param,
1351     struct mlx5e_cq *cq,
1352     mlx5e_cq_comp_t *comp,
1353     int eq_ix)
1354 {
1355         int err;
1356
1357         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1358         if (err)
1359                 return (err);
1360
1361         err = mlx5e_enable_cq(cq, param, eq_ix);
1362         if (err)
1363                 goto err_destroy_cq;
1364
1365         return (0);
1366
1367 err_destroy_cq:
1368         mlx5e_destroy_cq(cq);
1369
1370         return (err);
1371 }
1372
1373 void
1374 mlx5e_close_cq(struct mlx5e_cq *cq)
1375 {
1376         mlx5e_disable_cq(cq);
1377         mlx5e_destroy_cq(cq);
1378 }
1379
1380 static int
1381 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1382     struct mlx5e_channel_param *cparam)
1383 {
1384         int err;
1385         int tc;
1386
1387         for (tc = 0; tc < c->num_tc; tc++) {
1388                 /* open completion queue */
1389                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1390                     &mlx5e_tx_cq_comp, c->ix);
1391                 if (err)
1392                         goto err_close_tx_cqs;
1393         }
1394         return (0);
1395
1396 err_close_tx_cqs:
1397         for (tc--; tc >= 0; tc--)
1398                 mlx5e_close_cq(&c->sq[tc].cq);
1399
1400         return (err);
1401 }
1402
1403 static void
1404 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1405 {
1406         int tc;
1407
1408         for (tc = 0; tc < c->num_tc; tc++)
1409                 mlx5e_close_cq(&c->sq[tc].cq);
1410 }
1411
1412 static int
1413 mlx5e_open_sqs(struct mlx5e_channel *c,
1414     struct mlx5e_channel_param *cparam)
1415 {
1416         int err;
1417         int tc;
1418
1419         for (tc = 0; tc < c->num_tc; tc++) {
1420                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1421                 if (err)
1422                         goto err_close_sqs;
1423         }
1424
1425         return (0);
1426
1427 err_close_sqs:
1428         for (tc--; tc >= 0; tc--)
1429                 mlx5e_close_sq_wait(&c->sq[tc]);
1430
1431         return (err);
1432 }
1433
1434 static void
1435 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1436 {
1437         int tc;
1438
1439         for (tc = 0; tc < c->num_tc; tc++)
1440                 mlx5e_close_sq_wait(&c->sq[tc]);
1441 }
1442
1443 static void
1444 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1445 {
1446         int tc;
1447
1448         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1449
1450         for (tc = 0; tc < c->num_tc; tc++) {
1451                 struct mlx5e_sq *sq = c->sq + tc;
1452
1453                 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1454                 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1455                     MTX_DEF);
1456
1457                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1458
1459                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1460
1461                 /* ensure the TX completion event factor is not zero */
1462                 if (sq->cev_factor == 0)
1463                         sq->cev_factor = 1;
1464         }
1465 }
1466
1467 static void
1468 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1469 {
1470         int tc;
1471
1472         mtx_destroy(&c->rq.mtx);
1473
1474         for (tc = 0; tc < c->num_tc; tc++) {
1475                 mtx_destroy(&c->sq[tc].lock);
1476                 mtx_destroy(&c->sq[tc].comp_lock);
1477         }
1478 }
1479
1480 static int
1481 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1482     struct mlx5e_channel_param *cparam,
1483     struct mlx5e_channel *volatile *cp)
1484 {
1485         struct mlx5e_channel *c;
1486         int err;
1487
1488         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1489         if (c == NULL)
1490                 return (-ENOMEM);
1491
1492         c->priv = priv;
1493         c->ix = ix;
1494         c->cpu = 0;
1495         c->pdev = &priv->mdev->pdev->dev;
1496         c->ifp = priv->ifp;
1497         c->mkey_be = cpu_to_be32(priv->mr.key);
1498         c->num_tc = priv->num_tc;
1499
1500         /* init mutexes */
1501         mlx5e_chan_mtx_init(c);
1502
1503         /* open transmit completion queue */
1504         err = mlx5e_open_tx_cqs(c, cparam);
1505         if (err)
1506                 goto err_free;
1507
1508         /* open receive completion queue */
1509         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1510             &mlx5e_rx_cq_comp, c->ix);
1511         if (err)
1512                 goto err_close_tx_cqs;
1513
1514         err = mlx5e_open_sqs(c, cparam);
1515         if (err)
1516                 goto err_close_rx_cq;
1517
1518         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1519         if (err)
1520                 goto err_close_sqs;
1521
1522         /* store channel pointer */
1523         *cp = c;
1524
1525         /* poll receive queue initially */
1526         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1527
1528         return (0);
1529
1530 err_close_sqs:
1531         mlx5e_close_sqs_wait(c);
1532
1533 err_close_rx_cq:
1534         mlx5e_close_cq(&c->rq.cq);
1535
1536 err_close_tx_cqs:
1537         mlx5e_close_tx_cqs(c);
1538
1539 err_free:
1540         /* destroy mutexes */
1541         mlx5e_chan_mtx_destroy(c);
1542         free(c, M_MLX5EN);
1543         return (err);
1544 }
1545
1546 static void
1547 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1548 {
1549         struct mlx5e_channel *c = *pp;
1550
1551         /* check if channel is already closed */
1552         if (c == NULL)
1553                 return;
1554         mlx5e_close_rq(&c->rq);
1555 }
1556
1557 static void
1558 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1559 {
1560         struct mlx5e_channel *c = *pp;
1561
1562         /* check if channel is already closed */
1563         if (c == NULL)
1564                 return;
1565         /* ensure channel pointer is no longer used */
1566         *pp = NULL;
1567
1568         mlx5e_close_rq_wait(&c->rq);
1569         mlx5e_close_sqs_wait(c);
1570         mlx5e_close_cq(&c->rq.cq);
1571         mlx5e_close_tx_cqs(c);
1572         /* destroy mutexes */
1573         mlx5e_chan_mtx_destroy(c);
1574         free(c, M_MLX5EN);
1575 }
1576
1577 static void
1578 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1579     struct mlx5e_rq_param *param)
1580 {
1581         void *rqc = param->rqc;
1582         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1583
1584         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1585         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1586         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1587         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1588         MLX5_SET(wq, wq, pd, priv->pdn);
1589
1590         param->wq.buf_numa_node = 0;
1591         param->wq.db_numa_node = 0;
1592         param->wq.linear = 1;
1593 }
1594
1595 static void
1596 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1597     struct mlx5e_sq_param *param)
1598 {
1599         void *sqc = param->sqc;
1600         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1601
1602         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1603         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1604         MLX5_SET(wq, wq, pd, priv->pdn);
1605
1606         param->wq.buf_numa_node = 0;
1607         param->wq.db_numa_node = 0;
1608         param->wq.linear = 1;
1609 }
1610
1611 static void
1612 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1613     struct mlx5e_cq_param *param)
1614 {
1615         void *cqc = param->cqc;
1616
1617         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1618 }
1619
1620 static void
1621 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1622     struct mlx5e_cq_param *param)
1623 {
1624         void *cqc = param->cqc;
1625
1626
1627         /*
1628          * TODO The sysctl to control on/off is a bool value for now, which means
1629          * we only support CSUM, once HASH is implemnted we'll need to address that.
1630          */
1631         if (priv->params.cqe_zipping_en) {
1632                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1633                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1634         }
1635
1636         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1637         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1638         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1639
1640         switch (priv->params.rx_cq_moderation_mode) {
1641         case 0:
1642                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1643                 break;
1644         default:
1645                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1646                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1647                 else
1648                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1649                 break;
1650         }
1651
1652         mlx5e_build_common_cq_param(priv, param);
1653 }
1654
1655 static void
1656 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1657     struct mlx5e_cq_param *param)
1658 {
1659         void *cqc = param->cqc;
1660
1661         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1662         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1663         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1664
1665         switch (priv->params.tx_cq_moderation_mode) {
1666         case 0:
1667                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1668                 break;
1669         default:
1670                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1671                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1672                 else
1673                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1674                 break;
1675         }
1676
1677         mlx5e_build_common_cq_param(priv, param);
1678 }
1679
1680 static void
1681 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1682     struct mlx5e_channel_param *cparam)
1683 {
1684         memset(cparam, 0, sizeof(*cparam));
1685
1686         mlx5e_build_rq_param(priv, &cparam->rq);
1687         mlx5e_build_sq_param(priv, &cparam->sq);
1688         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1689         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1690 }
1691
1692 static int
1693 mlx5e_open_channels(struct mlx5e_priv *priv)
1694 {
1695         struct mlx5e_channel_param cparam;
1696         void *ptr;
1697         int err;
1698         int i;
1699         int j;
1700
1701         priv->channel = malloc(priv->params.num_channels *
1702             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1703         if (priv->channel == NULL)
1704                 return (-ENOMEM);
1705
1706         mlx5e_build_channel_param(priv, &cparam);
1707         for (i = 0; i < priv->params.num_channels; i++) {
1708                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1709                 if (err)
1710                         goto err_close_channels;
1711         }
1712
1713         for (j = 0; j < priv->params.num_channels; j++) {
1714                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1715                 if (err)
1716                         goto err_close_channels;
1717         }
1718
1719         return (0);
1720
1721 err_close_channels:
1722         for (i--; i >= 0; i--) {
1723                 mlx5e_close_channel(&priv->channel[i]);
1724                 mlx5e_close_channel_wait(&priv->channel[i]);
1725         }
1726
1727         /* remove "volatile" attribute from "channel" pointer */
1728         ptr = __DECONST(void *, priv->channel);
1729         priv->channel = NULL;
1730
1731         free(ptr, M_MLX5EN);
1732
1733         return (err);
1734 }
1735
1736 static void
1737 mlx5e_close_channels(struct mlx5e_priv *priv)
1738 {
1739         void *ptr;
1740         int i;
1741
1742         if (priv->channel == NULL)
1743                 return;
1744
1745         for (i = 0; i < priv->params.num_channels; i++)
1746                 mlx5e_close_channel(&priv->channel[i]);
1747         for (i = 0; i < priv->params.num_channels; i++)
1748                 mlx5e_close_channel_wait(&priv->channel[i]);
1749
1750         /* remove "volatile" attribute from "channel" pointer */
1751         ptr = __DECONST(void *, priv->channel);
1752         priv->channel = NULL;
1753
1754         free(ptr, M_MLX5EN);
1755 }
1756
1757 static int
1758 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1759 {
1760         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1761             priv->params.tx_cq_moderation_usec,
1762             priv->params.tx_cq_moderation_pkts));
1763 }
1764
1765 static int
1766 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1767 {
1768         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1769             priv->params.rx_cq_moderation_usec,
1770             priv->params.rx_cq_moderation_pkts));
1771 }
1772
1773 static int
1774 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1775 {
1776         int err;
1777         int i;
1778
1779         if (c == NULL)
1780                 return (EINVAL);
1781
1782         err = mlx5e_refresh_rq_params(priv, &c->rq);
1783         if (err)
1784                 goto done;
1785
1786         for (i = 0; i != c->num_tc; i++) {
1787                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1788                 if (err)
1789                         goto done;
1790         }
1791 done:
1792         return (err);
1793 }
1794
1795 int
1796 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1797 {
1798         int i;
1799
1800         if (priv->channel == NULL)
1801                 return (EINVAL);
1802
1803         for (i = 0; i < priv->params.num_channels; i++) {
1804                 int err;
1805
1806                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1807                 if (err)
1808                         return (err);
1809         }
1810         return (0);
1811 }
1812
1813 static int
1814 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1815 {
1816         struct mlx5_core_dev *mdev = priv->mdev;
1817         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1818         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1819
1820         memset(in, 0, sizeof(in));
1821
1822         MLX5_SET(tisc, tisc, prio, tc);
1823         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1824
1825         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1826 }
1827
1828 static void
1829 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1830 {
1831         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1832 }
1833
1834 static int
1835 mlx5e_open_tises(struct mlx5e_priv *priv)
1836 {
1837         int num_tc = priv->num_tc;
1838         int err;
1839         int tc;
1840
1841         for (tc = 0; tc < num_tc; tc++) {
1842                 err = mlx5e_open_tis(priv, tc);
1843                 if (err)
1844                         goto err_close_tises;
1845         }
1846
1847         return (0);
1848
1849 err_close_tises:
1850         for (tc--; tc >= 0; tc--)
1851                 mlx5e_close_tis(priv, tc);
1852
1853         return (err);
1854 }
1855
1856 static void
1857 mlx5e_close_tises(struct mlx5e_priv *priv)
1858 {
1859         int num_tc = priv->num_tc;
1860         int tc;
1861
1862         for (tc = 0; tc < num_tc; tc++)
1863                 mlx5e_close_tis(priv, tc);
1864 }
1865
1866 static int
1867 mlx5e_open_rqt(struct mlx5e_priv *priv)
1868 {
1869         struct mlx5_core_dev *mdev = priv->mdev;
1870         u32 *in;
1871         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1872         void *rqtc;
1873         int inlen;
1874         int err;
1875         int sz;
1876         int i;
1877
1878         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1879
1880         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1881         in = mlx5_vzalloc(inlen);
1882         if (in == NULL)
1883                 return (-ENOMEM);
1884         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1885
1886         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1887         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1888
1889         for (i = 0; i < sz; i++) {
1890                 int ix;
1891 #ifdef RSS
1892                 ix = rss_get_indirection_to_bucket(i);
1893 #else
1894                 ix = i;
1895 #endif
1896                 /* ensure we don't overflow */
1897                 ix %= priv->params.num_channels;
1898                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1899         }
1900
1901         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1902
1903         memset(out, 0, sizeof(out));
1904         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1905         if (!err)
1906                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1907
1908         kvfree(in);
1909
1910         return (err);
1911 }
1912
1913 static void
1914 mlx5e_close_rqt(struct mlx5e_priv *priv)
1915 {
1916         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1917         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1918
1919         memset(in, 0, sizeof(in));
1920
1921         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1922         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1923
1924         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1925             sizeof(out));
1926 }
1927
1928 static void
1929 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1930 {
1931         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1932         __be32 *hkey;
1933
1934         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1935
1936 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1937
1938 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1939                           MLX5_HASH_FIELD_SEL_DST_IP)
1940
1941 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1942                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1943                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1944                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1945
1946 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1947                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1948                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1949
1950         if (priv->params.hw_lro_en) {
1951                 MLX5_SET(tirc, tirc, lro_enable_mask,
1952                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1953                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1954                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1955                     (priv->params.lro_wqe_sz -
1956                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1957                 /* TODO: add the option to choose timer value dynamically */
1958                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1959                     MLX5_CAP_ETH(priv->mdev,
1960                     lro_timer_supported_periods[2]));
1961         }
1962
1963         /* setup parameters for hashing TIR type, if any */
1964         switch (tt) {
1965         case MLX5E_TT_ANY:
1966                 MLX5_SET(tirc, tirc, disp_type,
1967                     MLX5_TIRC_DISP_TYPE_DIRECT);
1968                 MLX5_SET(tirc, tirc, inline_rqn,
1969                     priv->channel[0]->rq.rqn);
1970                 break;
1971         default:
1972                 MLX5_SET(tirc, tirc, disp_type,
1973                     MLX5_TIRC_DISP_TYPE_INDIRECT);
1974                 MLX5_SET(tirc, tirc, indirect_table,
1975                     priv->rqtn);
1976                 MLX5_SET(tirc, tirc, rx_hash_fn,
1977                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1978                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1979 #ifdef RSS
1980                 /*
1981                  * The FreeBSD RSS implementation does currently not
1982                  * support symmetric Toeplitz hashes:
1983                  */
1984                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
1985                 rss_getkey((uint8_t *)hkey);
1986 #else
1987                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1988                 hkey[0] = cpu_to_be32(0xD181C62C);
1989                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
1990                 hkey[2] = cpu_to_be32(0x1983A2FC);
1991                 hkey[3] = cpu_to_be32(0x943E1ADB);
1992                 hkey[4] = cpu_to_be32(0xD9389E6B);
1993                 hkey[5] = cpu_to_be32(0xD1039C2C);
1994                 hkey[6] = cpu_to_be32(0xA74499AD);
1995                 hkey[7] = cpu_to_be32(0x593D56D9);
1996                 hkey[8] = cpu_to_be32(0xF3253C06);
1997                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
1998 #endif
1999                 break;
2000         }
2001
2002         switch (tt) {
2003         case MLX5E_TT_IPV4_TCP:
2004                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2005                     MLX5_L3_PROT_TYPE_IPV4);
2006                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2007                     MLX5_L4_PROT_TYPE_TCP);
2008 #ifdef RSS
2009                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2010                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2011                             MLX5_HASH_IP);
2012                 } else
2013 #endif
2014                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2015                     MLX5_HASH_ALL);
2016                 break;
2017
2018         case MLX5E_TT_IPV6_TCP:
2019                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2020                     MLX5_L3_PROT_TYPE_IPV6);
2021                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2022                     MLX5_L4_PROT_TYPE_TCP);
2023 #ifdef RSS
2024                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2025                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2026                             MLX5_HASH_IP);
2027                 } else
2028 #endif
2029                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2030                     MLX5_HASH_ALL);
2031                 break;
2032
2033         case MLX5E_TT_IPV4_UDP:
2034                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2035                     MLX5_L3_PROT_TYPE_IPV4);
2036                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2037                     MLX5_L4_PROT_TYPE_UDP);
2038 #ifdef RSS
2039                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2040                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2041                             MLX5_HASH_IP);
2042                 } else
2043 #endif
2044                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2045                     MLX5_HASH_ALL);
2046                 break;
2047
2048         case MLX5E_TT_IPV6_UDP:
2049                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2050                     MLX5_L3_PROT_TYPE_IPV6);
2051                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2052                     MLX5_L4_PROT_TYPE_UDP);
2053 #ifdef RSS
2054                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2055                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2056                             MLX5_HASH_IP);
2057                 } else
2058 #endif
2059                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2060                     MLX5_HASH_ALL);
2061                 break;
2062
2063         case MLX5E_TT_IPV4_IPSEC_AH:
2064                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2065                     MLX5_L3_PROT_TYPE_IPV4);
2066                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2067                     MLX5_HASH_IP_IPSEC_SPI);
2068                 break;
2069
2070         case MLX5E_TT_IPV6_IPSEC_AH:
2071                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2072                     MLX5_L3_PROT_TYPE_IPV6);
2073                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2074                     MLX5_HASH_IP_IPSEC_SPI);
2075                 break;
2076
2077         case MLX5E_TT_IPV4_IPSEC_ESP:
2078                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2079                     MLX5_L3_PROT_TYPE_IPV4);
2080                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2081                     MLX5_HASH_IP_IPSEC_SPI);
2082                 break;
2083
2084         case MLX5E_TT_IPV6_IPSEC_ESP:
2085                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2086                     MLX5_L3_PROT_TYPE_IPV6);
2087                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2088                     MLX5_HASH_IP_IPSEC_SPI);
2089                 break;
2090
2091         case MLX5E_TT_IPV4:
2092                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2093                     MLX5_L3_PROT_TYPE_IPV4);
2094                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095                     MLX5_HASH_IP);
2096                 break;
2097
2098         case MLX5E_TT_IPV6:
2099                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2100                     MLX5_L3_PROT_TYPE_IPV6);
2101                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2102                     MLX5_HASH_IP);
2103                 break;
2104
2105         default:
2106                 break;
2107         }
2108 }
2109
2110 static int
2111 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2112 {
2113         struct mlx5_core_dev *mdev = priv->mdev;
2114         u32 *in;
2115         void *tirc;
2116         int inlen;
2117         int err;
2118
2119         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2120         in = mlx5_vzalloc(inlen);
2121         if (in == NULL)
2122                 return (-ENOMEM);
2123         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2124
2125         mlx5e_build_tir_ctx(priv, tirc, tt);
2126
2127         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2128
2129         kvfree(in);
2130
2131         return (err);
2132 }
2133
2134 static void
2135 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2136 {
2137         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2138 }
2139
2140 static int
2141 mlx5e_open_tirs(struct mlx5e_priv *priv)
2142 {
2143         int err;
2144         int i;
2145
2146         for (i = 0; i < MLX5E_NUM_TT; i++) {
2147                 err = mlx5e_open_tir(priv, i);
2148                 if (err)
2149                         goto err_close_tirs;
2150         }
2151
2152         return (0);
2153
2154 err_close_tirs:
2155         for (i--; i >= 0; i--)
2156                 mlx5e_close_tir(priv, i);
2157
2158         return (err);
2159 }
2160
2161 static void
2162 mlx5e_close_tirs(struct mlx5e_priv *priv)
2163 {
2164         int i;
2165
2166         for (i = 0; i < MLX5E_NUM_TT; i++)
2167                 mlx5e_close_tir(priv, i);
2168 }
2169
2170 /*
2171  * SW MTU does not include headers,
2172  * HW MTU includes all headers and checksums.
2173  */
2174 static int
2175 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2176 {
2177         struct mlx5e_priv *priv = ifp->if_softc;
2178         struct mlx5_core_dev *mdev = priv->mdev;
2179         int hw_mtu;
2180         int err;
2181
2182
2183         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2184         if (err) {
2185                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2186                     __func__, sw_mtu, err);
2187                 return (err);
2188         }
2189         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2190         if (!err) {
2191                 ifp->if_mtu = MLX5E_HW2SW_MTU(hw_mtu);
2192
2193                 if (ifp->if_mtu != sw_mtu) {
2194                         if_printf(ifp, "Port MTU %d is different than "
2195                             "ifp mtu %d\n", sw_mtu, (int)ifp->if_mtu);
2196                 }
2197         } else {
2198                 if_printf(ifp, "Query port MTU, after setting new "
2199                     "MTU value, failed\n");
2200                 ifp->if_mtu = sw_mtu;
2201         }
2202         return (0);
2203 }
2204
2205 int
2206 mlx5e_open_locked(struct ifnet *ifp)
2207 {
2208         struct mlx5e_priv *priv = ifp->if_softc;
2209         int err;
2210         u16 set_id;
2211
2212         /* check if already opened */
2213         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2214                 return (0);
2215
2216 #ifdef RSS
2217         if (rss_getnumbuckets() > priv->params.num_channels) {
2218                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2219                     "channels(%u) available\n", rss_getnumbuckets(),
2220                     priv->params.num_channels);
2221         }
2222 #endif
2223         err = mlx5e_open_tises(priv);
2224         if (err) {
2225                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2226                     __func__, err);
2227                 return (err);
2228         }
2229         err = mlx5_vport_alloc_q_counter(priv->mdev,
2230             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2231         if (err) {
2232                 if_printf(priv->ifp,
2233                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2234                     __func__, err);
2235                 goto err_close_tises;
2236         }
2237         /* store counter set ID */
2238         priv->counter_set_id = set_id;
2239
2240         err = mlx5e_open_channels(priv);
2241         if (err) {
2242                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2243                     __func__, err);
2244                 goto err_dalloc_q_counter;
2245         }
2246         err = mlx5e_open_rqt(priv);
2247         if (err) {
2248                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2249                     __func__, err);
2250                 goto err_close_channels;
2251         }
2252         err = mlx5e_open_tirs(priv);
2253         if (err) {
2254                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2255                     __func__, err);
2256                 goto err_close_rqls;
2257         }
2258         err = mlx5e_open_flow_table(priv);
2259         if (err) {
2260                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2261                     __func__, err);
2262                 goto err_close_tirs;
2263         }
2264         err = mlx5e_add_all_vlan_rules(priv);
2265         if (err) {
2266                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2267                     __func__, err);
2268                 goto err_close_flow_table;
2269         }
2270         set_bit(MLX5E_STATE_OPENED, &priv->state);
2271
2272         mlx5e_update_carrier(priv);
2273         mlx5e_set_rx_mode_core(priv);
2274
2275         return (0);
2276
2277 err_close_flow_table:
2278         mlx5e_close_flow_table(priv);
2279
2280 err_close_tirs:
2281         mlx5e_close_tirs(priv);
2282
2283 err_close_rqls:
2284         mlx5e_close_rqt(priv);
2285
2286 err_close_channels:
2287         mlx5e_close_channels(priv);
2288
2289 err_dalloc_q_counter:
2290         mlx5_vport_dealloc_q_counter(priv->mdev,
2291             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2292
2293 err_close_tises:
2294         mlx5e_close_tises(priv);
2295
2296         return (err);
2297 }
2298
2299 static void
2300 mlx5e_open(void *arg)
2301 {
2302         struct mlx5e_priv *priv = arg;
2303
2304         PRIV_LOCK(priv);
2305         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2306                 if_printf(priv->ifp,
2307                     "%s: Setting port status to up failed\n",
2308                     __func__);
2309
2310         mlx5e_open_locked(priv->ifp);
2311         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2312         PRIV_UNLOCK(priv);
2313 }
2314
2315 int
2316 mlx5e_close_locked(struct ifnet *ifp)
2317 {
2318         struct mlx5e_priv *priv = ifp->if_softc;
2319
2320         /* check if already closed */
2321         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2322                 return (0);
2323
2324         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2325
2326         mlx5e_set_rx_mode_core(priv);
2327         mlx5e_del_all_vlan_rules(priv);
2328         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2329         mlx5e_close_flow_table(priv);
2330         mlx5e_close_tirs(priv);
2331         mlx5e_close_rqt(priv);
2332         mlx5e_close_channels(priv);
2333         mlx5_vport_dealloc_q_counter(priv->mdev,
2334             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2335         mlx5e_close_tises(priv);
2336
2337         return (0);
2338 }
2339
2340 #if (__FreeBSD_version >= 1100000)
2341 static uint64_t
2342 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2343 {
2344         struct mlx5e_priv *priv = ifp->if_softc;
2345         u64 retval;
2346
2347         /* PRIV_LOCK(priv); XXX not allowed */
2348         switch (cnt) {
2349         case IFCOUNTER_IPACKETS:
2350                 retval = priv->stats.vport.rx_packets;
2351                 break;
2352         case IFCOUNTER_IERRORS:
2353                 retval = priv->stats.vport.rx_error_packets;
2354                 break;
2355         case IFCOUNTER_IQDROPS:
2356                 retval = priv->stats.vport.rx_out_of_buffer;
2357                 break;
2358         case IFCOUNTER_OPACKETS:
2359                 retval = priv->stats.vport.tx_packets;
2360                 break;
2361         case IFCOUNTER_OERRORS:
2362                 retval = priv->stats.vport.tx_error_packets;
2363                 break;
2364         case IFCOUNTER_IBYTES:
2365                 retval = priv->stats.vport.rx_bytes;
2366                 break;
2367         case IFCOUNTER_OBYTES:
2368                 retval = priv->stats.vport.tx_bytes;
2369                 break;
2370         case IFCOUNTER_IMCASTS:
2371                 retval = priv->stats.vport.rx_multicast_packets;
2372                 break;
2373         case IFCOUNTER_OMCASTS:
2374                 retval = priv->stats.vport.tx_multicast_packets;
2375                 break;
2376         case IFCOUNTER_OQDROPS:
2377                 retval = priv->stats.vport.tx_queue_dropped;
2378                 break;
2379         default:
2380                 retval = if_get_counter_default(ifp, cnt);
2381                 break;
2382         }
2383         /* PRIV_UNLOCK(priv); XXX not allowed */
2384         return (retval);
2385 }
2386 #endif
2387
2388 static void
2389 mlx5e_set_rx_mode(struct ifnet *ifp)
2390 {
2391         struct mlx5e_priv *priv = ifp->if_softc;
2392
2393         schedule_work(&priv->set_rx_mode_work);
2394 }
2395
2396 static int
2397 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2398 {
2399         struct mlx5e_priv *priv;
2400         struct ifreq *ifr;
2401         struct ifi2creq i2c;
2402         int error = 0;
2403         int mask = 0;
2404         int size_read = 0;
2405         int module_num;
2406         int max_mtu;
2407         uint8_t read_addr;
2408
2409         priv = ifp->if_softc;
2410
2411         /* check if detaching */
2412         if (priv == NULL || priv->gone != 0)
2413                 return (ENXIO);
2414
2415         switch (command) {
2416         case SIOCSIFMTU:
2417                 ifr = (struct ifreq *)data;
2418
2419                 PRIV_LOCK(priv);
2420                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2421
2422                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2423                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2424                         int was_opened;
2425
2426                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2427                         if (was_opened)
2428                                 mlx5e_close_locked(ifp);
2429
2430                         /* set new MTU */
2431                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2432
2433                         if (was_opened)
2434                                 mlx5e_open_locked(ifp);
2435                 } else {
2436                         error = EINVAL;
2437                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2438                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2439                 }
2440                 PRIV_UNLOCK(priv);
2441                 break;
2442         case SIOCSIFFLAGS:
2443                 if ((ifp->if_flags & IFF_UP) &&
2444                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2445                         mlx5e_set_rx_mode(ifp);
2446                         break;
2447                 }
2448                 PRIV_LOCK(priv);
2449                 if (ifp->if_flags & IFF_UP) {
2450                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2451                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2452                                         mlx5e_open_locked(ifp);
2453                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2454                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2455                         }
2456                 } else {
2457                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2458                                 mlx5_set_port_status(priv->mdev,
2459                                     MLX5_PORT_DOWN);
2460                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2461                                         mlx5e_close_locked(ifp);
2462                                 mlx5e_update_carrier(priv);
2463                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2464                         }
2465                 }
2466                 PRIV_UNLOCK(priv);
2467                 break;
2468         case SIOCADDMULTI:
2469         case SIOCDELMULTI:
2470                 mlx5e_set_rx_mode(ifp);
2471                 break;
2472         case SIOCSIFMEDIA:
2473         case SIOCGIFMEDIA:
2474         case SIOCGIFXMEDIA:
2475                 ifr = (struct ifreq *)data;
2476                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2477                 break;
2478         case SIOCSIFCAP:
2479                 ifr = (struct ifreq *)data;
2480                 PRIV_LOCK(priv);
2481                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2482
2483                 if (mask & IFCAP_TXCSUM) {
2484                         ifp->if_capenable ^= IFCAP_TXCSUM;
2485                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2486
2487                         if (IFCAP_TSO4 & ifp->if_capenable &&
2488                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2489                                 ifp->if_capenable &= ~IFCAP_TSO4;
2490                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2491                                 if_printf(ifp,
2492                                     "tso4 disabled due to -txcsum.\n");
2493                         }
2494                 }
2495                 if (mask & IFCAP_TXCSUM_IPV6) {
2496                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2497                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2498
2499                         if (IFCAP_TSO6 & ifp->if_capenable &&
2500                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2501                                 ifp->if_capenable &= ~IFCAP_TSO6;
2502                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2503                                 if_printf(ifp,
2504                                     "tso6 disabled due to -txcsum6.\n");
2505                         }
2506                 }
2507                 if (mask & IFCAP_RXCSUM)
2508                         ifp->if_capenable ^= IFCAP_RXCSUM;
2509                 if (mask & IFCAP_RXCSUM_IPV6)
2510                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2511                 if (mask & IFCAP_TSO4) {
2512                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2513                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2514                                 if_printf(ifp, "enable txcsum first.\n");
2515                                 error = EAGAIN;
2516                                 goto out;
2517                         }
2518                         ifp->if_capenable ^= IFCAP_TSO4;
2519                         ifp->if_hwassist ^= CSUM_IP_TSO;
2520                 }
2521                 if (mask & IFCAP_TSO6) {
2522                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2523                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2524                                 if_printf(ifp, "enable txcsum6 first.\n");
2525                                 error = EAGAIN;
2526                                 goto out;
2527                         }
2528                         ifp->if_capenable ^= IFCAP_TSO6;
2529                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2530                 }
2531                 if (mask & IFCAP_VLAN_HWFILTER) {
2532                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2533                                 mlx5e_disable_vlan_filter(priv);
2534                         else
2535                                 mlx5e_enable_vlan_filter(priv);
2536
2537                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2538                 }
2539                 if (mask & IFCAP_VLAN_HWTAGGING)
2540                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2541                 if (mask & IFCAP_WOL_MAGIC)
2542                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2543
2544                 VLAN_CAPABILITIES(ifp);
2545                 /* turn off LRO means also turn of HW LRO - if it's on */
2546                 if (mask & IFCAP_LRO) {
2547                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2548                         bool need_restart = false;
2549
2550                         ifp->if_capenable ^= IFCAP_LRO;
2551                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2552                                 if (priv->params.hw_lro_en) {
2553                                         priv->params.hw_lro_en = false;
2554                                         need_restart = true;
2555                                         /* Not sure this is the correct way */
2556                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2557                                 }
2558                         }
2559                         if (was_opened && need_restart) {
2560                                 mlx5e_close_locked(ifp);
2561                                 mlx5e_open_locked(ifp);
2562                         }
2563                 }
2564 out:
2565                 PRIV_UNLOCK(priv);
2566                 break;
2567
2568         case SIOCGI2C:
2569                 ifr = (struct ifreq *)data;
2570
2571                 /*
2572                  * Copy from the user-space address ifr_data to the
2573                  * kernel-space address i2c
2574                  */
2575                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2576                 if (error)
2577                         break;
2578
2579                 if (i2c.len > sizeof(i2c.data)) {
2580                         error = EINVAL;
2581                         break;
2582                 }
2583
2584                 PRIV_LOCK(priv);
2585                 /* Get module_num which is required for the query_eeprom */
2586                 error = mlx5_query_module_num(priv->mdev, &module_num);
2587                 if (error) {
2588                         if_printf(ifp, "Query module num failed, eeprom "
2589                             "reading is not supported\n");
2590                         error = EINVAL;
2591                         goto err_i2c;
2592                 }
2593                 /* Check if module is present before doing an access */
2594                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2595                     MLX5_MODULE_STATUS_PLUGGED) {
2596                         error = EINVAL;
2597                         goto err_i2c;
2598                 }
2599                 /*
2600                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2601                  * The internal conversion is as follows:
2602                  */
2603                 if (i2c.dev_addr == 0xA0)
2604                         read_addr = MLX5E_I2C_ADDR_LOW;
2605                 else if (i2c.dev_addr == 0xA2)
2606                         read_addr = MLX5E_I2C_ADDR_HIGH;
2607                 else {
2608                         if_printf(ifp, "Query eeprom failed, "
2609                             "Invalid Address: %X\n", i2c.dev_addr);
2610                         error = EINVAL;
2611                         goto err_i2c;
2612                 }
2613                 error = mlx5_query_eeprom(priv->mdev,
2614                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2615                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2616                     (uint32_t *)i2c.data, &size_read);
2617                 if (error) {
2618                         if_printf(ifp, "Query eeprom failed, eeprom "
2619                             "reading is not supported\n");
2620                         error = EINVAL;
2621                         goto err_i2c;
2622                 }
2623
2624                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2625                         error = mlx5_query_eeprom(priv->mdev,
2626                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2627                             (uint32_t)(i2c.offset + size_read),
2628                             (uint32_t)(i2c.len - size_read), module_num,
2629                             (uint32_t *)(i2c.data + size_read), &size_read);
2630                 }
2631                 if (error) {
2632                         if_printf(ifp, "Query eeprom failed, eeprom "
2633                             "reading is not supported\n");
2634                         error = EINVAL;
2635                         goto err_i2c;
2636                 }
2637
2638                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2639 err_i2c:
2640                 PRIV_UNLOCK(priv);
2641                 break;
2642
2643         default:
2644                 error = ether_ioctl(ifp, command, data);
2645                 break;
2646         }
2647         return (error);
2648 }
2649
2650 static int
2651 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2652 {
2653         /*
2654          * TODO: uncoment once FW really sets all these bits if
2655          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2656          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2657          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2658          * -ENOTSUPP;
2659          */
2660
2661         /* TODO: add more must-to-have features */
2662
2663         return (0);
2664 }
2665
2666 static void
2667 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2668     struct mlx5e_priv *priv,
2669     int num_comp_vectors)
2670 {
2671         /*
2672          * TODO: Consider link speed for setting "log_sq_size",
2673          * "log_rq_size" and "cq_moderation_xxx":
2674          */
2675         priv->params.log_sq_size =
2676             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2677         priv->params.log_rq_size =
2678             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2679         priv->params.rx_cq_moderation_usec =
2680             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2681             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2682             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2683         priv->params.rx_cq_moderation_mode =
2684             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2685         priv->params.rx_cq_moderation_pkts =
2686             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2687         priv->params.tx_cq_moderation_usec =
2688             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2689         priv->params.tx_cq_moderation_pkts =
2690             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2691         priv->params.min_rx_wqes =
2692             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2693         priv->params.rx_hash_log_tbl_sz =
2694             (order_base_2(num_comp_vectors) >
2695             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2696             order_base_2(num_comp_vectors) :
2697             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2698         priv->params.num_tc = 1;
2699         priv->params.default_vlan_prio = 0;
2700         priv->counter_set_id = -1;
2701
2702         /*
2703          * hw lro is currently defaulted to off. when it won't anymore we
2704          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2705          */
2706         priv->params.hw_lro_en = false;
2707         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2708
2709         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2710
2711         priv->mdev = mdev;
2712         priv->params.num_channels = num_comp_vectors;
2713         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2714         priv->queue_mapping_channel_mask =
2715             roundup_pow_of_two(num_comp_vectors) - 1;
2716         priv->num_tc = priv->params.num_tc;
2717         priv->default_vlan_prio = priv->params.default_vlan_prio;
2718
2719         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2720         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2721         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2722 }
2723
2724 static int
2725 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2726     struct mlx5_core_mr *mr)
2727 {
2728         struct ifnet *ifp = priv->ifp;
2729         struct mlx5_core_dev *mdev = priv->mdev;
2730         struct mlx5_create_mkey_mbox_in *in;
2731         int err;
2732
2733         in = mlx5_vzalloc(sizeof(*in));
2734         if (in == NULL) {
2735                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2736                 return (-ENOMEM);
2737         }
2738         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2739             MLX5_PERM_LOCAL_READ |
2740             MLX5_ACCESS_MODE_PA;
2741         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2742         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2743
2744         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2745             NULL);
2746         if (err)
2747                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2748                     __func__, err);
2749
2750         kvfree(in);
2751
2752         return (err);
2753 }
2754
2755 static const char *mlx5e_vport_stats_desc[] = {
2756         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2757 };
2758
2759 static const char *mlx5e_pport_stats_desc[] = {
2760         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2761 };
2762
2763 static void
2764 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2765 {
2766         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2767         sx_init(&priv->state_lock, "mlx5state");
2768         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2769         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2770 }
2771
2772 static void
2773 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2774 {
2775         mtx_destroy(&priv->async_events_mtx);
2776         sx_destroy(&priv->state_lock);
2777 }
2778
2779 static int
2780 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2781 {
2782         /*
2783          * %d.%d%.d the string format.
2784          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2785          * We need at most 5 chars to store that.
2786          * It also has: two "." and NULL at the end, which means we need 18
2787          * (5*3 + 3) chars at most.
2788          */
2789         char fw[18];
2790         struct mlx5e_priv *priv = arg1;
2791         int error;
2792
2793         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2794             fw_rev_sub(priv->mdev));
2795         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2796         return (error);
2797 }
2798
2799 static void
2800 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2801 {
2802         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2803             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2804             sysctl_firmware, "A", "HCA firmware version");
2805
2806         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2807             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2808             "Board ID");
2809 }
2810
2811 static void
2812 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2813 {
2814 #if (__FreeBSD_version < 1100000)
2815         char path[64];
2816
2817 #endif
2818         /* Only receiving pauseframes is enabled by default */
2819         priv->params.tx_pauseframe_control = 0;
2820         priv->params.rx_pauseframe_control = 1;
2821
2822 #if (__FreeBSD_version < 1100000)
2823         /* compute path for sysctl */
2824         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2825             device_get_unit(priv->mdev->pdev->dev.bsddev));
2826
2827         /* try to fetch tunable, if any */
2828         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2829
2830         /* compute path for sysctl */
2831         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2832             device_get_unit(priv->mdev->pdev->dev.bsddev));
2833
2834         /* try to fetch tunable, if any */
2835         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2836 #endif
2837
2838         /* register pausframe SYSCTLs */
2839         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2840             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2841             &priv->params.tx_pauseframe_control, 0,
2842             "Set to enable TX pause frames. Clear to disable.");
2843
2844         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2845             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2846             &priv->params.rx_pauseframe_control, 0,
2847             "Set to enable RX pause frames. Clear to disable.");
2848
2849         /* range check */
2850         priv->params.tx_pauseframe_control =
2851             priv->params.tx_pauseframe_control ? 1 : 0;
2852         priv->params.rx_pauseframe_control =
2853             priv->params.rx_pauseframe_control ? 1 : 0;
2854
2855         /* update firmware */
2856         mlx5_set_port_pause(priv->mdev, 1,
2857             priv->params.rx_pauseframe_control,
2858             priv->params.tx_pauseframe_control);
2859 }
2860
2861 static void *
2862 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2863 {
2864         static volatile int mlx5_en_unit;
2865         struct ifnet *ifp;
2866         struct mlx5e_priv *priv;
2867         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2868         struct sysctl_oid_list *child;
2869         int ncv = mdev->priv.eq_table.num_comp_vectors;
2870         char unit[16];
2871         int err;
2872         int i;
2873         u32 eth_proto_cap;
2874
2875         if (mlx5e_check_required_hca_cap(mdev)) {
2876                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2877                 return (NULL);
2878         }
2879         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2880         if (priv == NULL) {
2881                 mlx5_core_err(mdev, "malloc() failed\n");
2882                 return (NULL);
2883         }
2884         mlx5e_priv_mtx_init(priv);
2885
2886         ifp = priv->ifp = if_alloc(IFT_ETHER);
2887         if (ifp == NULL) {
2888                 mlx5_core_err(mdev, "if_alloc() failed\n");
2889                 goto err_free_priv;
2890         }
2891         ifp->if_softc = priv;
2892         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2893         ifp->if_mtu = ETHERMTU;
2894         ifp->if_init = mlx5e_open;
2895         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2896         ifp->if_ioctl = mlx5e_ioctl;
2897         ifp->if_transmit = mlx5e_xmit;
2898         ifp->if_qflush = if_qflush;
2899 #if (__FreeBSD_version >= 1100000)
2900         ifp->if_get_counter = mlx5e_get_counter;
2901 #endif
2902         ifp->if_snd.ifq_maxlen = ifqmaxlen;
2903         /*
2904          * Set driver features
2905          */
2906         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2907         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2908         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2909         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2910         ifp->if_capabilities |= IFCAP_LRO;
2911         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2912
2913         /* set TSO limits so that we don't have to drop TX packets */
2914         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2915         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2916         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2917
2918         ifp->if_capenable = ifp->if_capabilities;
2919         ifp->if_hwassist = 0;
2920         if (ifp->if_capenable & IFCAP_TSO)
2921                 ifp->if_hwassist |= CSUM_TSO;
2922         if (ifp->if_capenable & IFCAP_TXCSUM)
2923                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2924         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2925                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2926
2927         /* ifnet sysctl tree */
2928         sysctl_ctx_init(&priv->sysctl_ctx);
2929         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2930             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2931         if (priv->sysctl_ifnet == NULL) {
2932                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2933                 goto err_free_sysctl;
2934         }
2935         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2936         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2937             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2938         if (priv->sysctl_ifnet == NULL) {
2939                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2940                 goto err_free_sysctl;
2941         }
2942
2943         /* HW sysctl tree */
2944         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2945         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2946             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2947         if (priv->sysctl_hw == NULL) {
2948                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2949                 goto err_free_sysctl;
2950         }
2951         mlx5e_build_ifp_priv(mdev, priv, ncv);
2952         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2953         if (err) {
2954                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2955                     __func__, err);
2956                 goto err_free_sysctl;
2957         }
2958         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2959         if (err) {
2960                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2961                     __func__, err);
2962                 goto err_unmap_free_uar;
2963         }
2964         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2965         if (err) {
2966                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2967                     __func__, err);
2968                 goto err_dealloc_pd;
2969         }
2970         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2971         if (err) {
2972                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
2973                     __func__, err);
2974                 goto err_dealloc_transport_domain;
2975         }
2976         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
2977
2978         /* check if we should generate a random MAC address */
2979         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
2980             is_zero_ether_addr(dev_addr)) {
2981                 random_ether_addr(dev_addr);
2982                 if_printf(ifp, "Assigned random MAC address\n");
2983         }
2984
2985         /* set default MTU */
2986         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
2987
2988         /* Set desc */
2989         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
2990
2991         /* Set default media status */
2992         priv->media_status_last = IFM_AVALID;
2993         priv->media_active_last = IFM_ETHER | IFM_AUTO |
2994             IFM_ETH_RXPAUSE | IFM_FDX;
2995
2996         /* setup default pauseframes configuration */
2997         mlx5e_setup_pauseframes(priv);
2998
2999         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3000         if (err) {
3001                 eth_proto_cap = 0;
3002                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3003                     __func__, err);
3004         }
3005
3006         /* Setup supported medias */
3007         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3008             mlx5e_media_change, mlx5e_media_status);
3009
3010         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3011                 if (mlx5e_mode_table[i].baudrate == 0)
3012                         continue;
3013                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3014                         ifmedia_add(&priv->media,
3015                             mlx5e_mode_table[i].subtype |
3016                             IFM_ETHER, 0, NULL);
3017                         ifmedia_add(&priv->media,
3018                             mlx5e_mode_table[i].subtype |
3019                             IFM_ETHER | IFM_FDX |
3020                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3021                 }
3022         }
3023
3024         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3025         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3026             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3027
3028         /* Set autoselect by default */
3029         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3030             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3031         ether_ifattach(ifp, dev_addr);
3032
3033         /* Register for VLAN events */
3034         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3035             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3036         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3037             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3038
3039         /* Link is down by default */
3040         if_link_state_change(ifp, LINK_STATE_DOWN);
3041
3042         mlx5e_enable_async_events(priv);
3043
3044         mlx5e_add_hw_stats(priv);
3045
3046         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3047             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3048             priv->stats.vport.arg);
3049
3050         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3051             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3052             priv->stats.pport.arg);
3053
3054         mlx5e_create_ethtool(priv);
3055
3056         mtx_lock(&priv->async_events_mtx);
3057         mlx5e_update_stats(priv);
3058         mtx_unlock(&priv->async_events_mtx);
3059
3060         return (priv);
3061
3062 err_dealloc_transport_domain:
3063         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3064
3065 err_dealloc_pd:
3066         mlx5_core_dealloc_pd(mdev, priv->pdn);
3067
3068 err_unmap_free_uar:
3069         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3070
3071 err_free_sysctl:
3072         sysctl_ctx_free(&priv->sysctl_ctx);
3073
3074         if_free(ifp);
3075
3076 err_free_priv:
3077         mlx5e_priv_mtx_destroy(priv);
3078         free(priv, M_MLX5EN);
3079         return (NULL);
3080 }
3081
3082 static void
3083 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3084 {
3085         struct mlx5e_priv *priv = vpriv;
3086         struct ifnet *ifp = priv->ifp;
3087
3088         /* don't allow more IOCTLs */
3089         priv->gone = 1;
3090
3091         /*
3092          * Clear the device description to avoid use after free,
3093          * because the bsddev is not destroyed when this module is
3094          * unloaded:
3095          */
3096         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3097
3098         /* XXX wait a bit to allow IOCTL handlers to complete */
3099         pause("W", hz);
3100
3101         /* stop watchdog timer */
3102         callout_drain(&priv->watchdog);
3103
3104         if (priv->vlan_attach != NULL)
3105                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3106         if (priv->vlan_detach != NULL)
3107                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3108
3109         /* make sure device gets closed */
3110         PRIV_LOCK(priv);
3111         mlx5e_close_locked(ifp);
3112         PRIV_UNLOCK(priv);
3113
3114         /* unregister device */
3115         ifmedia_removeall(&priv->media);
3116         ether_ifdetach(ifp);
3117         if_free(ifp);
3118
3119         /* destroy all remaining sysctl nodes */
3120         if (priv->sysctl_debug)
3121                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3122         sysctl_ctx_free(&priv->stats.vport.ctx);
3123         sysctl_ctx_free(&priv->stats.pport.ctx);
3124         sysctl_ctx_free(&priv->sysctl_ctx);
3125
3126         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3127         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3128         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3129         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3130         mlx5e_disable_async_events(priv);
3131         flush_scheduled_work();
3132         mlx5e_priv_mtx_destroy(priv);
3133         free(priv, M_MLX5EN);
3134 }
3135
3136 static void *
3137 mlx5e_get_ifp(void *vpriv)
3138 {
3139         struct mlx5e_priv *priv = vpriv;
3140
3141         return (priv->ifp);
3142 }
3143
3144 static struct mlx5_interface mlx5e_interface = {
3145         .add = mlx5e_create_ifp,
3146         .remove = mlx5e_destroy_ifp,
3147         .event = mlx5e_async_event,
3148         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3149         .get_dev = mlx5e_get_ifp,
3150 };
3151
3152 void
3153 mlx5e_init(void)
3154 {
3155         mlx5_register_interface(&mlx5e_interface);
3156 }
3157
3158 void
3159 mlx5e_cleanup(void)
3160 {
3161         mlx5_unregister_interface(&mlx5e_interface);
3162 }
3163
3164 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3165 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3166
3167 #if (__FreeBSD_version >= 1100000)
3168 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3169 #endif
3170 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3171 MODULE_VERSION(mlx5en, 1);