sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.2.1"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  38
  39 struct mlx5e_channel_param {
  40         struct mlx5e_rq_param rq;
  41         struct mlx5e_sq_param sq;
  42         struct mlx5e_cq_param rx_cq;
  43         struct mlx5e_cq_param tx_cq;
  44 };
  45
  46 static const struct {
  47         u32     subtype;
  48         u64     baudrate;
  49 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  50
  51         [MLX5E_1000BASE_CX_SGMII] = {
  52                 .subtype = IFM_1000_CX_SGMII,
  53                 .baudrate = IF_Mbps(1000ULL),
  54         },
  55         [MLX5E_1000BASE_KX] = {
  56                 .subtype = IFM_1000_KX,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_10GBASE_CX4] = {
  60                 .subtype = IFM_10G_CX4,
  61                 .baudrate = IF_Gbps(10ULL),
  62         },
  63         [MLX5E_10GBASE_KX4] = {
  64                 .subtype = IFM_10G_KX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KR] = {
  68                 .subtype = IFM_10G_KR,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_20GBASE_KR2] = {
  72                 .subtype = IFM_20G_KR2,
  73                 .baudrate = IF_Gbps(20ULL),
  74         },
  75         [MLX5E_40GBASE_CR4] = {
  76                 .subtype = IFM_40G_CR4,
  77                 .baudrate = IF_Gbps(40ULL),
  78         },
  79         [MLX5E_40GBASE_KR4] = {
  80                 .subtype = IFM_40G_KR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_56GBASE_R4] = {
  84                 .subtype = IFM_56G_R4,
  85                 .baudrate = IF_Gbps(56ULL),
  86         },
  87         [MLX5E_10GBASE_CR] = {
  88                 .subtype = IFM_10G_CR1,
  89                 .baudrate = IF_Gbps(10ULL),
  90         },
  91         [MLX5E_10GBASE_SR] = {
  92                 .subtype = IFM_10G_SR,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_LR] = {
  96                 .subtype = IFM_10G_LR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_40GBASE_SR4] = {
 100                 .subtype = IFM_40G_SR4,
 101                 .baudrate = IF_Gbps(40ULL),
 102         },
 103         [MLX5E_40GBASE_LR4] = {
 104                 .subtype = IFM_40G_LR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_100GBASE_CR4] = {
 108                 .subtype = IFM_100G_CR4,
 109                 .baudrate = IF_Gbps(100ULL),
 110         },
 111         [MLX5E_100GBASE_SR4] = {
 112                 .subtype = IFM_100G_SR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_KR4] = {
 116                 .subtype = IFM_100G_KR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_LR4] = {
 120                 .subtype = IFM_100G_LR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100BASE_TX] = {
 124                 .subtype = IFM_100_TX,
 125                 .baudrate = IF_Mbps(100ULL),
 126         },
 127         [MLX5E_100BASE_T] = {
 128                 .subtype = IFM_100_T,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_10GBASE_T] = {
 132                 .subtype = IFM_10G_T,
 133                 .baudrate = IF_Gbps(10ULL),
 134         },
 135         [MLX5E_25GBASE_CR] = {
 136                 .subtype = IFM_25G_CR,
 137                 .baudrate = IF_Gbps(25ULL),
 138         },
 139         [MLX5E_25GBASE_KR] = {
 140                 .subtype = IFM_25G_KR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_SR] = {
 144                 .subtype = IFM_25G_SR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_50GBASE_CR2] = {
 148                 .subtype = IFM_50G_CR2,
 149                 .baudrate = IF_Gbps(50ULL),
 150         },
 151         [MLX5E_50GBASE_KR2] = {
 152                 .subtype = IFM_50G_KR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155 };
 156
 157 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 158
 159 static void
 160 mlx5e_update_carrier(struct mlx5e_priv *priv)
 161 {
 162         struct mlx5_core_dev *mdev = priv->mdev;
 163         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 164         u32 eth_proto_oper;
 165         int error;
 166         u8 port_state;
 167         u8 i;
 168
 169         port_state = mlx5_query_vport_state(mdev,
 170             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 171
 172         if (port_state == VPORT_STATE_UP) {
 173                 priv->media_status_last |= IFM_ACTIVE;
 174         } else {
 175                 priv->media_status_last &= ~IFM_ACTIVE;
 176                 priv->media_active_last = IFM_ETHER;
 177                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 178                 return;
 179         }
 180
 181         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 182         if (error) {
 183                 priv->media_active_last = IFM_ETHER;
 184                 priv->ifp->if_baudrate = 1;
 185                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 186                     __func__, error);
 187                 return;
 188         }
 189         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 190
 191         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 192                 if (mlx5e_mode_table[i].baudrate == 0)
 193                         continue;
 194                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 195                         priv->ifp->if_baudrate =
 196                             mlx5e_mode_table[i].baudrate;
 197                         priv->media_active_last =
 198                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 199                 }
 200         }
 201         if_link_state_change(priv->ifp, LINK_STATE_UP);
 202 }
 203
 204 static void
 205 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 206 {
 207         struct mlx5e_priv *priv = dev->if_softc;
 208
 209         ifmr->ifm_status = priv->media_status_last;
 210         ifmr->ifm_active = priv->media_active_last |
 211             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 212             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 213
 214 }
 215
 216 static u32
 217 mlx5e_find_link_mode(u32 subtype)
 218 {
 219         u32 i;
 220         u32 link_mode = 0;
 221
 222         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 223                 if (mlx5e_mode_table[i].baudrate == 0)
 224                         continue;
 225                 if (mlx5e_mode_table[i].subtype == subtype)
 226                         link_mode |= MLX5E_PROT_MASK(i);
 227         }
 228
 229         return (link_mode);
 230 }
 231
 232 static int
 233 mlx5e_media_change(struct ifnet *dev)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236         struct mlx5_core_dev *mdev = priv->mdev;
 237         u32 eth_proto_cap;
 238         u32 link_mode;
 239         int was_opened;
 240         int locked;
 241         int error;
 242
 243         locked = PRIV_LOCKED(priv);
 244         if (!locked)
 245                 PRIV_LOCK(priv);
 246
 247         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 248                 error = EINVAL;
 249                 goto done;
 250         }
 251         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 252
 253         /* query supported capabilities */
 254         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 255         if (error != 0) {
 256                 if_printf(dev, "Query port media capability failed\n");
 257                 goto done;
 258         }
 259         /* check for autoselect */
 260         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 261                 link_mode = eth_proto_cap;
 262                 if (link_mode == 0) {
 263                         if_printf(dev, "Port media capability is zero\n");
 264                         error = EINVAL;
 265                         goto done;
 266                 }
 267         } else {
 268                 link_mode = link_mode & eth_proto_cap;
 269                 if (link_mode == 0) {
 270                         if_printf(dev, "Not supported link mode requested\n");
 271                         error = EINVAL;
 272                         goto done;
 273                 }
 274         }
 275         /* update pauseframe control bits */
 276         priv->params.rx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 278         priv->params.tx_pauseframe_control =
 279             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 280
 281         /* check if device is opened */
 282         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 283
 284         /* reconfigure the hardware */
 285         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 286         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 287         mlx5_set_port_pause(mdev, 1,
 288             priv->params.rx_pauseframe_control,
 289             priv->params.tx_pauseframe_control);
 290         if (was_opened)
 291                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 292
 293 done:
 294         if (!locked)
 295                 PRIV_UNLOCK(priv);
 296         return (error);
 297 }
 298
 299 static void
 300 mlx5e_update_carrier_work(struct work_struct *work)
 301 {
 302         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 303             update_carrier_work);
 304
 305         PRIV_LOCK(priv);
 306         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 307                 mlx5e_update_carrier(priv);
 308         PRIV_UNLOCK(priv);
 309 }
 310
 311 /*
 312  * This function reads the physical port counters from the firmware
 313  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 314  * macros. The output is converted from big-endian 64-bit values into
 315  * host endian ones and stored in the "priv->stats.pport" structure.
 316  */
 317 static void
 318 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 319 {
 320         struct mlx5_core_dev *mdev = priv->mdev;
 321         struct mlx5e_pport_stats *s = &priv->stats.pport;
 322         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 323         u32 *in;
 324         u32 *out;
 325         const u64 *ptr;
 326         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 327         unsigned x;
 328         unsigned y;
 329
 330         /* allocate firmware request structures */
 331         in = mlx5_vzalloc(sz);
 332         out = mlx5_vzalloc(sz);
 333         if (in == NULL || out == NULL)
 334                 goto free_out;
 335
 336         /*
 337          * Get pointer to the 64-bit counter set which is located at a
 338          * fixed offset in the output firmware request structure:
 339          */
 340         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 341
 342         MLX5_SET(ppcnt_reg, in, local_port, 1);
 343
 344         /* read IEEE802_3 counter group using predefined counter layout */
 345         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 346         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 347         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 348                 s->arg[y] = be64toh(ptr[x]);
 349
 350         /* read RFC2819 counter group using predefined counter layout */
 351         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 352         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 353         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 354                 s->arg[y] = be64toh(ptr[x]);
 355         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 356             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 357                 s_debug->arg[y] = be64toh(ptr[x]);
 358
 359         /* read RFC2863 counter group using predefined counter layout */
 360         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 361         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 362         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 363                 s_debug->arg[y] = be64toh(ptr[x]);
 364
 365         /* read physical layer stats counter group using predefined counter layout */
 366         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 367         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 368         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 369                 s_debug->arg[y] = be64toh(ptr[x]);
 370 free_out:
 371         /* free firmware request structures */
 372         kvfree(in);
 373         kvfree(out);
 374 }
 375
 376 /*
 377  * This function is called regularly to collect all statistics
 378  * counters from the firmware. The values can be viewed through the
 379  * sysctl interface. Execution is serialized using the priv's global
 380  * configuration lock.
 381  */
 382 static void
 383 mlx5e_update_stats_work(struct work_struct *work)
 384 {
 385         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 386             update_stats_work);
 387         struct mlx5_core_dev *mdev = priv->mdev;
 388         struct mlx5e_vport_stats *s = &priv->stats.vport;
 389         struct mlx5e_rq_stats *rq_stats;
 390         struct mlx5e_sq_stats *sq_stats;
 391         struct buf_ring *sq_br;
 392 #if (__FreeBSD_version < 1100000)
 393         struct ifnet *ifp = priv->ifp;
 394 #endif
 395
 396         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 397         u32 *out;
 398         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 399         u64 tso_packets = 0;
 400         u64 tso_bytes = 0;
 401         u64 tx_queue_dropped = 0;
 402         u64 tx_defragged = 0;
 403         u64 tx_offload_none = 0;
 404         u64 lro_packets = 0;
 405         u64 lro_bytes = 0;
 406         u64 sw_lro_queued = 0;
 407         u64 sw_lro_flushed = 0;
 408         u64 rx_csum_none = 0;
 409         u64 rx_wqe_err = 0;
 410         u32 rx_out_of_buffer = 0;
 411         int i;
 412         int j;
 413
 414         PRIV_LOCK(priv);
 415         out = mlx5_vzalloc(outlen);
 416         if (out == NULL)
 417                 goto free_out;
 418         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 419                 goto free_out;
 420
 421         /* Collect firts the SW counters and then HW for consistency */
 422         for (i = 0; i < priv->params.num_channels; i++) {
 423                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 424
 425                 rq_stats = &priv->channel[i]->rq.stats;
 426
 427                 /* collect stats from LRO */
 428                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 429                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 430                 sw_lro_queued += rq_stats->sw_lro_queued;
 431                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 432                 lro_packets += rq_stats->lro_packets;
 433                 lro_bytes += rq_stats->lro_bytes;
 434                 rx_csum_none += rq_stats->csum_none;
 435                 rx_wqe_err += rq_stats->wqe_err;
 436
 437                 for (j = 0; j < priv->num_tc; j++) {
 438                         sq_stats = &priv->channel[i]->sq[j].stats;
 439                         sq_br = priv->channel[i]->sq[j].br;
 440
 441                         tso_packets += sq_stats->tso_packets;
 442                         tso_bytes += sq_stats->tso_bytes;
 443                         tx_queue_dropped += sq_stats->dropped;
 444                         if (sq_br != NULL)
 445                                 tx_queue_dropped += sq_br->br_drops;
 446                         tx_defragged += sq_stats->defragged;
 447                         tx_offload_none += sq_stats->csum_offload_none;
 448                 }
 449         }
 450
 451         /* update counters */
 452         s->tso_packets = tso_packets;
 453         s->tso_bytes = tso_bytes;
 454         s->tx_queue_dropped = tx_queue_dropped;
 455         s->tx_defragged = tx_defragged;
 456         s->lro_packets = lro_packets;
 457         s->lro_bytes = lro_bytes;
 458         s->sw_lro_queued = sw_lro_queued;
 459         s->sw_lro_flushed = sw_lro_flushed;
 460         s->rx_csum_none = rx_csum_none;
 461         s->rx_wqe_err = rx_wqe_err;
 462
 463         /* HW counters */
 464         memset(in, 0, sizeof(in));
 465
 466         MLX5_SET(query_vport_counter_in, in, opcode,
 467             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 468         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 469         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 470
 471         memset(out, 0, outlen);
 472
 473         /* get number of out-of-buffer drops first */
 474         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 475             &rx_out_of_buffer))
 476                 goto free_out;
 477
 478         /* accumulate difference into a 64-bit counter */
 479         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 480         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 481
 482         /* get port statistics */
 483         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 484                 goto free_out;
 485
 486 #define MLX5_GET_CTR(out, x) \
 487         MLX5_GET64(query_vport_counter_out, out, x)
 488
 489         s->rx_error_packets =
 490             MLX5_GET_CTR(out, received_errors.packets);
 491         s->rx_error_bytes =
 492             MLX5_GET_CTR(out, received_errors.octets);
 493         s->tx_error_packets =
 494             MLX5_GET_CTR(out, transmit_errors.packets);
 495         s->tx_error_bytes =
 496             MLX5_GET_CTR(out, transmit_errors.octets);
 497
 498         s->rx_unicast_packets =
 499             MLX5_GET_CTR(out, received_eth_unicast.packets);
 500         s->rx_unicast_bytes =
 501             MLX5_GET_CTR(out, received_eth_unicast.octets);
 502         s->tx_unicast_packets =
 503             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 504         s->tx_unicast_bytes =
 505             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 506
 507         s->rx_multicast_packets =
 508             MLX5_GET_CTR(out, received_eth_multicast.packets);
 509         s->rx_multicast_bytes =
 510             MLX5_GET_CTR(out, received_eth_multicast.octets);
 511         s->tx_multicast_packets =
 512             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 513         s->tx_multicast_bytes =
 514             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 515
 516         s->rx_broadcast_packets =
 517             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 518         s->rx_broadcast_bytes =
 519             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 520         s->tx_broadcast_packets =
 521             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 522         s->tx_broadcast_bytes =
 523             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 524
 525         s->rx_packets =
 526             s->rx_unicast_packets +
 527             s->rx_multicast_packets +
 528             s->rx_broadcast_packets -
 529             s->rx_out_of_buffer;
 530         s->rx_bytes =
 531             s->rx_unicast_bytes +
 532             s->rx_multicast_bytes +
 533             s->rx_broadcast_bytes;
 534         s->tx_packets =
 535             s->tx_unicast_packets +
 536             s->tx_multicast_packets +
 537             s->tx_broadcast_packets;
 538         s->tx_bytes =
 539             s->tx_unicast_bytes +
 540             s->tx_multicast_bytes +
 541             s->tx_broadcast_bytes;
 542
 543         /* Update calculated offload counters */
 544         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 545         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 546
 547         /* Get physical port counters */
 548         mlx5e_update_pport_counters(priv);
 549
 550 #if (__FreeBSD_version < 1100000)
 551         /* no get_counters interface in fbsd 10 */
 552         ifp->if_ipackets = s->rx_packets;
 553         ifp->if_ierrors = s->rx_error_packets +
 554             priv->stats.pport.alignment_err +
 555             priv->stats.pport.check_seq_err +
 556             priv->stats.pport.crc_align_errors +
 557             priv->stats.pport.in_range_len_errors +
 558             priv->stats.pport.jabbers +
 559             priv->stats.pport.out_of_range_len +
 560             priv->stats.pport.oversize_pkts +
 561             priv->stats.pport.symbol_err +
 562             priv->stats.pport.too_long_errors +
 563             priv->stats.pport.undersize_pkts +
 564             priv->stats.pport.unsupported_op_rx;
 565         ifp->if_iqdrops = s->rx_out_of_buffer +
 566             priv->stats.pport.drop_events;
 567         ifp->if_opackets = s->tx_packets;
 568         ifp->if_oerrors = s->tx_error_packets;
 569         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 570         ifp->if_ibytes = s->rx_bytes;
 571         ifp->if_obytes = s->tx_bytes;
 572         ifp->if_collisions =
 573             priv->stats.pport.collisions;
 574 #endif
 575
 576 free_out:
 577         kvfree(out);
 578
 579         /* Update diagnostics, if any */
 580         if (priv->params_ethtool.diag_pci_enable ||
 581             priv->params_ethtool.diag_general_enable) {
 582                 int error = mlx5_core_get_diagnostics_full(mdev,
 583                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 584                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 585                 if (error != 0)
 586                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 587         }
 588         PRIV_UNLOCK(priv);
 589 }
 590
 591 static void
 592 mlx5e_update_stats(void *arg)
 593 {
 594         struct mlx5e_priv *priv = arg;
 595
 596         schedule_work(&priv->update_stats_work);
 597
 598         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 599 }
 600
 601 static void
 602 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 603     enum mlx5_dev_event event)
 604 {
 605         switch (event) {
 606         case MLX5_DEV_EVENT_PORT_UP:
 607         case MLX5_DEV_EVENT_PORT_DOWN:
 608                 schedule_work(&priv->update_carrier_work);
 609                 break;
 610
 611         default:
 612                 break;
 613         }
 614 }
 615
 616 static void
 617 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 618     enum mlx5_dev_event event, unsigned long param)
 619 {
 620         struct mlx5e_priv *priv = vpriv;
 621
 622         mtx_lock(&priv->async_events_mtx);
 623         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 624                 mlx5e_async_event_sub(priv, event);
 625         mtx_unlock(&priv->async_events_mtx);
 626 }
 627
 628 static void
 629 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 630 {
 631         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 632 }
 633
 634 static void
 635 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 636 {
 637         mtx_lock(&priv->async_events_mtx);
 638         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 639         mtx_unlock(&priv->async_events_mtx);
 640 }
 641
 642 static const char *mlx5e_rq_stats_desc[] = {
 643         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 644 };
 645
 646 static int
 647 mlx5e_create_rq(struct mlx5e_channel *c,
 648     struct mlx5e_rq_param *param,
 649     struct mlx5e_rq *rq)
 650 {
 651         struct mlx5e_priv *priv = c->priv;
 652         struct mlx5_core_dev *mdev = priv->mdev;
 653         char buffer[16];
 654         void *rqc = param->rqc;
 655         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 656         int wq_sz;
 657         int err;
 658         int i;
 659         u32 nsegs, wqe_sz;
 660
 661         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 662         if (err != 0)
 663                 goto done;
 664
 665         /* Create DMA descriptor TAG */
 666         if ((err = -bus_dma_tag_create(
 667             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 668             1,                          /* any alignment */
 669             0,                          /* no boundary */
 670             BUS_SPACE_MAXADDR,          /* lowaddr */
 671             BUS_SPACE_MAXADDR,          /* highaddr */
 672             NULL, NULL,                 /* filter, filterarg */
 673             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 674             nsegs,                      /* nsegments */
 675             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 676             0,                          /* flags */
 677             NULL, NULL,                 /* lockfunc, lockfuncarg */
 678             &rq->dma_tag)))
 679                 goto done;
 680
 681         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 682             &rq->wq_ctrl);
 683         if (err)
 684                 goto err_free_dma_tag;
 685
 686         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 687
 688         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 689         if (err != 0)
 690                 goto err_rq_wq_destroy;
 691
 692         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 693         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 694         for (i = 0; i != wq_sz; i++) {
 695                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 696 #if (MLX5E_MAX_RX_SEGS == 1)
 697                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 698 #else
 699                 int j;
 700 #endif
 701
 702                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 703                 if (err != 0) {
 704                         while (i--)
 705                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 706                         goto err_rq_mbuf_free;
 707                 }
 708
 709                 /* set value for constant fields */
 710 #if (MLX5E_MAX_RX_SEGS == 1)
 711                 wqe->data[0].lkey = c->mkey_be;
 712                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 713 #else
 714                 for (j = 0; j < rq->nsegs; j++)
 715                         wqe->data[j].lkey = c->mkey_be;
 716 #endif
 717         }
 718
 719         rq->ifp = c->ifp;
 720         rq->channel = c;
 721         rq->ix = c->ix;
 722
 723         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 724         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 725             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 726             rq->stats.arg);
 727
 728 #ifdef HAVE_TURBO_LRO
 729         if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
 730                 rq->lro.mbuf = NULL;
 731 #else
 732         if (tcp_lro_init(&rq->lro))
 733                 rq->lro.lro_cnt = 0;
 734         else
 735                 rq->lro.ifp = c->ifp;
 736 #endif
 737         return (0);
 738
 739 err_rq_mbuf_free:
 740         free(rq->mbuf, M_MLX5EN);
 741 err_rq_wq_destroy:
 742         mlx5_wq_destroy(&rq->wq_ctrl);
 743 err_free_dma_tag:
 744         bus_dma_tag_destroy(rq->dma_tag);
 745 done:
 746         return (err);
 747 }
 748
 749 static void
 750 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 751 {
 752         int wq_sz;
 753         int i;
 754
 755         /* destroy all sysctl nodes */
 756         sysctl_ctx_free(&rq->stats.ctx);
 757
 758         /* free leftover LRO packets, if any */
 759 #ifdef HAVE_TURBO_LRO
 760         tcp_tlro_free(&rq->lro);
 761 #else
 762         tcp_lro_free(&rq->lro);
 763 #endif
 764         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 765         for (i = 0; i != wq_sz; i++) {
 766                 if (rq->mbuf[i].mbuf != NULL) {
 767                         bus_dmamap_unload(rq->dma_tag,
 768                             rq->mbuf[i].dma_map);
 769                         m_freem(rq->mbuf[i].mbuf);
 770                 }
 771                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 772         }
 773         free(rq->mbuf, M_MLX5EN);
 774         mlx5_wq_destroy(&rq->wq_ctrl);
 775 }
 776
 777 static int
 778 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 779 {
 780         struct mlx5e_channel *c = rq->channel;
 781         struct mlx5e_priv *priv = c->priv;
 782         struct mlx5_core_dev *mdev = priv->mdev;
 783
 784         void *in;
 785         void *rqc;
 786         void *wq;
 787         int inlen;
 788         int err;
 789
 790         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 791             sizeof(u64) * rq->wq_ctrl.buf.npages;
 792         in = mlx5_vzalloc(inlen);
 793         if (in == NULL)
 794                 return (-ENOMEM);
 795
 796         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 797         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 798
 799         memcpy(rqc, param->rqc, sizeof(param->rqc));
 800
 801         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 802         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 803         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 804         if (priv->counter_set_id >= 0)
 805                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 806         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 807             PAGE_SHIFT);
 808         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 809
 810         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 811             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 812
 813         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 814
 815         kvfree(in);
 816
 817         return (err);
 818 }
 819
 820 static int
 821 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 822 {
 823         struct mlx5e_channel *c = rq->channel;
 824         struct mlx5e_priv *priv = c->priv;
 825         struct mlx5_core_dev *mdev = priv->mdev;
 826
 827         void *in;
 828         void *rqc;
 829         int inlen;
 830         int err;
 831
 832         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 833         in = mlx5_vzalloc(inlen);
 834         if (in == NULL)
 835                 return (-ENOMEM);
 836
 837         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 838
 839         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 840         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 841         MLX5_SET(rqc, rqc, state, next_state);
 842
 843         err = mlx5_core_modify_rq(mdev, in, inlen);
 844
 845         kvfree(in);
 846
 847         return (err);
 848 }
 849
 850 static void
 851 mlx5e_disable_rq(struct mlx5e_rq *rq)
 852 {
 853         struct mlx5e_channel *c = rq->channel;
 854         struct mlx5e_priv *priv = c->priv;
 855         struct mlx5_core_dev *mdev = priv->mdev;
 856
 857         mlx5_core_destroy_rq(mdev, rq->rqn);
 858 }
 859
 860 static int
 861 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 862 {
 863         struct mlx5e_channel *c = rq->channel;
 864         struct mlx5e_priv *priv = c->priv;
 865         struct mlx5_wq_ll *wq = &rq->wq;
 866         int i;
 867
 868         for (i = 0; i < 1000; i++) {
 869                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 870                         return (0);
 871
 872                 msleep(4);
 873         }
 874         return (-ETIMEDOUT);
 875 }
 876
 877 static int
 878 mlx5e_open_rq(struct mlx5e_channel *c,
 879     struct mlx5e_rq_param *param,
 880     struct mlx5e_rq *rq)
 881 {
 882         int err;
 883
 884         err = mlx5e_create_rq(c, param, rq);
 885         if (err)
 886                 return (err);
 887
 888         err = mlx5e_enable_rq(rq, param);
 889         if (err)
 890                 goto err_destroy_rq;
 891
 892         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 893         if (err)
 894                 goto err_disable_rq;
 895
 896         c->rq.enabled = 1;
 897
 898         return (0);
 899
 900 err_disable_rq:
 901         mlx5e_disable_rq(rq);
 902 err_destroy_rq:
 903         mlx5e_destroy_rq(rq);
 904
 905         return (err);
 906 }
 907
 908 static void
 909 mlx5e_close_rq(struct mlx5e_rq *rq)
 910 {
 911         mtx_lock(&rq->mtx);
 912         rq->enabled = 0;
 913         callout_stop(&rq->watchdog);
 914         mtx_unlock(&rq->mtx);
 915
 916         callout_drain(&rq->watchdog);
 917
 918         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 919 }
 920
 921 static void
 922 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 923 {
 924         struct mlx5_core_dev *mdev = rq->channel->priv->mdev;
 925
 926         /* wait till RQ is empty */
 927         while (!mlx5_wq_ll_is_empty(&rq->wq) &&
 928                 (mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)) {
 929                 msleep(4);
 930                 rq->cq.mcq.comp(&rq->cq.mcq);
 931         }
 932
 933         mlx5e_disable_rq(rq);
 934         mlx5e_destroy_rq(rq);
 935 }
 936
 937 void
 938 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 939 {
 940         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 941         int x;
 942
 943         for (x = 0; x != wq_sz; x++)
 944                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 945         free(sq->mbuf, M_MLX5EN);
 946 }
 947
 948 int
 949 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 950 {
 951         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 952         int err;
 953         int x;
 954
 955         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 956
 957         /* Create DMA descriptor MAPs */
 958         for (x = 0; x != wq_sz; x++) {
 959                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 960                 if (err != 0) {
 961                         while (x--)
 962                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 963                         free(sq->mbuf, M_MLX5EN);
 964                         return (err);
 965                 }
 966         }
 967         return (0);
 968 }
 969
 970 static const char *mlx5e_sq_stats_desc[] = {
 971         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 972 };
 973
 974 static int
 975 mlx5e_create_sq(struct mlx5e_channel *c,
 976     int tc,
 977     struct mlx5e_sq_param *param,
 978     struct mlx5e_sq *sq)
 979 {
 980         struct mlx5e_priv *priv = c->priv;
 981         struct mlx5_core_dev *mdev = priv->mdev;
 982         char buffer[16];
 983
 984         void *sqc = param->sqc;
 985         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 986 #ifdef RSS
 987         cpuset_t cpu_mask;
 988         int cpu_id;
 989 #endif
 990         int err;
 991
 992         /* Create DMA descriptor TAG */
 993         if ((err = -bus_dma_tag_create(
 994             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 995             1,                          /* any alignment */
 996             0,                          /* no boundary */
 997             BUS_SPACE_MAXADDR,          /* lowaddr */
 998             BUS_SPACE_MAXADDR,          /* highaddr */
 999             NULL, NULL,                 /* filter, filterarg */
1000             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1001             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1002             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1003             0,                          /* flags */
1004             NULL, NULL,                 /* lockfunc, lockfuncarg */
1005             &sq->dma_tag)))
1006                 goto done;
1007
1008         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1009         if (err)
1010                 goto err_free_dma_tag;
1011
1012         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1013             &sq->wq_ctrl);
1014         if (err)
1015                 goto err_unmap_free_uar;
1016
1017         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1018         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1019
1020         err = mlx5e_alloc_sq_db(sq);
1021         if (err)
1022                 goto err_sq_wq_destroy;
1023
1024         sq->mkey_be = c->mkey_be;
1025         sq->ifp = priv->ifp;
1026         sq->priv = priv;
1027         sq->tc = tc;
1028         sq->max_inline = priv->params.tx_max_inline;
1029         sq->min_inline_mode = priv->params.tx_min_inline_mode;
1030         sq->vlan_inline_cap = MLX5_CAP_ETH(mdev, wqe_vlan_insert);
1031
1032         /* check if we should allocate a second packet buffer */
1033         if (priv->params_ethtool.tx_bufring_disable == 0) {
1034                 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1035                     M_WAITOK, &sq->lock);
1036                 if (sq->br == NULL) {
1037                         if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1038                             __func__);
1039                         err = -ENOMEM;
1040                         goto err_free_sq_db;
1041                 }
1042
1043                 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1044                     taskqueue_thread_enqueue, &sq->sq_tq);
1045                 if (sq->sq_tq == NULL) {
1046                         if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1047                             __func__);
1048                         err = -ENOMEM;
1049                         goto err_free_drbr;
1050                 }
1051
1052                 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1053 #ifdef RSS
1054                 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1055                 CPU_SETOF(cpu_id, &cpu_mask);
1056                 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1057                     "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1058 #else
1059                 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1060                     "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1061 #endif
1062         }
1063         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1064         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1065             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1066             sq->stats.arg);
1067
1068         return (0);
1069
1070 err_free_drbr:
1071         buf_ring_free(sq->br, M_MLX5EN);
1072 err_free_sq_db:
1073         mlx5e_free_sq_db(sq);
1074 err_sq_wq_destroy:
1075         mlx5_wq_destroy(&sq->wq_ctrl);
1076
1077 err_unmap_free_uar:
1078         mlx5_unmap_free_uar(mdev, &sq->uar);
1079
1080 err_free_dma_tag:
1081         bus_dma_tag_destroy(sq->dma_tag);
1082 done:
1083         return (err);
1084 }
1085
1086 static void
1087 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1088 {
1089         /* destroy all sysctl nodes */
1090         sysctl_ctx_free(&sq->stats.ctx);
1091
1092         mlx5e_free_sq_db(sq);
1093         mlx5_wq_destroy(&sq->wq_ctrl);
1094         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1095         if (sq->sq_tq != NULL) {
1096                 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1097                 taskqueue_free(sq->sq_tq);
1098         }
1099         if (sq->br != NULL)
1100                 buf_ring_free(sq->br, M_MLX5EN);
1101 }
1102
1103 int
1104 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1105     int tis_num)
1106 {
1107         void *in;
1108         void *sqc;
1109         void *wq;
1110         int inlen;
1111         int err;
1112
1113         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1114             sizeof(u64) * sq->wq_ctrl.buf.npages;
1115         in = mlx5_vzalloc(inlen);
1116         if (in == NULL)
1117                 return (-ENOMEM);
1118
1119         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1120         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1121
1122         memcpy(sqc, param->sqc, sizeof(param->sqc));
1123
1124         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1125         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1126         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1127         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1128         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1129
1130         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1131         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1132         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1133             PAGE_SHIFT);
1134         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1135
1136         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1137             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1138
1139         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1140
1141         kvfree(in);
1142
1143         return (err);
1144 }
1145
1146 int
1147 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1148 {
1149         void *in;
1150         void *sqc;
1151         int inlen;
1152         int err;
1153
1154         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1155         in = mlx5_vzalloc(inlen);
1156         if (in == NULL)
1157                 return (-ENOMEM);
1158
1159         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1160
1161         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1162         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1163         MLX5_SET(sqc, sqc, state, next_state);
1164
1165         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1166
1167         kvfree(in);
1168
1169         return (err);
1170 }
1171
1172 void
1173 mlx5e_disable_sq(struct mlx5e_sq *sq)
1174 {
1175
1176         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1177 }
1178
1179 static int
1180 mlx5e_open_sq(struct mlx5e_channel *c,
1181     int tc,
1182     struct mlx5e_sq_param *param,
1183     struct mlx5e_sq *sq)
1184 {
1185         int err;
1186
1187         err = mlx5e_create_sq(c, tc, param, sq);
1188         if (err)
1189                 return (err);
1190
1191         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1192         if (err)
1193                 goto err_destroy_sq;
1194
1195         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1196         if (err)
1197                 goto err_disable_sq;
1198
1199         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1200
1201         return (0);
1202
1203 err_disable_sq:
1204         mlx5e_disable_sq(sq);
1205 err_destroy_sq:
1206         mlx5e_destroy_sq(sq);
1207
1208         return (err);
1209 }
1210
1211 static void
1212 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1213 {
1214         /* fill up remainder with NOPs */
1215         while (sq->cev_counter != 0) {
1216                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1217                         if (can_sleep != 0) {
1218                                 mtx_unlock(&sq->lock);
1219                                 msleep(4);
1220                                 mtx_lock(&sq->lock);
1221                         } else {
1222                                 goto done;
1223                         }
1224                 }
1225                 /* send a single NOP */
1226                 mlx5e_send_nop(sq, 1);
1227                 wmb();
1228         }
1229 done:
1230         /* Check if we need to write the doorbell */
1231         if (likely(sq->doorbell.d64 != 0)) {
1232                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1233                 sq->doorbell.d64 = 0;
1234         }
1235 }
1236
1237 void
1238 mlx5e_sq_cev_timeout(void *arg)
1239 {
1240         struct mlx5e_sq *sq = arg;
1241
1242         mtx_assert(&sq->lock, MA_OWNED);
1243
1244         /* check next state */
1245         switch (sq->cev_next_state) {
1246         case MLX5E_CEV_STATE_SEND_NOPS:
1247                 /* fill TX ring with NOPs, if any */
1248                 mlx5e_sq_send_nops_locked(sq, 0);
1249
1250                 /* check if completed */
1251                 if (sq->cev_counter == 0) {
1252                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1253                         return;
1254                 }
1255                 break;
1256         default:
1257                 /* send NOPs on next timeout */
1258                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1259                 break;
1260         }
1261
1262         /* restart timer */
1263         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1264 }
1265
1266 void
1267 mlx5e_drain_sq(struct mlx5e_sq *sq)
1268 {
1269         int error;
1270         struct mlx5_core_dev *mdev = sq->priv->mdev;
1271
1272         /*
1273          * Check if already stopped.
1274          *
1275          * NOTE: The "stopped" variable is only written when both the
1276          * priv's configuration lock and the SQ's lock is locked. It
1277          * can therefore safely be read when only one of the two locks
1278          * is locked. This function is always called when the priv's
1279          * configuration lock is locked.
1280          */
1281         if (sq->stopped != 0)
1282                 return;
1283
1284         mtx_lock(&sq->lock);
1285
1286         /* don't put more packets into the SQ */
1287         sq->stopped = 1;
1288
1289         /* teardown event factor timer, if any */
1290         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1291         callout_stop(&sq->cev_callout);
1292
1293         /* send dummy NOPs in order to flush the transmit ring */
1294         mlx5e_sq_send_nops_locked(sq, 1);
1295         mtx_unlock(&sq->lock);
1296
1297         /* make sure it is safe to free the callout */
1298         callout_drain(&sq->cev_callout);
1299
1300         /* wait till SQ is empty or link is down */
1301         mtx_lock(&sq->lock);
1302         while (sq->cc != sq->pc &&
1303             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1304             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1305                 mtx_unlock(&sq->lock);
1306                 msleep(1);
1307                 sq->cq.mcq.comp(&sq->cq.mcq);
1308                 mtx_lock(&sq->lock);
1309         }
1310         mtx_unlock(&sq->lock);
1311
1312         /* error out remaining requests */
1313         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1314         if (error != 0) {
1315                 if_printf(sq->ifp,
1316                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1317         }
1318
1319         /* wait till SQ is empty */
1320         mtx_lock(&sq->lock);
1321         while (sq->cc != sq->pc &&
1322             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1323                 mtx_unlock(&sq->lock);
1324                 msleep(1);
1325                 sq->cq.mcq.comp(&sq->cq.mcq);
1326                 mtx_lock(&sq->lock);
1327         }
1328         mtx_unlock(&sq->lock);
1329 }
1330
1331 static void
1332 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1333 {
1334
1335         mlx5e_drain_sq(sq);
1336         mlx5e_disable_sq(sq);
1337         mlx5e_destroy_sq(sq);
1338 }
1339
1340 static int
1341 mlx5e_create_cq(struct mlx5e_priv *priv,
1342     struct mlx5e_cq_param *param,
1343     struct mlx5e_cq *cq,
1344     mlx5e_cq_comp_t *comp,
1345     int eq_ix)
1346 {
1347         struct mlx5_core_dev *mdev = priv->mdev;
1348         struct mlx5_core_cq *mcq = &cq->mcq;
1349         int eqn_not_used;
1350         int irqn;
1351         int err;
1352         u32 i;
1353
1354         param->wq.buf_numa_node = 0;
1355         param->wq.db_numa_node = 0;
1356
1357         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1358             &cq->wq_ctrl);
1359         if (err)
1360                 return (err);
1361
1362         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1363
1364         mcq->cqe_sz = 64;
1365         mcq->set_ci_db = cq->wq_ctrl.db.db;
1366         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1367         *mcq->set_ci_db = 0;
1368         *mcq->arm_db = 0;
1369         mcq->vector = eq_ix;
1370         mcq->comp = comp;
1371         mcq->event = mlx5e_cq_error_event;
1372         mcq->irqn = irqn;
1373         mcq->uar = &priv->cq_uar;
1374
1375         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1376                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1377
1378                 cqe->op_own = 0xf1;
1379         }
1380
1381         cq->priv = priv;
1382
1383         return (0);
1384 }
1385
1386 static void
1387 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1388 {
1389         mlx5_wq_destroy(&cq->wq_ctrl);
1390 }
1391
1392 static int
1393 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1394 {
1395         struct mlx5_core_cq *mcq = &cq->mcq;
1396         void *in;
1397         void *cqc;
1398         int inlen;
1399         int irqn_not_used;
1400         int eqn;
1401         int err;
1402
1403         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1404             sizeof(u64) * cq->wq_ctrl.buf.npages;
1405         in = mlx5_vzalloc(inlen);
1406         if (in == NULL)
1407                 return (-ENOMEM);
1408
1409         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1410
1411         memcpy(cqc, param->cqc, sizeof(param->cqc));
1412
1413         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1414             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1415
1416         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1417
1418         MLX5_SET(cqc, cqc, c_eqn, eqn);
1419         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1420         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1421             PAGE_SHIFT);
1422         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1423
1424         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1425
1426         kvfree(in);
1427
1428         if (err)
1429                 return (err);
1430
1431         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1432
1433         return (0);
1434 }
1435
1436 static void
1437 mlx5e_disable_cq(struct mlx5e_cq *cq)
1438 {
1439
1440         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1441 }
1442
1443 int
1444 mlx5e_open_cq(struct mlx5e_priv *priv,
1445     struct mlx5e_cq_param *param,
1446     struct mlx5e_cq *cq,
1447     mlx5e_cq_comp_t *comp,
1448     int eq_ix)
1449 {
1450         int err;
1451
1452         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1453         if (err)
1454                 return (err);
1455
1456         err = mlx5e_enable_cq(cq, param, eq_ix);
1457         if (err)
1458                 goto err_destroy_cq;
1459
1460         return (0);
1461
1462 err_destroy_cq:
1463         mlx5e_destroy_cq(cq);
1464
1465         return (err);
1466 }
1467
1468 void
1469 mlx5e_close_cq(struct mlx5e_cq *cq)
1470 {
1471         mlx5e_disable_cq(cq);
1472         mlx5e_destroy_cq(cq);
1473 }
1474
1475 static int
1476 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1477     struct mlx5e_channel_param *cparam)
1478 {
1479         int err;
1480         int tc;
1481
1482         for (tc = 0; tc < c->num_tc; tc++) {
1483                 /* open completion queue */
1484                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1485                     &mlx5e_tx_cq_comp, c->ix);
1486                 if (err)
1487                         goto err_close_tx_cqs;
1488         }
1489         return (0);
1490
1491 err_close_tx_cqs:
1492         for (tc--; tc >= 0; tc--)
1493                 mlx5e_close_cq(&c->sq[tc].cq);
1494
1495         return (err);
1496 }
1497
1498 static void
1499 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1500 {
1501         int tc;
1502
1503         for (tc = 0; tc < c->num_tc; tc++)
1504                 mlx5e_close_cq(&c->sq[tc].cq);
1505 }
1506
1507 static int
1508 mlx5e_open_sqs(struct mlx5e_channel *c,
1509     struct mlx5e_channel_param *cparam)
1510 {
1511         int err;
1512         int tc;
1513
1514         for (tc = 0; tc < c->num_tc; tc++) {
1515                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1516                 if (err)
1517                         goto err_close_sqs;
1518         }
1519
1520         return (0);
1521
1522 err_close_sqs:
1523         for (tc--; tc >= 0; tc--)
1524                 mlx5e_close_sq_wait(&c->sq[tc]);
1525
1526         return (err);
1527 }
1528
1529 static void
1530 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1531 {
1532         int tc;
1533
1534         for (tc = 0; tc < c->num_tc; tc++)
1535                 mlx5e_close_sq_wait(&c->sq[tc]);
1536 }
1537
1538 static void
1539 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1540 {
1541         int tc;
1542
1543         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1544
1545         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1546
1547         for (tc = 0; tc < c->num_tc; tc++) {
1548                 struct mlx5e_sq *sq = c->sq + tc;
1549
1550                 mtx_init(&sq->lock, "mlx5tx",
1551                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1552                 mtx_init(&sq->comp_lock, "mlx5comp",
1553                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1554
1555                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1556
1557                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1558
1559                 /* ensure the TX completion event factor is not zero */
1560                 if (sq->cev_factor == 0)
1561                         sq->cev_factor = 1;
1562         }
1563 }
1564
1565 static void
1566 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1567 {
1568         int tc;
1569
1570         mtx_destroy(&c->rq.mtx);
1571
1572         for (tc = 0; tc < c->num_tc; tc++) {
1573                 mtx_destroy(&c->sq[tc].lock);
1574                 mtx_destroy(&c->sq[tc].comp_lock);
1575         }
1576 }
1577
1578 static int
1579 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1580     struct mlx5e_channel_param *cparam,
1581     struct mlx5e_channel *volatile *cp)
1582 {
1583         struct mlx5e_channel *c;
1584         int err;
1585
1586         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1587         c->priv = priv;
1588         c->ix = ix;
1589         c->cpu = 0;
1590         c->ifp = priv->ifp;
1591         c->mkey_be = cpu_to_be32(priv->mr.key);
1592         c->num_tc = priv->num_tc;
1593
1594         /* init mutexes */
1595         mlx5e_chan_mtx_init(c);
1596
1597         /* open transmit completion queue */
1598         err = mlx5e_open_tx_cqs(c, cparam);
1599         if (err)
1600                 goto err_free;
1601
1602         /* open receive completion queue */
1603         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1604             &mlx5e_rx_cq_comp, c->ix);
1605         if (err)
1606                 goto err_close_tx_cqs;
1607
1608         err = mlx5e_open_sqs(c, cparam);
1609         if (err)
1610                 goto err_close_rx_cq;
1611
1612         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1613         if (err)
1614                 goto err_close_sqs;
1615
1616         /* store channel pointer */
1617         *cp = c;
1618
1619         /* poll receive queue initially */
1620         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1621
1622         return (0);
1623
1624 err_close_sqs:
1625         mlx5e_close_sqs_wait(c);
1626
1627 err_close_rx_cq:
1628         mlx5e_close_cq(&c->rq.cq);
1629
1630 err_close_tx_cqs:
1631         mlx5e_close_tx_cqs(c);
1632
1633 err_free:
1634         /* destroy mutexes */
1635         mlx5e_chan_mtx_destroy(c);
1636         free(c, M_MLX5EN);
1637         return (err);
1638 }
1639
1640 static void
1641 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1642 {
1643         struct mlx5e_channel *c = *pp;
1644
1645         /* check if channel is already closed */
1646         if (c == NULL)
1647                 return;
1648         mlx5e_close_rq(&c->rq);
1649 }
1650
1651 static void
1652 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1653 {
1654         struct mlx5e_channel *c = *pp;
1655
1656         /* check if channel is already closed */
1657         if (c == NULL)
1658                 return;
1659         /* ensure channel pointer is no longer used */
1660         *pp = NULL;
1661
1662         mlx5e_close_rq_wait(&c->rq);
1663         mlx5e_close_sqs_wait(c);
1664         mlx5e_close_cq(&c->rq.cq);
1665         mlx5e_close_tx_cqs(c);
1666         /* destroy mutexes */
1667         mlx5e_chan_mtx_destroy(c);
1668         free(c, M_MLX5EN);
1669 }
1670
1671 static int
1672 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1673 {
1674         u32 r, n;
1675
1676         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1677             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1678         if (r > MJUM16BYTES)
1679                 return (-ENOMEM);
1680
1681         if (r > MJUM9BYTES)
1682                 r = MJUM16BYTES;
1683         else if (r > MJUMPAGESIZE)
1684                 r = MJUM9BYTES;
1685         else if (r > MCLBYTES)
1686                 r = MJUMPAGESIZE;
1687         else
1688                 r = MCLBYTES;
1689
1690         /*
1691          * n + 1 must be a power of two, because stride size must be.
1692          * Stride size is 16 * (n + 1), as the first segment is
1693          * control.
1694          */
1695         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1696                 ;
1697
1698         *wqe_sz = r;
1699         *nsegs = n;
1700         return (0);
1701 }
1702
1703 static void
1704 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1705     struct mlx5e_rq_param *param)
1706 {
1707         void *rqc = param->rqc;
1708         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1709         u32 wqe_sz, nsegs;
1710
1711         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1712         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1713         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1714         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1715             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1716         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1717         MLX5_SET(wq, wq, pd, priv->pdn);
1718
1719         param->wq.buf_numa_node = 0;
1720         param->wq.db_numa_node = 0;
1721         param->wq.linear = 1;
1722 }
1723
1724 static void
1725 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1726     struct mlx5e_sq_param *param)
1727 {
1728         void *sqc = param->sqc;
1729         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1730
1731         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1732         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1733         MLX5_SET(wq, wq, pd, priv->pdn);
1734
1735         param->wq.buf_numa_node = 0;
1736         param->wq.db_numa_node = 0;
1737         param->wq.linear = 1;
1738 }
1739
1740 static void
1741 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1742     struct mlx5e_cq_param *param)
1743 {
1744         void *cqc = param->cqc;
1745
1746         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1747 }
1748
1749 static void
1750 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1751     struct mlx5e_cq_param *param)
1752 {
1753         void *cqc = param->cqc;
1754
1755
1756         /*
1757          * TODO The sysctl to control on/off is a bool value for now, which means
1758          * we only support CSUM, once HASH is implemnted we'll need to address that.
1759          */
1760         if (priv->params.cqe_zipping_en) {
1761                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1762                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1763         }
1764
1765         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1766         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1767         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1768
1769         switch (priv->params.rx_cq_moderation_mode) {
1770         case 0:
1771                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1772                 break;
1773         default:
1774                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1775                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1776                 else
1777                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1778                 break;
1779         }
1780
1781         mlx5e_build_common_cq_param(priv, param);
1782 }
1783
1784 static void
1785 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1786     struct mlx5e_cq_param *param)
1787 {
1788         void *cqc = param->cqc;
1789
1790         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1791         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1792         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1793
1794         switch (priv->params.tx_cq_moderation_mode) {
1795         case 0:
1796                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1797                 break;
1798         default:
1799                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1800                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1801                 else
1802                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1803                 break;
1804         }
1805
1806         mlx5e_build_common_cq_param(priv, param);
1807 }
1808
1809 static void
1810 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1811     struct mlx5e_channel_param *cparam)
1812 {
1813         memset(cparam, 0, sizeof(*cparam));
1814
1815         mlx5e_build_rq_param(priv, &cparam->rq);
1816         mlx5e_build_sq_param(priv, &cparam->sq);
1817         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1818         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1819 }
1820
1821 static int
1822 mlx5e_open_channels(struct mlx5e_priv *priv)
1823 {
1824         struct mlx5e_channel_param cparam;
1825         void *ptr;
1826         int err;
1827         int i;
1828         int j;
1829
1830         priv->channel = malloc(priv->params.num_channels *
1831             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1832
1833         mlx5e_build_channel_param(priv, &cparam);
1834         for (i = 0; i < priv->params.num_channels; i++) {
1835                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1836                 if (err)
1837                         goto err_close_channels;
1838         }
1839
1840         for (j = 0; j < priv->params.num_channels; j++) {
1841                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1842                 if (err)
1843                         goto err_close_channels;
1844         }
1845
1846         return (0);
1847
1848 err_close_channels:
1849         for (i--; i >= 0; i--) {
1850                 mlx5e_close_channel(&priv->channel[i]);
1851                 mlx5e_close_channel_wait(&priv->channel[i]);
1852         }
1853
1854         /* remove "volatile" attribute from "channel" pointer */
1855         ptr = __DECONST(void *, priv->channel);
1856         priv->channel = NULL;
1857
1858         free(ptr, M_MLX5EN);
1859
1860         return (err);
1861 }
1862
1863 static void
1864 mlx5e_close_channels(struct mlx5e_priv *priv)
1865 {
1866         void *ptr;
1867         int i;
1868
1869         if (priv->channel == NULL)
1870                 return;
1871
1872         for (i = 0; i < priv->params.num_channels; i++)
1873                 mlx5e_close_channel(&priv->channel[i]);
1874         for (i = 0; i < priv->params.num_channels; i++)
1875                 mlx5e_close_channel_wait(&priv->channel[i]);
1876
1877         /* remove "volatile" attribute from "channel" pointer */
1878         ptr = __DECONST(void *, priv->channel);
1879         priv->channel = NULL;
1880
1881         free(ptr, M_MLX5EN);
1882 }
1883
1884 static int
1885 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1886 {
1887
1888         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1889                 uint8_t cq_mode;
1890
1891                 switch (priv->params.tx_cq_moderation_mode) {
1892                 case 0:
1893                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1894                         break;
1895                 default:
1896                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1897                         break;
1898                 }
1899
1900                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
1901                     priv->params.tx_cq_moderation_usec,
1902                     priv->params.tx_cq_moderation_pkts,
1903                     cq_mode));
1904         }
1905
1906         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1907             priv->params.tx_cq_moderation_usec,
1908             priv->params.tx_cq_moderation_pkts));
1909 }
1910
1911 static int
1912 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1913 {
1914
1915         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1916                 uint8_t cq_mode;
1917                 int retval;
1918
1919                 switch (priv->params.rx_cq_moderation_mode) {
1920                 case 0:
1921                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1922                         break;
1923                 default:
1924                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1925                         break;
1926                 }
1927
1928                 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
1929                     priv->params.rx_cq_moderation_usec,
1930                     priv->params.rx_cq_moderation_pkts,
1931                     cq_mode);
1932
1933                 return (retval);
1934         }
1935
1936         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1937             priv->params.rx_cq_moderation_usec,
1938             priv->params.rx_cq_moderation_pkts));
1939 }
1940
1941 static int
1942 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1943 {
1944         int err;
1945         int i;
1946
1947         if (c == NULL)
1948                 return (EINVAL);
1949
1950         err = mlx5e_refresh_rq_params(priv, &c->rq);
1951         if (err)
1952                 goto done;
1953
1954         for (i = 0; i != c->num_tc; i++) {
1955                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1956                 if (err)
1957                         goto done;
1958         }
1959 done:
1960         return (err);
1961 }
1962
1963 int
1964 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1965 {
1966         int i;
1967
1968         if (priv->channel == NULL)
1969                 return (EINVAL);
1970
1971         for (i = 0; i < priv->params.num_channels; i++) {
1972                 int err;
1973
1974                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1975                 if (err)
1976                         return (err);
1977         }
1978         return (0);
1979 }
1980
1981 static int
1982 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1983 {
1984         struct mlx5_core_dev *mdev = priv->mdev;
1985         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1986         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1987
1988         memset(in, 0, sizeof(in));
1989
1990         MLX5_SET(tisc, tisc, prio, tc);
1991         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1992
1993         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1994 }
1995
1996 static void
1997 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1998 {
1999         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2000 }
2001
2002 static int
2003 mlx5e_open_tises(struct mlx5e_priv *priv)
2004 {
2005         int num_tc = priv->num_tc;
2006         int err;
2007         int tc;
2008
2009         for (tc = 0; tc < num_tc; tc++) {
2010                 err = mlx5e_open_tis(priv, tc);
2011                 if (err)
2012                         goto err_close_tises;
2013         }
2014
2015         return (0);
2016
2017 err_close_tises:
2018         for (tc--; tc >= 0; tc--)
2019                 mlx5e_close_tis(priv, tc);
2020
2021         return (err);
2022 }
2023
2024 static void
2025 mlx5e_close_tises(struct mlx5e_priv *priv)
2026 {
2027         int num_tc = priv->num_tc;
2028         int tc;
2029
2030         for (tc = 0; tc < num_tc; tc++)
2031                 mlx5e_close_tis(priv, tc);
2032 }
2033
2034 static int
2035 mlx5e_open_rqt(struct mlx5e_priv *priv)
2036 {
2037         struct mlx5_core_dev *mdev = priv->mdev;
2038         u32 *in;
2039         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
2040         void *rqtc;
2041         int inlen;
2042         int err;
2043         int sz;
2044         int i;
2045
2046         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2047
2048         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2049         in = mlx5_vzalloc(inlen);
2050         if (in == NULL)
2051                 return (-ENOMEM);
2052         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2053
2054         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2055         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2056
2057         for (i = 0; i < sz; i++) {
2058                 int ix = i;
2059 #ifdef RSS
2060                 ix = rss_get_indirection_to_bucket(ix);
2061 #endif
2062                 /* ensure we don't overflow */
2063                 ix %= priv->params.num_channels;
2064
2065                 /* apply receive side scaling stride, if any */
2066                 ix -= ix % (int)priv->params.channels_rsss;
2067
2068                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2069         }
2070
2071         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2072
2073         memset(out, 0, sizeof(out));
2074         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
2075         if (!err)
2076                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2077
2078         kvfree(in);
2079
2080         return (err);
2081 }
2082
2083 static void
2084 mlx5e_close_rqt(struct mlx5e_priv *priv)
2085 {
2086         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
2087         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
2088
2089         memset(in, 0, sizeof(in));
2090
2091         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2092         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2093
2094         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
2095             sizeof(out));
2096 }
2097
2098 static void
2099 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2100 {
2101         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2102         __be32 *hkey;
2103
2104         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2105
2106 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2107
2108 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2109                           MLX5_HASH_FIELD_SEL_DST_IP)
2110
2111 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2112                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2113                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2114                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2115
2116 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2117                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2118                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2119
2120         if (priv->params.hw_lro_en) {
2121                 MLX5_SET(tirc, tirc, lro_enable_mask,
2122                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2123                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2124                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2125                     (priv->params.lro_wqe_sz -
2126                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2127                 /* TODO: add the option to choose timer value dynamically */
2128                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2129                     MLX5_CAP_ETH(priv->mdev,
2130                     lro_timer_supported_periods[2]));
2131         }
2132
2133         /* setup parameters for hashing TIR type, if any */
2134         switch (tt) {
2135         case MLX5E_TT_ANY:
2136                 MLX5_SET(tirc, tirc, disp_type,
2137                     MLX5_TIRC_DISP_TYPE_DIRECT);
2138                 MLX5_SET(tirc, tirc, inline_rqn,
2139                     priv->channel[0]->rq.rqn);
2140                 break;
2141         default:
2142                 MLX5_SET(tirc, tirc, disp_type,
2143                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2144                 MLX5_SET(tirc, tirc, indirect_table,
2145                     priv->rqtn);
2146                 MLX5_SET(tirc, tirc, rx_hash_fn,
2147                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2148                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2149 #ifdef RSS
2150                 /*
2151                  * The FreeBSD RSS implementation does currently not
2152                  * support symmetric Toeplitz hashes:
2153                  */
2154                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2155                 rss_getkey((uint8_t *)hkey);
2156 #else
2157                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2158                 hkey[0] = cpu_to_be32(0xD181C62C);
2159                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2160                 hkey[2] = cpu_to_be32(0x1983A2FC);
2161                 hkey[3] = cpu_to_be32(0x943E1ADB);
2162                 hkey[4] = cpu_to_be32(0xD9389E6B);
2163                 hkey[5] = cpu_to_be32(0xD1039C2C);
2164                 hkey[6] = cpu_to_be32(0xA74499AD);
2165                 hkey[7] = cpu_to_be32(0x593D56D9);
2166                 hkey[8] = cpu_to_be32(0xF3253C06);
2167                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2168 #endif
2169                 break;
2170         }
2171
2172         switch (tt) {
2173         case MLX5E_TT_IPV4_TCP:
2174                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2175                     MLX5_L3_PROT_TYPE_IPV4);
2176                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2177                     MLX5_L4_PROT_TYPE_TCP);
2178 #ifdef RSS
2179                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2180                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2181                             MLX5_HASH_IP);
2182                 } else
2183 #endif
2184                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2185                     MLX5_HASH_ALL);
2186                 break;
2187
2188         case MLX5E_TT_IPV6_TCP:
2189                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2190                     MLX5_L3_PROT_TYPE_IPV6);
2191                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2192                     MLX5_L4_PROT_TYPE_TCP);
2193 #ifdef RSS
2194                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2195                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2196                             MLX5_HASH_IP);
2197                 } else
2198 #endif
2199                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2200                     MLX5_HASH_ALL);
2201                 break;
2202
2203         case MLX5E_TT_IPV4_UDP:
2204                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2205                     MLX5_L3_PROT_TYPE_IPV4);
2206                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2207                     MLX5_L4_PROT_TYPE_UDP);
2208 #ifdef RSS
2209                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2210                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2211                             MLX5_HASH_IP);
2212                 } else
2213 #endif
2214                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2215                     MLX5_HASH_ALL);
2216                 break;
2217
2218         case MLX5E_TT_IPV6_UDP:
2219                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2220                     MLX5_L3_PROT_TYPE_IPV6);
2221                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2222                     MLX5_L4_PROT_TYPE_UDP);
2223 #ifdef RSS
2224                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2225                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2226                             MLX5_HASH_IP);
2227                 } else
2228 #endif
2229                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2230                     MLX5_HASH_ALL);
2231                 break;
2232
2233         case MLX5E_TT_IPV4_IPSEC_AH:
2234                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2235                     MLX5_L3_PROT_TYPE_IPV4);
2236                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2237                     MLX5_HASH_IP_IPSEC_SPI);
2238                 break;
2239
2240         case MLX5E_TT_IPV6_IPSEC_AH:
2241                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2242                     MLX5_L3_PROT_TYPE_IPV6);
2243                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2244                     MLX5_HASH_IP_IPSEC_SPI);
2245                 break;
2246
2247         case MLX5E_TT_IPV4_IPSEC_ESP:
2248                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2249                     MLX5_L3_PROT_TYPE_IPV4);
2250                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2251                     MLX5_HASH_IP_IPSEC_SPI);
2252                 break;
2253
2254         case MLX5E_TT_IPV6_IPSEC_ESP:
2255                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2256                     MLX5_L3_PROT_TYPE_IPV6);
2257                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2258                     MLX5_HASH_IP_IPSEC_SPI);
2259                 break;
2260
2261         case MLX5E_TT_IPV4:
2262                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2263                     MLX5_L3_PROT_TYPE_IPV4);
2264                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2265                     MLX5_HASH_IP);
2266                 break;
2267
2268         case MLX5E_TT_IPV6:
2269                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2270                     MLX5_L3_PROT_TYPE_IPV6);
2271                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2272                     MLX5_HASH_IP);
2273                 break;
2274
2275         default:
2276                 break;
2277         }
2278 }
2279
2280 static int
2281 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2282 {
2283         struct mlx5_core_dev *mdev = priv->mdev;
2284         u32 *in;
2285         void *tirc;
2286         int inlen;
2287         int err;
2288
2289         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2290         in = mlx5_vzalloc(inlen);
2291         if (in == NULL)
2292                 return (-ENOMEM);
2293         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2294
2295         mlx5e_build_tir_ctx(priv, tirc, tt);
2296
2297         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2298
2299         kvfree(in);
2300
2301         return (err);
2302 }
2303
2304 static void
2305 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2306 {
2307         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2308 }
2309
2310 static int
2311 mlx5e_open_tirs(struct mlx5e_priv *priv)
2312 {
2313         int err;
2314         int i;
2315
2316         for (i = 0; i < MLX5E_NUM_TT; i++) {
2317                 err = mlx5e_open_tir(priv, i);
2318                 if (err)
2319                         goto err_close_tirs;
2320         }
2321
2322         return (0);
2323
2324 err_close_tirs:
2325         for (i--; i >= 0; i--)
2326                 mlx5e_close_tir(priv, i);
2327
2328         return (err);
2329 }
2330
2331 static void
2332 mlx5e_close_tirs(struct mlx5e_priv *priv)
2333 {
2334         int i;
2335
2336         for (i = 0; i < MLX5E_NUM_TT; i++)
2337                 mlx5e_close_tir(priv, i);
2338 }
2339
2340 /*
2341  * SW MTU does not include headers,
2342  * HW MTU includes all headers and checksums.
2343  */
2344 static int
2345 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2346 {
2347         struct mlx5e_priv *priv = ifp->if_softc;
2348         struct mlx5_core_dev *mdev = priv->mdev;
2349         int hw_mtu;
2350         int err;
2351
2352         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2353
2354         err = mlx5_set_port_mtu(mdev, hw_mtu);
2355         if (err) {
2356                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2357                     __func__, sw_mtu, err);
2358                 return (err);
2359         }
2360
2361         /* Update vport context MTU */
2362         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2363         if (err) {
2364                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2365                     __func__, err);
2366         }
2367
2368         ifp->if_mtu = sw_mtu;
2369
2370         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2371         if (err || !hw_mtu) {
2372                 /* fallback to port oper mtu */
2373                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2374         }
2375         if (err) {
2376                 if_printf(ifp, "Query port MTU, after setting new "
2377                     "MTU value, failed\n");
2378                 return (err);
2379         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2380                 err = -E2BIG,
2381                 if_printf(ifp, "Port MTU %d is smaller than "
2382                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2383         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2384                 err = -EINVAL;
2385                 if_printf(ifp, "Port MTU %d is bigger than "
2386                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2387         }
2388         priv->params_ethtool.hw_mtu = hw_mtu;
2389
2390         return (err);
2391 }
2392
2393 int
2394 mlx5e_open_locked(struct ifnet *ifp)
2395 {
2396         struct mlx5e_priv *priv = ifp->if_softc;
2397         int err;
2398         u16 set_id;
2399
2400         /* check if already opened */
2401         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2402                 return (0);
2403
2404 #ifdef RSS
2405         if (rss_getnumbuckets() > priv->params.num_channels) {
2406                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2407                     "channels(%u) available\n", rss_getnumbuckets(),
2408                     priv->params.num_channels);
2409         }
2410 #endif
2411         err = mlx5e_open_tises(priv);
2412         if (err) {
2413                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2414                     __func__, err);
2415                 return (err);
2416         }
2417         err = mlx5_vport_alloc_q_counter(priv->mdev,
2418             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2419         if (err) {
2420                 if_printf(priv->ifp,
2421                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2422                     __func__, err);
2423                 goto err_close_tises;
2424         }
2425         /* store counter set ID */
2426         priv->counter_set_id = set_id;
2427
2428         err = mlx5e_open_channels(priv);
2429         if (err) {
2430                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2431                     __func__, err);
2432                 goto err_dalloc_q_counter;
2433         }
2434         err = mlx5e_open_rqt(priv);
2435         if (err) {
2436                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2437                     __func__, err);
2438                 goto err_close_channels;
2439         }
2440         err = mlx5e_open_tirs(priv);
2441         if (err) {
2442                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2443                     __func__, err);
2444                 goto err_close_rqls;
2445         }
2446         err = mlx5e_open_flow_table(priv);
2447         if (err) {
2448                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2449                     __func__, err);
2450                 goto err_close_tirs;
2451         }
2452         err = mlx5e_add_all_vlan_rules(priv);
2453         if (err) {
2454                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2455                     __func__, err);
2456                 goto err_close_flow_table;
2457         }
2458         set_bit(MLX5E_STATE_OPENED, &priv->state);
2459
2460         mlx5e_update_carrier(priv);
2461         mlx5e_set_rx_mode_core(priv);
2462
2463         return (0);
2464
2465 err_close_flow_table:
2466         mlx5e_close_flow_table(priv);
2467
2468 err_close_tirs:
2469         mlx5e_close_tirs(priv);
2470
2471 err_close_rqls:
2472         mlx5e_close_rqt(priv);
2473
2474 err_close_channels:
2475         mlx5e_close_channels(priv);
2476
2477 err_dalloc_q_counter:
2478         mlx5_vport_dealloc_q_counter(priv->mdev,
2479             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2480
2481 err_close_tises:
2482         mlx5e_close_tises(priv);
2483
2484         return (err);
2485 }
2486
2487 static void
2488 mlx5e_open(void *arg)
2489 {
2490         struct mlx5e_priv *priv = arg;
2491
2492         PRIV_LOCK(priv);
2493         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2494                 if_printf(priv->ifp,
2495                     "%s: Setting port status to up failed\n",
2496                     __func__);
2497
2498         mlx5e_open_locked(priv->ifp);
2499         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2500         PRIV_UNLOCK(priv);
2501 }
2502
2503 int
2504 mlx5e_close_locked(struct ifnet *ifp)
2505 {
2506         struct mlx5e_priv *priv = ifp->if_softc;
2507
2508         /* check if already closed */
2509         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2510                 return (0);
2511
2512         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2513
2514         mlx5e_set_rx_mode_core(priv);
2515         mlx5e_del_all_vlan_rules(priv);
2516         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2517         mlx5e_close_flow_table(priv);
2518         mlx5e_close_tirs(priv);
2519         mlx5e_close_rqt(priv);
2520         mlx5e_close_channels(priv);
2521         mlx5_vport_dealloc_q_counter(priv->mdev,
2522             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2523         mlx5e_close_tises(priv);
2524
2525         return (0);
2526 }
2527
2528 #if (__FreeBSD_version >= 1100000)
2529 static uint64_t
2530 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2531 {
2532         struct mlx5e_priv *priv = ifp->if_softc;
2533         u64 retval;
2534
2535         /* PRIV_LOCK(priv); XXX not allowed */
2536         switch (cnt) {
2537         case IFCOUNTER_IPACKETS:
2538                 retval = priv->stats.vport.rx_packets;
2539                 break;
2540         case IFCOUNTER_IERRORS:
2541                 retval = priv->stats.vport.rx_error_packets +
2542                     priv->stats.pport.alignment_err +
2543                     priv->stats.pport.check_seq_err +
2544                     priv->stats.pport.crc_align_errors +
2545                     priv->stats.pport.in_range_len_errors +
2546                     priv->stats.pport.jabbers +
2547                     priv->stats.pport.out_of_range_len +
2548                     priv->stats.pport.oversize_pkts +
2549                     priv->stats.pport.symbol_err +
2550                     priv->stats.pport.too_long_errors +
2551                     priv->stats.pport.undersize_pkts +
2552                     priv->stats.pport.unsupported_op_rx;
2553                 break;
2554         case IFCOUNTER_IQDROPS:
2555                 retval = priv->stats.vport.rx_out_of_buffer +
2556                     priv->stats.pport.drop_events;
2557                 break;
2558         case IFCOUNTER_OPACKETS:
2559                 retval = priv->stats.vport.tx_packets;
2560                 break;
2561         case IFCOUNTER_OERRORS:
2562                 retval = priv->stats.vport.tx_error_packets;
2563                 break;
2564         case IFCOUNTER_IBYTES:
2565                 retval = priv->stats.vport.rx_bytes;
2566                 break;
2567         case IFCOUNTER_OBYTES:
2568                 retval = priv->stats.vport.tx_bytes;
2569                 break;
2570         case IFCOUNTER_IMCASTS:
2571                 retval = priv->stats.vport.rx_multicast_packets;
2572                 break;
2573         case IFCOUNTER_OMCASTS:
2574                 retval = priv->stats.vport.tx_multicast_packets;
2575                 break;
2576         case IFCOUNTER_OQDROPS:
2577                 retval = priv->stats.vport.tx_queue_dropped;
2578                 break;
2579         case IFCOUNTER_COLLISIONS:
2580                 retval = priv->stats.pport.collisions;
2581                 break;
2582         default:
2583                 retval = if_get_counter_default(ifp, cnt);
2584                 break;
2585         }
2586         /* PRIV_UNLOCK(priv); XXX not allowed */
2587         return (retval);
2588 }
2589 #endif
2590
2591 static void
2592 mlx5e_set_rx_mode(struct ifnet *ifp)
2593 {
2594         struct mlx5e_priv *priv = ifp->if_softc;
2595
2596         schedule_work(&priv->set_rx_mode_work);
2597 }
2598
2599 static int
2600 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2601 {
2602         struct mlx5e_priv *priv;
2603         struct ifreq *ifr;
2604         struct ifi2creq i2c;
2605         int error = 0;
2606         int mask = 0;
2607         int size_read = 0;
2608         int module_num;
2609         int max_mtu;
2610         uint8_t read_addr;
2611
2612         priv = ifp->if_softc;
2613
2614         /* check if detaching */
2615         if (priv == NULL || priv->gone != 0)
2616                 return (ENXIO);
2617
2618         switch (command) {
2619         case SIOCSIFMTU:
2620                 ifr = (struct ifreq *)data;
2621
2622                 PRIV_LOCK(priv);
2623                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2624
2625                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2626                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2627                         int was_opened;
2628
2629                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2630                         if (was_opened)
2631                                 mlx5e_close_locked(ifp);
2632
2633                         /* set new MTU */
2634                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2635
2636                         if (was_opened)
2637                                 mlx5e_open_locked(ifp);
2638                 } else {
2639                         error = EINVAL;
2640                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2641                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2642                 }
2643                 PRIV_UNLOCK(priv);
2644                 break;
2645         case SIOCSIFFLAGS:
2646                 if ((ifp->if_flags & IFF_UP) &&
2647                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2648                         mlx5e_set_rx_mode(ifp);
2649                         break;
2650                 }
2651                 PRIV_LOCK(priv);
2652                 if (ifp->if_flags & IFF_UP) {
2653                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2654                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2655                                         mlx5e_open_locked(ifp);
2656                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2657                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2658                         }
2659                 } else {
2660                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2661                                 mlx5_set_port_status(priv->mdev,
2662                                     MLX5_PORT_DOWN);
2663                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2664                                         mlx5e_close_locked(ifp);
2665                                 mlx5e_update_carrier(priv);
2666                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2667                         }
2668                 }
2669                 PRIV_UNLOCK(priv);
2670                 break;
2671         case SIOCADDMULTI:
2672         case SIOCDELMULTI:
2673                 mlx5e_set_rx_mode(ifp);
2674                 break;
2675         case SIOCSIFMEDIA:
2676         case SIOCGIFMEDIA:
2677         case SIOCGIFXMEDIA:
2678                 ifr = (struct ifreq *)data;
2679                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2680                 break;
2681         case SIOCSIFCAP:
2682                 ifr = (struct ifreq *)data;
2683                 PRIV_LOCK(priv);
2684                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2685
2686                 if (mask & IFCAP_TXCSUM) {
2687                         ifp->if_capenable ^= IFCAP_TXCSUM;
2688                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2689
2690                         if (IFCAP_TSO4 & ifp->if_capenable &&
2691                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2692                                 ifp->if_capenable &= ~IFCAP_TSO4;
2693                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2694                                 if_printf(ifp,
2695                                     "tso4 disabled due to -txcsum.\n");
2696                         }
2697                 }
2698                 if (mask & IFCAP_TXCSUM_IPV6) {
2699                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2700                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2701
2702                         if (IFCAP_TSO6 & ifp->if_capenable &&
2703                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2704                                 ifp->if_capenable &= ~IFCAP_TSO6;
2705                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2706                                 if_printf(ifp,
2707                                     "tso6 disabled due to -txcsum6.\n");
2708                         }
2709                 }
2710                 if (mask & IFCAP_RXCSUM)
2711                         ifp->if_capenable ^= IFCAP_RXCSUM;
2712                 if (mask & IFCAP_RXCSUM_IPV6)
2713                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2714                 if (mask & IFCAP_TSO4) {
2715                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2716                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2717                                 if_printf(ifp, "enable txcsum first.\n");
2718                                 error = EAGAIN;
2719                                 goto out;
2720                         }
2721                         ifp->if_capenable ^= IFCAP_TSO4;
2722                         ifp->if_hwassist ^= CSUM_IP_TSO;
2723                 }
2724                 if (mask & IFCAP_TSO6) {
2725                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2726                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2727                                 if_printf(ifp, "enable txcsum6 first.\n");
2728                                 error = EAGAIN;
2729                                 goto out;
2730                         }
2731                         ifp->if_capenable ^= IFCAP_TSO6;
2732                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2733                 }
2734                 if (mask & IFCAP_VLAN_HWFILTER) {
2735                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2736                                 mlx5e_disable_vlan_filter(priv);
2737                         else
2738                                 mlx5e_enable_vlan_filter(priv);
2739
2740                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2741                 }
2742                 if (mask & IFCAP_VLAN_HWTAGGING)
2743                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2744                 if (mask & IFCAP_WOL_MAGIC)
2745                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2746
2747                 VLAN_CAPABILITIES(ifp);
2748                 /* turn off LRO means also turn of HW LRO - if it's on */
2749                 if (mask & IFCAP_LRO) {
2750                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2751                         bool need_restart = false;
2752
2753                         ifp->if_capenable ^= IFCAP_LRO;
2754                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2755                                 if (priv->params.hw_lro_en) {
2756                                         priv->params.hw_lro_en = false;
2757                                         need_restart = true;
2758                                         /* Not sure this is the correct way */
2759                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2760                                 }
2761                         }
2762                         if (was_opened && need_restart) {
2763                                 mlx5e_close_locked(ifp);
2764                                 mlx5e_open_locked(ifp);
2765                         }
2766                 }
2767 out:
2768                 PRIV_UNLOCK(priv);
2769                 break;
2770
2771         case SIOCGI2C:
2772                 ifr = (struct ifreq *)data;
2773
2774                 /*
2775                  * Copy from the user-space address ifr_data to the
2776                  * kernel-space address i2c
2777                  */
2778                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2779                 if (error)
2780                         break;
2781
2782                 if (i2c.len > sizeof(i2c.data)) {
2783                         error = EINVAL;
2784                         break;
2785                 }
2786
2787                 PRIV_LOCK(priv);
2788                 /* Get module_num which is required for the query_eeprom */
2789                 error = mlx5_query_module_num(priv->mdev, &module_num);
2790                 if (error) {
2791                         if_printf(ifp, "Query module num failed, eeprom "
2792                             "reading is not supported\n");
2793                         error = EINVAL;
2794                         goto err_i2c;
2795                 }
2796                 /* Check if module is present before doing an access */
2797                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2798                     MLX5_MODULE_STATUS_PLUGGED) {
2799                         error = EINVAL;
2800                         goto err_i2c;
2801                 }
2802                 /*
2803                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2804                  * The internal conversion is as follows:
2805                  */
2806                 if (i2c.dev_addr == 0xA0)
2807                         read_addr = MLX5E_I2C_ADDR_LOW;
2808                 else if (i2c.dev_addr == 0xA2)
2809                         read_addr = MLX5E_I2C_ADDR_HIGH;
2810                 else {
2811                         if_printf(ifp, "Query eeprom failed, "
2812                             "Invalid Address: %X\n", i2c.dev_addr);
2813                         error = EINVAL;
2814                         goto err_i2c;
2815                 }
2816                 error = mlx5_query_eeprom(priv->mdev,
2817                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2818                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2819                     (uint32_t *)i2c.data, &size_read);
2820                 if (error) {
2821                         if_printf(ifp, "Query eeprom failed, eeprom "
2822                             "reading is not supported\n");
2823                         error = EINVAL;
2824                         goto err_i2c;
2825                 }
2826
2827                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2828                         error = mlx5_query_eeprom(priv->mdev,
2829                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2830                             (uint32_t)(i2c.offset + size_read),
2831                             (uint32_t)(i2c.len - size_read), module_num,
2832                             (uint32_t *)(i2c.data + size_read), &size_read);
2833                 }
2834                 if (error) {
2835                         if_printf(ifp, "Query eeprom failed, eeprom "
2836                             "reading is not supported\n");
2837                         error = EINVAL;
2838                         goto err_i2c;
2839                 }
2840
2841                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2842 err_i2c:
2843                 PRIV_UNLOCK(priv);
2844                 break;
2845
2846         default:
2847                 error = ether_ioctl(ifp, command, data);
2848                 break;
2849         }
2850         return (error);
2851 }
2852
2853 static int
2854 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2855 {
2856         /*
2857          * TODO: uncoment once FW really sets all these bits if
2858          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2859          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2860          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2861          * -ENOTSUPP;
2862          */
2863
2864         /* TODO: add more must-to-have features */
2865
2866         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2867                 return (-ENODEV);
2868
2869         return (0);
2870 }
2871
2872 static u16
2873 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2874 {
2875         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2876
2877         return bf_buf_size -
2878                sizeof(struct mlx5e_tx_wqe) +
2879                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2880 }
2881
2882 static void
2883 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2884     struct mlx5e_priv *priv,
2885     int num_comp_vectors)
2886 {
2887         /*
2888          * TODO: Consider link speed for setting "log_sq_size",
2889          * "log_rq_size" and "cq_moderation_xxx":
2890          */
2891         priv->params.log_sq_size =
2892             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2893         priv->params.log_rq_size =
2894             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2895         priv->params.rx_cq_moderation_usec =
2896             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2897             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2898             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2899         priv->params.rx_cq_moderation_mode =
2900             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2901         priv->params.rx_cq_moderation_pkts =
2902             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2903         priv->params.tx_cq_moderation_usec =
2904             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2905         priv->params.tx_cq_moderation_pkts =
2906             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2907         priv->params.min_rx_wqes =
2908             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2909         priv->params.rx_hash_log_tbl_sz =
2910             (order_base_2(num_comp_vectors) >
2911             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2912             order_base_2(num_comp_vectors) :
2913             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2914         priv->params.num_tc = 1;
2915         priv->params.default_vlan_prio = 0;
2916         priv->counter_set_id = -1;
2917         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2918         mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
2919
2920         /*
2921          * hw lro is currently defaulted to off. when it won't anymore we
2922          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2923          */
2924         priv->params.hw_lro_en = false;
2925         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2926
2927         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2928
2929         priv->mdev = mdev;
2930         priv->params.num_channels = num_comp_vectors;
2931         priv->params.channels_rsss = 1;
2932         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2933         priv->queue_mapping_channel_mask =
2934             roundup_pow_of_two(num_comp_vectors) - 1;
2935         priv->num_tc = priv->params.num_tc;
2936         priv->default_vlan_prio = priv->params.default_vlan_prio;
2937
2938         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2939         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2940         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2941 }
2942
2943 static int
2944 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2945     struct mlx5_core_mr *mr)
2946 {
2947         struct ifnet *ifp = priv->ifp;
2948         struct mlx5_core_dev *mdev = priv->mdev;
2949         struct mlx5_create_mkey_mbox_in *in;
2950         int err;
2951
2952         in = mlx5_vzalloc(sizeof(*in));
2953         if (in == NULL) {
2954                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2955                 return (-ENOMEM);
2956         }
2957         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2958             MLX5_PERM_LOCAL_READ |
2959             MLX5_ACCESS_MODE_PA;
2960         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2961         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2962
2963         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2964             NULL);
2965         if (err)
2966                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2967                     __func__, err);
2968
2969         kvfree(in);
2970
2971         return (err);
2972 }
2973
2974 static const char *mlx5e_vport_stats_desc[] = {
2975         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2976 };
2977
2978 static const char *mlx5e_pport_stats_desc[] = {
2979         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2980 };
2981
2982 static void
2983 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2984 {
2985         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2986         sx_init(&priv->state_lock, "mlx5state");
2987         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2988         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2989 }
2990
2991 static void
2992 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2993 {
2994         mtx_destroy(&priv->async_events_mtx);
2995         sx_destroy(&priv->state_lock);
2996 }
2997
2998 static int
2999 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3000 {
3001         /*
3002          * %d.%d%.d the string format.
3003          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3004          * We need at most 5 chars to store that.
3005          * It also has: two "." and NULL at the end, which means we need 18
3006          * (5*3 + 3) chars at most.
3007          */
3008         char fw[18];
3009         struct mlx5e_priv *priv = arg1;
3010         int error;
3011
3012         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3013             fw_rev_sub(priv->mdev));
3014         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3015         return (error);
3016 }
3017
3018 u8
3019 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev)
3020 {
3021         u8 min_inline_mode;
3022
3023         min_inline_mode = MLX5_INLINE_MODE_L2;
3024         mlx5_query_min_inline(mdev, &min_inline_mode);
3025         if (min_inline_mode == MLX5_INLINE_MODE_NONE &&
3026             !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3027                 min_inline_mode = MLX5_INLINE_MODE_L2;
3028
3029         return (min_inline_mode);
3030 }
3031
3032 static void
3033 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3034 {
3035         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3036             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3037             sysctl_firmware, "A", "HCA firmware version");
3038
3039         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3040             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3041             "Board ID");
3042 }
3043
3044 static void
3045 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3046 {
3047 #if (__FreeBSD_version < 1100000)
3048         char path[64];
3049
3050 #endif
3051         /* Only receiving pauseframes is enabled by default */
3052         priv->params.tx_pauseframe_control = 0;
3053         priv->params.rx_pauseframe_control = 1;
3054
3055 #if (__FreeBSD_version < 1100000)
3056         /* compute path for sysctl */
3057         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3058             device_get_unit(priv->mdev->pdev->dev.bsddev));
3059
3060         /* try to fetch tunable, if any */
3061         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3062
3063         /* compute path for sysctl */
3064         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3065             device_get_unit(priv->mdev->pdev->dev.bsddev));
3066
3067         /* try to fetch tunable, if any */
3068         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3069 #endif
3070
3071         /* register pausframe SYSCTLs */
3072         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3073             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3074             &priv->params.tx_pauseframe_control, 0,
3075             "Set to enable TX pause frames. Clear to disable.");
3076
3077         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3078             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3079             &priv->params.rx_pauseframe_control, 0,
3080             "Set to enable RX pause frames. Clear to disable.");
3081
3082         /* range check */
3083         priv->params.tx_pauseframe_control =
3084             priv->params.tx_pauseframe_control ? 1 : 0;
3085         priv->params.rx_pauseframe_control =
3086             priv->params.rx_pauseframe_control ? 1 : 0;
3087
3088         /* update firmware */
3089         mlx5_set_port_pause(priv->mdev, 1,
3090             priv->params.rx_pauseframe_control,
3091             priv->params.tx_pauseframe_control);
3092 }
3093
3094 static void *
3095 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3096 {
3097         static volatile int mlx5_en_unit;
3098         struct ifnet *ifp;
3099         struct mlx5e_priv *priv;
3100         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3101         struct sysctl_oid_list *child;
3102         int ncv = mdev->priv.eq_table.num_comp_vectors;
3103         char unit[16];
3104         int err;
3105         int i;
3106         u32 eth_proto_cap;
3107
3108         if (mlx5e_check_required_hca_cap(mdev)) {
3109                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3110                 return (NULL);
3111         }
3112         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3113         mlx5e_priv_mtx_init(priv);
3114
3115         ifp = priv->ifp = if_alloc(IFT_ETHER);
3116         if (ifp == NULL) {
3117                 mlx5_core_err(mdev, "if_alloc() failed\n");
3118                 goto err_free_priv;
3119         }
3120         ifp->if_softc = priv;
3121         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
3122         ifp->if_mtu = ETHERMTU;
3123         ifp->if_init = mlx5e_open;
3124         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3125         ifp->if_ioctl = mlx5e_ioctl;
3126         ifp->if_transmit = mlx5e_xmit;
3127         ifp->if_qflush = if_qflush;
3128 #if (__FreeBSD_version >= 1100000)
3129         ifp->if_get_counter = mlx5e_get_counter;
3130 #endif
3131         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3132         /*
3133          * Set driver features
3134          */
3135         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3136         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3137         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3138         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3139         ifp->if_capabilities |= IFCAP_LRO;
3140         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3141         ifp->if_capabilities |= IFCAP_HWSTATS;
3142
3143         /* set TSO limits so that we don't have to drop TX packets */
3144         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3145         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3146         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3147
3148         ifp->if_capenable = ifp->if_capabilities;
3149         ifp->if_hwassist = 0;
3150         if (ifp->if_capenable & IFCAP_TSO)
3151                 ifp->if_hwassist |= CSUM_TSO;
3152         if (ifp->if_capenable & IFCAP_TXCSUM)
3153                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3154         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3155                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3156
3157         /* ifnet sysctl tree */
3158         sysctl_ctx_init(&priv->sysctl_ctx);
3159         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3160             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3161         if (priv->sysctl_ifnet == NULL) {
3162                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3163                 goto err_free_sysctl;
3164         }
3165         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3166         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3167             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3168         if (priv->sysctl_ifnet == NULL) {
3169                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3170                 goto err_free_sysctl;
3171         }
3172
3173         /* HW sysctl tree */
3174         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3175         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3176             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3177         if (priv->sysctl_hw == NULL) {
3178                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3179                 goto err_free_sysctl;
3180         }
3181         mlx5e_build_ifp_priv(mdev, priv, ncv);
3182         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3183         if (err) {
3184                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3185                     __func__, err);
3186                 goto err_free_sysctl;
3187         }
3188         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3189         if (err) {
3190                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3191                     __func__, err);
3192                 goto err_unmap_free_uar;
3193         }
3194         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3195         if (err) {
3196                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3197                     __func__, err);
3198                 goto err_dealloc_pd;
3199         }
3200         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3201         if (err) {
3202                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3203                     __func__, err);
3204                 goto err_dealloc_transport_domain;
3205         }
3206         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3207
3208         /* check if we should generate a random MAC address */
3209         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3210             is_zero_ether_addr(dev_addr)) {
3211                 random_ether_addr(dev_addr);
3212                 if_printf(ifp, "Assigned random MAC address\n");
3213         }
3214
3215         /* set default MTU */
3216         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3217
3218         /* Set desc */
3219         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3220
3221         /* Set default media status */
3222         priv->media_status_last = IFM_AVALID;
3223         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3224             IFM_ETH_RXPAUSE | IFM_FDX;
3225
3226         /* setup default pauseframes configuration */
3227         mlx5e_setup_pauseframes(priv);
3228
3229         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3230         if (err) {
3231                 eth_proto_cap = 0;
3232                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3233                     __func__, err);
3234         }
3235
3236         /* Setup supported medias */
3237         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3238             mlx5e_media_change, mlx5e_media_status);
3239
3240         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3241                 if (mlx5e_mode_table[i].baudrate == 0)
3242                         continue;
3243                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3244                         ifmedia_add(&priv->media,
3245                             mlx5e_mode_table[i].subtype |
3246                             IFM_ETHER, 0, NULL);
3247                         ifmedia_add(&priv->media,
3248                             mlx5e_mode_table[i].subtype |
3249                             IFM_ETHER | IFM_FDX |
3250                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3251                 }
3252         }
3253
3254         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3255         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3256             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3257
3258         /* Set autoselect by default */
3259         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3260             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3261         ether_ifattach(ifp, dev_addr);
3262
3263         /* Register for VLAN events */
3264         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3265             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3266         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3267             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3268
3269         /* Link is down by default */
3270         if_link_state_change(ifp, LINK_STATE_DOWN);
3271
3272         mlx5e_enable_async_events(priv);
3273
3274         mlx5e_add_hw_stats(priv);
3275
3276         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3277             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3278             priv->stats.vport.arg);
3279
3280         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3281             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3282             priv->stats.pport.arg);
3283
3284         mlx5e_create_ethtool(priv);
3285
3286         mtx_lock(&priv->async_events_mtx);
3287         mlx5e_update_stats(priv);
3288         mtx_unlock(&priv->async_events_mtx);
3289
3290         return (priv);
3291
3292 err_dealloc_transport_domain:
3293         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3294
3295 err_dealloc_pd:
3296         mlx5_core_dealloc_pd(mdev, priv->pdn);
3297
3298 err_unmap_free_uar:
3299         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3300
3301 err_free_sysctl:
3302         sysctl_ctx_free(&priv->sysctl_ctx);
3303
3304         if_free(ifp);
3305
3306 err_free_priv:
3307         mlx5e_priv_mtx_destroy(priv);
3308         free(priv, M_MLX5EN);
3309         return (NULL);
3310 }
3311
3312 static void
3313 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3314 {
3315         struct mlx5e_priv *priv = vpriv;
3316         struct ifnet *ifp = priv->ifp;
3317
3318         /* don't allow more IOCTLs */
3319         priv->gone = 1;
3320
3321         /*
3322          * Clear the device description to avoid use after free,
3323          * because the bsddev is not destroyed when this module is
3324          * unloaded:
3325          */
3326         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3327
3328         /* XXX wait a bit to allow IOCTL handlers to complete */
3329         pause("W", hz);
3330
3331         /* stop watchdog timer */
3332         callout_drain(&priv->watchdog);
3333
3334         if (priv->vlan_attach != NULL)
3335                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3336         if (priv->vlan_detach != NULL)
3337                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3338
3339         /* make sure device gets closed */
3340         PRIV_LOCK(priv);
3341         mlx5e_close_locked(ifp);
3342         PRIV_UNLOCK(priv);
3343
3344         /* unregister device */
3345         ifmedia_removeall(&priv->media);
3346         ether_ifdetach(ifp);
3347         if_free(ifp);
3348
3349         /* destroy all remaining sysctl nodes */
3350         if (priv->sysctl_debug)
3351                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3352         sysctl_ctx_free(&priv->stats.vport.ctx);
3353         sysctl_ctx_free(&priv->stats.pport.ctx);
3354         sysctl_ctx_free(&priv->sysctl_ctx);
3355
3356         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3357         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3358         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3359         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3360         mlx5e_disable_async_events(priv);
3361         flush_scheduled_work();
3362         mlx5e_priv_mtx_destroy(priv);
3363         free(priv, M_MLX5EN);
3364 }
3365
3366 static void *
3367 mlx5e_get_ifp(void *vpriv)
3368 {
3369         struct mlx5e_priv *priv = vpriv;
3370
3371         return (priv->ifp);
3372 }
3373
3374 static struct mlx5_interface mlx5e_interface = {
3375         .add = mlx5e_create_ifp,
3376         .remove = mlx5e_destroy_ifp,
3377         .event = mlx5e_async_event,
3378         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3379         .get_dev = mlx5e_get_ifp,
3380 };
3381
3382 void
3383 mlx5e_init(void)
3384 {
3385         mlx5_register_interface(&mlx5e_interface);
3386 }
3387
3388 void
3389 mlx5e_cleanup(void)
3390 {
3391         mlx5_unregister_interface(&mlx5e_interface);
3392 }
3393
3394 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3395 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3396
3397 #if (__FreeBSD_version >= 1100000)
3398 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3399 #endif
3400 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3401 MODULE_VERSION(mlx5en, 1);