2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <machine/atomic.h>
32 mlx5e_do_send_cqe(struct mlx5e_sq *sq)
35 /* interleave the CQEs */
36 if (sq->cev_counter >= sq->cev_factor) {
44 mlx5e_send_nop(struct mlx5e_sq *sq, u32 ds_cnt)
46 u16 pi = sq->pc & sq->wq.sz_m1;
47 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
49 memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));
51 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
52 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
53 if (mlx5e_do_send_cqe(sq))
54 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
56 wqe->ctrl.fm_ce_se = 0;
58 /* Copy data for doorbell */
59 memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));
61 sq->mbuf[pi].mbuf = NULL;
62 sq->mbuf[pi].num_bytes = 0;
63 sq->mbuf[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
64 sq->pc += sq->mbuf[pi].num_wqebbs;
67 #if (__FreeBSD_version >= 1100000)
68 static uint32_t mlx5e_hash_value;
71 mlx5e_hash_init(void *arg)
73 mlx5e_hash_value = m_ether_tcpip_hash_init();
76 /* Make kernel call mlx5e_hash_init after the random stack finished initializing */
77 SYSINIT(mlx5e_hash_init, SI_SUB_RANDOM, SI_ORDER_ANY, &mlx5e_hash_init, NULL);
80 static struct mlx5e_sq *
81 mlx5e_select_queue(struct ifnet *ifp, struct mbuf *mb)
83 struct mlx5e_priv *priv = ifp->if_softc;
84 struct mlx5e_channel * volatile *ppch;
85 struct mlx5e_channel *pch;
91 /* check if channels are successfully opened */
92 if (unlikely(ppch == NULL))
95 /* obtain VLAN information if present */
96 if (mb->m_flags & M_VLANTAG) {
97 tc = (mb->m_pkthdr.ether_vtag >> 13);
98 if (tc >= priv->num_tc)
99 tc = priv->default_vlan_prio;
101 tc = priv->default_vlan_prio;
104 ch = priv->params.num_channels;
106 /* check if flowid is set */
107 if (M_HASHTYPE_GET(mb) != M_HASHTYPE_NONE) {
111 if (rss_hash2bucket(mb->m_pkthdr.flowid,
112 M_HASHTYPE_GET(mb), &temp) == 0)
116 ch = (mb->m_pkthdr.flowid % 128) % ch;
118 #if (__FreeBSD_version >= 1100000)
119 ch = m_ether_tcpip_hash(MBUF_HASHFLAG_L3 |
120 MBUF_HASHFLAG_L4, mb, mlx5e_hash_value) % ch;
123 * m_ether_tcpip_hash not present in stable, so just
124 * throw unhashed mbufs on queue 0
130 /* check if channel is allocated and not stopped */
132 if (likely(pch != NULL && pch->sq[tc].stopped == 0))
133 return (&pch->sq[tc]);
138 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq, struct mbuf *mb)
141 switch(sq->min_inline_mode) {
142 case MLX5_INLINE_MODE_NONE:
144 * When inline mode is NONE, we do not need to copy
145 * headers into WQEs, except when vlan tag framing is
146 * requested. Hardware might offload vlan tagging on
147 * transmit. This is a separate capability, which is
148 * known to be disabled on ConnectX-5 due to a hardware
149 * bug RM 931383. If vlan_inline_cap is not present and
150 * the packet has vlan tag, fall back to inlining.
152 if ((mb->m_flags & M_VLANTAG) != 0 &&
153 sq->vlan_inline_cap == 0)
156 case MLX5_INLINE_MODE_L2:
158 * Due to hardware limitations, when trust mode is
159 * DSCP, the hardware may request MLX5_INLINE_MODE_L2
160 * while it really needs all L2 headers and the 4 first
161 * bytes of the IP header (which include the
162 * TOS/traffic-class).
164 * To avoid doing a firmware command for querying the
165 * trust state and parsing the mbuf for doing
166 * unnecessary checks (VLAN/eth_type) in the fast path,
167 * we are going for the worth case (22 Bytes) if
168 * the mb->m_pkthdr.len allows it.
170 if (mb->m_pkthdr.len > ETHER_HDR_LEN +
171 ETHER_VLAN_ENCAP_LEN + 4)
172 return (MIN(sq->max_inline, ETHER_HDR_LEN +
173 ETHER_VLAN_ENCAP_LEN + 4));
176 return (MIN(sq->max_inline, mb->m_pkthdr.len));
180 mlx5e_get_header_size(struct mbuf *mb)
182 struct ether_vlan_header *eh;
185 int ip_hlen, tcp_hlen;
190 eh = mtod(mb, struct ether_vlan_header *);
191 if (mb->m_len < ETHER_HDR_LEN)
193 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
194 eth_type = ntohs(eh->evl_proto);
195 eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
197 eth_type = ntohs(eh->evl_encap_proto);
198 eth_hdr_len = ETHER_HDR_LEN;
200 if (mb->m_len < eth_hdr_len)
204 ip = (struct ip *)(mb->m_data + eth_hdr_len);
205 if (mb->m_len < eth_hdr_len + sizeof(*ip))
207 if (ip->ip_p != IPPROTO_TCP)
209 ip_hlen = ip->ip_hl << 2;
210 eth_hdr_len += ip_hlen;
213 ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len);
214 if (mb->m_len < eth_hdr_len + sizeof(*ip6))
216 if (ip6->ip6_nxt != IPPROTO_TCP)
218 eth_hdr_len += sizeof(*ip6);
223 if (mb->m_len < eth_hdr_len + sizeof(*th))
225 th = (struct tcphdr *)(mb->m_data + eth_hdr_len);
226 tcp_hlen = th->th_off << 2;
227 eth_hdr_len += tcp_hlen;
228 if (mb->m_len < eth_hdr_len)
230 return (eth_hdr_len);
234 * The return value is not going back to the stack because of
238 mlx5e_sq_xmit(struct mlx5e_sq *sq, struct mbuf **mbp)
240 bus_dma_segment_t segs[MLX5E_MAX_TX_MBUF_FRAGS];
241 struct mlx5_wqe_data_seg *dseg;
242 struct mlx5e_tx_wqe *wqe;
247 struct mbuf *mb = *mbp;
254 * Return ENOBUFS if the queue is full, this may trigger reinsertion
255 * of the mbuf into the drbr (see mlx5e_xmit_locked)
257 if (unlikely(!mlx5e_sq_has_room_for(sq, 2 * MLX5_SEND_WQE_MAX_WQEBBS))) {
262 /* Align SQ edge with NOPs to avoid WQE wrap around */
263 pi = ((~sq->pc) & sq->wq.sz_m1);
264 if (pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1)) {
265 /* Send one multi NOP message instead of many */
266 mlx5e_send_nop(sq, (pi + 1) * MLX5_SEND_WQEBB_NUM_DS);
267 pi = ((~sq->pc) & sq->wq.sz_m1);
268 if (pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1)) {
274 /* Setup local variables */
275 pi = sq->pc & sq->wq.sz_m1;
276 wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
279 memset(wqe, 0, sizeof(*wqe));
281 /* Send a copy of the frame to the BPF listener, if any */
282 if (ifp != NULL && ifp->if_bpf != NULL)
283 ETHER_BPF_MTAP(ifp, mb);
285 if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) {
286 wqe->eth.cs_flags |= MLX5_ETH_WQE_L3_CSUM;
288 if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) {
289 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_CSUM;
291 if (wqe->eth.cs_flags == 0) {
292 sq->stats.csum_offload_none++;
294 if (mb->m_pkthdr.csum_flags & CSUM_TSO) {
296 u32 mss = mb->m_pkthdr.tso_segsz;
299 wqe->eth.mss = cpu_to_be16(mss);
300 opcode = MLX5_OPCODE_LSO;
301 ihs = mlx5e_get_header_size(mb);
302 payload_len = mb->m_pkthdr.len - ihs;
303 if (payload_len == 0)
306 num_pkts = DIV_ROUND_UP(payload_len, mss);
307 sq->mbuf[pi].num_bytes = payload_len + (num_pkts * ihs);
309 sq->stats.tso_packets++;
310 sq->stats.tso_bytes += payload_len;
312 opcode = MLX5_OPCODE_SEND;
313 ihs = mlx5e_get_inline_hdr_size(sq, mb);
314 sq->mbuf[pi].num_bytes = max_t (unsigned int,
315 mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
318 if ((mb->m_flags & M_VLANTAG) != 0) {
319 wqe->eth.vlan_cmd = htons(0x8000); /* bit 0 CVLAN */
320 wqe->eth.vlan_hdr = htons(mb->m_pkthdr.ether_vtag);
322 wqe->eth.inline_hdr_sz = 0;
325 if ((mb->m_flags & M_VLANTAG) != 0) {
326 struct ether_vlan_header *eh = (struct ether_vlan_header
327 *)wqe->eth.inline_hdr_start;
330 if (ihs > (MLX5E_MAX_TX_INLINE - ETHER_VLAN_ENCAP_LEN))
331 ihs = (MLX5E_MAX_TX_INLINE -
332 ETHER_VLAN_ENCAP_LEN);
333 else if (ihs < ETHER_HDR_LEN) {
337 m_copydata(mb, 0, ETHER_HDR_LEN, (caddr_t)eh);
338 m_adj(mb, ETHER_HDR_LEN);
339 /* Insert 4 bytes VLAN tag into data stream */
340 eh->evl_proto = eh->evl_encap_proto;
341 eh->evl_encap_proto = htons(ETHERTYPE_VLAN);
342 eh->evl_tag = htons(mb->m_pkthdr.ether_vtag);
343 /* Copy rest of header data, if any */
344 m_copydata(mb, 0, ihs - ETHER_HDR_LEN, (caddr_t)(eh +
346 m_adj(mb, ihs - ETHER_HDR_LEN);
347 /* Extend header by 4 bytes */
348 ihs += ETHER_VLAN_ENCAP_LEN;
350 m_copydata(mb, 0, ihs, wqe->eth.inline_hdr_start);
353 wqe->eth.inline_hdr_sz = cpu_to_be16(ihs);
356 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
357 if (ihs > sizeof(wqe->eth.inline_hdr_start)) {
358 ds_cnt += DIV_ROUND_UP(ihs - sizeof(wqe->eth.inline_hdr_start),
361 dseg = ((struct mlx5_wqe_data_seg *)&wqe->ctrl) + ds_cnt;
363 /* Trim off empty mbufs */
364 while (mb->m_len == 0) {
366 /* Check if all data has been inlined */
371 err = bus_dmamap_load_mbuf_sg(sq->dma_tag, sq->mbuf[pi].dma_map,
372 mb, segs, &nsegs, BUS_DMA_NOWAIT);
375 * Update *mbp before defrag in case it was trimmed in the
379 /* Update statistics */
380 sq->stats.defragged++;
381 /* Too many mbuf fragments */
382 mb = m_defrag(*mbp, M_NOWAIT);
388 err = bus_dmamap_load_mbuf_sg(sq->dma_tag, sq->mbuf[pi].dma_map,
389 mb, segs, &nsegs, BUS_DMA_NOWAIT);
395 for (x = 0; x != nsegs; x++) {
396 if (segs[x].ds_len == 0)
398 dseg->addr = cpu_to_be64((uint64_t)segs[x].ds_addr);
399 dseg->lkey = sq->mkey_be;
400 dseg->byte_count = cpu_to_be32((uint32_t)segs[x].ds_len);
404 ds_cnt = (dseg - ((struct mlx5_wqe_data_seg *)&wqe->ctrl));
406 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
407 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
408 if (mlx5e_do_send_cqe(sq))
409 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
411 wqe->ctrl.fm_ce_se = 0;
413 /* Copy data for doorbell */
414 memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));
416 /* Store pointer to mbuf */
417 sq->mbuf[pi].mbuf = mb;
418 sq->mbuf[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
419 sq->pc += sq->mbuf[pi].num_wqebbs;
421 /* Make sure all mbuf data is written to RAM */
423 bus_dmamap_sync(sq->dma_tag, sq->mbuf[pi].dma_map, BUS_DMASYNC_PREWRITE);
426 *mbp = NULL; /* safety clear */
437 mlx5e_poll_tx_cq(struct mlx5e_sq *sq, int budget)
442 * sq->cc must be updated only after mlx5_cqwq_update_db_record(),
443 * otherwise a cq overrun may occur
448 struct mlx5_cqe64 *cqe;
453 cqe = mlx5e_get_cqe(&sq->cq);
457 mlx5_cqwq_pop(&sq->cq.wq);
459 /* update budget according to the event factor */
460 budget -= sq->cev_factor;
462 for (x = 0; x != sq->cev_factor; x++) {
463 ci = sqcc & sq->wq.sz_m1;
464 mb = sq->mbuf[ci].mbuf;
465 sq->mbuf[ci].mbuf = NULL; /* Safety clear */
468 if (sq->mbuf[ci].num_bytes == 0) {
473 bus_dmamap_sync(sq->dma_tag, sq->mbuf[ci].dma_map,
474 BUS_DMASYNC_POSTWRITE);
475 bus_dmamap_unload(sq->dma_tag, sq->mbuf[ci].dma_map);
477 /* Free transmitted mbuf */
480 sqcc += sq->mbuf[ci].num_wqebbs;
484 mlx5_cqwq_update_db_record(&sq->cq.wq);
486 /* Ensure cq space is freed before enabling more cqes */
491 if (sq->sq_tq != NULL &&
492 atomic_cmpset_int(&sq->queue_state, MLX5E_SQ_FULL, MLX5E_SQ_READY))
493 taskqueue_enqueue(sq->sq_tq, &sq->sq_task);
497 mlx5e_xmit_locked(struct ifnet *ifp, struct mlx5e_sq *sq, struct mbuf *mb)
502 if (likely(mb != NULL)) {
504 * If we can't insert mbuf into drbr, try to xmit anyway.
505 * We keep the error we got so we could return that after xmit.
507 err = drbr_enqueue(ifp, sq->br, mb);
511 * Check if the network interface is closed or if the SQ is
514 if (unlikely((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
518 /* Process the queue */
519 while ((next = drbr_peek(ifp, sq->br)) != NULL) {
520 if (mlx5e_sq_xmit(sq, &next) != 0) {
522 drbr_putback(ifp, sq->br, next);
523 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_FULL);
527 drbr_advance(ifp, sq->br);
529 /* Check if we need to write the doorbell */
530 if (likely(sq->doorbell.d64 != 0)) {
531 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
532 sq->doorbell.d64 = 0;
535 * Check if we need to start the event timer which flushes the
536 * transmit ring on timeout:
538 if (unlikely(sq->cev_next_state == MLX5E_CEV_STATE_INITIAL &&
539 sq->cev_factor != 1)) {
540 /* start the timer */
541 mlx5e_sq_cev_timeout(sq);
543 /* don't send NOPs yet */
544 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
550 mlx5e_xmit_locked_no_br(struct ifnet *ifp, struct mlx5e_sq *sq, struct mbuf *mb)
554 if (unlikely((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
561 if (mlx5e_sq_xmit(sq, &mb) != 0) {
562 /* NOTE: m_freem() is NULL safe */
567 /* Check if we need to write the doorbell */
568 if (likely(sq->doorbell.d64 != 0)) {
569 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
570 sq->doorbell.d64 = 0;
574 * Check if we need to start the event timer which flushes the
575 * transmit ring on timeout:
577 if (unlikely(sq->cev_next_state == MLX5E_CEV_STATE_INITIAL &&
578 sq->cev_factor != 1)) {
579 /* start the timer */
580 mlx5e_sq_cev_timeout(sq);
582 /* don't send NOPs yet */
583 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
589 mlx5e_xmit(struct ifnet *ifp, struct mbuf *mb)
594 sq = mlx5e_select_queue(ifp, mb);
595 if (unlikely(sq == NULL)) {
596 /* Invalid send queue */
601 if (unlikely(sq->br == NULL)) {
602 /* rate limited traffic */
604 ret = mlx5e_xmit_locked_no_br(ifp, sq, mb);
605 mtx_unlock(&sq->lock);
606 } else if (mtx_trylock(&sq->lock)) {
607 ret = mlx5e_xmit_locked(ifp, sq, mb);
608 mtx_unlock(&sq->lock);
610 ret = drbr_enqueue(ifp, sq->br, mb);
611 taskqueue_enqueue(sq->sq_tq, &sq->sq_task);
618 mlx5e_tx_cq_comp(struct mlx5_core_cq *mcq)
620 struct mlx5e_sq *sq = container_of(mcq, struct mlx5e_sq, cq.mcq);
622 mtx_lock(&sq->comp_lock);
623 mlx5e_poll_tx_cq(sq, MLX5E_BUDGET_MAX);
624 mlx5e_cq_arm(&sq->cq, MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock));
625 mtx_unlock(&sq->comp_lock);
629 mlx5e_tx_que(void *context, int pending)
631 struct mlx5e_sq *sq = context;
632 struct ifnet *ifp = sq->ifp;
634 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
636 if (!drbr_empty(ifp, sq->br))
637 mlx5e_xmit_locked(ifp, sq, NULL);
638 mtx_unlock(&sq->lock);