2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
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9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <machine/atomic.h>
32 mlx5e_do_send_cqe(struct mlx5e_sq *sq)
35 /* interleave the CQEs */
36 if (sq->cev_counter >= sq->cev_factor) {
44 mlx5e_send_nop(struct mlx5e_sq *sq, u32 ds_cnt)
46 u16 pi = sq->pc & sq->wq.sz_m1;
47 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
49 memset(&wqe->ctrl, 0, sizeof(wqe->ctrl));
51 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
52 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
53 if (mlx5e_do_send_cqe(sq))
54 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
56 wqe->ctrl.fm_ce_se = 0;
58 /* Copy data for doorbell */
59 memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));
61 sq->mbuf[pi].mbuf = NULL;
62 sq->mbuf[pi].num_bytes = 0;
63 sq->mbuf[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
64 sq->pc += sq->mbuf[pi].num_wqebbs;
67 #if (__FreeBSD_version >= 1100000)
68 static uint32_t mlx5e_hash_value;
71 mlx5e_hash_init(void *arg)
73 mlx5e_hash_value = m_ether_tcpip_hash_init();
76 /* Make kernel call mlx5e_hash_init after the random stack finished initializing */
77 SYSINIT(mlx5e_hash_init, SI_SUB_RANDOM, SI_ORDER_ANY, &mlx5e_hash_init, NULL);
80 static struct mlx5e_sq *
81 mlx5e_select_queue(struct ifnet *ifp, struct mbuf *mb)
83 struct mlx5e_priv *priv = ifp->if_softc;
87 /* check if channels are successfully opened */
88 if (unlikely(priv->channel == NULL))
91 /* obtain VLAN information if present */
92 if (mb->m_flags & M_VLANTAG) {
93 tc = (mb->m_pkthdr.ether_vtag >> 13);
94 if (tc >= priv->num_tc)
95 tc = priv->default_vlan_prio;
97 tc = priv->default_vlan_prio;
100 ch = priv->params.num_channels;
102 /* check if flowid is set */
103 if (M_HASHTYPE_GET(mb) != M_HASHTYPE_NONE) {
107 if (rss_hash2bucket(mb->m_pkthdr.flowid,
108 M_HASHTYPE_GET(mb), &temp) == 0)
112 ch = (mb->m_pkthdr.flowid % 128) % ch;
114 #if (__FreeBSD_version >= 1100000)
115 ch = m_ether_tcpip_hash(MBUF_HASHFLAG_L3 |
116 MBUF_HASHFLAG_L4, mb, mlx5e_hash_value) % ch;
119 * m_ether_tcpip_hash not present in stable, so just
120 * throw unhashed mbufs on queue 0
126 /* check if channel is allocated */
127 if (unlikely(priv->channel[ch] == NULL))
130 return (&priv->channel[ch]->sq[tc]);
134 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq, struct mbuf *mb)
136 return (MIN(MLX5E_MAX_TX_INLINE, mb->m_len));
140 mlx5e_get_header_size(struct mbuf *mb)
142 struct ether_vlan_header *eh;
145 int ip_hlen, tcp_hlen;
150 eh = mtod(mb, struct ether_vlan_header *);
151 if (mb->m_len < ETHER_HDR_LEN)
153 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
154 eth_type = ntohs(eh->evl_proto);
155 eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
157 eth_type = ntohs(eh->evl_encap_proto);
158 eth_hdr_len = ETHER_HDR_LEN;
160 if (mb->m_len < eth_hdr_len)
164 ip = (struct ip *)(mb->m_data + eth_hdr_len);
165 if (mb->m_len < eth_hdr_len + sizeof(*ip))
167 if (ip->ip_p != IPPROTO_TCP)
169 ip_hlen = ip->ip_hl << 2;
170 eth_hdr_len += ip_hlen;
173 ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len);
174 if (mb->m_len < eth_hdr_len + sizeof(*ip6))
176 if (ip6->ip6_nxt != IPPROTO_TCP)
178 eth_hdr_len += sizeof(*ip6);
183 if (mb->m_len < eth_hdr_len + sizeof(*th))
185 th = (struct tcphdr *)(mb->m_data + eth_hdr_len);
186 tcp_hlen = th->th_off << 2;
187 eth_hdr_len += tcp_hlen;
188 if (mb->m_len < eth_hdr_len)
190 return (eth_hdr_len);
194 * The return value is not going back to the stack because of
198 mlx5e_sq_xmit(struct mlx5e_sq *sq, struct mbuf **mbp)
200 bus_dma_segment_t segs[MLX5E_MAX_TX_MBUF_FRAGS];
201 struct mlx5_wqe_data_seg *dseg;
202 struct mlx5e_tx_wqe *wqe;
207 struct mbuf *mb = *mbp;
214 * Return ENOBUFS if the queue is full, this may trigger reinsertion
215 * of the mbuf into the drbr (see mlx5e_xmit_locked)
217 if (unlikely(!mlx5e_sq_has_room_for(sq, 2 * MLX5_SEND_WQE_MAX_WQEBBS))) {
221 /* Align SQ edge with NOPs to avoid WQE wrap around */
222 pi = ((~sq->pc) & sq->wq.sz_m1);
223 if (pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1)) {
224 /* Send one multi NOP message instead of many */
225 mlx5e_send_nop(sq, (pi + 1) * MLX5_SEND_WQEBB_NUM_DS);
226 pi = ((~sq->pc) & sq->wq.sz_m1);
227 if (pi < (MLX5_SEND_WQE_MAX_WQEBBS - 1))
231 /* Setup local variables */
232 pi = sq->pc & sq->wq.sz_m1;
233 wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi);
236 memset(wqe, 0, sizeof(*wqe));
238 /* Send a copy of the frame to the BPF listener, if any */
239 if (ifp != NULL && ifp->if_bpf != NULL)
240 ETHER_BPF_MTAP(ifp, mb);
242 if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)) {
243 wqe->eth.cs_flags |= MLX5_ETH_WQE_L3_CSUM;
245 if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO)) {
246 wqe->eth.cs_flags |= MLX5_ETH_WQE_L4_CSUM;
248 if (wqe->eth.cs_flags == 0) {
249 sq->stats.csum_offload_none++;
251 if (mb->m_pkthdr.csum_flags & CSUM_TSO) {
253 u32 mss = mb->m_pkthdr.tso_segsz;
256 wqe->eth.mss = cpu_to_be16(mss);
257 opcode = MLX5_OPCODE_LSO;
258 ihs = mlx5e_get_header_size(mb);
259 payload_len = mb->m_pkthdr.len - ihs;
260 if (payload_len == 0)
263 num_pkts = DIV_ROUND_UP(payload_len, mss);
264 sq->mbuf[pi].num_bytes = payload_len + (num_pkts * ihs);
266 sq->stats.tso_packets++;
267 sq->stats.tso_bytes += payload_len;
269 opcode = MLX5_OPCODE_SEND;
270 ihs = mlx5e_get_inline_hdr_size(sq, mb);
271 sq->mbuf[pi].num_bytes = max_t (unsigned int,
272 mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
274 if (mb->m_flags & M_VLANTAG) {
275 struct ether_vlan_header *eh =
276 (struct ether_vlan_header *)wqe->eth.inline_hdr_start;
279 if (ihs > (MLX5E_MAX_TX_INLINE - ETHER_VLAN_ENCAP_LEN))
280 ihs = (MLX5E_MAX_TX_INLINE - ETHER_VLAN_ENCAP_LEN);
281 else if (ihs < ETHER_HDR_LEN) {
285 m_copydata(mb, 0, ETHER_HDR_LEN, (caddr_t)eh);
286 m_adj(mb, ETHER_HDR_LEN);
287 /* Insert 4 bytes VLAN tag into data stream */
288 eh->evl_proto = eh->evl_encap_proto;
289 eh->evl_encap_proto = htons(ETHERTYPE_VLAN);
290 eh->evl_tag = htons(mb->m_pkthdr.ether_vtag);
291 /* Copy rest of header data, if any */
292 m_copydata(mb, 0, ihs - ETHER_HDR_LEN, (caddr_t)(eh + 1));
293 m_adj(mb, ihs - ETHER_HDR_LEN);
294 /* Extend header by 4 bytes */
295 ihs += ETHER_VLAN_ENCAP_LEN;
297 m_copydata(mb, 0, ihs, wqe->eth.inline_hdr_start);
301 wqe->eth.inline_hdr_sz = cpu_to_be16(ihs);
303 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
304 if (likely(ihs > sizeof(wqe->eth.inline_hdr_start))) {
305 ds_cnt += DIV_ROUND_UP(ihs - sizeof(wqe->eth.inline_hdr_start),
308 dseg = ((struct mlx5_wqe_data_seg *)&wqe->ctrl) + ds_cnt;
310 /* Trim off empty mbufs */
311 while (mb->m_len == 0) {
313 /* Check if all data has been inlined */
318 err = bus_dmamap_load_mbuf_sg(sq->dma_tag, sq->mbuf[pi].dma_map,
319 mb, segs, &nsegs, BUS_DMA_NOWAIT);
322 * Update *mbp before defrag in case it was trimmed in the
326 /* Update statistics */
327 sq->stats.defragged++;
328 /* Too many mbuf fragments */
329 mb = m_defrag(*mbp, M_NOWAIT);
335 err = bus_dmamap_load_mbuf_sg(sq->dma_tag, sq->mbuf[pi].dma_map,
336 mb, segs, &nsegs, BUS_DMA_NOWAIT);
342 for (x = 0; x != nsegs; x++) {
343 if (segs[x].ds_len == 0)
345 dseg->addr = cpu_to_be64((uint64_t)segs[x].ds_addr);
346 dseg->lkey = sq->mkey_be;
347 dseg->byte_count = cpu_to_be32((uint32_t)segs[x].ds_len);
351 ds_cnt = (dseg - ((struct mlx5_wqe_data_seg *)&wqe->ctrl));
353 wqe->ctrl.opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
354 wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
355 if (mlx5e_do_send_cqe(sq))
356 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
358 wqe->ctrl.fm_ce_se = 0;
360 /* Copy data for doorbell */
361 memcpy(sq->doorbell.d32, &wqe->ctrl, sizeof(sq->doorbell.d32));
363 /* Store pointer to mbuf */
364 sq->mbuf[pi].mbuf = mb;
365 sq->mbuf[pi].num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
366 sq->pc += sq->mbuf[pi].num_wqebbs;
368 /* Make sure all mbuf data is written to RAM */
370 bus_dmamap_sync(sq->dma_tag, sq->mbuf[pi].dma_map, BUS_DMASYNC_PREWRITE);
373 *mbp = NULL; /* safety clear */
384 mlx5e_poll_tx_cq(struct mlx5e_sq *sq, int budget)
389 * sq->cc must be updated only after mlx5_cqwq_update_db_record(),
390 * otherwise a cq overrun may occur
395 struct mlx5_cqe64 *cqe;
400 cqe = mlx5e_get_cqe(&sq->cq);
404 mlx5_cqwq_pop(&sq->cq.wq);
406 /* update budget according to the event factor */
407 budget -= sq->cev_factor;
409 for (x = 0; x != sq->cev_factor; x++) {
410 ci = sqcc & sq->wq.sz_m1;
411 mb = sq->mbuf[ci].mbuf;
412 sq->mbuf[ci].mbuf = NULL; /* Safety clear */
415 if (sq->mbuf[ci].num_bytes == 0) {
420 bus_dmamap_sync(sq->dma_tag, sq->mbuf[ci].dma_map,
421 BUS_DMASYNC_POSTWRITE);
422 bus_dmamap_unload(sq->dma_tag, sq->mbuf[ci].dma_map);
424 /* Free transmitted mbuf */
427 sqcc += sq->mbuf[ci].num_wqebbs;
431 mlx5_cqwq_update_db_record(&sq->cq.wq);
433 /* Ensure cq space is freed before enabling more cqes */
438 if (atomic_cmpset_int(&sq->queue_state, MLX5E_SQ_FULL, MLX5E_SQ_READY))
439 taskqueue_enqueue(sq->sq_tq, &sq->sq_task);
443 mlx5e_xmit_locked(struct ifnet *ifp, struct mlx5e_sq *sq, struct mbuf *mb)
448 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
450 err = drbr_enqueue(ifp, sq->br, mb);
456 * If we can't insert mbuf into drbr, try to xmit anyway.
457 * We keep the error we got so we could return that after xmit.
459 err = drbr_enqueue(ifp, sq->br, mb);
461 /* Process the queue */
462 while ((next = drbr_peek(ifp, sq->br)) != NULL) {
463 if (mlx5e_sq_xmit(sq, &next) != 0) {
465 drbr_advance(ifp, sq->br);
467 drbr_putback(ifp, sq->br, next);
468 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_FULL);
472 drbr_advance(ifp, sq->br);
473 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
476 /* Check if we need to write the doorbell */
477 if (likely(sq->doorbell.d64 != 0)) {
478 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
479 sq->doorbell.d64 = 0;
482 * Check if we need to start the event timer which flushes the
483 * transmit ring on timeout:
485 if (unlikely(sq->cev_next_state == MLX5E_CEV_STATE_INITIAL &&
486 sq->cev_factor != 1)) {
487 /* start the timer */
488 mlx5e_sq_cev_timeout(sq);
490 /* don't send NOPs yet */
491 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
497 mlx5e_xmit(struct ifnet *ifp, struct mbuf *mb)
502 sq = mlx5e_select_queue(ifp, mb);
503 if (unlikely(sq == NULL)) {
504 /* Invalid send queue */
508 if (mtx_trylock(&sq->lock)) {
509 ret = mlx5e_xmit_locked(ifp, sq, mb);
510 mtx_unlock(&sq->lock);
512 ret = drbr_enqueue(ifp, sq->br, mb);
513 taskqueue_enqueue(sq->sq_tq, &sq->sq_task);
520 mlx5e_tx_cq_comp(struct mlx5_core_cq *mcq)
522 struct mlx5e_sq *sq = container_of(mcq, struct mlx5e_sq, cq.mcq);
524 mtx_lock(&sq->comp_lock);
525 mlx5e_poll_tx_cq(sq, MLX5E_BUDGET_MAX);
526 mlx5e_cq_arm(&sq->cq);
527 mtx_unlock(&sq->comp_lock);
531 mlx5e_tx_que(void *context, int pending)
533 struct mlx5e_sq *sq = context;
534 struct ifnet *ifp = sq->ifp;
536 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
538 if (!drbr_empty(ifp, sq->br))
539 mlx5e_xmit_locked(ifp, sq, NULL);
540 mtx_unlock(&sq->lock);