2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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28 #include <rdma/ib_mad.h>
29 #include <rdma/ib_smi.h>
30 #include <rdma/ib_pma.h>
32 #include <dev/mlx5/vport.h>
34 #define MAX_U32 0xffffffffULL
35 #define MAX_U16 0xffffUL
37 /* Counters should be saturate once they reach their maximum value */
38 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
39 if ((value) > MAX_U32) \
40 counter = cpu_to_be32(MAX_U32); \
42 counter = cpu_to_be32(value); \
45 /* Counters should be saturate once they reach their maximum value */
46 #define ASSIGN_16BIT_COUNTER(counter, value) do { \
47 if ((value) > MAX_U16) \
48 counter = cpu_to_be16(MAX_U16); \
50 counter = cpu_to_be16(value); \
54 MLX5_IB_VENDOR_CLASS1 = 0x9,
55 MLX5_IB_VENDOR_CLASS2 = 0xa
58 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
59 u8 port, struct ib_wc *in_wc, struct ib_grh *in_grh,
60 void *in_mad, void *response_mad)
64 /* Key check traps can't be generated unless we have in_wc to
65 * tell us where to send the trap.
67 if (ignore_mkey || !in_wc)
69 if (ignore_bkey || !in_wc)
72 return mlx5_core_mad_ifc(dev->mdev, in_mad, response_mad, op_modifier, port);
75 static int process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
76 struct ib_wc *in_wc, struct ib_grh *in_grh,
77 struct ib_mad *in_mad, struct ib_mad *out_mad)
82 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE);
84 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0)
85 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
87 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
88 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) {
89 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
90 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET &&
91 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS)
92 return IB_MAD_RESULT_SUCCESS;
94 /* Don't process SMInfo queries -- the SMA can't handle them.
96 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO)
97 return IB_MAD_RESULT_SUCCESS;
98 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT ||
99 in_mad->mad_hdr.mgmt_class == MLX5_IB_VENDOR_CLASS1 ||
100 in_mad->mad_hdr.mgmt_class == MLX5_IB_VENDOR_CLASS2 ||
101 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) {
102 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
103 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET)
104 return IB_MAD_RESULT_SUCCESS;
106 return IB_MAD_RESULT_SUCCESS;
109 err = mlx5_MAD_IFC(to_mdev(ibdev),
110 mad_flags & IB_MAD_IGNORE_MKEY,
111 mad_flags & IB_MAD_IGNORE_BKEY,
112 port_num, in_wc, in_grh, in_mad, out_mad);
114 return IB_MAD_RESULT_FAILURE;
116 /* set return bit in status of directed route responses */
117 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
118 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15);
120 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS)
121 /* no response for trap repress */
122 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
124 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
127 static void pma_cnt_ext_assign(struct ib_pma_portcounters_ext *pma_cnt_ext,
128 struct mlx5_vport_counters *vc)
130 pma_cnt_ext->port_xmit_data = cpu_to_be64((vc->transmitted_ib_unicast.octets +
131 vc->transmitted_ib_multicast.octets) >> 2);
132 pma_cnt_ext->port_rcv_data = cpu_to_be64((vc->received_ib_unicast.octets +
133 vc->received_ib_multicast.octets) >> 2);
134 pma_cnt_ext->port_xmit_packets = cpu_to_be64(vc->transmitted_ib_unicast.packets +
135 vc->transmitted_ib_multicast.packets);
136 pma_cnt_ext->port_rcv_packets = cpu_to_be64(vc->received_ib_unicast.packets +
137 vc->received_ib_multicast.packets);
138 pma_cnt_ext->port_unicast_xmit_packets = cpu_to_be64(vc->transmitted_ib_unicast.packets);
139 pma_cnt_ext->port_unicast_rcv_packets = cpu_to_be64(vc->received_ib_unicast.packets);
140 pma_cnt_ext->port_multicast_xmit_packets = cpu_to_be64(vc->transmitted_ib_multicast.packets);
141 pma_cnt_ext->port_multicast_rcv_packets = cpu_to_be64(vc->received_ib_multicast.packets);
144 static void pma_cnt_assign(struct ib_pma_portcounters *pma_cnt,
145 struct mlx5_vport_counters *vc)
147 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data,
148 (vc->transmitted_ib_unicast.octets +
149 vc->transmitted_ib_multicast.octets) >> 2);
150 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data,
151 (vc->received_ib_unicast.octets +
152 vc->received_ib_multicast.octets) >> 2);
153 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets,
154 vc->transmitted_ib_unicast.packets +
155 vc->transmitted_ib_multicast.packets);
156 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets,
157 vc->received_ib_unicast.packets +
158 vc->received_ib_multicast.packets);
161 static int process_pma_cmd(struct ib_device *ibdev, u8 port_num,
162 struct ib_mad *in_mad, struct ib_mad *out_mad)
164 struct mlx5_ib_dev *dev = to_mdev(ibdev);
165 struct mlx5_vport_counters *vc;
169 vc = kzalloc(sizeof(*vc), GFP_KERNEL);
173 ext = in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS_EXT;
175 err = mlx5_get_vport_counters(dev->mdev, port_num, vc);
178 struct ib_pma_portcounters_ext *pma_cnt_ext =
179 (struct ib_pma_portcounters_ext *)(out_mad->data + 40);
181 pma_cnt_ext_assign(pma_cnt_ext, vc);
183 struct ib_pma_portcounters *pma_cnt =
184 (struct ib_pma_portcounters *)(out_mad->data + 40);
186 ASSIGN_16BIT_COUNTER(pma_cnt->port_rcv_errors,
187 (u16)vc->received_errors.packets);
189 pma_cnt_assign(pma_cnt, vc);
191 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
198 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
199 struct ib_wc *in_wc, struct ib_grh *in_grh,
200 struct ib_mad *in_mad, struct ib_mad *out_mad)
202 struct mlx5_ib_dev *dev = to_mdev(ibdev);
203 struct mlx5_core_dev *mdev = dev->mdev;
205 memset(out_mad->data, 0, sizeof(out_mad->data));
207 if (MLX5_CAP_GEN(mdev, vport_counters) &&
208 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT &&
209 in_mad->mad_hdr.method == IB_MGMT_METHOD_GET) {
210 /* TBD: read error counters from the PPCNT */
211 return process_pma_cmd(ibdev, port_num, in_mad, out_mad);
213 return process_mad(ibdev, mad_flags, port_num, in_wc, in_grh,
218 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port)
220 struct ib_smp *in_mad = NULL;
221 struct ib_smp *out_mad = NULL;
225 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
226 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
227 if (!in_mad || !out_mad)
230 init_query_mad(in_mad);
231 in_mad->attr_id = MLX5_ATTR_EXTENDED_PORT_INFO;
232 in_mad->attr_mod = cpu_to_be32(port);
234 err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
236 packet_error = be16_to_cpu(out_mad->status);
238 dev->mdev->port_caps[port - 1].ext_port_cap = (!err && !packet_error) ?
239 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO : 0;
247 int mlx5_query_smp_attr_node_info_mad_ifc(struct ib_device *ibdev,
248 struct ib_smp *out_mad)
250 struct ib_smp *in_mad = NULL;
253 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
257 init_query_mad(in_mad);
258 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
260 err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, 1, NULL, NULL, in_mad,
267 int mlx5_query_system_image_guid_mad_ifc(struct ib_device *ibdev,
268 __be64 *sys_image_guid)
270 struct ib_smp *out_mad = NULL;
273 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
277 err = mlx5_query_smp_attr_node_info_mad_ifc(ibdev, out_mad);
281 memcpy(sys_image_guid, out_mad->data + 4, 8);
289 int mlx5_query_max_pkeys_mad_ifc(struct ib_device *ibdev,
292 struct ib_smp *out_mad = NULL;
295 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
299 err = mlx5_query_smp_attr_node_info_mad_ifc(ibdev, out_mad);
303 *max_pkeys = be16_to_cpup((__be16 *)(out_mad->data + 28));
311 int mlx5_query_vendor_id_mad_ifc(struct ib_device *ibdev,
314 struct ib_smp *out_mad = NULL;
317 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
321 err = mlx5_query_smp_attr_node_info_mad_ifc(ibdev, out_mad);
325 *vendor_id = be32_to_cpup((__be32 *)(out_mad->data + 36)) & 0xffff;
333 int mlx5_query_node_desc_mad_ifc(struct mlx5_ib_dev *dev, char *node_desc)
335 struct ib_smp *in_mad = NULL;
336 struct ib_smp *out_mad = NULL;
339 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
340 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
341 if (!in_mad || !out_mad)
344 init_query_mad(in_mad);
345 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
347 err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
351 memcpy(node_desc, out_mad->data, 64);
358 int mlx5_query_node_guid_mad_ifc(struct mlx5_ib_dev *dev, u64 *node_guid)
360 struct ib_smp *in_mad = NULL;
361 struct ib_smp *out_mad = NULL;
364 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
365 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
366 if (!in_mad || !out_mad)
369 init_query_mad(in_mad);
370 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
372 err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
376 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
383 int mlx5_query_pkey_mad_ifc(struct ib_device *ibdev, u8 port, u16 index,
386 struct ib_smp *in_mad = NULL;
387 struct ib_smp *out_mad = NULL;
390 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
391 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
392 if (!in_mad || !out_mad)
395 init_query_mad(in_mad);
396 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
397 in_mad->attr_mod = cpu_to_be32(index / 32);
399 err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad,
404 *pkey = be16_to_cpu(((__be16 *)out_mad->data)[index % 32]);
412 int mlx5_query_gids_mad_ifc(struct ib_device *ibdev, u8 port, int index,
415 struct ib_smp *in_mad = NULL;
416 struct ib_smp *out_mad = NULL;
419 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
420 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
421 if (!in_mad || !out_mad)
424 init_query_mad(in_mad);
425 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
426 in_mad->attr_mod = cpu_to_be32(port);
428 err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad,
433 memcpy(gid->raw, out_mad->data + 8, 8);
435 init_query_mad(in_mad);
436 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
437 in_mad->attr_mod = cpu_to_be32(index / 8);
439 err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad,
444 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
452 int mlx5_query_port_mad_ifc(struct ib_device *ibdev, u8 port,
453 struct ib_port_attr *props)
455 struct mlx5_ib_dev *dev = to_mdev(ibdev);
456 struct mlx5_core_dev *mdev = dev->mdev;
457 struct ib_smp *in_mad = NULL;
458 struct ib_smp *out_mad = NULL;
459 int ext_active_speed;
462 if (port < 1 || port > MLX5_CAP_GEN(mdev, num_ports)) {
463 mlx5_ib_warn(dev, "invalid port number %d\n", port);
467 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
468 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
469 if (!in_mad || !out_mad)
472 memset(props, 0, sizeof(*props));
474 init_query_mad(in_mad);
475 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
476 in_mad->attr_mod = cpu_to_be32(port);
478 err = mlx5_MAD_IFC(dev, 1, 1, port, NULL, NULL, in_mad, out_mad);
480 mlx5_ib_warn(dev, "err %d\n", err);
484 props->lid = be16_to_cpup((__be16 *)(out_mad->data + 16));
485 props->lmc = out_mad->data[34] & 0x7;
486 props->sm_lid = be16_to_cpup((__be16 *)(out_mad->data + 18));
487 props->sm_sl = out_mad->data[36] & 0xf;
488 props->state = out_mad->data[32] & 0xf;
489 props->phys_state = out_mad->data[33] >> 4;
490 props->port_cap_flags = be32_to_cpup((__be32 *)(out_mad->data + 20));
491 props->gid_tbl_len = out_mad->data[50];
492 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
493 props->pkey_tbl_len = mdev->port_caps[port - 1].pkey_table_len;
494 props->bad_pkey_cntr = be16_to_cpup((__be16 *)(out_mad->data + 46));
495 props->qkey_viol_cntr = be16_to_cpup((__be16 *)(out_mad->data + 48));
496 props->active_width = out_mad->data[31] & 0xf;
497 props->active_speed = out_mad->data[35] >> 4;
498 props->max_mtu = out_mad->data[41] & 0xf;
499 props->active_mtu = out_mad->data[36] >> 4;
500 props->subnet_timeout = out_mad->data[51] & 0x1f;
501 props->max_vl_num = out_mad->data[37] >> 4;
502 props->init_type_reply = out_mad->data[41] >> 4;
504 /* Check if extended speeds (EDR/FDR/...) are supported */
505 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
506 ext_active_speed = out_mad->data[62] >> 4;
508 switch (ext_active_speed) {
510 props->active_speed = 16; /* FDR */
513 props->active_speed = 32; /* EDR */
518 /* If reported active speed is QDR, check if is FDR-10 */
519 if (props->active_speed == 4) {
520 if (mdev->port_caps[port - 1].ext_port_cap &
521 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO) {
522 init_query_mad(in_mad);
523 in_mad->attr_id = MLX5_ATTR_EXTENDED_PORT_INFO;
524 in_mad->attr_mod = cpu_to_be32(port);
526 err = mlx5_MAD_IFC(dev, 1, 1, port,
527 NULL, NULL, in_mad, out_mad);
531 /* Checking LinkSpeedActive for FDR-10 */
532 if (out_mad->data[15] & 0x1)
533 props->active_speed = 8;