sys/dev/mlx5/qp.h

   1 /*-
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef MLX5_QP_H
  29 #define MLX5_QP_H
  30
  31 #include <dev/mlx5/device.h>
  32 #include <dev/mlx5/driver.h>
  33 #include <dev/mlx5/mlx5_ifc.h>
  34
  35 #define MLX5_INVALID_LKEY       0x100
  36 #define MLX5_SIG_WQE_SIZE       (MLX5_SEND_WQE_BB * 5)
  37 #define MLX5_DIF_SIZE           8
  38 #define MLX5_STRIDE_BLOCK_OP    0x400
  39 #define MLX5_CPY_GRD_MASK       0xc0
  40 #define MLX5_CPY_APP_MASK       0x30
  41 #define MLX5_CPY_REF_MASK       0x0f
  42 #define MLX5_BSF_INC_REFTAG     (1 << 6)
  43 #define MLX5_BSF_INL_VALID      (1 << 15)
  44 #define MLX5_BSF_REFRESH_DIF    (1 << 14)
  45 #define MLX5_BSF_REPEAT_BLOCK   (1 << 7)
  46 #define MLX5_BSF_APPTAG_ESCAPE  0x1
  47 #define MLX5_BSF_APPREF_ESCAPE  0x2
  48
  49 enum mlx5_qp_optpar {
  50         MLX5_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  51         MLX5_QP_OPTPAR_RRE                      = 1 << 1,
  52         MLX5_QP_OPTPAR_RAE                      = 1 << 2,
  53         MLX5_QP_OPTPAR_RWE                      = 1 << 3,
  54         MLX5_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  55         MLX5_QP_OPTPAR_Q_KEY                    = 1 << 5,
  56         MLX5_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  57         MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  58         MLX5_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  59         MLX5_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  60         MLX5_QP_OPTPAR_PM_STATE                 = 1 << 10,
  61         MLX5_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  62         MLX5_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  63         MLX5_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  64         MLX5_QP_OPTPAR_PRI_PORT                 = 1 << 16,
  65         MLX5_QP_OPTPAR_SRQN                     = 1 << 18,
  66         MLX5_QP_OPTPAR_CQN_RCV                  = 1 << 19,
  67         MLX5_QP_OPTPAR_DC_HS                    = 1 << 20,
  68         MLX5_QP_OPTPAR_DC_KEY                   = 1 << 21,
  69 };
  70
  71 enum mlx5_qp_state {
  72         MLX5_QP_STATE_RST                       = 0,
  73         MLX5_QP_STATE_INIT                      = 1,
  74         MLX5_QP_STATE_RTR                       = 2,
  75         MLX5_QP_STATE_RTS                       = 3,
  76         MLX5_QP_STATE_SQER                      = 4,
  77         MLX5_QP_STATE_SQD                       = 5,
  78         MLX5_QP_STATE_ERR                       = 6,
  79         MLX5_QP_STATE_SQ_DRAINING               = 7,
  80         MLX5_QP_STATE_SUSPENDED                 = 9,
  81         MLX5_QP_NUM_STATE
  82 };
  83
  84 enum {
  85         MLX5_QP_ST_RC                           = 0x0,
  86         MLX5_QP_ST_UC                           = 0x1,
  87         MLX5_QP_ST_UD                           = 0x2,
  88         MLX5_QP_ST_XRC                          = 0x3,
  89         MLX5_QP_ST_MLX                          = 0x4,
  90         MLX5_QP_ST_DCI                          = 0x5,
  91         MLX5_QP_ST_DCT                          = 0x6,
  92         MLX5_QP_ST_QP0                          = 0x7,
  93         MLX5_QP_ST_QP1                          = 0x8,
  94         MLX5_QP_ST_RAW_ETHERTYPE                = 0x9,
  95         MLX5_QP_ST_RAW_IPV6                     = 0xa,
  96         MLX5_QP_ST_SNIFFER                      = 0xb,
  97         MLX5_QP_ST_SYNC_UMR                     = 0xe,
  98         MLX5_QP_ST_PTP_1588                     = 0xd,
  99         MLX5_QP_ST_REG_UMR                      = 0xc,
 100         MLX5_QP_ST_SW_CNAK                      = 0x10,
 101         MLX5_QP_ST_MAX
 102 };
 103
 104 enum {
 105         MLX5_NON_ZERO_RQ        = 0 << 24,
 106         MLX5_SRQ_RQ             = 1 << 24,
 107         MLX5_CRQ_RQ             = 2 << 24,
 108         MLX5_ZERO_LEN_RQ        = 3 << 24
 109 };
 110
 111 enum {
 112         /* params1 */
 113         MLX5_QP_BIT_SRE                         = 1 << 15,
 114         MLX5_QP_BIT_SWE                         = 1 << 14,
 115         MLX5_QP_BIT_SAE                         = 1 << 13,
 116         /* params2 */
 117         MLX5_QP_BIT_RRE                         = 1 << 15,
 118         MLX5_QP_BIT_RWE                         = 1 << 14,
 119         MLX5_QP_BIT_RAE                         = 1 << 13,
 120         MLX5_QP_BIT_RIC                         = 1 <<  4,
 121         MLX5_QP_BIT_COLL_SYNC_RQ                = 1 << 2,
 122         MLX5_QP_BIT_COLL_SYNC_SQ                = 1 << 1,
 123         MLX5_QP_BIT_COLL_MASTER                 = 1 << 0
 124 };
 125
 126 enum {
 127         MLX5_DCT_BIT_RRE                = 1 << 19,
 128         MLX5_DCT_BIT_RWE                = 1 << 18,
 129         MLX5_DCT_BIT_RAE                = 1 << 17,
 130 };
 131
 132 enum {
 133         MLX5_WQE_CTRL_CQ_UPDATE         = 2 << 2,
 134         MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
 135         MLX5_WQE_CTRL_SOLICITED         = 1 << 1,
 136 };
 137
 138 #define MLX5_SEND_WQE_DS        16
 139 #define MLX5_SEND_WQE_BB        64
 140 #define MLX5_SEND_WQEBB_NUM_DS  (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
 141
 142 enum {
 143         MLX5_SEND_WQE_MAX_WQEBBS        = 16,
 144 };
 145
 146 enum {
 147         MLX5_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 148         MLX5_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 149         MLX5_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
 150         MLX5_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
 151         MLX5_WQE_FMR_PERM_ATOMIC        = 1 << 31
 152 };
 153
 154 enum {
 155         MLX5_FENCE_MODE_NONE                    = 0 << 5,
 156         MLX5_FENCE_MODE_INITIATOR_SMALL         = 1 << 5,
 157         MLX5_FENCE_MODE_STRONG_ORDERING         = 3 << 5,
 158         MLX5_FENCE_MODE_SMALL_AND_FENCE         = 4 << 5,
 159 };
 160
 161 enum {
 162         MLX5_QP_DRAIN_SIGERR    = 1 << 26,
 163         MLX5_QP_LAT_SENSITIVE   = 1 << 28,
 164         MLX5_QP_BLOCK_MCAST     = 1 << 30,
 165         MLX5_QP_ENABLE_SIG      = 1 << 31,
 166 };
 167
 168 enum {
 169         MLX5_RCV_DBR    = 0,
 170         MLX5_SND_DBR    = 1,
 171 };
 172
 173 enum {
 174         MLX5_FLAGS_INLINE       = 1<<7,
 175         MLX5_FLAGS_CHECK_FREE   = 1<<5,
 176 };
 177
 178 struct mlx5_wqe_fmr_seg {
 179         __be32                  flags;
 180         __be32                  mem_key;
 181         __be64                  buf_list;
 182         __be64                  start_addr;
 183         __be64                  reg_len;
 184         __be32                  offset;
 185         __be32                  page_size;
 186         u32                     reserved[2];
 187 };
 188
 189 struct mlx5_wqe_ctrl_seg {
 190         __be32                  opmod_idx_opcode;
 191         __be32                  qpn_ds;
 192         u8                      signature;
 193         u8                      rsvd[2];
 194         u8                      fm_ce_se;
 195         __be32                  imm;
 196 };
 197
 198 enum {
 199         MLX5_MLX_FLAG_MASK_VL15 = 0x40,
 200         MLX5_MLX_FLAG_MASK_SLR  = 0x20,
 201         MLX5_MLX_FLAG_MASK_ICRC = 0x8,
 202         MLX5_MLX_FLAG_MASK_FL   = 4
 203 };
 204
 205 struct mlx5_mlx_seg {
 206         __be32          rsvd0;
 207         u8              flags;
 208         u8              stat_rate_sl;
 209         u8              rsvd1[8];
 210         __be16          dlid;
 211 };
 212
 213 enum {
 214         MLX5_ETH_WQE_L3_INNER_CSUM      = 1 << 4,
 215         MLX5_ETH_WQE_L4_INNER_CSUM      = 1 << 5,
 216         MLX5_ETH_WQE_L3_CSUM            = 1 << 6,
 217         MLX5_ETH_WQE_L4_CSUM            = 1 << 7,
 218 };
 219
 220 enum {
 221         MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 0,
 222         MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 1,
 223         MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 4,
 224         MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 5,
 225 };
 226
 227 struct mlx5_wqe_eth_seg {
 228         u8              swp_outer_l4_offset;
 229         u8              swp_outer_l3_offset;
 230         u8              swp_inner_l4_offset;
 231         u8              swp_inner_l3_offset;
 232         u8              cs_flags;
 233         u8              swp_flags;
 234         __be16          mss;
 235         __be32          rsvd2;
 236         union {
 237                 struct {
 238                         __be16          inline_hdr_sz;
 239                         u8              inline_hdr_start[2];
 240                 };
 241                 struct {
 242                         __be16          vlan_cmd;
 243                         __be16          vlan_hdr;
 244                 };
 245         };
 246 };
 247
 248 struct mlx5_wqe_xrc_seg {
 249         __be32                  xrc_srqn;
 250         u8                      rsvd[12];
 251 };
 252
 253 struct mlx5_wqe_masked_atomic_seg {
 254         __be64                  swap_add;
 255         __be64                  compare;
 256         __be64                  swap_add_mask;
 257         __be64                  compare_mask;
 258 };
 259
 260 struct mlx5_av {
 261         union {
 262                 struct {
 263                         __be32  qkey;
 264                         __be32  reserved;
 265                 } qkey;
 266                 __be64  dc_key;
 267         } key;
 268         __be32  dqp_dct;
 269         u8      stat_rate_sl;
 270         u8      fl_mlid;
 271         union {
 272                 __be16  rlid;
 273                 __be16  udp_sport;
 274         };
 275         u8      reserved0[4];
 276         u8      rmac[6];
 277         u8      tclass;
 278         u8      hop_limit;
 279         __be32  grh_gid_fl;
 280         u8      rgid[16];
 281 };
 282
 283 struct mlx5_wqe_datagram_seg {
 284         struct mlx5_av  av;
 285 };
 286
 287 struct mlx5_wqe_raddr_seg {
 288         __be64                  raddr;
 289         __be32                  rkey;
 290         u32                     reserved;
 291 };
 292
 293 struct mlx5_wqe_atomic_seg {
 294         __be64                  swap_add;
 295         __be64                  compare;
 296 };
 297
 298 struct mlx5_wqe_data_seg {
 299         __be32                  byte_count;
 300         __be32                  lkey;
 301         __be64                  addr;
 302 };
 303
 304 struct mlx5_wqe_umr_ctrl_seg {
 305         u8              flags;
 306         u8              rsvd0[3];
 307         __be16          klm_octowords;
 308         __be16          bsf_octowords;
 309         __be64          mkey_mask;
 310         u8              rsvd1[32];
 311 };
 312
 313 struct mlx5_seg_set_psv {
 314         __be32          psv_num;
 315         __be16          syndrome;
 316         __be16          status;
 317         __be32          transient_sig;
 318         __be32          ref_tag;
 319 };
 320
 321 struct mlx5_seg_get_psv {
 322         u8              rsvd[19];
 323         u8              num_psv;
 324         __be32          l_key;
 325         __be64          va;
 326         __be32          psv_index[4];
 327 };
 328
 329 struct mlx5_seg_check_psv {
 330         u8              rsvd0[2];
 331         __be16          err_coalescing_op;
 332         u8              rsvd1[2];
 333         __be16          xport_err_op;
 334         u8              rsvd2[2];
 335         __be16          xport_err_mask;
 336         u8              rsvd3[7];
 337         u8              num_psv;
 338         __be32          l_key;
 339         __be64          va;
 340         __be32          psv_index[4];
 341 };
 342
 343 struct mlx5_rwqe_sig {
 344         u8      rsvd0[4];
 345         u8      signature;
 346         u8      rsvd1[11];
 347 };
 348
 349 struct mlx5_wqe_signature_seg {
 350         u8      rsvd0[4];
 351         u8      signature;
 352         u8      rsvd1[11];
 353 };
 354
 355 struct mlx5_wqe_inline_seg {
 356         __be32  byte_count;
 357 };
 358
 359 enum mlx5_sig_type {
 360         MLX5_DIF_CRC = 0x1,
 361         MLX5_DIF_IPCS = 0x2,
 362 };
 363
 364 struct mlx5_bsf_inl {
 365         __be16          vld_refresh;
 366         __be16          dif_apptag;
 367         __be32          dif_reftag;
 368         u8              sig_type;
 369         u8              rp_inv_seed;
 370         u8              rsvd[3];
 371         u8              dif_inc_ref_guard_check;
 372         __be16          dif_app_bitmask_check;
 373 };
 374
 375 struct mlx5_bsf {
 376         struct mlx5_bsf_basic {
 377                 u8              bsf_size_sbs;
 378                 u8              check_byte_mask;
 379                 union {
 380                         u8      copy_byte_mask;
 381                         u8      bs_selector;
 382                         u8      rsvd_wflags;
 383                 } wire;
 384                 union {
 385                         u8      bs_selector;
 386                         u8      rsvd_mflags;
 387                 } mem;
 388                 __be32          raw_data_size;
 389                 __be32          w_bfs_psv;
 390                 __be32          m_bfs_psv;
 391         } basic;
 392         struct mlx5_bsf_ext {
 393                 __be32          t_init_gen_pro_size;
 394                 __be32          rsvd_epi_size;
 395                 __be32          w_tfs_psv;
 396                 __be32          m_tfs_psv;
 397         } ext;
 398         struct mlx5_bsf_inl     w_inl;
 399         struct mlx5_bsf_inl     m_inl;
 400 };
 401
 402 struct mlx5_klm {
 403         __be32          bcount;
 404         __be32          key;
 405         __be64          va;
 406 };
 407
 408 struct mlx5_stride_block_entry {
 409         __be16          stride;
 410         __be16          bcount;
 411         __be32          key;
 412         __be64          va;
 413 };
 414
 415 struct mlx5_stride_block_ctrl_seg {
 416         __be32          bcount_per_cycle;
 417         __be32          op;
 418         __be32          repeat_count;
 419         u16             rsvd;
 420         __be16          num_entries;
 421 };
 422
 423 struct mlx5_core_qp {
 424         struct mlx5_core_rsc_common     common; /* must be first */
 425         void (*event)           (struct mlx5_core_qp *, int);
 426         int                     qpn;
 427         struct mlx5_rsc_debug   *dbg;
 428         int                     pid;
 429 };
 430
 431 struct mlx5_qp_path {
 432         u8                      fl_free_ar;
 433         u8                      rsvd3;
 434         __be16                  pkey_index;
 435         u8                      rsvd0;
 436         u8                      grh_mlid;
 437         __be16                  rlid;
 438         u8                      ackto_lt;
 439         u8                      mgid_index;
 440         u8                      static_rate;
 441         u8                      hop_limit;
 442         __be32                  tclass_flowlabel;
 443         union {
 444                 u8              rgid[16];
 445                 u8              rip[16];
 446         };
 447         u8                      f_dscp_ecn_prio;
 448         u8                      ecn_dscp;
 449         __be16                  udp_sport;
 450         u8                      dci_cfi_prio_sl;
 451         u8                      port;
 452         u8                      rmac[6];
 453 };
 454
 455 struct mlx5_qp_context {
 456         __be32                  flags;
 457         __be32                  flags_pd;
 458         u8                      mtu_msgmax;
 459         u8                      rq_size_stride;
 460         __be16                  sq_crq_size;
 461         __be32                  qp_counter_set_usr_page;
 462         __be32                  wire_qpn;
 463         __be32                  log_pg_sz_remote_qpn;
 464         struct                  mlx5_qp_path pri_path;
 465         struct                  mlx5_qp_path alt_path;
 466         __be32                  params1;
 467         u8                      reserved2[4];
 468         __be32                  next_send_psn;
 469         __be32                  cqn_send;
 470         u8                      reserved3[8];
 471         __be32                  last_acked_psn;
 472         __be32                  ssn;
 473         __be32                  params2;
 474         __be32                  rnr_nextrecvpsn;
 475         __be32                  xrcd;
 476         __be32                  cqn_recv;
 477         __be64                  db_rec_addr;
 478         __be32                  qkey;
 479         __be32                  rq_type_srqn;
 480         __be32                  rmsn;
 481         __be16                  hw_sq_wqe_counter;
 482         __be16                  sw_sq_wqe_counter;
 483         __be16                  hw_rcyclic_byte_counter;
 484         __be16                  hw_rq_counter;
 485         __be16                  sw_rcyclic_byte_counter;
 486         __be16                  sw_rq_counter;
 487         u8                      rsvd0[5];
 488         u8                      cgs;
 489         u8                      cs_req;
 490         u8                      cs_res;
 491         __be64                  dc_access_key;
 492         u8                      rsvd1[24];
 493 };
 494
 495 struct mlx5_create_qp_mbox_in {
 496         struct mlx5_inbox_hdr   hdr;
 497         __be32                  input_qpn;
 498         u8                      rsvd0[4];
 499         __be32                  opt_param_mask;
 500         u8                      rsvd1[4];
 501         struct mlx5_qp_context  ctx;
 502         u8                      rsvd3[16];
 503         __be64                  pas[0];
 504 };
 505
 506 struct mlx5_dct_context {
 507         u8                      state;
 508         u8                      rsvd0[7];
 509         __be32                  cqn;
 510         __be32                  flags;
 511         u8                      rsvd1;
 512         u8                      cs_res;
 513         u8                      min_rnr;
 514         u8                      rsvd2;
 515         __be32                  srqn;
 516         __be32                  pdn;
 517         __be32                  tclass_flow_label;
 518         __be64                  access_key;
 519         u8                      mtu;
 520         u8                      port;
 521         __be16                  pkey_index;
 522         u8                      rsvd4;
 523         u8                      mgid_index;
 524         u8                      rsvd5;
 525         u8                      hop_limit;
 526         __be32                  access_violations;
 527         u8                      rsvd[12];
 528 };
 529
 530 struct mlx5_create_dct_mbox_in {
 531         struct mlx5_inbox_hdr   hdr;
 532         u8                      rsvd0[8];
 533         struct mlx5_dct_context context;
 534         u8                      rsvd[48];
 535 };
 536
 537 struct mlx5_create_dct_mbox_out {
 538         struct mlx5_outbox_hdr  hdr;
 539         __be32                  dctn;
 540         u8                      rsvd0[4];
 541 };
 542
 543 struct mlx5_destroy_dct_mbox_in {
 544         struct mlx5_inbox_hdr   hdr;
 545         __be32                  dctn;
 546         u8                      rsvd0[4];
 547 };
 548
 549 struct mlx5_destroy_dct_mbox_out {
 550         struct mlx5_outbox_hdr  hdr;
 551         u8                      rsvd0[8];
 552 };
 553
 554 struct mlx5_drain_dct_mbox_in {
 555         struct mlx5_inbox_hdr   hdr;
 556         __be32                  dctn;
 557         u8                      rsvd0[4];
 558 };
 559
 560 struct mlx5_drain_dct_mbox_out {
 561         struct mlx5_outbox_hdr  hdr;
 562         u8                      rsvd0[8];
 563 };
 564
 565 struct mlx5_create_qp_mbox_out {
 566         struct mlx5_outbox_hdr  hdr;
 567         __be32                  qpn;
 568         u8                      rsvd0[4];
 569 };
 570
 571 struct mlx5_destroy_qp_mbox_in {
 572         struct mlx5_inbox_hdr   hdr;
 573         __be32                  qpn;
 574         u8                      rsvd0[4];
 575 };
 576
 577 struct mlx5_destroy_qp_mbox_out {
 578         struct mlx5_outbox_hdr  hdr;
 579         u8                      rsvd0[8];
 580 };
 581
 582 struct mlx5_modify_qp_mbox_in {
 583         struct mlx5_inbox_hdr   hdr;
 584         __be32                  qpn;
 585         u8                      rsvd1[4];
 586         __be32                  optparam;
 587         u8                      rsvd0[4];
 588         struct mlx5_qp_context  ctx;
 589         u8                      rsvd2[16];
 590 };
 591
 592 struct mlx5_modify_qp_mbox_out {
 593         struct mlx5_outbox_hdr  hdr;
 594         u8                      rsvd0[8];
 595 };
 596
 597 struct mlx5_query_qp_mbox_in {
 598         struct mlx5_inbox_hdr   hdr;
 599         __be32                  qpn;
 600         u8                      rsvd[4];
 601 };
 602
 603 struct mlx5_query_qp_mbox_out {
 604         struct mlx5_outbox_hdr  hdr;
 605         u8                      rsvd1[8];
 606         __be32                  optparam;
 607         u8                      rsvd0[4];
 608         struct mlx5_qp_context  ctx;
 609         u8                      rsvd2[16];
 610         __be64                  pas[0];
 611 };
 612
 613 struct mlx5_query_dct_mbox_in {
 614         struct mlx5_inbox_hdr   hdr;
 615         __be32                  dctn;
 616         u8                      rsvd[4];
 617 };
 618
 619 struct mlx5_query_dct_mbox_out {
 620         struct mlx5_outbox_hdr  hdr;
 621         u8                      rsvd0[8];
 622         struct mlx5_dct_context ctx;
 623         u8                      rsvd1[48];
 624 };
 625
 626 struct mlx5_arm_dct_mbox_in {
 627         struct mlx5_inbox_hdr   hdr;
 628         __be32                  dctn;
 629         u8                      rsvd[4];
 630 };
 631
 632 struct mlx5_arm_dct_mbox_out {
 633         struct mlx5_outbox_hdr  hdr;
 634         u8                      rsvd0[8];
 635 };
 636
 637 struct mlx5_conf_sqp_mbox_in {
 638         struct mlx5_inbox_hdr   hdr;
 639         __be32                  qpn;
 640         u8                      rsvd[3];
 641         u8                      type;
 642 };
 643
 644 struct mlx5_conf_sqp_mbox_out {
 645         struct mlx5_outbox_hdr  hdr;
 646         u8                      rsvd[8];
 647 };
 648
 649 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
 650 {
 651         return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
 652 }
 653
 654 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
 655 {
 656         return radix_tree_lookup(&dev->priv.mr_table.tree, key);
 657 }
 658
 659 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
 660                         struct mlx5_core_qp *qp,
 661                         struct mlx5_create_qp_mbox_in *in,
 662                         int inlen);
 663 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation,
 664                         struct mlx5_modify_qp_mbox_in *in, int sqd_event,
 665                         struct mlx5_core_qp *qp);
 666 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
 667                          struct mlx5_core_qp *qp);
 668 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
 669                        struct mlx5_query_qp_mbox_out *out, int outlen);
 670 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct,
 671                         struct mlx5_query_dct_mbox_out *out);
 672 int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct);
 673
 674 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
 675 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
 676 int mlx5_core_create_dct(struct mlx5_core_dev *dev,
 677                          struct mlx5_core_dct *dct,
 678                          struct mlx5_create_dct_mbox_in *in);
 679 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev,
 680                           struct mlx5_core_dct *dct);
 681 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
 682                                 struct mlx5_core_qp *rq);
 683 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
 684                                   struct mlx5_core_qp *rq);
 685 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
 686                                 struct mlx5_core_qp *sq);
 687 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
 688                                   struct mlx5_core_qp *sq);
 689 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
 690 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
 691 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
 692 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
 693
 694 static inline const char *mlx5_qp_type_str(int type)
 695 {
 696         switch (type) {
 697         case MLX5_QP_ST_RC: return "RC";
 698         case MLX5_QP_ST_UC: return "C";
 699         case MLX5_QP_ST_UD: return "UD";
 700         case MLX5_QP_ST_XRC: return "XRC";
 701         case MLX5_QP_ST_MLX: return "MLX";
 702         case MLX5_QP_ST_DCI: return "DCI";
 703         case MLX5_QP_ST_QP0: return "QP0";
 704         case MLX5_QP_ST_QP1: return "QP1";
 705         case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
 706         case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
 707         case MLX5_QP_ST_SNIFFER: return "SNIFFER";
 708         case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
 709         case MLX5_QP_ST_PTP_1588: return "PTP_1588";
 710         case MLX5_QP_ST_REG_UMR: return "REG_UMR";
 711         case MLX5_QP_ST_SW_CNAK: return "DC_CNAK";
 712         default: return "Invalid transport type";
 713         }
 714 }
 715
 716 static inline const char *mlx5_qp_state_str(int state)
 717 {
 718         switch (state) {
 719         case MLX5_QP_STATE_RST:
 720         return "RST";
 721         case MLX5_QP_STATE_INIT:
 722         return "INIT";
 723         case MLX5_QP_STATE_RTR:
 724         return "RTR";
 725         case MLX5_QP_STATE_RTS:
 726         return "RTS";
 727         case MLX5_QP_STATE_SQER:
 728         return "SQER";
 729         case MLX5_QP_STATE_SQD:
 730         return "SQD";
 731         case MLX5_QP_STATE_ERR:
 732         return "ERR";
 733         case MLX5_QP_STATE_SQ_DRAINING:
 734         return "SQ_DRAINING";
 735         case MLX5_QP_STATE_SUSPENDED:
 736         return "SUSPENDED";
 737         default: return "Invalid QP state";
 738         }
 739 }
 740
 741 #endif /* MLX5_QP_H */