2 * Copyright (c) 2012-2015 LSI Corp.
3 * Copyright (c) 2013-2016 Avago Technologies
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
36 * Copyright (c) 2000-2015 LSI Corporation.
37 * Copyright (c) 2013-2016 Avago Technologies
38 * All rights reserved.
42 * Title: MPI Message independent structures and definitions
43 * including System Interface Register Set and
44 * scatter/gather formats.
45 * Creation Date: June 21, 2006
47 * mpi2.h Version: 02.00.42
49 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
50 * prefix are for use only on MPI v2.5 products, and must not be used
51 * with MPI v2.0 products. Unless otherwise noted, names beginning with
52 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
57 * Date Version Description
58 * -------- -------- ------------------------------------------------------
59 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
60 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
61 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
62 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
63 * Moved ReplyPostHostIndex register to offset 0x6C of the
64 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
65 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
66 * Added union of request descriptors.
67 * Added union of reply descriptors.
68 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
69 * Added define for MPI2_VERSION_02_00.
70 * Fixed the size of the FunctionDependent5 field in the
71 * MPI2_DEFAULT_REPLY structure.
72 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Removed the MPI-defined Fault Codes and extended the
74 * product specific codes up to 0xEFFF.
75 * Added a sixth key value for the WriteSequence register
76 * and changed the flush value to 0x0.
77 * Added message function codes for Diagnostic Buffer Post
78 * and Diagnsotic Release.
79 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
80 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
81 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
83 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
84 * Added #defines for marking a reply descriptor as unused.
85 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
87 * Moved LUN field defines from mpi2_init.h.
88 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
89 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
90 * In all request and reply descriptors, replaced VF_ID
91 * field with MSIxIndex field.
92 * Removed DevHandle field from
93 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
95 * Added RAID Accelerator functionality.
96 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
97 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
98 * Added MSI-x index mask and shift for Reply Post Host
100 * Added function code for Host Based Discovery Action.
101 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
102 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
103 * Added defines for product-specific range of message
104 * function codes, 0xF0 to 0xFF.
105 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
106 * Added alternative defines for the SGE Direction bit.
107 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
108 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
109 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
110 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
111 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
112 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
113 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
114 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
115 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
116 * Incorporating additions for MPI v2.5.
117 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
118 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
119 * Added Hard Reset delay timings.
120 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
121 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
122 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
123 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
124 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
125 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
126 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
127 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
128 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
129 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT.
130 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
131 * 11-18-14 02.00.36 Updated copyright information.
132 * Bumped MPI2_HEADER_VERSION_UNIT.
133 * 03-16-15 02.00.37 Updated for MPI v2.6.
134 * Bumped MPI2_HEADER_VERSION_UNIT.
135 * Added Scratchpad registers to
136 * MPI2_SYSTEM_INTERFACE_REGS.
137 * Added MPI2_DIAG_SBR_RELOAD.
138 * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER.
139 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT.
140 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT
141 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT.
142 * Added V7 HostDiagnostic register defines
143 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT
144 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT
145 * --------------------------------------------------------------------------
152 /*****************************************************************************
154 * MPI Version Definitions
156 *****************************************************************************/
158 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
159 #define MPI2_VERSION_MAJOR_SHIFT (8)
160 #define MPI2_VERSION_MINOR_MASK (0x00FF)
161 #define MPI2_VERSION_MINOR_SHIFT (0)
163 /* major version for all MPI v2.x */
164 #define MPI2_VERSION_MAJOR (0x02)
166 /* minor version for MPI v2.0 compatible products */
167 #define MPI2_VERSION_MINOR (0x00)
168 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
170 #define MPI2_VERSION_02_00 (0x0200)
173 /* minor version for MPI v2.5 compatible products */
174 #define MPI25_VERSION_MINOR (0x05)
175 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
177 #define MPI2_VERSION_02_05 (0x0205)
180 /* minor version for MPI v2.6 compatible products */
181 #define MPI26_VERSION_MINOR (0x06)
182 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
184 #define MPI2_VERSION_02_06 (0x0206)
187 /* Unit and Dev versioning for this MPI header set */
188 #define MPI2_HEADER_VERSION_UNIT (0x2A)
189 #define MPI2_HEADER_VERSION_DEV (0x00)
190 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
191 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
192 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
193 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
194 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
197 /*****************************************************************************
199 * IOC State Definitions
201 *****************************************************************************/
203 #define MPI2_IOC_STATE_RESET (0x00000000)
204 #define MPI2_IOC_STATE_READY (0x10000000)
205 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
206 #define MPI2_IOC_STATE_FAULT (0x40000000)
208 #define MPI2_IOC_STATE_MASK (0xF0000000)
209 #define MPI2_IOC_STATE_SHIFT (28)
211 /* Fault state range for prodcut specific codes */
212 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
213 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
216 /*****************************************************************************
218 * System Interface Register Definitions
220 *****************************************************************************/
222 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
224 U32 Doorbell; /* 0x00 */
225 U32 WriteSequence; /* 0x04 */
226 U32 HostDiagnostic; /* 0x08 */
227 U32 Reserved1; /* 0x0C */
228 U32 DiagRWData; /* 0x10 */
229 U32 DiagRWAddressLow; /* 0x14 */
230 U32 DiagRWAddressHigh; /* 0x18 */
231 U32 Reserved2[5]; /* 0x1C */
232 U32 HostInterruptStatus; /* 0x30 */
233 U32 HostInterruptMask; /* 0x34 */
234 U32 DCRData; /* 0x38 */
235 U32 DCRAddress; /* 0x3C */
236 U32 Reserved3[2]; /* 0x40 */
237 U32 ReplyFreeHostIndex; /* 0x48 */
238 U32 Reserved4[8]; /* 0x4C */
239 U32 ReplyPostHostIndex; /* 0x6C */
240 U32 Reserved5; /* 0x70 */
241 U32 HCBSize; /* 0x74 */
242 U32 HCBAddressLow; /* 0x78 */
243 U32 HCBAddressHigh; /* 0x7C */
244 U32 Reserved6[12]; /* 0x80 */
245 U32 Scratchpad[4]; /* 0xB0 */
246 U32 RequestDescriptorPostLow; /* 0xC0 */
247 U32 RequestDescriptorPostHigh; /* 0xC4 */
248 U32 Reserved7[14]; /* 0xC8 */
249 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
250 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
253 * Defines for working with the Doorbell register.
255 #define MPI2_DOORBELL_OFFSET (0x00000000)
257 /* IOC --> System values */
258 #define MPI2_DOORBELL_USED (0x08000000)
259 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
260 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
261 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
262 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
264 /* System --> IOC values */
265 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
266 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
267 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
268 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
272 * Defines for the WriteSequence register
274 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
275 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
276 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
277 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
278 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
279 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
280 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
281 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
282 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
285 * Defines for the HostDiagnostic register
287 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
289 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
291 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
292 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
293 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
295 /* Defines for V7A/V7R HostDiagnostic Register */
296 #define MPI26_DIAG_BOOT_DEVICE_SELECT_FLASH64 (0x00000000)
297 #define MPI26_DIAG_BOOT_DEVICE_SELECT_HCDW64 (0x00000800)
298 #define MPI26_DIAG_BOOT_DEVICE_SELECT_FLASH32 (0x00001000)
299 #define MPI26_DIAG_BOOT_DEVICE_SELECT_HCDW32 (0x00001800)
300 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
301 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
302 #define MPI2_DIAG_HCB_MODE (0x00000100)
303 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
304 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
305 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
306 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
307 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
308 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
311 * Offsets for DiagRWData and address
313 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
314 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
315 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
318 * Defines for the HostInterruptStatus register
320 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
321 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
322 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
323 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
324 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
325 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
326 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
329 * Defines for the HostInterruptMask register
331 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
332 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
333 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
334 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
335 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
336 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
339 * Offsets for DCRData and address
341 #define MPI2_DCR_DATA_OFFSET (0x00000038)
342 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
345 * Offset for the Reply Free Queue
347 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
350 * Defines for the Reply Descriptor Post Queue
352 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
353 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
354 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
355 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
356 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */
360 * Defines for the HCBSize and address
362 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
363 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
364 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
366 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
367 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
370 * Offsets for the Scratchpad registers
372 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
373 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
374 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
375 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
378 * Offsets for the Request Descriptor Post Queue
380 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
381 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
384 /* Hard Reset delay timings */
385 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
386 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
387 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
389 /*****************************************************************************
391 * Message Descriptors
393 *****************************************************************************/
395 /* Request Descriptors */
397 /* Default Request Descriptor */
398 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
400 U8 RequestFlags; /* 0x00 */
401 U8 MSIxIndex; /* 0x01 */
404 U16 DescriptorTypeDependent; /* 0x06 */
405 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
406 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
407 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
409 /* defines for the RequestFlags field */
410 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
411 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */
412 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
413 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
414 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
415 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
416 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
417 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
419 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
422 /* High Priority Request Descriptor */
423 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
425 U8 RequestFlags; /* 0x00 */
426 U8 MSIxIndex; /* 0x01 */
429 U16 Reserved1; /* 0x06 */
430 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
431 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
432 Mpi2HighPriorityRequestDescriptor_t,
433 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
436 /* SCSI IO Request Descriptor */
437 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
439 U8 RequestFlags; /* 0x00 */
440 U8 MSIxIndex; /* 0x01 */
443 U16 DevHandle; /* 0x06 */
444 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
445 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
446 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
449 /* SCSI Target Request Descriptor */
450 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
452 U8 RequestFlags; /* 0x00 */
453 U8 MSIxIndex; /* 0x01 */
456 U16 IoIndex; /* 0x06 */
457 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
458 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
459 Mpi2SCSITargetRequestDescriptor_t,
460 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
463 /* RAID Accelerator Request Descriptor */
464 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
466 U8 RequestFlags; /* 0x00 */
467 U8 MSIxIndex; /* 0x01 */
470 U16 Reserved; /* 0x06 */
471 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
472 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
473 Mpi2RAIDAcceleratorRequestDescriptor_t,
474 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
477 /* Fast Path SCSI IO Request Descriptor */
478 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
479 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
480 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
481 Mpi25FastPathSCSIIORequestDescriptor_t,
482 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t;
485 /* union of Request Descriptors */
486 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
488 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
489 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
490 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
491 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
492 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
493 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
495 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
496 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
500 /* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */
503 /* Reply Descriptors */
505 /* Default Reply Descriptor */
506 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
508 U8 ReplyFlags; /* 0x00 */
509 U8 MSIxIndex; /* 0x01 */
510 U16 DescriptorTypeDependent1; /* 0x02 */
511 U32 DescriptorTypeDependent2; /* 0x04 */
512 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
513 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
515 /* defines for the ReplyFlags field */
516 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
517 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
518 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
519 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
520 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
521 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
522 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
523 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
525 /* values for marking a reply descriptor as unused */
526 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
527 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
529 /* Address Reply Descriptor */
530 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
532 U8 ReplyFlags; /* 0x00 */
533 U8 MSIxIndex; /* 0x01 */
535 U32 ReplyFrameAddress; /* 0x04 */
536 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
537 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
539 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
542 /* SCSI IO Success Reply Descriptor */
543 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
545 U8 ReplyFlags; /* 0x00 */
546 U8 MSIxIndex; /* 0x01 */
548 U16 TaskTag; /* 0x04 */
549 U16 Reserved1; /* 0x06 */
550 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
551 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
552 Mpi2SCSIIOSuccessReplyDescriptor_t,
553 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
556 /* TargetAssist Success Reply Descriptor */
557 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
559 U8 ReplyFlags; /* 0x00 */
560 U8 MSIxIndex; /* 0x01 */
562 U8 SequenceNumber; /* 0x04 */
563 U8 Reserved1; /* 0x05 */
564 U16 IoIndex; /* 0x06 */
565 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
566 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
567 Mpi2TargetAssistSuccessReplyDescriptor_t,
568 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
571 /* Target Command Buffer Reply Descriptor */
572 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
574 U8 ReplyFlags; /* 0x00 */
575 U8 MSIxIndex; /* 0x01 */
578 U16 InitiatorDevHandle; /* 0x04 */
579 U16 IoIndex; /* 0x06 */
580 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
581 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
582 Mpi2TargetCommandBufferReplyDescriptor_t,
583 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
585 /* defines for Flags field */
586 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
589 /* RAID Accelerator Success Reply Descriptor */
590 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
592 U8 ReplyFlags; /* 0x00 */
593 U8 MSIxIndex; /* 0x01 */
595 U32 Reserved; /* 0x04 */
596 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
597 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
598 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
599 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
602 /* Fast Path SCSI IO Success Reply Descriptor */
603 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
604 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
605 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
606 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
607 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
610 /* union of Reply Descriptors */
611 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
613 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
614 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
615 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
616 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
617 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
618 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
619 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
621 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
622 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
626 /*****************************************************************************
630 *****************************************************************************/
632 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
633 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
634 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
635 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
636 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
637 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
638 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
639 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
640 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
641 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
642 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
643 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
644 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
645 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
646 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
647 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
648 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
649 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
650 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
651 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */
652 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */
653 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
654 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
655 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
656 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
657 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
658 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
659 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
660 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
661 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */
662 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
663 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
667 /* Doorbell functions */
668 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
669 #define MPI2_FUNCTION_HANDSHAKE (0x42)
672 /*****************************************************************************
676 *****************************************************************************/
678 /* mask for IOCStatus status value */
679 #define MPI2_IOCSTATUS_MASK (0x7FFF)
681 /****************************************************************************
682 * Common IOCStatus values for all replies
683 ****************************************************************************/
685 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
686 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
687 #define MPI2_IOCSTATUS_BUSY (0x0002)
688 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
689 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
690 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
691 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
692 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
693 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
694 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
695 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */
697 /****************************************************************************
698 * Config IOCStatus values
699 ****************************************************************************/
701 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
702 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
703 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
704 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
705 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
706 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
708 /****************************************************************************
710 ****************************************************************************/
712 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
713 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
714 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
715 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
716 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
717 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
718 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
719 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
720 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
721 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
722 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
723 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
725 /****************************************************************************
726 * For use by SCSI Initiator and SCSI Target end-to-end data protection
727 ****************************************************************************/
729 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
730 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
731 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
733 /****************************************************************************
735 ****************************************************************************/
737 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
738 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
739 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
740 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
741 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
742 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
743 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
744 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
745 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
746 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
748 /****************************************************************************
749 * Serial Attached SCSI values
750 ****************************************************************************/
752 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
753 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
755 /****************************************************************************
756 * Diagnostic Buffer Post / Diagnostic Release values
757 ****************************************************************************/
759 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
761 /****************************************************************************
762 * RAID Accelerator values
763 ****************************************************************************/
765 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
767 /****************************************************************************
768 * IOCStatus flag to indicate that log info is available
769 ****************************************************************************/
771 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
773 /****************************************************************************
775 ****************************************************************************/
777 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
778 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
779 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
780 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
781 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
782 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
783 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
784 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
787 /*****************************************************************************
789 * Standard Message Structures
791 *****************************************************************************/
793 /****************************************************************************
794 * Request Message Header for all request messages
795 ****************************************************************************/
797 typedef struct _MPI2_REQUEST_HEADER
799 U16 FunctionDependent1; /* 0x00 */
800 U8 ChainOffset; /* 0x02 */
801 U8 Function; /* 0x03 */
802 U16 FunctionDependent2; /* 0x04 */
803 U8 FunctionDependent3; /* 0x06 */
804 U8 MsgFlags; /* 0x07 */
807 U16 Reserved1; /* 0x0A */
808 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
809 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
812 /****************************************************************************
814 ****************************************************************************/
816 typedef struct _MPI2_DEFAULT_REPLY
818 U16 FunctionDependent1; /* 0x00 */
819 U8 MsgLength; /* 0x02 */
820 U8 Function; /* 0x03 */
821 U16 FunctionDependent2; /* 0x04 */
822 U8 FunctionDependent3; /* 0x06 */
823 U8 MsgFlags; /* 0x07 */
826 U16 Reserved1; /* 0x0A */
827 U16 FunctionDependent5; /* 0x0C */
828 U16 IOCStatus; /* 0x0E */
829 U32 IOCLogInfo; /* 0x10 */
830 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
831 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
834 /* common version structure/union used in messages and configuration pages */
836 typedef struct _MPI2_VERSION_STRUCT
842 } MPI2_VERSION_STRUCT;
844 typedef union _MPI2_VERSION_UNION
846 MPI2_VERSION_STRUCT Struct;
848 } MPI2_VERSION_UNION;
851 /* LUN field defines, common to many structures */
852 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
853 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
854 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
855 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
856 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
857 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
860 /*****************************************************************************
862 * Fusion-MPT MPI Scatter Gather Elements
864 *****************************************************************************/
866 /****************************************************************************
867 * MPI Simple Element structures
868 ****************************************************************************/
870 typedef struct _MPI2_SGE_SIMPLE32
874 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
875 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
877 typedef struct _MPI2_SGE_SIMPLE64
881 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
882 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
884 typedef struct _MPI2_SGE_SIMPLE_UNION
892 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
893 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
896 /****************************************************************************
897 * MPI Chain Element structures - for MPI v2.0 products only
898 ****************************************************************************/
900 typedef struct _MPI2_SGE_CHAIN32
906 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
907 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
909 typedef struct _MPI2_SGE_CHAIN64
915 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
916 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
918 typedef struct _MPI2_SGE_CHAIN_UNION
928 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
929 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
932 /****************************************************************************
933 * MPI Transaction Context Element structures - for MPI v2.0 products only
934 ****************************************************************************/
936 typedef struct _MPI2_SGE_TRANSACTION32
942 U32 TransactionContext[1];
943 U32 TransactionDetails[1];
944 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
945 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
947 typedef struct _MPI2_SGE_TRANSACTION64
953 U32 TransactionContext[2];
954 U32 TransactionDetails[1];
955 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
956 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
958 typedef struct _MPI2_SGE_TRANSACTION96
964 U32 TransactionContext[3];
965 U32 TransactionDetails[1];
966 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
967 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
969 typedef struct _MPI2_SGE_TRANSACTION128
975 U32 TransactionContext[4];
976 U32 TransactionDetails[1];
977 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
978 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
980 typedef struct _MPI2_SGE_TRANSACTION_UNION
988 U32 TransactionContext32[1];
989 U32 TransactionContext64[2];
990 U32 TransactionContext96[3];
991 U32 TransactionContext128[4];
993 U32 TransactionDetails[1];
994 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
995 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
998 /****************************************************************************
999 * MPI SGE union for IO SGL's - for MPI v2.0 products only
1000 ****************************************************************************/
1002 typedef struct _MPI2_MPI_SGE_IO_UNION
1006 MPI2_SGE_SIMPLE_UNION Simple;
1007 MPI2_SGE_CHAIN_UNION Chain;
1009 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
1010 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
1013 /****************************************************************************
1014 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1015 ****************************************************************************/
1017 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
1021 MPI2_SGE_SIMPLE_UNION Simple;
1022 MPI2_SGE_TRANSACTION_UNION Transaction;
1024 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
1025 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
1028 /****************************************************************************
1029 * All MPI SGE types union
1030 ****************************************************************************/
1032 typedef struct _MPI2_MPI_SGE_UNION
1036 MPI2_SGE_SIMPLE_UNION Simple;
1037 MPI2_SGE_CHAIN_UNION Chain;
1038 MPI2_SGE_TRANSACTION_UNION Transaction;
1040 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
1041 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
1044 /****************************************************************************
1045 * MPI SGE field definition and masks
1046 ****************************************************************************/
1048 /* Flags field bit definitions */
1050 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
1051 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
1052 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1053 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1054 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
1055 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1056 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1058 #define MPI2_SGE_FLAGS_SHIFT (24)
1060 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1061 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1065 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */
1066 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1067 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */
1068 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1070 /* Address location */
1072 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1076 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1077 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1079 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1080 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1084 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1085 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1089 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1090 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1091 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1092 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1094 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1095 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
1097 /****************************************************************************
1098 * MPI SGE operation Macros
1099 ****************************************************************************/
1101 /* SIMPLE FlagsLength manipulations... */
1102 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1103 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
1104 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1105 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1107 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
1109 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1110 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1111 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
1113 /* CAUTION - The following are READ-MODIFY-WRITE! */
1114 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
1115 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
1117 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
1120 /*****************************************************************************
1122 * Fusion-MPT IEEE Scatter Gather Elements
1124 *****************************************************************************/
1126 /****************************************************************************
1127 * IEEE Simple Element structures
1128 ****************************************************************************/
1130 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1131 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1135 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1136 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1138 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1145 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1146 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1148 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1150 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1151 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1152 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1153 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1156 /****************************************************************************
1157 * IEEE Chain Element structures
1158 ****************************************************************************/
1160 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1161 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1163 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1164 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1166 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1168 MPI2_IEEE_SGE_CHAIN32 Chain32;
1169 MPI2_IEEE_SGE_CHAIN64 Chain64;
1170 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1171 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1173 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1174 typedef struct _MPI25_IEEE_SGE_CHAIN64
1181 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
1182 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
1185 /****************************************************************************
1186 * All IEEE SGE types union
1187 ****************************************************************************/
1189 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1190 typedef struct _MPI2_IEEE_SGE_UNION
1194 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1195 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1197 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1198 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1201 /****************************************************************************
1202 * IEEE SGE union for IO SGL's
1203 ****************************************************************************/
1205 typedef union _MPI25_SGE_IO_UNION
1207 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1208 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1209 } MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION,
1210 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t;
1213 /****************************************************************************
1214 * IEEE SGE field definitions and masks
1215 ****************************************************************************/
1217 /* Flags field bit definitions */
1219 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1220 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1222 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1224 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1228 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1229 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1231 /* Next Segment Format */
1233 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1234 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1236 /* Data Location Address Space */
1238 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1239 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */
1240 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */
1241 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1242 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */
1243 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */
1244 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1246 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */
1248 /****************************************************************************
1249 * IEEE SGE operation Macros
1250 ****************************************************************************/
1252 /* SIMPLE FlagsLength manipulations... */
1253 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1254 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1255 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1257 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1259 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1260 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1261 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1263 /* CAUTION - The following are READ-MODIFY-WRITE! */
1264 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1265 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1269 /*****************************************************************************
1271 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1273 *****************************************************************************/
1275 typedef union _MPI2_SIMPLE_SGE_UNION
1277 MPI2_SGE_SIMPLE_UNION MpiSimple;
1278 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1279 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1280 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1283 typedef union _MPI2_SGE_IO_UNION
1285 MPI2_SGE_SIMPLE_UNION MpiSimple;
1286 MPI2_SGE_CHAIN_UNION MpiChain;
1287 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1288 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1289 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1290 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1293 /****************************************************************************
1295 * Values for SGLFlags field, used in many request messages with an SGL
1297 ****************************************************************************/
1299 /* values for MPI SGL Data Location Address Space subfield */
1300 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1301 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1302 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1303 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */
1304 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */
1305 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */
1306 /* values for SGL Type subfield */
1307 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1308 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1309 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */
1310 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)