2 * Copyright (c) 2009 Yahoo! Inc.
3 * Copyright (c) 2011-2015 LSI Corp.
4 * Copyright (c) 2013-2016 Avago Technologies
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 /* Communications core for Avago Technologies (LSI) MPT3 */
37 /* TODO Move headers to mprvar */
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/selinfo.h>
44 #include <sys/mutex.h>
45 #include <sys/module.h>
49 #include <sys/malloc.h>
51 #include <sys/sysctl.h>
52 #include <sys/queue.h>
53 #include <sys/kthread.h>
54 #include <sys/taskqueue.h>
55 #include <sys/endian.h>
56 #include <sys/eventhandler.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
63 #include <dev/pci/pcivar.h>
66 #include <cam/cam_ccb.h>
67 #include <cam/scsi/scsi_all.h>
69 #include <dev/mpr/mpi/mpi2_type.h>
70 #include <dev/mpr/mpi/mpi2.h>
71 #include <dev/mpr/mpi/mpi2_ioc.h>
72 #include <dev/mpr/mpi/mpi2_sas.h>
73 #include <dev/mpr/mpi/mpi2_pci.h>
74 #include <dev/mpr/mpi/mpi2_cnfg.h>
75 #include <dev/mpr/mpi/mpi2_init.h>
76 #include <dev/mpr/mpi/mpi2_tool.h>
77 #include <dev/mpr/mpr_ioctl.h>
78 #include <dev/mpr/mprvar.h>
79 #include <dev/mpr/mpr_table.h>
80 #include <dev/mpr/mpr_sas.h>
82 static int mpr_diag_reset(struct mpr_softc *sc, int sleep_flag);
83 static int mpr_init_queues(struct mpr_softc *sc);
84 static int mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag);
85 static int mpr_transition_operational(struct mpr_softc *sc);
86 static int mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching);
87 static void mpr_iocfacts_free(struct mpr_softc *sc);
88 static void mpr_startup(void *arg);
89 static int mpr_send_iocinit(struct mpr_softc *sc);
90 static int mpr_alloc_queues(struct mpr_softc *sc);
91 static int mpr_alloc_replies(struct mpr_softc *sc);
92 static int mpr_alloc_requests(struct mpr_softc *sc);
93 static int mpr_alloc_nvme_prp_pages(struct mpr_softc *sc);
94 static int mpr_attach_log(struct mpr_softc *sc);
95 static __inline void mpr_complete_command(struct mpr_softc *sc,
96 struct mpr_command *cm);
97 static void mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data,
98 MPI2_EVENT_NOTIFICATION_REPLY *reply);
99 static void mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm);
100 static void mpr_periodic(void *);
101 static int mpr_reregister_events(struct mpr_softc *sc);
102 static void mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm);
103 static int mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts);
104 static int mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag);
105 SYSCTL_NODE(_hw, OID_AUTO, mpr, CTLFLAG_RD, 0, "MPR Driver Parameters");
107 MALLOC_DEFINE(M_MPR, "mpr", "mpr driver memory");
110 * Do a "Diagnostic Reset" aka a hard reset. This should get the chip out of
111 * any state and back to its initialization state machine.
113 static char mpt2_reset_magic[] = { 0x00, 0x0f, 0x04, 0x0b, 0x02, 0x07, 0x0d };
116 * Added this union to smoothly convert le64toh cm->cm_desc.Words.
117 * Compiler only supports uint64_t to be passed as an argument.
118 * Otherwise it will through this error:
119 * "aggregate value used where an integer was expected"
121 typedef union _reply_descriptor {
127 } reply_descriptor, request_descriptor;
129 /* Rate limit chain-fail messages to 1 per minute */
130 static struct timeval mpr_chainfail_interval = { 60, 0 };
133 * sleep_flag can be either CAN_SLEEP or NO_SLEEP.
134 * If this function is called from process context, it can sleep
135 * and there is no harm to sleep, in case if this fuction is called
136 * from Interrupt handler, we can not sleep and need NO_SLEEP flag set.
137 * based on sleep flags driver will call either msleep, pause or DELAY.
138 * msleep and pause are of same variant, but pause is used when mpr_mtx
139 * is not hold by driver.
142 mpr_diag_reset(struct mpr_softc *sc,int sleep_flag)
145 int i, error, tries = 0;
146 uint8_t first_wait_done = FALSE;
148 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
150 /* Clear any pending interrupts */
151 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
154 * Force NO_SLEEP for threads prohibited to sleep
155 * e.a Thread from interrupt handler are prohibited to sleep.
157 #if __FreeBSD_version >= 1000029
158 if (curthread->td_no_sleeping)
159 #else //__FreeBSD_version < 1000029
160 if (curthread->td_pflags & TDP_NOSLEEPING)
161 #endif //__FreeBSD_version >= 1000029
162 sleep_flag = NO_SLEEP;
164 /* Push the magic sequence */
166 while (tries++ < 20) {
167 for (i = 0; i < sizeof(mpt2_reset_magic); i++)
168 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET,
169 mpt2_reset_magic[i]);
172 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
173 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
175 else if (sleep_flag == CAN_SLEEP)
176 pause("mprdiag", hz/10);
180 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);
181 if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) {
189 /* Send the actual reset. XXX need to refresh the reg? */
190 mpr_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET,
191 reg | MPI2_DIAG_RESET_ADAPTER);
193 /* Wait up to 300 seconds in 50ms intervals */
195 for (i = 0; i < 6000; i++) {
197 * Wait 50 msec. If this is the first time through, wait 256
198 * msec to satisfy Diag Reset timing requirements.
200 if (first_wait_done) {
201 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
202 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
204 else if (sleep_flag == CAN_SLEEP)
205 pause("mprdiag", hz/20);
210 first_wait_done = TRUE;
213 * Check for the RESET_ADAPTER bit to be cleared first, then
214 * wait for the RESET state to be cleared, which takes a little
217 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);
218 if (reg & MPI2_DIAG_RESET_ADAPTER) {
221 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
222 if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) {
230 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 0x0);
236 mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag)
241 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET,
242 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET <<
243 MPI2_DOORBELL_FUNCTION_SHIFT);
245 if (mpr_wait_db_ack(sc, 5, sleep_flag) != 0) {
246 mpr_dprint(sc, MPR_FAULT, "Doorbell handshake failed : <%s>\n",
255 mpr_transition_ready(struct mpr_softc *sc)
258 int error, tries = 0;
262 /* If we are in attach call, do not sleep */
263 sleep_flags = (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE)
264 ? CAN_SLEEP : NO_SLEEP;
267 while (tries++ < 1200) {
268 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
269 mpr_dprint(sc, MPR_INIT, "Doorbell= 0x%x\n", reg);
272 * Ensure the IOC is ready to talk. If it's not, try
275 if (reg & MPI2_DOORBELL_USED) {
276 mpr_diag_reset(sc, sleep_flags);
281 /* Is the adapter owned by another peer? */
282 if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) ==
283 (MPI2_WHOINIT_PCI_PEER << MPI2_DOORBELL_WHO_INIT_SHIFT)) {
284 device_printf(sc->mpr_dev, "IOC is under the control "
285 "of another peer host, aborting initialization.\n");
289 state = reg & MPI2_IOC_STATE_MASK;
290 if (state == MPI2_IOC_STATE_READY) {
294 } else if (state == MPI2_IOC_STATE_FAULT) {
295 mpr_dprint(sc, MPR_FAULT, "IOC in fault state 0x%x\n",
296 state & MPI2_DOORBELL_FAULT_CODE_MASK);
297 mpr_diag_reset(sc, sleep_flags);
298 } else if (state == MPI2_IOC_STATE_OPERATIONAL) {
299 /* Need to take ownership */
300 mpr_message_unit_reset(sc, sleep_flags);
301 } else if (state == MPI2_IOC_STATE_RESET) {
302 /* Wait a bit, IOC might be in transition */
303 mpr_dprint(sc, MPR_FAULT,
304 "IOC in unexpected reset state\n");
306 mpr_dprint(sc, MPR_FAULT,
307 "IOC in unknown state 0x%x\n", state);
312 /* Wait 50ms for things to settle down. */
317 device_printf(sc->mpr_dev, "Cannot transition IOC to ready\n");
322 mpr_transition_operational(struct mpr_softc *sc)
330 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
331 mpr_dprint(sc, MPR_INIT, "Doorbell= 0x%x\n", reg);
333 state = reg & MPI2_IOC_STATE_MASK;
334 if (state != MPI2_IOC_STATE_READY) {
335 if ((error = mpr_transition_ready(sc)) != 0) {
336 mpr_dprint(sc, MPR_FAULT,
337 "%s failed to transition ready\n", __func__);
342 error = mpr_send_iocinit(sc);
347 * This is called during attach and when re-initializing due to a Diag Reset.
348 * IOC Facts is used to allocate many of the structures needed by the driver.
349 * If called from attach, de-allocation is not required because the driver has
350 * not allocated any structures yet, but if called from a Diag Reset, previously
351 * allocated structures based on IOC Facts will need to be freed and re-
352 * allocated bases on the latest IOC Facts.
355 mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching)
358 Mpi2IOCFactsReply_t saved_facts;
359 uint8_t saved_mode, reallocating;
361 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
363 /* Save old IOC Facts and then only reallocate if Facts have changed */
365 bcopy(sc->facts, &saved_facts, sizeof(MPI2_IOC_FACTS_REPLY));
369 * Get IOC Facts. In all cases throughout this function, panic if doing
370 * a re-initialization and only return the error if attaching so the OS
373 if ((error = mpr_get_iocfacts(sc, sc->facts)) != 0) {
375 mpr_dprint(sc, MPR_FAULT, "%s failed to get IOC Facts "
376 "with error %d\n", __func__, error);
379 panic("%s failed to get IOC Facts with error %d\n",
384 mpr_print_iocfacts(sc, sc->facts);
386 snprintf(sc->fw_version, sizeof(sc->fw_version),
387 "%02d.%02d.%02d.%02d",
388 sc->facts->FWVersion.Struct.Major,
389 sc->facts->FWVersion.Struct.Minor,
390 sc->facts->FWVersion.Struct.Unit,
391 sc->facts->FWVersion.Struct.Dev);
393 mpr_printf(sc, "Firmware: %s, Driver: %s\n", sc->fw_version,
395 mpr_printf(sc, "IOCCapabilities: %b\n", sc->facts->IOCCapabilities,
396 "\20" "\3ScsiTaskFull" "\4DiagTrace" "\5SnapBuf" "\6ExtBuf"
397 "\7EEDP" "\10BiDirTarg" "\11Multicast" "\14TransRetry" "\15IR"
398 "\16EventReplay" "\17RaidAccel" "\20MSIXIndex" "\21HostDisc"
399 "\22FastPath" "\23RDPQArray" "\24AtomicReqDesc" "\25PCIeSRIOV");
402 * If the chip doesn't support event replay then a hard reset will be
403 * required to trigger a full discovery. Do the reset here then
404 * retransition to Ready. A hard reset might have already been done,
405 * but it doesn't hurt to do it again. Only do this if attaching, not
409 if ((sc->facts->IOCCapabilities &
410 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY) == 0) {
411 mpr_diag_reset(sc, NO_SLEEP);
412 if ((error = mpr_transition_ready(sc)) != 0) {
413 mpr_dprint(sc, MPR_FAULT, "%s failed to "
414 "transition to ready with error %d\n",
422 * Set flag if IR Firmware is loaded. If the RAID Capability has
423 * changed from the previous IOC Facts, log a warning, but only if
424 * checking this after a Diag Reset and not during attach.
426 saved_mode = sc->ir_firmware;
427 if (sc->facts->IOCCapabilities &
428 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)
431 if (sc->ir_firmware != saved_mode) {
432 mpr_dprint(sc, MPR_FAULT, "%s new IR/IT mode in IOC "
433 "Facts does not match previous mode\n", __func__);
437 /* Only deallocate and reallocate if relevant IOC Facts have changed */
438 reallocating = FALSE;
440 ((saved_facts.MsgVersion != sc->facts->MsgVersion) ||
441 (saved_facts.HeaderVersion != sc->facts->HeaderVersion) ||
442 (saved_facts.MaxChainDepth != sc->facts->MaxChainDepth) ||
443 (saved_facts.RequestCredit != sc->facts->RequestCredit) ||
444 (saved_facts.ProductID != sc->facts->ProductID) ||
445 (saved_facts.IOCCapabilities != sc->facts->IOCCapabilities) ||
446 (saved_facts.IOCRequestFrameSize !=
447 sc->facts->IOCRequestFrameSize) ||
448 (saved_facts.IOCMaxChainSegmentSize !=
449 sc->facts->IOCMaxChainSegmentSize) ||
450 (saved_facts.MaxTargets != sc->facts->MaxTargets) ||
451 (saved_facts.MaxSasExpanders != sc->facts->MaxSasExpanders) ||
452 (saved_facts.MaxEnclosures != sc->facts->MaxEnclosures) ||
453 (saved_facts.HighPriorityCredit != sc->facts->HighPriorityCredit) ||
454 (saved_facts.MaxReplyDescriptorPostQueueDepth !=
455 sc->facts->MaxReplyDescriptorPostQueueDepth) ||
456 (saved_facts.ReplyFrameSize != sc->facts->ReplyFrameSize) ||
457 (saved_facts.MaxVolumes != sc->facts->MaxVolumes) ||
458 (saved_facts.MaxPersistentEntries !=
459 sc->facts->MaxPersistentEntries))) {
464 * Some things should be done if attaching or re-allocating after a Diag
465 * Reset, but are not needed after a Diag Reset if the FW has not
468 if (attaching || reallocating) {
470 * Check if controller supports FW diag buffers and set flag to
473 if (sc->facts->IOCCapabilities &
474 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER)
475 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_TRACE].
477 if (sc->facts->IOCCapabilities &
478 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER)
479 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_SNAPSHOT].
481 if (sc->facts->IOCCapabilities &
482 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER)
483 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_EXTENDED].
487 * Set flags for some supported items.
489 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP)
490 sc->eedp_enabled = TRUE;
491 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR)
492 sc->control_TLR = TRUE;
493 if (sc->facts->IOCCapabilities &
494 MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
495 sc->atomic_desc_capable = TRUE;
498 * Size the queues. Since the reply queues always need one free
499 * entry, we'll just deduct one reply message here.
501 sc->num_reqs = MIN(MPR_REQ_FRAMES, sc->facts->RequestCredit);
502 sc->num_replies = MIN(MPR_REPLY_FRAMES + MPR_EVT_REPLY_FRAMES,
503 sc->facts->MaxReplyDescriptorPostQueueDepth) - 1;
506 * Initialize all Tail Queues
508 TAILQ_INIT(&sc->req_list);
509 TAILQ_INIT(&sc->high_priority_req_list);
510 TAILQ_INIT(&sc->chain_list);
511 TAILQ_INIT(&sc->prp_page_list);
512 TAILQ_INIT(&sc->tm_list);
516 * If doing a Diag Reset and the FW is significantly different
517 * (reallocating will be set above in IOC Facts comparison), then all
518 * buffers based on the IOC Facts will need to be freed before they are
522 mpr_iocfacts_free(sc);
523 mprsas_realloc_targets(sc, saved_facts.MaxTargets +
524 saved_facts.MaxVolumes);
528 * Any deallocation has been completed. Now start reallocating
529 * if needed. Will only need to reallocate if attaching or if the new
530 * IOC Facts are different from the previous IOC Facts after a Diag
531 * Reset. Targets have already been allocated above if needed.
533 if (attaching || reallocating) {
534 if (((error = mpr_alloc_queues(sc)) != 0) ||
535 ((error = mpr_alloc_replies(sc)) != 0) ||
536 ((error = mpr_alloc_requests(sc)) != 0)) {
538 mpr_dprint(sc, MPR_FAULT, "%s failed to alloc "
539 "queues with error %d\n", __func__, error);
543 panic("%s failed to alloc queues with error "
544 "%d\n", __func__, error);
549 /* Always initialize the queues */
550 bzero(sc->free_queue, sc->fqdepth * 4);
554 * Always get the chip out of the reset state, but only panic if not
555 * attaching. If attaching and there is an error, that is handled by
558 error = mpr_transition_operational(sc);
561 mpr_printf(sc, "%s failed to transition to operational "
562 "with error %d\n", __func__, error);
566 panic("%s failed to transition to operational with "
567 "error %d\n", __func__, error);
572 * Finish the queue initialization.
573 * These are set here instead of in mpr_init_queues() because the
574 * IOC resets these values during the state transition in
575 * mpr_transition_operational(). The free index is set to 1
576 * because the corresponding index in the IOC is set to 0, and the
577 * IOC treats the queues as full if both are set to the same value.
578 * Hence the reason that the queue can't hold all of the possible
581 sc->replypostindex = 0;
582 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex);
583 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 0);
586 * Attach the subsystems so they can prepare their event masks.
588 /* XXX Should be dynamic so that IM/IR and user modules can attach */
590 if (((error = mpr_attach_log(sc)) != 0) ||
591 ((error = mpr_attach_sas(sc)) != 0) ||
592 ((error = mpr_attach_user(sc)) != 0)) {
593 mpr_printf(sc, "%s failed to attach all subsystems: "
594 "error %d\n", __func__, error);
599 if ((error = mpr_pci_setup_interrupts(sc)) != 0) {
600 mpr_printf(sc, "%s failed to setup interrupts\n",
611 * This is called if memory is being free (during detach for example) and when
612 * buffers need to be reallocated due to a Diag Reset.
615 mpr_iocfacts_free(struct mpr_softc *sc)
617 struct mpr_command *cm;
620 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
622 if (sc->free_busaddr != 0)
623 bus_dmamap_unload(sc->queues_dmat, sc->queues_map);
624 if (sc->free_queue != NULL)
625 bus_dmamem_free(sc->queues_dmat, sc->free_queue,
627 if (sc->queues_dmat != NULL)
628 bus_dma_tag_destroy(sc->queues_dmat);
630 if (sc->chain_busaddr != 0)
631 bus_dmamap_unload(sc->chain_dmat, sc->chain_map);
632 if (sc->chain_frames != NULL)
633 bus_dmamem_free(sc->chain_dmat, sc->chain_frames,
635 if (sc->chain_dmat != NULL)
636 bus_dma_tag_destroy(sc->chain_dmat);
638 if (sc->sense_busaddr != 0)
639 bus_dmamap_unload(sc->sense_dmat, sc->sense_map);
640 if (sc->sense_frames != NULL)
641 bus_dmamem_free(sc->sense_dmat, sc->sense_frames,
643 if (sc->sense_dmat != NULL)
644 bus_dma_tag_destroy(sc->sense_dmat);
646 if (sc->prp_page_busaddr != 0)
647 bus_dmamap_unload(sc->prp_page_dmat, sc->prp_page_map);
648 if (sc->prp_pages != NULL)
649 bus_dmamem_free(sc->prp_page_dmat, sc->prp_pages,
651 if (sc->prp_page_dmat != NULL)
652 bus_dma_tag_destroy(sc->prp_page_dmat);
654 if (sc->reply_busaddr != 0)
655 bus_dmamap_unload(sc->reply_dmat, sc->reply_map);
656 if (sc->reply_frames != NULL)
657 bus_dmamem_free(sc->reply_dmat, sc->reply_frames,
659 if (sc->reply_dmat != NULL)
660 bus_dma_tag_destroy(sc->reply_dmat);
662 if (sc->req_busaddr != 0)
663 bus_dmamap_unload(sc->req_dmat, sc->req_map);
664 if (sc->req_frames != NULL)
665 bus_dmamem_free(sc->req_dmat, sc->req_frames, sc->req_map);
666 if (sc->req_dmat != NULL)
667 bus_dma_tag_destroy(sc->req_dmat);
669 if (sc->chains != NULL)
670 free(sc->chains, M_MPR);
671 if (sc->prps != NULL)
672 free(sc->prps, M_MPR);
673 if (sc->commands != NULL) {
674 for (i = 1; i < sc->num_reqs; i++) {
675 cm = &sc->commands[i];
676 bus_dmamap_destroy(sc->buffer_dmat, cm->cm_dmamap);
678 free(sc->commands, M_MPR);
680 if (sc->buffer_dmat != NULL)
681 bus_dma_tag_destroy(sc->buffer_dmat);
685 * The terms diag reset and hard reset are used interchangeably in the MPI
686 * docs to mean resetting the controller chip. In this code diag reset
687 * cleans everything up, and the hard reset function just sends the reset
688 * sequence to the chip. This should probably be refactored so that every
689 * subsystem gets a reset notification of some sort, and can clean up
693 mpr_reinit(struct mpr_softc *sc)
696 struct mprsas_softc *sassc;
702 mtx_assert(&sc->mpr_mtx, MA_OWNED);
704 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) {
705 mpr_dprint(sc, MPR_INIT, "%s reset already in progress\n",
710 mpr_dprint(sc, MPR_INFO, "Reinitializing controller,\n");
711 /* make sure the completion callbacks can recognize they're getting
712 * a NULL cm_reply due to a reset.
714 sc->mpr_flags |= MPR_FLAGS_DIAGRESET;
717 * Mask interrupts here.
719 mpr_dprint(sc, MPR_INIT, "%s mask interrupts\n", __func__);
722 error = mpr_diag_reset(sc, CAN_SLEEP);
724 panic("%s hard reset failed with error %d\n", __func__, error);
727 /* Restore the PCI state, including the MSI-X registers */
730 /* Give the I/O subsystem special priority to get itself prepared */
731 mprsas_handle_reinit(sc);
734 * Get IOC Facts and allocate all structures based on this information.
735 * The attach function will also call mpr_iocfacts_allocate at startup.
736 * If relevant values have changed in IOC Facts, this function will free
737 * all of the memory based on IOC Facts and reallocate that memory.
739 if ((error = mpr_iocfacts_allocate(sc, FALSE)) != 0) {
740 panic("%s IOC Facts based allocation failed with error %d\n",
745 * Mapping structures will be re-allocated after getting IOC Page8, so
746 * free these structures here.
748 mpr_mapping_exit(sc);
751 * The static page function currently read is IOC Page8. Others can be
752 * added in future. It's possible that the values in IOC Page8 have
753 * changed after a Diag Reset due to user modification, so always read
754 * these. Interrupts are masked, so unmask them before getting config
758 sc->mpr_flags &= ~MPR_FLAGS_DIAGRESET;
759 mpr_base_static_config_pages(sc);
762 * Some mapping info is based in IOC Page8 data, so re-initialize the
765 mpr_mapping_initialize(sc);
768 * Restart will reload the event masks clobbered by the reset, and
769 * then enable the port.
771 mpr_reregister_events(sc);
773 /* the end of discovery will release the simq, so we're done. */
774 mpr_dprint(sc, MPR_INFO, "%s finished sc %p post %u free %u\n",
775 __func__, sc, sc->replypostindex, sc->replyfreeindex);
776 mprsas_release_simq_reinit(sassc);
781 /* Wait for the chip to ACK a word that we've put into its FIFO
782 * Wait for <timeout> seconds. In single loop wait for busy loop
783 * for 500 microseconds.
784 * Total is [ 0.5 * (2000 * <timeout>) ] in miliseconds.
787 mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag)
794 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
796 int_status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET);
797 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
798 mpr_dprint(sc, MPR_INIT, "%s: successful count(%d), "
799 "timeout(%d)\n", __func__, count, timeout);
801 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
802 doorbell = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
803 if ((doorbell & MPI2_IOC_STATE_MASK) ==
804 MPI2_IOC_STATE_FAULT) {
805 mpr_dprint(sc, MPR_FAULT,
806 "fault_state(0x%04x)!\n", doorbell);
809 } else if (int_status == 0xFFFFFFFF)
813 * If it can sleep, sleep for 1 milisecond, else busy loop for
816 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
817 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, "mprdba",
819 else if (sleep_flag == CAN_SLEEP)
820 pause("mprdba", hz/1000);
827 mpr_dprint(sc, MPR_FAULT, "%s: failed due to timeout count(%d), "
828 "int_status(%x)!\n", __func__, count, int_status);
832 /* Wait for the chip to signal that the next word in its FIFO can be fetched */
834 mpr_wait_db_int(struct mpr_softc *sc)
838 for (retry = 0; retry < MPR_DB_MAX_WAIT; retry++) {
839 if ((mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET) &
840 MPI2_HIS_IOC2SYS_DB_STATUS) != 0)
847 /* Step through the synchronous command state machine, i.e. "Doorbell mode" */
849 mpr_request_sync(struct mpr_softc *sc, void *req, MPI2_DEFAULT_REPLY *reply,
850 int req_sz, int reply_sz, int timeout)
854 int i, count, ioc_sz, residual;
855 int sleep_flags = CAN_SLEEP;
857 #if __FreeBSD_version >= 1000029
858 if (curthread->td_no_sleeping)
859 #else //__FreeBSD_version < 1000029
860 if (curthread->td_pflags & TDP_NOSLEEPING)
861 #endif //__FreeBSD_version >= 1000029
862 sleep_flags = NO_SLEEP;
865 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
868 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED)
872 * Announce that a message is coming through the doorbell. Messages
873 * are pushed at 32bit words, so round up if needed.
875 count = (req_sz + 3) / 4;
876 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET,
877 (MPI2_FUNCTION_HANDSHAKE << MPI2_DOORBELL_FUNCTION_SHIFT) |
878 (count << MPI2_DOORBELL_ADD_DWORDS_SHIFT));
881 if (mpr_wait_db_int(sc) ||
882 (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) == 0) {
883 mpr_dprint(sc, MPR_FAULT, "Doorbell failed to activate\n");
886 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
887 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) {
888 mpr_dprint(sc, MPR_FAULT, "Doorbell handshake failed\n");
893 /* Clock out the message data synchronously in 32-bit dwords*/
894 data32 = (uint32_t *)req;
895 for (i = 0; i < count; i++) {
896 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, htole32(data32[i]));
897 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) {
898 mpr_dprint(sc, MPR_FAULT,
899 "Timeout while writing doorbell\n");
905 /* Clock in the reply in 16-bit words. The total length of the
906 * message is always in the 4th byte, so clock out the first 2 words
907 * manually, then loop the rest.
909 data16 = (uint16_t *)reply;
910 if (mpr_wait_db_int(sc) != 0) {
911 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 0\n");
915 mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_DATA_MASK;
916 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
917 if (mpr_wait_db_int(sc) != 0) {
918 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 1\n");
922 mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_DATA_MASK;
923 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
925 /* Number of 32bit words in the message */
926 ioc_sz = reply->MsgLength;
929 * Figure out how many 16bit words to clock in without overrunning.
930 * The precision loss with dividing reply_sz can safely be
931 * ignored because the messages can only be multiples of 32bits.
934 count = MIN((reply_sz / 4), ioc_sz) * 2;
935 if (count < ioc_sz * 2) {
936 residual = ioc_sz * 2 - count;
937 mpr_dprint(sc, MPR_ERROR, "Driver error, throwing away %d "
938 "residual message words\n", residual);
941 for (i = 2; i < count; i++) {
942 if (mpr_wait_db_int(sc) != 0) {
943 mpr_dprint(sc, MPR_FAULT,
944 "Timeout reading doorbell %d\n", i);
947 data16[i] = mpr_regread(sc, MPI2_DOORBELL_OFFSET) &
948 MPI2_DOORBELL_DATA_MASK;
949 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
953 * Pull out residual words that won't fit into the provided buffer.
954 * This keeps the chip from hanging due to a driver programming
958 if (mpr_wait_db_int(sc) != 0) {
959 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell\n");
962 (void)mpr_regread(sc, MPI2_DOORBELL_OFFSET);
963 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
967 if (mpr_wait_db_int(sc) != 0) {
968 mpr_dprint(sc, MPR_FAULT, "Timeout waiting to exit doorbell\n");
971 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED)
972 mpr_dprint(sc, MPR_FAULT, "Warning, doorbell still active\n");
973 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
979 mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm)
981 request_descriptor rd;
984 mpr_dprint(sc, MPR_TRACE, "SMID %u cm %p ccb %p\n",
985 cm->cm_desc.Default.SMID, cm, cm->cm_ccb);
987 if (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE && !(sc->mpr_flags &
989 mtx_assert(&sc->mpr_mtx, MA_OWNED);
991 if (++sc->io_cmds_active > sc->io_cmds_highwater)
992 sc->io_cmds_highwater++;
994 if (sc->atomic_desc_capable) {
995 rd.u.low = cm->cm_desc.Words.Low;
996 mpr_regwrite(sc, MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET,
999 rd.u.low = cm->cm_desc.Words.Low;
1000 rd.u.high = cm->cm_desc.Words.High;
1001 rd.word = htole64(rd.word);
1002 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET,
1004 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET,
1010 * Just the FACTS, ma'am.
1013 mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts)
1015 MPI2_DEFAULT_REPLY *reply;
1016 MPI2_IOC_FACTS_REQUEST request;
1017 int error, req_sz, reply_sz;
1021 req_sz = sizeof(MPI2_IOC_FACTS_REQUEST);
1022 reply_sz = sizeof(MPI2_IOC_FACTS_REPLY);
1023 reply = (MPI2_DEFAULT_REPLY *)facts;
1025 bzero(&request, req_sz);
1026 request.Function = MPI2_FUNCTION_IOC_FACTS;
1027 error = mpr_request_sync(sc, &request, reply, req_sz, reply_sz, 5);
1033 mpr_send_iocinit(struct mpr_softc *sc)
1035 MPI2_IOC_INIT_REQUEST init;
1036 MPI2_DEFAULT_REPLY reply;
1037 int req_sz, reply_sz, error;
1039 uint64_t time_in_msec;
1043 req_sz = sizeof(MPI2_IOC_INIT_REQUEST);
1044 reply_sz = sizeof(MPI2_IOC_INIT_REPLY);
1045 bzero(&init, req_sz);
1046 bzero(&reply, reply_sz);
1049 * Fill in the init block. Note that most addresses are
1050 * deliberately in the lower 32bits of memory. This is a micro-
1051 * optimzation for PCI/PCIX, though it's not clear if it helps PCIe.
1053 init.Function = MPI2_FUNCTION_IOC_INIT;
1054 init.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
1055 init.MsgVersion = htole16(MPI2_VERSION);
1056 init.HeaderVersion = htole16(MPI2_HEADER_VERSION);
1057 init.SystemRequestFrameSize = htole16(sc->facts->IOCRequestFrameSize);
1058 init.ReplyDescriptorPostQueueDepth = htole16(sc->pqdepth);
1059 init.ReplyFreeQueueDepth = htole16(sc->fqdepth);
1060 init.SenseBufferAddressHigh = 0;
1061 init.SystemReplyAddressHigh = 0;
1062 init.SystemRequestFrameBaseAddress.High = 0;
1063 init.SystemRequestFrameBaseAddress.Low =
1064 htole32((uint32_t)sc->req_busaddr);
1065 init.ReplyDescriptorPostQueueAddress.High = 0;
1066 init.ReplyDescriptorPostQueueAddress.Low =
1067 htole32((uint32_t)sc->post_busaddr);
1068 init.ReplyFreeQueueAddress.High = 0;
1069 init.ReplyFreeQueueAddress.Low = htole32((uint32_t)sc->free_busaddr);
1071 time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000);
1072 init.TimeStamp.High = htole32((time_in_msec >> 32) & 0xFFFFFFFF);
1073 init.TimeStamp.Low = htole32(time_in_msec & 0xFFFFFFFF);
1074 init.HostPageSize = HOST_PAGE_SIZE_4K;
1076 error = mpr_request_sync(sc, &init, &reply, req_sz, reply_sz, 5);
1077 if ((reply.IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS)
1080 mpr_dprint(sc, MPR_INIT, "IOCInit status= 0x%x\n", reply.IOCStatus);
1085 mpr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1090 *addr = segs[0].ds_addr;
1094 mpr_alloc_queues(struct mpr_softc *sc)
1096 bus_addr_t queues_busaddr;
1098 int qsize, fqsize, pqsize;
1101 * The reply free queue contains 4 byte entries in multiples of 16 and
1102 * aligned on a 16 byte boundary. There must always be an unused entry.
1103 * This queue supplies fresh reply frames for the firmware to use.
1105 * The reply descriptor post queue contains 8 byte entries in
1106 * multiples of 16 and aligned on a 16 byte boundary. This queue
1107 * contains filled-in reply frames sent from the firmware to the host.
1109 * These two queues are allocated together for simplicity.
1111 sc->fqdepth = roundup2((sc->num_replies + 1), 16);
1112 sc->pqdepth = roundup2((sc->num_replies + 1), 16);
1113 fqsize= sc->fqdepth * 4;
1114 pqsize = sc->pqdepth * 8;
1115 qsize = fqsize + pqsize;
1117 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */
1118 16, 0, /* algnmnt, boundary */
1119 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1120 BUS_SPACE_MAXADDR, /* highaddr */
1121 NULL, NULL, /* filter, filterarg */
1122 qsize, /* maxsize */
1124 qsize, /* maxsegsize */
1126 NULL, NULL, /* lockfunc, lockarg */
1127 &sc->queues_dmat)) {
1128 device_printf(sc->mpr_dev, "Cannot allocate queues DMA tag\n");
1131 if (bus_dmamem_alloc(sc->queues_dmat, (void **)&queues, BUS_DMA_NOWAIT,
1133 device_printf(sc->mpr_dev, "Cannot allocate queues memory\n");
1136 bzero(queues, qsize);
1137 bus_dmamap_load(sc->queues_dmat, sc->queues_map, queues, qsize,
1138 mpr_memaddr_cb, &queues_busaddr, 0);
1140 sc->free_queue = (uint32_t *)queues;
1141 sc->free_busaddr = queues_busaddr;
1142 sc->post_queue = (MPI2_REPLY_DESCRIPTORS_UNION *)(queues + fqsize);
1143 sc->post_busaddr = queues_busaddr + fqsize;
1149 mpr_alloc_replies(struct mpr_softc *sc)
1151 int rsize, num_replies;
1154 * sc->num_replies should be one less than sc->fqdepth. We need to
1155 * allocate space for sc->fqdepth replies, but only sc->num_replies
1156 * replies can be used at once.
1158 num_replies = max(sc->fqdepth, sc->num_replies);
1160 rsize = sc->facts->ReplyFrameSize * num_replies * 4;
1161 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */
1162 4, 0, /* algnmnt, boundary */
1163 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1164 BUS_SPACE_MAXADDR, /* highaddr */
1165 NULL, NULL, /* filter, filterarg */
1166 rsize, /* maxsize */
1168 rsize, /* maxsegsize */
1170 NULL, NULL, /* lockfunc, lockarg */
1172 device_printf(sc->mpr_dev, "Cannot allocate replies DMA tag\n");
1175 if (bus_dmamem_alloc(sc->reply_dmat, (void **)&sc->reply_frames,
1176 BUS_DMA_NOWAIT, &sc->reply_map)) {
1177 device_printf(sc->mpr_dev, "Cannot allocate replies memory\n");
1180 bzero(sc->reply_frames, rsize);
1181 bus_dmamap_load(sc->reply_dmat, sc->reply_map, sc->reply_frames, rsize,
1182 mpr_memaddr_cb, &sc->reply_busaddr, 0);
1188 mpr_alloc_requests(struct mpr_softc *sc)
1190 struct mpr_command *cm;
1191 struct mpr_chain *chain;
1192 int i, rsize, nsegs;
1194 rsize = sc->facts->IOCRequestFrameSize * sc->num_reqs * 4;
1195 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */
1196 16, 0, /* algnmnt, boundary */
1197 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1198 BUS_SPACE_MAXADDR, /* highaddr */
1199 NULL, NULL, /* filter, filterarg */
1200 rsize, /* maxsize */
1202 rsize, /* maxsegsize */
1204 NULL, NULL, /* lockfunc, lockarg */
1206 device_printf(sc->mpr_dev, "Cannot allocate request DMA tag\n");
1209 if (bus_dmamem_alloc(sc->req_dmat, (void **)&sc->req_frames,
1210 BUS_DMA_NOWAIT, &sc->req_map)) {
1211 device_printf(sc->mpr_dev, "Cannot allocate request memory\n");
1214 bzero(sc->req_frames, rsize);
1215 bus_dmamap_load(sc->req_dmat, sc->req_map, sc->req_frames, rsize,
1216 mpr_memaddr_cb, &sc->req_busaddr, 0);
1219 * Gen3 and beyond uses the IOCMaxChainSegmentSize from IOC Facts to
1220 * get the size of a Chain Frame. Previous versions use the size as a
1221 * Request Frame for the Chain Frame size. If IOCMaxChainSegmentSize
1222 * is 0, use the default value. The IOCMaxChainSegmentSize is the
1223 * number of 16-byte elelements that can fit in a Chain Frame, which is
1224 * the size of an IEEE Simple SGE.
1226 if (sc->facts->MsgVersion >= MPI2_VERSION_02_05) {
1227 sc->chain_seg_size =
1228 htole16(sc->facts->IOCMaxChainSegmentSize);
1229 if (sc->chain_seg_size == 0) {
1230 sc->chain_frame_size = MPR_DEFAULT_CHAIN_SEG_SIZE *
1231 MPR_MAX_CHAIN_ELEMENT_SIZE;
1233 sc->chain_frame_size = sc->chain_seg_size *
1234 MPR_MAX_CHAIN_ELEMENT_SIZE;
1237 sc->chain_frame_size = sc->facts->IOCRequestFrameSize * 4;
1239 rsize = sc->chain_frame_size * sc->max_chains;
1240 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */
1241 16, 0, /* algnmnt, boundary */
1242 BUS_SPACE_MAXADDR, /* lowaddr */
1243 BUS_SPACE_MAXADDR, /* highaddr */
1244 NULL, NULL, /* filter, filterarg */
1245 rsize, /* maxsize */
1247 rsize, /* maxsegsize */
1249 NULL, NULL, /* lockfunc, lockarg */
1251 device_printf(sc->mpr_dev, "Cannot allocate chain DMA tag\n");
1254 if (bus_dmamem_alloc(sc->chain_dmat, (void **)&sc->chain_frames,
1255 BUS_DMA_NOWAIT, &sc->chain_map)) {
1256 device_printf(sc->mpr_dev, "Cannot allocate chain memory\n");
1259 bzero(sc->chain_frames, rsize);
1260 bus_dmamap_load(sc->chain_dmat, sc->chain_map, sc->chain_frames, rsize,
1261 mpr_memaddr_cb, &sc->chain_busaddr, 0);
1263 rsize = MPR_SENSE_LEN * sc->num_reqs;
1264 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */
1265 1, 0, /* algnmnt, boundary */
1266 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1267 BUS_SPACE_MAXADDR, /* highaddr */
1268 NULL, NULL, /* filter, filterarg */
1269 rsize, /* maxsize */
1271 rsize, /* maxsegsize */
1273 NULL, NULL, /* lockfunc, lockarg */
1275 device_printf(sc->mpr_dev, "Cannot allocate sense DMA tag\n");
1278 if (bus_dmamem_alloc(sc->sense_dmat, (void **)&sc->sense_frames,
1279 BUS_DMA_NOWAIT, &sc->sense_map)) {
1280 device_printf(sc->mpr_dev, "Cannot allocate sense memory\n");
1283 bzero(sc->sense_frames, rsize);
1284 bus_dmamap_load(sc->sense_dmat, sc->sense_map, sc->sense_frames, rsize,
1285 mpr_memaddr_cb, &sc->sense_busaddr, 0);
1287 sc->chains = malloc(sizeof(struct mpr_chain) * sc->max_chains, M_MPR,
1290 device_printf(sc->mpr_dev, "Cannot allocate memory %s %d\n",
1291 __func__, __LINE__);
1294 for (i = 0; i < sc->max_chains; i++) {
1295 chain = &sc->chains[i];
1296 chain->chain = (MPI2_SGE_IO_UNION *)(sc->chain_frames +
1297 i * sc->chain_frame_size);
1298 chain->chain_busaddr = sc->chain_busaddr +
1299 i * sc->chain_frame_size;
1300 mpr_free_chain(sc, chain);
1301 sc->chain_free_lowwater++;
1305 * Allocate NVMe PRP Pages for NVMe SGL support only if the FW supports
1308 if ((sc->facts->MsgVersion >= MPI2_VERSION_02_06) &&
1309 (sc->facts->ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES)) {
1310 if (mpr_alloc_nvme_prp_pages(sc) == ENOMEM)
1314 /* XXX Need to pick a more precise value */
1315 nsegs = (MAXPHYS / PAGE_SIZE) + 1;
1316 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */
1317 1, 0, /* algnmnt, boundary */
1318 BUS_SPACE_MAXADDR, /* lowaddr */
1319 BUS_SPACE_MAXADDR, /* highaddr */
1320 NULL, NULL, /* filter, filterarg */
1321 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1322 nsegs, /* nsegments */
1323 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1324 BUS_DMA_ALLOCNOW, /* flags */
1325 busdma_lock_mutex, /* lockfunc */
1326 &sc->mpr_mtx, /* lockarg */
1327 &sc->buffer_dmat)) {
1328 device_printf(sc->mpr_dev, "Cannot allocate buffer DMA tag\n");
1333 * SMID 0 cannot be used as a free command per the firmware spec.
1334 * Just drop that command instead of risking accounting bugs.
1336 sc->commands = malloc(sizeof(struct mpr_command) * sc->num_reqs,
1337 M_MPR, M_WAITOK | M_ZERO);
1338 if (!sc->commands) {
1339 device_printf(sc->mpr_dev, "Cannot allocate memory %s %d\n",
1340 __func__, __LINE__);
1343 for (i = 1; i < sc->num_reqs; i++) {
1344 cm = &sc->commands[i];
1345 cm->cm_req = sc->req_frames +
1346 i * sc->facts->IOCRequestFrameSize * 4;
1347 cm->cm_req_busaddr = sc->req_busaddr +
1348 i * sc->facts->IOCRequestFrameSize * 4;
1349 cm->cm_sense = &sc->sense_frames[i];
1350 cm->cm_sense_busaddr = sc->sense_busaddr + i * MPR_SENSE_LEN;
1351 cm->cm_desc.Default.SMID = i;
1353 TAILQ_INIT(&cm->cm_chain_list);
1354 TAILQ_INIT(&cm->cm_prp_page_list);
1355 callout_init_mtx(&cm->cm_callout, &sc->mpr_mtx, 0);
1357 /* XXX Is a failure here a critical problem? */
1358 if (bus_dmamap_create(sc->buffer_dmat, 0, &cm->cm_dmamap)
1360 if (i <= sc->facts->HighPriorityCredit)
1361 mpr_free_high_priority_command(sc, cm);
1363 mpr_free_command(sc, cm);
1365 panic("failed to allocate command %d\n", i);
1375 * Allocate contiguous buffers for PCIe NVMe devices for building native PRPs,
1376 * which are scatter/gather lists for NVMe devices.
1378 * This buffer must be contiguous due to the nature of how NVMe PRPs are built
1379 * and translated by FW.
1381 * returns ENOMEM if memory could not be allocated, otherwise returns 0.
1384 mpr_alloc_nvme_prp_pages(struct mpr_softc *sc)
1386 int PRPs_per_page, PRPs_required, pages_required;
1388 struct mpr_prp_page *prp_page;
1391 * Assuming a MAX_IO_SIZE of 1MB and a PAGE_SIZE of 4k, the max number
1392 * of PRPs (NVMe's Scatter/Gather Element) needed per I/O is:
1393 * MAX_IO_SIZE / PAGE_SIZE = 256
1395 * 1 PRP entry in main frame for PRP list pointer still leaves 255 PRPs
1396 * required for the remainder of the 1MB I/O. 512 PRPs can fit into one
1397 * page (4096 / 8 = 512), so only one page is required for each I/O.
1399 * Each of these buffers will need to be contiguous. For simplicity,
1400 * only one buffer is allocated here, which has all of the space
1401 * required for the NVMe Queue Depth. If there are problems allocating
1402 * this one buffer, this function will need to change to allocate
1403 * individual, contiguous NVME_QDEPTH buffers.
1405 * The real calculation will use the real max io size. Above is just an
1409 PRPs_required = sc->maxio / PAGE_SIZE;
1410 PRPs_per_page = (PAGE_SIZE / PRP_ENTRY_SIZE) - 1;
1411 pages_required = (PRPs_required / PRPs_per_page) + 1;
1413 sc->prp_buffer_size = PAGE_SIZE * pages_required;
1414 rsize = sc->prp_buffer_size * NVME_QDEPTH;
1415 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */
1416 4, 0, /* algnmnt, boundary */
1417 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1418 BUS_SPACE_MAXADDR, /* highaddr */
1419 NULL, NULL, /* filter, filterarg */
1420 rsize, /* maxsize */
1422 rsize, /* maxsegsize */
1424 NULL, NULL, /* lockfunc, lockarg */
1425 &sc->prp_page_dmat)) {
1426 device_printf(sc->mpr_dev, "Cannot allocate NVMe PRP DMA "
1430 if (bus_dmamem_alloc(sc->prp_page_dmat, (void **)&sc->prp_pages,
1431 BUS_DMA_NOWAIT, &sc->prp_page_map)) {
1432 device_printf(sc->mpr_dev, "Cannot allocate NVMe PRP memory\n");
1435 bzero(sc->prp_pages, rsize);
1436 bus_dmamap_load(sc->prp_page_dmat, sc->prp_page_map, sc->prp_pages,
1437 rsize, mpr_memaddr_cb, &sc->prp_page_busaddr, 0);
1439 sc->prps = malloc(sizeof(struct mpr_prp_page) * NVME_QDEPTH, M_MPR,
1441 for (i = 0; i < NVME_QDEPTH; i++) {
1442 prp_page = &sc->prps[i];
1443 prp_page->prp_page = (uint64_t *)(sc->prp_pages +
1444 i * sc->prp_buffer_size);
1445 prp_page->prp_page_busaddr = (uint64_t)(sc->prp_page_busaddr +
1446 i * sc->prp_buffer_size);
1447 mpr_free_prp_page(sc, prp_page);
1448 sc->prp_pages_free_lowwater++;
1455 mpr_init_queues(struct mpr_softc *sc)
1459 memset((uint8_t *)sc->post_queue, 0xff, sc->pqdepth * 8);
1462 * According to the spec, we need to use one less reply than we
1463 * have space for on the queue. So sc->num_replies (the number we
1464 * use) should be less than sc->fqdepth (allocated size).
1466 if (sc->num_replies >= sc->fqdepth)
1470 * Initialize all of the free queue entries.
1472 for (i = 0; i < sc->fqdepth; i++) {
1473 sc->free_queue[i] = sc->reply_busaddr +
1474 (i * sc->facts->ReplyFrameSize * 4);
1476 sc->replyfreeindex = sc->num_replies;
1481 /* Get the driver parameter tunables. Lowest priority are the driver defaults.
1482 * Next are the global settings, if they exist. Highest are the per-unit
1483 * settings, if they exist.
1486 mpr_get_tunables(struct mpr_softc *sc)
1490 /* XXX default to some debugging for now */
1491 sc->mpr_debug = MPR_INFO | MPR_FAULT;
1492 sc->disable_msix = 0;
1493 sc->disable_msi = 0;
1494 sc->max_chains = MPR_CHAIN_FRAMES;
1495 sc->max_io_pages = MPR_MAXIO_PAGES;
1496 sc->enable_ssu = MPR_SSU_ENABLE_SSD_DISABLE_HDD;
1497 sc->spinup_wait_time = DEFAULT_SPINUP_WAIT;
1501 * Grab the global variables.
1503 TUNABLE_INT_FETCH("hw.mpr.debug_level", &sc->mpr_debug);
1504 TUNABLE_INT_FETCH("hw.mpr.disable_msix", &sc->disable_msix);
1505 TUNABLE_INT_FETCH("hw.mpr.disable_msi", &sc->disable_msi);
1506 TUNABLE_INT_FETCH("hw.mpr.max_chains", &sc->max_chains);
1507 TUNABLE_INT_FETCH("hw.mpr.max_io_pages", &sc->max_io_pages);
1508 TUNABLE_INT_FETCH("hw.mpr.enable_ssu", &sc->enable_ssu);
1509 TUNABLE_INT_FETCH("hw.mpr.spinup_wait_time", &sc->spinup_wait_time);
1510 TUNABLE_INT_FETCH("hw.mpr.use_phy_num", &sc->use_phynum);
1512 /* Grab the unit-instance variables */
1513 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.debug_level",
1514 device_get_unit(sc->mpr_dev));
1515 TUNABLE_INT_FETCH(tmpstr, &sc->mpr_debug);
1517 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msix",
1518 device_get_unit(sc->mpr_dev));
1519 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msix);
1521 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msi",
1522 device_get_unit(sc->mpr_dev));
1523 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msi);
1525 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_chains",
1526 device_get_unit(sc->mpr_dev));
1527 TUNABLE_INT_FETCH(tmpstr, &sc->max_chains);
1529 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_io_pages",
1530 device_get_unit(sc->mpr_dev));
1531 TUNABLE_INT_FETCH(tmpstr, &sc->max_io_pages);
1533 bzero(sc->exclude_ids, sizeof(sc->exclude_ids));
1534 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.exclude_ids",
1535 device_get_unit(sc->mpr_dev));
1536 TUNABLE_STR_FETCH(tmpstr, sc->exclude_ids, sizeof(sc->exclude_ids));
1538 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.enable_ssu",
1539 device_get_unit(sc->mpr_dev));
1540 TUNABLE_INT_FETCH(tmpstr, &sc->enable_ssu);
1542 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.spinup_wait_time",
1543 device_get_unit(sc->mpr_dev));
1544 TUNABLE_INT_FETCH(tmpstr, &sc->spinup_wait_time);
1546 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.use_phy_num",
1547 device_get_unit(sc->mpr_dev));
1548 TUNABLE_INT_FETCH(tmpstr, &sc->use_phynum);
1552 mpr_setup_sysctl(struct mpr_softc *sc)
1554 struct sysctl_ctx_list *sysctl_ctx = NULL;
1555 struct sysctl_oid *sysctl_tree = NULL;
1556 char tmpstr[80], tmpstr2[80];
1559 * Setup the sysctl variable so the user can change the debug level
1562 snprintf(tmpstr, sizeof(tmpstr), "MPR controller %d",
1563 device_get_unit(sc->mpr_dev));
1564 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mpr_dev));
1566 sysctl_ctx = device_get_sysctl_ctx(sc->mpr_dev);
1567 if (sysctl_ctx != NULL)
1568 sysctl_tree = device_get_sysctl_tree(sc->mpr_dev);
1570 if (sysctl_tree == NULL) {
1571 sysctl_ctx_init(&sc->sysctl_ctx);
1572 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1573 SYSCTL_STATIC_CHILDREN(_hw_mpr), OID_AUTO, tmpstr2,
1574 CTLFLAG_RD, 0, tmpstr);
1575 if (sc->sysctl_tree == NULL)
1577 sysctl_ctx = &sc->sysctl_ctx;
1578 sysctl_tree = sc->sysctl_tree;
1581 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1582 OID_AUTO, "debug_level", CTLFLAG_RW, &sc->mpr_debug, 0,
1585 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1586 OID_AUTO, "disable_msix", CTLFLAG_RD, &sc->disable_msix, 0,
1587 "Disable the use of MSI-X interrupts");
1589 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1590 OID_AUTO, "disable_msi", CTLFLAG_RD, &sc->disable_msi, 0,
1591 "Disable the use of MSI interrupts");
1593 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1594 OID_AUTO, "firmware_version", CTLFLAG_RW, sc->fw_version,
1595 strlen(sc->fw_version), "firmware version");
1597 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1598 OID_AUTO, "driver_version", CTLFLAG_RW, MPR_DRIVER_VERSION,
1599 strlen(MPR_DRIVER_VERSION), "driver version");
1601 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1602 OID_AUTO, "io_cmds_active", CTLFLAG_RD,
1603 &sc->io_cmds_active, 0, "number of currently active commands");
1605 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1606 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD,
1607 &sc->io_cmds_highwater, 0, "maximum active commands seen");
1609 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1610 OID_AUTO, "chain_free", CTLFLAG_RD,
1611 &sc->chain_free, 0, "number of free chain elements");
1613 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1614 OID_AUTO, "chain_free_lowwater", CTLFLAG_RD,
1615 &sc->chain_free_lowwater, 0,"lowest number of free chain elements");
1617 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1618 OID_AUTO, "max_chains", CTLFLAG_RD,
1619 &sc->max_chains, 0,"maximum chain frames that will be allocated");
1621 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1622 OID_AUTO, "max_io_pages", CTLFLAG_RD,
1623 &sc->max_io_pages, 0,"maximum pages to allow per I/O (if <1 use "
1626 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1627 OID_AUTO, "enable_ssu", CTLFLAG_RW, &sc->enable_ssu, 0,
1628 "enable SSU to SATA SSD/HDD at shutdown");
1630 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1631 OID_AUTO, "chain_alloc_fail", CTLFLAG_RD,
1632 &sc->chain_alloc_fail, "chain allocation failures");
1634 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1635 OID_AUTO, "spinup_wait_time", CTLFLAG_RD,
1636 &sc->spinup_wait_time, DEFAULT_SPINUP_WAIT, "seconds to wait for "
1637 "spinup after SATA ID error");
1639 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1640 OID_AUTO, "use_phy_num", CTLFLAG_RD, &sc->use_phynum, 0,
1641 "Use the phy number for enumeration");
1643 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1644 OID_AUTO, "prp_pages_free", CTLFLAG_RD,
1645 &sc->prp_pages_free, 0, "number of free PRP pages");
1647 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1648 OID_AUTO, "prp_pages_free_lowwater", CTLFLAG_RD,
1649 &sc->prp_pages_free_lowwater, 0,"lowest number of free PRP pages");
1651 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1652 OID_AUTO, "prp_page_alloc_fail", CTLFLAG_RD,
1653 &sc->prp_page_alloc_fail, "PRP page allocation failures");
1657 mpr_attach(struct mpr_softc *sc)
1661 mpr_get_tunables(sc);
1665 mtx_init(&sc->mpr_mtx, "MPR lock", NULL, MTX_DEF);
1666 callout_init_mtx(&sc->periodic, &sc->mpr_mtx, 0);
1667 callout_init_mtx(&sc->device_check_callout, &sc->mpr_mtx, 0);
1668 TAILQ_INIT(&sc->event_list);
1669 timevalclear(&sc->lastfail);
1671 if ((error = mpr_transition_ready(sc)) != 0) {
1672 mpr_printf(sc, "%s failed to transition ready\n", __func__);
1676 sc->facts = malloc(sizeof(MPI2_IOC_FACTS_REPLY), M_MPR,
1679 device_printf(sc->mpr_dev, "Cannot allocate memory %s %d\n",
1680 __func__, __LINE__);
1685 * Get IOC Facts and allocate all structures based on this information.
1686 * A Diag Reset will also call mpr_iocfacts_allocate and re-read the IOC
1687 * Facts. If relevant values have changed in IOC Facts, this function
1688 * will free all of the memory based on IOC Facts and reallocate that
1689 * memory. If this fails, any allocated memory should already be freed.
1691 if ((error = mpr_iocfacts_allocate(sc, TRUE)) != 0) {
1692 mpr_dprint(sc, MPR_FAULT, "%s IOC Facts based allocation "
1693 "failed with error %d\n", __func__, error);
1697 /* Start the periodic watchdog check on the IOC Doorbell */
1701 * The portenable will kick off discovery events that will drive the
1702 * rest of the initialization process. The CAM/SAS module will
1703 * hold up the boot sequence until discovery is complete.
1705 sc->mpr_ich.ich_func = mpr_startup;
1706 sc->mpr_ich.ich_arg = sc;
1707 if (config_intrhook_establish(&sc->mpr_ich) != 0) {
1708 mpr_dprint(sc, MPR_ERROR, "Cannot establish MPR config hook\n");
1713 * Allow IR to shutdown gracefully when shutdown occurs.
1715 sc->shutdown_eh = EVENTHANDLER_REGISTER(shutdown_final,
1716 mprsas_ir_shutdown, sc, SHUTDOWN_PRI_DEFAULT);
1718 if (sc->shutdown_eh == NULL)
1719 mpr_dprint(sc, MPR_ERROR, "shutdown event registration "
1722 mpr_setup_sysctl(sc);
1724 sc->mpr_flags |= MPR_FLAGS_ATTACH_DONE;
1729 /* Run through any late-start handlers. */
1731 mpr_startup(void *arg)
1733 struct mpr_softc *sc;
1735 sc = (struct mpr_softc *)arg;
1738 mpr_unmask_intr(sc);
1740 /* initialize device mapping tables */
1741 mpr_base_static_config_pages(sc);
1742 mpr_mapping_initialize(sc);
1747 /* Periodic watchdog. Is called with the driver lock already held. */
1749 mpr_periodic(void *arg)
1751 struct mpr_softc *sc;
1754 sc = (struct mpr_softc *)arg;
1755 if (sc->mpr_flags & MPR_FLAGS_SHUTDOWN)
1758 db = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
1759 if ((db & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
1760 if ((db & MPI2_DOORBELL_FAULT_CODE_MASK) ==
1761 IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED) {
1762 panic("TEMPERATURE FAULT: STOPPING.");
1764 mpr_dprint(sc, MPR_FAULT, "IOC Fault 0x%08x, Resetting\n", db);
1768 callout_reset(&sc->periodic, MPR_PERIODIC_DELAY * hz, mpr_periodic, sc);
1772 mpr_log_evt_handler(struct mpr_softc *sc, uintptr_t data,
1773 MPI2_EVENT_NOTIFICATION_REPLY *event)
1775 MPI2_EVENT_DATA_LOG_ENTRY_ADDED *entry;
1777 mpr_print_event(sc, event);
1779 switch (event->Event) {
1780 case MPI2_EVENT_LOG_DATA:
1781 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_DATA:\n");
1782 if (sc->mpr_debug & MPR_EVENT)
1783 hexdump(event->EventData, event->EventDataLength, NULL,
1786 case MPI2_EVENT_LOG_ENTRY_ADDED:
1787 entry = (MPI2_EVENT_DATA_LOG_ENTRY_ADDED *)event->EventData;
1788 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_ENTRY_ADDED event "
1789 "0x%x Sequence %d:\n", entry->LogEntryQualifier,
1790 entry->LogSequence);
1799 mpr_attach_log(struct mpr_softc *sc)
1804 setbit(events, MPI2_EVENT_LOG_DATA);
1805 setbit(events, MPI2_EVENT_LOG_ENTRY_ADDED);
1807 mpr_register_events(sc, events, mpr_log_evt_handler, NULL,
1814 mpr_detach_log(struct mpr_softc *sc)
1817 if (sc->mpr_log_eh != NULL)
1818 mpr_deregister_events(sc, sc->mpr_log_eh);
1823 * Free all of the driver resources and detach submodules. Should be called
1824 * without the lock held.
1827 mpr_free(struct mpr_softc *sc)
1831 /* Turn off the watchdog */
1833 sc->mpr_flags |= MPR_FLAGS_SHUTDOWN;
1835 /* Lock must not be held for this */
1836 callout_drain(&sc->periodic);
1837 callout_drain(&sc->device_check_callout);
1839 if (((error = mpr_detach_log(sc)) != 0) ||
1840 ((error = mpr_detach_sas(sc)) != 0))
1843 mpr_detach_user(sc);
1845 /* Put the IOC back in the READY state. */
1847 if ((error = mpr_transition_ready(sc)) != 0) {
1853 if (sc->facts != NULL)
1854 free(sc->facts, M_MPR);
1857 * Free all buffers that are based on IOC Facts. A Diag Reset may need
1858 * to free these buffers too.
1860 mpr_iocfacts_free(sc);
1862 if (sc->sysctl_tree != NULL)
1863 sysctl_ctx_free(&sc->sysctl_ctx);
1865 /* Deregister the shutdown function */
1866 if (sc->shutdown_eh != NULL)
1867 EVENTHANDLER_DEREGISTER(shutdown_final, sc->shutdown_eh);
1869 mtx_destroy(&sc->mpr_mtx);
1874 static __inline void
1875 mpr_complete_command(struct mpr_softc *sc, struct mpr_command *cm)
1880 mpr_dprint(sc, MPR_ERROR, "Completing NULL command\n");
1884 if (cm->cm_flags & MPR_CM_FLAGS_POLLED)
1885 cm->cm_flags |= MPR_CM_FLAGS_COMPLETE;
1887 if (cm->cm_complete != NULL) {
1888 mpr_dprint(sc, MPR_TRACE,
1889 "%s cm %p calling cm_complete %p data %p reply %p\n",
1890 __func__, cm, cm->cm_complete, cm->cm_complete_data,
1892 cm->cm_complete(sc, cm);
1895 if (cm->cm_flags & MPR_CM_FLAGS_WAKEUP) {
1896 mpr_dprint(sc, MPR_TRACE, "waking up %p\n", cm);
1900 if (sc->io_cmds_active != 0) {
1901 sc->io_cmds_active--;
1903 mpr_dprint(sc, MPR_ERROR, "Warning: io_cmds_active is "
1904 "out of sync - resynching to 0\n");
1909 mpr_sas_log_info(struct mpr_softc *sc , u32 log_info)
1911 union loginfo_type {
1920 union loginfo_type sas_loginfo;
1921 char *originator_str = NULL;
1923 sas_loginfo.loginfo = log_info;
1924 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
1927 /* each nexus loss loginfo */
1928 if (log_info == 0x31170000)
1931 /* eat the loginfos associated with task aborts */
1932 if ((log_info == 30050000) || (log_info == 0x31140000) ||
1933 (log_info == 0x31130000))
1936 switch (sas_loginfo.dw.originator) {
1938 originator_str = "IOP";
1941 originator_str = "PL";
1944 originator_str = "IR";
1948 mpr_dprint(sc, MPR_LOG, "log_info(0x%08x): originator(%s), "
1949 "code(0x%02x), sub_code(0x%04x)\n", log_info, originator_str,
1950 sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1954 mpr_display_reply_info(struct mpr_softc *sc, uint8_t *reply)
1956 MPI2DefaultReply_t *mpi_reply;
1959 mpi_reply = (MPI2DefaultReply_t*)reply;
1960 sc_status = le16toh(mpi_reply->IOCStatus);
1961 if (sc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
1962 mpr_sas_log_info(sc, le32toh(mpi_reply->IOCLogInfo));
1966 mpr_intr(void *data)
1968 struct mpr_softc *sc;
1971 sc = (struct mpr_softc *)data;
1972 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
1975 * Check interrupt status register to flush the bus. This is
1976 * needed for both INTx interrupts and driver-driven polling
1978 status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET);
1979 if ((status & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) == 0)
1983 mpr_intr_locked(data);
1989 * In theory, MSI/MSIX interrupts shouldn't need to read any registers on the
1990 * chip. Hopefully this theory is correct.
1993 mpr_intr_msi(void *data)
1995 struct mpr_softc *sc;
1997 sc = (struct mpr_softc *)data;
1998 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2000 mpr_intr_locked(data);
2006 * The locking is overly broad and simplistic, but easy to deal with for now.
2009 mpr_intr_locked(void *data)
2011 MPI2_REPLY_DESCRIPTORS_UNION *desc;
2012 struct mpr_softc *sc;
2013 struct mpr_command *cm = NULL;
2016 MPI2_DIAG_RELEASE_REPLY *rel_rep;
2017 mpr_fw_diagnostic_buffer_t *pBuffer;
2019 sc = (struct mpr_softc *)data;
2021 pq = sc->replypostindex;
2022 mpr_dprint(sc, MPR_TRACE,
2023 "%s sc %p starting with replypostindex %u\n",
2024 __func__, sc, sc->replypostindex);
2028 desc = &sc->post_queue[sc->replypostindex];
2029 flags = desc->Default.ReplyFlags &
2030 MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
2031 if ((flags == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) ||
2032 (le32toh(desc->Words.High) == 0xffffffff))
2035 /* increment the replypostindex now, so that event handlers
2036 * and cm completion handlers which decide to do a diag
2037 * reset can zero it without it getting incremented again
2038 * afterwards, and we break out of this loop on the next
2039 * iteration since the reply post queue has been cleared to
2040 * 0xFF and all descriptors look unused (which they are).
2042 if (++sc->replypostindex >= sc->pqdepth)
2043 sc->replypostindex = 0;
2046 case MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS:
2047 case MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS:
2048 case MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS:
2049 cm = &sc->commands[le16toh(desc->SCSIIOSuccess.SMID)];
2050 cm->cm_reply = NULL;
2052 case MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY:
2058 * Re-compose the reply address from the address
2059 * sent back from the chip. The ReplyFrameAddress
2060 * is the lower 32 bits of the physical address of
2061 * particular reply frame. Convert that address to
2062 * host format, and then use that to provide the
2063 * offset against the virtual address base
2064 * (sc->reply_frames).
2066 baddr = le32toh(desc->AddressReply.ReplyFrameAddress);
2067 reply = sc->reply_frames +
2068 (baddr - ((uint32_t)sc->reply_busaddr));
2070 * Make sure the reply we got back is in a valid
2071 * range. If not, go ahead and panic here, since
2072 * we'll probably panic as soon as we deference the
2073 * reply pointer anyway.
2075 if ((reply < sc->reply_frames)
2076 || (reply > (sc->reply_frames +
2077 (sc->fqdepth * sc->facts->ReplyFrameSize * 4)))) {
2078 printf("%s: WARNING: reply %p out of range!\n",
2080 printf("%s: reply_frames %p, fqdepth %d, "
2081 "frame size %d\n", __func__,
2082 sc->reply_frames, sc->fqdepth,
2083 sc->facts->ReplyFrameSize * 4);
2084 printf("%s: baddr %#x,\n", __func__, baddr);
2085 /* LSI-TODO. See Linux Code for Graceful exit */
2086 panic("Reply address out of range");
2088 if (le16toh(desc->AddressReply.SMID) == 0) {
2089 if (((MPI2_DEFAULT_REPLY *)reply)->Function ==
2090 MPI2_FUNCTION_DIAG_BUFFER_POST) {
2092 * If SMID is 0 for Diag Buffer Post,
2093 * this implies that the reply is due to
2094 * a release function with a status that
2095 * the buffer has been released. Set
2096 * the buffer flags accordingly.
2099 (MPI2_DIAG_RELEASE_REPLY *)reply;
2100 if ((le16toh(rel_rep->IOCStatus) &
2101 MPI2_IOCSTATUS_MASK) ==
2102 MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED)
2105 &sc->fw_diag_buffer_list[
2106 rel_rep->BufferType];
2107 pBuffer->valid_data = TRUE;
2108 pBuffer->owned_by_firmware =
2110 pBuffer->immediate = FALSE;
2113 mpr_dispatch_event(sc, baddr,
2114 (MPI2_EVENT_NOTIFICATION_REPLY *)
2118 le16toh(desc->AddressReply.SMID)];
2119 cm->cm_reply = reply;
2121 le32toh(desc->AddressReply.
2126 case MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS:
2127 case MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER:
2128 case MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS:
2131 mpr_dprint(sc, MPR_ERROR, "Unhandled reply 0x%x\n",
2132 desc->Default.ReplyFlags);
2138 // Print Error reply frame
2140 mpr_display_reply_info(sc,cm->cm_reply);
2141 mpr_complete_command(sc, cm);
2144 desc->Words.Low = 0xffffffff;
2145 desc->Words.High = 0xffffffff;
2148 if (pq != sc->replypostindex) {
2149 mpr_dprint(sc, MPR_TRACE,
2150 "%s sc %p writing postindex %d\n",
2151 __func__, sc, sc->replypostindex);
2152 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET,
2153 sc->replypostindex);
2160 mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data,
2161 MPI2_EVENT_NOTIFICATION_REPLY *reply)
2163 struct mpr_event_handle *eh;
2164 int event, handled = 0;
2166 event = le16toh(reply->Event);
2167 TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2168 if (isset(eh->mask, event)) {
2169 eh->callback(sc, data, reply);
2175 mpr_dprint(sc, MPR_EVENT, "Unhandled event 0x%x\n",
2179 * This is the only place that the event/reply should be freed.
2180 * Anything wanting to hold onto the event data should have
2181 * already copied it into their own storage.
2183 mpr_free_reply(sc, data);
2187 mpr_reregister_events_complete(struct mpr_softc *sc, struct mpr_command *cm)
2189 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2193 (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply);
2195 mpr_free_command(sc, cm);
2197 /* next, send a port enable */
2202 * For both register_events and update_events, the caller supplies a bitmap
2203 * of events that it _wants_. These functions then turn that into a bitmask
2204 * suitable for the controller.
2207 mpr_register_events(struct mpr_softc *sc, uint8_t *mask,
2208 mpr_evt_callback_t *cb, void *data, struct mpr_event_handle **handle)
2210 struct mpr_event_handle *eh;
2213 eh = malloc(sizeof(struct mpr_event_handle), M_MPR, M_WAITOK|M_ZERO);
2215 device_printf(sc->mpr_dev, "Cannot allocate memory %s %d\n",
2216 __func__, __LINE__);
2221 TAILQ_INSERT_TAIL(&sc->event_list, eh, eh_list);
2223 error = mpr_update_events(sc, eh, mask);
2230 mpr_update_events(struct mpr_softc *sc, struct mpr_event_handle *handle,
2233 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq;
2234 MPI2_EVENT_NOTIFICATION_REPLY *reply;
2235 struct mpr_command *cm;
2236 struct mpr_event_handle *eh;
2239 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2241 if ((mask != NULL) && (handle != NULL))
2242 bcopy(mask, &handle->mask[0], 16);
2243 memset(sc->event_mask, 0xff, 16);
2245 TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2246 for (i = 0; i < 16; i++)
2247 sc->event_mask[i] &= ~eh->mask[i];
2250 if ((cm = mpr_alloc_command(sc)) == NULL)
2252 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req;
2253 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
2254 evtreq->MsgFlags = 0;
2255 evtreq->SASBroadcastPrimitiveMasks = 0;
2256 #ifdef MPR_DEBUG_ALL_EVENTS
2258 u_char fullmask[16];
2259 memset(fullmask, 0x00, 16);
2260 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16);
2263 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, 16);
2265 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2268 error = mpr_request_polled(sc, cm);
2269 reply = (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply;
2270 if ((reply == NULL) ||
2271 (reply->IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS)
2275 mpr_print_event(sc, reply);
2277 mpr_dprint(sc, MPR_TRACE, "%s finished error %d\n", __func__, error);
2279 mpr_free_command(sc, cm);
2284 mpr_reregister_events(struct mpr_softc *sc)
2286 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq;
2287 struct mpr_command *cm;
2288 struct mpr_event_handle *eh;
2291 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2293 /* first, reregister events */
2295 memset(sc->event_mask, 0xff, 16);
2297 TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2298 for (i = 0; i < 16; i++)
2299 sc->event_mask[i] &= ~eh->mask[i];
2302 if ((cm = mpr_alloc_command(sc)) == NULL)
2304 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req;
2305 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
2306 evtreq->MsgFlags = 0;
2307 evtreq->SASBroadcastPrimitiveMasks = 0;
2308 #ifdef MPR_DEBUG_ALL_EVENTS
2310 u_char fullmask[16];
2311 memset(fullmask, 0x00, 16);
2312 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16);
2315 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, 16);
2317 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2319 cm->cm_complete = mpr_reregister_events_complete;
2321 error = mpr_map_command(sc, cm);
2323 mpr_dprint(sc, MPR_TRACE, "%s finished with error %d\n", __func__,
2329 mpr_deregister_events(struct mpr_softc *sc, struct mpr_event_handle *handle)
2332 TAILQ_REMOVE(&sc->event_list, handle, eh_list);
2333 free(handle, M_MPR);
2334 return (mpr_update_events(sc, NULL, NULL));
2338 * mpr_build_nvme_prp - This function is called for NVMe end devices to build a
2339 * native SGL (NVMe PRP). The native SGL is built starting in the first PRP entry
2340 * of the NVMe message (PRP1). If the data buffer is small enough to be described
2341 * entirely using PRP1, then PRP2 is not used. If needed, PRP2 is used to
2342 * describe a larger data buffer. If the data buffer is too large to describe
2343 * using the two PRP entriess inside the NVMe message, then PRP1 describes the
2344 * first data memory segment, and PRP2 contains a pointer to a PRP list located
2345 * elsewhere in memory to describe the remaining data memory segments. The PRP
2346 * list will be contiguous.
2348 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP
2349 * consists of a list of PRP entries to describe a number of noncontigous
2350 * physical memory segments as a single memory buffer, just as a SGL does. Note
2351 * however, that this function is only used by the IOCTL call, so the memory
2352 * given will be guaranteed to be contiguous. There is no need to translate
2353 * non-contiguous SGL into a PRP in this case. All PRPs will describe contiguous
2354 * space that is one page size each.
2356 * Each NVMe message contains two PRP entries. The first (PRP1) either contains
2357 * a PRP list pointer or a PRP element, depending upon the command. PRP2 contains
2358 * the second PRP element if the memory being described fits within 2 PRP
2359 * entries, or a PRP list pointer if the PRP spans more than two entries.
2361 * A PRP list pointer contains the address of a PRP list, structured as a linear
2362 * array of PRP entries. Each PRP entry in this list describes a segment of
2365 * Each 64-bit PRP entry comprises an address and an offset field. The address
2366 * always points to the beginning of a PAGE_SIZE physical memory page, and the
2367 * offset describes where within that page the memory segment begins. Only the
2368 * first element in a PRP list may contain a non-zero offest, implying that all
2369 * memory segments following the first begin at the start of a PAGE_SIZE page.
2371 * Each PRP element normally describes a chunck of PAGE_SIZE physical memory,
2372 * with exceptions for the first and last elements in the list. If the memory
2373 * being described by the list begins at a non-zero offset within the first page,
2374 * then the first PRP element will contain a non-zero offset indicating where the
2375 * region begins within the page. The last memory segment may end before the end
2376 * of the PAGE_SIZE segment, depending upon the overall size of the memory being
2377 * described by the PRP list.
2379 * Since PRP entries lack any indication of size, the overall data buffer length
2380 * is used to determine where the end of the data memory buffer is located, and
2381 * how many PRP entries are required to describe it.
2386 mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm,
2387 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data,
2388 uint32_t data_in_sz, uint32_t data_out_sz)
2390 int prp_size = PRP_ENTRY_SIZE;
2391 uint64_t *prp_entry, *prp1_entry, *prp2_entry;
2392 uint64_t *prp_entry_phys, *prp_page, *prp_page_phys;
2393 uint32_t offset, entry_len, page_mask_result, page_mask;
2396 struct mpr_prp_page *prp_page_info = NULL;
2399 * Not all commands require a data transfer. If no data, just return
2400 * without constructing any PRP.
2402 if (!data_in_sz && !data_out_sz)
2406 * Set pointers to PRP1 and PRP2, which are in the NVMe command. PRP1 is
2407 * located at a 24 byte offset from the start of the NVMe command. Then
2408 * set the current PRP entry pointer to PRP1.
2410 prp1_entry = (uint64_t *)(nvme_encap_request->NVMe_Command +
2411 NVME_CMD_PRP1_OFFSET);
2412 prp2_entry = (uint64_t *)(nvme_encap_request->NVMe_Command +
2413 NVME_CMD_PRP2_OFFSET);
2414 prp_entry = prp1_entry;
2417 * For the PRP entries, use the specially allocated buffer of
2418 * contiguous memory. PRP Page allocation failures should not happen
2419 * because there should be enough PRP page buffers to account for the
2420 * possible NVMe QDepth.
2422 prp_page_info = mpr_alloc_prp_page(sc);
2423 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be "
2424 "used for building a native NVMe SGL.\n", __func__));
2425 prp_page = (uint64_t *)prp_page_info->prp_page;
2426 prp_page_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr;
2429 * Insert the allocated PRP page into the command's PRP page list. This
2430 * will be freed when the command is freed.
2432 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link);
2435 * Check if we are within 1 entry of a page boundary we don't want our
2436 * first entry to be a PRP List entry.
2438 page_mask = PAGE_SIZE - 1;
2439 page_mask_result = (uintptr_t)((uint8_t *)prp_page + prp_size) &
2441 if (!page_mask_result)
2443 /* Bump up to next page boundary. */
2444 prp_page = (uint64_t *)((uint8_t *)prp_page + prp_size);
2445 prp_page_phys = (uint64_t *)((uint8_t *)prp_page_phys +
2450 * Set PRP physical pointer, which initially points to the current PRP
2453 prp_entry_phys = prp_page_phys;
2455 /* Get physical address and length of the data buffer. */
2456 paddr = (bus_addr_t)data;
2458 length = data_in_sz;
2460 length = data_out_sz;
2462 /* Loop while the length is not zero. */
2466 * Check if we need to put a list pointer here if we are at page
2467 * boundary - prp_size (8 bytes).
2469 page_mask_result = (uintptr_t)((uint8_t *)prp_entry_phys +
2470 prp_size) & page_mask;
2471 if (!page_mask_result)
2474 * This is the last entry in a PRP List, so we need to
2475 * put a PRP list pointer here. What this does is:
2476 * - bump the current memory pointer to the next
2477 * address, which will be the next full page.
2478 * - set the PRP Entry to point to that page. This is
2479 * now the PRP List pointer.
2480 * - bump the PRP Entry pointer the start of the next
2481 * page. Since all of this PRP memory is contiguous,
2482 * no need to get a new page - it's just the next
2487 htole64((uint64_t)(uintptr_t)prp_entry_phys);
2491 /* Need to handle if entry will be part of a page. */
2492 offset = (uint32_t)paddr & page_mask;
2493 entry_len = PAGE_SIZE - offset;
2495 if (prp_entry == prp1_entry)
2498 * Must fill in the first PRP pointer (PRP1) before
2501 *prp1_entry = htole64((uint64_t)paddr);
2504 * Now point to the second PRP entry within the
2507 prp_entry = prp2_entry;
2509 else if (prp_entry == prp2_entry)
2512 * Should the PRP2 entry be a PRP List pointer or just a
2513 * regular PRP pointer? If there is more than one more
2514 * page of data, must use a PRP List pointer.
2516 if (length > PAGE_SIZE)
2519 * PRP2 will contain a PRP List pointer because
2520 * more PRP's are needed with this command. The
2521 * list will start at the beginning of the
2522 * contiguous buffer.
2526 (uint64_t)(uintptr_t)prp_entry_phys);
2529 * The next PRP Entry will be the start of the
2532 prp_entry = prp_page;
2537 * After this, the PRP Entries are complete.
2538 * This command uses 2 PRP's and no PRP list.
2540 *prp2_entry = htole64((uint64_t)paddr);
2546 * Put entry in list and bump the addresses.
2548 * After PRP1 and PRP2 are filled in, this will fill in
2549 * all remaining PRP entries in a PRP List, one per each
2550 * time through the loop.
2552 *prp_entry = htole64((uint64_t)paddr);
2558 * Bump the phys address of the command's data buffer by the
2563 /* Decrement length accounting for last partial page. */
2564 if (entry_len > length)
2567 length -= entry_len;
2572 * mpr_check_pcie_native_sgl - This function is called for PCIe end devices to
2573 * determine if the driver needs to build a native SGL. If so, that native SGL
2574 * is built in the contiguous buffers allocated especially for PCIe SGL
2575 * creation. If the driver will not build a native SGL, return TRUE and a
2576 * normal IEEE SGL will be built. Currently this routine supports NVMe devices
2579 * Returns FALSE (0) if native SGL was built, TRUE (1) if no SGL was built.
2582 mpr_check_pcie_native_sgl(struct mpr_softc *sc, struct mpr_command *cm,
2583 bus_dma_segment_t *segs, int segs_left)
2585 uint32_t i, sge_dwords, length, offset, entry_len;
2586 uint32_t num_entries, buff_len = 0, sges_in_segment;
2587 uint32_t page_mask, page_mask_result, *curr_buff;
2588 uint32_t *ptr_sgl, *ptr_first_sgl, first_page_offset;
2589 uint32_t first_page_data_size, end_residual;
2592 int build_native_sgl = 0, first_prp_entry;
2593 int prp_size = PRP_ENTRY_SIZE;
2594 Mpi25IeeeSgeChain64_t *main_chain_element = NULL;
2595 struct mpr_prp_page *prp_page_info = NULL;
2597 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2600 * Add up the sizes of each segment length to get the total transfer
2601 * size, which will be checked against the Maximum Data Transfer Size.
2602 * If the data transfer length exceeds the MDTS for this device, just
2603 * return 1 so a normal IEEE SGL will be built. F/W will break the I/O
2604 * up into multiple I/O's. [nvme_mdts = 0 means unlimited]
2606 for (i = 0; i < segs_left; i++)
2607 buff_len += htole32(segs[i].ds_len);
2608 if ((cm->cm_targ->MDTS > 0) && (buff_len > cm->cm_targ->MDTS))
2611 /* Create page_mask (to get offset within page) */
2612 page_mask = PAGE_SIZE - 1;
2615 * Check if the number of elements exceeds the max number that can be
2616 * put in the main message frame (H/W can only translate an SGL that
2617 * is contained entirely in the main message frame).
2619 sges_in_segment = (sc->facts->IOCRequestFrameSize -
2620 offsetof(Mpi25SCSIIORequest_t, SGL)) / sizeof(MPI25_SGE_IO_UNION);
2621 if (segs_left > sges_in_segment)
2622 build_native_sgl = 1;
2626 * NVMe uses one PRP for each physical page (or part of physical
2628 * if 4 pages or less then IEEE is OK
2629 * if > 5 pages then we need to build a native SGL
2630 * if > 4 and <= 5 pages, then check the physical address of
2631 * the first SG entry, then if this first size in the page
2632 * is >= the residual beyond 4 pages then use IEEE,
2633 * otherwise use native SGL
2635 if (buff_len > (PAGE_SIZE * 5))
2636 build_native_sgl = 1;
2637 else if ((buff_len > (PAGE_SIZE * 4)) &&
2638 (buff_len <= (PAGE_SIZE * 5)) )
2640 msg_phys = (uint64_t *)segs[0].ds_addr;
2642 ((uint32_t)(uint64_t)(uintptr_t)msg_phys &
2644 first_page_data_size = PAGE_SIZE - first_page_offset;
2645 end_residual = buff_len % PAGE_SIZE;
2648 * If offset into first page pushes the end of the data
2649 * beyond end of the 5th page, we need the extra PRP
2652 if (first_page_data_size < end_residual)
2653 build_native_sgl = 1;
2656 * Check if first SG entry size is < residual beyond 4
2659 if (htole32(segs[0].ds_len) <
2660 (buff_len - (PAGE_SIZE * 4)))
2661 build_native_sgl = 1;
2665 /* check if native SGL is needed */
2666 if (!build_native_sgl)
2670 * Native SGL is needed.
2671 * Put a chain element in main message frame that points to the first
2674 * NOTE: The ChainOffset field must be 0 when using a chain pointer to
2678 /* Set main message chain element pointer */
2679 main_chain_element = (pMpi25IeeeSgeChain64_t)cm->cm_sge;
2682 * For NVMe the chain element needs to be the 2nd SGL entry in the main
2685 main_chain_element = (Mpi25IeeeSgeChain64_t *)
2686 ((uint8_t *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
2689 * For the PRP entries, use the specially allocated buffer of
2690 * contiguous memory. PRP Page allocation failures should not happen
2691 * because there should be enough PRP page buffers to account for the
2692 * possible NVMe QDepth.
2694 prp_page_info = mpr_alloc_prp_page(sc);
2695 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be "
2696 "used for building a native NVMe SGL.\n", __func__));
2697 curr_buff = (uint32_t *)prp_page_info->prp_page;
2698 msg_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr;
2701 * Insert the allocated PRP page into the command's PRP page list. This
2702 * will be freed when the command is freed.
2704 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link);
2707 * Check if we are within 1 entry of a page boundary we don't want our
2708 * first entry to be a PRP List entry.
2710 page_mask_result = (uintptr_t)((uint8_t *)curr_buff + prp_size) &
2712 if (!page_mask_result) {
2713 /* Bump up to next page boundary. */
2714 curr_buff = (uint32_t *)((uint8_t *)curr_buff + prp_size);
2715 msg_phys = (uint64_t *)((uint8_t *)msg_phys + prp_size);
2718 /* Fill in the chain element and make it an NVMe segment type. */
2719 main_chain_element->Address.High =
2720 htole32((uint32_t)((uint64_t)(uintptr_t)msg_phys >> 32));
2721 main_chain_element->Address.Low =
2722 htole32((uint32_t)(uintptr_t)msg_phys);
2723 main_chain_element->NextChainOffset = 0;
2724 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2725 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2726 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
2728 /* Set SGL pointer to start of contiguous PCIe buffer. */
2729 ptr_sgl = curr_buff;
2734 * NVMe has a very convoluted PRP format. One PRP is required for each
2735 * page or partial page. We need to split up OS SG entries if they are
2736 * longer than one page or cross a page boundary. We also have to insert
2737 * a PRP list pointer entry as the last entry in each physical page of
2740 * NOTE: The first PRP "entry" is actually placed in the first SGL entry
2741 * in the main message in IEEE 64 format. The 2nd entry in the main
2742 * message is the chain element, and the rest of the PRP entries are
2743 * built in the contiguous PCIe buffer.
2745 first_prp_entry = 1;
2746 ptr_first_sgl = (uint32_t *)cm->cm_sge;
2748 for (i = 0; i < segs_left; i++) {
2749 /* Get physical address and length of this SG entry. */
2750 paddr = segs[i].ds_addr;
2751 length = segs[i].ds_len;
2754 * Check whether a given SGE buffer lies on a non-PAGED
2755 * boundary if this is not the first page. If so, this is not
2756 * expected so have FW build the SGL.
2759 if ((uint32_t)paddr & page_mask) {
2760 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE while "
2761 "building NVMe PRPs, low address is 0x%x\n",
2767 /* Apart from last SGE, if any other SGE boundary is not page
2768 * aligned then it means that hole exists. Existence of hole
2769 * leads to data corruption. So fallback to IEEE SGEs.
2771 if (i != (segs_left - 1)) {
2772 if (((uint32_t)paddr + length) & page_mask) {
2773 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE "
2774 "boundary while building NVMe PRPs, low "
2775 "address: 0x%x and length: %u\n",
2776 (uint32_t)paddr, length);
2781 /* Loop while the length is not zero. */
2784 * Check if we need to put a list pointer here if we are
2785 * at page boundary - prp_size.
2787 page_mask_result = (uintptr_t)((uint8_t *)ptr_sgl +
2788 prp_size) & page_mask;
2789 if (!page_mask_result) {
2791 * Need to put a PRP list pointer here.
2793 msg_phys = (uint64_t *)((uint8_t *)msg_phys +
2795 *ptr_sgl = htole32((uintptr_t)msg_phys);
2796 *(ptr_sgl+1) = htole32((uint64_t)(uintptr_t)
2798 ptr_sgl += sge_dwords;
2802 /* Need to handle if entry will be part of a page. */
2803 offset = (uint32_t)paddr & page_mask;
2804 entry_len = PAGE_SIZE - offset;
2805 if (first_prp_entry) {
2807 * Put IEEE entry in first SGE in main message.
2808 * (Simple element, System addr, not end of
2811 *ptr_first_sgl = htole32((uint32_t)paddr);
2812 *(ptr_first_sgl + 1) =
2813 htole32((uint32_t)((uint64_t)paddr >> 32));
2814 *(ptr_first_sgl + 2) = htole32(entry_len);
2815 *(ptr_first_sgl + 3) = 0;
2817 /* No longer the first PRP entry. */
2818 first_prp_entry = 0;
2820 /* Put entry in list. */
2821 *ptr_sgl = htole32((uint32_t)paddr);
2823 htole32((uint32_t)((uint64_t)paddr >> 32));
2825 /* Bump ptr_sgl, msg_phys, and num_entries. */
2826 ptr_sgl += sge_dwords;
2827 msg_phys = (uint64_t *)((uint8_t *)msg_phys +
2832 /* Bump the phys address by the entry_len. */
2835 /* Decrement length accounting for last partial page. */
2836 if (entry_len > length)
2839 length -= entry_len;
2843 /* Set chain element Length. */
2844 main_chain_element->Length = htole32(num_entries * prp_size);
2846 /* Return 0, indicating we built a native SGL. */
2851 * Add a chain element as the next SGE for the specified command.
2852 * Reset cm_sge and cm_sgesize to indicate all the available space. Chains are
2853 * only required for IEEE commands. Therefore there is no code for commands
2854 * that have the MPR_CM_FLAGS_SGE_SIMPLE flag set (and those commands
2855 * shouldn't be requesting chains).
2858 mpr_add_chain(struct mpr_command *cm, int segsleft)
2860 struct mpr_softc *sc = cm->cm_sc;
2861 MPI2_REQUEST_HEADER *req;
2862 MPI25_IEEE_SGE_CHAIN64 *ieee_sgc;
2863 struct mpr_chain *chain;
2864 int sgc_size, current_segs, rem_segs, segs_per_frame;
2865 uint8_t next_chain_offset = 0;
2868 * Fail if a command is requesting a chain for SIMPLE SGE's. For SAS3
2869 * only IEEE commands should be requesting chains. Return some error
2870 * code other than 0.
2872 if (cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE) {
2873 mpr_dprint(sc, MPR_ERROR, "A chain element cannot be added to "
2878 sgc_size = sizeof(MPI25_IEEE_SGE_CHAIN64);
2879 if (cm->cm_sglsize < sgc_size)
2880 panic("MPR: Need SGE Error Code\n");
2882 chain = mpr_alloc_chain(cm->cm_sc);
2887 * Note: a double-linked list is used to make it easier to walk for
2890 TAILQ_INSERT_TAIL(&cm->cm_chain_list, chain, chain_link);
2893 * Need to know if the number of frames left is more than 1 or not. If
2894 * more than 1 frame is required, NextChainOffset will need to be set,
2895 * which will just be the last segment of the frame.
2898 if (cm->cm_sglsize < (sgc_size * segsleft)) {
2900 * rem_segs is the number of segements remaining after the
2901 * segments that will go into the current frame. Since it is
2902 * known that at least one more frame is required, account for
2903 * the chain element. To know if more than one more frame is
2904 * required, just check if there will be a remainder after using
2905 * the current frame (with this chain) and the next frame. If
2906 * so the NextChainOffset must be the last element of the next
2909 current_segs = (cm->cm_sglsize / sgc_size) - 1;
2910 rem_segs = segsleft - current_segs;
2911 segs_per_frame = sc->chain_frame_size / sgc_size;
2912 if (rem_segs > segs_per_frame) {
2913 next_chain_offset = segs_per_frame - 1;
2916 ieee_sgc = &((MPI25_SGE_IO_UNION *)cm->cm_sge)->IeeeChain;
2917 ieee_sgc->Length = next_chain_offset ?
2918 htole32((uint32_t)sc->chain_frame_size) :
2919 htole32((uint32_t)rem_segs * (uint32_t)sgc_size);
2920 ieee_sgc->NextChainOffset = next_chain_offset;
2921 ieee_sgc->Flags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2922 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
2923 ieee_sgc->Address.Low = htole32(chain->chain_busaddr);
2924 ieee_sgc->Address.High = htole32(chain->chain_busaddr >> 32);
2925 cm->cm_sge = &((MPI25_SGE_IO_UNION *)chain->chain)->IeeeSimple;
2926 req = (MPI2_REQUEST_HEADER *)cm->cm_req;
2927 req->ChainOffset = (sc->chain_frame_size - sgc_size) >> 4;
2929 cm->cm_sglsize = sc->chain_frame_size;
2934 * Add one scatter-gather element to the scatter-gather list for a command.
2935 * Maintain cm_sglsize and cm_sge as the remaining size and pointer to the
2936 * next SGE to fill in, respectively. In Gen3, the MPI SGL does not have a
2937 * chain, so don't consider any chain additions.
2940 mpr_push_sge(struct mpr_command *cm, MPI2_SGE_SIMPLE64 *sge, size_t len,
2943 uint32_t saved_buf_len, saved_address_low, saved_address_high;
2947 * case 1: >=1 more segment, no room for anything (error)
2948 * case 2: 1 more segment and enough room for it
2951 if (cm->cm_sglsize < (segsleft * sizeof(MPI2_SGE_SIMPLE64))) {
2952 mpr_dprint(cm->cm_sc, MPR_ERROR,
2953 "%s: warning: Not enough room for MPI SGL in frame.\n",
2958 KASSERT(segsleft == 1,
2959 ("segsleft cannot be more than 1 for an MPI SGL; segsleft = %d\n",
2963 * There is one more segment left to add for the MPI SGL and there is
2964 * enough room in the frame to add it. This is the normal case because
2965 * MPI SGL's don't have chains, otherwise something is wrong.
2967 * If this is a bi-directional request, need to account for that
2968 * here. Save the pre-filled sge values. These will be used
2969 * either for the 2nd SGL or for a single direction SGL. If
2970 * cm_out_len is non-zero, this is a bi-directional request, so
2971 * fill in the OUT SGL first, then the IN SGL, otherwise just
2972 * fill in the IN SGL. Note that at this time, when filling in
2973 * 2 SGL's for a bi-directional request, they both use the same
2974 * DMA buffer (same cm command).
2976 saved_buf_len = sge->FlagsLength & 0x00FFFFFF;
2977 saved_address_low = sge->Address.Low;
2978 saved_address_high = sge->Address.High;
2979 if (cm->cm_out_len) {
2980 sge->FlagsLength = cm->cm_out_len |
2981 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2982 MPI2_SGE_FLAGS_END_OF_BUFFER |
2983 MPI2_SGE_FLAGS_HOST_TO_IOC |
2984 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
2985 MPI2_SGE_FLAGS_SHIFT);
2986 cm->cm_sglsize -= len;
2987 /* Endian Safe code */
2988 sge_flags = sge->FlagsLength;
2989 sge->FlagsLength = htole32(sge_flags);
2990 sge->Address.High = htole32(sge->Address.High);
2991 sge->Address.Low = htole32(sge->Address.Low);
2992 bcopy(sge, cm->cm_sge, len);
2993 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len);
2995 sge->FlagsLength = saved_buf_len |
2996 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2997 MPI2_SGE_FLAGS_END_OF_BUFFER |
2998 MPI2_SGE_FLAGS_LAST_ELEMENT |
2999 MPI2_SGE_FLAGS_END_OF_LIST |
3000 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
3001 MPI2_SGE_FLAGS_SHIFT);
3002 if (cm->cm_flags & MPR_CM_FLAGS_DATAIN) {
3004 ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
3005 MPI2_SGE_FLAGS_SHIFT);
3008 ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
3009 MPI2_SGE_FLAGS_SHIFT);
3011 sge->Address.Low = saved_address_low;
3012 sge->Address.High = saved_address_high;
3014 cm->cm_sglsize -= len;
3015 /* Endian Safe code */
3016 sge_flags = sge->FlagsLength;
3017 sge->FlagsLength = htole32(sge_flags);
3018 sge->Address.High = htole32(sge->Address.High);
3019 sge->Address.Low = htole32(sge->Address.Low);
3020 bcopy(sge, cm->cm_sge, len);
3021 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len);
3026 * Add one IEEE scatter-gather element (chain or simple) to the IEEE scatter-
3027 * gather list for a command. Maintain cm_sglsize and cm_sge as the
3028 * remaining size and pointer to the next SGE to fill in, respectively.
3031 mpr_push_ieee_sge(struct mpr_command *cm, void *sgep, int segsleft)
3033 MPI2_IEEE_SGE_SIMPLE64 *sge = sgep;
3034 int error, ieee_sge_size = sizeof(MPI25_SGE_IO_UNION);
3035 uint32_t saved_buf_len, saved_address_low, saved_address_high;
3036 uint32_t sge_length;
3039 * case 1: No room for chain or segment (error).
3040 * case 2: Two or more segments left but only room for chain.
3041 * case 3: Last segment and room for it, so set flags.
3045 * There should be room for at least one element, or there is a big
3048 if (cm->cm_sglsize < ieee_sge_size)
3049 panic("MPR: Need SGE Error Code\n");
3051 if ((segsleft >= 2) && (cm->cm_sglsize < (ieee_sge_size * 2))) {
3052 if ((error = mpr_add_chain(cm, segsleft)) != 0)
3056 if (segsleft == 1) {
3058 * If this is a bi-directional request, need to account for that
3059 * here. Save the pre-filled sge values. These will be used
3060 * either for the 2nd SGL or for a single direction SGL. If
3061 * cm_out_len is non-zero, this is a bi-directional request, so
3062 * fill in the OUT SGL first, then the IN SGL, otherwise just
3063 * fill in the IN SGL. Note that at this time, when filling in
3064 * 2 SGL's for a bi-directional request, they both use the same
3065 * DMA buffer (same cm command).
3067 saved_buf_len = sge->Length;
3068 saved_address_low = sge->Address.Low;
3069 saved_address_high = sge->Address.High;
3070 if (cm->cm_out_len) {
3071 sge->Length = cm->cm_out_len;
3072 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3073 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
3074 cm->cm_sglsize -= ieee_sge_size;
3075 /* Endian Safe code */
3076 sge_length = sge->Length;
3077 sge->Length = htole32(sge_length);
3078 sge->Address.High = htole32(sge->Address.High);
3079 sge->Address.Low = htole32(sge->Address.Low);
3080 bcopy(sgep, cm->cm_sge, ieee_sge_size);
3082 (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge +
3085 sge->Length = saved_buf_len;
3086 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3087 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
3088 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
3089 sge->Address.Low = saved_address_low;
3090 sge->Address.High = saved_address_high;
3093 cm->cm_sglsize -= ieee_sge_size;
3094 /* Endian Safe code */
3095 sge_length = sge->Length;
3096 sge->Length = htole32(sge_length);
3097 sge->Address.High = htole32(sge->Address.High);
3098 sge->Address.Low = htole32(sge->Address.Low);
3099 bcopy(sgep, cm->cm_sge, ieee_sge_size);
3100 cm->cm_sge = (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge +
3106 * Add one dma segment to the scatter-gather list for a command.
3109 mpr_add_dmaseg(struct mpr_command *cm, vm_paddr_t pa, size_t len, u_int flags,
3112 MPI2_SGE_SIMPLE64 sge;
3113 MPI2_IEEE_SGE_SIMPLE64 ieee_sge;
3115 if (!(cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE)) {
3116 ieee_sge.Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3117 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
3118 ieee_sge.Length = len;
3119 mpr_from_u64(pa, &ieee_sge.Address);
3121 return (mpr_push_ieee_sge(cm, &ieee_sge, segsleft));
3124 * This driver always uses 64-bit address elements for
3127 flags |= MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
3128 MPI2_SGE_FLAGS_64_BIT_ADDRESSING;
3129 /* Set Endian safe macro in mpr_push_sge */
3130 sge.FlagsLength = len | (flags << MPI2_SGE_FLAGS_SHIFT);
3131 mpr_from_u64(pa, &sge.Address);
3133 return (mpr_push_sge(cm, &sge, sizeof sge, segsleft));
3138 mpr_data_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3140 struct mpr_softc *sc;
3141 struct mpr_command *cm;
3142 u_int i, dir, sflags;
3144 cm = (struct mpr_command *)arg;
3148 * In this case, just print out a warning and let the chip tell the
3149 * user they did the wrong thing.
3151 if ((cm->cm_max_segs != 0) && (nsegs > cm->cm_max_segs)) {
3152 mpr_dprint(sc, MPR_ERROR, "%s: warning: busdma returned %d "
3153 "segments, more than the %d allowed\n", __func__, nsegs,
3158 * Set up DMA direction flags. Bi-directional requests are also handled
3159 * here. In that case, both direction flags will be set.
3162 if (cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) {
3164 * We have to add a special case for SMP passthrough, there
3165 * is no easy way to generically handle it. The first
3166 * S/G element is used for the command (therefore the
3167 * direction bit needs to be set). The second one is used
3168 * for the reply. We'll leave it to the caller to make
3169 * sure we only have two buffers.
3172 * Even though the busdma man page says it doesn't make
3173 * sense to have both direction flags, it does in this case.
3174 * We have one s/g element being accessed in each direction.
3176 dir = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD;
3179 * Set the direction flag on the first buffer in the SMP
3180 * passthrough request. We'll clear it for the second one.
3182 sflags |= MPI2_SGE_FLAGS_DIRECTION |
3183 MPI2_SGE_FLAGS_END_OF_BUFFER;
3184 } else if (cm->cm_flags & MPR_CM_FLAGS_DATAOUT) {
3185 sflags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
3186 dir = BUS_DMASYNC_PREWRITE;
3188 dir = BUS_DMASYNC_PREREAD;
3190 /* Check if a native SG list is needed for an NVMe PCIe device. */
3191 if (cm->cm_targ && cm->cm_targ->is_nvme &&
3192 mpr_check_pcie_native_sgl(sc, cm, segs, nsegs) == 0) {
3193 /* A native SG list was built, skip to end. */
3197 for (i = 0; i < nsegs; i++) {
3198 if ((cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) && (i != 0)) {
3199 sflags &= ~MPI2_SGE_FLAGS_DIRECTION;
3201 error = mpr_add_dmaseg(cm, segs[i].ds_addr, segs[i].ds_len,
3204 /* Resource shortage, roll back! */
3205 if (ratecheck(&sc->lastfail, &mpr_chainfail_interval))
3206 mpr_dprint(sc, MPR_INFO, "Out of chain frames, "
3207 "consider increasing hw.mpr.max_chains.\n");
3208 cm->cm_flags |= MPR_CM_FLAGS_CHAIN_FAILED;
3209 mpr_complete_command(sc, cm);
3215 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, dir);
3216 mpr_enqueue_request(sc, cm);
3222 mpr_data_cb2(void *arg, bus_dma_segment_t *segs, int nsegs, bus_size_t mapsize,
3225 mpr_data_cb(arg, segs, nsegs, error);
3229 * This is the routine to enqueue commands ansynchronously.
3230 * Note that the only error path here is from bus_dmamap_load(), which can
3231 * return EINPROGRESS if it is waiting for resources. Other than this, it's
3232 * assumed that if you have a command in-hand, then you have enough credits
3236 mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm)
3240 if (cm->cm_flags & MPR_CM_FLAGS_USE_UIO) {
3241 error = bus_dmamap_load_uio(sc->buffer_dmat, cm->cm_dmamap,
3242 &cm->cm_uio, mpr_data_cb2, cm, 0);
3243 } else if (cm->cm_flags & MPR_CM_FLAGS_USE_CCB) {
3244 error = bus_dmamap_load_ccb(sc->buffer_dmat, cm->cm_dmamap,
3245 cm->cm_data, mpr_data_cb, cm, 0);
3246 } else if ((cm->cm_data != NULL) && (cm->cm_length != 0)) {
3247 error = bus_dmamap_load(sc->buffer_dmat, cm->cm_dmamap,
3248 cm->cm_data, cm->cm_length, mpr_data_cb, cm, 0);
3250 /* Add a zero-length element as needed */
3251 if (cm->cm_sge != NULL)
3252 mpr_add_dmaseg(cm, 0, 0, 0, 1);
3253 mpr_enqueue_request(sc, cm);
3260 * This is the routine to enqueue commands synchronously. An error of
3261 * EINPROGRESS from mpr_map_command() is ignored since the command will
3262 * be executed and enqueued automatically. Other errors come from msleep().
3265 mpr_wait_command(struct mpr_softc *sc, struct mpr_command *cm, int timeout,
3269 struct timeval cur_time, start_time;
3271 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET)
3274 cm->cm_complete = NULL;
3275 cm->cm_flags |= (MPR_CM_FLAGS_WAKEUP + MPR_CM_FLAGS_POLLED);
3276 error = mpr_map_command(sc, cm);
3277 if ((error != 0) && (error != EINPROGRESS))
3280 // Check for context and wait for 50 mSec at a time until time has
3281 // expired or the command has finished. If msleep can't be used, need
3283 #if __FreeBSD_version >= 1000029
3284 if (curthread->td_no_sleeping)
3285 #else //__FreeBSD_version < 1000029
3286 if (curthread->td_pflags & TDP_NOSLEEPING)
3287 #endif //__FreeBSD_version >= 1000029
3288 sleep_flag = NO_SLEEP;
3289 getmicrotime(&start_time);
3290 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) {
3291 error = msleep(cm, &sc->mpr_mtx, 0, "mprwait", timeout*hz);
3293 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) {
3294 mpr_intr_locked(sc);
3295 if (sleep_flag == CAN_SLEEP)
3296 pause("mprwait", hz/20);
3300 getmicrotime(&cur_time);
3301 if ((cur_time.tv_sec - start_time.tv_sec) > timeout) {
3302 error = EWOULDBLOCK;
3308 if (error == EWOULDBLOCK) {
3309 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s\n", __func__);
3310 rc = mpr_reinit(sc);
3311 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" :
3319 * This is the routine to enqueue a command synchonously and poll for
3320 * completion. Its use should be rare.
3323 mpr_request_polled(struct mpr_softc *sc, struct mpr_command *cm)
3325 int error, timeout = 0, rc;
3326 struct timeval cur_time, start_time;
3330 cm->cm_flags |= MPR_CM_FLAGS_POLLED;
3331 cm->cm_complete = NULL;
3332 mpr_map_command(sc, cm);
3334 getmicrotime(&start_time);
3335 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) {
3336 mpr_intr_locked(sc);
3338 if (mtx_owned(&sc->mpr_mtx))
3339 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
3342 pause("mprpoll", hz/20);
3345 * Check for real-time timeout and fail if more than 60 seconds.
3347 getmicrotime(&cur_time);
3348 timeout = cur_time.tv_sec - start_time.tv_sec;
3350 mpr_dprint(sc, MPR_FAULT, "polling failed\n");
3357 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s\n", __func__);
3358 rc = mpr_reinit(sc);
3359 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" :
3366 * The MPT driver had a verbose interface for config pages. In this driver,
3367 * reduce it to much simplier terms, similar to the Linux driver.
3370 mpr_read_config_page(struct mpr_softc *sc, struct mpr_config_params *params)
3372 MPI2_CONFIG_REQUEST *req;
3373 struct mpr_command *cm;
3376 if (sc->mpr_flags & MPR_FLAGS_BUSY) {
3380 cm = mpr_alloc_command(sc);
3385 req = (MPI2_CONFIG_REQUEST *)cm->cm_req;
3386 req->Function = MPI2_FUNCTION_CONFIG;
3387 req->Action = params->action;
3389 req->ChainOffset = 0;
3390 req->PageAddress = params->page_address;
3391 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) {
3392 MPI2_CONFIG_EXTENDED_PAGE_HEADER *hdr;
3394 hdr = ¶ms->hdr.Ext;
3395 req->ExtPageType = hdr->ExtPageType;
3396 req->ExtPageLength = hdr->ExtPageLength;
3397 req->Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED;
3398 req->Header.PageLength = 0; /* Must be set to zero */
3399 req->Header.PageNumber = hdr->PageNumber;
3400 req->Header.PageVersion = hdr->PageVersion;
3402 MPI2_CONFIG_PAGE_HEADER *hdr;
3404 hdr = ¶ms->hdr.Struct;
3405 req->Header.PageType = hdr->PageType;
3406 req->Header.PageNumber = hdr->PageNumber;
3407 req->Header.PageLength = hdr->PageLength;
3408 req->Header.PageVersion = hdr->PageVersion;
3411 cm->cm_data = params->buffer;
3412 cm->cm_length = params->length;
3413 if (cm->cm_data != NULL) {
3414 cm->cm_sge = &req->PageBufferSGE;
3415 cm->cm_sglsize = sizeof(MPI2_SGE_IO_UNION);
3416 cm->cm_flags = MPR_CM_FLAGS_SGE_SIMPLE | MPR_CM_FLAGS_DATAIN;
3419 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
3421 cm->cm_complete_data = params;
3422 if (params->callback != NULL) {
3423 cm->cm_complete = mpr_config_complete;
3424 return (mpr_map_command(sc, cm));
3426 error = mpr_wait_command(sc, cm, 0, CAN_SLEEP);
3428 mpr_dprint(sc, MPR_FAULT,
3429 "Error %d reading config page\n", error);
3430 mpr_free_command(sc, cm);
3433 mpr_config_complete(sc, cm);
3440 mpr_write_config_page(struct mpr_softc *sc, struct mpr_config_params *params)
3446 mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm)
3448 MPI2_CONFIG_REPLY *reply;
3449 struct mpr_config_params *params;
3452 params = cm->cm_complete_data;
3454 if (cm->cm_data != NULL) {
3455 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap,
3456 BUS_DMASYNC_POSTREAD);
3457 bus_dmamap_unload(sc->buffer_dmat, cm->cm_dmamap);
3461 * XXX KDM need to do more error recovery? This results in the
3462 * device in question not getting probed.
3464 if ((cm->cm_flags & MPR_CM_FLAGS_ERROR_MASK) != 0) {
3465 params->status = MPI2_IOCSTATUS_BUSY;
3469 reply = (MPI2_CONFIG_REPLY *)cm->cm_reply;
3470 if (reply == NULL) {
3471 params->status = MPI2_IOCSTATUS_BUSY;
3474 params->status = reply->IOCStatus;
3475 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) {
3476 params->hdr.Ext.ExtPageType = reply->ExtPageType;
3477 params->hdr.Ext.ExtPageLength = reply->ExtPageLength;
3478 params->hdr.Ext.PageType = reply->Header.PageType;
3479 params->hdr.Ext.PageNumber = reply->Header.PageNumber;
3480 params->hdr.Ext.PageVersion = reply->Header.PageVersion;
3482 params->hdr.Struct.PageType = reply->Header.PageType;
3483 params->hdr.Struct.PageNumber = reply->Header.PageNumber;
3484 params->hdr.Struct.PageLength = reply->Header.PageLength;
3485 params->hdr.Struct.PageVersion = reply->Header.PageVersion;
3489 mpr_free_command(sc, cm);
3490 if (params->callback != NULL)
3491 params->callback(sc, params);