2 * Copyright (C) 2013 Intel Corporation
3 * Copyright (C) 2015 EMC Corporation
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/kernel.h>
33 #include <sys/systm.h>
35 #include <sys/endian.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/pciio.h>
40 #include <sys/queue.h>
43 #include <sys/sysctl.h>
46 #include <machine/bus.h>
47 #include <machine/intr_machdep.h>
48 #include <machine/pmap.h>
49 #include <machine/resource.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
57 * The Non-Transparent Bridge (NTB) is a device on some Intel processors that
58 * allows you to connect two systems using a PCI-e link.
60 * This module contains the hardware abstraction layer for the NTB. It allows
61 * you to send and recieve interrupts, map the memory windows and send and
62 * receive messages in the scratch-pad registers.
64 * NOTE: Much of the code in this module is shared with Linux. Any patches may
65 * be picked up and redistributed in Linux with a dual GPL/BSD license.
68 #define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT)
70 #define NTB_HB_TIMEOUT 1 /* second */
71 #define ATOM_LINK_RECOVERY_TIME 500 /* ms */
72 #define BAR_HIGH_MASK (~((1ull << 12) - 1))
74 #define DEVICE2SOFTC(dev) ((struct ntb_softc *) device_get_softc(dev))
76 #define NTB_MSIX_VER_GUARD 0xaabbccdd
77 #define NTB_MSIX_RECEIVED 0xe0f0e0f0
78 #define ONE_MB (1024u * 1024)
81 * PCI constants could be somewhere more generic, but aren't defined/used in
84 #define PCI_MSIX_ENTRY_SIZE 16
85 #define PCI_MSIX_ENTRY_LOWER_ADDR 0
86 #define PCI_MSIX_ENTRY_UPPER_ADDR 4
87 #define PCI_MSIX_ENTRY_DATA 8
89 enum ntb_device_type {
94 /* ntb_conn_type are hardware numbers, cannot change. */
96 NTB_CONN_TRANSPARENT = 0,
101 enum ntb_b2b_direction {
126 /* Device features and workarounds */
127 #define HAS_FEATURE(feature) \
128 ((ntb->features & (feature)) != 0)
133 enum ntb_device_type type;
137 struct ntb_pci_bar_info {
138 bus_space_tag_t pci_bus_tag;
139 bus_space_handle_t pci_bus_handle;
141 struct resource *pci_resource;
145 vm_memattr_t map_mode;
147 /* Configuration register offsets */
150 uint32_t pbarxlat_off;
153 struct ntb_int_info {
154 struct resource *res;
160 struct ntb_softc *ntb;
169 unsigned mw_bar[NTB_MAX_BARS];
178 struct ntb_xlat_reg {
193 struct ntb_b2b_addr {
195 uint64_t bar2_addr64;
196 uint64_t bar4_addr64;
197 uint64_t bar4_addr32;
198 uint64_t bar5_addr32;
201 struct ntb_msix_data {
208 enum ntb_device_type type;
211 struct ntb_pci_bar_info bar_info[NTB_MAX_BARS];
212 struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS];
213 uint32_t allocated_interrupts;
215 struct ntb_msix_data peer_msix_data[XEON_NONLINK_DB_MSIX_BITS];
216 struct ntb_msix_data msix_data[XEON_NONLINK_DB_MSIX_BITS];
219 struct ntb_pci_bar_info *peer_lapic_bar;
220 struct callout peer_msix_work;
222 struct callout heartbeat_timer;
223 struct callout lr_timer;
226 const struct ntb_ctx_ops *ctx_ops;
227 struct ntb_vec *msix_vec;
228 #define CTX_LOCK(sc) mtx_lock(&(sc)->ctx_lock)
229 #define CTX_UNLOCK(sc) mtx_unlock(&(sc)->ctx_lock)
230 #define CTX_ASSERT(sc,f) mtx_assert(&(sc)->ctx_lock, (f))
234 enum ntb_conn_type conn_type;
235 enum ntb_b2b_direction dev_type;
237 /* Offset of peer bar0 in B2B BAR */
239 /* Memory window used to access peer bar0 */
240 #define B2B_MW_DISABLED UINT8_MAX
247 uint8_t db_vec_count;
248 uint8_t db_vec_shift;
250 /* Protects local db_mask. */
251 #define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock)
252 #define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock)
253 #define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f))
254 struct mtx db_mask_lock;
256 volatile uint32_t ntb_ctl;
257 volatile uint32_t lnk_sta;
259 uint64_t db_valid_mask;
260 uint64_t db_link_mask;
263 int last_ts; /* ticks @ last irq */
265 const struct ntb_reg *reg;
266 const struct ntb_alt_reg *self_reg;
267 const struct ntb_alt_reg *peer_reg;
268 const struct ntb_xlat_reg *xlat_reg;
272 static __inline uint64_t
273 bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
277 return (bus_space_read_4(tag, handle, offset) |
278 ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32);
282 bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle,
283 bus_size_t offset, uint64_t val)
286 bus_space_write_4(tag, handle, offset, val);
287 bus_space_write_4(tag, handle, offset + 4, val >> 32);
291 #define ntb_bar_read(SIZE, bar, offset) \
292 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \
293 ntb->bar_info[(bar)].pci_bus_handle, (offset))
294 #define ntb_bar_write(SIZE, bar, offset, val) \
295 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \
296 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val))
297 #define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset)
298 #define ntb_reg_write(SIZE, offset, val) \
299 ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val)
300 #define ntb_mw_read(SIZE, offset) \
301 ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset)
302 #define ntb_mw_write(SIZE, offset, val) \
303 ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \
306 static int ntb_probe(device_t device);
307 static int ntb_attach(device_t device);
308 static int ntb_detach(device_t device);
309 static unsigned ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx);
310 static inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw);
311 static inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar);
312 static inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar,
313 uint32_t *base, uint32_t *xlat, uint32_t *lmt);
314 static int ntb_map_pci_bars(struct ntb_softc *ntb);
315 static int ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx,
317 static void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *,
319 static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar);
320 static int map_memory_window_bar(struct ntb_softc *ntb,
321 struct ntb_pci_bar_info *bar);
322 static void ntb_unmap_pci_bar(struct ntb_softc *ntb);
323 static int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail);
324 static int ntb_init_isr(struct ntb_softc *ntb);
325 static int ntb_setup_legacy_interrupt(struct ntb_softc *ntb);
326 static int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors);
327 static void ntb_teardown_interrupts(struct ntb_softc *ntb);
328 static inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector);
329 static void ntb_interrupt(struct ntb_softc *, uint32_t vec);
330 static void ndev_vec_isr(void *arg);
331 static void ndev_irq_isr(void *arg);
332 static inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff);
333 static inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t);
334 static inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t);
335 static int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors);
336 static void ntb_free_msix_vec(struct ntb_softc *ntb);
337 static void ntb_get_msix_info(struct ntb_softc *ntb);
338 static void ntb_exchange_msix(void *);
339 static struct ntb_hw_info *ntb_get_device_info(uint32_t device_id);
340 static void ntb_detect_max_mw(struct ntb_softc *ntb);
341 static int ntb_detect_xeon(struct ntb_softc *ntb);
342 static int ntb_detect_atom(struct ntb_softc *ntb);
343 static int ntb_xeon_init_dev(struct ntb_softc *ntb);
344 static int ntb_atom_init_dev(struct ntb_softc *ntb);
345 static void ntb_teardown_xeon(struct ntb_softc *ntb);
346 static void configure_atom_secondary_side_bars(struct ntb_softc *ntb);
347 static void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx,
348 enum ntb_bar regbar);
349 static void xeon_set_sbar_base_and_limit(struct ntb_softc *,
350 uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar);
351 static void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr,
353 static int xeon_setup_b2b_mw(struct ntb_softc *,
354 const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr);
355 static int xeon_setup_msix_bar(struct ntb_softc *);
356 static inline bool link_is_up(struct ntb_softc *ntb);
357 static inline bool _xeon_link_is_up(struct ntb_softc *ntb);
358 static inline bool atom_link_is_err(struct ntb_softc *ntb);
359 static inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *);
360 static inline enum ntb_width ntb_link_sta_width(struct ntb_softc *);
361 static void atom_link_hb(void *arg);
362 static void ntb_db_event(struct ntb_softc *ntb, uint32_t vec);
363 static void recover_atom_link(void *arg);
364 static bool ntb_poll_link(struct ntb_softc *ntb);
365 static void save_bar_parameters(struct ntb_pci_bar_info *bar);
366 static void ntb_sysctl_init(struct ntb_softc *);
367 static int sysctl_handle_features(SYSCTL_HANDLER_ARGS);
368 static int sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS);
369 static int sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS);
370 static int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS);
371 static int sysctl_handle_register(SYSCTL_HANDLER_ARGS);
373 static unsigned g_ntb_hw_debug_level;
374 TUNABLE_INT("hw.ntb.debug_level", &g_ntb_hw_debug_level);
375 SYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN,
376 &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose");
377 #define ntb_printf(lvl, ...) do { \
378 if ((lvl) <= g_ntb_hw_debug_level) { \
379 device_printf(ntb->device, __VA_ARGS__); \
383 #define _NTB_PAT_UC 0
384 #define _NTB_PAT_WC 1
385 #define _NTB_PAT_WT 4
386 #define _NTB_PAT_WP 5
387 #define _NTB_PAT_WB 6
388 #define _NTB_PAT_UCM 7
389 static unsigned g_ntb_mw_pat = _NTB_PAT_UC;
390 TUNABLE_INT("hw.ntb.default_mw_pat", &g_ntb_mw_pat);
391 SYSCTL_UINT(_hw_ntb, OID_AUTO, default_mw_pat, CTLFLAG_RDTUN,
392 &g_ntb_mw_pat, 0, "Configure the default memory window cache flags (PAT): "
393 "UC: " __XSTRING(_NTB_PAT_UC) ", "
394 "WC: " __XSTRING(_NTB_PAT_WC) ", "
395 "WT: " __XSTRING(_NTB_PAT_WT) ", "
396 "WP: " __XSTRING(_NTB_PAT_WP) ", "
397 "WB: " __XSTRING(_NTB_PAT_WB) ", "
398 "UC-: " __XSTRING(_NTB_PAT_UCM));
400 static inline vm_memattr_t
404 switch (g_ntb_mw_pat) {
406 return (VM_MEMATTR_WRITE_COMBINING);
408 return (VM_MEMATTR_WRITE_THROUGH);
410 return (VM_MEMATTR_WRITE_PROTECTED);
412 return (VM_MEMATTR_WRITE_BACK);
414 return (VM_MEMATTR_WEAK_UNCACHEABLE);
418 return (VM_MEMATTR_UNCACHEABLE);
423 * Well, this obviously doesn't belong here, but it doesn't seem to exist
424 * anywhere better yet.
426 static inline const char *
427 ntb_vm_memattr_to_str(vm_memattr_t pat)
431 case VM_MEMATTR_WRITE_COMBINING:
432 return ("WRITE_COMBINING");
433 case VM_MEMATTR_WRITE_THROUGH:
434 return ("WRITE_THROUGH");
435 case VM_MEMATTR_WRITE_PROTECTED:
436 return ("WRITE_PROTECTED");
437 case VM_MEMATTR_WRITE_BACK:
438 return ("WRITE_BACK");
439 case VM_MEMATTR_WEAK_UNCACHEABLE:
441 case VM_MEMATTR_UNCACHEABLE:
442 return ("UNCACHEABLE");
448 static int g_ntb_msix_idx = 0;
449 SYSCTL_INT(_hw_ntb, OID_AUTO, msix_mw_idx, CTLFLAG_RDTUN, &g_ntb_msix_idx,
450 0, "Use this memory window to access the peer MSIX message complex on "
451 "certain Xeon-based NTB systems, as a workaround for a hardware errata. "
452 "Like b2b_mw_idx, negative values index from the last available memory "
453 "window. (Applies on Xeon platforms with SB01BASE_LOCKUP errata.)");
455 static int g_ntb_mw_idx = -1;
456 TUNABLE_INT("hw.ntb.b2b_mw_idx", &g_ntb_mw_idx);
457 SYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx,
458 0, "Use this memory window to access the peer NTB registers. A "
459 "non-negative value starts from the first MW index; a negative value "
460 "starts from the last MW index. The default is -1, i.e., the last "
461 "available memory window. Both sides of the NTB MUST set the same "
462 "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)");
464 static struct ntb_hw_info pci_ids[] = {
465 /* XXX: PS/SS IDs left out until they are supported. */
466 { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B",
469 { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B",
470 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 },
471 { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B",
472 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 },
473 { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON,
474 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 |
475 NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K },
476 { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON,
477 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 |
478 NTB_SB01BASE_LOCKUP },
479 { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON,
480 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 |
481 NTB_SB01BASE_LOCKUP },
483 { 0x00000000, NULL, NTB_ATOM, 0 }
486 static const struct ntb_reg atom_reg = {
487 .ntb_ctl = ATOM_NTBCNTL_OFFSET,
488 .lnk_sta = ATOM_LINK_STATUS_OFFSET,
489 .db_size = sizeof(uint64_t),
490 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 },
493 static const struct ntb_alt_reg atom_pri_reg = {
494 .db_bell = ATOM_PDOORBELL_OFFSET,
495 .db_mask = ATOM_PDBMSK_OFFSET,
496 .spad = ATOM_SPAD_OFFSET,
499 static const struct ntb_alt_reg atom_b2b_reg = {
500 .db_bell = ATOM_B2B_DOORBELL_OFFSET,
501 .spad = ATOM_B2B_SPAD_OFFSET,
504 static const struct ntb_xlat_reg atom_sec_xlat = {
506 /* "FIXME" says the Linux driver. */
507 .bar0_base = ATOM_SBAR0BASE_OFFSET,
508 .bar2_base = ATOM_SBAR2BASE_OFFSET,
509 .bar4_base = ATOM_SBAR4BASE_OFFSET,
511 .bar2_limit = ATOM_SBAR2LMT_OFFSET,
512 .bar4_limit = ATOM_SBAR4LMT_OFFSET,
515 .bar2_xlat = ATOM_SBAR2XLAT_OFFSET,
516 .bar4_xlat = ATOM_SBAR4XLAT_OFFSET,
519 static const struct ntb_reg xeon_reg = {
520 .ntb_ctl = XEON_NTBCNTL_OFFSET,
521 .lnk_sta = XEON_LINK_STATUS_OFFSET,
522 .db_size = sizeof(uint16_t),
523 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 },
526 static const struct ntb_alt_reg xeon_pri_reg = {
527 .db_bell = XEON_PDOORBELL_OFFSET,
528 .db_mask = XEON_PDBMSK_OFFSET,
529 .spad = XEON_SPAD_OFFSET,
532 static const struct ntb_alt_reg xeon_b2b_reg = {
533 .db_bell = XEON_B2B_DOORBELL_OFFSET,
534 .spad = XEON_B2B_SPAD_OFFSET,
537 static const struct ntb_xlat_reg xeon_sec_xlat = {
538 .bar0_base = XEON_SBAR0BASE_OFFSET,
539 .bar2_base = XEON_SBAR2BASE_OFFSET,
540 .bar4_base = XEON_SBAR4BASE_OFFSET,
541 .bar5_base = XEON_SBAR5BASE_OFFSET,
543 .bar2_limit = XEON_SBAR2LMT_OFFSET,
544 .bar4_limit = XEON_SBAR4LMT_OFFSET,
545 .bar5_limit = XEON_SBAR5LMT_OFFSET,
547 .bar2_xlat = XEON_SBAR2XLAT_OFFSET,
548 .bar4_xlat = XEON_SBAR4XLAT_OFFSET,
549 .bar5_xlat = XEON_SBAR5XLAT_OFFSET,
552 static struct ntb_b2b_addr xeon_b2b_usd_addr = {
553 .bar0_addr = XEON_B2B_BAR0_ADDR,
554 .bar2_addr64 = XEON_B2B_BAR2_ADDR64,
555 .bar4_addr64 = XEON_B2B_BAR4_ADDR64,
556 .bar4_addr32 = XEON_B2B_BAR4_ADDR32,
557 .bar5_addr32 = XEON_B2B_BAR5_ADDR32,
560 static struct ntb_b2b_addr xeon_b2b_dsd_addr = {
561 .bar0_addr = XEON_B2B_BAR0_ADDR,
562 .bar2_addr64 = XEON_B2B_BAR2_ADDR64,
563 .bar4_addr64 = XEON_B2B_BAR4_ADDR64,
564 .bar4_addr32 = XEON_B2B_BAR4_ADDR32,
565 .bar5_addr32 = XEON_B2B_BAR5_ADDR32,
568 SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0,
569 "B2B MW segment overrides -- MUST be the same on both sides");
571 TUNABLE_QUAD("hw.ntb.usd_bar2_addr64", &xeon_b2b_usd_addr.bar2_addr64);
572 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN,
573 &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon "
574 "hardware, use this 64-bit address on the bus between the NTB devices for "
575 "the window at BAR2, on the upstream side of the link. MUST be the same "
576 "address on both sides.");
577 TUNABLE_QUAD("hw.ntb.usd_bar4_addr64", &xeon_b2b_usd_addr.bar4_addr64);
578 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN,
579 &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4.");
580 TUNABLE_QUAD("hw.ntb.usd_bar4_addr32", &xeon_b2b_usd_addr.bar4_addr32);
581 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN,
582 &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 "
583 "(split-BAR mode).");
584 TUNABLE_QUAD("hw.ntb.usd_bar5_addr32", &xeon_b2b_usd_addr.bar5_addr32);
585 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN,
586 &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 "
587 "(split-BAR mode).");
589 TUNABLE_QUAD("hw.ntb.dsd_bar2_addr64", &xeon_b2b_dsd_addr.bar2_addr64);
590 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN,
591 &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon "
592 "hardware, use this 64-bit address on the bus between the NTB devices for "
593 "the window at BAR2, on the downstream side of the link. MUST be the same"
594 " address on both sides.");
595 TUNABLE_QUAD("hw.ntb.dsd_bar4_addr64", &xeon_b2b_dsd_addr.bar4_addr64);
596 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN,
597 &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4.");
598 TUNABLE_QUAD("hw.ntb.dsd_bar4_addr32", &xeon_b2b_dsd_addr.bar4_addr32);
599 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN,
600 &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 "
601 "(split-BAR mode).");
602 TUNABLE_QUAD("hw.ntb.dsd_bar5_addr32", &xeon_b2b_dsd_addr.bar5_addr32);
603 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN,
604 &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 "
605 "(split-BAR mode).");
608 * OS <-> Driver interface structures
610 MALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations");
612 static device_method_t ntb_pci_methods[] = {
613 /* Device interface */
614 DEVMETHOD(device_probe, ntb_probe),
615 DEVMETHOD(device_attach, ntb_attach),
616 DEVMETHOD(device_detach, ntb_detach),
620 static driver_t ntb_pci_driver = {
623 sizeof(struct ntb_softc),
626 static devclass_t ntb_devclass;
627 DRIVER_MODULE(ntb_hw, pci, ntb_pci_driver, ntb_devclass, NULL, NULL);
628 MODULE_VERSION(ntb_hw, 1);
630 SYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls");
633 * OS <-> Driver linkage functions
636 ntb_probe(device_t device)
638 struct ntb_hw_info *p;
640 p = ntb_get_device_info(pci_get_devid(device));
644 device_set_desc(device, p->desc);
649 ntb_attach(device_t device)
651 struct ntb_softc *ntb;
652 struct ntb_hw_info *p;
655 ntb = DEVICE2SOFTC(device);
656 p = ntb_get_device_info(pci_get_devid(device));
658 ntb->device = device;
660 ntb->features = p->features;
661 ntb->b2b_mw_idx = B2B_MW_DISABLED;
662 ntb->msix_mw_idx = B2B_MW_DISABLED;
664 /* Heartbeat timer for NTB_ATOM since there is no link interrupt */
665 callout_init(&ntb->heartbeat_timer, CALLOUT_MPSAFE);
666 callout_init(&ntb->lr_timer, CALLOUT_MPSAFE);
667 callout_init(&ntb->peer_msix_work, 1);
668 mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN);
669 mtx_init(&ntb->ctx_lock, "ntb ctx", NULL, MTX_DEF);
671 if (ntb->type == NTB_ATOM)
672 error = ntb_detect_atom(ntb);
674 error = ntb_detect_xeon(ntb);
678 ntb_detect_max_mw(ntb);
680 pci_enable_busmaster(ntb->device);
682 error = ntb_map_pci_bars(ntb);
685 if (ntb->type == NTB_ATOM)
686 error = ntb_atom_init_dev(ntb);
688 error = ntb_xeon_init_dev(ntb);
696 ntb_sysctl_init(ntb);
705 ntb_detach(device_t device)
707 struct ntb_softc *ntb;
709 ntb = DEVICE2SOFTC(device);
711 if (ntb->self_reg != NULL) {
713 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_valid_mask);
716 callout_drain(&ntb->heartbeat_timer);
717 callout_drain(&ntb->lr_timer);
718 callout_drain(&ntb->peer_msix_work);
719 pci_disable_busmaster(ntb->device);
720 if (ntb->type == NTB_XEON)
721 ntb_teardown_xeon(ntb);
722 ntb_teardown_interrupts(ntb);
724 mtx_destroy(&ntb->db_mask_lock);
725 mtx_destroy(&ntb->ctx_lock);
727 ntb_unmap_pci_bar(ntb);
733 * Driver internal routines
735 static inline enum ntb_bar
736 ntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw)
739 KASSERT(mw < ntb->mw_count,
740 ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count));
741 KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw"));
743 return (ntb->reg->mw_bar[mw]);
747 bar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar)
749 /* XXX This assertion could be stronger. */
750 KASSERT(bar < NTB_MAX_BARS, ("bogus bar"));
751 return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(NTB_SPLIT_BAR));
755 bar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base,
756 uint32_t *xlat, uint32_t *lmt)
758 uint32_t basev, lmtv, xlatv;
762 basev = ntb->xlat_reg->bar2_base;
763 lmtv = ntb->xlat_reg->bar2_limit;
764 xlatv = ntb->xlat_reg->bar2_xlat;
767 basev = ntb->xlat_reg->bar4_base;
768 lmtv = ntb->xlat_reg->bar4_limit;
769 xlatv = ntb->xlat_reg->bar4_xlat;
772 basev = ntb->xlat_reg->bar5_base;
773 lmtv = ntb->xlat_reg->bar5_limit;
774 xlatv = ntb->xlat_reg->bar5_xlat;
777 KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS,
779 basev = lmtv = xlatv = 0;
792 ntb_map_pci_bars(struct ntb_softc *ntb)
796 ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0);
797 rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]);
801 ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2);
802 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]);
805 ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET;
806 ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET;
807 ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET;
809 ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4);
810 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]);
813 ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET;
814 ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET;
815 ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET;
817 if (!HAS_FEATURE(NTB_SPLIT_BAR))
820 ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5);
821 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]);
822 ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET;
823 ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET;
824 ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET;
828 device_printf(ntb->device,
829 "unable to allocate pci resource\n");
834 print_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar,
838 device_printf(ntb->device,
839 "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n",
840 PCI_RID2BAR(bar->pci_resource_id), bar->vbase,
841 (char *)bar->vbase + bar->size - 1,
842 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1),
843 (uintmax_t)bar->size, kind);
847 map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar)
850 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY,
851 &bar->pci_resource_id, RF_ACTIVE);
852 if (bar->pci_resource == NULL)
855 save_bar_parameters(bar);
856 bar->map_mode = VM_MEMATTR_UNCACHEABLE;
857 print_map_success(ntb, bar, "mmr");
862 map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar)
865 vm_memattr_t mapmode;
866 uint8_t bar_size_bits = 0;
868 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY,
869 &bar->pci_resource_id, RF_ACTIVE);
871 if (bar->pci_resource == NULL)
874 save_bar_parameters(bar);
876 * Ivytown NTB BAR sizes are misreported by the hardware due to a
877 * hardware issue. To work around this, query the size it should be
878 * configured to by the device and modify the resource to correspond to
879 * this new size. The BIOS on systems with this problem is required to
880 * provide enough address space to allow the driver to make this change
883 * Ideally I could have just specified the size when I allocated the
885 * bus_alloc_resource(ntb->device,
886 * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul,
887 * 1ul << bar_size_bits, RF_ACTIVE);
888 * but the PCI driver does not honor the size in this call, so we have
889 * to modify it after the fact.
891 if (HAS_FEATURE(NTB_BAR_SIZE_4K)) {
892 if (bar->pci_resource_id == PCIR_BAR(2))
893 bar_size_bits = pci_read_config(ntb->device,
894 XEON_PBAR23SZ_OFFSET, 1);
896 bar_size_bits = pci_read_config(ntb->device,
897 XEON_PBAR45SZ_OFFSET, 1);
899 rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY,
900 bar->pci_resource, bar->pbase,
901 bar->pbase + (1ul << bar_size_bits) - 1);
903 device_printf(ntb->device,
904 "unable to resize bar\n");
908 save_bar_parameters(bar);
911 bar->map_mode = VM_MEMATTR_UNCACHEABLE;
912 print_map_success(ntb, bar, "mw");
915 * Optionally, mark MW BARs as anything other than UC to improve
918 mapmode = ntb_pat_flags();
919 if (mapmode == bar->map_mode)
922 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode);
924 bar->map_mode = mapmode;
925 device_printf(ntb->device,
926 "Marked BAR%d v:[%p-%p] p:[%p-%p] as "
928 PCI_RID2BAR(bar->pci_resource_id), bar->vbase,
929 (char *)bar->vbase + bar->size - 1,
930 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1),
931 ntb_vm_memattr_to_str(mapmode));
933 device_printf(ntb->device,
934 "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as "
936 PCI_RID2BAR(bar->pci_resource_id), bar->vbase,
937 (char *)bar->vbase + bar->size - 1,
938 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1),
939 ntb_vm_memattr_to_str(mapmode), rc);
945 ntb_unmap_pci_bar(struct ntb_softc *ntb)
947 struct ntb_pci_bar_info *current_bar;
950 for (i = 0; i < NTB_MAX_BARS; i++) {
951 current_bar = &ntb->bar_info[i];
952 if (current_bar->pci_resource != NULL)
953 bus_release_resource(ntb->device, SYS_RES_MEMORY,
954 current_bar->pci_resource_id,
955 current_bar->pci_resource);
960 ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors)
965 for (i = 0; i < num_vectors; i++) {
966 ntb->int_info[i].rid = i + 1;
967 ntb->int_info[i].res = bus_alloc_resource_any(ntb->device,
968 SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE);
969 if (ntb->int_info[i].res == NULL) {
970 device_printf(ntb->device,
971 "bus_alloc_resource failed\n");
974 ntb->int_info[i].tag = NULL;
975 ntb->allocated_interrupts++;
976 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res,
977 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr,
978 &ntb->msix_vec[i], &ntb->int_info[i].tag);
980 device_printf(ntb->device, "bus_setup_intr failed\n");
988 * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector
989 * cannot be allocated for each MSI-X message. JHB seems to think remapping
990 * should be okay. This tunable should enable us to test that hypothesis
991 * when someone gets their hands on some Xeon hardware.
993 static int ntb_force_remap_mode;
994 TUNABLE_INT("hw.ntb.force_remap_mode", &ntb_force_remap_mode);
995 SYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN,
996 &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped"
997 " to a smaller number of ithreads, even if the desired number are "
1001 * In case it is NOT ok, give consumers an abort button.
1003 static int ntb_prefer_intx;
1004 TUNABLE_INT("hw.ntb.prefer_intx_to_remap", &ntb_prefer_intx);
1005 SYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN,
1006 &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather "
1007 "than remapping MSI-X messages over available slots (match Linux driver "
1011 * Remap the desired number of MSI-X messages to available ithreads in a simple
1012 * round-robin fashion.
1015 ntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail)
1021 if (ntb_prefer_intx != 0)
1024 vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK);
1026 for (i = 0; i < desired; i++)
1027 vectors[i] = (i % avail) + 1;
1029 rc = pci_remap_msix(dev, desired, vectors);
1030 free(vectors, M_NTB);
1035 ntb_init_isr(struct ntb_softc *ntb)
1037 uint32_t desired_vectors, num_vectors;
1040 ntb->allocated_interrupts = 0;
1041 ntb->last_ts = ticks;
1044 * Mask all doorbell interrupts. (Except link events!)
1047 ntb->db_mask = ntb->db_valid_mask;
1048 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
1049 DB_MASK_UNLOCK(ntb);
1051 num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device),
1053 if (desired_vectors >= 1) {
1054 rc = pci_alloc_msix(ntb->device, &num_vectors);
1056 if (ntb_force_remap_mode != 0 && rc == 0 &&
1057 num_vectors == desired_vectors)
1060 if (rc == 0 && num_vectors < desired_vectors) {
1061 rc = ntb_remap_msix(ntb->device, desired_vectors,
1064 num_vectors = desired_vectors;
1066 pci_release_msi(ntb->device);
1073 if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) {
1074 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) {
1075 device_printf(ntb->device,
1076 "Errata workaround does not support MSI or INTX\n");
1080 ntb->db_vec_count = 1;
1081 ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT;
1082 rc = ntb_setup_legacy_interrupt(ntb);
1084 if (num_vectors - 1 != XEON_NONLINK_DB_MSIX_BITS &&
1085 HAS_FEATURE(NTB_SB01BASE_LOCKUP)) {
1086 device_printf(ntb->device,
1087 "Errata workaround expects %d doorbell bits\n",
1088 XEON_NONLINK_DB_MSIX_BITS);
1092 ntb_create_msix_vec(ntb, num_vectors);
1093 rc = ntb_setup_msix(ntb, num_vectors);
1094 if (rc == 0 && HAS_FEATURE(NTB_SB01BASE_LOCKUP))
1095 ntb_get_msix_info(ntb);
1098 device_printf(ntb->device,
1099 "Error allocating interrupts: %d\n", rc);
1100 ntb_free_msix_vec(ntb);
1107 ntb_setup_legacy_interrupt(struct ntb_softc *ntb)
1111 ntb->int_info[0].rid = 0;
1112 ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ,
1113 &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE);
1114 if (ntb->int_info[0].res == NULL) {
1115 device_printf(ntb->device, "bus_alloc_resource failed\n");
1119 ntb->int_info[0].tag = NULL;
1120 ntb->allocated_interrupts = 1;
1122 rc = bus_setup_intr(ntb->device, ntb->int_info[0].res,
1123 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr,
1124 ntb, &ntb->int_info[0].tag);
1126 device_printf(ntb->device, "bus_setup_intr failed\n");
1134 ntb_teardown_interrupts(struct ntb_softc *ntb)
1136 struct ntb_int_info *current_int;
1139 for (i = 0; i < ntb->allocated_interrupts; i++) {
1140 current_int = &ntb->int_info[i];
1141 if (current_int->tag != NULL)
1142 bus_teardown_intr(ntb->device, current_int->res,
1145 if (current_int->res != NULL)
1146 bus_release_resource(ntb->device, SYS_RES_IRQ,
1147 rman_get_rid(current_int->res), current_int->res);
1150 ntb_free_msix_vec(ntb);
1151 pci_release_msi(ntb->device);
1155 * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it
1156 * out to make code clearer.
1158 static inline uint64_t
1159 db_ioread(struct ntb_softc *ntb, uint64_t regoff)
1162 if (ntb->type == NTB_ATOM)
1163 return (ntb_reg_read(8, regoff));
1165 KASSERT(ntb->type == NTB_XEON, ("bad ntb type"));
1167 return (ntb_reg_read(2, regoff));
1171 db_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val)
1174 KASSERT((val & ~ntb->db_valid_mask) == 0,
1175 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__,
1176 (uintmax_t)(val & ~ntb->db_valid_mask),
1177 (uintmax_t)ntb->db_valid_mask));
1179 if (regoff == ntb->self_reg->db_mask)
1180 DB_MASK_ASSERT(ntb, MA_OWNED);
1181 db_iowrite_raw(ntb, regoff, val);
1185 db_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val)
1188 if (ntb->type == NTB_ATOM) {
1189 ntb_reg_write(8, regoff, val);
1193 KASSERT(ntb->type == NTB_XEON, ("bad ntb type"));
1194 ntb_reg_write(2, regoff, (uint16_t)val);
1198 ntb_db_set_mask(struct ntb_softc *ntb, uint64_t bits)
1201 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP))
1205 ntb->db_mask |= bits;
1206 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
1207 DB_MASK_UNLOCK(ntb);
1211 ntb_db_clear_mask(struct ntb_softc *ntb, uint64_t bits)
1214 KASSERT((bits & ~ntb->db_valid_mask) == 0,
1215 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__,
1216 (uintmax_t)(bits & ~ntb->db_valid_mask),
1217 (uintmax_t)ntb->db_valid_mask));
1219 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP))
1223 ntb->db_mask &= ~bits;
1224 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
1225 DB_MASK_UNLOCK(ntb);
1229 ntb_db_read(struct ntb_softc *ntb)
1232 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) {
1237 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
1238 if (ntb->msix_vec[i].masked != 0)
1239 res |= ntb_db_vector_mask(ntb, i);
1244 return (db_ioread(ntb, ntb->self_reg->db_bell));
1248 ntb_db_clear(struct ntb_softc *ntb, uint64_t bits)
1251 KASSERT((bits & ~ntb->db_valid_mask) == 0,
1252 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__,
1253 (uintmax_t)(bits & ~ntb->db_valid_mask),
1254 (uintmax_t)ntb->db_valid_mask));
1256 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) {
1259 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
1260 if ((bits & ntb_db_vector_mask(ntb, i)) != 0) {
1262 if (ntb->msix_vec[i].masked != 0) {
1263 /* XXX These need a public API. */
1265 pci_unmask_msix(ntb->device, i);
1267 ntb->msix_vec[i].masked = 0;
1269 DB_MASK_UNLOCK(ntb);
1275 db_iowrite(ntb, ntb->self_reg->db_bell, bits);
1278 static inline uint64_t
1279 ntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector)
1281 uint64_t shift, mask;
1283 shift = ntb->db_vec_shift;
1284 mask = (1ull << shift) - 1;
1285 return (mask << (shift * db_vector));
1289 ntb_interrupt(struct ntb_softc *ntb, uint32_t vec)
1293 ntb->last_ts = ticks;
1294 vec_mask = ntb_vec_mask(ntb, vec);
1296 if ((vec_mask & ntb->db_link_mask) != 0) {
1297 if (ntb_poll_link(ntb))
1298 ntb_link_event(ntb);
1301 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP) &&
1302 (vec_mask & ntb->db_link_mask) == 0) {
1304 if (ntb->msix_vec[vec].masked == 0) {
1305 /* XXX These need a public API. */
1307 pci_mask_msix(ntb->device, vec);
1309 ntb->msix_vec[vec].masked = 1;
1311 DB_MASK_UNLOCK(ntb);
1314 if ((vec_mask & ntb->db_valid_mask) != 0)
1315 ntb_db_event(ntb, vec);
1319 ndev_vec_isr(void *arg)
1321 struct ntb_vec *nvec = arg;
1323 ntb_interrupt(nvec->ntb, nvec->num);
1327 ndev_irq_isr(void *arg)
1329 /* If we couldn't set up MSI-X, we only have the one vector. */
1330 ntb_interrupt(arg, 0);
1334 ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors)
1338 ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB,
1340 for (i = 0; i < num_vectors; i++) {
1341 ntb->msix_vec[i].num = i;
1342 ntb->msix_vec[i].ntb = ntb;
1349 ntb_free_msix_vec(struct ntb_softc *ntb)
1352 if (ntb->msix_vec == NULL)
1355 free(ntb->msix_vec, M_NTB);
1356 ntb->msix_vec = NULL;
1360 ntb_get_msix_info(struct ntb_softc *ntb)
1362 struct pci_devinfo *dinfo;
1363 struct pcicfg_msix *msix;
1364 uint32_t laddr, data, i, offset;
1366 dinfo = device_get_ivars(ntb->device);
1367 msix = &dinfo->cfg.msix;
1371 CTASSERT(XEON_NONLINK_DB_MSIX_BITS == nitems(ntb->msix_data));
1373 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
1374 offset = msix->msix_table_offset + i * PCI_MSIX_ENTRY_SIZE;
1376 laddr = bus_read_4(msix->msix_table_res, offset +
1377 PCI_MSIX_ENTRY_LOWER_ADDR);
1378 ntb_printf(2, "local lower MSIX addr(%u): 0x%x\n", i, laddr);
1380 KASSERT((laddr & MSI_INTEL_ADDR_BASE) == MSI_INTEL_ADDR_BASE,
1381 ("local MSIX addr 0x%x not in MSI base 0x%x", laddr,
1382 MSI_INTEL_ADDR_BASE));
1383 ntb->msix_data[i].nmd_ofs = laddr & ~MSI_INTEL_ADDR_BASE;
1385 data = bus_read_4(msix->msix_table_res, offset +
1386 PCI_MSIX_ENTRY_DATA);
1387 ntb_printf(2, "local MSIX data(%u): 0x%x\n", i, data);
1389 ntb->msix_data[i].nmd_data = data;
1393 static struct ntb_hw_info *
1394 ntb_get_device_info(uint32_t device_id)
1396 struct ntb_hw_info *ep = pci_ids;
1398 while (ep->device_id) {
1399 if (ep->device_id == device_id)
1407 ntb_teardown_xeon(struct ntb_softc *ntb)
1410 if (ntb->reg != NULL)
1411 ntb_link_disable(ntb);
1415 ntb_detect_max_mw(struct ntb_softc *ntb)
1418 if (ntb->type == NTB_ATOM) {
1419 ntb->mw_count = ATOM_MW_COUNT;
1423 if (HAS_FEATURE(NTB_SPLIT_BAR))
1424 ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT;
1426 ntb->mw_count = XEON_SNB_MW_COUNT;
1430 ntb_detect_xeon(struct ntb_softc *ntb)
1432 uint8_t ppd, conn_type;
1434 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1);
1437 if ((ppd & XEON_PPD_DEV_TYPE) != 0)
1438 ntb->dev_type = NTB_DEV_DSD;
1440 ntb->dev_type = NTB_DEV_USD;
1442 if ((ppd & XEON_PPD_SPLIT_BAR) != 0)
1443 ntb->features |= NTB_SPLIT_BAR;
1446 * SDOORBELL errata workaround gets in the way of SB01BASE_LOCKUP
1447 * errata workaround; only do one at a time.
1449 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP))
1450 ntb->features &= ~NTB_SDOORBELL_LOCKUP;
1452 conn_type = ppd & XEON_PPD_CONN_TYPE;
1453 switch (conn_type) {
1455 ntb->conn_type = conn_type;
1458 case NTB_CONN_TRANSPARENT:
1460 device_printf(ntb->device, "Unsupported connection type: %u\n",
1461 (unsigned)conn_type);
1468 ntb_detect_atom(struct ntb_softc *ntb)
1470 uint32_t ppd, conn_type;
1472 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4);
1475 if ((ppd & ATOM_PPD_DEV_TYPE) != 0)
1476 ntb->dev_type = NTB_DEV_DSD;
1478 ntb->dev_type = NTB_DEV_USD;
1480 conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8;
1481 switch (conn_type) {
1483 ntb->conn_type = conn_type;
1486 device_printf(ntb->device, "Unsupported NTB configuration\n");
1493 ntb_xeon_init_dev(struct ntb_softc *ntb)
1497 ntb->spad_count = XEON_SPAD_COUNT;
1498 ntb->db_count = XEON_DB_COUNT;
1499 ntb->db_link_mask = XEON_DB_LINK_BIT;
1500 ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT;
1501 ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT;
1503 if (ntb->conn_type != NTB_CONN_B2B) {
1504 device_printf(ntb->device, "Connection type %d not supported\n",
1509 ntb->reg = &xeon_reg;
1510 ntb->self_reg = &xeon_pri_reg;
1511 ntb->peer_reg = &xeon_b2b_reg;
1512 ntb->xlat_reg = &xeon_sec_xlat;
1514 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) {
1515 ntb->msix_mw_idx = (ntb->mw_count + g_ntb_msix_idx) %
1517 ntb_printf(2, "Setting up MSIX mw idx %d means %u\n",
1518 g_ntb_msix_idx, ntb->msix_mw_idx);
1519 rc = ntb_mw_set_wc_internal(ntb, ntb->msix_mw_idx,
1520 VM_MEMATTR_UNCACHEABLE);
1521 KASSERT(rc == 0, ("shouldn't fail"));
1522 } else if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) {
1524 * There is a Xeon hardware errata related to writes to SDOORBELL or
1525 * B2BDOORBELL in conjunction with inbound access to NTB MMIO space,
1526 * which may hang the system. To workaround this, use a memory
1527 * window to access the interrupt and scratch pad registers on the
1530 ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) %
1532 ntb_printf(2, "Setting up b2b mw idx %d means %u\n",
1533 g_ntb_mw_idx, ntb->b2b_mw_idx);
1534 rc = ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx,
1535 VM_MEMATTR_UNCACHEABLE);
1536 KASSERT(rc == 0, ("shouldn't fail"));
1537 } else if (HAS_FEATURE(NTB_B2BDOORBELL_BIT14))
1539 * HW Errata on bit 14 of b2bdoorbell register. Writes will not be
1540 * mirrored to the remote system. Shrink the number of bits by one,
1541 * since bit 14 is the last bit.
1543 * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register
1544 * anyway. Nor for non-B2B connection types.
1546 ntb->db_count = XEON_DB_COUNT - 1;
1548 ntb->db_valid_mask = (1ull << ntb->db_count) - 1;
1550 if (ntb->dev_type == NTB_DEV_USD)
1551 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr,
1552 &xeon_b2b_usd_addr);
1554 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr,
1555 &xeon_b2b_dsd_addr);
1559 /* Enable Bus Master and Memory Space on the secondary side */
1560 ntb_reg_write(2, XEON_SPCICMD_OFFSET,
1561 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
1564 * Mask all doorbell interrupts.
1567 ntb->db_mask = ntb->db_valid_mask;
1568 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
1569 DB_MASK_UNLOCK(ntb);
1571 rc = xeon_setup_msix_bar(ntb);
1575 rc = ntb_init_isr(ntb);
1580 ntb_atom_init_dev(struct ntb_softc *ntb)
1584 KASSERT(ntb->conn_type == NTB_CONN_B2B,
1585 ("Unsupported NTB configuration (%d)\n", ntb->conn_type));
1587 ntb->spad_count = ATOM_SPAD_COUNT;
1588 ntb->db_count = ATOM_DB_COUNT;
1589 ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT;
1590 ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT;
1591 ntb->db_valid_mask = (1ull << ntb->db_count) - 1;
1593 ntb->reg = &atom_reg;
1594 ntb->self_reg = &atom_pri_reg;
1595 ntb->peer_reg = &atom_b2b_reg;
1596 ntb->xlat_reg = &atom_sec_xlat;
1599 * FIXME - MSI-X bug on early Atom HW, remove once internal issue is
1600 * resolved. Mask transaction layer internal parity errors.
1602 pci_write_config(ntb->device, 0xFC, 0x4, 4);
1604 configure_atom_secondary_side_bars(ntb);
1606 /* Enable Bus Master and Memory Space on the secondary side */
1607 ntb_reg_write(2, ATOM_SPCICMD_OFFSET,
1608 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
1610 error = ntb_init_isr(ntb);
1614 /* Initiate PCI-E link training */
1615 ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO);
1617 callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb);
1622 /* XXX: Linux driver doesn't seem to do any of this for Atom. */
1624 configure_atom_secondary_side_bars(struct ntb_softc *ntb)
1627 if (ntb->dev_type == NTB_DEV_USD) {
1628 ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET,
1629 XEON_B2B_BAR2_ADDR64);
1630 ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET,
1631 XEON_B2B_BAR4_ADDR64);
1632 ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64);
1633 ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64);
1635 ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET,
1636 XEON_B2B_BAR2_ADDR64);
1637 ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET,
1638 XEON_B2B_BAR4_ADDR64);
1639 ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64);
1640 ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64);
1646 * When working around Xeon SDOORBELL errata by remapping remote registers in a
1647 * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW
1648 * remains for use by a higher layer.
1650 * Will only be used if working around SDOORBELL errata and the BIOS-configured
1651 * MW size is sufficiently large.
1653 static unsigned int ntb_b2b_mw_share;
1654 TUNABLE_INT("hw.ntb.b2b_mw_share", &ntb_b2b_mw_share);
1655 SYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share,
1656 0, "If enabled (non-zero), prefer to share half of the B2B peer register "
1657 "MW with higher level consumers. Both sides of the NTB MUST set the same "
1661 xeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx,
1662 enum ntb_bar regbar)
1664 struct ntb_pci_bar_info *bar;
1667 if (!HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3)
1670 bar = &ntb->bar_info[idx];
1671 bar_sz = pci_read_config(ntb->device, bar->psz_off, 1);
1672 if (idx == regbar) {
1673 if (ntb->b2b_off != 0)
1677 } else if (HAS_FEATURE(NTB_SB01BASE_LOCKUP) &&
1678 ntb_mw_to_bar(ntb, ntb->msix_mw_idx) == idx) {
1679 /* Restrict LAPIC BAR to 1MB */
1680 pci_write_config(ntb->device, bar->psz_off, 20, 1);
1681 pci_write_config(ntb->device, bar->ssz_off, 20, 1);
1682 bar_sz = pci_read_config(ntb->device, bar->psz_off, 1);
1683 bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1);
1687 pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1);
1688 bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1);
1693 xeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr,
1694 enum ntb_bar idx, enum ntb_bar regbar)
1696 uint64_t reg_val, lmt_addr;
1697 uint32_t base_reg, lmt_reg;
1699 bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg);
1701 bar_addr += ntb->b2b_off;
1702 lmt_addr = bar_addr;
1704 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP) &&
1705 ntb_mw_to_bar(ntb, ntb->msix_mw_idx) == idx)
1709 * Set limit registers first to avoid an errata where setting the base
1710 * registers locks the limit registers.
1712 if (!bar_is_64bit(ntb, idx)) {
1713 ntb_reg_write(4, lmt_reg, lmt_addr);
1714 reg_val = ntb_reg_read(4, lmt_reg);
1717 ntb_reg_write(4, base_reg, bar_addr);
1718 reg_val = ntb_reg_read(4, base_reg);
1721 ntb_reg_write(8, lmt_reg, lmt_addr);
1722 reg_val = ntb_reg_read(8, lmt_reg);
1725 ntb_reg_write(8, base_reg, bar_addr);
1726 reg_val = ntb_reg_read(8, base_reg);
1732 xeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx)
1734 struct ntb_pci_bar_info *bar;
1736 bar = &ntb->bar_info[idx];
1737 if (HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) {
1738 ntb_reg_write(4, bar->pbarxlat_off, base_addr);
1739 base_addr = ntb_reg_read(4, bar->pbarxlat_off);
1741 ntb_reg_write(8, bar->pbarxlat_off, base_addr);
1742 base_addr = ntb_reg_read(8, bar->pbarxlat_off);
1748 xeon_setup_msix_bar(struct ntb_softc *ntb)
1750 struct ntb_pci_bar_info *lapic_bar;
1751 enum ntb_bar bar_num;
1754 if (!HAS_FEATURE(NTB_SB01BASE_LOCKUP))
1757 bar_num = ntb_mw_to_bar(ntb, ntb->msix_mw_idx);
1758 lapic_bar = &ntb->bar_info[bar_num];
1760 /* Restrict LAPIC BAR to 1MB */
1761 if (lapic_bar->size > ONE_MB) {
1762 rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY,
1763 lapic_bar->pci_resource, lapic_bar->pbase,
1764 lapic_bar->pbase + ONE_MB - 1);
1766 lapic_bar->size = ONE_MB;
1768 ntb_printf(0, "Failed to shrink LAPIC BAR resource to "
1774 ntb->peer_lapic_bar = lapic_bar;
1779 xeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr,
1780 const struct ntb_b2b_addr *peer_addr)
1782 struct ntb_pci_bar_info *b2b_bar;
1785 enum ntb_bar b2b_bar_num, i;
1787 if (ntb->b2b_mw_idx == B2B_MW_DISABLED) {
1789 b2b_bar_num = NTB_CONFIG_BAR;
1792 b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx);
1793 KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS,
1794 ("invalid b2b mw bar"));
1796 b2b_bar = &ntb->bar_info[b2b_bar_num];
1797 bar_size = b2b_bar->size;
1799 if (ntb_b2b_mw_share != 0 &&
1800 (bar_size >> 1) >= XEON_B2B_MIN_SIZE)
1801 ntb->b2b_off = bar_size >> 1;
1802 else if (bar_size >= XEON_B2B_MIN_SIZE) {
1805 device_printf(ntb->device,
1806 "B2B bar size is too small!\n");
1812 * Reset the secondary bar sizes to match the primary bar sizes.
1813 * (Except, disable or halve the size of the B2B secondary bar.)
1815 for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++)
1816 xeon_reset_sbar_size(ntb, i, b2b_bar_num);
1819 if (b2b_bar_num == NTB_CONFIG_BAR)
1820 bar_addr = addr->bar0_addr;
1821 else if (b2b_bar_num == NTB_B2B_BAR_1)
1822 bar_addr = addr->bar2_addr64;
1823 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR))
1824 bar_addr = addr->bar4_addr64;
1825 else if (b2b_bar_num == NTB_B2B_BAR_2)
1826 bar_addr = addr->bar4_addr32;
1827 else if (b2b_bar_num == NTB_B2B_BAR_3)
1828 bar_addr = addr->bar5_addr32;
1830 KASSERT(false, ("invalid bar"));
1832 ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr);
1835 * Other SBARs are normally hit by the PBAR xlat, except for the b2b
1836 * register BAR. The B2B BAR is either disabled above or configured
1837 * half-size. It starts at PBAR xlat + offset.
1839 * Also set up incoming BAR limits == base (zero length window).
1841 xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1,
1843 if (HAS_FEATURE(NTB_SPLIT_BAR)) {
1844 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32,
1845 NTB_B2B_BAR_2, b2b_bar_num);
1846 xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32,
1847 NTB_B2B_BAR_3, b2b_bar_num);
1849 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64,
1850 NTB_B2B_BAR_2, b2b_bar_num);
1852 /* Zero incoming translation addrs */
1853 ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0);
1854 ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0);
1856 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) {
1857 size_t size, xlatoffset;
1859 switch (ntb_mw_to_bar(ntb, ntb->msix_mw_idx)) {
1862 xlatoffset = XEON_SBAR2XLAT_OFFSET;
1865 xlatoffset = XEON_SBAR4XLAT_OFFSET;
1866 if (HAS_FEATURE(NTB_SPLIT_BAR))
1872 xlatoffset = XEON_SBAR5XLAT_OFFSET;
1876 KASSERT(false, ("Bogus msix mw idx: %u",
1882 * We point the chosen MSIX MW BAR xlat to remote LAPIC for
1886 ntb_reg_write(4, xlatoffset, MSI_INTEL_ADDR_BASE);
1888 ntb_reg_write(8, xlatoffset, MSI_INTEL_ADDR_BASE);
1890 (void)ntb_reg_read(8, XEON_SBAR2XLAT_OFFSET);
1891 (void)ntb_reg_read(8, XEON_SBAR4XLAT_OFFSET);
1893 /* Zero outgoing translation limits (whole bar size windows) */
1894 ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0);
1895 ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0);
1897 /* Set outgoing translation offsets */
1898 xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1);
1899 if (HAS_FEATURE(NTB_SPLIT_BAR)) {
1900 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2);
1901 xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3);
1903 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2);
1905 /* Set the translation offset for B2B registers */
1907 if (b2b_bar_num == NTB_CONFIG_BAR)
1908 bar_addr = peer_addr->bar0_addr;
1909 else if (b2b_bar_num == NTB_B2B_BAR_1)
1910 bar_addr = peer_addr->bar2_addr64;
1911 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR))
1912 bar_addr = peer_addr->bar4_addr64;
1913 else if (b2b_bar_num == NTB_B2B_BAR_2)
1914 bar_addr = peer_addr->bar4_addr32;
1915 else if (b2b_bar_num == NTB_B2B_BAR_3)
1916 bar_addr = peer_addr->bar5_addr32;
1918 KASSERT(false, ("invalid bar"));
1921 * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits
1924 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff);
1925 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32);
1930 _xeon_link_is_up(struct ntb_softc *ntb)
1933 if (ntb->conn_type == NTB_CONN_TRANSPARENT)
1935 return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0);
1939 link_is_up(struct ntb_softc *ntb)
1942 if (ntb->type == NTB_XEON)
1943 return (_xeon_link_is_up(ntb) && (ntb->peer_msix_good ||
1944 !HAS_FEATURE(NTB_SB01BASE_LOCKUP)));
1946 KASSERT(ntb->type == NTB_ATOM, ("ntb type"));
1947 return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0);
1951 atom_link_is_err(struct ntb_softc *ntb)
1955 KASSERT(ntb->type == NTB_ATOM, ("ntb type"));
1957 status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET);
1958 if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0)
1961 status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET);
1962 return ((status & ATOM_IBIST_ERR_OFLOW) != 0);
1965 /* Atom does not have link status interrupt, poll on that platform */
1967 atom_link_hb(void *arg)
1969 struct ntb_softc *ntb = arg;
1970 sbintime_t timo, poll_ts;
1972 timo = NTB_HB_TIMEOUT * hz;
1973 poll_ts = ntb->last_ts + timo;
1976 * Delay polling the link status if an interrupt was received, unless
1977 * the cached link status says the link is down.
1979 if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) {
1980 timo = poll_ts - ticks;
1984 if (ntb_poll_link(ntb))
1985 ntb_link_event(ntb);
1987 if (!link_is_up(ntb) && atom_link_is_err(ntb)) {
1988 /* Link is down with error, proceed with recovery */
1989 callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb);
1994 callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb);
1998 atom_perform_link_restart(struct ntb_softc *ntb)
2002 /* Driver resets the NTB ModPhy lanes - magic! */
2003 ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0);
2004 ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40);
2005 ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60);
2006 ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60);
2008 /* Driver waits 100ms to allow the NTB ModPhy to settle */
2009 pause("ModPhy", hz / 10);
2011 /* Clear AER Errors, write to clear */
2012 status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET);
2013 status &= PCIM_AER_COR_REPLAY_ROLLOVER;
2014 ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status);
2016 /* Clear unexpected electrical idle event in LTSSM, write to clear */
2017 status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET);
2018 status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
2019 ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status);
2021 /* Clear DeSkew Buffer error, write to clear */
2022 status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET);
2023 status |= ATOM_DESKEWSTS_DBERR;
2024 ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status);
2026 status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET);
2027 status &= ATOM_IBIST_ERR_OFLOW;
2028 ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status);
2030 /* Releases the NTB state machine to allow the link to retrain */
2031 status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET);
2032 status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
2033 ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status);
2037 * ntb_set_ctx() - associate a driver context with an ntb device
2038 * @ntb: NTB device context
2039 * @ctx: Driver context
2040 * @ctx_ops: Driver context operations
2042 * Associate a driver context and operations with a ntb device. The context is
2043 * provided by the client driver, and the driver may associate a different
2044 * context with each ntb device.
2046 * Return: Zero if the context is associated, otherwise an error number.
2049 ntb_set_ctx(struct ntb_softc *ntb, void *ctx, const struct ntb_ctx_ops *ops)
2052 if (ctx == NULL || ops == NULL)
2054 if (ntb->ctx_ops != NULL)
2058 if (ntb->ctx_ops != NULL) {
2070 * It is expected that this will only be used from contexts where the ctx_lock
2071 * is not needed to protect ntb_ctx lifetime.
2074 ntb_get_ctx(struct ntb_softc *ntb, const struct ntb_ctx_ops **ops)
2077 KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus"));
2079 *ops = ntb->ctx_ops;
2080 return (ntb->ntb_ctx);
2084 * ntb_clear_ctx() - disassociate any driver context from an ntb device
2085 * @ntb: NTB device context
2087 * Clear any association that may exist between a driver context and the ntb
2091 ntb_clear_ctx(struct ntb_softc *ntb)
2095 ntb->ntb_ctx = NULL;
2096 ntb->ctx_ops = NULL;
2101 * ntb_link_event() - notify driver context of a change in link status
2102 * @ntb: NTB device context
2104 * Notify the driver context that the link status may have changed. The driver
2105 * should call ntb_link_is_up() to get the current status.
2108 ntb_link_event(struct ntb_softc *ntb)
2112 if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL)
2113 ntb->ctx_ops->link_event(ntb->ntb_ctx);
2118 * ntb_db_event() - notify driver context of a doorbell event
2119 * @ntb: NTB device context
2120 * @vector: Interrupt vector number
2122 * Notify the driver context of a doorbell event. If hardware supports
2123 * multiple interrupt vectors for doorbells, the vector number indicates which
2124 * vector received the interrupt. The vector number is relative to the first
2125 * vector used for doorbells, starting at zero, and must be less than
2126 * ntb_db_vector_count(). The driver may call ntb_db_read() to check which
2127 * doorbell bits need service, and ntb_db_vector_mask() to determine which of
2128 * those bits are associated with the vector number.
2131 ntb_db_event(struct ntb_softc *ntb, uint32_t vec)
2135 if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL)
2136 ntb->ctx_ops->db_event(ntb->ntb_ctx, vec);
2141 * ntb_link_enable() - enable the link on the secondary side of the ntb
2142 * @ntb: NTB device context
2143 * @max_speed: The maximum link speed expressed as PCIe generation number[0]
2144 * @max_width: The maximum link width expressed as the number of PCIe lanes[0]
2146 * Enable the link on the secondary side of the ntb. This can only be done
2147 * from the primary side of the ntb in primary or b2b topology. The ntb device
2148 * should train the link to its maximum speed and width, or the requested speed
2149 * and width, whichever is smaller, if supported.
2151 * Return: Zero on success, otherwise an error number.
2153 * [0]: Only NTB_SPEED_AUTO and NTB_WIDTH_AUTO are valid inputs; other speed
2154 * and width input will be ignored.
2157 ntb_link_enable(struct ntb_softc *ntb, enum ntb_speed s __unused,
2158 enum ntb_width w __unused)
2162 ntb_printf(2, "%s\n", __func__);
2164 if (ntb->type == NTB_ATOM) {
2165 pci_write_config(ntb->device, NTB_PPD_OFFSET,
2166 ntb->ppd | ATOM_PPD_INIT_LINK, 4);
2170 if (ntb->conn_type == NTB_CONN_TRANSPARENT) {
2171 ntb_link_event(ntb);
2175 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
2176 cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK);
2177 cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP;
2178 cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP;
2179 if (HAS_FEATURE(NTB_SPLIT_BAR))
2180 cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP;
2181 ntb_reg_write(4, ntb->reg->ntb_ctl, cntl);
2186 * ntb_link_disable() - disable the link on the secondary side of the ntb
2187 * @ntb: NTB device context
2189 * Disable the link on the secondary side of the ntb. This can only be done
2190 * from the primary side of the ntb in primary or b2b topology. The ntb device
2191 * should disable the link. Returning from this call must indicate that a
2192 * barrier has passed, though with no more writes may pass in either direction
2193 * across the link, except if this call returns an error number.
2195 * Return: Zero on success, otherwise an error number.
2198 ntb_link_disable(struct ntb_softc *ntb)
2202 ntb_printf(2, "%s\n", __func__);
2204 if (ntb->conn_type == NTB_CONN_TRANSPARENT) {
2205 ntb_link_event(ntb);
2209 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
2210 cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP);
2211 cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP);
2212 if (HAS_FEATURE(NTB_SPLIT_BAR))
2213 cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP);
2214 cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK;
2215 ntb_reg_write(4, ntb->reg->ntb_ctl, cntl);
2220 ntb_link_enabled(struct ntb_softc *ntb)
2224 if (ntb->type == NTB_ATOM) {
2225 cntl = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4);
2226 return ((cntl & ATOM_PPD_INIT_LINK) != 0);
2229 if (ntb->conn_type == NTB_CONN_TRANSPARENT)
2232 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
2233 return ((cntl & NTB_CNTL_LINK_DISABLE) == 0);
2237 recover_atom_link(void *arg)
2239 struct ntb_softc *ntb = arg;
2240 unsigned speed, width, oldspeed, oldwidth;
2243 atom_perform_link_restart(ntb);
2246 * There is a potential race between the 2 NTB devices recovering at
2247 * the same time. If the times are the same, the link will not recover
2248 * and the driver will be stuck in this loop forever. Add a random
2249 * interval to the recovery time to prevent this race.
2251 status32 = arc4random() % ATOM_LINK_RECOVERY_TIME;
2252 pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000);
2254 if (atom_link_is_err(ntb))
2257 status32 = ntb_reg_read(4, ntb->reg->ntb_ctl);
2258 if ((status32 & ATOM_CNTL_LINK_DOWN) != 0)
2261 status32 = ntb_reg_read(4, ntb->reg->lnk_sta);
2262 width = NTB_LNK_STA_WIDTH(status32);
2263 speed = status32 & NTB_LINK_SPEED_MASK;
2265 oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta);
2266 oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK;
2267 if (oldwidth != width || oldspeed != speed)
2271 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb,
2276 callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link,
2281 * Polls the HW link status register(s); returns true if something has changed.
2284 ntb_poll_link(struct ntb_softc *ntb)
2289 if (ntb->type == NTB_ATOM) {
2290 ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl);
2291 if (ntb_cntl == ntb->ntb_ctl)
2294 ntb->ntb_ctl = ntb_cntl;
2295 ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta);
2297 db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask);
2299 reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2);
2300 if (reg_val == ntb->lnk_sta)
2303 ntb->lnk_sta = reg_val;
2305 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) {
2306 if (_xeon_link_is_up(ntb)) {
2307 if (!ntb->peer_msix_good) {
2308 callout_reset(&ntb->peer_msix_work, 0,
2309 ntb_exchange_msix, ntb);
2313 ntb->peer_msix_good = false;
2314 ntb->peer_msix_done = false;
2321 static inline enum ntb_speed
2322 ntb_link_sta_speed(struct ntb_softc *ntb)
2325 if (!link_is_up(ntb))
2326 return (NTB_SPEED_NONE);
2327 return (ntb->lnk_sta & NTB_LINK_SPEED_MASK);
2330 static inline enum ntb_width
2331 ntb_link_sta_width(struct ntb_softc *ntb)
2334 if (!link_is_up(ntb))
2335 return (NTB_WIDTH_NONE);
2336 return (NTB_LNK_STA_WIDTH(ntb->lnk_sta));
2339 SYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0,
2340 "Driver state, statistics, and HW registers");
2342 #define NTB_REGSZ_MASK (3ul << 30)
2343 #define NTB_REG_64 (1ul << 30)
2344 #define NTB_REG_32 (2ul << 30)
2345 #define NTB_REG_16 (3ul << 30)
2346 #define NTB_REG_8 (0ul << 30)
2348 #define NTB_DB_READ (1ul << 29)
2349 #define NTB_PCI_REG (1ul << 28)
2350 #define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG)
2353 ntb_sysctl_init(struct ntb_softc *ntb)
2355 struct sysctl_oid_list *globals, *tree_par, *regpar, *statpar, *errpar;
2356 struct sysctl_ctx_list *ctx;
2357 struct sysctl_oid *tree, *tmptree;
2359 ctx = device_get_sysctl_ctx(ntb->device);
2360 globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device));
2362 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "link_status",
2363 CTLFLAG_RD | CTLTYPE_STRING, ntb, 0,
2364 sysctl_handle_link_status_human, "A",
2365 "Link status (human readable)");
2366 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "active",
2367 CTLFLAG_RD | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_status,
2368 "IU", "Link status (1=active, 0=inactive)");
2369 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "admin_up",
2370 CTLFLAG_RW | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_admin,
2371 "IU", "Set/get interface status (1=UP, 0=DOWN)");
2373 tree = SYSCTL_ADD_NODE(ctx, globals, OID_AUTO, "debug_info",
2374 CTLFLAG_RD, NULL, "Driver state, statistics, and HW registers");
2375 tree_par = SYSCTL_CHILDREN(tree);
2377 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD,
2378 &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port");
2379 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD,
2380 &ntb->dev_type, 0, "0 - USD; 1 - DSD");
2381 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD,
2382 &ntb->ppd, 0, "Raw PPD register (cached)");
2384 if (ntb->b2b_mw_idx != B2B_MW_DISABLED) {
2386 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD,
2387 &ntb->b2b_mw_idx, 0,
2388 "Index of the MW used for B2B remote register access");
2390 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off",
2391 CTLFLAG_RD, &ntb->b2b_off,
2392 "If non-zero, offset of B2B register region in shared MW");
2395 SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features",
2396 CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A",
2397 "Features/errata of this NTB device");
2399 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD,
2400 __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0,
2401 "NTB CTL register (cached)");
2402 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD,
2403 __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0,
2404 "LNK STA register (cached)");
2407 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD,
2408 &ntb->mw_count, 0, "MW count");
2409 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD,
2410 &ntb->spad_count, 0, "Scratchpad count");
2411 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD,
2412 &ntb->db_count, 0, "Doorbell count");
2413 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD,
2414 &ntb->db_vec_count, 0, "Doorbell vector count");
2415 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD,
2416 &ntb->db_vec_shift, 0, "Doorbell vector shift");
2419 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD,
2420 &ntb->db_valid_mask, "Doorbell valid mask");
2421 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD,
2422 &ntb->db_link_mask, "Doorbell link mask");
2423 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD,
2424 &ntb->db_mask, "Doorbell mask (cached)");
2426 tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers",
2427 CTLFLAG_RD, NULL, "Raw HW registers (big-endian)");
2428 regpar = SYSCTL_CHILDREN(tmptree);
2430 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl",
2431 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 |
2432 ntb->reg->ntb_ctl, sysctl_handle_register, "IU",
2433 "NTB Control register");
2434 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap",
2435 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 |
2436 0x19c, sysctl_handle_register, "IU",
2437 "NTB Link Capabilities");
2438 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon",
2439 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 |
2440 0x1a0, sysctl_handle_register, "IU",
2441 "NTB Link Control register");
2443 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask",
2444 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2445 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask,
2446 sysctl_handle_register, "QU", "Doorbell mask register");
2447 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell",
2448 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2449 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell,
2450 sysctl_handle_register, "QU", "Doorbell register");
2452 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23",
2453 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2454 NTB_REG_64 | ntb->xlat_reg->bar2_xlat,
2455 sysctl_handle_register, "QU", "Incoming XLAT23 register");
2456 if (HAS_FEATURE(NTB_SPLIT_BAR)) {
2457 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4",
2458 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2459 NTB_REG_32 | ntb->xlat_reg->bar4_xlat,
2460 sysctl_handle_register, "IU", "Incoming XLAT4 register");
2461 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5",
2462 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2463 NTB_REG_32 | ntb->xlat_reg->bar5_xlat,
2464 sysctl_handle_register, "IU", "Incoming XLAT5 register");
2466 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45",
2467 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2468 NTB_REG_64 | ntb->xlat_reg->bar4_xlat,
2469 sysctl_handle_register, "QU", "Incoming XLAT45 register");
2472 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23",
2473 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2474 NTB_REG_64 | ntb->xlat_reg->bar2_limit,
2475 sysctl_handle_register, "QU", "Incoming LMT23 register");
2476 if (HAS_FEATURE(NTB_SPLIT_BAR)) {
2477 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4",
2478 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2479 NTB_REG_32 | ntb->xlat_reg->bar4_limit,
2480 sysctl_handle_register, "IU", "Incoming LMT4 register");
2481 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5",
2482 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2483 NTB_REG_32 | ntb->xlat_reg->bar5_limit,
2484 sysctl_handle_register, "IU", "Incoming LMT5 register");
2486 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45",
2487 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2488 NTB_REG_64 | ntb->xlat_reg->bar4_limit,
2489 sysctl_handle_register, "QU", "Incoming LMT45 register");
2492 if (ntb->type == NTB_ATOM)
2495 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats",
2496 CTLFLAG_RD, NULL, "Xeon HW statistics");
2497 statpar = SYSCTL_CHILDREN(tmptree);
2498 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss",
2499 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2500 NTB_REG_16 | XEON_USMEMMISS_OFFSET,
2501 sysctl_handle_register, "SU", "Upstream Memory Miss");
2503 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err",
2504 CTLFLAG_RD, NULL, "Xeon HW errors");
2505 errpar = SYSCTL_CHILDREN(tmptree);
2507 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd",
2508 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2509 NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET,
2510 sysctl_handle_register, "CU", "PPD");
2512 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz",
2513 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2514 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET,
2515 sysctl_handle_register, "CU", "PBAR23 SZ (log2)");
2516 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz",
2517 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2518 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET,
2519 sysctl_handle_register, "CU", "PBAR4 SZ (log2)");
2520 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz",
2521 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2522 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET,
2523 sysctl_handle_register, "CU", "PBAR5 SZ (log2)");
2525 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz",
2526 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2527 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET,
2528 sysctl_handle_register, "CU", "SBAR23 SZ (log2)");
2529 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz",
2530 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2531 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET,
2532 sysctl_handle_register, "CU", "SBAR4 SZ (log2)");
2533 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz",
2534 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2535 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET,
2536 sysctl_handle_register, "CU", "SBAR5 SZ (log2)");
2538 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts",
2539 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2540 NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET,
2541 sysctl_handle_register, "SU", "DEVSTS");
2542 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts",
2543 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2544 NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET,
2545 sysctl_handle_register, "SU", "LNKSTS");
2546 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts",
2547 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2548 NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET,
2549 sysctl_handle_register, "SU", "SLNKSTS");
2551 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts",
2552 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2553 NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET,
2554 sysctl_handle_register, "IU", "UNCERRSTS");
2555 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts",
2556 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2557 NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET,
2558 sysctl_handle_register, "IU", "CORERRSTS");
2560 if (ntb->conn_type != NTB_CONN_B2B)
2563 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23",
2564 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2565 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off,
2566 sysctl_handle_register, "QU", "Outgoing XLAT23 register");
2567 if (HAS_FEATURE(NTB_SPLIT_BAR)) {
2568 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4",
2569 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2570 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off,
2571 sysctl_handle_register, "IU", "Outgoing XLAT4 register");
2572 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5",
2573 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2574 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off,
2575 sysctl_handle_register, "IU", "Outgoing XLAT5 register");
2577 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45",
2578 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2579 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off,
2580 sysctl_handle_register, "QU", "Outgoing XLAT45 register");
2583 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23",
2584 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2585 NTB_REG_64 | XEON_PBAR2LMT_OFFSET,
2586 sysctl_handle_register, "QU", "Outgoing LMT23 register");
2587 if (HAS_FEATURE(NTB_SPLIT_BAR)) {
2588 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4",
2589 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2590 NTB_REG_32 | XEON_PBAR4LMT_OFFSET,
2591 sysctl_handle_register, "IU", "Outgoing LMT4 register");
2592 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5",
2593 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2594 NTB_REG_32 | XEON_PBAR5LMT_OFFSET,
2595 sysctl_handle_register, "IU", "Outgoing LMT5 register");
2597 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45",
2598 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2599 NTB_REG_64 | XEON_PBAR4LMT_OFFSET,
2600 sysctl_handle_register, "QU", "Outgoing LMT45 register");
2603 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base",
2604 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2605 NTB_REG_64 | ntb->xlat_reg->bar0_base,
2606 sysctl_handle_register, "QU", "Secondary BAR01 base register");
2607 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base",
2608 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2609 NTB_REG_64 | ntb->xlat_reg->bar2_base,
2610 sysctl_handle_register, "QU", "Secondary BAR23 base register");
2611 if (HAS_FEATURE(NTB_SPLIT_BAR)) {
2612 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base",
2613 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2614 NTB_REG_32 | ntb->xlat_reg->bar4_base,
2615 sysctl_handle_register, "IU",
2616 "Secondary BAR4 base register");
2617 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base",
2618 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2619 NTB_REG_32 | ntb->xlat_reg->bar5_base,
2620 sysctl_handle_register, "IU",
2621 "Secondary BAR5 base register");
2623 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base",
2624 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb,
2625 NTB_REG_64 | ntb->xlat_reg->bar4_base,
2626 sysctl_handle_register, "QU",
2627 "Secondary BAR45 base register");
2632 sysctl_handle_features(SYSCTL_HANDLER_ARGS)
2634 struct ntb_softc *ntb;
2641 sbuf_new_for_sysctl(&sb, NULL, 256, req);
2643 sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR);
2644 error = sbuf_finish(&sb);
2647 if (error || !req->newptr)
2653 sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS)
2655 struct ntb_softc *ntb;
2662 old = ntb_link_enabled(ntb);
2664 error = SYSCTL_OUT(req, &old, sizeof(old));
2665 if (error != 0 || req->newptr == NULL)
2668 error = SYSCTL_IN(req, &new, sizeof(new));
2672 ntb_printf(0, "Admin set interface state to '%sabled'\n",
2673 (new != 0)? "en" : "dis");
2676 error = ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO);
2678 error = ntb_link_disable(ntb);
2683 sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS)
2685 struct ntb_softc *ntb;
2687 enum ntb_speed speed;
2688 enum ntb_width width;
2694 sbuf_new_for_sysctl(&sb, NULL, 32, req);
2696 if (ntb_link_is_up(ntb, &speed, &width))
2697 sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u",
2698 (unsigned)speed, (unsigned)width);
2700 sbuf_printf(&sb, "down");
2702 error = sbuf_finish(&sb);
2705 if (error || !req->newptr)
2711 sysctl_handle_link_status(SYSCTL_HANDLER_ARGS)
2713 struct ntb_softc *ntb;
2720 res = ntb_link_is_up(ntb, NULL, NULL);
2722 error = SYSCTL_OUT(req, &res, sizeof(res));
2723 if (error || !req->newptr)
2729 sysctl_handle_register(SYSCTL_HANDLER_ARGS)
2731 struct ntb_softc *ntb;
2735 char be[sizeof(umv)];
2742 reg = arg2 & ~NTB_REGFLAGS_MASK;
2743 sz = arg2 & NTB_REGSZ_MASK;
2744 db = (arg2 & NTB_DB_READ) != 0;
2745 pci = (arg2 & NTB_PCI_REG) != 0;
2747 KASSERT(!(db && pci), ("bogus"));
2750 KASSERT(sz == NTB_REG_64, ("bogus"));
2751 umv = db_ioread(ntb, reg);
2752 outsz = sizeof(uint64_t);
2757 umv = pci_read_config(ntb->device, reg, 8);
2759 umv = ntb_reg_read(8, reg);
2760 outsz = sizeof(uint64_t);
2764 umv = pci_read_config(ntb->device, reg, 4);
2766 umv = ntb_reg_read(4, reg);
2767 outsz = sizeof(uint32_t);
2771 umv = pci_read_config(ntb->device, reg, 2);
2773 umv = ntb_reg_read(2, reg);
2774 outsz = sizeof(uint16_t);
2778 umv = pci_read_config(ntb->device, reg, 1);
2780 umv = ntb_reg_read(1, reg);
2781 outsz = sizeof(uint8_t);
2789 /* Encode bigendian so that sysctl -x is legible. */
2791 outp = ((char *)be) + sizeof(umv) - outsz;
2793 error = SYSCTL_OUT(req, outp, outsz);
2794 if (error || !req->newptr)
2800 ntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx)
2803 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 &&
2804 uidx >= ntb->b2b_mw_idx) ||
2805 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx))
2807 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 &&
2808 uidx >= ntb->b2b_mw_idx) &&
2809 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx))
2815 ntb_exchange_msix(void *ctx)
2817 struct ntb_softc *ntb;
2823 if (ntb->peer_msix_good)
2825 if (ntb->peer_msix_done)
2828 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
2829 ntb_peer_spad_write(ntb, NTB_MSIX_DATA0 + i,
2830 ntb->msix_data[i].nmd_data);
2831 ntb_peer_spad_write(ntb, NTB_MSIX_OFS0 + i,
2832 ntb->msix_data[i].nmd_ofs);
2834 ntb_peer_spad_write(ntb, NTB_MSIX_GUARD, NTB_MSIX_VER_GUARD);
2836 ntb_spad_read(ntb, NTB_MSIX_GUARD, &val);
2837 if (val != NTB_MSIX_VER_GUARD)
2840 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
2841 ntb_spad_read(ntb, NTB_MSIX_DATA0 + i, &val);
2842 ntb->peer_msix_data[i].nmd_data = val;
2843 ntb_spad_read(ntb, NTB_MSIX_OFS0 + i, &val);
2844 ntb->peer_msix_data[i].nmd_ofs = val;
2847 ntb->peer_msix_done = true;
2850 ntb_peer_spad_write(ntb, NTB_MSIX_DONE, NTB_MSIX_RECEIVED);
2851 ntb_spad_read(ntb, NTB_MSIX_DONE, &val);
2852 if (val != NTB_MSIX_RECEIVED)
2855 ntb->peer_msix_good = true;
2856 /* Give peer time to see our NTB_MSIX_RECEIVED. */
2861 ntb_link_event(ntb);
2865 ntb->lnk_sta = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2);
2866 if (_xeon_link_is_up(ntb)) {
2867 callout_reset(&ntb->peer_msix_work,
2868 hz * (ntb->peer_msix_good ? 2 : 1) / 100,
2869 ntb_exchange_msix, ntb);
2871 ntb_spad_clear(ntb);
2875 * Public API to the rest of the OS
2879 * ntb_get_max_spads() - get the total scratch regs usable
2880 * @ntb: pointer to ntb_softc instance
2882 * This function returns the max 32bit scratchpad registers usable by the
2885 * RETURNS: total number of scratch pad registers available
2888 ntb_get_max_spads(struct ntb_softc *ntb)
2891 return (ntb->spad_count);
2895 * ntb_mw_count() - Get the number of memory windows available for KPI
2898 * (Excludes any MW wholly reserved for register access.)
2901 ntb_mw_count(struct ntb_softc *ntb)
2905 res = ntb->mw_count;
2906 if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0)
2908 if (ntb->msix_mw_idx != B2B_MW_DISABLED)
2914 * ntb_spad_write() - write to the secondary scratchpad register
2915 * @ntb: pointer to ntb_softc instance
2916 * @idx: index to the scratchpad register, 0 based
2917 * @val: the data value to put into the register
2919 * This function allows writing of a 32bit value to the indexed scratchpad
2920 * register. The register resides on the secondary (external) side.
2922 * RETURNS: An appropriate ERRNO error value on error, or zero for success.
2925 ntb_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val)
2928 if (idx >= ntb->spad_count)
2931 ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val);
2937 * Zeros the local scratchpad.
2940 ntb_spad_clear(struct ntb_softc *ntb)
2944 for (i = 0; i < ntb->spad_count; i++)
2945 ntb_spad_write(ntb, i, 0);
2949 * ntb_spad_read() - read from the primary scratchpad register
2950 * @ntb: pointer to ntb_softc instance
2951 * @idx: index to scratchpad register, 0 based
2952 * @val: pointer to 32bit integer for storing the register value
2954 * This function allows reading of the 32bit scratchpad register on
2955 * the primary (internal) side.
2957 * RETURNS: An appropriate ERRNO error value on error, or zero for success.
2960 ntb_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val)
2963 if (idx >= ntb->spad_count)
2966 *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4);
2972 * ntb_peer_spad_write() - write to the secondary scratchpad register
2973 * @ntb: pointer to ntb_softc instance
2974 * @idx: index to the scratchpad register, 0 based
2975 * @val: the data value to put into the register
2977 * This function allows writing of a 32bit value to the indexed scratchpad
2978 * register. The register resides on the secondary (external) side.
2980 * RETURNS: An appropriate ERRNO error value on error, or zero for success.
2983 ntb_peer_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val)
2986 if (idx >= ntb->spad_count)
2989 if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP))
2990 ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val);
2992 ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val);
2998 * ntb_peer_spad_read() - read from the primary scratchpad register
2999 * @ntb: pointer to ntb_softc instance
3000 * @idx: index to scratchpad register, 0 based
3001 * @val: pointer to 32bit integer for storing the register value
3003 * This function allows reading of the 32bit scratchpad register on
3004 * the primary (internal) side.
3006 * RETURNS: An appropriate ERRNO error value on error, or zero for success.
3009 ntb_peer_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val)
3012 if (idx >= ntb->spad_count)
3015 if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP))
3016 *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4);
3018 *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4);
3024 * ntb_mw_get_range() - get the range of a memory window
3025 * @ntb: NTB device context
3026 * @idx: Memory window number
3027 * @base: OUT - the base address for mapping the memory window
3028 * @size: OUT - the size for mapping the memory window
3029 * @align: OUT - the base alignment for translating the memory window
3030 * @align_size: OUT - the size alignment for translating the memory window
3032 * Get the range of a memory window. NULL may be given for any output
3033 * parameter if the value is not needed. The base and size may be used for
3034 * mapping the memory window, to access the peer memory. The alignment and
3035 * size may be used for translating the memory window, for the peer to access
3036 * memory on the local system.
3038 * Return: Zero on success, otherwise an error number.
3041 ntb_mw_get_range(struct ntb_softc *ntb, unsigned mw_idx, vm_paddr_t *base,
3042 caddr_t *vbase, size_t *size, size_t *align, size_t *align_size,
3045 struct ntb_pci_bar_info *bar;
3048 enum ntb_bar bar_num;
3050 if (mw_idx >= ntb_mw_count(ntb))
3052 mw_idx = ntb_user_mw_to_idx(ntb, mw_idx);
3054 bar_num = ntb_mw_to_bar(ntb, mw_idx);
3055 bar = &ntb->bar_info[bar_num];
3057 if (mw_idx == ntb->b2b_mw_idx) {
3058 KASSERT(ntb->b2b_off != 0,
3059 ("user shouldn't get non-shared b2b mw"));
3060 bar_b2b_off = ntb->b2b_off;
3063 if (bar_is_64bit(ntb, bar_num))
3064 limit = BUS_SPACE_MAXADDR;
3066 limit = BUS_SPACE_MAXADDR_32BIT;
3069 *base = bar->pbase + bar_b2b_off;
3071 *vbase = bar->vbase + bar_b2b_off;
3073 *size = bar->size - bar_b2b_off;
3076 if (align_size != NULL)
3084 * ntb_mw_set_trans() - set the translation of a memory window
3085 * @ntb: NTB device context
3086 * @idx: Memory window number
3087 * @addr: The dma address local memory to expose to the peer
3088 * @size: The size of the local memory to expose to the peer
3090 * Set the translation of a memory window. The peer may access local memory
3091 * through the window starting at the address, up to the size. The address
3092 * must be aligned to the alignment specified by ntb_mw_get_range(). The size
3093 * must be aligned to the size alignment specified by ntb_mw_get_range(). The
3094 * address must be below the plimit specified by ntb_mw_get_range() (i.e. for
3097 * Return: Zero on success, otherwise an error number.
3100 ntb_mw_set_trans(struct ntb_softc *ntb, unsigned idx, bus_addr_t addr,
3103 struct ntb_pci_bar_info *bar;
3104 uint64_t base, limit, reg_val;
3105 size_t bar_size, mw_size;
3106 uint32_t base_reg, xlat_reg, limit_reg;
3107 enum ntb_bar bar_num;
3109 if (idx >= ntb_mw_count(ntb))
3111 idx = ntb_user_mw_to_idx(ntb, idx);
3113 bar_num = ntb_mw_to_bar(ntb, idx);
3114 bar = &ntb->bar_info[bar_num];
3116 bar_size = bar->size;
3117 if (idx == ntb->b2b_mw_idx)
3118 mw_size = bar_size - ntb->b2b_off;
3122 /* Hardware requires that addr is aligned to bar size */
3123 if ((addr & (bar_size - 1)) != 0)
3129 bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg);
3132 if (bar_is_64bit(ntb, bar_num)) {
3133 base = ntb_reg_read(8, base_reg) & BAR_HIGH_MASK;
3135 if (limit_reg != 0 && size != mw_size)
3136 limit = base + size;
3138 /* Set and verify translation address */
3139 ntb_reg_write(8, xlat_reg, addr);
3140 reg_val = ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK;
3141 if (reg_val != addr) {
3142 ntb_reg_write(8, xlat_reg, 0);
3146 /* Set and verify the limit */
3147 ntb_reg_write(8, limit_reg, limit);
3148 reg_val = ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK;
3149 if (reg_val != limit) {
3150 ntb_reg_write(8, limit_reg, base);
3151 ntb_reg_write(8, xlat_reg, 0);
3155 /* Configure 32-bit (split) BAR MW */
3157 if ((addr & UINT32_MAX) != addr)
3159 if (((addr + size) & UINT32_MAX) != (addr + size))
3162 base = ntb_reg_read(4, base_reg) & BAR_HIGH_MASK;
3164 if (limit_reg != 0 && size != mw_size)
3165 limit = base + size;
3167 /* Set and verify translation address */
3168 ntb_reg_write(4, xlat_reg, addr);
3169 reg_val = ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK;
3170 if (reg_val != addr) {
3171 ntb_reg_write(4, xlat_reg, 0);
3175 /* Set and verify the limit */
3176 ntb_reg_write(4, limit_reg, limit);
3177 reg_val = ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK;
3178 if (reg_val != limit) {
3179 ntb_reg_write(4, limit_reg, base);
3180 ntb_reg_write(4, xlat_reg, 0);
3188 * ntb_mw_clear_trans() - clear the translation of a memory window
3189 * @ntb: NTB device context
3190 * @idx: Memory window number
3192 * Clear the translation of a memory window. The peer may no longer access
3193 * local memory through the window.
3195 * Return: Zero on success, otherwise an error number.
3198 ntb_mw_clear_trans(struct ntb_softc *ntb, unsigned mw_idx)
3201 return (ntb_mw_set_trans(ntb, mw_idx, 0, 0));
3205 * ntb_mw_get_wc - Get the write-combine status of a memory window
3207 * Returns: Zero on success, setting *wc; otherwise an error number (e.g. if
3208 * idx is an invalid memory window).
3210 * Mode is a VM_MEMATTR_* type.
3213 ntb_mw_get_wc(struct ntb_softc *ntb, unsigned idx, vm_memattr_t *mode)
3215 struct ntb_pci_bar_info *bar;
3217 if (idx >= ntb_mw_count(ntb))
3219 idx = ntb_user_mw_to_idx(ntb, idx);
3221 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)];
3222 *mode = bar->map_mode;
3227 * ntb_mw_set_wc - Set the write-combine status of a memory window
3229 * If 'mode' matches the current status, this does nothing and succeeds. Mode
3230 * is a VM_MEMATTR_* type.
3232 * Returns: Zero on success, setting the caching attribute on the virtual
3233 * mapping of the BAR; otherwise an error number (e.g. if idx is an invalid
3234 * memory window, or if changing the caching attribute fails).
3237 ntb_mw_set_wc(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode)
3240 if (idx >= ntb_mw_count(ntb))
3243 idx = ntb_user_mw_to_idx(ntb, idx);
3244 return (ntb_mw_set_wc_internal(ntb, idx, mode));
3248 ntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode)
3250 struct ntb_pci_bar_info *bar;
3253 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)];
3254 if (bar->map_mode == mode)
3257 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode);
3259 bar->map_mode = mode;
3265 * ntb_peer_db_set() - Set the doorbell on the secondary/external side
3266 * @ntb: pointer to ntb_softc instance
3267 * @bit: doorbell bits to ring
3269 * This function allows triggering of a doorbell on the secondary/external
3270 * side that will initiate an interrupt on the remote host
3273 ntb_peer_db_set(struct ntb_softc *ntb, uint64_t bit)
3276 if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) {
3277 struct ntb_pci_bar_info *lapic;
3280 lapic = ntb->peer_lapic_bar;
3282 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) {
3283 if ((bit & ntb_db_vector_mask(ntb, i)) != 0)
3284 bus_space_write_4(lapic->pci_bus_tag,
3285 lapic->pci_bus_handle,
3286 ntb->peer_msix_data[i].nmd_ofs,
3287 ntb->peer_msix_data[i].nmd_data);
3292 if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) {
3293 ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit);
3297 db_iowrite(ntb, ntb->peer_reg->db_bell, bit);
3301 * ntb_get_peer_db_addr() - Return the address of the remote doorbell register,
3302 * as well as the size of the register (via *sz_out).
3304 * This function allows a caller using I/OAT DMA to chain the remote doorbell
3305 * ring to its memory window write.
3307 * Note that writing the peer doorbell via a memory window will *not* generate
3308 * an interrupt on the remote host; that must be done seperately.
3311 ntb_get_peer_db_addr(struct ntb_softc *ntb, vm_size_t *sz_out)
3313 struct ntb_pci_bar_info *bar;
3316 KASSERT(sz_out != NULL, ("must be non-NULL"));
3318 if (!HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) {
3319 bar = &ntb->bar_info[NTB_CONFIG_BAR];
3320 regoff = ntb->peer_reg->db_bell;
3322 KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED,
3323 ("invalid b2b idx"));
3325 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)];
3326 regoff = XEON_PDOORBELL_OFFSET;
3328 KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh"));
3330 *sz_out = ntb->reg->db_size;
3331 /* HACK: Specific to current x86 bus implementation. */
3332 return ((uint64_t)bar->pci_bus_handle + regoff);
3336 * ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb
3337 * @ntb: NTB device context
3339 * Hardware may support different number or arrangement of doorbell bits.
3341 * Return: A mask of doorbell bits supported by the ntb.
3344 ntb_db_valid_mask(struct ntb_softc *ntb)
3347 return (ntb->db_valid_mask);
3351 * ntb_db_vector_mask() - get a mask of doorbell bits serviced by a vector
3352 * @ntb: NTB device context
3353 * @vector: Doorbell vector number
3355 * Each interrupt vector may have a different number or arrangement of bits.
3357 * Return: A mask of doorbell bits serviced by a vector.
3360 ntb_db_vector_mask(struct ntb_softc *ntb, uint32_t vector)
3363 if (vector > ntb->db_vec_count)
3365 return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector));
3369 * ntb_link_is_up() - get the current ntb link state
3370 * @ntb: NTB device context
3371 * @speed: OUT - The link speed expressed as PCIe generation number
3372 * @width: OUT - The link width expressed as the number of PCIe lanes
3374 * RETURNS: true or false based on the hardware link state
3377 ntb_link_is_up(struct ntb_softc *ntb, enum ntb_speed *speed,
3378 enum ntb_width *width)
3382 *speed = ntb_link_sta_speed(ntb);
3384 *width = ntb_link_sta_width(ntb);
3385 return (link_is_up(ntb));
3389 save_bar_parameters(struct ntb_pci_bar_info *bar)
3392 bar->pci_bus_tag = rman_get_bustag(bar->pci_resource);
3393 bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource);
3394 bar->pbase = rman_get_start(bar->pci_resource);
3395 bar->size = rman_get_size(bar->pci_resource);
3396 bar->vbase = rman_get_virtual(bar->pci_resource);
3400 ntb_get_device(struct ntb_softc *ntb)
3403 return (ntb->device);
3406 /* Export HW-specific errata information. */
3408 ntb_has_feature(struct ntb_softc *ntb, uint32_t feature)
3411 return (HAS_FEATURE(feature));